TC74VHC161,163F/FT/FK
2012-02-29
1
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74VHC161F,TC74VHC161FT,TC74VHC161FK
TC74VHC163F,TC74VHC163FT,TC74VHC163FK
Synchronous Presettable 4-Bit Counter
TC74VHC161F/FT/FK Binary, Asynchronous
Clear
TC74VHC163F/FT/FK Binary, Synchronous
Clear
The TC74VHC 161 and 163 are advanced high speed CMOS
SYNCHRONOUS PRESETTABLE 4 BIT BINARY COUNTERs
fabricated with silicon gate C2MOS technology.
They achieve the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
The CK input is active on the rising edge. Both LOAD and
CLR inputs are active on low logic level.
Presetting of each IC’s is synchronous to the rising edge of CK.
The clear function of the TC74VHC163 is synchronous to CK,
while the TC74VHC161 are cleared asynchronously.
Two enable inputs (ENP and ENT) and CARRY OUTPUT are
provided to enable easy cascading of counters, which facilitates
easy implementation of n-bit counters without using external
gates.
An input protection circuit ensures that 0 to 5.5 V can be
applied to the input pins without regard to the supply voltage.
This device can be used to interface 5 V to 3 V systems and two
supply systems such as battery back up. This circuit prevents
device destruction due to mismatched supply and input voltages.
Features
• High speed: fmax = 185 MHz (typ.) at VCC = 5 V
• Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
• High noise immunity: VNIH = VNIL = 28% VCC (min)
• Power down protection is provided on all inputs.
• Balanced propagation delays: tpLH ∼
−
tpHL
• Wide operating voltage range: VCC (opr) = 2 to 5.5 V
• Low noise: VOLP = 0.8 V (max)
• Pin and function compatible with 74ALS161/163
TC74VHC161F, TC74VHC163F
TC74VHC161FT, TC74VHC163FT
TC74VHC161FK, TC74VHC163FK
Weight
SOP16-P-300-1.27A : 0.18 g (typ.)
TSSOP16-P-0044-0.65A : 0.06 g (typ.)
VSSOP16-P-0030-0.50 : 0.02 g (typ.)
TC74VHC161,163F/FT/FK
2012-02-29
2
Pin Assignment
IEC Logic Symbol
Truth Table (Note)
TC74VHC161 TC74VHC163
Inputs Inputs
Outputs
CLR LD ENP ENT CK CLR LD ENP ENT CK QA QB QC QD
Function
L X X X X L X X X L L L L Reset to “0”
H L X X H L X X A B C D Preset Data
H H X L H H X L No Change No Count
H H L X H H L X No Change No Count
H H H H H H H H Count Up Count
H X X X X X X X No Change No Count
Note: X: Don’t care
A, B, C, D: Logic level of data inputs
Carry: CARRY = ENT･QA･QB･QC･QD
VCC 16
CARRY OUTPUT
QA
QB
15
14
13
12
11
10
CLR 1
2
3
4
5
6
7
B
C
D
ENP
GND
QC
8 LOAD
9
QD
ENT
(top view)
CK
A
(9)
(1)
(10)
(2)
(7)
ENP
1, 5D [1]
CK
(3)
(4)
B
A
(15)
(14)
QB
(13)
QA
QC
CT = 0
M1
LOAD
CLR
C(5)
(6)
D
(12)
QD
(11)
CARRY OUTPUT
ENT
TC74VHC161
CTRDIV 16
M2
G3
G4
C5/2, 3, 4+
3CT = 15
[2]
[4]
[8]
(9)
(1)
(10)
(2)
(7)
ENP
1, 5D [1]
CK
(3)
(4)
B
A
(15)
(14)
QB
(13)
QA
QC
5CT = 0
M1
LOAD
CLR
C(5)
(6)
D
(12)
QD
(11)
CARRY OUTPUT
ENT
TC74VHC163
CTRDIV 16
M2
G3
G4
C5/2, 3, 4+
3CT = 15
[2]
[4]
[8]
TC74VHC161,163F/FT/FK
2012-02-29
3
Timing Chart
COUNT INHIBIT
12
ASYNC
CLEAR
(161)
SYNC
CLEAR
(163)
PRESET
13 14 15 0 1 2
CARRY
QD
QC
QB
QA
ENT
ENP
CK
D
C
B
A
LOAD
CLR
Data
Inputs
Outputs
DON’T CARE UNTIL LOAD GOES LOW
TC74VHC161,163F/FT/FK
2012-02-29
4
System Diagram
Note: Truth table of internal F/F
TC74VHC161 TC74VHC163
D CK R Q Q D CK R Q Q
X X H L H X H L H
L L L H L L L H
H L H L H L H L
X L No Change X X No Change
X: Don’t care
CLR
ENP
1
7
ENT
LOAD
10
9
E
E
E
L
15 CARRY
OUT
14 QA
E
E
L
(Note)
L
A
3
RQD
Q
CK
13 QB
EL
L
B 4
RQD
Q
CK
E
12 QC
EL
L
C 5
RQD
Q
CK
E
11 QD
E
L
D
RQD
Q
CK
6
CK 2
L
L
(Note)
(Note)
(Note)
TC74VHC161,163F/FT/FK
2012-02-29
5
Absolute Maximum Ratings (Note)
Characteristics Symbol Rating Unit
Supply voltage range VCC −0.5 to 7.0 V
DC input voltage VIN −0.5 to 7.0 V
DC output voltage VOUT −0.5 to VCC + 0.5 V
Input diode current IIK −20 mA
Output diode current IOK ±20 mA
DC output current IOUT ±25 mA
DC VCC/ground current ICC ±50 mA
Power dissipation PD 180 mW
Storage temperature Tstg −65 to 150 °C
Note: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
even destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly
even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute
maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/“Derating Concept and Methods”) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Operating Range (Note)
Characteristics Symbol Rating Unit
Supply voltage VCC 2.0 to 5.5 V
Input voltage VIN 0 to 5.5 V
Output voltage VOUT 0 to VCC V
Operating temperature Topr −40 to 85 °C
Input rise and fall time dt/dv 0 to 100 (VCC = 3.3 ± 0.3 V)
0 to 20 (VCC = 5 ± 0.5 V) ns/V
Note: The operating ranges must be maintained to ensure the normal operation of the device.
Unused inputs must be tied to either VCC or GND.
TC74VHC161,163F/FT/FK
2012-02-29
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Electrical Characteristics
DC Characteristics
Test Condition Ta = 25°C Ta =
−40 to 85°C
Characteristics Symbol
VCC
(V) Min Typ. Max Min Max
Unit
High-level input
voltage VIH ―
2.0
3.0
to
5.5
1.50
VCC ×
0.7
―
―
―
―
1.50
VCC ×
0.7
―
― V
Low-level input
voltage VIL ―
2.0
3.0
to
5.5
―
―
―
―
0.50
VCC ×
0.3
―
―
0.50
VCC ×
0.3
V
IOH = −50 μA
2.0
3.0
4.5
1.9
2.9
4.4
2.0
3.0
4.5
―
―
―
1.9
2.9
4.4
―
―
―
High-level output
voltage VOH
VIN
= VIH or
VIL IOH = −4 mA
IOH = −8 mA
3.0
4.5
2.58
3.94
―
―
―
―
2.48
3.80
―
―
V
IOL = 50 μA
2.0
3.0
4.5
―
―
―
0.0
0.0
0.0
0.1
0.1
0.1
―
―
―
0.1
0.1
0.1
Low-level output
voltage VOL
VIN
= VIH or
VIL IOL = 4 mA
IOL = 8 mA
3.0
4.5
―
―
―
―
0.36
0.36
―
―
0.44
0.44
V
Input leakage
current IIN VIN = 5.5 or GND 0 to
5.5 ― ― ±0.1 ― ±1.0 μA
Quiescent supply
current ICC VIN = VCC or GND 5.5 ― ― 4.0 ― 40.0 μA
TC74VHC161,163F/FT/FK
2012-02-29
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Timing Requirements (input: tr = tf = 3 ns)
Test Condition Ta =
25°C
Ta =
−40 to
85°C
Characteristics Symbol
VCC (V) Limit Limit
Unit
Minimum pulse width
(CK)
tw (L)
tw (H)
Figure 1 3.3 ± 0.3
5.0 ± 0.5
5.0
5.0
5.0
5.0 ns
Minimum pulse width
(CLR ) (Note1)
tw (L) Figure 4 3.3 ± 0.3
5.0 ± 0.5
5.0
5.0
5.0
5.0 ns
Minimum set-up time
(A, B, C, D) ts Figure 2 3.3 ± 0.3
5.0 ± 0.5
5.5
4.5
6.5
4.5 ns
Minimum set-up time
(LOAD ) ts Figure 2 3.3 ± 0.3
5.0 ± 0.5
8.0
5.0
9.5
6.0 ns
Minimum set-up time
(ENT, ENP) ts Figure 3 3.3 ± 0.3
5.0 ± 0.5
7.5
5.0
9.0
6.0 ns
Minimum set-up time
(CLR ) (Note 2)
ts Figure 5 3.3 ± 0.3
5.0 ± 0.5
4.0
3.5
4.0
3.5 ns
Minimum hold time th Figure 2, Figure 3 3.3 ± 0.3
5.0 ± 0.5
1.0
1.0
1.0
1.0 ns
Minimum hold time
(CLR ) (Note 2)
th Figure 5 3.3 ± 0.3
5.0 ± 0.5
1.0
1.5
1.0
1.5 ns
Minimum removal time
(CLR ) (Note 1)
trem Figure 4 3.3 ± 0.3
5.0 ± 0.5
2.5
1.5
2.5
1.5 ns
Note 1: For TC74VHC161 only
Note 2: For TC74VHC163 only
TC74VHC161,163F/FT/FK
2012-02-29
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AC Characteristics (input: tr = tf = 3 ns)
Test Condition Ta = 25°C Ta =
−40 to 85°C
Characteristics Symbol
VCC (V) CL (pF) Min Typ. Max Min Max
Unit
15 ― 8.3 12.8 1.0 15.0
3.3 ± 0.3
50 ― 10.8 16.3 1.0 18.5
15 ― 4.9 8.1 1.0 9.5
Propagation delay
time
(CK-Q)
tpLH
tpHL
Figure 1,
Figure 2
5.0 ± 0.5
50 ― 6.4 10.1 1.0 11.5
ns
15 ― 8.7 13.6 1.0 16.0
3.3 ± 0.3
50 ― 11.2 17.1 1.0 19.5
15 ― 4.9 8.1 1.0 9.5
Propagation delay
time
(CK-CARRY,
count-mode)
tpLH
tpHL
Figure 1
5.0 ± 0.5
50 ― 6.4 10.1 1.0 11.5
ns
15 ― 11.0 17.2 1.0 20.0
3.3 ± 0.3
50 ― 13.5 20.7 1.0 23.5
15 ― 6.2 10.3 1.0 12.0
Propagation delay
time
(CK-CARRY,
preset-mode)
tpLH
tpHL
Figure 2
5.0 ± 0.5
50 ― 7.7 12.3 1.0 14.0
ns
15 ― 7.5 12.3 1.0 14.5
3.3 ± 0.3
50 ― 10.5 15.8 1.0 18.0
15 ― 4.9 8.1 1.0 9.5
Propagation delay
time
(ENT-CARRY)
tpLH
tpHL
Figure 6
5.0 ± 0.5
50 ― 6.4 10.1 1.0 11.5
ns
15 ― 8.9 13.6 1.0 16.0
3.3 ± 0.3
50 ― 11.2 17.1 1.0 19.5
15 ― 5.5 9.0 1.0 10.5
Propagation delay
time
(CLR -Q) (Note 2)
tpHL Figure 4
5.0 ± 0.5
50 ― 7.0 11.0 1.0 12.5
ns
15 ― 8.4 13.2 1.0 15.5
3.3 ± 0.3
50 ― 10.9 16.7 1.0 19.0
15 ― 5.0 8.6 1.0 10.0
Propagation delay
time
(CLR -CARRY)
(Note 2)
tpHL Figure 4
5.0 ± 0.5
50 ― 6.5 10.6 1.0 12.0
ns
15 80 130 ― 70 ―
3.3 ± 0.3
50 55 85 ― 50 ―
15 135 185 ― 115 ―
Maximum clock
frequency fmax ―
5.0 ± 0.5
50 95 125 ― 85 ―
MHz
Input capacitance CIN ― ― 4 10 ― 10 pF
Power dissipation
capacitance CPD (Note 1) ― 23 ― ― ― pF
Note 1: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
ICC (opr) = CPD･VCC･fIN + ICC
When the outputs drive a capacitive load, total current consumption is the sum of CPD, and ΔICC which is
obtained from the following formula:
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛++++⋅ 16
C
16
C
8
C
4
C
2
C
Vf = ΔICO
QDQCQBQA
CCCKCC
C
QA to CQD and CCO are the capacitances at QA to QD and CARRY OUT, respectively.
f
CK is the input frequency of the CK.
Note 2: For TC74VHC161 only
TC74VHC161,163F/FT/FK
2012-02-29
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Switching Characteristics Test Waveform
Figure 1 Count Mode Figure 4 Clear Mode (TC74VHC161)
CK 50％
twH t
wL
VCC
GND
50％
VOH
VOL
tpHL
50％
50％
tpLH
Q,
CARRY
CLR 50％
twL
VCC
GND
VOH
VOL
trem
50％
50％
tpHL
CK
Q,
CARRY
VCC
GND
Figure 2 Preset Mode Figure 5 Clear Mode (TC74VHC163)
LOAD 50％
ts
VCC
GND
th
50％
ts th
50％
ts th
50％
A
to D
tpLH, tpHL
50％
VCC
GND
CK
VOH
VOL
Q,
CARRY 50％
CLR 50％
VCC
GND
VOH
VOL
50％CK
Q,
CARRY
VCC
GND
50％
tsth
ENP
ENT 50％
ts
VCC
GND
th
50％
ts th
CK
Q
VOH
VOL
VCC
GND
50％50％
VOH
VOL
ENT
VCC
GND
50％ 50％
CARRY 50％ 50％
tpLH tpHL
Figure 3 Count Enable Mode Figure 6 Cascade Mode
(fix maximum count)
TC74VHC161,163F/FT/FK
2012-02-29
10
Noise Characteristics (input: tr = tf = 3 ns)
Test Condition Ta = 25°C
Characteristics Symbol
VCC (V) Typ. Max
Unit
Quiet output maximum dynamic VOL V
OLP CL = 50 pF 5.0 0.4 0.8 V
Quiet output minimum dynamic VOL V
OLV CL = 50 pF 5.0 −0.4 −0.8 V
Minimum high level dynamic input voltage VIHD CL = 50 pF 5.0 ― 3.5 V
Maximum low level dynamic input voltage VILD CL = 50 pF 5.0 ― 1.5 V
Input Equivalent Circuit
Typical Application
Parallel Carry N-Bit Counter
INPUT
LD A
CLR QA
BC
QB QC
D
QD
INPUTS
OUTPUTS
CARRY
ENP
ENT
CK
LD A
CLR QA
BC
QB QC
D
QD
INPUTS
OUTPUTS
CARRY
ENP
ENT
CK
LD A
CLR QA
BC
QB QC
D
QD
INPUTS
OUTPUTS
CARRY
ENP
ENT
CK
NEXT
STAGE
H: COUNT
L: DISABLE
H: COUNT
L: DISABLE
CK
CLR
TC74VHC161,163F/FT/FK
2012-02-29
11
Package Dimensions
Weight: 0.18 g (typ.)
TC74VHC161,163F/FT/FK
2012-02-29
12
Package Dimensions
Weight: 0.06 g (typ.)
TC74VHC161,163F/FT/FK
2012-02-29
13
Package Dimensions
Weight: 0.02 g (typ.)
TC74VHC161,163F/FT/FK
2012-02-29
14
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• Toshiba Corporation, and its subsidiaries and affiliates (collectively "TOSHIBA"), reserve the right to make changes to the information
in this document, and related hardware, software and systems (collectively "Product") without notice.
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responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and
systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily
injury or damage to property, including data loss or corruption. Before customers use the Product, create designs including the
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all relevant TOSHIBA information, including without limitation, this document, the specifications, the data sheets and application notes
for Product and the precautions and conditions set forth in the "TOSHIBA Semiconductor Reliability Handbook" and (b) the
instructions for the application with which the Product will be used with or for. Customers are solely responsible for all aspects of their
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