Octal LNA/VGA/AAF/ADC
and Crosspoint Switch
AD9272
Rev. C
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FEATURES
8 channels of LNA, VGA, AAF, and ADC
Low noise preamplifier (LNA)
Input-referred noise voltage = 0.75 nV/√Hz
(gain = 21.3 dB) @ 5 MHz typical
SPI-programmable gain = 15.6 dB/17.9 dB/21.3 dB
Single-ended input; VIN maximum = 733 mV p-p/
550 mV p-p/367 mV p-p
Dual-mode active input impedance matching
Bandwidth (BW) > 100 MHz
Full-scale (FS) output = 4.4 V p-p differential
Variable gain amplifier (VGA)
Attenuator range = −42 dB to 0 dB
SPI-programmable PGA gain = 21 dB/24 dB/27 dB/30 dB
Linear-in-dB gain control
Antialiasing filter (AAF)
Programmable 2nd-order low-pass filter (LPF) from
8 MHz to 18 MHz
Programmable high-pass filter (HPF)
Analog-to-digital converter (ADC)
12 bits at 10 MSPS to 80 MSPS
SNR = 70 dB
SFDR = 75 dB
Serial LVDS (ANSI-644, IEEE 1596.3 reduced range link)
Data and frame clock outputs
Includes an 8 × 8 differential crosspoint switch to support
continuous wave (CW) Doppler
Low power, 195 mW per channel at 12 bits/40 MSPS (TGC)
120 mW per channel in CW Doppler
Flexible power-down modes
Overload recovery in <10 ns
Fast recovery from low power standby mode, <2 μs
100-lead TQFP
APPLICATIONS
Medical imaging/ultrasound
Automotive radar
GENERAL DESCRIPTION
The AD9272 is designed for low cost, low power, small size, and
ease of use. It contains eight channels of a low noise preamplifier
(LNA) with a variable gain amplifier (VGA), an antialiasing
filter (AAF), and a 12-bit, 10 MSPS to 80 MSPS analog-to-
digital converter (ADC).
Each channel features a variable gain range of 42 dB, a fully
differential signal path, an active input preamplifier termination, a
maximum gain of up to 52 dB, and an ADC with a conversion
rate of up to 80 MSPS. The channel is optimized for dynamic
performance and low power in applications where a small
package size is critical.
FUNCTIONAL BLOCK DIAGRAM
07029-001
SERIAL
PORT
INTERFACE
REFERENCE
FCO+
FCO–
DCO+
DCO–
LNA
LO-H
LOSW-H
LI-H
LG-H
12-BIT
ADC SERIAL
LVDS
DOUTH+
DOUTH–
LNA
LO-G
LOSW-G
LI-G
LG-G
12-BIT
ADC SERIAL
LVDS
DOUTG+
DOUTG–
LNA
LO-F
LOSW-F
LI-F
LG-F
12-BIT
ADC SERIAL
LVDS
DOUTF+
DOUTF–
LNA
LO-E
LOSW-E
LI-E
LG-E
12-BIT
ADC SERIAL
LVDS
DOUTE+
DOUTE–
LNA
LO-D
LOSW-D
LI-D
LG-D
12-BIT
ADC SERIAL
LVDS
DOUTD+
DOUTD–
LNA
LO-C
LOSW-C
LI-C
LG-C
12-BIT
ADC SERIAL
LVDS
DOUTC+
DOUTC–
LNA
LO-B
LOSW-B
LI-B
LG-B
12-BIT
ADC SERIAL
LVDS
DOUTB+
DOUTB–
LNA
LO-A
LOSW-A
LI-A
LG-A
12-BIT
ADC SERIAL
LVDS
DOUTA+
DOUTA–
AVDD1
AVDD2
STBY
DRVDD
PDWN
CLK–
CLK+
SDIO
SCLK
CSB
RBIAS
VREF
GAIN+
GAIN–
CWD[7:0]+
AND
CWD[7:0]–
SWITCH
ARRAY
DATA
RATE
MULTIPLIER
AAF
AAF
AAF
AAF
AAF
AAF
AAF
AAF
AD9272
VGA
VGA
VGA
VGA
VGA
VGA
VGA
VGA
Figure 1.
The LNA has a single-ended-to-differential gain that is selectable
through the SPI. The LNA input-referred noise voltage is typically
0.75 nV/√Hz at a gain of 21.3 dB, and the combined input-referred
noise voltage of the entire channel is 0.85 nV/√Hz at maximum
gain. Assuming a 15 MHz noise bandwidth (NBW) and a 21.3 dB
LNA gain, the input SNR is about 92 dB. In CW Doppler mode,
the LNA output drives a transconductance amp that is switched
through an 8 × 8 differential crosspoint switch. The switch is
programmable through the SPI.
AD9272
Rev. C | Page 2 of 44
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Product Highlights ........................................................................... 3
Specifications ..................................................................................... 4
AC Specifications .......................................................................... 4
Digital Specifications ................................................................... 8
Switching Specifications .............................................................. 9
Absolute Maximum Ratings .......................................................... 11
Thermal Impedance ................................................................... 11
ESD Caution ................................................................................ 11
Pin Configuration and Function Descriptions ........................... 12
Typical Performance Characteristics ........................................... 15
Equivalent Circuits ......................................................................... 19
Theory of Operation ...................................................................... 21
Ultrasound .................................................................................. 21
Channel Overview ..................................................................... 22
Input Overdrive .......................................................................... 25
CW Doppler Operation ............................................................. 25
TGC Operation ........................................................................... 27
ADC ............................................................................................. 31
Clock Input Considerations ...................................................... 31
Serial Port Interface (SPI) .............................................................. 38
Hardware Interface ..................................................................... 38
Memory Map .................................................................................. 40
Reading the Memory Map Table .............................................. 40
Reserved Locations .................................................................... 40
Default Values ............................................................................. 40
Logic Levels ................................................................................. 40
Outline Dimensions ....................................................................... 44
Ordering Guide .......................................................................... 44
REVISION HISTORY
7/09—Rev. B to Rev. C
Changes to Input Overload Protection Section and Figure 43 ....... 25
Changes to Digital Outputs and Timing Section and Changes
to Figure 63 ...................................................................................... 33
Changes to Hardware Interface Section ...................................... 39
6/09—Rev. A to Rev. B
Changes to Product Highlights Section ......................................... 3
Changes to Table 1 ............................................................................ 4
Changes to Absolute Maximum Ratings Table ........................... 11
Changes to Figure 22 ...................................................................... 17
Changes to Figure 33 and Figure 34 ............................................. 20
Changes to Low Noise Amplifier (LNA) Section ....................... 22
Changes to Active Impedance Matching Section ....................... 23
Changes to Figure 39 ...................................................................... 23
Changes to LNA Noise Section ..................................................... 24
Changes to Figure 47 ...................................................................... 28
Changes to Figure 48 and Figure 49 ............................................. 29
Changes to CSB Pin Section .......................................................... 36
Changes to Reading the Memory Map Table Section................ 40
4/09—Revision A: Initial Version
AD9272
Rev. C | Page 3 of 44
The AD9272 requires a LVPECL-/CMOS-/LVDS-compatible
sample rate clock for full performance operation. No external
reference or driver components are required for many
applications.
The ADC automatically multiplies the sample rate clock for
the appropriate LVDS serial data rate. A data clock (DCO±) for
capturing data on the output and a frame clock (FCO±) trigger
for signaling a new output byte are provided.
Powering down individual channels is supported to increase
battery life for portable applications. There is also a standby
mode option that allows quick power-up for power cycling. In
CW Doppler operation, the VGA, antialiasing filter (AAF), and
ADC are powered down. The power of the time gain control
(TGC) path scales with selectable speed grades.
The ADC contains several features designed to maximize flexibility
and minimize system cost, such as a programmable clock, data
alignment, and programmable digital test pattern generation. The
digital test patterns include built-in fixed patterns, built-in
pseudorandom patterns, and custom user-defined test patterns
entered via the serial port interface.
Fabricated in an advanced CMOS process, the AD9272 is
available in a 16 mm × 16 mm, RoHS-compliant, 100-lead
TQFP. It is specified over the industrial temperature range of
−40°C to +85°C.
PRODUCT HIGHLIGHTS
1. Small Footprint. Eight channels are contained in a
small, space-saving package. A full TGC path, ADC, and
crosspoint switch are contained within a 100-lead, 16 mm ×
16 mm TQFP.
2. Low Power of 195 mW Per Channel at 40 MSPS.
3. Integrated Crosspoint Switch. This switch allows numerous
multichannel configuration options to enable the CW
Doppler mode.
4. Ease of Use. A data clock output (DCO±) operates up to
480 MHz and supports double data rate (DDR) operation.
5. User Flexibility. Serial port interface (SPI) control offers a wide
range of flexible features to meet specific system requirements.
6. Integrated Second-Order Antialiasing Filter. This filter is
placed between the VGA and the ADC and is programmable
from 8 MHz to 18 MHz.
AD9272
Rev. C | Page 4 of 44
SPECIFICATIONS
AC SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, fIN = 5 MHz, RS = 50 Ω, LNA gain = 21.3 dB, LNA bias = high,
PGA gain = 27 dB, GAIN− = 0.8 V, AAF LPF cutoff = fSAMPLE/4.5, HPF = LPF cutoff/20.7 (default), full temperature, ANSI-644 LVDS mode,
unless otherwise noted.
Table 1.
AD9272-40 AD9272-65 AD9272-80
Parameter1 Conditions Min Typ Max Min Typ Max Min Typ Max Unit
LNA CHARACTERISTICS
Gain Single-ended
input to
differential output
15.6/17.9/21.3 15.6/17.9/21.3 15.6/17.9/21.3 dB
Single-ended
input to
single-ended
output
9.6/11.9/15.3 9.6/11.9/15.3 9.6/11.9/15.3 dB
Input Voltage Range LNA gain =
15.6 dB/
17.9 dB/
21.3 dB,
LNA output
limited to
4.4 V p-p
differential output
733/550/367 733/550/367 733/550/367 mV p-p
SE2
Input Common
Mode
0.9 0.9 0.9 V
Input Resistance RFB = 250 Ω 50 50 50 Ω
R
FB = 500 Ω 100 100 100 Ω
R
FB = ∞ 15 15 15 kΩ
Input Capacitance LI-x 22 22 22 pF
−3 dB Bandwidth 100 100 100 MHz
Input-Referred
Noise Voltage
LNA gain =
15.6 dB/
17.9 dB/
21.3 dB,
RS = 0 Ω,
RFB = ∞
0.98/0.86/0.75 0.98/0.86/0.75 0.98/0.86/0.75 nV/√Hz
Input Noise Current RFB = ∞ 1 1 1 pA/√Hz
1 dB Input Com-
pression Point
LNA gain =
15.6 dB/
17.9 dB/
21.3 dB,
GAIN+ = 0 V
1.0/0.8/0.5 1.0/0.8/0.5 1.0/0.8/0.5 mV p-p
Noise Figure LNA gain =
15.6 dB/
17.9 dB/
21.3 dB
Active Termination
Matched
RS = 50 Ω,
RFB = 200 Ω/
250 Ω/350 Ω
4.8/4.1/3.2 4.8/4.1/3.2 4.8/4.0/3.2 dB
Unterminated RFB = ∞ 3.4/2.8/2.3 3.4/2.8/2.3 3.4/2.8/2.3 dB
FULL-CHANNEL (TGC)
CHARACTERISTICS
AAF Low-Pass Filter
Cutoff -In Range
−3 dB,
programmable
8 to 18 8 to 18 8 to 18 MHz
AAF Low-Pass Filter
Cutoff - Out of
Range3
−3 dB,
programmable,
AAF Bandwidth
Tolerance
5 to 8 and
18 to 35
5 to 8 and
18 to 35
5 to 8 and
18 to 35
MHz
AAF Bandwidth
Tolerance -In
Range
±10 ±10 ±10 %
AD9272
Rev. C | Page 5 of 44
AD9272-40 AD9272-65 AD9272-80
Parameter1 Conditions Min Typ Max Min Typ Max Min Typ Max Unit
Group Delay
Variation
f = 1 MHz to
18 MHz,
GAIN+ = 0 V to
1.6 V
±2 ±2 ±2 ns
Input-Referred
Noise Voltage
LNA gain =
15.6 dB/
17.9 dB/
21.3 dB,
RFB = ∞
1.26/1.04/0.85 1.26/1.04/0.85 1.26/1.04/0.85 nV/√Hz
Noise Figure LNA gain =
15.6 dB/
17.9 dB/
21.3 dB
Active Termina-
tion Matched
RS = 50 Ω,
RFB = 200 Ω/
250 Ω/350 Ω
8.0/6.6/4.7 7.7/6.2/4.5 7.6/6.1/4.4 dB
Unterminated RFB = ∞ 4.7/3.7/2.8 4.6/3.6/2.8 4.5/3.6/2.7 dB
Correlated Noise
Ratio
No signal,
correlated/
uncorrelated
−30 −30 −30 dB
Output Offset −35 +35 −35 +35 −35 +35 LSB
Signal-to-Noise
Ratio (SNR)
fIN = 5 MHz at
−10 dBFS, GAIN+
= 0 V
65 64 63 dBFS
f
IN = 5 MHz at
−1 dBFS, GAIN+ =
1.6 V
57 56 54.5 dBFS
Harmonic Distortion
Second
Harmonic
fIN = 5 MHz at
−10 dBFS, GAIN+
= 0 V
−62 −58 −55 dBc
f
IN = 5 MHz at
−1 dBFS, GAIN+ =
1.6 V
−60 −61 −58 dBc
Third Harmonic fIN = 5 MHz at
−10 dBFS, GAIN+
= 0 V
−71 −60 −60 dBc
f
IN = 5 MHz at
−1 dBFS, GAIN+ =
1.6 V
−57 −55 −56 dBc
Two-Tone IMD3
(2 × F1 − F2)
Distortion
fIN1 = 5.0 MHz at
−1 dBFS,
fIN2 = 5.01 MHz at
−21 dBFS, GAIN+
= 1.6 V,
LNA gain = 21.3 dB
−75 −75 −75 dBc
Channel-to-Channel
Crosstalk
fIN1 = 5.0 MHz at −1
dBFS
−70 −70 −70 dB
Overrange
condition4
−65 −65 −65 dB
Channel-to-Channel
Delay Variation
Full TGC path,
fIN = 5 MHz,
GAIN+ = 0 V to
1.6 V
0.3 0.3 0.3 Degrees
PGA GAIN Differential input
to differential
output
21/24/27/30 21/24/27/30 21/24/27/30 dB
AD9272
Rev. C | Page 6 of 44
AD9272-40 AD9272-65 AD9272-80
Parameter1 Conditions Min Typ Max Min Typ Max Min Typ Max Unit
GAIN ACCURACY 25°C
Gain Law Confor-
mance Error
0 V < GAIN+ <
0.16 V
1.5 1.5 1.5 dB
0.16 V < GAIN+ <
1.44 V
−1.5 +1.5 −1.5 +1.5 −1.6 +1.6 dB
1.44 V < GAIN+ <
1.6 V
−2.5 −2.5 −2.5 dB
Linear Gain Error GAIN+ = 0.8 V,
normalized for
ideal AAF loss
−1.5 +1.5 −1.5 +1.5 −1.6 +1.6 dB
Channel-to-Channel
Matching
0.16 V < GAIN+ <
1.44 V
0.1 0.1 0.1 dB
GAIN CONTROL
INTERFACE
Normal Operating
Range
0 1.6 0 1.6 0 1.6 V
Gain Range GAIN+ = 0 V to
1.6 V
42 42 42 dB
Scale Factor 28.5 28.5 28.5 dB/V
Response Time 42 dB change 750 750 750 ns
Gain+ Impedance Single-ended 10 10 10 MΩ
Gain− Impedance Single-ended 70 70 70 kΩ
CW DOPPLER MODE
Transconductance
(differential)
LNA gain =
15.6 dB/
17.9 dB/
21.3 dB
5.4/7.3/10.9 5.4/7.3/10.9 5.4/7.3/10.9 mA/V
Output Level Range
(differential)
CW Doppler
output pins
1.5 3.6 1.5 3.6 1.5 3.6 V
Input-Referred
Noise Voltage
LNA gain =
15.6 dB/
17.9 dB/
21.3 dB,
RS = 0 Ω,
RFB = ∞,
RL = 675 Ω
2.35/1.82/1.31 2.35/1.82/1.31 2.35/1.82/1.31 nV/√Hz
Input-Referred
Dynamic Range
LNA gain =
15.6 dB/
17.9 dB/
21.3 dB,
RS = 0 Ω,
RFB = ∞
161/161/160 161/161/160 161/161/160 dBFS/√Hz
Two-Tone IMD3
(2 × F1 − F2)
Distortion
fIN1 = 5.0 MHz at
−1 dBFS (FS at LNA
input),
fIN2 = 5.01 MHz at
−21 dBFS (FS at
LNA input),
LNA gain = 21.3 dB
−70 −70 −70 dBc
Output DC Bias
(single-ended)
Per channel 2.4 2.4 2.4 mA
Maximum Output
Swing (single-
ended)
Per channel ±2 ±2 ±2 mA p-p
POWER SUPPLY
AVDD1 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
AVDD2 2.7 3.0 3.6 2.7 3.0 3.6 2.7 3.0 3.6 V
DRVDD 1.7 1.8 1.9 1.7 1.8 1.9 1.7 1.8 1.9 V
AD9272
Rev. C | Page 7 of 44
AD9272-40 AD9272-65 AD9272-80
Parameter1 Conditions Min Typ Max Min Typ Max Min Typ Max Unit
IAVDD1 Full-channel
mode
210 280 335 mA
CW Doppler mode
with four channels
enabled
32 32 32 mA
IAVDD2 Full-channel mode 365 365 365 mA
CW Doppler mode
with four channels
enabled
140 140 140 mA
IDRVDD 49 51 52 mA
Total Power
Dissipation
Includes output
drivers, full-
channel mode, no
signal
1560 1713 1690 1860 1780 1975 mW
CW Doppler mode
with four channels
enabled
475 475 475 mW
Power-Down
Dissipation
5 5 5 mW
Standby Power
Dissipation
175 200 210 mW
Power Supply
Rejection Ratio
(PSRR)
1.6 1.6 1.6 mV/V
ADC RESOLUTION 12 12 12 Bits
ADC REFERENCE
Output Voltage Error VREF = 1 V ±20 ±20 ±20 mV
Load Regulation At 1.0 mA,
VREF = 1 V
2 2 2 mV
Input Resistance 6 6 6 kΩ
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were
completed.
2 SE = single-ended.
3 AAF settings < 5 MHz are out of range and not supported.
4 The overrange condition is specified as being 6 dB more than the full-scale input range.
AD9272
Rev. C | Page 8 of 44
DIGITAL SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, fIN = 5 MHz, full temperature, unless otherwise noted.
Table 2.
Parameter1 Temperature Min Typ Max Unit
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance CMOS/LVDS/LVPECL
Differential Input Voltage2 Full 250 mV p-p
Input Common-Mode Voltage Full 1.2 V
Input Resistance (Differential) 25°C 20 kΩ
Input Capacitance 25°C 1.5 pF
LOGIC INPUTS (PDWN, STBY, SCLK)
Logic 1 Voltage Full 1.2 3.6 V
Logic 0 Voltage Full 0.3 V
Input Resistance 25°C 30 kΩ
Input Capacitance 25°C 0.5 pF
LOGIC INPUT (CSB)
Logic 1 Voltage Full 1.2 3.6 V
Logic 0 Voltage Full 0.3 V
Input Resistance 25°C 70 kΩ
Input Capacitance 25°C 0.5 pF
LOGIC INPUT (SDIO)
Logic 1 Voltage Full 1.2 DRVDD + 0.3 V
Logic 0 Voltage Full 0 0.3 V
Input Resistance 25°C 30 kΩ
Input Capacitance 25°C 2 pF
LOGIC OUTPUT (SDIO)3
Logic 1 Voltage (IOH = 800 A) Full 1.79 V
Logic 0 Voltage (IOL = 50 A) Full 0.05 V
DIGITAL OUTPUTS (DOUTx+, DOUTx−), IN ANSI-644 MODE1
Logic Compliance LVDS
Differential Output Voltage (VOD) Full 247 454 mV
Output Offset Voltage (VOS) Full 1.125 1.375 V
Output Coding (Default) Offset binary
DIGITAL OUTPUTS (DOUTx+, DOUTx−), WITH
LOW POWER, REDUCED SIGNAL OPTION1
Logic Compliance LVDS
Differential Output Voltage (VOD) Full 150 250 mV
Output Offset Voltage (VOS) Full 1.10 1.30 V
Output Coding (Default) Offset binary
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were
completed.
2 Specified for LVDS and LVPECL only.
3 Specified for 13 SDIO pins sharing the same connection.
AD9272
Rev. C | Page 9 of 44
SWITCHING SPECIFICATIONS
AVDD1 = 1.8 V, AVDD2 = 3.0 V, DRVDD = 1.8 V, 1.0 V internal ADC reference, fIN = 5 MHz, full temperature, unless otherwise noted.
Table 3.
Parameter1 Temp Min Typ Max Unit
CLOCK2
Clock Rate Full 10 80 MSPS
Clock Pulse Width High (tEH) Full 6.25 ns
Clock Pulse Width Low (tEL) Full 6.25 ns
OUTPUT PARAMETERS2, 3
Propagation Delay (tPD) Full (tSAMPLE/2) + 1.5 (tSAMPLE/2) + 2.3 (tSAMPLE/2) + 3.1 ns
Rise Time (tR) (20% to 80%) Full 300 ps
Fall Time (tF) (20% to 80%) Full 300 ps
FCO± Propagation Delay (tFCO) Full (tSAMPLE/2) + 1.5 (tSAMPLE/2) + 2.3 (tSAMPLE/2) + 3.1 ns
DCO± Propagation Delay (tCPD)4 Full tFCO + (tSAMPLE/24) ns
DCO± to Data Delay (tDATA)4 Full (tSAMPLE/24) − 300 (tSAMPLE/24) (tSAMPLE/24) + 300 ps
DCO± to FCO± Delay (tFRAME)4 Full (tSAMPLE/24) − 300 (tSAMPLE/24) (tSAMPLE/24) + 300 ps
Data-to-Data Skew
(tDATA-MAX − tDATA-MIN)
Full ±100 ±350 ps
Wake-Up Time (Standby), GAIN+ = 0.8 V 25°C 2 µs
Wake-Up Time (Power-Down) 25°C 1 ms
Pipeline Latency Full 8 Clock cycles
APERTURE
Aperture Uncertainty (Jitter) 25°C <1 ps rms
1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were
completed.
2 Can be adjusted via the SPI.
3 Measurements were made using a part soldered to FR-4 material.
4 tSAMPLE/24 is based on the number of bits divided by 2 because the delays are based on half duty cycles.
AD9272
Rev. C | Page 10 of 44
ADC Timing Diagrams
DCO–
DCO+
DOUTx–
DOUTx+
FCO–
FCO+
AIN
CLK–
CLK+
MSB
N – 8
D10
N – 8
D9
N – 8
D8
N – 8
D7
N – 8
D6
N – 8
D5
N – 8
D4
N – 8
D3
N – 8
D2
N – 8
D1
N – 8
D0
N – 8
D10
N – 7
MSB
N – 7
N – 1
N
t
DATA
t
FRAME
t
FCO
t
PD
t
CPD
t
EH
t
EL
07029-002
Figure 2. 12-Bit Data Serial Stream (Default)
DCO–
DCO+
DOUTx–
DOUTx+
FCO–
FCO+
AIN
CLK–
CLK+
LSB
N – 8
D0
N – 8
D1
N – 8
D2
N – 8
D3
N – 8
D4
N – 8
D5
N – 8
D6
N – 8
D7
N – 8
D8
N – 8
D9
N – 8
D10
N – 8
D0
N – 7
LSB
N – 7
N – 1
N
tDATA
tFRAME
tFCO
tPD
tCPD
tEH tEL
07029-004
Figure 3. 12-Bit Data Serial Stream, LSB First
AD9272
Rev. C | Page 11 of 44
ABSOLUTE MAXIMUM RATINGS
Table 4. Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
With
Respect To Rating
Electrical
AVDD1 GND −0.3 V to +2.0 V
AVDD2 GND −0.3 V to +3.9 V
DRVDD GND −0.3 V to +2.0 V
GND GND −0.3 V to +0.3 V
AVDD2 AVDD1 −2.0 V to +3.9 V
AVDD1 DRVDD −2.0 V to +2.0 V
AVDD2 DRVDD −2.0 V to +3.9 V
Digital Outputs
(DOUTx+, DOUTx−,
DCO+, DCO−,
FCO+, FCO−)
GND −0.3 V to +2.0 V
CLK+, CLK−,
GAIN+,GAIN−
GND −0.3 V to +3.9 V
LI-x, LO-x, LOSW-x LG-x −0.3 V to +2.0 V
CWDx−, CWDx+ GND −0.3 V to +3.9 V
GND −0.3 V to +2.0 V
PDWN, STBY, SCLK, CSB GND −0.3 V to +3.9 V
RBIAS, VREF, SDIO GND −0.3 V to +2.0 V
Environmental
Operating Temperature
Range (Ambient)
−40°C to +85°C
Storage Temperature
Range (Ambient)
−65°C to +150°C
Maximum Junction
Temperature
150°C
Lead Temperature
(Soldering, 10 sec)
300°C
THERMAL IMPEDANCE
Table 5.
Air Flow Velocity (m/sec) θJA1 θ
JB θJC Unit
0.0 20.3 N/A N/A °C/W
1.0 14.4 7.6 4.7 °C/W
2.5 12.9 N/A N/A °C/W
1 θJA is for a 4-layer PCB with a solid ground plane (simulated). The exposed
pad is soldered to the PCB.
ESD CAUTION
AD9272
Rev. C | Page 12 of 44
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
LI-F
LG-F
LO-F
LI-G
LG-G
LO-G
AVDD1
CLK–
NOTES
1. THE EXPOSED PAD SHOULD BE TIED TO A QUIET ANALOG GROUND.
CLK+
AVDD2
AVDD1
AVDD1
AVDD1
LI-E
LG-E
AVDD2
AVDD2
LI-H
LG-H
LO-H
AVDD2
AVDD1
LOSW-F
LOSW-G
LOSW-H
07029-005
AD9272
TOP VIEW
(Not to Scale)
EXPOSED PADDLE, PIN 0
(BOTTOM OF PACKAGE)
PIN 1
INDICATOR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
AVDD1
74
75
PDWN
73
STBY
72
DRVDD
71
DOUTA+
70
DOUTA–
69
DOUTB+
68
DOUTB–
67
DOUTC+
66
DOUTC–
65
DOUTD+
64
DOUTD–
63
FCO+
62
FCO–
61
DCO+
60
DCO–
59
DOUTE+
58
DOUTE–
57
DOUTF+
56
DOUTF–
55
DOUTG+
54
DOUTG–
53
DOUTH+
52
DOUTH–
51
DRVDD
AVDD1
LI-A
LG-A
LOSW-A
LI-B
LG-B
LO-B
AVDD1
SDIO
SCLK
CSB
AVDD2
AVDD2
LI-C
LG-C
LO-C
AVDD1
AVDD2
LI-D
LG-D
AVDD1
AVDD2
LO-A
LOSW-B
LOSW-C
LOSW-
D
LO-D
CWD0–
CWD0+
CWD1–
CWD1+
CWD2–
CWD2+
CWD3–
CWD3+
AVDD2
GAIN–
GAIN+
VREF
RBIAS
CWD5–
CWD5+
CWD4–
CWD4+
CWD6–
CWD6+
CWD7–
CWD7+
LO-E
LOSW-E
Figure 4. TQFP Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Name Description
0 GND Ground (exposed paddle should be tied to a quiet analog ground)
4, 10, 16, 22, 25, 50,
54, 60, 66, 72
AVDD1 1.8 V Analog Supply
3, 9, 15, 21, 55, 61,
67, 73, 86
AVDD2 3.0 V Analog Supply
26, 47 DRVDD 1.8 V Digital Output Driver Supply
1 LI-E LNA Analog Input for Channel E
2 LG-E LNA Ground for Channel E
5 LO-F LNA Analog Inverted Output for Channel F
6 LOSW-F LNA Analog Switched Output for Channel F
7 LI-F LNA Analog Input for Channel F
8 LG-F LNA Ground for Channel F
11 LO-G LNA Analog Inverted Output for Channel G
12 LOSW-G LNA Analog Switched Output for Channel G
13 LI-G LNA Analog Input for Channel G
14 LG-G LNA Ground for Channel G
17 LO-H LNA Analog Inverted Output for Channel H
18 LOSW-H LNA Analog Switched Output for Channel H
19 LI-H LNA Analog Input for Channel H
AD9272
Rev. C | Page 13 of 44
Pin No. Name Description
20 LG-H LNA Ground for Channel H
23 CLK− Clock Input Complement
24 CLK+ Clock Input True
27 DOUTH− ADC H Digital Output Complement
28 DOUTH+ ADC H Digital Output True
29 DOUTG− ADC G Digital Output Complement
30 DOUTG+ ADC G Digital Output True
31 DOUTF− ADC F Digital Output Complement
32 DOUTF+ ADC F Digital Output True
33 DOUTE− ADC E Digital Output Complement
34 DOUTE+ ADC E Digital Output True
35 DCO− Digital Clock Output Complement
36 DCO+ Digital Clock Output True
37 FCO− Frame Clock Digital Output Complement
38 FCO+ Frame Clock Digital Output True
39 DOUTD− ADC D Digital Output Complement
40 DOUTD+ ADC D Digital Output True
41 DOUTC− ADC C Digital Output Complement
42 DOUTC+ ADC C Digital Output True
43 DOUTB− ADC B Digital Output Complement
44 DOUTB+ ADC B Digital Output True
45 DOUTA− ADC A Digital Output Complement
46 DOUTA+ ADC A Digital Output True
48 STBY Standby Power-Down
49 PDWN Full Power-Down
51 SCLK Serial Clock
52 SDIO Serial Data Input/Output
53 CSB Chip Select Bar
56 LG-A LNA Ground for Channel A
57 LI-A LNA Analog Input for Channel A
58 LOSW-A LNA Analog Switched Output for Channel A
59 LO-A LNA Analog Inverted Output for Channel A
62 LG-B LNA Ground for Channel B
63 LI-B LNA Analog Input for Channel B
64 LOSW-B LNA Analog Switched Output for Channel B
65 LO-B LNA Analog Inverted Output for Channel B
68 LG-C LNA Ground for Channel C
69 LI-C LNA Analog Input for Channel C
70 LOSW-C LNA Analog Switched Output for Channel C
71 LO-C LNA Analog Inverted Output for Channel C
74 LG-D LNA Ground for Channel D
75 LI-D LNA Analog Input for Channel D
76 LOSW-D LNA Analog Switched Output for Channel D
77 LO-D LNA Analog Inverted Output for Channel D
78 CWD0− CW Doppler Output Complement for Channel 0
79 CWD0+ CW Doppler Output True for Channel 0
80 CWD1− CW Doppler Output Complement for Channel 1
81 CWD1+ CW Doppler Output True for Channel 1
82 CWD2− CW Doppler Output Complement for Channel 2
83 CWD2+ CW Doppler Output True for Channel 2
84 CWD3− CW Doppler Output Complement for Channel 3
85 CWD3+ CW Doppler Output True for Channel 3
87 GAIN− Gain Control Voltage Input Complement
AD9272
Rev. C | Page 14 of 44
Pin No. Name Description
88 GAIN+ Gain Control Voltage Input True
89 RBIAS External Resistor to Set the Internal ADC Core Bias Current
90 VREF Voltage Reference Input/Output
91 CWD4− CW Doppler Output Complement for Channel 4
92 CWD4+ CW Doppler Output True for Channel 4
93 CWD5− CW Doppler Output Complement for Channel 5
94 CWD5+ CW Doppler Output True for Channel 5
95 CWD6− CW Doppler Output Complement for Channel 6
96 CWD6+ CW Doppler Output True for Channel 6
97 CWD7− CW Doppler Output Complement for Channel 7
98 CWD7+ CW Doppler Output True for Channel 7
99 LO-E LNA Analog Inverted Output for Channel E
100 LOSW-E LNA Analog Switched Output for Channel E
AD9272
Rev. C | Page 15 of 44
TYPICAL PERFORMANCE CHARACTERISTICS
fSAMPLE = 40 MSPS, fIN = 5 MHz, RS = 50 Ω, LNA gain = 21.3 dB, LNA bias = high, PGA gain = 27 dB, AAF LPF cutoff = fSAMPLE/4.5, HPF = LPF
cutoff/20.7 (default), unless otherwise noted.
–2.0
–1.5
–0.5
–1.0
0
0.5
1.0
1.5
2.0
0 0.2 0.4 0.6 0.8 1.0
GAIN+ (V)
GAIN ERROR (dB)
1.2 1.4 1.6
+85°C
+25°C
–40°C
07029-114
Figure 5. Gain Error vs. GAIN+ at Three Temperatures
0
5
10
15
20
25
–1.0
–0.9
–0.8
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
PERCENTAGE OF UNITS (%)
GAIN ERROR (dB)
07029-184
Figure 6. Gain Error Histogram, GAIN+ = 0.16 V
0
2
4
6
10
8
12
14
–1.0
–0.9
–0.8
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
PERCENTAGE OF UNITS (%)
GAIN ERROR (dB)
07029-185
Figure 7. Gain Error Histogram, GAIN+ = 0.8 V
0
5
10
15
20
25
–1.0
–0.9
–0.8
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
PERCENTAGE OF UNITS (%)
GAIN ERROR (dB)
07029-186
Figure 8. Gain Error Histogram, GAIN+ = 1.44 V
0
5
10
15
20
25
–1.25 –1.00 –0.75
PERCENTAGE OF UNITS (%)
–0.50 –0.25 0
CHANNEL-TO-CHANNEL GAIN MATCHING (dB)
0.25 0.50 0.75 1.00 1.25
07029-180
Figure 9. Gain Match Histogram, GAIN+ = 0.3 V
07029-181
5
0
10
15
20
25
–1.25 –1.00 –0.75
PERCENTAGE OF UNITS (%)
–0.50 –0.25 0
CHANNEL-TO-CHANNEL GAIN MATCHING (dB)
0.25 0.50 0.75 1.00 1.25
Figure 10. Gain Match Histogram, GAIN+ = 1.3 V
AD9272
Rev. C | Page 16 of 44
–7 –6 –5 –4
500k
450k
400k
350k
300k
250k
200k
150k
100k
50k
0
–3–2–101234567
NUMBER OF HITS
CODES
07029-115
Figure 11. Output-Referred Noise Histogram, GAIN+ = 0 V
–7 –6 –5 –4
180k
160k
140k
120k
100k
80k
60k
40k
20k
0
–3–2–101234567
NUMBER OF HITS
CODES
07029-116
Figure 12. Output-Referred Noise Histogram, GAIN+ = 1.6 V
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
1234567891
INPUT-REFERRED NOISE (nV/
0
√
Hz)
FREQUENCY (MHz)
LNA GAIN = 21.3dB
LNA GAIN = 15.6dB
LNA GAIN = 17.9dB
07029-187
Figure 13. Short-Circuit, Input-Referred Noise vs. Frequency,
PGA Gain = 30 dB, GAIN+ = 1.6 V
–140
–138
–136
–134
–132
–130
–128
–
126
0 0.2 0.4 0.6 0.8
GAIN+ (V)
1.0 1.2 1.4 1.6
OUTPUT-REFERRED NOISE (dBFS/Hz)
LNA GAIN = 8×
LNA GAIN = 12×
LNA GAIN = 6×
07029-117
Figure 14. Short-Circuit, Output-Referred Noise vs. GAIN+
50
52
54
56
58
60
62
64
0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6
SNR/SIN
A
D(dBFS)
GAIN+ (V)
SINAD
SNR
07029-118
Figure 15. SNR/SINAD vs. GAIN+, AIN = −1 dBFS
–25
–20
–15
–10
–5
0
0 5 10 15 20 25 30 35 40
AMPLITUDE (dBFS)
FREQUENCY (MHz)
07029-120
AD9272-40
AD9272-65
AD9272-80
Figure 16. Antialiasing Filter (AAF) Pass-Band Response,
LPF Cutoff = 1 × (1/4.5) × fSAMPLE
AD9272
Rev. C | Page 17 of 44
0
25
50
75
100
125
150
0 5 10 15 20 25 30 35 40
GROUP DELAY (ns)
FREQUENCY (MHz)
GAIN+ = 1.6V
GAIN+ = 0.8V
GAIN+ = 0V
07029-121
Figure 17. Antialiasing Filter (AAF) Group Delay Response
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
024681012141
SECOND-ORDER H
6
A
RMONIC DISTORTION (dBFS)
INPUT FREQUENCY (MHz)
07029-122
GAIN+ = 1.6V
GAIN+ = 1.0V
GAIN+ = 0.4V
Figure 18. Second-Order Harmonic Distortion vs. Frequency, AIN = −1 dBFS
–80
–70
–60
–50
–40
–30
–20
–10
0
024 681012141
THIRD-ORDE
6
R
H
A
RMONIC DISTORTION (dBFS)
INPUT FREQUENCY (MHz)
GAIN+ = 1.6V
GAIN+ = 1.0V
GAIN+ = 0.4V
07029-123
Figure 19. Third-Order Harmonic Distortion vs. Frequency, AIN = −1 dBFS
–120
–100
–80
–60
–40
–20
0
–50 –40 –30 –20 –10 0
SECOND-ORDER H
A
RMONIC DISTORTION (dBFS)
ADC OUTPUT LEVEL (dBFS)
07029-124
GAIN+ =
1.6V
GAIN+ = 0.8V
GAIN+ = 0V
Figure 20. Second-Order Harmonic Distortion vs. ADC Output
–120
–100
–80
–60
–40
–20
0
–40 –35 –30 –25 –20 –15 –10 –5 0
THIRD-ORDER H
A
RMONIC DISTORTION (dBFS)
ADC OUTPUT LEVEL (dBFS)
GAIN+ = 1.6V
GAIN+ = 0.8V
GAIN+ = 0V
07029-125
Figure 21. Third-Order Harmonic Distortion vs. ADC Output Level
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
0.4 0.6 0.8 1.0 1.2 1.4 1.6
IMD3 (
d
BFS)
GAIN+ (V)
8MHz
2.3MHz 5MHz
fIN2
=
fIN1
+0.01MHz
A
IN1
= –1dBFS, A
IN2
= –21dBFS
07029-126
Figure 22. IMD3 vs. GAIN+
AD9272
Rev. C | Page 18 of 44
–120
–100
–80
–60
–40
–20
0
–40 –35 –30 –25 –20 –15 –10 –5 0
IMD3 (dBFS)
FUND1 LEVEL (dBFS)
GAIN+ = 0.8V
GAIN+ = 1.6V
GAIN+ = 0V
f
IN1
= 5.00MHz,
f
IN2
= 5.01MHz
FUND2 LEVEL = FUND1 LEVEL – 20dB
07029-127
Figure 23. IMD3 vs. Fundamental 1 Amplitude Level
AD9272
Rev. C | Page 19 of 44
EQUIVALENT CIRCUITS
LI-x,
LG-x
AVDDx
15kΩ
V
CM
07029-073
Figure 24. Equivalent LNA Input Circuit
LO-x,
LOSW-x
10Ω
AVDDx
07029-075
Figure 25. Equivalent LNA Output Circuit
10Ω
10kΩ
10kΩ
CLK–
10Ω
1.25V
CLK+
07029-007
Figure 26. Equivalent Clock Input Circuit
07029-008
S
DIO
350Ω
30kΩ
A
VDDx
Figure 27. Equivalent SDIO Input Circuit
DR
V
DD
DRGND
DOUTx– DOUTx+
V
V
V
V
07029-009
Figure 28. Equivalent Digital Output Circuit
07029-010
SCLK, PDWN,
OR STBY 30kΩ
1kΩ
Figure 29. Equivalent SCLK, PDWN, or STBY Input Circuit
AD9272
Rev. C | Page 20 of 44
07029-011
100Ω
A
V
DDx
RBIAS
Figure 30. Equivalent RBIAS Circuit
C
SB
70kΩ
1kΩ
A
V
DDx
07029-012
Figure 31. Equivalent CSB Input Circuit
VREF
6kΩ
07029-014
Figure 32. Equivalent VREF Circuit
G
AIN+
A
VDD2
50Ω
07029-074
Figure 33. Equivalent GAIN+ Input Circuit
GAIN– 40Ω
+0.5V
07029-176
Figure 34. Equivalent GAIN− Input Circuit
CWDx+,
CWDx–
10Ω
+0.5V
07029-076
Figure 35. Equivalent CWDx± Output Circuit
AD9272
Rev. C | Page 21 of 44
THEORY OF OPERATION
ULTRASOUND
The primary application for the AD9272 is medical ultrasound.
Figure 36 shows a simplified block diagram of an ultrasound
system. A critical function of an ultrasound system is the time
gain control (TGC) compensation for physiological signal
attenuation. Because the attenuation of ultrasound signals is
exponential with respect to distance (time), a linear-in-dB VGA
is the optimal solution.
Key requirements in an ultrasound signal chain are very low
noise, active input termination, fast overload recovery, low
power, and differential drive to an ADC. Because ultrasound
machines use beam-forming techniques requiring large binary-
weighted numbers (for example, 32 to 512) of channels, using
the lowest power at the lowest possible noise is of chief importance.
Most modern machines use digital beam forming. In this
technique, the signal is converted to digital format immediately
following the TGC amplifier, and then beam forming is
accomplished digitally.
The ADC resolution of 12 bits with up to 80 MSPS sampling
satisfies the requirements of both general-purpose and high-
end systems.
Power conservation and low cost are two of the most important
factors in low-end and portable ultrasound machines, and the
AD9272 is designed to meet these criteria.
For additional information regarding ultrasound systems, refer
to “How Ultrasound System Considerations Influence Front-End
Component Choice,” Analog Dialogue, Volume 36, Number 1,
May–July 2002, and “The AD9271—A Revolutionary Solution
for Portable Ultrasound,” Analog Dialogue, Volume 41, Number 3,
July 2007.
BEAM-FORMER
CENTRAL CONTROL
Rx BEAM FORMER
(B AND F MODES)
COLOR
DOPPLER (PW)
PROCESSING
(F MODE)
IMAGE AND
MOTION
PROCESSING
(B MODE)
SPECTRAL
DOPPLER
PROCESSING
MODE
DISPLAY
AUDIO
OUTPUT
Tx BEAM FORMER
CW (ANALOG)
BEAM FORMER
TRANSDUCER
ARRAY
128, 256, ...
ELEMENTS BIDIRECTIONAL
CABLE
HV
MUX/
DEMUX T/R
SWITCHES
Tx H
V
AMPs
MULTICHANNELS
AD9272
AAF
VGALNA ADC
CW
07029-077
Figure 36. Simplified Ultrasound System Block Diagram
AD9272
Rev. C | Page 22 of 44
07029-071
LNA
LI-x
LG-x
LO-x
DOUTx+
DOUTx–
C
S
T/R
SWITCH
C
LG
C
FB
R
FB2
C
SH
GAIN
INTERPOLATOR
LOSW-x
R
FB1
SWITCH
ARRAY
g
m
CWD[7:0]+
CWD[7:0]–
ATTENUATOR
–42dB TO 0dB
GAIN–
PIPELINE
ADC
SERIAL
LVDS
POSTAMP
GAIN+
AD9272
TRANSDUCE
R
FILTER
21dB
24dB,
27dB,
30dB
15.6dB,
17.9dB,
21.3dB
Figure 37. Simplified Block Diagram of a Single Channel
CHANNEL OVERVIEW
Each channel contains both a TGC signal path and a CW Doppler
signal path. Common to both signal paths, the LNA provides user-
adjustable input impedance termination. The CW Doppler path
includes a transconductance amplifier and a crosspoint switch.
The TGC path includes a differential X-AMP® VGA, an antialiasing
filter, and an ADC. Figure 37 shows a simplified block diagram
with external components.
The signal path is fully differential throughout to maximize signal
swing and reduce even-order distortion; however, the LNA is
designed to be driven from a single-ended signal source.
Low Noise Amplifier (LNA)
Good noise performance relies on a proprietary ultralow noise
LNA at the beginning of the signal chain, which minimizes the
noise contribution in the following VGA. Active impedance
control optimizes noise performance for applications that benefit
from input impedance matching.
A simplified schematic of the LNA is shown in Figure 38. LI-x is
capacitively coupled to the source. An on-chip bias generator
establishes dc input bias voltages of around 0.9 V and centers
the output common-mode levels at 1.5 V (AVDD2 divided by
2). A capacitor, CLG, of the same value as the input coupling
capacitor, CS, is connected from the LG-x pin to ground.
07029-101
LI-x
CS
CLG
CFB
CSH
LG-x
LO-x
LOSW-x
VCM VCM
VO+
VO–
RFB1
RFB2
T/R
SWITCH
TRANSDUCER
Figure 38. Simplified LNA Schematic
The LNA supports differential output voltages as high as 4.4 V p-p
with positive and negative excursions of ±1.1 V from a common-
mode voltage of 1.5 V. The LNA differential gain sets the maximum
input signal before saturation. One of three gains is set through
the SPI. The corresponding full-scale input for the gain settings
of 6, 8, and 12 is 733 mV p-p, 550 mV p-p, and 367 mV p-p,
respectively. Overload protection ensures quick recovery time
from large input voltages. Because the inputs are capacitively
coupled to a bias voltage near midsupply, very large inputs can
be handled without interacting with the ESD protection.
Low value feedback resistors and the current-driving capability
of the output stage allow the LNA to achieve a low input-referred
noise voltage of 0.75 nV/√Hz (at a gain of 21.3 dB). This is
achieved with a current consumption of only 27 mA per channel
(80 mW). On-chip resistor matching results in precise single-
ended gains, which are critical for accurate impedance control.
The use of a fully differential topology and negative feedback
minimizes distortion. Low second-order harmonic distortion is
particularly important in second harmonic ultrasound imaging
applications. Differential signaling enables smaller swings at each
output, further reducing third-order distortion.
Recommendation
It is highly recommended that the LG-x pins form a Kelvin type
connection to the input or probe connection ground. Simply
connecting the LG pin to ground near the device can allow
differences in potential to be amplified through the LNA. This
generally shows up as a dc offset voltage that can vary from
channel to channel and part to part given the application and
layout of the PCB (see Figure 38).
AD9272
Rev. C | Page 23 of 44
Active Impedance Matching
The LNA consists of a single-ended voltage gain amplifier with
differential outputs, and the negative output is externally
available. For example, with a fixed gain of 8× (17.9 dB), an
active input termination is synthesized by connecting a
feedback resistor between the negative output pin, LO-x, and the
positive input pin, LI-x. This is a well known technique used for
interfacing multiple probe impedances to a single system. The
input resistance is shown in Equation 1.
)
2
1( A
R
RFB
IN
+
= (1)
where A/2 is the single-ended gain or the gain from the LI-x
inputs to the LO-x outputs, and RFB is the resulting impedance
of the RFB1 and RFB2 combination (see Figure 38).
Because the amplifier has a gain of 8× from its input to its
differential output, it is important to note that the gain A/2 is
the gain from Pin LI-x to Pin LO-x, and it is 6 dB less than the
gain of the amplifier or 12.1 dB (4×). The input resistance is
reduced by an internal bias resistor of 15 kΩ in parallel with the
source resistance connected to Pin LI-x, with Pin LG-x ac
grounded. Equation 2 can be used to calculate the needed RFB
for a desired RIN, even for higher values of RIN.
Ω
+
=k15||
)31(
FB
IN
R
R (2)
For example, to set RIN to 200 Ω, the value of RFB must be
1000 Ω. If the simplified equation (Equation 2) is used to
calculate RIN, the value is 188 Ω, resulting in a gain error less
than 0.6 dB. Some factors, such as the presence of a dynamic
source resistance, might influence the absolute gain accuracy
more significantly. At higher frequencies, the input capacitance
of the LNA must be considered. The user must determine the
level of matching accuracy and adjust RFB accordingly.
The bandwidth (BW) of the LNA is greater than 100 MHz.
Ultimately, the BW of the LNA limits the accuracy of the
synthesized RIN. For RIN = RS up to about 200 Ω, the best match
is between 100 kHz and 10 MHz, where the lower frequency
limit is determined by the size of the ac-coupling capacitors,
and the upper limit is determined by the LNA BW. Furthermore,
the input capacitance and RS limit the BW at higher frequencies.
Figure 39 shows RIN vs. frequency for various values of RFB.
07029-188
10
100
1k
100k 1M 10M 100M
INPUT RESISTANCE (Ω)
FREQUENCY (Hz)
RS = 50Ω, RFB = 200Ω, CSH = 70pF
RS = 100Ω, RFB = 400Ω, CSH = 20pF
RS = 200Ω, RFB = 800Ω
RS = 500Ω, RFB = 2kΩ
Figure 39. RIN vs. Frequency for Various Values of RFB
(Effects of RS and CSH Are Also Shown)
Note that at the lowest value (50 Ω), RIN peaks at frequencies
greater than 10 MHz. This is due to the BW roll-off of the LNA,
as mentioned previously.
However, as can be seen for larger RIN values, parasitic capacitance
starts rolling off the signal BW before the LNA can produce
peaking. CSH further degrades the match; therefore, CSH should
not be used for values of RIN that are greater than 100 Ω. Table 7
lists the recommended values for RFB and CSH in terms of RIN.
CFB is needed in series with RFB because the dc levels at Pin LO-x
and Pin LI-x are unequal.
Table 7. Active Termination External Component Values
LNA Gain
(dB) RIN (Ω) RFB (Ω)
Minimum
CSH (pF) BW (MHz)
15.6 50 200 90 57
17.9 50 250 70 69
21.3 50 350 50 88
15.6 100 400 30 57
17.9 100 500 20 69
21.3 100 700 10 88
15.6 200 800 N/A 72
17.9 200 1000 N/A 72
21.3 200 1400 N/A 72
AD9272
Rev. C | Page 24 of 44
LNA Noise
The short-circuit noise voltage (input-referred noise) is an impor-
tant limit on system performance. The short-circuit input-referred
noise voltage for the LNA is 0.85 nV/√Hz at a gain of 21.3 dB,
including the VGA noise at a VGA postamp gain of 27 dB. These
measurements, which were taken without a feedback resistor,
provide the basis for calculating the input noise and noise figure
(NF) performance of the configurations shown in Figure 40.
V
OUT
UNTERMINATED
+
–
LI-x
R
IN
R
S
V
OUT
RESISTIVE TERMINATION
+
–
LI-x
R
IN
R
S
R
S
V
OUT
ACTIVE IMPEDANCE MATCH
+
–
LI-x
R
IN
R
FB
R
FB
1 + A/2
R
S
R
IN
=
07029-104
Figure 40. Input Configurations
Figure 41 and Figure 42 are simulations of noise figure vs. RS
results using these configurations and an input-referred noise
voltage of 3.8 nV/√Hz for the VGA. Unterminated (RFB = ∞)
operation exhibits the lowest equivalent input noise and noise
figure. Figure 42 shows the noise figure vs. source resistance
rising at low RS—where the LNA voltage noise is large compared
with the source noise—and at high RS due to the noise contribution
from RFB. The lowest NF is achieved when RS matches RIN.
The main purpose of input impedance matching is to improve the
transient response of the system. With resistive termination, the
input noise increases due to the thermal noise of the matching
resistor and the increased contribution of the input voltage
noise generator of the LNA. With active impedance matching,
however, the contributions of both are smaller (by a factor of
1/(1 + LNA Gain)) than they would be for resistive termination.
Figure 41 shows the relative noise figure performance. In this
graph, the input impedance was swept with RS to preserve the
match at each point. The noise figures for a source impedance of
50 are 7.3 dB, 4.2 dB, and 2.8 dB for the resistive termination,
active termination, and unterminated configurations, respectively.
The noise figures for 200 are 4.5 dB, 1.7 dB, and 1 dB,
respectively.
Figure 42 shows the noise figure as it relates to RS for various values
of RIN, which is helpful for design purposes.
10 100 1k
0
1.5
3.0
4.5
6.0
7.5
9.0
10.5
12.0
R
S
(Ω)
NOISE FIGURE (dB)
UNTERMINATED
RESISTIVE TERMINATION
ACTIVE TERMINATION
07029-182
Figure 41. Noise Figure vs. RS for Resistive Termination,
Active Termination Matched, and Unterminated Inputs, VGAIN = 0.8 V
10 100 1k
0
1
2
3
4
5
6
7
8
RS(Ω)
NOISE FIGURE (dB)
RIN = 50Ω
RIN = 75Ω
RIN = 100Ω
RIN = 200Ω
UNTERMINATED
07029-183
Figure 42. Noise Figure vs. RS for Various Fixed Values of RIN,
Active Termination Matched Inputs, VGAIN = 0.8 V
AD9272
Rev. C | Page 25 of 44
INPUT OVERDRIVE CW DOPPLER OPERATION
Excellent overload behavior is of primary importance in
ultrasound. Both the LNA and VGA have built-in overdrive
protection and quickly recover after an overload event.
Modern ultrasound machines used for medical applications
employ a 2N binary array of receivers for beam forming, with
typical array sizes of 16 or 32 receiver channels phase-shifted
and summed together to extract coherent information. When
used in multiples, the desired signals from each channel can be
summed to yield a larger signal (increased by a factor N, where
N is the number of channels), and the noise is increased by the
square root of the number of channels. This technique enhances
the signal-to-noise performance of the machine. The critical
elements in a beam-former design are the means to align the
incoming signals in the time domain and the means to sum the
individual signals into a composite whole.
Input Overload Protection
As with any amplifier, voltage clamping prior to the inputs is
highly recommended if the application is subject to high
transient voltages.
In Figure 43, a simplified ultrasound transducer interface is
shown. A common transducer element serves the dual functions
of transmitting and receiving ultrasound energy. During the
transmitting phase, high voltage pulses are applied to the ceramic
elements. A typical transmit/receive (T/R) switch can consist of
four high voltage diodes in a bridge configuration. Although the
diodes ideally block transmit pulses from the sensitive receiver
input, diode characteristics are not ideal, and the resulting leakage
transients imposed on the LI-x inputs can be problematic.
Beam forming, as applied to medical ultrasound, is defined as the
phase alignment and summation of signals that are generated
from a common source but received at different times by a
multi-element ultrasound transducer. Beam forming has two
functions: it imparts directivity to the transducer, enhancing its
gain, and it defines a focal point within the body from which the
location of the returning echo is derived.
Because ultrasound is a pulse system and time-of-flight is used to
determine depth, quick recovery from input overloads is essential.
Overload can occur in the preamp and the VGA. Immediately
following a transmit pulse, the typical VGA gains are low, and
the LNA is subject to overload from T/R switch leakage. With
increasing gain, the VGA can become overloaded due to strong
echoes that occur near field echoes and acoustically dense materials,
such as bone.
The AD9272 includes the front-end components needed to
implement analog beam forming for CW Doppler operation.
These components allow CW channels with similar phases to be
coherently combined before phase alignment and down mixing,
thus reducing the number of delay lines or adjustable phase shifters/
down mixers (AD8333 or AD8339) required. Next, if delay lines
are used, the phase alignment is performed, and then the channels
are coherently summed and down converted by a dynamic range
I/Q demodulator. Alternatively, if phase shifters/down mixers,
such as the AD8333 and AD8339, are used, phase alignment
and down conversion are done before coherently summing all
channels into I/Q signals. In either case, the resultant I and Q
signals are filtered and sampled by two high resolution ADCs,
and the sampled signals are processed to extract the relevant
Doppler information.
Figure 43 illustrates an external overload protection scheme. A
pair of back-to-back signal diodes is installed prior to installing the
ac-coupling capacitors. Keep in mind that all diodes shown in
this example are prone to exhibiting some amount of shot noise.
Many types of diodes are available for achieving the desired
noise performance. The configuration shown in Figure 43 tends
to add 2 nV/√Hz of input-referred noise. Decreasing the 5 kΩ
resistor and increasing the 2 kΩ resistor may improve noise
contribution, depending on the application. With the diodes
shown in Figure 43, clamping levels of ±0.5 V or less
significantly enhance the overload performance of the system. Alternately, the LNA of the AD9272 can directly drive the AD8333
or AD8339 without the crosspoint switch. The LO-x pin presents
the inverting LNA output, and the LOSW-x pin can be configured
via Register 0x2C (see Table 17) to connect to the noninverting
output to provide a differential output of the LNA. The LNA output
full-scale voltage of the AD9272 is 4.4 V p-p, and the input full-
scale voltage is 2.7 V p-p. If no attenuation is provided between
the LNA output and the demodulator, the LNA input full-scale
voltage must be limited.
TRANSDUCER
10nF
10nF
2kΩ
5kΩ
5kΩ
AD9272
Tx
DRIVER HV
+5
V
–5V
LNA
07029-100
Figure 43. Input Overload Protection
AD9272
Rev. C | Page 26 of 44
AD9272
LNA
g
m
g
m
g
m
g
m
g
m
g
m
g
m
g
m
SWITCH
ARRAY
8 × CHANNEL
16-BIT
ADC
Q
I
LNA
LNA
LNA
AD9272
LNA
SWITCH
ARRAY
8 × CHANNEL
LNA
LNA
LNA
2.5V
AD8333
2.5V
2.5V
2.5V
AD8333
16-BIT
ADC
600µH
600µH
600µH
600µH
600µH
700Ω
700Ω
700Ω
700Ω
600µH
600µH
600µH
07029-096
Figure 44. Typical Connection Interface with the AD8333 or AD8339 Using the CWDx± Outputs
LNA
AD9272
1nF
500Ω
LO-A
LOSW-A
5kΩ5kΩ
AD8339
2.5
V
1nF
500Ω
LNA
1nF
500ΩLOS-B
LOSW-B
5kΩ5kΩ
2.5V
1nF
500Ω
LNA
1nF
500ΩLO-H
LOSW-H
5kΩ5kΩ
AD8339
I
2.5V
1nF
500Ω
Q
16-BIT
ADC
16-BIT
ADC
07029-111
Figure 45. Typical Connection Interface with the AD8333 or AD8339 Using the LO-x and LOSW-x Outputs
AD9272
Rev. C | Page 27 of 44
Crosspoint Switch
Each LNA is followed by a transconductance amp for voltage-
to-current conversion. Currents can be routed to one of eight
pairs of differential outputs or to 16 single-ended outputs for
summing. Each CWD output pin sinks 2.4 mA dc current, and
the signal has a full-scale current of ±2 mA for each channel
selected by the crosspoint switch. For example, if four channels
are summed on one CWD output, the output sinks 9.6 mA dc
and has a full-scale current output of ±8 mA.
The maximum number of channels combined must be considered
when setting the load impedance for current-to-voltage conversion
to ensure that the full-scale swing and common-mode voltage
are within the operating limits of the AD9272. When interfacing
to the AD8339, a common-mode voltage of 2.5 V and a full-scale
swing of 2.8 V p-p are desired. This can be accomplished by
connecting an inductor between each CWD output and a 2.5 V
supply and then connecting either a single-ended or differential
load resistance to the CWDx± outputs. The value of resistance
should be calculated based on the maximum number of channels
that can be combined.
CWDx± outputs are required under full-scale swing to be
greater than 1.5 V and less than AVDD2 (3.0 V supply).
TGC OPERATION
The TGC signal path is fully differential throughout to
maximize signal swing and reduce even-order distortion;
however, the LNAs are designed to be driven from a single-
ended signal source. Gain values are referenced from the single-
ended LNA input to the differential ADC input. A simple
exercise in understanding the maximum and minimum gain
requirements is shown in Figure 46.
LNA FS
(0.55V p-p SE)
LNA INPUT-REFERRED
NOISE FLOOR
(3.9µV rms) @ AAF BW = 15MHz
LNA + VGA NOISE = 1.0nV/ Hz
ADC FS (2
V
p-p)
~10dB MARGIN
>11dB MARGIN
ADC NOISE FLOOR
(224µV rms)
MINIMUM GAIN
MAXIMUM GAIN
LNA
ADC
70dB
VGA GAIN RANGE > 42dB
MAX CHANNEL GAIN > 48dB
94dB
0
7029-097
Figure 46. Gain Requirements of TGC Operation for a 12-Bit, 40 MSPS ADC
The maximum gain required is determined by
(ADC Noise Floor/VGA Input Noise Floor) + Margin =
20 log(224/3.9) + 11 dB = 46 dB
The minimum gain required is determined by
(ADC Input FS/VGA Input FS) + Margin =
20 log(2/0.55) − 10 dB = 3 dB
Therefore, 42 dB of gain range for a 12-bit, 40 MSPS ADC with
15 MHz of bandwidth should suffice in achieving the dynamic
range required for most ultrasound systems today.
The system gain is distributed as listed in Table 8.
Table 8. Channel Gain Distribution
Section Nominal Gain (dB)
LNA 15.6/17.9/21.3
Attenuator 0 to −42
VGA Amp 21/24/27/30
Filter 0
ADC 0
The linear-in-dB gain (law conformance) range of the TGC path
is 42 dB. The slope of the gain control interface is 28 dB/V, and
the gain control range is −0.8 V to +0.8 V. Equation 3 is the
expression for the differential voltage VGAIN, and Equation 4 is
the expression for the channel gain.
)()()( −
−
+
=
GAINGAINVVGAIN (3)
ICPTVGain GAIN += V
dB
5.28)dB( (4)
where ICPT is the intercept point of the TGC gain.
In its default condition, the LNA has a gain of 21.3 dB (12×), and
the VGA postamp gain is 24 dB if the voltage on the GAIN+ pin is
0 V and GAIN− is 0.8 V (42 dB attenuation). This gives rise to a
total gain (or ICPT) of 3.6 dB through the TGC path if the LNA
input is unmatched or of −2.4 dB if the LNA is matched to 50 Ω
(RFB = 350 Ω). If the voltage on the GAIN+ pin is 1.6 V and the
GAIN− pin is 0.8 V (0 dB attenuation), however, the VGA gain
is 24 dB. This results in a total gain of 45 dB through the TGC path
if the LNA input is unmatched or in a total gain of 39 dB if the
LNA input is matched.
Each LNA output is dc-coupled to a VGA input. The VGA consists
of an attenuator with a range of −42 dB to 0 dB followed by an
amplifier with 21 dB, 24 dB, 27 dB, or 30 dB of gain. The X-AMP
gain-interpolation technique results in low gain error and uniform
bandwidth, and differential signal paths minimize distortion.
AD9272
Rev. C | Page 28 of 44
Table 9. Sensitivity and Dynamic Range of Trade-Offs1, 2, 3
LNA VGA Channel
Gain
Full-Scale Input
(V p-p)
Input-Referred
Noise Voltage
(nV/√Hz) Postamp Gain (dB)
Typical Output Dynamic Range
Input-Referred Noise4 @
GAIN+ = 1.6 V (nV/√Hz)
(V/V) (dB) GAIN+ = 0 V5 GAIN+ = 1.6 V6
6 15.6 0.733 0.98 21 67.5 65.1 1.395
24 66.4 63.0 1.286
27 64.6 60.6 1.227
30 62.5 57.9 1.197
8 17.9 0.550 0.86 21 67.5 64.5 1.149
24 66.4 62.3 1.071
27 64.5 59.8 1.030
30 62.5 57.1 1.009
12 21.3 0.367 0.75 21 67.5 63.3 0.910
24 66.4 60.9 0.865
27 64.6 58.2 0.842
30 62.5 55.4 0.830
1 LNA: output full scale = 4.4 V p-p differential.
2 Filter: loss ~ 1 dB, NBW = 13.3 MHz, GAIN− = 0.8 V.
3 ADC: 40 MSPS, 70 dB SNR, 2 V p-p full-scale input.
4 Channel noise at maximum VGA gain.
5 Output dynamic range at minimum VGA gain (VGA dominated).
6 Output dynamic range at maximum VGA gain (LNA dominated).
Table 9 demonstrates the sensitivity and dynamic range of
trade-offs that can be achieved relative to various LNA and
VGA gain settings.
For example, when the VGA is set for the minimum gain voltage,
the TGC path is dominated by VGA noise and achieves the
maximum output SNR. However, as the postamp gain options
are increased, the input-referred noise is reduced, and the SNR
is degraded.
If the VGA is set for the maximum gain voltage, the TGC path
is dominated by LNA noise and achieves the lowest input-
referred noise but with degraded output SNR. The higher the
TGC (LNA + VGC) gain, the lower the output SNR. As the
postamp gain is increased, the input-referred noise is reduced.
At low gains, the VGA should limit the system noise perfor-
mance (SNR); at high gains, the noise is defined by the source and
the LNA. The maximum voltage swing is bound by the full-
scale peak-to-peak ADC input voltage (2 V p-p).
Both the LNA and VGA have full-scale limitations within each
section of the TGC path. These limitations are dependent on the
gain setting of each function block and on the voltage applied to the
GAIN± pins. The LNA has three limitations, or full-scale settings,
that can be applied through the SPI. Similarly, the VGA has four
postamp gain settings that can be applied through the SPI. The
voltage applied to the GAIN± pins determines which amplifier
(the LNA or VGA) saturates first. The maximum signal input level
that can be applied as a function of voltage on the GAIN± pins
for the selectable gain options of the SPI is shown in Figure 47 to
Figure 49.
0
0.1
0.2
0.3
0.4
0.5
0.6
0.8
0.7
0.9
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
INPUT FULL SCALE (V p-p)
GAIN+ (V)
07029-177
PGA GAIN = 21dB
PGA GAIN = 24dB
PGA GAIN = 27dB
PGA GAIN = 30dB
Figure 47. LNA with 15.6 dB Gain Setting/VGA Full-Scale Limitations
AD9272
Rev. C | Page 29 of 44
0
0.1
0.2
0.3
0.4
0.5
0.6
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
INPUT FULL SCALE (V p-p)
GAIN+ (V)
PGA GAIN = 21dB
07029-178
PGA GAIN = 30dB
PGA GAIN = 27dB
PGA GAIN = 24dB
Figure 48. LNA with 17.9 dB Gain Setting/VGA Full-Scale Limitations
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.9
0.8
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
INPUT FULL SCALE (V p-p)
GAIN+ (V)
PGA GAIN = 21dB
PGA GAIN = 30dB
PGA GAIN = 30dB
07029-179
PGA GAIN = 24dB
PGA GAIN = 27dB
Figure 49. LNA with 21.3 dB Gain Setting/VGA Full-Scale Limitations
Variable Gain Amplifier
The differential X-AMP VGA provides precise input attenuation
and interpolation. It has a low input-referred noise of 3.8 nV/√Hz
and excellent gain linearity. A simplified block diagram is shown in
Figure 50.
VIP
G
AIN±
3dB
VIN
g
m
POSTAMP
POSTAMP
+
–
GAIN INTERPOLATOR
07029-078
Figure 50. Simplified VGA Schematic
The input of the VGA is a 14-stage differential resistor ladder with
3.5 dB per tap. The resulting total gain range is 42 dB, which
allows for range loss at the endpoints. The effective input resistance
per side is 180 Ω nominally for a total differential resistance of
360 Ω. The ladder is driven by a fully differential input signal from
the LNA. LNA outputs are dc-coupled to avoid external decoupling
capacitors. The common-mode voltage of the attenuator and the
VGA is controlled by an amplifier that uses the same midsupply
voltage derived in the LNA, permitting dc coupling of the LNA
to the VGA without introducing large offsets due to common-
mode differences. However, any offset from the LNA becomes
amplified as the gain increases, producing an exponentially
increasing VGA output offset.
The input stages of the X-AMP are distributed along the ladder,
and a biasing interpolator, controlled by the gain interface, deter-
mines the input tap point. With overlapping bias currents, signals
from successive taps merge to provide a smooth attenuation range
from −42 dB to 0 dB. This circuit technique results in linear-in-dB
gain law conformance and low distortion levels—only deviating
±0.5 dB or less from the ideal. The gain slope is monotonic with
respect to the control voltage and is stable with variations in
process, temperature, and supply.
The X-AMP inputs are part of a programmable gain feedback
amplifier that completes the VGA. Its bandwidth is approximately
100 MHz. The input stage is designed to reduce feedthrough to
the output and to ensure excellent frequency response uniformity
across the gain setting.
Gain Control
The gain control interface, GAIN±, is a differential input. VGAIN
varies the gain of all VGAs through the interpolator by selecting
the appropriate input stages connected to the input attenuator.
For GAIN− at 0.8 V, the nominal GAIN+ range for 28.5 dB/V is
0 V to 1.6 V, with the best gain linearity from about 0.16 V to
1.44 V, where the error is typically less than ±0.5 dB. For
GAIN+ voltages greater than 1.44 V and less than 0.16 V, the
error increases. The value of GAIN+ can exceed the supply
voltage by 1 V without gain foldover.
Gain control response time is less than 750 ns to settle within 10%
of the final value for a change from minimum to maximum gain.
There are two ways in which the GAIN+ and GAIN− pins can
be interfaced. Using a single-ended method, a Kelvin type of
connection to ground can be used as shown in Figure 51. For
driving multiple devices, it is preferable to use a differential
method, as shown in Figure 52. In either method, the GAIN+
and GAIN− pins should be dc-coupled and driven to accom-
modate a 1.6 V full-scale input.
AD9272
GAIN+
GAIN–
100Ω
0V TO 1.6V DC
50Ω
0.01µF
0.01µF
KELVIN
CONNECTION
07029-109
Figure 51. Single-Ended GAIN± Pins Configuration
AD9272
Rev. C | Page 30 of 44
GAIN–
50Ω
GAIN+
AD9272
AVDD2
31.3kΩ
10kΩ
0.01µF
±0.4DC AT
0.8V CM
±0.4DC AT
0.8V CM
100Ω
499Ω
±0.8V DC
0.01µF
100Ω
499Ω
523Ω
499Ω
0.8V CM
AD8138
07029-098
Figure 52. Differential GAIN± Pins Configuration
VGA Noise
In a typical application, a VGA compresses a wide dynamic
range input signal to within the input span of an ADC. The
input-referred noise of the LNA limits the minimum resolvable
input signal, whereas the output-referred noise, which depends
primarily on the VGA, limits the maximum instantaneous
dynamic range that can be processed at any one particular gain
control voltage. This latter limit is set in accordance with the
total noise floor of the ADC.
Output-referred noise as a function of GAIN+ is shown in
Figure 14 for the short-circuit input conditions. The input
noise voltage is simply equal to the output noise divided by
the measured gain at each point in the control range.
The output-referred noise is a flat 60 nV/√Hz (postamp gain =
24 dB) over most of the gain range because it is dominated by
the fixed output-referred noise of the VGA. At the high end of
the gain control range, the noise of the LNA and of the source
prevail. The input-referred noise reaches its minimum value
near the maximum gain control voltage, where the input-
referred contribution of the VGA is miniscule.
At lower gains, the input-referred noise, and therefore, the noise
figure, increases as the gain decreases. The instantaneous
dynamic range of the system is not lost, however, because the
input capacity increases as the input-referred noise increases.
The contribution of the ADC noise floor has the same dependence.
The important relationship is the magnitude of the VGA output
noise floor relative to that of the ADC.
Gain control noise is a concern in very low noise applications.
Thermal noise in the gain control interface can modulate the
channel gain. The resultant noise is proportional to the output
signal level and is usually evident only when a large signal is
present. The gain interface includes an on-chip noise filter, which
significantly reduces this effect at frequencies above 5 MHz. Care
should be taken to minimize noise impinging at the GAIN±
inputs. An external RC filter can be used to remove VGAIN source
noise. The filter bandwidth should be sufficient to accommodate
the desired control bandwidth.
Antialiasing Filter
The filter that the signal reaches prior to the ADC is used to
reject dc signals and to band limit the signal for antialiasing.
Figure 53 shows the architecture of the filter.
The antialaising filter is a combination of a single-pole high-
pass filter and a second-order low-pass filter. The high-pass
filter can be configured at a ratio of the low-pass filter cutoff.
This is selectable through the SPI.
The filter uses on-chip tuning to trim the capacitors and in turn
set the desired cutoff frequency and reduce variations. The
default −3 dB low-pass filter cutoff is 1/3 or 1/4.5 the ADC
sample clock rate. The cutoff can be scaled to 0.7, 0.8, 0.9, 1, 1.1,
1.2, or 1.3 times this frequency through the SPI. The cutoff
tolerance is maintained from 8 MHz to 18 MHz.
30C
4C
30C
C
C = 0.8pF TO 5.1pF
n = 0 TO 7
10kΩ/n
0
7029-110
4kΩ
4kΩ
4kΩ
2kΩ
4kΩ
2kΩ
C
Figure 53. Simplified Filter Schematic
Tuning is normally off to avoid changing the capacitor settings
during critical times. The tuning circuit is enabled and disabled
through the SPI. Initializing the tuning of the filter must be
performed after initial power-up and after reprogramming
the filter cutoff scaling or ADC sample rate. Occasional
retuning during an idle time is recommended to compensate
for temperature drift.
There is a total of eight SPI-programmable settings that allow the
user to vary the high-pass filter cutoff frequency as a function
of the low-pass cutoff frequency. Two examples are shown in
Table 10: one is for an 8 MHz low-pass cutoff frequency and the
other is for an 18 MHz low-pass cutoff frequency. In both cases,
as the ratio decreases, the amount of rejection on the low-end
frequencies increases. Therefore, making the entire AAF
frequency pass band narrow can reduce low frequency noise or
maximize dynamic range for harmonic processing.
Table 10. SPI-Selectable High-Pass Filter Cutoff Options
High-Pass Cutoff
SPI Setting Ratio1
Low-Pass Cutoff
= 8 MHz
Low-Pass Cutoff
= 18 MHz
0 20.65 387 kHz 872 kHz
1 11.45 698 kHz 1.571 MHz
2 7.92 1.010 MHz 2.273 MHz
3 6.04 1.323 MHz 2.978 MHz
4 4.88 1.638 MHz 3.685 MHz
5 4.10 1.953 MHz 4.394 MHz
6 3.52 2.270 MHz 5.107 MHz
7 3.09 2.587 MHz 5.822 MHz
1 Ratio = low-pass filter cutoff frequency/high-pass filter cutoff frequency.
AD9272
Rev. C | Page 31 of 44
ADC
The AD9272 uses a pipelined ADC architecture. The quantized
output from each stage is combined into a 12-bit result in the
digital correction logic. The pipelined architecture permits the
first stage to operate on a new input sample and the remaining
stages to operate on preceding samples. Sampling occurs on the
rising edge of the clock.
The output staging block aligns the data, corrects errors, and
passes the data to the output buffers. The data is then serialized
and aligned to the frame and output clocks.
CLOCK INPUT CONSIDERATIONS
For optimum performance, the AD9272 sample clock inputs
(CLK+ and CLK−) should be clocked with a differential signal.
This signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or capacitors. These pins are biased internally
and require no additional bias.
Figure 54 shows the preferred method for clocking the AD9272.
A low jitter clock source, such as the Valpey Fisher oscillator
VFAC3-BHL-50 MHz, is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the secondary transformer limit clock excursions
into the AD9272 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD9272, and it preserves the
fast rise and fall times of the signal, which are critical to low
jitter performance.
0.1µF
0.1µF
0.1µF
0.1µF
SCHOTTKY
DIODES:
HSM2812
3.3V
50Ω100Ω
CLK–
CLK+
ADC
AD9272
MINI-CIRCUITS
ADT1-1WT, 1:1Z
XFMR
VFAC3
OUT
0
7029-050
Figure 54. Transformer-Coupled Differential Clock
If a low jitter clock is available, another option is to ac-couple a
differential PECL signal to the sample clock input pins as shown
in Figure 55. The AD951x family of clock drivers offers excellent
jitter performance.
100Ω
0.1µF
0.1µF
0.1µF
0.1µF
240Ω240Ω
AD951x FAMILY
50Ω
*
CLK
CLK
*
50Ω RESISTOR IS OPTIONAL.
CLK–
CLK+
ADC
AD9272
PECL DRIVER
3.3V
OUT
VFAC3
07029-051
Figure 55. Differential PECL Sample Clock
100Ω
0.1µF
0.1µF
0.1µF
0.1µF
AD951x FAMILY
50Ω
*
CLK
CLK
*
50Ω RESISTOR IS OPTIONAL.
CLK–
CLK+
ADC
AD9272
LVDS DRIVER
3.3V
OUT
VFAC3
07029-052
Figure 56. Differential LVDS Sample Clock
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be driven directly from a CMOS gate, and the
CLK− pin should be bypassed to ground with a 0.1 F capacitor
in parallel with a 39 kΩ resistor (see Figure 57). Although the
CLK+ input circuit supply is AVDDx (1.8 V), this input is
designed to withstand input voltages of up to 3.3 V, making the
selection of the drive logic voltage very flexible.
0.1µF
0.1µF
0.1µF
39kΩ
CMOS DRIVER
50Ω
*
OPTIONAL
100Ω
0.1µF
CLK
CLK
*
50Ω RESISTOR IS OPTIONAL.
CLK–
CLK+
ADC
AD9272
AD951x FAMILY
3.3
V
OUT
VFAC3
07029-053
Figure 57. Single-Ended 1.8 V CMOS Sample Clock
0.1µF
0.1µF
CMOS DRIVER
50Ω
*
OPTIONAL
100Ω
0.1µF
CLK
CLK
*
50Ω RESISTOR IS OPTIONAL.
CLK–
CLK+
ADC
AD9272
AD951x FAMILY
3.3
V
OUT
VFAC3
07029-054
0.1µF
Figure 58. Single-Ended 3.3 V CMOS Sample Clock
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to the clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic performance
characteristics. The AD9272 contains a duty cycle stabilizer (DCS)
that retimes the nonsampling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD9272. When the DCS is on, noise and distortion perfor-
mance are nearly flat for a wide range of duty cycles. However,
some applications may require the DCS function to be off. If so,
keep in mind that the dynamic range performance can be affected
when operated in this mode. See Table 17 for more details on
using this feature.
AD9272
Rev. C | Page 32 of 44
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately eight clock cycles
to allow the DLL to acquire and lock to the new rate.
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency (fA)
due only to aperture jitter (tJ) can be calculated by
SNR Degradation = 20 × log 10[1/2 × π × fA × tJ]
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter. IF undersampling applications
are particularly sensitive to jitter (see Figure 59).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9272.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources, such as the Valpey Fisher VFAC3 series.
If the clock is generated from another type of source (by gating,
dividing, or other methods), it should be retimed by the
original clock during the last step.
Refer to the AN-501 Application Note and the AN-756
Application Note for more in-depth information about how
jitter performance relates to ADCs (visit www.analog.com).
1 10 100 1000
16 BITS
14 BITS
12 BITS
30
40
50
60
70
80
90
100
110
120
130
0.125ps
0.5ps
1.0ps
2.0ps
ANALOG INPUT FREQUENCY (MHz)
10 BITS
8 BITS
RMS CLOCK JITTER REQUIREMENT
SNR (dB)
07029-038
0.25ps
Figure 59. Ideal SNR vs. Analog Input Frequency and Jitter
Power Dissipation and Power-Down Mode
As shown in Figure 61, the power dissipated by the AD9272 is
proportional to its sample rate. The digital power dissipation
does not vary much because it is determined primarily by the
DRVDD supply and bias current of the LVDS output drivers.
400
0
0
SAMPLING FREQUENCY (MSPS)
CURRENT (mA)
350
300
250
200
150
100
50
10 3020 40 50 60 70 80
07029-032
I
AVDD1
, 80MSPS SPEED GRADE
I
AVDD1
, 65MSPS SPEED GRADE
I
AVDD1
, 40MSPS SPEED GRADE
I
DRVDD
Figure 60. Supply Current vs. fSAMPLE for fIN = 5 MHz
220
170
0
SAMPLING FREQUENCY (MSPS)
POWER/CHANNEL (mW)
10 3020 5040 60 8070
215
210
205
200
195
190
185
180
175
07029-031
80MSPS SPEED GRADE
65MSPS SPEED GRADE
40MSPS SPEED GRADE
Figure 61. Power per Channel vs. fSAMPLE for fIN = 5 MHz
The AD9272 features scalable LNA bias currents (see Register 0x12
in Table 17). The default LNA bias current settings are high.
Figure 62 shows the typical reduction of AVDD2 current with
each bias setting. It is also recommended to adjust the LNA offset
using Register 0x10 in Table 17 when the LNA bias setting is low.
0 50 100 150 200 250 300 350 400
HIGH
LNA BIAS SETTIN
G
MID-HIGH
MID-LOW
LOW
TOTAL AVDD2 CURRENT (mA)
07029-119
Figure 62. AVDD2 Current at Different LNA Bias Settings, AD9272-40
AD9272
Rev. C | Page 33 of 44
By asserting the PDWN pin high, the AD9272 is placed into
power-down mode. In this state, the device typically dissipates
2 mW. During power-down, the LVDS output drivers are placed
into a high impedance state. The AD9272 returns to normal
operating mode when the PDWN pin is pulled low. This pin is
both 1.8 V and 3.3 V tolerant.
By asserting the STBY pin high, the AD9272 is placed into a
standby mode. In this state, the device typically dissipates
150 mW. During standby, the entire part is powered down
except the internal references. The LVDS output drivers are
placed into a high impedance state. This mode is well suited for
applications that require power savings because it allows the
device to be powered down when not in use and then quickly
powered up. The time to power this device back up is also greatly
reduced. The AD9272 returns to normal operating mode when
the STBY pin is pulled low. This pin is both 1.8 V and 3.3 V
tolerant.
In power-down mode, low power dissipation is achieved by
shutting down the reference buffer, PLL, and biasing networks.
The decoupling capacitors on VREF are discharged when
entering power-down mode and must be recharged when
returning to normal operation. As a result, the wake-up time is
related to the time spent in the power-down mode: shorter cycles
result in proportionally shorter wake-up times. To restore the
device to full operation, approximately 0.5 ms is required when
using the recommended 1 µF and 0.1 µF decoupling capacitors
on the VREF pin and 0.01 µF on the GAIN± pins. Most of this
time is dependent on the gain decoupling: higher value decoupling
capacitors on the GAIN± pins result in longer wake-up times.
There are a number of other power-down options available when
using the SPI port interface. The user can individually power
down each channel or put the entire device into standby mode.
This allows the user to keep the internal PLL powered up when fast
wake-up times are required. The wake-up time is slightly dependent
on gain. To achieve a 1 µs wake-up time when the device is in
standby mode, 0.8 V must be applied to the GAIN± pins. See
Table 17 for more details on using these features.
Digital Outputs and Timing
The AD9272 differential outputs conform to the ANSI-644 LVDS
standard on default power-up. This can be changed to a low power,
reduced signal option similar to the IEEE 1596.3 standard by
using Register 14, Bit 6 or via the SPI. This LVDS standard can
further reduce the overall power dissipation of the device by
approximately 36 mW.
The LVDS driver current is derived on chip and sets the output
current at each output equal to a nominal 3.5 mA. A 100 Ω differ-
ential termination resistor placed at the LVDS receiver inputs
results in a nominal 350 mV swing at the receiver.
The AD9272 LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs that have LVDS capability
for superior switching performance in noisy environments.
Single point-to-point net topologies are recommended with a
100 Ω termination resistor placed as close to the receiver as
possible. No far-end receiver termination and poor differential
trace routing may result in timing errors. It is recommended
that the trace length be no longer than 24 inches and that the
differential output traces be kept close together and at equal
lengths. An example of the FCO, DCO, and data stream with
proper trace length and position can be found in Figure 63.
07029-034
CH1 500mV/DIV = DCO
CH2 500mV/DIV = DATA
CH3 500mV/DIV = FCO
5.0ns/DIV
Figure 63. LVDS Output Timing Example in ANSI-644 Mode (Default)
An example of the LVDS output using the ANSI-644 standard
(default) data eye and a time interval error (TIE) jitter histogram
with trace lengths less than 24 inches on regular FR-4 material is
shown in Figure 64. Figure 65 shows an example of the trace
lengths exceeding 24 inches on regular FR-4 material. Notice
that the TIE jitter histogram reflects the decrease of the data eye
opening as the edge deviates from the ideal position; therefore,
the user must determine if the waveforms meet the timing budget
of the design when the trace lengths exceed 24 inches.
Additional SPI options allow the user to further increase the
internal termination (and therefore increase the current) of all
eight outputs in order to drive longer trace lengths (see Figure 66).
Even though this produces sharper rise and fall times on the
data edges, is less prone to bit errors, and improves frequency
distribution (see Figure 66), the power dissipation of the DRVDD
supply increases when this option is used.
In cases that require increased driver strength to the DCO± and
FCO± outputs because of load mismatch, Register 0x15 allows
the user to double the drive strength. To do this, set the appropriate
bit in Register 0x05. Note that this feature cannot be used with
Bit 4 and Bit 5 in Register 0x15 because these bits take precedence
over this feature. See Table 17 for more details.
AD9272
Rev. C | Page 34 of 44
07029-035
600
400
–200
200
–100
100
–400
–600
0
–1.5ns –0.5ns–1.0ns 0ns 0.5ns 1.0ns 1.5ns
EYE DIAGRAM VOLTAGE (V)
EYE: ALL BITS ULS: 2398/2398
25
0
5
10
15
20
–200ps –100ps 0ps 100ps 200ps
TIE JITTER HISTOGRAM (Hits)
Figure 64. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
of Less Than 24 Inches On Standard FR-4
07029-036
400
–300
300
–200
200
–100
100
–400
0
–1.5ns –0.5ns–1.0ns 0ns 0.5ns 1.0ns 1.5ns
EYE DIAGRAM VOLTAGE (V)
EYE: ALL BITS ULS: 2399/2399
25
0
5
10
15
20
–200ps –100ps 0ps 100ps 200ps
TIE JITTER HISTOGRAM (Hits)
Figure 65. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths
of Greater Than 24 Inches On Standard FR-4
AD9272
Rev. C | Page 35 of 44
600
–400
400
–200
200
–600
0
–1.5ns –0.5ns–1.0ns 0ns 0.5ns 1.0ns 1.5ns
EYE DIAGRAM VOLTAGE (V)
EYE: ALL BITS ULS: 2396/2396
25
0
5
10
15
20
–200ps –100ps 0ps 100ps 200ps
TIE JITTER HISTOGRAM (Hits)
07029-037
The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 11.
To change the output data format to twos complement, see the
Memory Map section.
Table 11. Digital Output Coding
Code
(VIN+) − (VIN−),
Input Span = 2 V p-p (V)
Digital Output Offset Binary
(D11...D0)
4095 +1.00 1111 1111 1111
2048 0.00 1000 0000 0000
2047 −0.000488 0111 1111 1111
0 −1.00 0000 0000 0000
Data from each ADC is serialized and provided on a separate
channel. The data rate for each serial stream is equal to 12 bits
times the sample clock rate, with a maximum of 960 Mbps
(12 bits × 80 MSPS = 960 Mbps). The lowest typical conversion
rate is 10 MSPS, but the PLL can be set up for encode rates as
low as 5 MSPS via the SPI if lower sample rates are required for
a specific application. See Table 17 for details on enabling this
feature.
Two output clocks are provided to assist in capturing data from
the AD9272. DCO± is used to clock the output data and is equal
to six times the sampling clock rate. Data is clocked out of the
AD9272 and must be captured on the rising and falling edges of
the DCO± that supports double data rate (DDR) capturing. The
frame clock output (FCO±) is used to signal the start of a new
output byte and is equal to the sampling clock rate. See the
timing diagram shown in Figure 2 for more information.
Figure 66. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω
Termination On and Trace Lengths of Greater Than 24 Inches on Standard FR-4
Table 12. Flexible Output Test Modes
Output Test Mode
Bit Sequence Pattern Name Digital Output Word 1 Digital Output Word 2
Subject to Data
Format Select
0000 Off (default) N/A N/A N/A
0001 Midscale short 1000 0000 0000 1000 0000 0000 Yes
0010 +Full-scale short 1111 1111 1111 1111 1111 1111 Yes
0011 −Full-scale short 0000 0000 0000 0000 0000 0000 Yes
0100 Checkerboard output 1010 1010 1010 0101 0101 0101 No
0101 PN sequence long N/A N/A Yes
0110 PN sequence short N/A N/A Yes
0111 One-/zero-word toggle 1111 1111 1111 0000 0000 0000 No
1000 User input Register 0x19 to Register 0x1A Register 0x1B to Register 0x1C No
1001 1-/0-bit toggle 1010 1010 1010 N/A No
1010 1× sync 0000 0011 1111 N/A No
1011 One bit high 1000 0000 0000 N/A No
1100 Mixed bit frequency 1010 0011 0011 N/A No
AD9272
Rev. C | Page 36 of 44
When using the serial port interface (SPI), the DCO± phase can
be adjusted in 60° increments relative to the data edge. This
enables the user to refine system timing margins if required.
The default DCO± timing, as shown in Figure 2, is 90° relative
to the output data edge.
An 8-, 10-, and 14-bit serial stream can also be initiated from
the SPI. This allows the user to implement different serial streams
and test the compatibility of the device, with lower and higher
resolution systems. When changing the resolution to an 8- or
10-bit serial stream, the data stream is shortened. When using
the 14-bit option, the data stream stuffs two 0s at the end of the
normal 14-bit serial data.
When using the SPI, all of the data outputs can also be inverted
from their nominal state. This is not to be confused with inverting
the serial stream to an LSB-first mode. In default mode, as shown
in Figure 2, the MSB is represented first in the data output serial
stream. However, this can be inverted so that the LSB is repre-
sented first in the data output serial stream (see Figure 3).
There are 12 digital output test pattern options available that
can be initiated through the SPI. This is a useful feature when
validating receiver capture and timing. Refer to Table 12 for the
output bit sequencing options available. Some test patterns have
two serial sequential words and can be alternated in various
ways, depending on the test pattern chosen. Note that some
patterns may not adhere to the data format select option. In
addition, user patterns can be assigned in the 0x19, 0x1A, 0x1B,
and 0x1C register addresses. All test mode options except PN
sequence short and PN sequence long can support 8- to 14-bit
word lengths in order to verify data capture to the receiver.
The PN sequence short pattern produces a pseudorandom
bit sequence that repeats itself every 29 − 1 bits or 511 bits. A
description of the PN sequence and how it is generated can be
found in Section 5.1 of the ITU-T 0.150 (05/96) standard. The
only difference is that the starting value is a specific value instead
of all 1s (see Table 13 for the initial values).
The PN sequence long pattern produces a pseudorandom bit
sequence that repeats itself every 223 − 1 bits or 8,388,607 bits. A
description of the PN sequence and how it is generated can be
found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The
only differences are that the starting value is a specific value
instead of all 1s, and the AD9272 inverts the bit stream with
relation to the ITU standard (see Table 13 for the initial values).
Table 13. PN Sequence
Sequence
Initial
Value
First Three Output Samples
(MSB First)
PN Sequence Short 0x0DF 0xDF9, 0x353, 0x301
PN Sequence Long 0x29B80A 0x591, 0xFD7, 0x0A3
Consult the Memory Map section for information on how to
change these additional digital output timing features through the
SPI.
SDIO Pin
This pin is required to operate the SPI. It has an internal 30 kΩ
pull-down resistor that pulls this pin low and is only 1.8 V
tolerant. If applications require that this pin be driven from a
3.3 V logic level, insert a 1 kΩ resistor in series with this pin to
limit the current.
SCLK Pin
This pin is required to operate the SPI port interface. It has an
internal 30 kΩ pull-down resistor that pulls this pin low and is
both 1.8 V and 3.3 V tolerant.
CSB Pin
This pin is required to operate the SPI port interface. It has an
internal 70 kΩ pull-up resistor that pulls this pin high and is both
1.8 V and 3.3 V tolerant.
RBIAS Pin
To set the internal core bias current of the ADC, place a resistor
nominally equal to 10 kΩ to ground at the RBIAS pin. Using
other than the recommended 10 kΩ resistor for RBIAS degrades
the performance of the device. Therefore, it is imperative that at
least a 1% tolerance on this resistor be used to achieve consistent
performance.
Voltage Reference
A stable and accurate 0.5 V voltage reference is built into the
AD9272. This is gained up internally by a factor of 2, setting
VREF to 1 V, which results in a full-scale differential input span
of 2 V p-p for the ADC. VREF is set internally by default, but the
VREF pin can be driven externally with a 1.0 V reference to
achieve more accuracy. However, this device does not support
ADC full-scale ranges below 2 V p-p.
When applying the decoupling capacitors to the VREF pin, use
ceramic low-ESR capacitors. These capacitors should be close to
the reference pin and on the same layer of the PCB as the AD9272.
The VREF pin should have both a 0.1 µF capacitor and a 1 µF
capacitor connected in parallel to the analog ground. These
capacitor values are recommended for the ADC to properly
settle and acquire the next valid sample.
The reference settings can be selected using the SPI. The settings
allow two options: using the internal reference or using an external
reference. The internal reference option is the default setting and
has a resulting differential span of 2 V p-p.
Table 14. SPI-Selectable Reference Settings
SPI-Selected Mode
Resulting
VREF (V)
Resulting Differential
Span (V p-p)
External Reference N/A 2 × external reference
Internal Reference (Default) 1 2
AD9272
Rev. C | Page 37 of 44
Power and Ground Recommendations
When connecting power to the AD9272, it is recommended
that two separate 1.8 V supplies be used: one for analog (AVDD)
and one for digital (DRVDD). If only one 1.8 V supply is
available, it should be routed to the AVDD1 first and then
tapped off and isolated with a ferrite bead or a filter choke
preceded by decoupling capacitors for the DRVDD. The user
should employ several decoupling capacitors on all supplies to
cover both high and low frequencies. These should be located
close to the point of entry at the PC board level and close to the
parts with minimal trace lengths.
A single PC board ground plane should be sufficient when
using the AD9272. With proper decoupling and smart parti-
tioning of the analog, digital, and clock sections of the PC
board, optimum performance can be easily achieved.
Exposed Paddle Thermal Heat Slug Recommendations
It is required that the exposed paddle on the underside of the
device be connected to a quiet analog ground to achieve the
best electrical and thermal performance of the AD9272. An
exposed continuous copper plane on the PCB should mate to
the AD9272 exposed paddle, Pin 0. The copper plane should
have several vias to achieve the lowest possible resistive thermal
path for heat dissipation to flow through the bottom of the PCB.
These vias should be filled or plugged with nonconductive epoxy.
To maximize the coverage and adhesion between the device and
PCB, partition the continuous copper pad by overlaying a silk-
screen or solder mask to divide it into several uniform sections.
This ensures several tie points between the two during the reflow
process. Using one continuous plane with no partitions only
guarantees one tie point between the AD9272 and PCB. See
Figure 67 for a PCB layout example. For more detailed infor-
mation on packaging and for more PCB layout examples, see
the AN-772 Application Note.
SILKSCREEN P
A
RTITION
PIN 1 INDICATOR
07029-069
Figure 67. Typical PCB Layout
AD9272
Rev. C | Page 38 of 44
SERIAL PORT INTERFACE (SPI)
The AD9272 serial port interface allows the user to configure
the signal chain for specific functions or operations through a
structured register space provided inside the chip. This offers
the user added flexibility and customization, depending on the
application. Addresses are accessed via the serial port and can
be written to or read from via the port. Memory is organized
into bytes that can be further divided down into fields, as doc-
umented in the Memory Map section. Detailed operational
information can be found in the Analog Devices, Inc., AN-877
Application Note, Interfacing to High Speed ADCs via SPI.
There are three pins that define the serial port interface or SPI.
They are the SCLK, SDIO, and CSB pins. The SCLK (serial
clock) is used to synchronize the read and write data presented
to the device. The SDIO (serial data input/output) is a dual-
purpose pin that allows data to be sent to and read from the
internal memory map registers of the device. The CSB (chip
select bar) is an active low control that enables or disables the
read and write cycles (see Table 15).
Table 15. Serial Port Pins
Pin Function
SCLK Serial clock. The serial shift clock input. SCLK is used to
synchronize serial interface reads and writes.
SDIO Serial data input/output. A dual-purpose pin. The typical
role for this pin is as an input or output, depending on
the instruction sent and the relative position in the
timing frame.
CSB Chip select bar (active low). This control gates the read
and write cycles.
The falling edge of the CSB pin in conjunction with the rising edge
of the SCLK determines the start of the framing sequence. During
an instruction phase, a 16-bit instruction is transmitted, followed
by one or more data bytes, which is determined by Bit Field W0
and Bit Field W1. An example of the serial timing and its
definitions can be found in Figure 69 and Table 16.
In normal operation, CSB is used to signal to the device that SPI
commands are to be received and processed. When CSB is brought
low, the device processes SCLK and SDIO to process instructions.
Normally, CSB remains low until the communication cycle is
complete. However, if connected to a slow device, CSB can be
brought high between bytes, allowing older microcontrollers
enough time to transfer data into shift registers. CSB can be stalled
when transferring one, two, or three bytes of data. When W0 and
W1 are set to 11, the device enters streaming mode and continues
to process data, either reading or writing, until CSB is taken
high to end the communication cycle. This allows complete
memory transfers without having to provide additional instruct-
tions. Regardless of the mode, if CSB is taken high in the middle
of any byte transfer, the SPI state machine is reset, and the device
waits for a new instruction.
In addition to the operation modes, the SPI port can be
configured to operate in different manners. For applications
that do not require a control port, the CSB line can be tied and
held high. This places the remainder of the SPI pins in their
secondary mode as defined in the SDIO Pin and SCLK Pin
sections. CSB can also be tied low to enable 2-wire mode. When
CSB is tied low, SCLK and SDIO are the only pins required for
communication. Although the device is synchronized during
power-up, caution must be exercised when using this mode to
ensure that the serial port remains synchronized with the CSB
line. When operating in 2-wire mode, it is recommended to use
a 1-, 2-, or 3-byte transfer exclusively. Without an active CSB
line, streaming mode can be entered but not exited.
In addition to word length, the instruction phase determines if
the serial frame is a read or write operation, allowing the serial
port to be used to both program the chip and read the contents
of the on-chip memory. If the instruction is a readback operation,
performing a readback causes the serial data input/output (SDIO)
pin to change direction from an input to an output at the
appropriate point in the serial frame.
Data can be sent in MSB- or LSB-first mode. MSB-first mode
is the default at power-up and can be changed by adjusting the
configuration register. For more information about this and
other features, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI.
HARDWARE INTERFACE
The pins described in Table 15 constitute the physical interface
between the programming device of the user and the serial port
of the AD9272. The SCLK and CSB pins function as inputs
when using the SPI interface. The SDIO pin is bidirectional,
functioning as an input during write phases and as an output
during readback.
In cases where multiple SDIO pins share a common connection,
care should be taken to ensure that proper VOH levels are met.
Figure 68 shows the number of SDIO pins that can be connected
together, assuming the same load as the AD9272 and the
resulting VOH level.
AD9272
Rev. C | Page 39 of 44
07029-113
NUMBER OF SDIO PINS CONNECTED TOGETHER
V
OH
(V)
1.715
1.720
1.725
1.730
1.735
1.740
1.745
1.750
1.755
1.760
1.765
1.770
1.775
1.780
1.785
1.790
1.795
1.800
0302010 40 50 60 70 80 90 100
Figure 68. SDIO Pin Loading
This interface is flexible enough to be controlled by either serial
PROMS or PIC mirocontrollers. This provides the user with
an alternative method, other than a full SPI controller, for
programming the device (see the AN-812 Application Note).
DON’T CARE
DON’T CAREDON’T CARE
DON’T CARE
SDIO
SCLK
CSB
t
S
t
DH
t
HI
t
CLK
t
LO
t
DS
t
H
R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0
07029-068
Figure 69. Serial Timing Details
Table 16. Serial Timing Definitions
Parameter Minimum Timing (ns) Description
tDS 5 Setup time between the data and the rising edge of SCLK
tDH 2 Hold time between the data and the rising edge of SCLK
tCLK 40 Period of the clock
tS 5 Setup time between CSB and SCLK
tH 2 Hold time between CSB and SCLK
tHI 16 Minimum period that SCLK should be in a logic high state
tLO 16 Minimum period that SCLK should be in a logic low state
tEN_SDIO 10 Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge (not shown in Figure 69)
tDIS_SDIO 10 Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK
rising edge (not shown in Figure 69)
AD9272
Rev. C | Page 40 of 44
MEMORY MAP
READING THE MEMORY MAP TABLE
Each row in the memory map table has eight address locations.
The memory map is roughly divided into three sections: the
chip configuration register map (Address 0x00 to Address 0x02),
the device index and transfer register map (Address 0x04 to
Address 0xFF), and the ADC functions register map (Address
0x08 to Address 0x2D).
The leftmost column of the memory map indicates the register
address number, and the default value is shown in the second
rightmost column. The Bit 7 (MSB) column is the start of the
default hexadecimal value given. For example, Address 0x09,
the clock register, has a default value of 0x01, meaning that Bit 7
= 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0,
and Bit 0 = 1, or 0000 0001 in binary. This setting is the default
for the duty cycle stabilizer in the on condition. When a 0 is
written to Bit 0 of this address followed by an 0x01 to the SW
transfer bit in Register 0xFF, the duty cycle stabilizer turns off. It
is important to follow each writing sequence with a write to the
SW transfer bit to update the SPI registers.
Caution
All registers except Register 0x00, Register 0x02, Register 0x04,
Register 0x05, and Register 0xFF are buffered with a master
slave latch and require writing to the transfer bit. For more
information on this and other functions, consult the AN-877
Application Note, Interfacing to High Speed ADCs via SPI.
RESERVED LOCATIONS
Undefined memory locations should not be written to except
when writing the default values suggested in this data sheet.
Addresses that have values marked as 0 should be considered
reserved and have a 0 written into their registers during power-up.
DEFAULT VALUES
After a reset, critical registers are automatically loaded with
default values. These values are indicated in Table 17, where an
X refers to an undefined feature.
LOGIC LEVELS
An explanation of various registers follows: “bit is set” is
synonymous with “bit is set to Logic 1” or “writing Logic 1 for
the bit.” Similarly, “clear a bit” is synonymous with “bit is set to
Logic 0” or “writing Logic 0 for the bit.”
AD9272
Rev. C | Page 41 of 44
Table 17. AD9272 Memory Map Register
Addr.
(Hex) Register Name
Bit 7
(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
(LSB)
Default
Value
Default Notes/
Comments
Chip Configuration Registers
00 Chip_port_config 0 LSB first
1 = on
0 = off
(default)
Soft
reset
1 = on
0 = off
(default)
1 1 Soft
reset
1 = on
0 = off
(default)
LSB first
1 = on
0 = off
(default)
0 0x18 The nibbles
should be
mirrored so that
LSB- or MSB-first
mode is set cor-
rectly regardless of
shift mode.
01 Chip_id Chip ID Bits[7:0]
(AD9272 = 0x2E, default)
Read
only
Default is unique
chip ID, different
for each device.
This is a read-only
register.
02 Chip_grade X X Child ID[5:4]
(identify device
variants of Chip ID)
00 = 40 MSPS
(default)
01 = 65 MSPS
10 = 80 MSPS
X X X X 0x00 Child ID used to
differentiate
graded devices.
Device Index and Transfer Registers
04 Device_index_2 X X X X Data
Channel
H
1 = on
(default)
0 = off
Data
Channel
G
1 = on
(default)
0 = off
Data
Channel
F
1 = on
(default)
0 = off
Data
Channel
E
1 = on
(default)
0 = off
0x0F Bits are set to
determine which
on-chip device
receives the next
write command.
05 Device_index_1 X X Clock
Channel
DCO±
1 = on
0 = off
(default)
Clock
Channel
FCO±
1 = on
0 = off
(default)
Data
Channel
D
1 = on
(default)
0 = off
Data
Channel
C
1 = on
(default)
0 = off
Data
Channel
B
1 = on
(default)
0 = off
Data
Channel
A
1 = on
(default)
0 = off
0x0F Bits are set to
determine which
on-chip device
receives the next
write command.
FF device_update X X X X X X X SW
transfer
1 = on
0 = off
(default)
0x00 Synchronously
transfers data
from the master
shift register to
the slave.
ADC Functions
08 Modes X X X X 0 Internal power-down mode
000 = chip run (default)
001 = full power-down
010 = standby
011 = reset
100 = CW mode (TGC PDWN)
0x00 Determines
various generic
modes of chip
operation
(global).
09 Clock X X X X X X X Duty
cycle
stabilizer
1 = on
(default)
0 = off
0x01 Turns the internal
duty cycle stabilizer
on and off
(global).
0D Test_io User test mode
00 = off (default)
01 = on, single
alternate
10 = on, single once
11 = on, alternate once
Reset PN
long
gen
1 = on
0 = off
(default)
Reset PN
short
gen
1 = on
0 = off
(default)
Output test mode—see Table 12
0000 = off (default)
0001 = midscale short
0010 = +FS short
0011 = −FS short
0100 = checkerboard output
0101 = PN sequence long
0110 = PN sequence short
0111 = one-/zero-word toggle
1000 = user input
1001 = 1-/0-bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency (format
determined by the output_mode register)
0x00 When this register
is set, the test data
is placed on the
output pins in
place of normal
data. (Local, expect
for PN sequence.)
AD9272
Rev. C | Page 42 of 44
Addr.
(Hex) Register Name
Bit 7
(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
(LSB)
Default
Value
Default Notes/
Comments
0F Flex_channel_input Filter cutoff frequency control
0000 = 1.3 × 1/3 × fSAMPLE
0001 = 1.2 × 1/3 × fSAMPLE
0010 = 1.1 × 1/3 × fSAMPLE
0011 = 1.0 × 1/3 × fSAMPLE (default)
0100 = 0.9 × 1/3 × fSAMPLE
0101 = 0.8 × 1/3 × fSAMPLE
0110 = 0.7 × 1/3 × fSAMPLE
1000 = 1.3 × 1/4.5 × fSAMPLE
1001 = 1.2 × 1/4.5 × fSAMPLE
1010 = 1.1 × 1/4.5 × fSAMPLE
1011 = 1.0 × 1/4.5 × fSAMPLE
1100 = 0.9 × 1/4.5 × fSAMPLE
1101 = 0.8 × 1/4.5 × fSAMPLE
1110 = 0.7 × 1/4.5 × fSAMPLE
X X X X 0x30 Antialiasing filter
cutoff (global).
10 Flex_offset X X 6-bit LNA offset adjustment
10 0000 for LNA bias high, mid-high, mid-low (default)
10 0001 for LNA bias low
0x20 LNA force offset
correction
(local).
11 Flex_gain X X X X PGA gain
00 = 21 dB
01 = 24 dB (default)
10 = 27 dB
11 = 30 dB
LNA gain
00 = 15.6 dB
01 = 17.9 dB
10 = 21.3 dB
(default)
0x06 LNA and PGA
gain adjustment
(global).
12 Bias_current X X X X 1 X LNA bias
00 = high (default)
01 = mid-high
10 = mid-low
11 = low
0x08 LNA bias current
adjustment
(global).
14 Output_mode X 0 = LVDS
ANSI-644
(default)
1 = LVDS
low power,
(IEEE
1596.3
similar)
X X X Output
invert
1 = on
0 = off
(default)
00 = offset binary
(default)
01 = twos
complement
0x00 Configures the
outputs and the
format of the data
(Bits[7:3] and
Bits[1:0] are global;
Bit 2 is local).
15 Output_adjust X X Output driver
termination
00 = none (default)
01 = 200 Ω
10 = 100 Ω
11 = 100 Ω
X X X DCO±
and
FCO±
2× drive
strength
1 = on
0 = off
(default)
0x00 Determines LVDS
or other output
properties.
Primarily functions
to set the LVDS
span and
common-mode
levels in place of
an external resistor
(Bits[7:1] are global;
Bit 0 is local).
16 Output_phase X X X X 0011 = output clock phase adjust
(0000 through 1010)
(Default: 180° relative to data edge)
0000 = 0° relative to data edge
0001 = 60° relative to data edge
0010 = 120° relative to data edge
0011 = 180° relative to data edge
0100 = 240° relative to data edge
0101 = 300° relative to data edge
0110 = 360° relative to data edge
0111 = 420° relative to data edge
1000 = 480° relative to data edge
1001 = 540° relative to data edge
1010 = 600° relative to data edge
1011 to 1111 = 660° relative to data edge
0x03 On devices that
use global clock
divide,
determines which
phase of the
divider output is
used to supply
the output clock.
Internal latching
is unaffected.
18 Flex_vref X 0 =
internal
reference
1 =
external
reference
X X X X X X 0x00 Select internal
reference
(recommended
default) or
external
reference
(global).
AD9272
Rev. C | Page 43 of 44
Addr.
(Hex) Register Name
Bit 7
(MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
Bit 0
(LSB)
Default
Value
Default Notes/
Comments
19 User_patt1_lsb B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined
pattern, 1 LSB
(global).
1A User_patt1_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined
pattern, 1 MSB
(global).
1B User_patt2_lsb B7 B6 B5 B4 B3 B2 B1 B0 0x00 User-defined
pattern, 2 LSB
(global).
1C User_patt2_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 User-defined
pattern, 2 MSB
(global).
21 Serial_control LSB first
1 = on
0 = off
(default)
X X X <10
MSPS,
low
encode
rate
mode
1 = on
0 = off
(default)
000 = 12 bits (default, normal
bit stream)
001 = 8 bits
010 = 10 bits
011 = 12 bits
100 = 14 bits
0x00 Serial stream
control. Default
causes MSB first
and the native bit
stream (global).
22 Serial_ch_stat X X X X X X Channel
output
reset
1 = on
0 = off
(default)
Channel
power-
down
1 = on
0 = off
(default)
0x00 Used to power
down individual
sections of a
converter (local).
2B Flex_filter X Enable
automatic
low-pass
tuning
1 = on
(self-
clearing)
X X High-pass filter cutoff
0000 = fLP/20.7
0001 = fLP/11.5
0010 = fLP/7.9
0011 = fLP/6.0
0100 = fLP/4.9
0101 = fLP/4.1
0110 = fLP/3.5
0111 = fLP/3.1
0x00 Filter cutoff
(global). (fLP =
low-pass filter
cutoff frequency.)
2C Analog_input X X X X X X LOSW-x connect
00 = high Z
01 = (−)LNA output
10 = (+)LNA output
11 = high Z
0x00 LNA active
termination/input
impedance
(global).
2D Cross_point_switch X X Crosspoint switch enable
10 0000 = CWD0± (differential)
10 0001 = CWD1± (differential)
10 0010 = CWD2± (differential)
10 0011 = CWD3± (differential)
10 0100 = CWD4± (differential)
10 0101 = CWD5± (differential)
10 0110 = CWD6± (differential)
10 0111 = CWD7± (differential)
11 0000 = CWD0+ (single-ended)
11 0001 = CWD1+ (single-ended)
11 0010 = CWD2+ (single-ended)
11 0011 = CWD3+ (single-ended)
11 0100 = CWD4+ (single-ended)
11 0101 = CWD5+ (single-ended)
11 0110 = CWD6+ (single-ended)
11 0111 = CWD7+ (single-ended)
11 1000 = CWD0− (single-ended)
11 1001 = CWD1− (single-ended)
11 1010 = CWD2− (single-ended)
11 1011 = CWD3− (single-ended)
11 1100 = CWD4− (single-ended)
11 1101 = CWD5− (single-ended)
11 1110 = CWD6− (single-ended)
11 1111 = CWD7− (single-ended)
0x xxxx = power down CW channel (default)
0x00 Crosspoint switch
enable (local).
AD9272
Rev. C | Page 44 of 44
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MS-026-AED-HD
1
25
26 50
76
100
75
51
14.00 BSC SQ
16.00 BSC SQ
0.75
0.60
0.45
1.20
MAX
1.05
1.00
0.95
0.20
0.09
0.08 MAX
COPLANARITY
VIEW A
ROTATED 90
°
CCW
SEATING
PLANE
0° MIN
7°
3.5°
0°
0.15
0.05
VIEW A
PIN 1
TOP VIEW
(PINS DOWN)
0.27
0.22
0.17
0.50 BSC
LEAD PITCH
1
25
2650
76 100
75
51
BOTTOM VIEW
(PINS UP)
9.50 SQ
EXPOSED
PAD
100908-A
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
Figure 70. 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]
(SV-100-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
Temperature
Range Package Description
Package
Option
AD9272BSVZ-801 −40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-100-3
AD9272BSVZRL-801 −40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] Tape and Reel SV-100-3
AD9272BSVZ-651 −40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-100-3
AD9272BSVZRL-651 −40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] Tape and Reel SV-100-3
AD9272BSVZ-401 −40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] SV-100-3
AD9272BSVZRL-401 −40°C to +85°C 100-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] Tape and Reel SV-100-3
AD9272-65EBZ1 Evaluation Board
AD9272-80KITZ1 Evaluation Board and High Speed FPGA-Based Data Capture Board
1 Z = RoHS Compliant Part.
©2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07029-0-7/09(C)
