2.7 V to 5.5 V, <100 µA, 14-Bit nanoDAC,
SPI Interface in LFCSP and SC70
Data Sheet
AD5641
Rev. D
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FEATURES
6-lead LFCSP and SC70 packages
Micropower operation: 100 µA maximum at 5 V
Power-down to typically 0.2 µA at 3 V
Single 14-bit DAC
B version: ±4 LSB INL
A version: ±16 LSB INL
2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to 0 V with brownout detection
3 power-down functions
Low power serial interface with Schmitt-triggered inputs
On-chip output buffer amplifier, rail-to-rail operation
SYNC interrupt facility
APPLICATIONS
Voltage level setting
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
The AD5641, a member of the nanoDAC® family, is a single,
14-bit, buffered, voltage-out DAC that operates from a single
2.7 V to 5.5 V supply, typically consuming 75 µA at 5 V. The
part comes in tiny LFCSP and SC70 packages. Its on-chip
precision output amplifier allows rail-to-rail output swing to be
achieved. The AD5641 uses a versatile 3-wire serial interface
that operates at clock rates up to 30 MHz and is compatible with
SPI®, QSPI™, MICROWIRE™, and DSP interface standards. The
reference for AD5641 is derived from the power supply inputs
and, therefore, gives the widest dynamic output range. The part
incorporates a power-on reset circuit, which ensures that the
DAC output powers up to 0 V and remains there until a valid
write to the device takes place.
The AD5641 contains a power-down feature that reduces
current consumption typically to 0.2 µA at 3 V, and provides
software-selectable output loads while in power-down mode.
The part is put into power-down mode over the serial interface.
The low power consumption of the part in normal operation
makes it ideally suited to portable battery-operated equipment.
The combination of small package and low power makes this
nanoDAC device ideal for level-setting requirements such as
generating bias or control voltages in space-constrained and
power-sensitive applications.
FUNCTIONAL BLOCK DIAGRAM
AD5641
V
DD
V
OUT
GND
POWER-ON
RESET
DAC
REGISTER 14-BIT
DAC
INPUT
CONTROL
LOGIC
POWER-DOWN
CONTROL LOGIC
OUTPUT
BUFFER
RESISTOR
NETWORK
REF(+)
SCLK SDIN
04611-001
SYNC
Figure 1.
Table 1. Related Devices
Part Number Description
AD5601 2.7 V to 5.5 V, <100 µA, 8-bit nanoDAC,
SPI interface in LFCSP and SC70 packages
AD5611 2.7 V to 5.5 V, <100 µA, 10-bit nanoDAC,
SPI interface in LFCSP and SC70 packages
AD5621 2.7 V to 5.5 V, <100 µA, 12-bit nanoDAC,
SPI interface in LFCSP and SC70 packages
PRODUCT HIGHLIGHTS
1. Available in space-saving 6-lead LFCSP and SC70
packages.
2. Low power, single-supply operation. The AD5641 operates
from a single 2.7 V to 5.5 V supply and with a maximum
current consumption of 100 µA, making it ideal for
battery-powered applications.
3. The on-chip output buffer amplifier allows the output of
the DAC to swing rail-to-rail with a typical slew rate of
0.5 V/µs.
4. Reference derived from the power supply.
5. High speed serial interface with clock speeds up to
30 MHz. Designed for very low power consumption. The
interface powers up only during a write cycle.
6. Power-down capability. When powered down, the DAC
typically consumes 0.2 µA at 3 V.
7. Power-on reset with brownout detection.
AD5641 Data Sheet
Rev. D | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Characteristics ................................................................ 4
Absolute Maximum Ratings ............................................................ 5
ESD Caution .................................................................................. 5
Pin Configuration and Function Descriptions ............................. 6
Typical Performance Characteristics ............................................. 7
Terminology .................................................................................... 12
Theory of Operation ...................................................................... 13
Digital-to-Analog Section ......................................................... 13
Resistor String ............................................................................. 13
Output Amplifier ........................................................................ 13
Serial Interface ............................................................................ 13
Input Shift Register .................................................................... 13
SYNC Interrupt .......................................................................... 13
Power-On Reset .......................................................................... 14
Power-Down Modes .................................................................. 14
Microprocessor Interfacing ....................................................... 15
Applications ..................................................................................... 16
Choosing a Reference as Power Supply for the AD5641....... 16
Bipolar Operation Using the AD5641 ..................................... 16
Using the AD5641 with a Galvanically Isolated Interface .... 17
Power Supply Bypassing and Grounding ................................ 17
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 19
REVISION HISTORY
2/12—Rev. C to Rev. D
Added 6-Lead LFCSP ......................................................... Universal
Changes to Title, Features Section, General Description Section,
Table 1, and Product Highlights Section, ...................................... 1
Changes to Table 4 ............................................................................ 5
Added Figure 4; Renumbered Sequentially .................................. 6
Changes to Table 5 ............................................................................ 6
Change to Choosing a Reference as Power Supply for the
AD5641 Section .............................................................................. 16
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 19
10/07—Rev. B to Rev. C
Added B Grade .................................................................... Universal
Changes to Offset Error and Gain Error Specifications .............. 3
Changes to Table 4 ............................................................................ 5
Changes to Typical Performance Characteristics ......................... 7
Changes to Ordering Guide .......................................................... 18
7/05—Rev. A to Rev. B
Change to Galvanically Isolated Interface Section ..................... 18
Changes to Figure 44 ...................................................................... 18
3/05—Rev. 0 to Rev. A
Changes to Timing Characteristics ................................................. 4
Changes to Absolute Maximum Ratings ........................................ 5
Changes to Full-Scale Error Section ............................................... 7
Changes to Figures 28 and 30 ....................................................... 12
Change to Resistor String Section ................................................ 13
Changes to Power-Down Mode Section ..................................... 14
1/05—Revision 0: Initial Version
Data Sheet AD5641
Rev. D | Page 3 of 20
SPECIFICATIONS
VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; −40°C < TA < +125°C; typical at +25°C; all specifications TMIN to TMAX,
unless otherwise noted.
Table 2.
A Grade B Grade
Parameter Min Typ Max Min Typ Max Unit Test Conditions/Comments
STATIC PERFORMANCE
Resolution 14 14 Bits
Relative Accuracy1 ±16 ±4 LSB
Differential Nonlinearity1 ±1 ±1 LSB Guaranteed monotonic by design
Zero-Code Error 0.5 10 0.5 10 mV All 0s loaded to DAC register
Offset Error ±0.63 ±10 ±0.63 ±10 mV
Full-Scale Error ±0.5 ±0.5 mV All 1s loaded to DAC register
Gain Error ±0.004 ±0.037 ±0.004 ±0.037 % of FSR
Zero-Code Error Drift 5.0 5.0 µV/°C
Gain Temperature Coefficient 2.0 2.0 ppm of
FSR/°C
OUTPUT CHARACTERISTICS
2
Output Voltage Range 0 VDD 0 VDD V
Output Voltage Settling Time 6 10 6 10 µs Code ¼ scale to ¾ scale, to ±1 LSB
Slew Rate 0.5 0.5 V/µs
Capacitive Load Stability 470 470 pF RL = ∞
1000 1000 pF RL = 2 kΩ
Output Noise Spectral Density 120 120 nV/√Hz DAC code = midscale, 1 kHz
Noise 2 2 µV DAC code = midscale, 0.1 Hz to
10 Hz bandwidth
Digital-to-Analog Glitch
Impulse
5 5 nV-s 1 LSB change around major carry
Digital Feedthrough 0.2 0.2 nV-s
DC Output Impedance 0.5 0.5 Ω
Short-Circuit Current 15 15 mA VDD = 3 V/5 V
LOGIC INPUTS
Input Current3 ±2 ±2 µA
VINL, Input Low Voltage 0.8 0.8 V VDD = 4.5 V to 5.5 V
0.6 0.6 V VDD = 2.7 V to 3.6 V
VINH, Input High Voltage 1.8 1.8 V VDD = 4.5 V to 5.5 V
1.4 1.4 V VDD = 2.7 V to 3.6 V
Pin Capacitance 3 3 pF
POWER REQUIREMENTS
VDD 2.7 5.5 2.7 5.5 V All digital inputs at 0 V or VDD
I
DD
(Normal Mode)
DAC active and excluding load current
VDD = 4.5 V to 5.5 V 75 100 75 100 µA VIH = VDD and VIL = GND
VDD = 2.7 V to 3.6 V 60 90 60 90 µA VIH = VDD and VIL = GND
IDD (All Power-Down Modes)
VDD = 4.5 V to 5.5 V 0.5 0.5 µA VIH = VDD and VIL = GND
V
DD
= 2.7 V to 3.6 V
0.2
0.2
µA
V
IH
= V
DD
and V
IL
= GND
POWER EFFICIENCY
IOUT/IDD 96 96 % ILOAD = 2 mA and VDD = ±5 V, full-scale
loaded
1 Linearity calculated using a reduced code range (Code 256 to Code 16,128).
2 Guaranteed by design and characterization, not production tested.
3 Total current flowing into all pins.
AD5641 Data Sheet
Rev. D | Page 4 of 20
TIMING CHARACTERISTICS
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. See Figure 2.
Table 3.
Parameter Limit1 Unit Test Conditions/Comments
t12 33 ns min SCLK cycle time
t2 5 ns min SCLK high time
t3 5 ns min SCLK low time
t4 10 ns min SYNC to SCLK falling edge setup time
t5 5 ns min Data setup time
t
6
4.5
ns min
Data hold time
t7 0 ns min SCLK falling edge to SYNC rising edge
t8 20 ns min Minimum SYNC high time
t9 13 ns min SYNC rising edge to next SCLK falling edge ignored
1 All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
2 Maximum SCLK frequency is 30 MHz.
t
4
t
3
t
2
t
5
t
7
t
6
D0D1D2D14D15
SYNC
SCLK
04611-002
t
9
t
1
t
8
D15 D14
SDIN
Figure 2. Timing Diagram
Data Sheet AD5641
Rev. D | Page 5 of 20
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter Rating
VDD to GND −0.3 V to +7.0 V
Digital Input Voltage to GND –0.3 V to VDD + 0.3 V
VOUT to GND –0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial –40°C to +125°C
Storage Temperature Range –65°C to +160°C
Maximum Junction Temperature
150°C
SC70 Package
θJA Thermal Impedance 433.34°C/W
θJC Thermal Impedance 149.47°C/W
LFCSP Package
θJA Thermal Impedance 95°C/W
Reflow Soldering
Peak Temperature 260°C
Time at Peak Temperature 20 sec to 40 sec
ESD 2.0 kV
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD5641 Data Sheet
Rev. D | Page 6 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD5641
TOP VIEW
(Not to Scale)
V
OUT
SYNC
16
GNDSCLK
25
SDIN V
DD
34
04611-003
Figure 3. 6-Lead SC70 Pin Configuration
04611-045
AD5641
TOP VIEW
(Not to Scale)
1V
DD
3SDIN
2
S
CLK
NOTES:
1. CONNECT THE EXPOSED PAD TO GND.
6V
OUT
4 SYNC
5GND
Figure 4. 6-Lead LFCSP Pin Configuration
Table 5. Pin Function Descriptions
SC70
Pin No.
LFCSP
Pin No. Mnemonic Description
1 4 SYNC Level-Triggered Control Input (Active Low). This is the frame synchronization signal for the input
data. When SYNC goes low, it enables the input shift register and data is transferred in on the falling
edges of the clocks that follow. The DAC is updated following the 16th clock cycle unless SYNC is
taken high before this edge, in which case the rising edge of SYNC acts as an interrupt and the write
sequence is ignored by the DAC.
2 2 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates up to 30 MHz.
3 3 SDIN Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling
edge of the serial clock input.
4 1 VDD Power Supply Input. The AD5641 can be operated from 2.7 V to 5.5 V. VDD should be decoupled to
GND.
5 5 GND Ground Reference Point for All Circuitry on the AD5641.
6 6 VOUT Analog Output Voltage from the DAC. The output amplifier has rail-to-rail operation.
EP Exposed Pad. Connect to GND.
Data Sheet AD5641
Rev. D | Page 7 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
–4
–3
–2
–1
0
1
2
3
4
256 2256 4256 6256 8256 10256 12256 14256
DAC CODE
INL ERRO R ( LSB)
VDD = VREF = 5V
TA = 25° C
04611-004
Figure 5. Typical INL
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
–40 –20 020 40 60 80 100 120 140
TEMPERATURE (°C)
INL ERRO R ( LSB)
MAX INL @ V
DD
= V
REF
= 5V
MAX INL @ V
DD
= V
REF
= 3V
MIN INL @ V
DD
= V
REF
= 5V
MIN INL @ V
DD
= V
REF
= 3V
04611-005
Figure 6. INL Error vs. Temperature (3 V/5 V Supply)
–5
–4
–3
–2
–1
0
1
2
3
4
5
2.7 3.2 3.7 4.2 4.7 5.2
INL ERROR (LSB)
TA = 25° C
SUPPLY (V)
04611-006
MAX INL ERROR
MIN INL ERROR
Figure 7. INL Error vs. Supply at 25°C
–8
–6
–4
–2
0
2
4
6
8
256 2256 4256 6256 8256 10256 12256 14256
DAC CODE
TUE E RROR (L S B)
°c
V
DD
= V
REF
= 5V
T
A
= 25° C
04611-007
Figure 8. Typical Total Unadjusted Error (TUE)
–14
–12
–10
–8
–6
–4
–2
0
–40 –20 020 40 60 80 100 120 140
TEMPERATURE (°C)
TUE ERROR (LSB)
MAX TUE ERROR @ VDD = VREF = 5V
MI N TUE ERROR @ VDD = VREF = 3V
MI N TUE ERROR @ VDD = VREF = 5V
MAX TUE ERROR @ VDD = VREF = 3V
04611-008
Figure 9. Total Unadjusted Error (TUE) vs. Temperature (3 V/5 V Supply)
–15
–10
–5
0
5
10
2.7 3.2 3.7 4.2 4.7 5.2
SUPPLY (V)
TUE E RROR (L S B)
TA = 25° C
04611-009
MAX TUE ERROR
MIN TUE ERROR
Figure 10. Total Unadjusted Error (TUE) vs. Supply at 25°C
AD5641 Data Sheet
Rev. D | Page 8 of 20
–0.0025
–0.0020
–0.0015
–0.0010
–0.0005
0
0.0005
0.0010
0.0015
0.0020
0.0025
–40 –20 020 40 60 80 100 120 140
TEMPERATURE (°C)
ERRO R ( V )
ZE RO-CO DE E RROR @ V
DD
= 5V
FULL- S CALE E RROR @ V
DD
= 5V
FULL- S CALE E RROR @ V
DD
= 3V
ZE RO-CO DE E RROR @ V
DD
= 3V
04611-010
Figure 11. Zero-Code/Full-Scale Error vs. Temperature (3 V/5 V)
–0.0020
–0.0015
–0.0010
–0.0005
0
0.0005
0.0010
0.0015
0.0020
2.7 3.2 3.7 4.2 4.7 5.2
SUPPLY (V)
ERRO R ( V )
TA = 25° C
FULL- S CALE E RROR
ZE RO-CO DE E RROR
04611-011
Figure 12. Zero-Code/Full-Scale Error vs. Supply at 25°C
–0.5
–0.4
–0.3
–0.2
–0.1
0
0.1
0.2
0.3
0.4
0.5
256 2256 4256 6256 8256 10256 12256 14256
DAC CODE
DNL ERROR (LSB)
V
DD
= 5V
T
A
= 25°C
04611-012
Figure 13. Typical DNL
–0.4
–0.3
–0.2
–0.1
0.1
0.2
0.3
0.4
0.5
0.6
–40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
DNL ERROR (LSB)
0
MAX DNL @ VDD = 5V
MIN DNL @ VDD = 5V
MAX DNL @ VDD = 3V
MIN DNL @ VDD = 3V
04611-013
Figure 14. DNL Error vs. Temperature (3 V/5 V)
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
2.7 3.2 3.7 4.2 4.7 5.2
SUPPLY (V)
DNL ERROR (LSB)
T
A
= 25°C
04611-014
MAX DNL ERROR
MIN DNL ERROR
Figure 15. DNL Error vs. Supply at 25°C
0
2
4
6
8
10
12
0.05456
0.05527
0.05599
0.05671
0.05742
0.05814
0.05885
0.06648
0.06710
0.06773
0.06835
0.06897
0.06960
0.07022
0.07084
0.07147
0.07209
0.07271
0.07334
I
DD
(mA)
NUMBER OF DEVICES
04611-015
V
DD
= 5V
V
IH
= DV
DD
V
IL
= GND
T
A
= 25°C
V
DD
= 3V
V
IH
= DV
DD
V
IL
= GND
T
A
= 25°C
Figure 16. IDD Histogram (3 V/5 V)
Data Sheet AD5641
Rev. D | Page 9 of 20
–1.6
–1.5
–1.4
–1.3
–1.2
–1.1
–1.0
–0.9
–0.8
–0.7
–0.6
–0.5
–0.4
–0.3
–0.2
–0.1
0
–40 –20 020 40 60 80 100 120 140
TEMPERATURE (°C)
OFF SET ERROR (mV)
04611-016
VDD = VREF = 5V
VDD = VREF = 3V
Figure 17. Offset Error vs. Temperature (3 V/5 V Supply)
–0.016
–0.014
–0.012
–0.010
–0.008
–0.006
–0.004
–0.002
0
–40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
GAIN ERROR (%FSR)
V
DD
= 3V
V
DD
= 5V
04611-017
Figure 18. Gain Error vs. Temperature (3 V/5 V)
0
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
–40 –20 0 20 40 60 80 100 120 140
TEMPERATURE (°C)
IDD (mA)
VDD = 3V
VDD = 5V
04611-018
Figure 19. Supply Current vs. Temperature (3 V/5 V Supply)
0
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
2.7 3.2 3.7 4.2 4.7 5.2
SUPPLY VOLTAGE (V)
I
DD
(mA)
T
A
= 25°C
0.01
04611-019
Figure 20. Supply Current vs. Supply Voltage at 25°C
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
–15 –10 –5 0 5 10 15
I ( mA)
ΔV
OUT
(V)
04611-020
DAC LOADED W IT H ZERO - S CALE CODE
VDD = 5V
TA = 25° C
DAC LOADED W IT H FULL-S CALE CO DE
Figure 21. Sink and Source Capability
0
10
20
30
40
50
60
70
02000 4000 6000 8000 10000 12000 14000 16000
DIGITAL INPUT CODE
I
DD
(µA)
V
DD
= 5V
V
DD
= 3V
04611-021
Figure 22. Supply Current vs. Digital Input Code
AD5641 Data Sheet
Rev. D | Page 10 of 20
CH1 = 5V/DIV CH2 = 1V/DIV TIME BASE = 2µs/DIV
CH1 = SCLK
CH2 = VOUT
04611-022
TA = 25°C
VDD = 5V
Figure 23. Full-Scale Settling Time
CH1 = 5V/DIV CH2 = 1V/DIV TIME BASE = 2µs/DIV
CH1 = SCLK
CH2 = V
OUT
T
A
= 25°C
V
DD
= 5V
04611-023
Figure 24. Midscale Settling Time
CH2
CH1
04611-024
VDD = 5V
TA = 25°C
VDD
VOUT = 70mV
CH1 1V, CH2 20mV, TIME BASE = 20µs/DIV
Figure 25. Power-On Reset to 0 V
CH1 1V, CH2 5V, TIME BASE = 50µs/DIV
CH2
CH1
04611-025
VDD
VOUT
VDD = 5V
TA = 25°C
Figure 26. VDD vs. VOUT
SAMPLE NUMBER
AMPLITUDE (V)
0 100 200 300 400 500
2.458
2.456
2.454
2.452
2.450
2.448
2.446
2.444
2.442
2.440
2.438
2.436
T
A
= 25°C
V
DD
= 5V
LOAD = 2kΩ AND 220pF
CODE 0x2000 TO 0x1FFF
10ns/SAMPLE NUMBER
04611-026
Figure 27. Digital-to-Analog Glitch Energy
04611-027
CH1
V
DD
= 5V
T
A
= 25°C
MIDSCALE LOADED
CH1 5µV/DIV
Figure 28. 1/f Noise, 0.1 Hz to 10 Hz Bandwidth
Data Sheet AD5641
Rev. D | Page 11 of 20
CH1 5V, CH2 1V, TIME BASE = 2µs/DIV
CH1
CH2
04611-028
V
DD
= 5V
T
A
= 25°C
V
OUT
Figure 29. Exiting Power-Down Mode
0
20
40
60
80
100
120
140
0 5 10 15 20 25
FREQUENCY (MHz)
I
DD
(A)
04611-029
3/4 SCALE
FULL SCALE
1/4 SCALE
MIDSCALE
ZERO SCALE
Figure 30. IDD vs. SCLK vs. Code
04611-030
0
100
200
300
400
500
600
700
100 1000 10000 100000
FREQUENCY (Hz)
OUTPUT NOISE SPECTRAL DENSITY (nV/ Hz)
FULL SCALE
ZERO SCALE
V
DD
= 5V
T
A
= 25°C
UNLOADED OUTPUT
MIDSCALE
Figure 31. Noise Spectral Density
0
50
100
150
200
250
300
350
400
450
0
V
LOGIC
(V)
I
DD
(A)
SCLK/SDIN
INCREASING
V
DD
= 3V
SCLK/SDIN DECREASING V
DD
= 3V
SCLK/SDIN
DECREASING
V
DD
= 5V
SCLK/SDIN
INCREASING
V
DD
= 5V
645321
T
A
= 25°C
04611-044
Figure 32. SCLK/SDIN vs. Logic Voltage
AD5641 Data Sheet
Rev. D | Page 12 of 20
TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer
function. See Figure 5 for a plot of typical INL vs. code.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. See Figure 13 for a plot of typical DNL vs. code.
Zero-Code Error
Zero-code error is a measure of the output error when zero
code (0x0000) is loaded to the DAC register. Ideally, the output
should be 0 V. The zero-code error is always positive in the
AD5641 because the output of the DAC cannot go below 0 V.
Zero-code error is due to a combination of the offset errors in
the DAC and output amplifier. Zero-code error is expressed in
mV. See Figure 11 for a plot of zero-code error vs. temperature.
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code (0xFFFF) is loaded to the DAC register. Ideally, the output
should be VDD − 1 LSB. Full-scale error is expressed in mV. See
Figure 11 for a plot of full-scale error vs. temperature.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from ideal,
expressed as a percent of the full-scale range.
Tota l Un adju sted Error (TUE)
Total unadjusted error is a measure of the output error taking
the various errors into account. See Figure 8 for a plot of typical
TUE vs. code.
Zero-Code Error Drift
Zero-code error drift is a measure of the change in zero-code
error with a change in temperature. It is expressed in μV/°C.
Gain Error Drift
Gain error drift is a measure of the change in gain error with
changes in temperature. It is expressed in (ppm of full-scale
range)/°C.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x2000 to 0x1FFF). See
Figure 27.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated.
It is specified in nV-s and is measured with a full-scale code
change on the data bus, that is, from all 0s to all 1s and vice versa.
Data Sheet AD5641
Rev. D | Page 13 of 20
THEORY OF OPERATION
DIGITAL-TO-ANALOG SECTION
The AD5641 DAC is fabricated on a CMOS process. The
architecture consists of a string DAC followed by an output
buffer amplifier. Figure 33 is a block diagram of the DAC
architecture.
V
DD
V
OUT
GND
RESISTOR
NETWORK
REF (+)
REF (–)
OUTPUT
AMPLIFIER
DAC REGISTER
04611-031
Figure 33. DAC Architecture
Because the input coding to the DAC is straight binary, the ideal
output voltage is given by
384,16
D
VV DD
OUT
where D is the decimal equivalent of the binary code that is
loaded to the DAC register; it can range from 0 to 16,384.
RESISTOR STRING
The resistor string structure is shown in Figure 34. It is simply a
string of resistors, each of value R. The code loaded to the DAC
register determines at which node on the string the voltage is
tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string
to the amplifier. Because it is a string of resistors, it is guaran-
teed monotonic.
R
R
R
R
RTO OUTPUT
AMPLIFIER
04611-032
Figure 34. Resistor String Structure
OUTPUT AMPLIFIER
The output buffer amplifier is capable of generating rail-to-rail
voltages on its output, giving an output range of 0 V to VDD. It is
capable of driving a load of 2 kΩ in parallel with 1000 pF to
GND. The source and sink capabilities of the output amplifier
can be seen in Figure 21. The slew rate is 0.5 V/μs, with a
midscale settling time of 8 μs with the output loaded.
SERIAL INTERFACE
The AD5641 has a 3-wire serial interface (SYNC, SCLK, and
SDIN) that is compatible with SPI, QSPI, and MICROWIRE
interface standards, as well as most DSPs. See Figure 2 for a
timing diagram of a typical write sequence.
The write sequence begins by bringing the SYNC line low. Data
from the SDIN line is clocked into the 16-bit shift register on
the falling edge of SCLK. The serial clock frequency can be as
high as 30 MHz, making the AD5641 compatible with high
speed DSPs. On the 16th falling clock edge, the last data bit is
clocked in and the programmed function is executed (a change
in DAC register contents and/or a change in the mode of
operation). At this stage, the SYNC line can be kept low or
brought high. In either case, it must be brought high for a
minimum of 20 ns before the next write sequence, so that a
falling edge of SYNC can initiate the next write sequence.
Because the SYNC buffer draws more current when VIN = 1.8 V
than it does when VIN = 0.8 V, SYNC should be idled low between
write sequences for even lower power operation of the part, as
previously mentioned. However, it must be brought high again
just before the next write sequence.
INPUT SHIFT REGISTER
The input shift register is 16 bits wide (see Figure 35). The first
two bits are control bits, which determine the operating mode
of the part (normal mode or any one of three power-down modes).
For a complete description of the various modes, see the Power-
Down Modes section. The next 14 bits are the data bits, which
are transferred to the DAC register on the 16th falling edge
of SCLK.
SYNC INTERRUPT
In a normal write sequence, the SYNC line is kept low for at
least 16 falling edges of SCLK and the DAC is updated on the
16th falling edge. However, if SYNC is brought high before the
16th falling edge, this acts as an interrupt to the write sequence.
The shift register is reset and the write sequence is seen as
invalid. Neither an update of the DAC register contents nor a
change in the operating mode occurs (see Figure 36).
AD5641 Data Sheet
Rev. D | Page 14 of 20
DATA BITS
DB15 (MSB) DB0 (LSB)
PD1 PD0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NORMAL OPERATION
1 kΩ TO GND
100 kΩ TO GND
THREE-STATE POWER-DOWN MODES
0
0
1
1
0
1
0
1
04611-033
Figure 35. Input Register Contents
04611-034
DB15 DB16 DB0DB0
INVALID WRITE SEQUENCE:
SYNC HIGH BEFORE 16
TH
FALLING EDGE VALID WRITE SEQUENCE, OUTPUT UPDATES
ON THE 16
TH
FALLING EDGE
SYNC
SCLK
SDIN
Figure 36. SYNC Interrupt Facility
POWER-ON RESET
The AD5641 contains a power-on reset circuit that controls the
output voltage during power-up. The DAC register is filled with
0s and the output voltage is 0 V. It remains there until a valid
write sequence is made to the DAC. This is useful in applica-
tions in which it is important to know the state of the DAC
output while it is in the process of powering up.
POWER-DOWN MODES
The AD5641 has four separate modes of operation. These
modes are software programmable by setting two bits (DB15
and DB14) in the control register. Table 6 shows how the state
of the bits corresponds to the operating mode of the device.
Table 6. Operating Modes for the AD5641
DB15 DB14 Operating Mode
0 0 Normal operation
Power-down mode:
0 1 1 kΩ to GND
1 0 100 kΩ to GND
1 1 Three-state
When both bits are set to 0, the part has normal power
consumption of 100 µA maximum at 5 V. However, for the
three power-down modes, the supply current falls to typically
0.2 µA at 3 V.
Not only does the supply current fall, but the output stage is
also internally switched from the output of the amplifier to a
resistor network of known values. This has the advantage that
the output impedance of the part is known while the part is in
power-down mode. There are three different options: the
output is connected internally to GND through either a 1 kΩ
resistor or a 100 kΩ resistor, or the output is left open-circuited
(three-stated). Figure 37 shows the output stage.
POWER-DOWN
CIRCUITRY RESISTOR
NETWORK
V
OUT
RESISTOR
STRING DAC AMPLIFIER
04611-035
Figure 37. Output Stage During Power-Down
The bias generator, output amplifier, resistor string, and other
associated linear circuitry are all shut down when power-down
mode is activated. However, the contents of the DAC register
are unaffected when in power-down. The time to exit power-
down is typically 13 µs for VDD = 5 V and 16 µs for VDD = 3 V.
See Figure 29 for a plot.
Data Sheet AD5641
Rev. D | Page 15 of 20
MICROPROCESSOR INTERFACING
AD5641 to ADSP-2101 Interface
Figure 38 shows a serial interface between the AD5641 and the
ADSP-2101. The ADSP-2101 should be set up to operate in
SPORT transmit alternate framing mode. The ADSP-2101
SPORT is programmed through the SPORT control register and
should be configured as follows: internal clock operation, active
low framing, and 16-bit word length. Transmission is initiated
by writing a word to the Tx register after the SPORT is enabled.
AD5641*
*ADDITIONAL PINS OMITTED FOR CLARITY
TFS
DT
SCLK
SYNC
SDIN
SCLK
04611-036
ADSP-2101*
Figure 38. AD5641 to ADSP-2101 Interface
AD5641 to 68HC11/68L11 Interface
Figure 39 shows a serial interface between the AD5641 and the
68HC11/68L11 microcontroller. SCK of the 68HC11/68L11
drives the SCLK of the AD5641, while the MOSI output drives
the serial data line of the DAC. The SYNC signal is derived
from a port line (PC7). The setup conditions for correct
operation of this interface are as follows: the 68HC11/68L11
should be configured so that the CPOL bit is 0 and the CPHA
bit is 1. When data is being transmitted to the DAC, the SYNC
line is taken low (PC7). When the 68HC11/68L11 are config-
ured as previously described, data appearing on the MOSI
output is valid on the falling edge of SCK. Serial data from the
68HC11/68L11 is transmitted in 8-bit bytes with only eight
falling clock edges occurring in the transmit cycle. Data is
transmitted MSB first. To load data to the AD5641, PC7 is left
low after the first eight bits are transferred and a second serial
write operation is performed to the DAC. PC7 is taken high at
the end of this procedure.
AD5641*
*ADDITIONAL PINS OMITTED FOR CLARITY
PC7
SCK
MOSI
SYNC
SCLK
SDIN
04611-037
68HC11/
68L11*
Figure 39. AD5641 to 68HC11/68L11 Interface
AD5641 to Blackfin® ADSP-BF53x Interface
Figure 40 shows a serial interface between the AD5641 and
the Blackfin ADSP-BF53x microprocessor. The ADSP-BF53x
processor family incorporates two dual-channel synchronous
serial ports, SPORT1 and SPORT0, for serial and multi-
processor communications. Using SPORT0 to connect to the
AD5641, the setup for the interface is as follows: DT0PRI drives
the SDIN pin of the AD5641, while TSCLK0 drives the SCLK of
the part. The SYNC is driven from TFS0.
ADSP-BF53x* AD5641*
*ADDITIONAL PINS OMITTED FOR CLARITY
DT0PRI
TSCLK0
TFS0
SDIN
SCLK
SYNC
04611-038
Figure 40. AD5641 to Blackfin ADSP-BF53x Interface
AD5641 to 80C51/80L51 Interface
Figure 41 shows a serial interface between the AD5641 and the
80C51/80L51 microcontroller. The setup for the interface is as
follows: TxD of the 80C51/80L51 drives SCLK of the AD5641,
while RxD drives the serial data line of the part. The SYNC
signal is again derived from a bit-programmable pin on the
port. In this case, Port Line P3.3 is used. When data is to be
transmitted to the AD5641, P3.3 is taken low.
The 80C51/80L51 transmits data only in 8-bit bytes; therefore,
only eight falling clock edges occur in the transmit cycle. To
load data to the DAC, P3.3 is left low after the first eight bits are
transmitted, and a second write cycle is initiated to transmit the
second byte of data. P3.3 is taken high following the completion
of this cycle. The 80C51/80L51 outputs the serial data LSB first.
The AD5641 requires its data with the MSB as the first bit
received. The 80C51/80L51 transmit routine should take this
into account.
80C51/80L51*
AD5641*
*ADDITIONAL PINS OMITTED FOR CLARITY
P3.3
TxD
RxD
SYNC
SCLK
SDIN
04611-039
Figure 41. AD5641 to 80C51/80L51 Interface
AD5641 to MICROWIRE Interface
Figure 42 shows an interface between the AD5641 and any
MICROWIRE-compatible device. Serial data is shifted out on
the falling edge of the serial clock and is clocked into the
AD5641 on the rising edge of SK.
MICROWIRE*
AD5641*
*ADDITIONAL PINS OMITTED FOR CLARITY
CS
SK
SO
SYNC
SCLK
SDIN
04611-040
Figure 42. AD5641 to MICROWIRE Interface
AD5641 Data Sheet
Rev. D | Page 16 of 20
APPLICATIONS
CHOOSING A REFERENCE AS POWER SUPPLY FOR
THE AD5641
The AD5641 comes in tiny LFCSP and SC70 packages with less
than 100 μA supply current. Because of this, the choice of refer-
ence depends on the application requirement. For space-saving
applications, the ADR02 is available in an SC70 package and
has excellent drift at 9 ppm/°C (3 ppm/°C in the R-8 package).
It also provides very good noise performance at 3.4 μV p-p in
the 0.1 Hz to 10 Hz range.
Because the supply current required by the AD5641 is
extremely low, the parts are ideal for low supply applications.
The ADR395 voltage reference is recommended in this case.
It requires less than 100 μA of quiescent current and can,
therefore, drive multiple DACs in one system, if required. It
also provides very good noise performance at 8 μV p-p in the
0.1 Hz to 10 Hz range.
AD5641
3-WIRE
SERIAL
INTERFACE
SYNC
SCLK
SDIN
7V
5V
V
OUT
= 0V TO 5V
ADR395
04611-041
Figure 43. ADR395 as Power Supply to AD5641
Table 7 lists some recommended precision references for use as
supplies to the AD5641.
Table 7. Precision References for Use with AD5641
Part No.
Initial
Accuracy
(mV max)
Temperature
Drift
(ppm/°C max)
0.1 Hz to 10 Hz
Noise (μV p-p typ)
ADR435 ±2 3 (R-8) 8
ADR425 ±2 3 (R-8) 3.4
ADR02 ±3 3 (R-8) 10
ADR02 ±3 3 (SC70) 10
ADR395 ±5 9 (TSOT-23) 8
BIPOLAR OPERATION USING THE AD5641
The AD5641 has been designed for single-supply operation,
but a bipolar output range is also possible using the circuit in
Figure 44. The circuit in Figure 44 gives an output voltage
range of ±5 V. Rail-to-rail operation at the amplifier output is
achievable using an AD820 or OP295 as the output amplifier.
R2 = 10k
04611-042
+5V
–5V
AD820/
OP295
3-WIRE
SERIAL
INTERFACE
+5V
AD5641
10F0.1FV
DD
V
OUT
R1 = 10k
+5V
Figure 44. Bipolar Operation with the AD5641
The output voltage for any input code can be calculated as
R1
R2
V
R1
R2R1D
VV DDDD
OUT 384,16
where D represents the input code in decimal (0 – 16384).
With VDD = 5 V, R1 = R2 = 10 kΩ,
V5
384,16
10
D
VOUT
This is an output voltage range of ±5 V with 0x0000 corre-
sponding to a –5 V output, and 0x3FFF corresponding to a
+5 V output.
Data Sheet AD5641
Rev. D | Page 17 of 20
USING THE AD5641 WITH A GALVANICALLY
ISOLATED INTERFACE
In process control applications in industrial environments, it
is often necessary to use a galvanically isolated interface to
protect and isolate the controlling circuitry from any hazardous
common-mode voltages that might occur in the area where
the DAC is functioning. iCoupler® provides isolation in excess
of 2.5 kV. The AD5641 use a 3-wire serial logic interface, so the
ADuM1300 three-channel digital isolator provides the required
isolation (see Figure 45). The power supply to the part also
needs to be isolated, which is done by using a transformer. On
the DAC side of the transformer, a 5 V regulator provides the
5 V supply required for the AD5641.
VDD
AD5641ADuM1300
POWER 10µF 0.1µF
GND
5V
REGULATOR
SCLKVOA
VOUT
VOB SYNC
VOC
VIA
VIB
VIC
SCLK
SDI
DATA SDIN
04611-043
Figure 45. AD5641 with a Galvanically Isolated Interface
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5641 should
have separate analog and digital sections, each having its own
area of the board. If the AD5641 is in a system where other
devices require an AGND-to-DGND connection, the
connection should be made at one point only. This ground
point should be as close as possible to the AD5641.
The power supply to the AD5641 should be bypassed with
10 µF and 0.1 µF capacitors. The capacitors should be physically
as close as possible to the device, with the 0.1 µF capacitor
ideally right up against the device. The 10 µF capacitors are
the tantalum bead type. It is important that the 0.1 µF capacitor
has low effective series resistance (ESR) and effective series
inductance (ESI), such as in common ceramic types of
capacitors. This 0.1 µF capacitor provides a low impedance
path to ground for high frequencies caused by transient
currents due to internal logic switching.
The power supply line itself should have as large a trace as
possible to provide a low impedance path and reduce glitch
effects on the supply line. Clocks and other fast switching
digital signals should be shielded from other parts of the board
by digital ground. Avoid crossover of digital and analog signals,
if possible. When traces cross on opposite sides of the board,
ensure that they run at right angles to each other to reduce
feedthrough effects on the board. The best board layout
technique is the microstrip technique, where the component
side of the board is dedicated to the ground plane only and the
signal traces are placed on the solder side. However, this is not
always possible with a 2-layer board.
AD5641 Data Sheet
Rev. D | Page 18 of 20
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-203-AB
0.22
0.08
0.30
0.10
0.30
0.15
1.00
0.90
0.70
SEATING
PLANE
4 5 6
3 2 1
PIN 1 0.65 BSC
1.30 BSC
0.10 MAX
0.10 COPLANARITY
0.40
0.10
1.10
0.80
2.20
2.00
1.80
2.40
2.10
1.80
1.35
1.25
1.15
Figure 46. 6-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-6)
Dimensions shown in millimeters
1.50
1.40
1.30
0.45
0.40
0.35
TOP VIEW
6
1
4
3
BOTTOM VIEW
PIN 1 INDEX
AREA
SEATING
PLANE
0.80
0.75
0.70
1.70
1.60
1.50
0.203 REF 0.05 MAX
0.00 MIN
0.65 REF
EXPOSED
PAD
PIN 1
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
10-18-2010-A
2.10
2.00
1.90
3.10
3.00
2.90
COMPLIANT
TO
JEDEC STANDARDS MO-229
COPLANARITY
0.08
0.20 MIN
0.35
0.30
0.25
Figure 47. 6-Lead Lead Frame Chip Scale Package [LFCSP_WD]
2.00 × 3.00 mm Body, Very Very Thin, Dual Lead
(CP-6-5)
Dimensions shown in millimeters
Data Sheet AD5641
Rev. D | Page 19 of 20
ORDERING GUIDE
Model1
Temperature
Range Description Package Description
Package
Option Branding
AD5641AKSZ-REEL7 –40°C to +125°C ±16 LSB INL 6-Lead Thin Shrink Small Outline Transistor
Package [SC70]
KS-6 D3Q
AD5641AKSZ-500RL7 –40°C to +125°C ±16 LSB INL 6-Lead Thin Shrink Small Outline Transistor
Package [SC70]
KS-6 D3Q
AD5641ACPZ-REEL7 –40°C to +125°C ±16 LSB INL 6-Lead Lead Frame Chip Scale Package
[LFCSP_WD]
CP-6-5 8A
AD5641BKSZ-REEL7 –40°C to +125°C ±4 LSB INL 6-Lead Thin Shrink Small Outline Transistor
Package [SC70]
KS-6 D3P
AD5641BKSZ-500RL7 –40°C to +125°C ±4 LSB INL 6-Lead Thin Shrink Small Outline Transistor
Package [SC70]
KS-6 D3P
1 Z = RoHS Compliant Part.
AD5641 Data Sheet
Rev. D | Page 20 of 20
NOTES
©2005–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04611-0-2/12(D)
