ATR2406 Low-IF 2.4-GHz ISM Transceiver DATASHEET Features Fully integrated low IF receiver Fully integrated GFSK modulator for 72, 144, 288, 576 and 1152Kbits/s High sensitivity of typically -93dBm due to integrated LNA High output power of typically +4dBm Multi-channel operation 95 channels Support frequency hopping (ETSI) and digital modulation (FCC) Supply-voltage range 2.9V to 3.6V (unregulated) Auxiliary voltage regulator on chip (3.2V to 4.6V) Low current consumption Few low-cost external components Integrated ramp-signal generator and power control for an additional power amplifier Low profile lead-free plastic package QFN32 (5mm x 5mm x 0.9mm) RoHs compliant Applications High-tech multi-user toys Wireless game controllers Telemetry Wireless audio/video Electronic point of sales Wireless head set FCC CFR47, part 15, ETSI EN 300 328, EN 300 440 and ARIB STD-T-66 compliant radio links 4779Q-ISM-09/14 1. Description The Atmel(R) ATR2406 is a single chip RF transceiver intended for applications in the 2.4GHz ISM band. The QFN32-packaged IC is a complete transceiver including image rejection mixer, low IF filter, FM demodulator, RSSI, TX preamplifier, power-ramping generator for external power amplifier, integrated synthesizer, and a fully integrated VCO and TX filter. No mechanical adjustment is necessary in production. The RF transceiver offers a clock recovery function on-chip. Figure 1-1. Block Diagram REG_DEC VREG REG_CTRL VS_REG IREF VS_SYN VREG_VCO VCO REG AUX REG AUX REG LNA IR-Mixer BP VS_IFD VS_IFA VS_RX/TX RX_IN LIMITER RSSI DEMOD RX_DATA RSSI PA VCO Divider by 2 TX_OUT BUS CLOCK DATA ENABLE TEST1 TEST2 RAMP_OUT RAMP GEN PLL PU_REG GAUSSIAN FILTER CTRL LOGIC PU_TRX RX_ON TX_ON nOLE CP 2 ATR2406 [DATASHEET] 4779Q-ISM-09/14 REF_CLK TX_DATA VTUNE Pin Configuration Table 2-1. TX_ON nOLE PU_TRX RX_DATA TX_DATA CLOCK DATA PENABLE Figure 2-1. Pinning QFN32 - 5 x 5 PU_REG 1 32 31 30 29 28 27 26 25 24 REF_CLK RSSI 2 23 IC 3 22 IC VS_IFD 4 21 RAMP_OUT VS_IFA 5 20 TX_OUT RX-CLOCK 6 19 RX_IN1 IC 7 18 RX_IN2 IREF 8 17 9 10 11 12 13 14 15 16 RX_ON VS_TRX VS_SYN CP VTUNE VREG_VCO REG_DEC VS_REG VREG ATR2406 REG_CTRL 2. Pin Description Pin Symbol Function 1 PU_REG Power-up input for auxiliary regulator 2 REF_CLK Reference frequency input 3 RSSI 4 VS_IFD Digital supply voltage 5 VS_IFA Analog supply voltage for IF circuits 6 RX-CLOCK 7 IC 8 IREF External resistor for band-gap reference 9 REG_CTRL Auxiliary voltage regulator control output Received signal strength indicator output RX-CLOCK, if RX mode with clock recovery is active Internally connected. Connect to VS if internal AUX regulator is not used 10 VREG 11 VS_REG Auxiliary voltage regulator output 12 REG_DEC 13 VREG_VCO 14 VTUNE 15 CP 16 VS_SYN Synchronous supply voltage 17 VS_TRX Transmitter receiver supply voltage 18 RX_IN2 Differential receiver input 2 19 RX_IN1 Differential receiver input 1 20 TX_OUT TX driver amplifier output 21 RAMP_OUT Ramp generator output for PA power ramping 22 IC Internally connected, do not connect on PCB 23 IC Internally connected, do not connect on PCB 24 RX_ON Auxiliary voltage regulator supply voltage Decoupling pin for VCO_REG VCO voltage regulator VCO tuning voltage input Charge-pump output RX control input ATR2406 [DATASHEET] 4779Q-ISM-09/14 3 Table 2-1. 4 Pin Description (Continued) Pin Symbol Function 25 TX_ON TX control input 26 NOLE Open loop enable input 27 PU_TRX RX/TX/PLL/VCO power-up input 28 RX_DATA RX data output 29 TX_DATA TX data input 30 CLOCK 3-wire-bus: Clock input 31 DATA 3-wire-bus: Data input 32 ENABLE Paddle GND ATR2406 [DATASHEET] 4779Q-ISM-09/14 3-wire-bus: Enable input Ground 3. Functional Description 3.1 Receiver The RF signal at RF_IN is differentially fed through the LNA to the image rejection mixer IR_MIXER, driving the integrated low-IF band-pass filter. The IF frequency is 864kHz. The limiting IF_AMP with an integrated RSSI function feeds the signal to the digital demodulator DEMOD. No tuning is required. Data slicing is handled internally. 3.2 Clock Recovery For a 1152Kbit/s data rate, the receiver has a clock recovery function on-chip. The receiver includes a clock recovery circuit which regenerates the clock out of the received data. The advantage is that this recovered clock is synchronous to the clock of the transmitting device (and thus to the transmitted data), which significantly reduces the load of the processing microcontroller. The falling edge of the clock is the optimal sampling position for the RX_Data signal, so at this event the data must be sampled by the microcontroller. The recovered clock is available at pin 6. 3.3 Transmitter The transmit data at TX_DATA is filtered by an integrated Gaussian filter (GF) and fed to the fully integrated VCO operating at twice the output frequency. After modulation, the signal is frequency divided by 2 and fed to the internal preamplifier PA. This preamplifier supplies typically +4dBm output power at TX_OUT. A ramp-signal generator RAMP_GEN, providing a ramp signal at RAMP_OUT for the external power amplifier, is integrated. The slope of the ramp signal is controlled internally so that spurious requirements are fulfilled. 3.4 Synthesizer The IR_MIXER, the PA, and the programmable counter (PC) are driven by the fully integrated VCO, using on-chip inductors and varactors. The output signal is frequency divided to supply the desired frequency to the TX_DRIVER, the 0/90 degree phase shifter for the IR_MIXER, and to be used by the PC for the phase detector (PD) (fPD = 1.728MHz). Open loop modulation is supported. 3.5 Power Supply An integrated band-gap-stabilized voltage regulator for use with an external low-cost PNP transistor is implemented. Multiple power-down and current saving modes are provided. ATR2406 [DATASHEET] 4779Q-ISM-09/14 5 4. Absolute Maximum Ratings Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Supply voltage auxiliary regulator Supply voltage Symbol Min. Max. Unit VS -0.3 +4.7 V VS -0.3 +3.6 V Vcontr -0.3 VS V Storage temperature Tstg -40 +125 C Input RF level PRF +10 dBm VESD_ana TBD V VESD_dig TBD V Control voltages ESD protection 5. Thermal Resistance Parameters Junction ambient 6. Symbol Value Unit RthJA 35 K/W Operating Range Parameters Supply voltage Auxiliary regulator supply voltage Symbol Min. Max. Unit VS 2.9 3.6 V VS_BATT 3.2 4.6 V Temperature ambient Tamb -10 +60 C Input frequency range fRX 2400 2483 MHz 6 ATR2406 [DATASHEET] 4779Q-ISM-09/14 7. Electrical Characteristics VS = 3.6V with AUX regulator, Tamb = 25C, unless otherwise specified No. 1 Parameters Test Conditions Symbol Min. Typ. Max. Unit Supply 1.1 Supply voltage With AUX regulator VS 3.2 3.6 4.6 V 1.2 Supply voltage Without AUX regulator VS 2.9 3.0 3.6 V 1.3 RX supply current CW mode (peak current) IS 57 mA Burst mode at 10Kbits/s(4) IS 625 A 1.4 TX supply current CW mode (peak current) IS 42 mA IS 500 A 1.5 Battery lifetime of a remote control application using an AVR(R) See Section 11. "Appendix: Current Calculations for a Remote Control" on page 21 1.6 Supply current in power-down mode With AUX regulator PU_TRX = 0; PU_REG = 0 IS <1 A 1.7 Supply current in power-down mode Without AUX regulator PU_TRX = 0; PU_REG = 0 IS <1 A 2 (4) Burst mode at 10Kbits/s Voltage Regulator 2.1 AUX regulator VREG 3.0 V 2.2 VCO regulator VREG_VCO 2.7 V 72/144/288/576/1152 kBits/s 3 Transmitter Part 3.1 TX data rate 3.2 Output power 3.3 TX data filter clock 9 taps in filter 3.4 Frequency deviation To be tuned by GFCS bits 3.5 Frequency deviation scaling(3) GFFM = GFFM_nom x GFCS (Refer to bus protocol D9 to D11) GFCS 3.6 Frequency drift With standard loop filter and slot length of 1400s (refer to the application note "ATR2406 Loop Filter and Data Rates") Dfo (drift) 3.7 Harmonics BW = 100kHz(1) 3.8 Spurious emissions 30 to 1000MHz 1 to 12.75GHz 1.8 to 1.9GHz 5.15 to 5.3GHz BW = 100kHz(1) PTX 4 dBm fTXFCLK 10.368/13.824 MHz GFFM_nom 400 kHz 4 Ramp Generator, Pin 21 4.1 Minimum output voltage TX_ON = low Vmin 4.2 Maximum output voltage Refer to bus protocol D12 to D13 Vmax 60 130 % 40 kHz -41.2 dBm -57 -57 -57 -57 dBm dBm dBm dBm 0.7 1.1 V 1.9 V 4.3 Rise time tr 5 s Notes: 1. Measured and guaranteed only on the Atmel(R) evaluation board, including microstrip filter, balun, and smart radio frequency (smart RF) firmware. Conducted measured. 2. Timing is determined by external loop filter characteristics. Faster timing can be achieved by modification of the loop filter. For further information refer to the application notes. 3. The Gaussian filter control setting (GFCS) is used to compensate production tolerances by tuning the modulation deviation in production to the nominal value of 400kHz. 4. Burst mode with 0.9% duty cycle ATR2406 [DATASHEET] 4779Q-ISM-09/14 7 7. Electrical Characteristics (Continued) VS = 3.6V with AUX regulator, Tamb = 25C, unless otherwise specified No. Parameters 4.4 Fall time 5 5.1 Test Conditions Symbol Min. Typ. Max. Unit tf 5 s Zin 170 + j0 -93 dBm -15 dBm Receiver Part RX input impedance 5.2 Sensitivity 5.3 Third order input intercept point Differential -3 At input for BER 10 at 1152Kbits/s(1) IIP3 5.4 Intermodulation rejection BER < 10-3, wanted at -83dBm, level of interferers in channels N + 2 and N + 4(1) 5.5 Co-channel rejection BER < 10-3, wanted at -76dBm(1) RCO -11 dBc 5.6 Adjacent channel rejection 1.728MHz BER < 10-3, wanted at -76dBm, adjacent level referred to wanted channel level(1) Ri (N - 1) 14 dBc 5.7 Bi-adjacent channel rejection 3.456MHz BER < 10-3, wanted at -76dBm, bi-adjacent level referred to wanted channel level(1) Ri (N - 2) 30 dBc 5.8 Rejection with 3 channels separation 5.128MHz BER < 10-3, wanted at -76dBm, n 3 adjacent level referred to wanted channel level(1) Ri (n 3) 40 dBc 5.9 Out of band rejection > 6MHz BER < 10-3, wanted at -83dBm at 2.45GHz(1) Bldf>6MHz 38 dBc Out of band rejection 5.10 2300MHz to 2394MHz 2506MHz to 2600GHz BER < 10-3, wanted at -83dBm at 2.45GHz(1) Blnear 47 dBc Out of band rejection 5.11 30MHz to 2300MHz 2600MHz to 6GHz BER < 10-3, wanted at -83dBm at 2.45GHz(1) Blfar 57 dBc 6 32 dBc RSSI Part 6.1 Maximum RSSI output voltage 6.2 RSSI output voltage, monotonic With -33dBm at RF input over range -96dBm to -36dBm With -96dBm at RF input 7 IM3 Under high RX input signal level VRSSImax 2.1 V VRSSI 1.9 0.1 V V VCO 7.1 Oscillator frequency defined at TX output 7.2 Frequency control voltage range Over full temperature range(1) VVTUNE 2400 2483 MHz 0.5 VCC - 0.5 V VCO tuning input gain defined GVCO 240 MHz/V at TX output Notes: 1. Measured and guaranteed only on the Atmel(R) evaluation board, including microstrip filter, balun, and smart radio frequency (smart RF) firmware. Conducted measured. 7.3 2. Timing is determined by external loop filter characteristics. Faster timing can be achieved by modification of the loop filter. For further information refer to the application notes. 3. The Gaussian filter control setting (GFCS) is used to compensate production tolerances by tuning the modulation deviation in production to the nominal value of 400kHz. 4. Burst mode with 0.9% duty cycle 8 ATR2406 [DATASHEET] 4779Q-ISM-09/14 7. Electrical Characteristics (Continued) VS = 3.6V with AUX regulator, Tamb = 25C, unless otherwise specified No. Parameters 8 Synthesizer Test Conditions Symbol Min. Typ. Max. 8.1 External reference input frequency D7 = 0 D7 = 1 REF_CLK 8.2 Sinusoidal input signal level (peak-to-peak value) AC-coupled sine wave REF_CLK 8.3 Scaling factor prescaler SPSC 32/33 - 8.4 Scaling factor main counter SMC 86/87/88/89 - 8.5 Scaling factor swallow counter SSC 9 10.368 13.824 Unit 500 1000 0 31 mVPP - Phase Detector 9.1 Phase detector comparison frequency 10 Charge-pump Output fPD 1728 kHz mA 10.1 Charge-pump output current VCP = 1/2 VCC ICP 2 10.2 Leakage current VCP = 1/2 VCC IL 100 11 MHz MHz 1000 pA Timing Conditions(1)(2) 11.1 Transmit to receive time Reference clock stable TX RX time 200 s 11.2 Receive to transmit time Reference clock stable RX TX time 200 s 11.3 Channel switch time Reference clock stable CS time 200 s 11.4 Power down to transmit Reference clock stable PD TR time 250 s 11.5 Power down to receive Reference clock stable PD RX time 200 s 11.6 Programming register Reference clock stable PRR time 3 s 11.7 PLL settling time Reference clock stable PLL set time 200 s 12 Interface Logic Input and Output Signal Levels, Pin DATA, CLOCK, ENABLE 12.1 HIGH-level input voltage Logic 1 VIH 1.4 3.1 V 12.2 LOW-level input voltage Logic 0 VIL -0.3 +0.4 V 12.3 HIGH-level output voltage Logic 1 VOH 3.1 V 12.4 LOW-level output voltage Logic 0 VOL 0 12.5 Input bias current Logic 1 or logic 0 Ibias -5 V +5 A 12.6 3-wire bus clock frequency fCLKmax 10 MHz Notes: 1. Measured and guaranteed only on the Atmel(R) evaluation board, including microstrip filter, balun, and smart radio frequency (smart RF) firmware. Conducted measured. 2. Timing is determined by external loop filter characteristics. Faster timing can be achieved by modification of the loop filter. For further information refer to the application notes. 3. The Gaussian filter control setting (GFCS) is used to compensate production tolerances by tuning the modulation deviation in production to the nominal value of 400kHz. 4. Burst mode with 0.9% duty cycle ATR2406 [DATASHEET] 4779Q-ISM-09/14 9 8. PLL Principle Figure 8-1. PLL Principle Programmable counter PC "- Main counter MC "- Swallow counter SC fCVO = 1728kHz x (SMC x 32 + SSC) External loop filter PA driver Phase frequency detector (PD) fPD = 1728kHz Charge pump Divide by 2 VCO Mixer Gaussian filter (GF) Reference counter (RC) REF_CLK D7 10.368MHz 0 13.824MHz 1 TXDAT PLL reference frequency REF_CLK Baseband controller Table 8-1 shows the LO frequencies for RX and TX in the 2.4-GHz ISM band. There are 95 channels available. Since the ATR2406 supports wideband modulation with 400-kHz deviation, every second channel can be used without overlap in the spectrum. Table 8-1. LO Frequencies Mode fIF/kHz TX RX 10 864 ATR2406 [DATASHEET] 4779Q-ISM-09/14 Channel fANT/MHz fVCO/MHz divided by 2 SMC SSC N C0 2401.056 2401.056 86 27 2779 C1 2401.920 2401.920 86 28 2780 ... ... ... ... ... ... C93 2481.408 2481.408 89 24 2872 C94 2482.272 2482.272 89 25 2873 C0 2401.056 2401.920 86 28 2780 C1 2401.920 2402.784 86 29 2781 ... ... ... ... ... ... C93 2481.408 2482.272 89 25 2873 C94 2482.272 2483.136 89 26 2874 8.1 TX Register Setting The following 16-bit word has to be programmed for TX. MSB LSB Data bits D15 D14 0 1 D13 D12 D11 PA D10 D9 GFCS D8 D7 1 RC D6 D5 D4 D3 MC D2 D1 D0 SC Note: D12 and D13 are only relevant if ramping generator in conjunction with external PA is used, otherwise it can be programmed 0 or 1. Table 8-2. Output Power Settings with Bits D12 - D13 PA (Output Power Settings) D13 D12 RAMP_OUT (Pin 21) 0 0 1.3V 0 1 1.35V 1 0 1.4V 1 1 1.75V The VRAMP voltage is used to control the output power of an external power amplifier. The voltage ramp is started with the TX_ON signal. These bits are only relevant in TX mode. 8.2 RX Register Setting There are two RX settings possible. For a data rate of 1152kBits/s, an internal clock recovery function is implemented. 8.3 Register Setting Without Clock Recovery Must be used for data rates below 1.152Mbits/s. MSB LSB Data bits D15 D14 D13 D12 D11 D10 D9 D8 D7 0 1 X X X X X 0 RC Note: D6 D5 MC D4 D3 D2 D1 D0 SC X values are not relevant and can be set to 0 or 1. ATR2406 [DATASHEET] 4779Q-ISM-09/14 11 8.4 RX Register Setting with Internal Clock Recovery Recommended for 1.152Mbit/s data rate. The output pin of the recovered clock is pin 6. The falling edge of the recovered clock signal samples the data signal. MSB Data bits D24 D23 D22 D21 D20 D19 D18 D17 D16 1 0 1 0 0 0 0 0 0 LSB Data bits D15 D14 D13 D12 D11 D10 D9 D8 D7 0 0 X X X X X 0 RC Note: 8.5 D6 D5 D4 D3 MC D2 D1 D0 SC X values are not relevant and can be set to 0 or 1. PLL Settings RC, MC and SC bits control the synthesizer frequency as shown in Table 8-3, Table 8-4 on page 12 and Table 8-5 on page 13. Formula for calculating the frequency: TX frequency: fANT = 864kHz x (32 x SMC + SSC) RX frequency: fANT = 864kHz x (32 x SMC + SSC - 1) Table 8-3. PLL Settings of the Reference Counter Bit D7 RC (Reference Counter) Table 8-4. D7 CLK Reference 0 10.368MHz 1 13.824MHz PLL Settings of the Main Counter Bits D5 to D6 MC (Main Counter) 12 D6 D5 SMC 0 0 86 0 1 87 1 0 88 1 1 89 ATR2406 [DATASHEET] 4779Q-ISM-09/14 Table 8-5. PLL Settings of the Swallow Counter Bits D0 to D4 SC (Swallow Counter) 8.6 D4 D3 D2 D1 D0 SSC 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 2 ... ... ... ... ... ... 1 1 1 0 1 29 1 1 1 1 0 30 1 1 1 1 1 31 GFCS Adjustment The Gaussian filter control setting (GFCS) is used to compensate for production tolerances by tuning the modulation deviation in production to the nominal value of 400kHz. These bits are only relevant in TX mode. Table 8-6. GFCS Adjustment of Bits D9 - D11 GFCS 8.7 D11 D10 D9 GFCS 0 0 0 60% 0 0 1 70% 0 1 0 80% 0 1 1 90% 1 0 0 100% 1 0 1 110% 1 1 0 120% 1 1 1 130% Control Signals The various transceiver functions are activated by the following control signals. A timing proposal is shown in Figure 8-3 on page 15. Table 8-7. Control Signals and Functions Signal Functions PU_REG Activates AUX voltage regulator and the VCO voltage regulator supplying the complete transceiver PU_TRX Activates RX/TX blocks RX_ON Activates RX circuits: DEMOD, IF AMP, IR MIXER TX_ON Activates TX circuits: PA, RAMP GEN, Starts RAMP SIGNAL at RAMP_OUT NOLE Disables open loop mode of the PLL ATR2406 [DATASHEET] 4779Q-ISM-09/14 13 8.8 Serial Programming Bus The transceiver is programmed by the SPI (CLOCK, DATA and ENABLE). After setting the enable signal to low, the data is transferred bit by bit into the shift register on the rising edge of the clock signal, starting with the MSBit. When the enable signal has returned to high, the programmed information is active. Additional leading bits are ignored and there is no check made of how many clock pulses arrived during enable low. The programming of the transceiver is done by a 16-bit or 25-bit data word (for the RX clock recovery mode). 8.9 3-wire Bus Timing Figure 8-2. 3-wire Bus Protocol Timing Diagram DATA CLOCK ENABLE TL TPER TS TC TEC TT TH Table 8-8. 3-wire Bus Protocol Table Description Symbol Minimum Value Unit Clock period TPER 100 ns Set time data to clock TS 20 ns Hold time data to clock TH 20 ns Clock pulse width TC 60 ns Set time enable to clock TL 100 ns Hold time enable to data TEC 0 ns TT 250 ns Time between two protocols 14 ATR2406 [DATASHEET] 4779Q-ISM-09/14 connected to RAMP_IN of optional PA RAMP_OUT Pin 21 RSSI Pin 3 Signals to TRX (Input) RX_DATA Pin 28 TX_ON Pin 25 RX_ON Pin 24 REF_CLK Pin 2 nOLE Pin 26 3W_ENA Pin 32 3W_DATA Pin 31 3W_CLK Pin 30 TX_DATA Pin 29 PU_REG Pin 1 PU_TRX Pin 27 Pin name MODE Note: Power up Power down 16/25 bits > 50s C4 Valid signal Active RX slot REF_CLK > 200s Programming C3 C1 Power down optional 1. Keep input signals at low level during power-down state of TRX > 40s C2 C1 > 40s Power up optional C2 16 bits C5 Data > 50s Active TX slot REF_CLK > 200s Preamble (1-0-1-0) Programming C3 Power down C1 0V VS 0V VS Figure 8-3. Example TX and RX Timing Diagram TRX (Output) Signals from ATR2406 [DATASHEET] 4779Q-ISM-09/14 15 Table 8-9. Description of the Conditions/States Condition 8.10 Description C1 Power down ATR2406 is switched off and the supply current is lower than 1A. C2 Power up ATR2406 is powered up by toggling PU_REG and PU_TRX to high. PU_REG enables the external AUX regulator transistor including VCO regulator. PU_TRX enables internal blocks like the PLL and the VCO. Depending on the value of the external capacitors (for example, at the AUX regulator, if one is used), it is necessary to wait at least 40s until the different supply voltages have settled. C3 Programming The internal register of the ATR2406 is programmed via the three-wire interface. At TX, this is just the PLL (transmit channel) and the deviation (Gaussian filter). At RX, this is just the PLL (receive channel) and, if the clock recovery is used, also the bits to enable this option. At the start of the three-wire programming, the enable signal is toggled from high to low to enable clocking the data into the internal register. When the enable signal rises again to high, the programmed data is latched. This is the time point at which the settling of the PLL starts. It is necessary to wait the settling time of 200s so that the VCO frequency is stable. The reference clock needs to be applied to ATR2406 for at least the time when the PLL is in operation, which is the programming state (C3) and the active slot (C4, C5). Out of the reference clock, several internal signals are also derived, for example, the Gaussian filter circuitry and TX_DATA sampling. C4 This is the receive slot where the transmit burst is received and data as well as recovered clock are available. C5 This is the active transmit slot. As soon as TX_DATA is applied to ATR2406, the signal nOLE toggles to low which enables modulation in open-loop mode. The preamble (1-0-1-0 pattern) should start being sent at the start of TX_ON. Received Signal Strength Indication (RSSI) The RSSI is given as an analog voltage at the RSSI pin. A typical plot of the RSSI value is shown in Figure 8-4. Figure 8-4. Typical RSSI Value versus Input Power 2.5 RSSI Level (V) 2.0 1.5 1.0 0.5 0 -130 -110 -90 -70 -50 RF Level (dBm) 16 ATR2406 [DATASHEET] 4779Q-ISM-09/14 -30 -10 10 9. Application Circuit The Atmel(R) ATR2406 requires only a few low-cost external components for operation. A typical application is shown in Figure 9-3 on page 18. Typical Application Circuit Figure 9-1. Microcontroller Interfacing with General Purpose MCU, Pin Connections between Microcontroller and ATR2406 ATR2406 RF-DATA Interface Microcontroller TX_DATA RX_DATA RX-CLOCK ENABLE CLOCK DATA Configuration and control 9.1 XTAL (1) Ctrl_Lines REF_CLK XTAL_OUT Figure 9-2. Example with AVR MCU AVR_MCU ATR2406 USART RF_DATA TXD TX_DATA RXD RX_DATA XCK GPIO GPIO2 GPIO3 GPIO4 GPIO5 13.824MHz XTAL 1. RX-CLOCK RF_CTRL GPIO1 Note: R ENABLE CLOCK DATA nOLE TX_ON RX_ON PU_REG PU_TRX RSSI REF_CLK XTAL: for example, XRFBCC-NANL; 13.824MHz, 10ppm Order at: Taitien Electronic, Taitien Specific No.: A009-x-B26-3, SMD ATR2406 [DATASHEET] 4779Q-ISM-09/14 17 NC RX_DATA J17 J18 J19 J20 J21 ENABLE DATA nOLE PU_REG RX_CLOCK GND SMASI J2 NC 2 4 6 8 10 12 14 16 18 20 22 24 26 28 R1 C3 J24 1 3 5 7 9 11 13 15 17 19 21 23 25 27 1.8pF C7 Microstrip Low-passfilter R5 1.5k 2.2pF C6 1.8pF Slug 1.5k GND3 J3 GND1 GND6 REF_CLK 1.5pF RSSI J10 C10 RX_ON Microstrip VBATT TX_ON TX_DATA PU_TRX C9 J9 R6 2.2pF J8 R2 J4 J5 J6 J7 Select integrated F antenna or SMA connector by setting the 0 resistor RFOUT (Ant) ANT J12 J13 J14 J15 J16 GND CLOCK ANT VBATT F antenna ANT2 J11 Figure 9-3. Application Circuit for ATR2406-DEV-BOARD GND5 IC2P GND4 GND GND9 GND8 VBATT Microstrip balun C1 5.6pF GND7 GND2 Microstrip RAMP_OUT TP1 TP2 RX_ON J26 C14 24 23 22 21 20 19 18 17 R4 25 26 27 28 29 30 31 32 nOLE PU_TRX RX_DATA TX_DATA CLOCK PU_TRX RX_DATA TX_DATA CLOCK DATA ENABLE 1k C4 G GND VS_SYN CP VTUNE VREG_VCO REG_DEC VS_REG VREG REG_CTRL 390pF 16 15 14 13 12 11 10 9 RAMP C21 C18 NC C17 2.2nF 68pF C19 470nF 1 2 3 4 5 6 7 8 ENABLE 22nF C20, C21, COG dielectric PU_REG REF_CLK RSSI VS_IFD VS_IFA RX_CLOCK IC IREF DATA TX_ON nOLE ATR2416 TX_ON NC RX_ON IC IC RAMP_OUT TX_OUT RX_IN1 RX_IN2 VS_TRX IC2 C20 R3 C29 62k 4.7nF PU_REG C11 18pF RSSI RX_CLOCK 18 ATR2406 [DATASHEET] 4779Q-ISM-09/14 T1 BC808 C24 REF_CLK 4.7pF J2 C16 C15 C12 C13 4.7F 100nF 100nF 4.7F VS 10. PCB Layout Design Figure 10-1. PCB Layout ATR2406-DEV-BOARD ATR2406 [DATASHEET] 4779Q-ISM-09/14 19 Table 10-1. Bill of Materials Part Value Part Number Vendor Package C1 5.6pF 0402 C3, C10 1.8pF 0402 C4 390pF 0402 C5 4.7pF 0402 C6, C7 2.2pF 0402 C9 1.5pF 0402 C11 18pF 0402 C12, C15 100nF Comment NC 0402 3216 Optional(2) 1nF 0402 NC C17 3.3nF 0402 NC C18 68pF 0402 C19 470nF 0402/0603 C13, C16 4.7F C14 B45196H2475M109 Epcos (R) C20 22nF, COG GRM21B5C1H223JA01 Murata 0805 COG, important for good RF performance C21 2.2nF, COG GRM1885C1H222JA01 Murata 0603 COG, important for good RF performance C23 4.7nF C24 4.7pF R3 62k 62k, 5% 0402 R4 1.0k 1k0, 5% 0402 R5 1.5k 1k5, 5% 0402 Ref_Clk level, optional(1) R6 1.5k 1k5, 5% 0402 Ref_Clk level, optional(1) IC2 ATR2406 ATR2406 T1 BC808-40 MSUB FR4 Notes: 0402 0402 Atmel BC808-40, any standard type can be used, but it is important that be "-40"! (R) Vishay , Philips(R), etc. MLF32 Optional(2) SOT-23 FR4, e_r = 4.4 at 2.45GHz, H = 500m, T = 35m, tand = 0.02, surface, that is, chem. tin or chem. gold 1. Not necessary if supplied RefClk level is within specification range 2. If no AUX regulator is used, then T1 and C16 can be removed and a jumper is needed from the collector to the emitter pad. Additionally, pin 7 of the ATR2406 has to be connected to pin 4 or pin 5 to use the integrated F antenna, set jumper R2 (0R resistor 0603) Table 10-2. Parts Count Bill of Materials 20 Parts Count Required (Minimal BOM) Optional (Depending on Application) Capacitors 0402 14 14 Capacitors >0402 2 4 Resistors 0402 2 2 Inductors 0402 - - Semiconductors 1 2 ATR2406 [DATASHEET] 4779Q-ISM-09/14 11. Appendix: Current Calculations for a Remote Control Assumptions: Protocol A data packet consists of 24 bytes. 24 bytes = 240bits (USART connection) Tpacket_length = 210s at 1.152Mbits/s Channel The system will use five predefined channels for frequency hopping spread spectrum (FHSS) which gives improved immunity against interferers Loop filter Loop filter settling time will be 110s Handheld device If not in use, the handheld device will be in power-down mode with the AVR(R) watchdog timer disabled. The AVR power-down current is typically 1.25A. If an external voltage regulator is used, additional power-down current has to be taken into account Base station device The base station will periodically scan all the channels of the used subset. The base station will stay on one channel for 2 seconds. If the base station receives a correct packet, an acknowledge will be returned to the handheld device. The power consumption of the base station device is not power-sensitive, as this part of the application is normally mains powered Basic Numbers: Peak current ATR2406 in TX at 1.152Kbits/s 42mA Peak current ATR2406 in RX at 1.152Kbits/s 57mA Peak current ATR2406 with synthesizer running 26mA Current ATmega88 active 5mA Current ATmega88 power down (no WDT) 1.25A Current ATmega88 power down (+ WDT) 5A Loop settling time of ATR2406 110s Configuration of ATR2406 30s Time needed for exchanging a packet at 1.152Kbits/s 210s Amount of Current Needed to Transmit One Packet: Q1 = (0.005A + 0.026A) x 5030s = 155As (charge up time ATR2406 + AVR internal calculations) Q2 = (0.005A + 0.026A) x 30s = 0.93As (charge for configuring the ATR2406) Q3 = (0.005A + 0.026A) x 110s = 3.41As (charge for settling the loop filter) Q4 = (0.005A + 0.042A) x 210s = 9.87As (charge for transmitting the packet) Q5 = (0.005A) 250 s = 1.25As (charge for turn around (TX to RX, RX to TX, etc.)) Q6 = (0.005A + 0.026A) x 30s = 0.93As (charge for configuring the ATR2406) Q7 = (0.005A + 0.026A) x 60s = 1.86As (charge for settling the loop filter) Q8 = (0.005A + 0.057A) x 50s = 3.10 As (charge until valid data can be received) Q9 = (0.005A + 0.057A) x 210s = 13.02As (charge for receiving the packet) Q10 = (0.005A + 0.057A) x 50s = 3.1As (charge for latency before receiving) ATR2406 [DATASHEET] 4779Q-ISM-09/14 21 A successful packet exchange needs the following charge Q = Q1 + Q2 + Q3 + Q4 + Q5 + Q6 + Q7 + Q8 + Q9 + Q10 = 192.47As As the described system is a FHSS system with 5 different channels, the system has to do this up to five times before the packet is acknowledged by the base station. The average will be 2.5 times. In the case of an interfered environment, some more retries may be required; therefore, it is assumed the factor will be 3. The power-up time is included only once, as the cycle will be completed without powering up and down the handheld in order to be as power efficient as possible. Average current needed for a packet exchange: 155As + (37.5As x 3) = 267.5As If the device will be used 1000 times a day 3.1A Average current in active mode: System power down current: Current ATmega88: Current ATR2406: Current VREG (+ ShutDown): 1.25A 1.0A 2.75A Assumed average power-down current is 5A. Overall power consumption is 8.1A It is assumed the system uses a small battery with a capacity of 100mAh. This is 100.000Ah. Battery lifetime will be around: 12345 hours = 514 days = 1.4 years. The most important factor is to get the power-down current as low as possible! Example: Assume a system where the handheld is used just 10 times per day. Iactive = 0.031A and assuming the power-down current of this device is just 4 A. I = 0.031A + 4A = 4.03A Battery lifetime will be around 24807 hours = 1033 days = 2.83 years. Power-down current is the main factor influencing the battery lifetime. 22 ATR2406 [DATASHEET] 4779Q-ISM-09/14 Ordering Information Extended Type Number Package ATR2406-PNQW MOQ Taped and reeled, Pb-free 6000 Package Information Top View D 32 1 technical drawings according to DIN specifications E PIN 1 ID 8 A1 Dimensions in mm A Side View Bottom View D2 9 16 17 E2 8 1 Z 24 32 e 25 COMMON DIMENSIONS (Unit of Measure = mm) Z 10:1 L 13. QFN32 - 5x5 Remarks A3 12. b Symbol MIN NOM MAX A 0.8 0.85 0.9 A1 A3 0 0.16 0.035 0.21 0.05 0.26 D 4.9 5 5.1 D2 3.5 3.6 3.7 E 4.9 5 5.1 E2 3.5 3.6 3.7 L 0.35 0.4 0.45 b e 0.2 0.25 0.5 0.3 NOTE 05/20/14 TITLE Package Drawing Contact: packagedrawings@atmel.com Package: QFN_5x5_32L Exposed pad 3.6x3.6 GPC DRAWING NO. REV. 6.543-5203.01-4 1 ATR2406 [DATASHEET] 4779Q-ISM-09/14 23 14. Recommended Footprint/Landing Pattern Figure 14-1. Recommenced Footprint/Landing Pattern Table 14-1. Recommended Footprint/Landing Pattern Signs 24 ATR2406 [DATASHEET] 4779Q-ISM-09/14 Sign Size A 3.2mm B 1.2mm C 0.3mm a 1.1mm b 0.3mm c 0.2mm d 0.55mm e 0.5mm 15. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. 4779Q-ISM-09/14 History * Section 11 "Ordering Information" on page 23 updated * Section 12 "Package Information" on page 23 updated 4779P-ISM-09/14 * Section 11 "Ordering Information" on page 23 updated 4779O-ISM-03/14 * Put datasheet in the latest template 4779N-ISM-12/08 4779M-ISM-02/07 * Put datasheet in the latest template * Section 12 "Package Information" on page 22 updated * Put datasheet in the latest template * Table 9-1 "Bill of Materials" on page 19 updated * Table "Electrical Characteristics" on pages 6 to 8 updated 4779L-ISM-08/06 * Section 10 "Appendix: Current calculations for a remote control" on pages 20 to 21 updated * Table "Ordering Information" on page 22 updated * Minor corrections to grammar and style throughout document * Put datasheet in a new template * Table "Electrical Characteristics" on pages 6 to 8 updated 4779K-ISM-06/06 * Section 10 "Appendix: Current calculations for a remote control" on pages 20 to 21 added * Ordering information on page 22 updated ATR2406 [DATASHEET] 4779Q-ISM-09/14 25 XXXXXX Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com (c) 2014 Atmel Corporation. / Rev.: Rev.: 4779Q-ISM-09/14 Atmel(R), Atmel logo and combinations thereof, Enabling Unlimited Possibilities(R), AVR(R), and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. 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