OP07DP - National Semiconductor

TL/H/10550

OP-07 Low Offset, Low Drift Operational Amplifier

December 1994

OP-07 Low Offset, Low Drift Operational Amplifier

General Description

The OP-07 has very low input offset voltage which is ob-

tained by trimming at the wafer stage. These low offset volt-

ages generally eliminate any need for external nulling. The

OP-07 also features low input bias current and high open-

loop gain. The low offsets and high open-loop gain make

the OP-07 particularly useful for high-gain applications.

The wide input voltage range of g13V minimum combined

with high CMRR of 110 dB and high input impedance pro-

vide high accuracy in the non-inverting circuit configuration.

Excellent linearity and gain accuracy can be maintained

even at high closed-loop gains.

Stability of offsets and gain with time or variation in temper-

ature is excellent.

The OP-07 is available in TO-99 metal can, ceramic or

molded DIP.

For improved specifications, see the LM607.

Features

YLow VOS 75 mV Max

YLow VOS Drift 0.6 mV/§C Max

YUltra-Stable vs Time 1.0 mV/Month Max

YLow Noise 0.6 mVp-p Max

YWide Input Voltage Range g14V

YWide Supply Voltage Range g3V to g18V

YFits 725/108A/308A, 741, AD510 Sockets

YReplaces the mA714

Applications

YStrain Gauge Amplifiers

YThermocouple Amplifiers

YPrecision Reference Buffer

YAnalog Computing Functions

Connection Diagram

Dual-In-Line Package

TL/H/10550–1

See NS Package Number N08E

Ordering Information

TAe25§CN08E Operating

VOSMax Plastic Temperature

(mV) Range

75 OP07EP COM

150 OP07CP COM

150 OP07DP COM

*Also available per SMD Ý8203602

C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.

Absolute Maximum Ratings

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

Supply Voltage g22V

Internal Power Dissipation (Note 5) 500 mW

Differential Input Voltage g30V

Input Voltage (Note 6) g22V

Output Short-Circuit Duration Continuous

Storage Temperature Range b65§Ctoa

150§C

Lead Temperature (Soldering, 60 sec.) 260§C

Junction Temperature b65§Ctoa

150§C

Operating Temperature Range

OP-07E, OP-07C, OP-07D 0§Ctoa

70§C

Simplified Schematic

TL/H/10550–3

*R2A and R2B are electronically trimmed on chip at the factory for minimum offset voltage.

Electrical Characteristics

Unless otherwise specified, VSeg15V, TAe25§C. Boldface type refers to limits over 0§CsTAs70§C

Symbol Parameter Conditions OP-07E OP-07C Units

Min Typ Max Min Typ Max

VOS Input Offset Voltage (Note 1) 30 75 60 150 mV

45 130 85 250

VOS/t Long-Term VOS (Note 2) 0.3 1.5 0.4 2.0 mV/Mo

Stability

IOS Input Offset Current 0.5 3.8 0.8 6.0 nA

0.9 5.3 1.6 8.0

IBInput Bias Current g1.2 g4.0 g1.8 g7.0 nA

g1.5 g5.5 g2.2 g9.0

enp-p Input Noise Voltage 0.1 Hz to 10 Hz (Note 3) 0.35 0.6 0.38 0.65 mVp-p

enInput Noise Voltage fOe10 Hz 10.3 18.0 10.5 20.0

Density fOe100 Hz (Note 3) 10.0 13.0 10.2 13.5 nV/0Hz

fOe1000 Hz 9.6 11.0 9.8 11.5

inp-p Input Noise Current 0.1 Hz to 10 Hz (Note 3) 14 30 15 35 pAp-p

inInput Noise Current fOe10 Hz 0.32 0.80 0.35 0.90

Density fOe100 Hz (Note 3) 0.14 0.23 0.15 0.27 pA/0Hz

fOe1000 Hz 0.12 0.17 0.13 0.18

RIN Input Resistance (Note 4) 15 50 8 33 MX

Differential-Mode

RINCM Input Resistance 160 120 GX

Common-Mode

IVR Input Voltage Range g13.0 g14.0 g13 g14 V

CMRR Common-Mode VCM eg13V 106 123 100 120 dB

Rejection Ratio 103 123 97 120

PSRR Power Supply VSeg3V to g18V 5 20 7 32 mV/V

Rejection Ratio VSeg3V to g18V 732 1051

VO Large Signal RLt2kX,V

Oeg

10V 200 500 120 400

Voltage Gain RLt2kX180 450 100 400 V/mV

RLt500X,V

Oeg

0.5V, 150 400 100 400

VSeg3V (Note 4)

VOOutput Voltage Swing RLt10 kXg12.5 g13.0 g12.0 g13.0

RLt2kXg

12.0 g12.8 g11.5 g12.8 V

RLt2kXg

12.0 g12.6 g11.0 g12.6

RLt1kXg

10.5 g12.0 g12.0

SR Slew Rate RLt2kX(Note 3) 0.1 0.3 0.1 0.3 V/ms

BW Closed-Loop Bandwidth AVCL ea

1 (Note 3) 0.4 0.6 0.4 0.6 MHz

ROOutput Resistance VOe0, IOe060 60X

Power Consumption VSeg15V, No Load 75 120 80 150 mW

VSeg3V, No Load 4 6 4 8

Offset Adj. Range RPe20 kXg4g4mV

TCVOS Average Input Offset (Note 4) 0.3 1.3 0.5 1.8

Voltage Drift Without mV/§C

External Trim

TCVOSn With External Trim RPe20 kX(Note 4) 0.3 1.3 0.4 1.6

TCIOS Average Input Offset (Note 3) 835 1250pA/§C

Current Drift

TCIBAverage Input Bias (Note 3) 13 35 18 50 pA/§C

Current Drift

Electrical Characteristics

Unless otherwise specified, VSeg15V, TAe25§C. Boldface type refers to limits over 0§CsTAsa70§C

Symbol Parameter Conditions OP-07D Units

Min Typ Max

VOS Input Offset Voltage (Note 1) 60 150 mV

85 250

VOS/t Long-Term VOS Stability (Note 2) 0.5 3.0 mV/Mo

IOS Input Offset Current 0.8 6.0 nA

1.6 8.0

IBInput Bias Current g2.0 g12.0 nA

g3.0 g14.0

enp-p Input Noise Voltage 0.1 Hz to 10 Hz (Note 3) 0.38 0.65 mVp-p

enInput Noise Voltage Density fOe10 Hz 10.5 20.0

fOe100 Hz (Note 3) 10.3 13.5 nV/0Hz

fOe1000 Hz 9.8 11.5

inp-p Input Noise Current 0.1 Hz to 10 Hz (Note 3) 15 35 pAp-p

inInput Noise Current Density fOe10 Hz 0.35 0.90 pA/0Hz

fOe100 Hz (Note 3) 0.15 0.27

fOe1000 Hz 0.13 0.18

RIN Input Resistance Differential-Mode (Note 4) 7 31 MX

RINCM Input Resistance Common-Mode 120 GX

IVR Input Voltage Range g13 g14 V

CMRR Common-Mode VCM eg13V 94 110 dB

Rejection Ratio 94 106

PSRR Power Supply VSeg3V to g18V 7 32 mV/V

Rejection Ratio 10 51

AVO Large Signal RLs2kX,V

Oeg

10V 120 400

Voltage Gain RLe2kX,V

Oeg

10V 100 400 V/mV

RLt500X,V

Oeg

0.5V, 400

VSg3V (Note 4)

VOOutput Voltage Swing RLt10 kXg12.0 g13.0

RLt2kXg

11.5 g12.8 V

RLt2kXg

11.0 g12.6

RLt1kXg

12.0

SR Slew Rate RLt2kX(Note 3) 0.1 0.3 V/ms

BW Closed-Loop Bandwidth AVCL ea

1 (Note 3) 0.4 0.6 MHz

RO Output Resistance VOe0, IOe060X

Power Consumption VSeg15V, No Load 80 150 mW

VSeg3V, No Load 4 8

Offset Adj. Range RPe20 kXg4mV

TCVOS Average Input Offset (Note 4) 0.7 2.5 mV/§C

Voltage Drift Without

External Trim

TCVOSn With External Trim RPe20 kX(Note 4) 0.7 2.5 mV/§C

TCIOS Average Input Offset Current Drift (Note 3) 12 50 pA/§C

TCIBAverage Input Bias Current Drift (Note 3) 18 50 pA/§C

Note 1: VOS is measured approximately 0.5 second after application of power.

Note 2: Long-Term Offset Voltage Stability refers to the averaged trend line of VOS vs Time over extended periods after the first 30 days of operation.

Excluding the initial hour of operation, changes in VOS during the first 30 operating days are typically 2.5 mV. Parameter is sample tested.

Note 3: Sample Tested.

Note 4: Guaranteed by design.

Test Circuits

Offset Voltage Test Circuit

TL/H/10550–4

Low Frequency Noise Test Circuit

TL/H/10550–5

Optional Offset Nulling Circuit

TL/H/10550–6

OP-07 Low Offset, Low Drift Operational Amplifier

Physical Dimensions inches (millimeters) (Continued)

Order Number OP-07EP, OP-07CP or OP-07DP

NS Package Number N08E

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