SEMICONDUCTOR
1
November 1996
HIP4086
80V, 0.5A Three Phase Driver
Features
• Independently Drives 6 N-Channel MOSFETs in Three
Phase Bridge Configuration
• Bootstrap Supply Max Voltage to 95VDC
• Bias Supply Operation from 7V to 15V
• 1.25A Peak Turn-Off Current
• User-Programmable Dead Time (0.25µs to 4.5µs)
• Charge-Pump and Bootstrap Maintain Upper Bias
Supplies
• Programmable Bootstrap Refresh Time
• Drives 1000pF Load with Typical Rise Time of 20ns
and Fall Time of 10ns
• DIS (Disable) Overrides Input Control
• Input Logic Thresholds Compatible with 5V to 15V
Logic Levels
• Dead Time Disable Capability
• Programmable Undervoltage Set Point
Applications
• Brushless Motors
• AC Motor Drives
• Switched Reluctance Motor Drives
• Battery Powered Vehicles
Description
The HIP4086 is a Three Phase Bridge N-Channel MOSFET
driver IC. The HIP4086 is specifically targeted for PWM
motor control. It makes bridge based designs simple and
flexible. Like the HIP4081, the HIP4086 has a flexible input
protocol f or driving ev ery possible s witch combination. Unlik e
the HIP4081, the user can override the shoot-through
protection f or s witched reluctance applications. The HIP4086
has reduced drive current compared to the HIP4081 (0.5A
vs 2.5A) and a much wider range of programmable dead
times (0.25µs to 4.5µs) - like the HIP4082. The HIP4086 is
suitable for applications requiring DC to 100kHz. Unlike the
previous family members, the HIP4086 has a programmable
undervoltage set point.
Also refer to the HIP4083, three phase upper only MOSFET
driver, for a lower current solution optimized for smaller
motors.
Pinout
HIP4086
(PDIP, SOIC)
TOP VIEW
Application Block Diagram
Ordering Information
PART NUMBER TEMP.
RANGE (oC) PACKAGE PKG.
NO.
HIP4086AB -40 to 125 24 Pin SOIC M24.3
HIP4086AP -40 to 125 24 Pin PDIP E24.3
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
21
22
23
24
15
14
13
AHB
BHO
BLO
ALO
BHS
VDD
AHS
AHO
CHO
CHB
CLO
CHS
BHB
BHI
AHI
BLI
ALI
VSS
DIS
RFSH
CHI
UVLO
CLI
RDEL
12V
80V
GND
GND
HIP4086
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © Harris Corporation 1996 File Number 4220.1
2
Functional Block Diagram
(1/3 of HIP4086 )
Typical Application
(PWM Mode Switching)
TRUTH TABLE
INPUT OUTPUT
ALI, BLI, CLI AHI, BHI, CHI UV DIS RDEL ALO, BLO, CLO AHO, BHO, CHO
XXX1X00
XX1XX00
1 X 0 0 >100mV 1 0
0000X01
0100X00
1 0 0 0 <100mV 1 1
NOTE: X signifies that input can be either a “1” or “0”.
CHARGE
PUMP
VDD
DIS
ALI
UVLO
AHB
AHO
AHS
UV
20
8
AHI 5
10ns
DELAY
10
UNDERVOLTAGE
DETECTOR
RFSH
9
RFSH PULSE
4
LEVEL
SHIFTER
TURN-ON
DELAY
DRIVER 16
17
18
TURN-ON
DELAY
VDD
ALO
VSS
DRIVER 20
21
6
DEAD TIME
CURRENT
MIRRORS
7
RDEL
2µs
DELAY
+
-
100mV
+
-
VSS
DEAD TIME
DISABLE
DEAD TIME
DISABLE
UV
80V
+12V
PWM
INPUTS
CRFSH
RDIS
FROM
OPTIONAL
OVERCURRENT
LATCH
RDEL
3-PHASE
LOAD
GND
1
2
3
4
5
6
7
8
9
10
11
12
16
17
18
19
20
21
22
23
24
15
14
13
BHB
BHI
AHI
BLI
ALI
VSS
AHB
BHO
BLO
ALO
BHS
VDD
AHS
AHO
DIS
RFSH
CHI
UVLO
CLI CHO
CHB
CLO
CHS
RDEL
(OPTIONAL)
RUV
(OPTIONAL)
+12V
HIP4086
3
Pin Descriptions
PIN
NUMBER SYMBOL DESCRIPTION
17
1
13
AHB
BHB
CHB
(xHB)
High-Side Bootstrap supplies. One external bootstrap diode and one capacitor are required for each.
Connect cathode of bootstrap diode and positive side of bootstrap capacitor to each xHB pin.
5
2
12
AHI
BHI
CHI
(xHI)
High-Side Logic Level Inputs. Logic at these three pins controls the three high side output drivers, AHO
(Pin 17), BHO (Pin 24) and CHO (Pin 14). When xHI is low, xHO is high. When xHI is high, xHO is low.
Unless the dead time is disabled b y connecting RDEL ( Pin 7) to ground, the low side input of each phase
will ov erride the corresponding high side input on that phase - see Truth Table on pre vious page. If RDEL
is tied to ground, dead time is disabled and the outputs follow the inputs. Care must be taken to avoid
shoot-through in this application. DIS (Pin 10) also overrides the high side inputs. xHI can be driven by
signal lev els of 0V to 15V (no greater than V DD). An internal 100µA pull-up to VDD will hold each xHI high
if the pins are not driven.
4
3
11
ALI
BLI
CLI
(xLI)
Low-Side Logic Le vel Inputs. Logic at these three pins controls the three lo w side output drivers ALO (Pin
21), BLO (Pin 22) and CLO (Pin 19). If the upper inputs are grounded then the lower inputs control both
xLO and xHO drivers, with the dead time set b y the resistor at RDEL (Pin 7). DIS (Pin 10) high lev el input
overrides xLI, forcing all outputs low. xLI can be driven by signal levels of 0V to 15V (no greater than
VDD). An internal 100µA pull-up to VDD will hold xLI high if these pins are not driven.
6V
SS Ground. Connect the sources of the Low-Side power MOSFETs to this pin.
7 RDEL Dead Time Setting. Connect a resistor from this pin to VDD to set timing current that defines the dead
time between drivers - see Figure 17. All drivers turn-off with no adjustable delay, so the RDEL resistor
guarantees no shoot-through by dela ying the turn-on of all drivers . When RDEL is tied to VSS, both upper
and lowers can be commanded on simultaneously. While not necessar y in most applications, a decou-
pling capacitor of 0.1µF or smaller may be connected between RDEL and VSS.
8 UVLO Undervoltage Setting. A resistor can be connected between this pin and VSS to program the under volt-
age set point, see Figure 18. With this pin not connected, the undervoltage disable is typically 6.6V. When
this pin is tied to VDD, the undervoltage disable is typically 6.2V.
9 RFSH Refresh Pulse Setting. An external capacitor can be connected from this pin to VSS to increase the length
of the star t up refresh pulse - see Figure 16. If this pin is not connected, the refresh pulse is typically
1.5µs.
10 DIS Disable Input. Logic level input that when taken high sets all six outputs low. DIS high overrides all other
inputs. With DIS low, the outputs are controlled by the other inputs. DIS can be driven by signal levels of
0V to 15V (no greater than VDD). An internal 100µA pull-up to VDD will hold DIS high if this pin is not
driven.
17
24
14
AHO
BHO
CHO
(xHO)
High-Side Outputs. Connect to the gates of the High-Side power MOSFETs in each phase.
15
23
15
AHS
BHS
CHS
(xHS)
High-Side Source Connection. Connect the sources of the High-Side power MOSFETs to these pins.
The negative side of the bootstrap capacitors should also be connected to these pins.
20 VDD Positive Supply. Decouple this pin to VSS (Pin 6).
21
22
19
ALO
BLO
CLO
(xLO)
Low-Side Outputs. Connect the gates of the Low-Side power MOSFETs to these pins.
NOTE: x = A, B and C.
HIP4086
4
Absolute Maximum Ratings Thermal Information
Supply Voltage, VDD. . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V
Logic I/O Voltages . . . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD +0.3V
Voltage on xHS. . . . . . . . . .-6V (Transient) to 85V (-40oC to 150oC)
Voltage on xHB. . . . . . . . . . . . . . . . . . . . .VxHS -0.3V to VxHS +VDD
Voltage on xLO. . . . . . . . . . . . . . . . . . . . . . VSS -0.3V to VDD +0.3V
Voltage on xHO . . . . . . . . . . . . . . . . . . . VxHS -0.3V to VxHB +0.3V
Phase Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20V/ns
Operating Conditions
Supply Voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . +7V to +15V
Voltage on xHB. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VxHS + VDD
Voltage on xHS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0V to 80V
Thermal Resistance (Typical, Note 1) θJA (oC/W)
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
DIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Storage Temperature Range. . . . . . . . . . . . . . . . . . .-65oC to 150oC
Operating Max. Junction Temperature . . . . . . . . . . . . . . . . . . 150oC
Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Ambient Temperature Range . . . . . . . . . .-40oC to 125oC
Operating Junction Temperature Range . . . . . . . . . .-40oC to 150oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
2. All voltages are relative to V SS unless otherwise specified.
3. x = A, B and C. For example, xHS refers to AHS, BHS and CHS.
Electrical Specifications VDD = VxHB = 12V, VSS = VxHS = 0V, RDEL = 20K, RUV = ∞, Gate Capacitance(CGATE ) = 1000pF
PARAMETER TEST CONDITIONS
TJ = 25oCTJ = -40oC TO
150oC
UNITSMIN TYP MAX MIN MAX
SUPPLY CURRENTS AND UNDER VOLTAGE PROTECTION
VDD Quiescent Current xHI = 5V, xLI = 5V 2.7 3.4 4.2 2.1 4.3 mA
VDD Operating Current f = 20kHz, 50% Duty Cycle 6.3 8.25 10.5 5 11 mA
xHB On Quiescent Current xHI = 0V - 40 80 - 100 µA
xHB Off Quiescent Current xHI = VDD 0.6 0.8 1.3 0.5 1.4 mA
xHB Operating Current f = 20kHz, 50% Duty Cycle 0.7 0.9 1.3 - 2.0 mA
Qpump Output Voltage No Load 11.5 12.5 14 10.5 14.5 V
Qpump Output Current VxHS = 12V, VxHB = 22V 50 100 130 - 140 µA
xHB, xHS Leakage Current VxHS = 80V, VxHB = 93V 7 24 45 - 50 µA
VDD Rising Undervoltage Threshold RUV open 6.2 7.1 8.0 6.1 8.1 V
VDD Falling Undervoltage Threshold RUV open 5.75 6.6 7.5 5.6 7.6 V
Minimum Undervoltage Threshold RUV = VDD 5 6.2 6.8 4.9 6.9 V
INPUT PINS: ALI, BLI, CLI, AHI, BHI, CHI, AND DIS
Low Level Input Voltage - - 1.0 - 0.8 V
High Level Input Voltage 2.5 - - 2.7 - V
Input Voltage Hysteresis - 35 - - - mV
Low Level Input Current VIN = 0V 60 100 135 55 140 µA
High Level Input Current VIN = 5V -1 - +1 -10 +10 µA
GATE DRIVER OUTPUT PINS: ALO, BLO, CLO, AHO, BHO, AND CHO
Low Level Output Voltage (VOUT - VSS)I
SINKING = 30mA - 100 - - 200 mV
Peak Turn-On Current VOUT = 0V 0.3 0.5 0.7 - 1.0 A
Peak Turn-Off Current VOUT = 12V 0.7 1.1 1.5 0.5 1.7 A
HIP4086
5
Switching Specifications VDD = VxHB = 12V, VSS = VxHS = 0V, CGATE = 1000pF, RDEL = 10k
PARAMETER TEST CONDITIONS
TJ = 25oCTJ = -40oC TO
150oC
UNITSMIN TYP MAX MIN MAX
TURN-ON DELAY AND PROPAGATION DELAY
Dead Time RDEL = 100K 3.8 4.5 6 3 7 µs
RDEL = 10K 0.38 0.5 0.65 0.3 0.7 µs
Dead Time Channel Matching RDEL = 10K - 7 15 - 20 %
Lower Turn-Off Propagation Delay
(xLI-xLO) No Load - 30 45 - 65 ns
Upper Turn-Off Propagation Delay
(xHI-xHO) No Load - 75 90 - 100 ns
Lower Turn-On Propagation Delay
(xLI-xLO) No Load - 45 75 - 90 ns
Upper Turn-On Propagation Delay
(xHI-xHO) No Load - 65 90 - 100 ns
Rise Time CGATE = 1000pF - 20 40 - 50 ns
Fall Time CGATE = 1000pF - 10 20 - 25 ns
Disable Turn-Off Propagation Delay
(DIS - Lower Outputs) - 55 80 - 90 ns
Disable Turn-Off Propagation Delay
(DIS - Upper Outputs) - 80 90 - 100 ns
Disable to Lower Turn-On Propagation Delay
(DIS - xLO) - 55 80 - 100 ns
Disable to Upper Enable (DIS - xHO) RDEL = 10K, CRFSH Open - 2.0 - - - µs
Refresh Pulse Width (xLO) CRFSH Open - 1.5 - - - µs
HIP4086
6
Timing Diagrams
FIGURE 1.
FIGURE 2. DISABLE FUNCTION
NOTES:
4. X means any “A”, “B”, or “C” phase.
5. With RDEL resistor tied to VDD, lowers and uppers cannot be turned on at the same time. Low side logic overrides high side logic unless
RDEL < 100mV.
XLI
XHI
XLO
XHO
XLO
XHO
DEAD TIME DEAD TIME
(RDEL = VSS)
LOWER LOWER
UPPER UPPER
(RDEL = VSS)
TURN-ON TURN-OFF
TURN-ONTURN-OFF
DIS OR UV
XHI, XLI
XLO
XHO
DISABLE TO LOWER DISABLE TURN-OFF
DISABLE TO UPPER
REFRESH
TURN-ON PROP DELAY
PULSE WIDTH
PROP DELAY (UPPERS)
ENABLE
HIP4086
7
Typical Performance Curves
FIGURE 3. VDD SUPPLY CURRENT vs VDD SUPPLY VOLTAGE FIGURE 4. VDD SUPPLY CURRENT vs SWITCHING
FREQUENCY
FIGURE 5. FLOATING IXHB BIAS CURRENT FIGURE 6. OFF-STATE IXHB BIAS CURRENT
FIGURE 7. CHARGE PUMP OUTPUT CURRENT FIGURE 8. CHARGE PUMP OUTPUT VOLTAGE
-60 -40 -20 0 20 40 60 80 100 120 140 160
2
3
4
5
6
JUNCTION TEMPERATURE (oC)
VDD SUPPLY CURRENT (mA)
VDD = 7V
VDD = 8V
VDD = 10V
VDD = 12V
VDD = 15V
VDD = 16V ALL GATE CONTROL INPUTS = 5V
-60 -40 -20 0 20 40 60 80 100 120 140 160
10
15
20
25
30
JUNCTION TEMPERATURE (oC)
VDD SUPPLY CURRENT (mA)
200kHz
CGATE = 1000pF
20kHz
50kHz
100kHz
10kHz
0 20 40 60 80 100 120 140 160 180 200
0
1000
2000
3000
4000
SWITCHING FREQUENCY (kHz)
FLOATING BIAS CURRENT (µA)
CGATE = NO LOAD
CGATE = 1000pF
TJ = 25oC
JUNCTION TEMPERATURE (oC)
-60 -40 -20 0 20 40 60 80 100 120 140 160
0.6
0.8
1.0
1.2
1.4
1.6
1.8
BIAS CURRENT (mA)
VDD = 10V
VDD = 12V
VDD = 15V
VDD = 7V
VDD = 8V
-60 -40 -20 0 20 40 60 80 100 120 140 160
200
150
100
50
0
JUNCTION TEMPERATURE (oC)
OUTPUT CURRENT (µA)
VxHB - VxHS = 10V
-60 -40 -20 0 20 40 60 80 100 120 140 160
6
7
8
9
10
11
12
13
14
JUNCTION TEMPERATURE (oC)
CHARGE PUMP OUTPUT VOLTAGE (V)
VDD = 7V
VDD = 12V
VDD = 10V
VDD = 8V
VDD = 15V
HIP4086
8
FIGURE 9. AVERAGE TURN-ON CURRENT (0 TO 5V) FIGURE 10. AVERAGE TURN-OFF CURRENT (VDD TO 4V)
FIGURE 11. RISE AND FALL TIMES (10-90%) FIGURE 12. PROPAGATION DELAY
FIGURE 13. DISABLE PIN PROPAGATION DELAY FIGURE 14. REFRESH TIME
Typical Performance Curves
(Continued)
-60 -40 -20 0 20 40 60 80 100 120 140 160
0
0.2
0.4
0.6
0.8
1
JUNCTION TEMPERATURE (oC)
AVERAGE TURN-ON CURRENT (A)
CGATE = 1000pF
VDD = 15V
VDD = 8V
VDD = 10V
VDD = 12V
VDD = 7V
-60 -40 -20 0 20 40 60 80 100 120 140 160
0
0.4
0.8
1.2
1.6
2
JUNCTION TEMPERATURE (oC)
AVERAGE TURN-OFF CURRENT (A)
CGATE = 1000pF
VDD = 15V
VDD = 8V
VDD = 10V
VDD = 12V
VDD = 7V
-60 -40 -20 0 20 40 60 80 100 120 140 16
0
0
10
20
30
40
JUNCTION TEMPERATURE (oC)
RISE AND FALL TIMES (ns)
RISE
FALL
VDD = XHB-XHS = 12V, CGATE = 1000pF
-60 -40 -20 0 20 40 60 80 100 120 140 160
20
40
60
80
100
JUNCTION TEMPERATURE (oC)
PROPAGATION DELAY (ns)
xHI to xHO
xLI to xLO
JUNCTION TEMPERATURE (oC)
-60 -40 -20 0 20 40 60 80 100 120 140 160
10
100
PROPAGATION DELAY (ns)
LOWER ENABLE TURN-ON
LOWER DISABLE TURN-OFF
UPPER DISABLE TURN-OFF
CRFSH (pF)
0 50 100 150 200 250 300 350 400 450 500
0
20
40
60
80
REFRESH TIME (µs)
TJ = 25oC
HIP4086
9
FIGURE 15. DEAD TIME FIGURE 16. UNDERVOLTAGE THRESHOLD
FIGURE 17. IxHS LEAKAGE CURRENT
Typical Performance Curves
(Continued)
JUNCTION TEMPERATURE (oC)
-60 -40 -20 0 20 40 60 80 100 120 140 160
0
2
4
6
DEAD TIME (µs)
RDEL = 100kΩ
RDEL = 10kΩ
JUNCTION TEMPERATURE (oC)
UNDERVOLTAGE SHUTDOWN/
-60 -40 -20 0 20 40 60 80 100 120 140 160
6
6.5
7
7.5
8
8.5
9
9.5
10
10.5
11
ENABLE VOLTAGE
ENABLE (50K, UVLO TO GND)
TRIP (50K, UVLO TO GND)
ENABLE (UVLO OPEN)
TRIP (UVLO OPEN)
TRIP/ENABLE (0K, UVLO TO VDD)
JUNCTION TEMPERATURE (oC)
-60 -40 -20 0 20 40 60 80 100 120 140 160
10
15
20
25
LEAKAGE CURRENT (µA)
VxHS = 80V
HIP4086
10
HIP4086
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protru-
sions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and are measured with the leads constrained to be per-
pendicular to datum .
7. eB and eC are measured at the lead tips with the leads uncon-
strained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 1 2 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1 Be
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C A
MBS
eA-C-
Dual-In-Line Plastic Packages (PDIP)
E24.3 (JEDEC MS-001-AF ISSUE D)
24 LEAD NARROW BODY DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.15 1.77 8
C 0.008 0.014 0.204 0.355 -
D 1.230 1.280 31.24 32.51 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA0.300 BSC 7.62 BSC 6
eB- 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N24 249
Rev. 0 12/93
11
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Harris Semiconductor products are sold by description only. Harris Semiconductor reserves the right to make changes in circuit design and/or specifications at
any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Harris is
believed to be accurate and reliable. However, no responsibility is assumed by Harris or its subsidiaries for its use; nor for any infringements of patents or other
rights of third parties which ma y result from its use . No license is g ranted by implication or otherwise under any patent or patent rights of Harris or its subsidiaries.
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Singapore 1334
TEL: (65) 748-4200
FAX: (65) 748-0400
SEMICONDUCTOR
HIP4086
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. In-
terlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimen-
sions are not necessarily exact.
INDEX
AREA E
D
N
123
-B-
0.25(0.010) C A
MBS
e
-A-
L
B
M
-C-
A1
A
SEATING PLANE
0.10(0.004)
h x 45o
C
H
0.25(0.010) B
MM
α
Small Outline Plastic Packages (SOIC)
M24.3 (JEDEC MS-013-AD ISSUE C)
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A 0.0926 0.1043 2.35 2.65 -
A1 0.0040 0.0118 0.10 0.30 -
B 0.013 0.020 0.33 0.51 9
C 0.0091 0.0125 0.23 0.32 -
D 0.5985 0.6141 15.20 15.60 3
E 0.2914 0.2992 7.40 7.60 4
e 0.05 BSC 1.27 BSC -
H 0.394 0.419 10.00 10.65 -
h 0.010 0.029 0.25 0.75 5
L 0.016 0.050 0.40 1.27 6
N24 247
α
0
o
8
o
0
o
8
o
-
Rev. 0 12/93
