1
LTC4210-3/LTC4210-4
421034fa
APPLICATIO S
U
DESCRIPTIO
U
FEATURES
TYPICAL APPLICATIO
U
The LTC
®
4210-3/LTC4210-4 is a 6-pin SOT-23 Hot Swap
TM
controller that allows a board to be safely inserted and
removed from a live backplane. An internal high side
switch driver controls the GATE of an external N-channel
MOSFET for a supply voltage ranging from 2.7V to 7V. The
LTC4210 provides the initial timing cycle and allows the
GATE to be ramped up at an adjustable rate.
The LTC4210 features a fast current limit loop providing
active current limiting together with a circuit breaker
timer. The signal at the ON pin turns the part on and off and
is also used for the reset function.
The LTC4210-3 retries on overcurrent fault and the
LTC4210-4 latches off on an overcurrent fault.
■
Allows Safe Board Insertion and Removal
from a Live Backplane
■
Adjustable Analog Current Limit
with Circuit Breaker
■
Fast Response Limits Peak Fault Current
■
Automatic Retry or Latch Off On Current Fault
■
Adjustable Supply Voltage Power-Up Rate
■
High Side Drive for External MOSFET Switch
■
Controls Supply Voltages from 2.7V to 7V
■
Undervoltage Lockout
■
Adjustable Overvoltage Protection
■
Low Profile (1mm) SOT-23 (ThinSOT
TM
) Package
■
Hot Board Insertion
■
Electronic Circuit Breaker
■
Industrial High Side Switch/Circuit Breaker
Hot Swap Controller in
6-Lead SOT-23 Package
Single Channel 5V Hot Swap Controller
Power-Up Sequence
+
V
CC
SENSE
LTC4210-3
470µF
V
OUT
5V
4A
GND
4210 TA01
100Ω
GATE
GND
TIMER
ON
SHORT
LONG
V
IN
5V
GND LONG
Z1: ISMA10A OR SMAJ10A
10k
20k
10Ω
R
SENSE
0.01Ω
PCB EDGE
CONNECTOR
(MALE) Q1
Si4410DY
Z1
OPTIONAL
100Ω
0.22µF
0.1µF
0.01µF
BACKPLANE
CONNECTOR
(FEMALE)
4210 TA02
10ms/DIV
IOUT
(0.5A/DIV)
VOUT
(5V/DIV)
VON
(2V/DIV)
VTIMER
(1V/DIV)
CLOAD = 470µF
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
ThinSOT and Hot Swap are trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
2
LTC4210-3/LTC4210-4
421034fa
(Note 1)
Supply Voltage (V
CC
) ............................................... 17V
Input Voltage (SENSE, TIMER) .. –0.3V to (V
CC
+ 0.3V)
Input Voltage (ON)..................................... –0.3V to 17V
Output Voltage (GATE) ........ Internally Limited (Note 3)
Operating Temperature Range
LTC4210-3C/LTC4210-4C ....................... 0°C to 70°C
LTC4210-3I/LTC4210-4I .................... –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
ABSOLUTE AXI U RATI GS
WWWU
PACKAGE/ORDER I FOR ATIO
UU
W
ORDER PART
NUMBER
LTC4210-3CS6
LTC4210-4CS6
LTC4210-3IS6
LTC4210-4IS6
T
JMAX
= 125°C, θ
JA
= 230°C/ W
TIMER 1
GND 2
ON 3
6 V
CC
5 SENSE
4 GATE
TOP VIEW
S6 PACKAGE
6-LEAD PLASTIC TSOT-23
S6 PART MARKING
LTCPJ
LTCPM
LTCPK
LTCPN
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
CC
Supply Voltage ●2.7 7.0 V
I
CC
V
CC
Supply Current ●0.75 3.5 mA
V
LKOR
V
CC
Undervoltage Lockout Release V
CC
Rising ●2.2 2.5 2.65 V
V
LKOHYST
V
CC
Undervoltage Lockout Hysteresis 100 mV
I
INON
ON Pin Input Current ●–10 0 10 µA
I
INSENSE
SENSE Pin Input Current V
SENSE
= V
CC
●–10 5 10 µA
V
CB
Circuit Breaker Trip Voltage V
CB
= (V
CC
– V
SENSE
)●44 50 56 mV
I
GATEUP
GATE Pin Pull-Up Current V
GATE
= 0V ●–5 –10 –15 µA
I
GATEDN
GATE Pin Pull-Down Current V
TIMER
= 1.5V, V
GATE
= 3V or 25 mA
V
ON
= 0V, V
GATE
= 3V or
V
CC
– V
SENSE
= 100mV, V
GATE
= 3V
∆V
GATE
External N-Channel Gate Drive V
GATE
– V
CC
, V
CC
= 2.7V ●4.0 6.5 8 V
V
GATE
– V
CC
, V
CC
= 3V ●4.5 7.5 10 V
V
GATE
– V
CC
, V
CC
= 3.3V ●5.0 8.5 9.7 V
V
GATE
– V
CC
, V
CC
= 5V ●5.0 7.0 8.0 V
V
GATE
GATE Pin Voltage V
CC
= 2.7V ●6.7 9.2 10.7 V
V
CC
= 3.0V ●7.5 10.5 13.0 V
V
CC
= 3.3V ●8.3 11.8 13.0 V
V
CC
= 5.0V ●10.0 12.0 13.0 V
I
TIMERUP
TIMER Pin Pull-Up Current Initial Cycle, V
TIMER
= 1V ●–2 –5 –8.5 µA
During Current Fault Condition, V
TIMER
= 1V ●–25 –60 –100 µA
I
TIMERDN
TIMER Pin Pull-Down Current After Current Fault Disappears, V
TIMER
= 1V ●2 3.5 µA
Under Normal Conditions, V
TIMER
= 1V 100 µA
V
TIMER
TIMER Pin Threshold High Threshold, TIMER Rising ●1.22 1.3 1.38 V
Low Threshold, TIMER Falling ●0.15 0.2 0.25 V
V
TMRHYST
TIMER Low Threshold Hysteresis 100 mV
V
ON
ON Pin Threshold ON Threshold, ON Rising ●1.22 1.3 1.38 V
V
ONHYST
ON Pin Threshold Hysteresis 80 mV
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VCC = 5V, unless otherwise noted. (Note 2)
ELECTRICAL CHARACTERISTICS
Consult factory for parts specified with wider operating temperature ranges.
Order Options Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking: http://www.linear.com/leadfree/
3
LTC4210-3/LTC4210-4
421034fa
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t
OFF(TMRHIGH)
Turn-Off Time (TIMER Rise to GATE Fall) V
TIMER
= 0V to 2V Step, V
CC
= V
ON
= 5V 1 µs
t
OFF(ONLOW)
Turn-Off Time (ON Fall to GATE Fall) V
ON
= 5V to 0V Step, V
CC
= 5V 30 µs
t
OFF(VCCLOW)
Turn-Off Time (V
CC
Fall to IC Reset) V
CC
= 5V to 2V Step, V
ON
= 5V 30 µs
The ● denotes specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VCC = 5V, unless otherwise noted. (Note 2)
ELECTRICAL CHARACTERISTICS
Note 3: An internal Zener clamped the GATE pin to a typical voltage of
12V. External overdrive of the GATE pin beyond the internal Zener voltage
may damage the device. Without a limiting resistor, the GATE capacitance
must be <0.15µF at maximum V
CC
.
TYPICAL PERFOR A CE CHARACTERISTICS
UW
Supply Current vs Supply Voltage Supply Current vs Temperature
Undervoltage Lockout Threshold
vs Temperature
VGATE vs Supply Voltage VGATE vs Temperature IGATEUP vs Supply Voltage
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
TEMPERATURE (°C)
–75
UNDERVOLTAGE LOCKOUT THRESHOLD (V)
2.45
2.50
2.55
125
LTC4210 • G03
2.40
2.35
2.25 –25 25 75
–50 150
050 100
2.30
2.65
2.60
V
CC
RISING
V
CC
FALLING
SUPPLY VOLTAGE (V)
2.5
0.0
SUPPLY CURRENT (mA)
0.2
0.6
0.8
1.0
2.0
1.4
3.5 4.5 5.0 7.0
LTC4210 • G01
0.4
1.6
1.8
1.2
3.0 4.0 5.5 6.0 6.5
TA = 25°C
VS = 5V
TEMPERATURE (°C)
–75
0.0
SUPPLY CURRENT (mA)
0.2
0.6
0.8
1.0
2.0
1.4
–25 25 50 150
LTC4210 • G02
0.4
1.6
1.8
1.2
–50 0 75 100 125
V
CC
= 5V
V
CC
= 3V
SUPPLY VOLTAGE (V)
2.5
6
V
GATE
(V)
7
9
10
11
16
13
3.5 4.5 5.0 7.0
LTC4210 • G04
8
14
15
12
3.0 4.0 5.5 6.0 6.5
TEMPERATURE (°C)
–75
6
V
GATE
(V)
7
9
10
11
16
13
–25 25 50 150
LTC4210 • G05
8
14
15
12
–50 0 75 100 125
V
CC
= 5V
V
CC
= 3V
SUPPLY VOLTAGE (V)
2.5
I
GATEUP
(µA)
–10.0
–9.5
–9.0
6.5
LTC4210 • G06
–10.5
–11
–12.0 3.5 4.5 5.5
3.0 7.0
4.0 5.0 6.0
–11.5
–8.0
–8.5 TA = 25°C
4
LTC4210-3/LTC4210-4
421034fa
TYPICAL PERFOR A CE CHARACTERISTICS
UW
ITIMERUP (In Initial Cycle)
vs Supply Voltage
ITIMERUP (During Circuit Breaker
Delay) vs Supply Voltage
ITIMERUP (During Circuit Breaker
Delay) vs Temperature
ITIMERDN (In Cool-Off Cycle)
vs Supply Voltage
ITIMERUP (In Initial Cycle)
vs Temperature
ITIMERDN (In Cool-Off Cycle)
vs Temperature
IGATEUP vs Temperature ∆VGATE vs Supply Voltage ∆VGATE vs Temperature
TEMPERATURE (°C)
–75
I
GATEUP
(µA)
–10.0
–9.5
–9.0
125
LTC4210 • G07
–10.5
–11
–12.0 –25 25 75
–50 150
050 100
–11.5
–8.0
–8.5
V
CC
= 3V
V
CC
= 5V
SUPPLY VOLTAGE (V)
2.5
2
∆VGATE (V)
3
5
6
7
12
9
3.5 4.5 5.0 7.0
LTC4210 • G08
4
10
11
8
3.0 4.0 5.5 6.0 6.5
TEMPERATURE (°C)
–75
2
∆V
GATE
(V)
3
5
6
7
12
9
–25 25 50 150
LTC4210 • G09
4
10
11
8
–50 0 75 100 125
V
CC
= 5V
V
CC
= 3V
SUPPLY VOLTAGE (V)
2.5
–10
ITIMERUP (µA)
–9
–7
–6
–5
0
–3
3.5 4.5 5.0 7.0
LTC4210 • G10
–8
–2
–1
–4
3.0 4.0 5.5 6.0 6.5
TA = 25 °C
TEMPERATURE (°C)
–75
–10
ITIMERUP (µA)
–9
–7
–6
–5
0
–3
–25 25 50 150
LTC4210 • G11
–8
–2
–1
–4
–50 0 75 100 125
VCC = 5V
SUPPLY VOLTAGE (V)
–75
I
TIMERUP
(µA)
–60
–50
–40
125
LTC4210 • G13
–70
–80
–100 –25 25 75
–50 150
050 100
–90
–20
–30
V
CC
= 5V
SUPPLY VOLTAGE (V)
2.5
I
TIMERUP
(µA)
–60
–50
–40
6.5
LTC4210 • G12
–70
–80
–100 3.5 4.5 5.5
3.0 7.0
4.0 5.0 6.0
–90
–20
–30
TA = 25°C
SUPPLY VOLTAGE (V)
2.5
1.0
ITIMERDN (µA)
1.2
1.6
1.8
2.0
3.0
2.4
3.5 4.5 5.0 7.0
LTC4210 • G14
1.4
2.6
2.8
2.2
3.0 4.0 5.5 6.0 6.5
TA = 25°C
TEMPERATURE (°C)
–75
1.0
I
TIMERDN
(µA)
1.2
1.6
1.8
2.0
3.0
2.4
–25 25 50 150
LTC4210 • G15
1.4
2.6
2.8
2.2
–50 0 75 100 125
V
CC
= 5V
5
LTC4210-3/LTC4210-4
421034fa
TYPICAL PERFOR A CE CHARACTERISTICS
UW
TIMER Low Threshold
vs Temperature
ON Pin Threshold
vs Temperature
tOFF(ONLOW) vs Supply Voltage
ON Pin Threshold
vs Supply Voltage
tOFF(ONLOW) vs Temperature
TIMER High Threshold
vs Supply Voltage
TIMER High Threshold
vs Temperature
TIMER Low Threshold
vs Supply Voltage
SUPPLY VOLTAGE (V)
2.5
TIMER HIGH THRESHOLD (V)
1.30
1.32
1.34
6.5
LTC4210 • G16
1.28
1.26
1.22 3.5 4.5 5.5
3.0 7.0
4.0 5.0 6.0
1.24
1.38
1.36
TA = 25°C
TEMPERATURE (°C)
–75
TIMER HIGH THRESHOLD (V)
1.30
1.32
1.34
125
LTC4210 • G17
1.28
1.26
1.22 –25 25 75
–50 150
050 100
1.24
1.38
1.36
V
CC
= 5V
SUPPLY VOLTAGE (V)
2.5
TIMER LOW THRESHOLD (V)
0.20
0.21
0.22
6.5
LTC4210 • G18
0.19
0.18
0.16 3.5 4.5 5.5
3.0 7.0
4.0 5.0 6.0
0.17
0.24
0.23
TA = 25°C
TEMPERATURE (°C)
–75
TIMER LOW THRESHOLD (V)
0.20
0.21
0.22
125
LTC4210 • G19
0.19
0.18
0.16 –25 25 75
–50 150
050 100
0.17
0.24
0.23
V
CC
= 5V
SUPPLY VOLTAGE (V)
2.5
ON PIN THRESHOLD (V)
1.25
1.30
1.35
6.5
LTC4210 • G20
1.20
1.15
1.05 3.5 4.5 5.5
3.0 7.0
4.0 5.0 6.0
1.10
1.45
1.40
TA = 25°C
LOW THRESHOLD
HIGH THRESHOLD
TEMPERATURE (°C)
–75
ON PIN THRESHOLD (V)
1.25
1.30
1.35
125
LTC4210 • G21
1.20
1.15
1.05 –25 25 75
–50 150
050 100
1.10
1.45
1.40
V
CC
= 5V
LOW THRESHOLD
HIGH THRESHOLD
SUPPLY VOLTAGE (V)
2.5
0
T
OFF, ONLOW
(µs)
5
15
20
25
50
35
3.5 4.5 5.0 7.0
LTC4210 • G22
10
40
45
30
3.0 4.0 5.5 6.0 6.5
TA = 25°C
TEMPERATURE (°C)
–75
0
T
OFF, ONLOW
(µs)
5
15
20
25
50
35
–25 25 50 150
LTC4210 • G23
10
40
45
30
–50 0 75 100 125
v
cc
= 5v
v
cc
= 3v
6
LTC4210-3/LTC4210-4
421034fa
VCB vs Supply Voltage
TYPICAL PERFOR A CE CHARACTERISTICS
UW
VCB vs Temperature
UU
U
PI FU CTIO S
TIMER (Pin 1): Timer Input Pin. An external capacitor
C
TIMER
sets a 272.9ms/µF initial timing delay and a 21.7ms/
µF circuit breaker delay. The GATE pin turns off whenever
the TIMER pin is pulled beyond the COMP2 threshold,
such as for overvoltage detection with an external zener.
GND (Pin 2): Ground Pin.
ON (Pin 3): ON Input Pin. The ON pin comparator has a
low-to-high threshold of 1.3V with 80mV hysteresis and a
glitch filter. When the ON pin is low, the LTC4210 is reset.
When the ON pin goes high, the GATE turns on after the
initial timing cycle.
GATE (Pin 4): GATE Output Pin. This pin is the high side
gate drive of an external N-channel MOSFET. An internal
charge pump provides a 10µA pull-up current with Zener
clamps to V
CC
and ground. In overload, the error amplifier
(EA) controls the external MOSFET to maintain a constant
load current. An external R-C compensation network
should be connected to this pin for current limit loop
stability.
SENSE (Pin 5): Current Limit Sense Input Pin. A sense
resistor between the V
CC
and SENSE pins sets the analog
current limit. In overload, the EA controls the external
MOSFET gate to maintain the SENSE pin voltage at 50mV
below V
CC
. When the EA is maintaining current limit, the
TIMER circuit breaker mode is activated. The current limit
loop/circuit breaker mode can be disabled by connecting
the SENSE pin to the V
CC
pin.
V
CC
(Pin 6): Positive Supply Input Pin. The operating
supply voltage range is between 2.7V to 7V. An undervolt-
age lockout (UVLO) circuit with a glitch filter resets the
LTC4210 when a low supply voltage is detected.
SUPPLY VOLTAGE (V)
2.5
V
CB
(mV)
50
52
54
6.5
LTC4210 • G24
48
46
42 3.5 4.5 5.5
3.0 7.0
4.0 5.0 6.0
44
58
56
TA = 25°C
TEMPERATURE (°C)
–75
V
CB
(mV)
50
52
54
125
LTC4210 • G25
48
46
42 –25 25 75
–50 150
050 100
44
58
56
V
CC
= 5V
7
LTC4210-3/LTC4210-4
421034fa
BLOCK DIAGRA
W
–
+
–+
–+
+
–
6
COMP1
CURRENT LIMIT
INITIAL DOWN/NORMAL
COOL OFF
INITIAL UP/LATCH OFF
0.2V
60µA
1.3V –
+
COMP2
COMP3
1.3V ON
5µA
TIMER
3
GND
100µA2µA
GLITCH
FILTER
SHUTDOWN
M5
GATE
4210 BD
UVLO
V
CC
SENSE
50mV
EA
5
CHARGE
PUMP
10µA
Z1
12V
Z2
26V
4
1
2
LOGIC
GLITCH
FILTER
4k
Hot Circuit Insertion
When circuit boards are inserted into live backplanes, the
supply bypass capacitors can draw large transient cur-
rents from the backplane power bus as they charge. Such
transient currents can cause permanent damage to con-
nector pins, glitches on the system supply or reset other
boards in the system.
The LTC4210 is designed to turn a printed circuit board’s
supply voltage ON and OFF in a controlled manner, allow-
ing the circuit board to be safely inserted into or removed
from a live backplane. The LTC4210 can reside either on
the backplane or on the daughter board for hot circuit
insertion applications.
Overview
The LTC4210-3/LTC4210-4 is designed to operate over a
range of supplies from 2.7V to 7V. Upon insertion, an
undervoltage lockout circuit determines if sufficient sup-
ply voltage is present. When the ON pin goes high an initial
timing cycle assures that the board is fully seated in the
backplane before the MOSFET is turned on. A single timer
capacitor sets the periods for all of the timer functions.
After the initial timing cycle the LTC4210 can either start
up in current limit or with a lower load current. Once the
external MOSFET is fully enhanced and the supply has
ramped up, the LTC4210 monitors the load current through
an external sense resistor. Overcurrent faults are actively
limited to 50mV/R
SENSE
for a specified circuit breaker
timer limit. The LTC4210-3 will automatically retry after a
current limit fault while the LTC4210-4 latches off. The
LTC4210-3 timer function limits the retry duty cycle to
3.8% for MOSFET cooling.
APPLICATIO S I FOR ATIO
WUUU
8
LTC4210-3/LTC4210-4
421034fa
Undervoltage Lockout
An internal undervoltage lockout (UVLO) circuit resets the
LTC4210 if the V
CC
supply is too low for normal operation.
The UVLO has a low-to-high threshold of 2.5V, a 100mV
hysteresis and a high-to-low glitch filter of 30µs. Above
2.5V supply voltage, the LTC4210 will start if the ON pin
conditions are met. A short supply dip below 2.4V for less
than 30µs is ignored to allow for bus supply transients.
ON Function
The ON pin is the input to a comparator which has a low-
to-high threshold of 1.3V, an 80mV hysteresis and a high-
to-low glitch filter of 30µs. A low input on the ON pin resets
the LTC4210 TIMER status and turns off the external
MOSFET by pulling the GATE pin to ground. A low-to-high
transition on the ON pin starts an initial cycle followed by
a start-up cycle. A 10k pull-up resistor connecting the ON
pin to the supply is recommended. The 10k resistor shunts
any potential static charge on the backplane and reduces
the overvoltage stress at the ON pin during live insertion.
Alternatively, an external resistor divider at the ON pin can
be used to program an undervoltage lockout value higher
than the internal UVLO circuit. An RC filter can be added at
the ON pin to increase the delay time at card insertion if the
internal glitch filter delay is insufficient.
GATE Function
During hot insertion of the PCB, an abrupt application of
supply voltage charges the external MOSFET drain/gate
capacitance. This can cause an unwanted gate voltage
spike. An internal proprietary circuit holds GATE low
before the internal circuitry wakes up. This reduces the
MOSFET current surges substantially at insertion. The
GATE pin is held low in reset mode and during the initial
timing cycle. In the start-up cycle the GATE pin is pulled up
by a 10µA current source. During an overcurrent fault
condition, the error amplifier servoes the GATE pin to
maintain a constant current to the load until the circuit
breaker trips. When the circuit breaker trips, the GATE pin
shuts down abruptly.
Current Limit Circuit Breaker Function
The LTC4210 features a current limiting circuit breaker
instead of a traditional comparator circuit breaker. When
there is a sudden load current surge, such as a low
impedance fault, the bus supply voltage can drop signifi-
cantly to a point where the power to an adjacent card is
affected, causing system malfunctions. The LTC4210 fast
response error amplifier (EA) instantly limits current by
reducing the external MOSFET GATE pin voltage. This
minimizes the bus supply voltage drop and permits power
budgeting and fault isolation without affecting neighbor-
ing cards. A compensation circuit should be connected to
the GATE pin for current limit loop stability.
Sense Resistor Consideration
The nominal fault current limit is determined by a sense
resistor connected between V
CC
and the SENSE pin as
given by Equation 1.
IV
R
mV
R
LIMIT NOM
CB NOM
SENSE NOM SENSE
()
()
() (
==
50
NNOM)
(1)
The power rating of the sense resistor should be rated at
the fault current level.
For proper circuit breaker operation, Kelvin-sense PCB
connections between the sense resistor and the LTC4210
V
CC
and SENSE pins are strongly recommended. The
drawing in Figure 1 illustrates the connections between
the LTC4210 and the sense resistor. PCB layout should be
balanced and symmetrical to minimize wiring errors. In
addition, the PCB layout for the sense resistor should
include good thermal management techniques for optimal
sense resistor power dissipation.
APPLICATIO S I FOR ATIO
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SENSE RESISTOR
CURRENT FLOW
TO LOAD
TRACK WIDTH W:
0.03" PER AMP
ON 1 OZ COPPER
W
TO
V
CC
TO
SENSE
4210 F01
CURRENT FLOW
TO LOAD
Figure 1. Making PCB Connections to the Sense Resistor
9
LTC4210-3/LTC4210-4
421034fa
APPLICATIO S I FOR ATIO
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Calculating Current Limit
For a selected R
SENSE
, the nominal load current is given by
Equation 1. The minimum load current is given by
Equation 2:
IV
R
mV
R
LIMIT MIN
CB MIN
SENSE MAX SENSE
()
()
() (
==
44
MMAX)
(2)
where
RR
R
SENSE MAX SENSE TOL
() •=+
⎛
⎝
⎜⎞
⎠
⎟
1100
The maximum load current is given by Equation 3:
IV
R
mV
R
LIMIT MAX
CB MAX
SENSE MIN SENSE
()
()
() (
==
56
MMIN)
(3)
where
RR
R
SENSE MIN SENSE TOL
() •–=⎛
⎝
⎜⎞
⎠
⎟
1100
If
a 7
mΩ sense resistor with ±1% tolerance is used for
current limiting, the nominal current limit is 7.14A.
From Equations 2 and 3, ILIMIT(MIN) = 6.22A and
ILIMIT(MAX) = 8.08A. For proper operation, the minimum
current limit must exceed the circuit maximum operat-
ing load current with margin. The sense resistor power
rating must exceed VCB(MAX)2/RSENSE(MIN).
Frequency Compensation
A compensation circuit should be connected to the GATE
pin for current limit loop stability.
Method 1
The simplest frequency compensation network consists
of R
C
and C
C
(Figure 2a). The total GATE capacitance is:
C
GATE
= C
ISS
+ C
C
(4)
Generally, the compensation value in Figure 2a is suffi-
cient for a pair of input wires less than a foot in length.
Applications with longer input wires may require the R
C
or
C
C
value to be increased for better fault transient perfor-
mance. For a pair of three foot input wires, users can start
with C
C
= 47nF and R
C
= 100Ω. Despite the wire length, the
general rule for AC stability required is C
C
≥ 8nF and R
C
≤
1kΩ.
Method 2
The compensation network in Figure 2b is similar to the
circuitry used in method 1 but with an additional gate
resistor R
G
. The R
G
resistor helps to minimize high
frequency parasitic oscillations frequently associated with
the power MOSFET. In some applications, the user may
find that R
G
helps in short-circuit transient recovery as
well. However, too large of an R
G
value will slow down the
turn-off time. The recommended R
G
range is between 5Ω
and 500Ω. R
G
limits the current flow into the GATE pin’s
internal zener clamp during transient events. The recom-
mended R
C
and C
C
values are the same as method 1. The
parasitic compensation capacitor C
P
is required when 0.2µF
< load capacitance C
L
< 9µF, otherwise it is optional.
Parasitic MOSFET Oscillation
There are two possible parasitic oscillations when the
MOSFET operates as a source follower when ramping at
Figure 2. Frequency Compensation
Q1
Si4410DY
V
CC
SENSE
R
SENSE
0.007Ω
R
G
200Ω
C
P
**
2.2nF
V
IN
12V V
OUT
65
4
R
C
100Ω
C
C
10nF
4210 F02
GATE
LTC4210*
(2b)
Method 2
C
L
+
*ADDITIONAL DETAILS
OMITTED FOR CLARITY
**USE CP IF 0.2µF < CL < 9µF,
OTHERWISE NOT REQUIRED
VCC SENSE
RSENSE
0.007Ω
Q1
Si4410DY
VIN
5V
*ADD
I
OMI
T
**USE
OTH
E
65 CL
4
RC
100Ω
CC
10nF
GATE
LTC4210*
(2a)
Method 1
VOUT
+
10
LTC4210-3/LTC4210-4
421034fa
APPLICATIO S I FOR ATIO
WUUU
power-up or during current limiting. The first type of oscil-
lation occurs at high frequencies, typically above 1MHz.
This high frequency oscillation is easily damped with R
G
as
mentioned in method 2.
The second type of oscillation occurs at frequencies
between 200kHz and 800kHz due to the load capacitance
being between 0.2µF and 9µF, the presence of R
G
and R
C
resistance, the absence of a drain bypass capacitor, a
combination of bus wiring inductance and bus supply output
impedance. There are several ways to prevent this second
type of oscillation. The simplest way is to avoid load
capacitance below 10µF™, the second choice is connect-
ing an external C
P
> 1.5nF.
Whichever method of compensation is used, board level
short-circuit testing is highly recommended as board
layout can affect transient performance. Beside frequency
compensation, the total gate capacitance CGATE also
determines the GATE start-up as in Equation 6. The CGATE
should be kept below 0.15µF at high supply operation as
the capacitive energy ( 0.5 • CGATE • VGATE2 ) is discharged
by the LTC4210 internal pull-down transistor. This pre-
vents the internal pull-down transistor from overheating
when the GATE turns off and/or is serving during current
limiting.
Timer Function
The TIMER pin handles several key functions with an
external capacitor, C
TIMER
. There are two comparator
thresholds: COMP1 (0.2V) and COMP2 (1.3V). The four
timing current sources are:
5µA pull-up
60µA pull-up
2µA pull-down
100µA pull-down
The 100µA is a nonideal current source approximating a 7k
resistor below 0.4V.
Initial Timing Cycle
When the card is being inserted into the bus connector, the
long pins mate first which brings up the supply V
IN
at time
point 1 of Figure 3. The LTC4210 is in reset mode as the ON
pin is low. GATE is pulled low and the TIMER pin is pulled
low with a 100µA source. At time point 2, the short pin
makes contact and ON is pulled high. At this instant, a
start-up check requires that the supply voltage be above
UVLO, the ON pin be above 1.3V and the TIMER pin voltage
be less than 0.2V. When these three conditions are ful-
filled, the initial cycle begins and the TIMER pin is pulled
high with 5µA. At time point 3, the TIMER reaches the
COMP2 threshold and the first portion of the initial cycle
ends. The 100µA current source then pulls down the
TIMER pin until it reaches 0.2V at time point 4. The initial
cycle delay (time point 2 to time point 4) is related to
C
TIMER
by equation:
t
INITIAL
≈ 272.9 • C
TIMER
ms/µF (5)
When the initial cycle terminates, a start-up cycle is
activated and the GATE pin ramps high. The TIMER pin
continues to be pulled down towards ground.
Start-Up Cycle Without Current Limit
The GATE is released with a 10µA pull-up at time point 4
of Figure 3. At time point 5, GATE reaches the external
MOSFET threshold VTH and VOUT starts to follow the
1
>2.5V
COMP2
100µA
10µA
V
IN
V
ON
V
GATE
RESET
MODE
V
OUT
V
TIMER
2345 6 7
COMP1
4210 F03
5µA
INITIAL
CYCLE
START-UP
CYCLE
NORMAL
CYCLE
DISCHARGE
BY LOAD
V
TH
>1.3V
Figure 3. Normal Operating Sequence
11
LTC4210-3/LTC4210-4
421034fa
APPLICATIO S I FOR ATIO
WUUU
GATE ramp up. If the RSENSE current is below the current
limit, the GATE ramps at a constant rate of:
∆
∆=
V
T
I
C
GATE GATE
GATE
(6)
where C
GATE
is the total capacitance at the GATE pin.
The current through R
SENSE
can be divided into two
components; I
CLOAD
due to the total load capacitance
(C
LOAD
) and I
LOAD
due to the noncapacitive load elements.
The capacitive load typically dominates.
For a successful start-up without current limit, I
RSENSE
<
I
LIMIT
:
I
RSENSE
= I
CLOAD
+ I
LOAD
< I
LIMIT
IC
V
TII
RSENSE LOAD OUT LOAD LIMIT
=∆
∆
⎛
⎝
⎜⎞
⎠
⎟+<•
(7)
Due to the voltage follower configuration, the V
OUT
ramp
rate approximately tracks V
GATE
:
∆
∆=≈∆
∆=
V
T
I
C
V
T
I
C
OUT CLOAD
LOAD
GATE GATE
GATE
(8)
At time point 6, V
OUT
is approximately V
IN
but GATE ramp-
up continues until it reaches a maximum voltage. This
maximum voltage is determined either by the charge
pump or the internal clamp.
Start-Up Cycle With Current Limit
If the duration of the current limit is brief during start-up
(Figure 4) and it did not last beyond the circuit breaker
function time out, the GATE behaves the same as in start-
up without current limit except for the time interval be-
tween time point 5A and time point 5B. The servo amplifier
limits I
RSENSE
by decreasing the I
GATE
current (<10µA).
II mV
R
RSENSE LIMIT SENSE
==
50
Equations 7 and 8 are applicable but with a lower GATE and
V
OUT
ramp rate.
Gate Start-Up Time
The start-up time without current limit is given by:
tC
VV
I
tC
V
STARTUP GATE TH IN
GATE
STARTUP GATE
=+
=
•
•TTH
GATE GATE IN
GATE
ICV
I
+•
VTIMER
VGATE
VOUT
IRSENSE
VON
VIN
>2.5V
12 345 5A5B6 7
RESET
MODE
INITIAL
CYCLE
START-UP
CYCLE
NORMAL
CYCLE
5µA
100µA
COMP1
10µA
10µA
60µA
100µA
DISCHARGE
BY LOAD
REGULATED AT 50mV/RSENSE
VTH
COMP2
2µA
<10µA
4210 F04
>1.3V
Figure 4. Operating Sequence with
Current Limiting at Start-Up Cycle
(9)
(10)
During current limiting, the second term in Equation 10 is
partly modified from CGATE • VIN/IGATE to CLOAD •
VIN/ICLOAD. The start-up time is now given by:
tC
V
ICV
I
C
STARTUP GATE TH
GATE LOAD IN
CLOAD
GA
=+
=
••
TTE TH
GATE LOAD IN
RSENSE LOAD
V
ICV
II
••
–
+
(11)
For successful completion of current limit start-up cycle
there must be a net current to charge C
LOAD
and the
current limit duration must be less than t
CBDELAY
. The
second term in Equation 11 has to fulfill Equation 12.
12
LTC4210-3/LTC4210-4
421034fa
APPLICATIO S I FOR ATIO
WUUU
CV
II
t
LOAD IN
RSENSE LOAD CBDELAY
•–<
(12)
Circuit Breaker Timer Operation
When a current limit fault is encountered at time point A in
Figure 5, the circuit breaker timing is activated with a 60µA
pull-up. The circuit breaker trips at time point B if the fault
is still present and the TIMER pin voltage reaches the
COMP2 threshold and the LTC4210 shuts down. For a
continuous fault, the circuit breaker delay is:
tV
C
A
CBDELAY TIMER
=µ
13 60
.•
(13)
Intermittent overloads may exceed the current limit as in
Figure 6, but if the duration is sufficiently short, the TIMER
pin may not reach the COMP2 threshold and the LTC4210
will not shut down. To handle this situation, the TIMER
discharges with 2µA whenever (V
CC
– SENSE) voltage is
below the 50mV limit and the TIMER voltage is between
the COMP1 and COMP2 thresholds. When the TIMER
voltage falls below the COMP1 threshold, the TIMER pin is
discharged with an equivalent 7k resistor (normal mode,
100µA source) when (V
CC
– SENSE) voltage is below the
50mV limit. If the TIMER pin does not drop below the
COMP1 threshold, any intermittent overload with an ag-
gregate duty cycle of more than 3.8% will eventually trip
the circuit breaker. Figure 7 shows the circuit breaker
response time in seconds normalized to 1µF. The asym-
metric charging and discharging of TIMER is a fair gauge
of MOSFET heating.
t
CsF VF
AD A
TIMER
(/ ) .•
•–
µ= µ
µ
()
µ
13 1
60 2
(14)
When the circuit breaker trips, the GATE pin is pulled low.
The TIMER enters latchoff mode with a 5µA pull-up for the
LTC4210-4 (latched-off version), while an autoretry “cool-
off” cycle begins with a 2µA pull-down for the LTC4210-3
(autoretry version). An autoretry cool-off delay of the
LTC4210-3 between COMP2 and COMP1 thresholds takes:
tV
C
A
COOLOFF TIMER
=µ
11 2
.•
(15)
OVERLOAD DUTY CYCLE, D (%)
10
NORMALIZED RESPONSE TIME (s/µF)
30
1
4210 F07
0.01
0.1
20 100
90
807060
50
40
0
(s/µF) =
t
CTIMER
1.3V • 1µF
60µA • D – 2µA
Figure 7. Circuit Breaker Timer Response
for Intermittent Overload
A1 B1 A2 B2 A3 B3
~50mV/R
SENSE
60µA
CIRCUIT BREAKER
TRIPS
COMP1
4210 F06
COMP2
I
LOAD
V
TIMER
V
GATE
2µA
CB
FAULT
CB
FAULT
CB
FAULT
2µALATCHED OFF (5µA PULL-UP)
OR RETRY (2µA PULL-DOWN)
60µA60µA
10µA10µA
Figure 6. Mulitple Intermittent Overcurrent Conditon
VTIMER
NORMAL
MODE
FAULT
MODE
100µA
COMP1
CIRCUIT BREAKER
TRIPS
LATCHED OFF (5µA PULL-UP)
OR RETRY (2µA PULL-DOWN)
COMP2
AB
60µA
4210 F05
Figure 5. A Continuous Fault Timing
13
LTC4210-3/LTC4210-4
421034fa
APPLICATIO S I FOR ATIO
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Latch-Off After Current Fault (LTC4210-4)
Figure 9 shows the waveforms of the LTC4210-4 (latch-off
version) during a circuit breaker fault. At time point B, the
TIMER trips the COMP2 threshold. The GATE pin pulls to
ground while the TIMER pin is latched high by a 5µA pull-
up. The TIMER pin eventually reaches the soft-clamped
voltage (V
CLAMP
) of 2.3V. To clear the latchoff mode, the
user can either pull the TIMER pin to below 0.2V externally
or cycle the ON pin low for more than 30µs.
Autoretry After Current Fault (LTC4210-3)
Figure 8 shows the waveforms of the LTC4210-3 (autoretry
version) during a circuit breaker fault. At time point B1, the
TIMER trips the COMP2 threshold of 1.3V. The GATE pin
pulls to ground while TIMER begins a “cool-off” cycle with
a 2µA pull-down to the COMP1 threshold of 0.2V. At time
point C1, the TIMER pin pulls down with approximately a
7k resistor to ground and a GATE start-up cycle is initiated.
If the fault persists, the fault autoretry duty cycle is
approximately 3.8%. Pulling the ON pin low for more than
30µs will stop the autoretry function and put the LTC4210
in reset mode.
Figure 8. Automatic Retry After Overcurrent Fault
A1
V
TIMER
V
GATE
V
OUT
I
LOAD
4210 F08
B1 C1 A2 B2
COMP2
COMP1
CB
FAULT
CB
FAULT
NORMAL
MODE
COOL OFF
CYCLE
COOL OFF
CYCLE
60µA
100µA
2µA2µA
60µA
REGULATING AT 50mV/R
SENSE
Normal Mode/External Timer Control
Whenever the TIMER pin voltage drops below the COMP1
threshold, but is not in reset mode, the TIMER enters
normal (100µA source) mode with an equivalent 7k resis-
tive pull-down. Table 1 shows the relationship of t
INITIAL
,
t
CBDELAY
, t
COOLOFF
vs C
TIMER
.
If the TIMER pin is pulled beyond the COMP2 threshold,
the GATE pin is pulled to ground immediately. This allows
the TIMER pin to be used for overvoltage detection, see
Figure 11.
Externally forcing the TIMER pin below the COMP1 thresh-
old will reset the TIMER to normal mode. During over-
voltage detection, the TIMER’s 100µA pull-down current
will continue to be on if (VCC – SENSE) voltage is below
50mV. If the (VCC – SENSE) voltage exceeds 50mV during
the overvoltage detection, the TIMER current will be the
same as described for latched-off or autoretry mode. See
the section OVERVOLTAGE DETECTION USING TIMER
PIN for details of the application.
NORMAL
MODE
LATCHED OFF CYCLE
CB
FAULT
60µA
VTIMER
VGATE
VOUT
ILOAD
AB C
VCLAMP
COMP2
COMP1
0V
0V
2410 F09
REGULATING AT 50mV/RSENSE
Figure 9. Latchoff After Overcurrent Fault
14
LTC4210-3/LTC4210-4
421034fa
APPLICATIO S I FOR ATIO
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Table 1. tINITIAL, tCBDELAY, tCOOLOFF vs CTIMER
C
TIMER
(µF) t
INITIAL
(ms) t
CBDELAY
(ms) t
COOLOFF
(ms)
0.033 9.0 0.7 18.2
0.047 12.8 1 25.9
0.068 18.6 1.5 37.4
0.082 22.4 1.8 45.1
0.1 27.3 2.2 55
0.22 60.0 4.8 121
0.33 90.1 7.2 181.5
0.47 128.3 10.2 258.5
0.68 185.6 14.7 374
0.82 223.8 17.8 451
1 272.9 21.7 550
2.2 600.5 47.7 1210
3.3 900.7 71.5 1815
Power-Off Cycle
The system can be reset by toggling the ON pin low for
more than 30µs as shown at time point 7 of Figure 3. The
GATE pin is pulled to ground. The TIMER capacitor is also
discharged to ground. C
LOAD
discharges through the load.
Alternatively, the TIMER pin can be externally driven above
the COMP2 threshold to turn off the GATE pin.
POWER MOSFET SELECTION
Power MOSFETs can be classified by R
DSON
at V
GS
gate
drive ratings of 10V, 4.5V, 2.5V and 1.8V. Use the typical
curves ∆VGATE vs Supply Voltage and ∆VGATE vs Tem-
perature to determine whether the gate drive voltage is
adequate for the selected MOSFET at the operating volt-
age.
In addition, the selected MOSFET should fulfill two V
GS
criteria:
1. Positive V
GS
absolute maximum rating > LTC4210-3/
LTC4210-4 maximum ∆V
GATE
, and
2. Negative V
GS
absolute maximum rating > supply
voltage. The gate of the MOSFET can discharge faster
than V
OUT
when shutting down the MOSFET with a large
C
LOAD
.
If one of the conditions cannot be met, an external Zener
clamp shown on Figure 10a or Figure 10b can be used. The
selection of R
G
should be within the allowed LTC4210
package dissipation when discharging V
OUT
via the Zener
clamp.
In addition to the MOSFET gate drive rating and V
GS
absolute maximum rating, other criteria such as V
BDSS
,
I
D(MAX)
, R
DS(ON)
, P
D
, θ
JA
, T
J(MAX)
and maximum safe
operating area should also be carefully reviewed. V
BDSS
should exceed the maximum supply voltage inclusive of
spikes and ringing. I
D(MAX)
should be greater than the
current limit, I
LIMIT
. R
DS(ON)
determines the MOSFET V
DS
which together with V
CB
yields an error in the V
OUT
voltage.
At 2.7V supply voltage, the total of V
DS
+ V
CB
of 0.1V yields
3.7% V
OUT
error.
The maximum power dissipated in the MOSFET is
ILIMIT2 • RDS(ON) and this should be less than the maxi-
mum power dissipation, PD allowed in that package.
Given power dissipation, the MOSFET junction tempera-
ture, TJ can be computed from the operating temperature
(TA) and the MOSFET package thermal resistance (θJA).
The operating TJ should be less than the TJ(MAX) specifi-
cation.
Next review the short-circuit condition under maximum
supply V
IN(MAX)
conditions and maximum current limit,
I
LIMIT(MAX)
during the circuit breaker time-out interval of
t
CBDELAY
with the maximum safe operating area of the
MOSFET. The operation during output short-circuit condi-
tions must be well within the manufacturer’s recom-
mended safe operating region with sufficient margin. To
ensure a reliable design, fault tests should be evaluated in
the laboratory.
V
IN
TRANSIENT PROTECTION
Unlike most circuits, Hot Swap controllers typically are
not allowed the good engineering practice of supply
bypass capacitors, since controlling the surge current to
bypass capacitors at plug-in is the primary motivation for
the Hot Swap controller. Although wire harness, back-
plane and PCB trace inductances are usually small, these
can create spikes when currents are suddenly drawn, cut-
off or limited. The transient associated with the GATE turn
15
LTC4210-3/LTC4210-4
421034fa
APPLICATIO S I FOR ATIO
WUUU
off can be controlled with a snubber and/or transient
voltage suppressor. RC snubber networks are effective
for LTC4210-3/LTC4210-4 applications. The choice of
RC is usually determined experimentally. The value of the
snubber capacitor is usually chosen between 10 to 100
times the MOSFET COSS. The value of the snubber resistor
is typically between 3Ω to 100Ω. A snubber network is
normally sufficient to protect against transient voltages.
However, when input wires are long or EMI beads exist in
the wire harness, a transient suppressor should be used
in conjuction with the snubber to clip off voltage spikes
and reduce ringing. In many cases, a simple short-circuit
test can be performed to determine the need of the
transient voltage suppressor.
OVERVOLTAGE DETECTION USING THE TIMER PIN
Figure 11 shows a supply side overvoltage detection
circuit. A Zener diode, a diode and COMP2 threshold sets
the overvoltage threshold. Resistor R
B
biases the Zener
diode voltage. Diode D1 blocks forward current in the
Zener during start-up or output short-circuit. R
TIMER
with
C
TIMER
sets the overload noise filter.
RELATED PARTS
1.50 – 1.75
(NOTE 4)
2.80 BSC
0.30 – 0.45
6 PLCS (NOTE 3)
DATUM ‘A’
0.09 – 0.20
(NOTE 3)
S6 TSOT-23 0302
2.90 BSC
(NOTE 4)
0.95 BSC
1.90 BSC
0.80 – 0.90
1.00 MAX 0.01 – 0.10
0.20 BSC
0.30 – 0.50 REF
PIN ONE ID
NOTE:
1. DIMENSIONS ARE IN MILLIMETERS
2. DRAWING NOT TO SCALE
3. DIMENSIONS ARE INCLUSIVE OF PLATING
4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR
5. MOLD FLASH SHALL NOT EXCEED 0.254mm
6. JEDEC PACKAGE REFERENCE IS MO-193
3.85 MAX
0.62
MAX
0.95
REF
RECOMMENDED SOLDER PAD LAYOUT
PER IPC CALCULATOR
1.4 MIN
2.62 REF
1.22 REF
S6 Package
6-Lead Plastic TSOT-23
(Reference LTC DWG # 05-08-1636)
16
LTC4210-3/LTC4210-4
421034fa
LT 1106 REV A• PRINTED IN USA
© LINEAR TECHNOLOGY CORPORATION 2006
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900
●
FAX: (408) 434-0507
●
www.linear.com
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1421 Two Channel, Hot Swap Controller Operates from 3V to 12V and Supports –12V
LTC1422 Single Channel, Hot Swap Controller in SO-8 Operates from 2.7V to 12V, Reset Output
LT1640AL/LT1640AH Negative Voltage Hot Swap Controller in SO-8 Operates from –10V to –80V
LTC1642 Single Channel, Hot Swap Controller Overvoltage Protection to 33V, Foldback Current Limiting
LTC1643AL/LTC1643AH PCI Hot Swap Controller 3.3V, 5V, Internal FETs for ±12V
LTC1647 Dual Channel, Hot Swap Controller Operates from 2.7V to 16.5V, Separate ON pins for Sequencing
LTC4211 Single Channel, Hot Swap Controller 2.5V to 16.5V, Multifunction Current Control
LTC4230 Triple Channel, Hot Swap Controller 1.7V to 16.5V, Multifunction Current Control
LTC4251 –48V Hot Swap Controller in SOT-23 Floating Supply, Three-Level Current Limiting
LTC4252 –48V Hot Swap Controller in MSOP Floating Supply, Power Good, Three-Level Current Limiting
LTC4253 –48V Hot Swap Controller with Triple Supply Sequencing Floating Supply, Three-Level Current Limiting
TYPICAL APPLICATIO
U
D1*
Q1
GATE
(10a) (10b)
RSENSE
VOUT
RG
200Ω
VCC D2*D1*
Q1
GATE
RSENSE
VOUT
RG
200Ω
*USER SELECTED VOLTAGE CLAMP
(A LOW BIAS CURRENT ZENER DIODE
IS RECOMMENDED)
1N4688 (5V)
VCC
Figure 10. Gate Protection Zener Clamp
Figure 11. Supply Side Overvoltage Protection
+
V
CC
SENSE
LTC4210-3
6
3
1
2
5
C
LOAD
470µF
V
OUT
5V
4A
GND
4210 F11
4
R4
100Ω
GATE
GND
TIMER
ON
SHORT
LONG
V
IN
5V
GND LONG
R
ON2
10k
R
ON1
20k
R
X
10Ω
R
SENSE
0.01Ω
PCB EDGE
CONNECTOR
(MALE) Q1
Si4410DY
Z1
R
TIMER
18Ω
R
G
100Ω
C
TIMER
0.22µF
C
X
0.1µF
C
C
10nF
Z2
D1
1N4148
BACKPLANE
CONNECTOR
(FEMALE)
R
B
10k
Z1: SMAJ10A Z2: BZX84C6V2
APPLICATIO S I FOR ATIO
WUUU
