IS63LV1024L ISSI®
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 1
Rev. B
08/07/02
Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
128K x 8 HIGH-SPEED CMOS STATIC RAM
3.3V REVOLUTIONARY PINOUT
FEATURES
• High-speed access times:
8, 10, 12 ns
• High-performance, low-power CMOS process
• Multiple center power and ground pins for
greater noise immunity
• Easy memory expansion with CE and OE
options
•CE power-down
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 3.3V power supply
• Packages available:
– 32-pin 300-mil SOJ
– 32-pin 400-mil SOJ
DESCRIPTION
The ISSI IS63LV1024L is a very high-speed, low power,
131,072-word by 8-bit CMOS static RAM in revolutionary
pinout. The IS63LV1024L is fabricated using ISSI's
high-performance CMOS technology. This highly reliable
process coupled with innovative circuit design
techniques, yields higher performance and low power
consumption devices.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 250 µW (typical) with CMOS input levels.
The IS63LV1024L operates from a single 3.3V power
supply and all inputs are TTL-compatible.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
CE
OE
WE
128K X 8
MEMORY ARRAY
DECODER
COLUMN I/O
CONTROL
CIRCUIT
GND
VCC
I/O
DATA
CIRCUIT
I/O0-I/O7
AUGUST 2002
– 32-pin TSOP (Type II)
– 32-pin STSOP (Type I)
– 36-pin BGA (8mmx10mm)
2Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
08/07/02
IS63LV1024L ISSI
®
PIN CONFIGURATION
32-Pin SOJ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A0
A1
A2
A3
CE
I/O0
I/O1
Vcc
GND
I/O2
I/O3
WE
A4
A5
A6
A7
A16
A15
A14
A13
OE
I/O7
I/O6
GND
Vcc
I/O5
I/O4
A12
A11
A10
A9
A8
PIN DESCRIPTIONS
A0-A16 Address Inputs
CE Chip Enable Input
OE Output Enable Input
WE Write Enable Input
I/O0-I/O7 Bidirectional Ports
Vcc Power
GND Ground
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A0
A1
A2
A3
CE
I/O0
I/O1
Vcc
GND
I/O2
I/O3
WE
A4
A5
A6
A7
A16
A15
A14
A13
OE
I/o7
I/O6
GND
Vcc
I/O5
I/O4
A12
A11
A10
A9
A8
PIN CONFIGURATION
32-Pin TSOP (Type II) (T)
32-Pin STSOP (Type I) (H)
PIN CONFIGURATION
36-mini BGA (B) (8 mm x 10 mm)
1 2 3 4 5 6
A
B
C
D
E
F
G
H
A0 A1 NC A3 A6 A8
I/O4 A2 WE A4 A7 I/O
0
I/O5 NC A5 I/O
1
GND Vcc
Vcc GND
I/O6 NC NC I/O
2
I/O7 OE CE A16 A15 I/O
3
A9 A10 A11 A12 A13 A14
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 3
Rev. B
08/07/02
IS63LV1024L ISSI
®
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
VTERM Terminal Voltage with Respect to GND –0.5 to Vcc + 0.5 V
TBIAS Temperature Under Bias –55 to +125 °C
TSTG Storage Temperature –65 to +150 ° C
PTPower Dissipation 1.0 W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
TRUTH TABLE
Mode WEWE
WEWE
WE CECE
CECE
CE OEOE
OEOE
OE I/O Operation Vcc Current
Not Selected X H X High-Z ISB1, I SB2
(Power-down)
Output Disabled H L H High-Z ICC1, ICC2
Read H L L DOUT ICC1, ICC2
Write L L X DIN ICC1, ICC2
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 — V
VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA — 0.4 V
VIH Input HIGH Voltage 2.2 VCC + 0.3 V
VIL Input LOW Voltage(1) –0.3 0.8 V
ILI Input Leakage GND ≤ VIN ≤ VCC Com. –1 1 µA
Ind. –5 5
ILO Output Leakage GND ≤ VOUT ≤ VCC, Outputs Disabled Com. –1 1 µA
Ind. –5 5
Notes:
1. VIL = –3.0V for pulse width less than 10 ns.
OPERATING RANGE
Range Ambient Temperature VCC
Commercial 0°C to +70°C 3.3V ± 0.3V
Industrial –40°C to +85°C 3.3V ± 0.15V
4Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
08/07/02
IS63LV1024L ISSI
®
CAPACITANCE(1,2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 6 pF
CI/O Input/Output Capacitance VOUT = 0V 8 p F
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.
POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
-8 ns -10 ns -12 ns
Symbol Parameter Test Conditions Min. Max. Min. Max. Min. Max. Unit
ICC1Vcc Operating VCC = Max., CE = VIL Com. — 100 — 95 — 90 mA
Supply Current IOUT = 0 mA, f = Max. Ind. — 1 10 — 1 05 — 1 00
ISB TTL Standby VCC = Max., Com. — 3 5 — 3 0 — 2 5 mA
Current VIN = VIH or VIL Ind. — 40 — 35 — 30
(TTL Inputs) CE ≥ VIH, f = Max
ISB1TTL Standby VCC = Max., Com. — 1 5 — 1 5 — 1 5 mA
Current VIN = VIH or VIL Ind. — 20 — 20 — 20
(TTL Inputs) CE ≥ VIH, f = 0
ISB2CMOS Standby VCC = Max., Com. — 1 — 1 — 1 mA
Current CE ≤ VCC – 0.2V, Ind. — 1.5 — 1.5 — 1.5
(CMOS Inputs) VIN ≥ VCC – 0.2V, or
VIN ≤ 0.2V, f = 0
Notes:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 5
Rev. B
08/07/02
IS63LV1024L ISSI
®
AC TEST LOADS
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 3 ns
Input and Output Timing 1.5V
and Reference Levels
Output Load See Figures 1a and 1b
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
-8 ns -10 ns -12 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tRC Read Cycle Time 8 — 1 0 — 1 2 — n s
tAA Address Access Time — 8 — 10 — 1 2 ns
tOHA Output Hold Time 2 — 2 — 2 — n s
tACE CE Access Time — 8 — 1 0 — 1 2 n s
tDOE OE Access Time — 4 — 5 — 6 ns
tLZOE
(2)
OE to Low-Z Output 0 — 0 — 0 — n s
tHZOE
(2)
OE to High-Z Output 0 4 0 5 0 6 ns
tLZCE
(2)
CE to Low-Z Output 3 — 3 — 3 — n s
tHZCE
(2)
CE to High-Z Output 0 4 0 5 0 6 ns
tPU CE to Power Up Time 0 — 0 — 0 — ns
tPD CE to Power Down Time — 8 — 1 0 — 12 ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and C1
output loading specified in Figure 1.
2. Tested with the C2 load in Figure 1. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
Figure 1
OUTPUT
VT = 1.5V
ZOUT = 50 Ω
50 Ω
317 Ω
5 pF
Including
jig and
scope
351 Ω
OUTPUT
3.3V
Figure 2
6Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
08/07/02
IS63LV1024L ISSI
®
DATA VALID
READ1.eps
PREVIOUS DATA VALID
t AA
t OHA t OHA
t RC
DOUT
ADDRESS
t RC
t OHA
t AA
t DOE
t LZOE
t ACE
t LZCE
t HZOE
HIGH-Z DATA VALID
CE_RD2.eps
ADDRESS
OE
CE
D
OUT
t HZCE
READ CYCLE NO. 2(1,3)
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE = VIL.
3. Address is valid prior to or coincident with CE LOW transitions.
AC WAVEFORMS
READ CYCLE NO. 1(1,2)
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 7
Rev. B
08/07/02
IS63LV1024L ISSI
®
WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range)
-8 ns -10 ns -12 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tWC Write Cycle Time 8 — 1 0 — 1 2 — n s
tSCE CE to Write End 7 — 7 — 8 — ns
tAW Address Setup Time to 8 — 8 — 8 — ns
Write End
tHA Address Hold from 0 — 0 — 0 — ns
Write End
tSA Address Setup Time 0 — 0 — 0 — ns
tPWE
1(1)
WE Pulse Width (OE High) 7 — 7 — 8 — ns
tPWE
2(2)
WE Pulse Width (OE Low) 8 — 10 — 12 — ns
tSD Data Setup to Write End 5 — 5 — 6 — n s
tHD Data Hold from Write End 0 — 0 — 0 — ns
tHZWE
(2)
WE LOW to High-Z Output — 4 — 5 — 6 ns
tLZWE
(2)
WE HIGH to Low-Z Output 3 — 3 — 3 — ns
Notes:
1. Test conditions assume signal transition times of 3ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and
output loading specified in Figure 1a.
2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
3. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write, but
any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of
the signal that terminates the Write.
AC WAVEFORMS
WRITE CYCLE NO. 1(1,2 (CE Controlled, OE = HIGH or LOW)
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCE
t
PWE1
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN DATA
IN
VALID
t
LZWE
t
SD
CE_WR1.e
p
s
8Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. B
08/07/02
IS63LV1024L ISSI
®
AC WAVEFORMS
WRITE CYCLE NO. 2(1)
(WE Controlled, OE = HIGH during Write Cycle)
WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)
Notes:
1. The internal write time is defined by the overlap of CE LOW and WE LOW. All signals must be in valid states to initiate a Write,
but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling
edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if OE • VIH.
DATA UNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
DOUT
DIN
OE
DATA
IN
VALID
t
LZWE
t
SD
CE_WR2.e
p
s
DATA UNDEFINED
t
WC
VALID ADDRESS
LOW
LOW
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
CE_WR3.eps
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 9
Rev. B
08/07/02
IS63LV1024L ISSI
®
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed (ns) Order Part No. Package
8 IS63LV1024L-8T TSOP (Type II)
IS63LV1024L-8H STSOP (Type I) (8mm x13.4mm)
IS63LV1024L-8J 300-mil Plastic SOJ
IS63LV1024L-8K 400-mil Plastic SOJ
IS63LV1024L-8B mBGA(8mmx10mm)
1 0 IS63LV1024L-10T TSOP (Type II)
IS63LV1024L-10J 300-mil Plastic SOJ
IS63LV1024L-10K 400-mil Plastic SOJ
IS63LV1024L-10B mBGA(8mmx10mm)
1 2 IS63LV1024L-12T TSOP (Type II)
IS63LV1024L-12H STSOP (Type I) (8mm x13.4mm)
IS63LV1024L-12J 300-mil Plastic SOJ
IS63LV1024L-12K 400-mil Plastic SOJ
IS63LV1024L-12B mBGA(8mmx10mm)
Industrial Range: –40°C to +85°C
Speed (ns) Order Part No. Package
8 IS63LV1024L-8TI TSOP (Type II)
IS63LV1024L-8JI 300-mil Plastic SOJ
IS63LV1024L-8KI 400-mil Plastic SOJ
IS63LV1024L-8BI mBGA(8mmx10mm)
1 0 IS63LV1024L-10TI TSOP (Type II)
IS63LV1024L-10HI STSOP (Type I) (8mm x13.4mm)
IS63LV1024L-10JI 300-mil Plastic SOJ
IS63LV1024L-10KI 400-mil Plastic SOJ
IS63LV1024L-10BI mBGA(8mmx10mm)
1 2 IS63LV1024L-12TI TSOP (Type II)
IS63LV1024L-12JI 300-mil Plastic SOJ
IS63LV1024L-12KI 400-mil Plastic SOJ
IS63LV1024L-12BI mBGA(8mmx10mm)
