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TMS320DM335
Digital Media System-on-Chip (DMSoC)
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1 Digital Media System-on-Chip (DMSoC)
1.1 TMS320DM335 Features
123 – EmbeddedICE-RT™ Logic for Real-Time
• Highlights Debug
– High-Performance Digital Media • ARM9 Memory Architecture
System-On-Chip (DMSoC) – 16K-Byte Instruction Cache
– Up to 216-MHz ARM926EJ-S™ Clock Rate – 8K-Byte Data Cache
– Digital HDTV (720p/1080i) output for
connection to external encoder – 32K-Byte RAM
– Video Processing Subsystem – 8K-Byte ROM
• Hardware IPIPE for Real-Time Image – Little Endian
Processing • Video Processing Subsystem
• Up to 14-bit CCD/CMOS Digital Interface – Front End Provides:
• Histogram Module • Hardware IPIPE for Real-Time Image
• Resize Image 1/16x to 8x Processing
• Hardware On-Screen Display • Up to 14-bit CCD/CMOS Digital Interface
• Up to 75-MHz Pixel Clock • 16-/8-bit Generic YcBcR-4:2 Interface
(BT.601)
• Composite NTSC/PAL video encoder
output • 10-/8-bit CCIR6565/BT655 Interface
– Peripherals include DDR and mDDR SDRAM, • Up to 75-MHz Pixel Clock
2 MMC/SD/SDIO and SmartMedia Flash Card • Histogram Module
Interfaces, USB 2.0, 3 UARTs and 3 SPIs • Resize Engine
– Enhanced Direct-Memory-Access (EDMA) – Resize Images From 1/16x to 8x
– Configurable Power-Saving Modes – Separate Horizontal/Vertical Control
– On-Chip ARM ROM Bootloader (RBL) to Boot – Two Simultaneous Output Paths
From NAND Flash, MMC/SD, or UART – Back End Provides:
– 3.3-V and 1.8-V I/O, 1.3-V Core • Hardware On-Screen Display (OSD)
– Debug Interface Support • Composite NTSC/PAL video encoder
– Up to 104 General-Purpose I/O (GPIO) Pins output
– 337-Pin Ball Grid Array at 65 nm Process • 8-/16-bit YCC and Up to 18-Bit RGB666
Technology Digital Output
• High-Performance Digital Media • BT.601/BT.656 Digital YCbCr 4:2:2
System-on-Chip (DMSoC) (8-/16-Bit) Interface
– 135-, 216-MHz ARM926EJ-S™ Clock Rate • Digital HDTV (720p/1080i) output for
– Fully Software-Compatible With ARM™ connection to external encoder
– Extended Temperature 135- and 216-MHz • External Memory Interfaces (EMIFs)
Devices are Available – DDR2 and mDDR SDRAM 16-bit wide EMIF
• ARM926EJ-S Core With 256 MByte Address Space (1.8-V I/O)
– Support for 32-Bit and 16-Bit (Thumb Mode) – Asynchronous16-/8-bit Wide EMIF (AEMIF)
Instruction Sets • Flash Memory Interfaces
– DSP Instruction Extensions and Single Cycle – NAND (8-/16-bit Wide Data)
MAC – OneNAND(16-bit Wide Data)
– ARM® Jazelle® Technology • Flash Card Interfaces
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2Windows is a trademark of Microsoft.
3All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2008–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TMS320DM335
SPRS528C–JULY 2008–REVISED JUNE 2010
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– Two Multimedia Card (MMC) / Secure Digital • Four Pulse Width Modulator (PWM) Outputs
(SD/SDIO) • Four RTO (Real Time Out) Outputs
– SmartMedia • Up to 104 General-Purpose I/O (GPIO) Pins
• Enhanced Direct-Memory-Access (EDMA) (Multiplexed with Other Device Functions)
Controller (64 Independent Channels) • On-Chip ARM ROM Bootloader (RBL) to Boot
• USB Port with Integrated 2.0 High-Speed PHY from NAND Flash (with SPI EEPROM Boot
that Supports option), MMC/SD, or UART
– USB 2.0 Full and High-Speed Device • Configurable Power-Saving Modes
– USB 2.0 Low, Full, and High-Speed Host • Crystal or External Clock Input (typically
24 MHz or 36 MHz)
• Three 64-Bit General-Purpose Timers (each
configurable as two 32-bit timers) • Flexible PLL Clock Generators
• One 64-Bit Watch Dog Timer • Debug Interface Support
• Three UARTs (One fast UART with RTS and – IEEE-1149.1 (JTAG)
CTS Flow Control) Boundary-Scan-Compatible
• Three Serial Port Interfaces (SPI) each with two – ETB™ (Embedded Trace Buffer™) with
Chip-Selects 4K-Bytes Trace Buffer memory
• One Master/Slave Inter-Integrated Circuit (I2C) – Device Revision ID Readable by ARM
Bus® • 337-Pin Ball Grid Array (BGA) Package
• Two Audio Serial Port (ASP) (ZCE Suffix), 0.65-mm Ball Pitch
– I2S and TDM I2S • 90nm Process Technology
– AC97 Audio Codec Interface • 3.3-V and 1.8-V I/O, 1.3-V Internal
– S/PDIF via Software • Community Resources
– Standard Voice Codec Interface (AIC12) – TI E2E Community
– SPI Protocol (Master Mode Only) – TI Embedded Processors Wiki
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1.2 Description
The DM335 processor is a low-cost, low-power processor providing advanced graphical user interface for
display applications that do not require video compression and decompression. Coupled with a video
processing subsystem (VPSS) that provides 720p display, the DM335 processor is powered by a
135/216-MHz ARM926EJ-S core so developers can create feature-rich graphical user interfaces allowing
customers to interact with their portable, electronic devices such as video-enabled universal remote
controls, Internet radio, e-books, video doorbells, and digital telescopes. The new DM335 is packed with
the same peripherals as its predecessor, the TMS320DM355 device, including high-speed USB 2.0
on-the-go, external memory interface (EMIF), mobile DDR/DDR2, two SDIO ports, three UART Ports, two
Audio Serial Ports, three SPI Ports, and SLC/MCL NAND Flash memory support. These peripherals help
customers create DM335 processor-based designs that add video and audio excitement to a wide range
of today's static user-interface applications while keeping silicon costs and power consumption low. The
new digital media processor is completely scalable with the DM355 processor and Digital Video Evaluation
Board (DVEVM), allowing customers to utilize their same code for their new DM335 processor focused
designs.
The new DM335 device delivers a sophisticated suite of capabilities allowing for flexible image capture
and display. Through its user interface technology, such as a four-level on-screen display, developers are
able to create picture-within-picture and video-within-video as well as innovative graphic user interfaces.
This is especially important for portable products that require the use of button or touch screen, such as
portable karaoke, video surveillance and electronic gaming applications. Additional advanced capture and
imaging technologies include support for CCD/CMOS image sensors, resize capability and video
stabilization. The 1280-by-960-pixel digital LCD connection runs on a 75-MHz pixel clock and supports TV
composite output for increased expandability. This highly integrated device is packaged in a 13 x 13 mm,
337 pin , 0.65 mm pitch BGA package.
The DM335 processor core is an ARM926EJ-S RISC processor. The ARM926EJ-S is a 32-bit processor
core that performs 32-bit and 16-bit instructions and processes 32-bit, 16-bit, and 8-bit data. The core
uses pipelining so that all parts of the processor and memory system can operate continuously. The ARM
core incorporates:
• A coprocessor 15 (CP15) and protection module
• Data and program Memory Management Units (MMUs) with table look-aside buffers.
• Separate 16K-byte instruction and 8K-byte data caches. Both are four-way associative with virtual
index virtual tag (VIVT).
The DM335 device has a Video Processing Subsystem (VPSS) with two configurable video/imaging
peripherals:
• A Video Processing Front-End (VPFE)
• A Video Processing Back-End (VPBE)
The VPFE port provides an interface for CCD/CMOS imager modules and video decoders. The VPBE
provides hardware On Screen Display (OSD) support and composite NTSC/PAL and digital LCD output.
The DM335 peripheral set includes:
• An inter-integrated circuit (I2C) Bus interface
• Two audio serial ports (ASP)
• Three 64-bit general-purpose timers each configurable as two independent 32-bit timers
• A 64-bit watchdog timer
• Up to 104-pins of general-purpose input/output (GPIO) with programmable interrupt/event generation
modes, multiplexed with other peripherals
• Three UARTs with hardware handshaking support on one UART
• Three serial port Interfaces (SPI)
• Four pulse width modulator (PWM) peripherals
• Four real time out (RTO) outputs
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Peripherals
64bitDMA/DataBus
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microphone
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TMS320DM335
SPRS528C–JULY 2008–REVISED JUNE 2010
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• Two Multi-Media Card / Secure Digital (MMC/SD/SDIO) interfaces
• Wireless interfaces (Bluetooth, WLAN, WUSB) through SDIO
• A USB 2.0 full and high-speed device and host interface
• Two external memory interfaces:
– An asynchronous external memory interface (AEMIF) for slower memories/peripherals such as
NAND and OneNAND,
– A high speed synchronous memory interface for DDR2/mDDR.
For software development support the DM335 has a complete set of ARM development tools which
include: C compilers, assembly optimizers to simplify programming and scheduling, and a Windows™
debugger interface for visibility into source code execution.
1.3 Functional Block Diagram
The below figure shows the functional block diagram of the DM335 device.
Figure 1-1. Functional Block Diagram
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1 Digital Media System-on-Chip (DMSoC) ............ 13.8 System Control Module ............................. 78
1.1 TMS320DM335 Features ............................ 13.9 Pin Multiplexing ..................................... 79
1.2 Description ........................................... 33.10 Device Reset ....................................... 80
3.11 Default Device Configurations ...................... 81
1.3 Functional Block Diagram ............................ 43.12 Device Boot Modes ................................. 85
Revision History .............................................. 63.13 Power Management ................................ 89
2 Device Overview ........................................ 73.14 64-Bit Crossbar Architecture ....................... 91
2.1 Device Characteristics ............................... 74 Device Operating Conditions ....................... 95
2.2 Memory Map Summary .............................. 84.1 Absolute Maximum Ratings Over Operating Case
2.3 Pin Assignments .................................... 10 Temperature Range
2.4 Pin Functions ....................................... 14 (Unless Otherwise Noted) ................................. 95
2.5 Image Data Output - Video Processing Back End 4.2 Recommended Operating Conditions .............. 96
(VPBE) .............................................. 16 4.3 Electrical Characteristics Over Recommended
2.6 Asynchronous External Memory Interface (AEMIF) Ranges of Supply Voltage and Operating Case
...................................................... 19 Temperature (Unless Otherwise Noted) ............ 97
5 DM335 Peripheral Information and Electrical
2.7 DDR Memory Interface ............................. 21 Specifications .......................................... 98
2.8 GPIO ................................................ 23 5.1 Parameter Information Device-Specific Information
2.9 Multi-Media Card/Secure Digital (MMC/SD) ...................................................... 98
Interfaces ........................................... 28 5.2 Recommended Clock and Control Signal Transition
2.10 Universal Serial Bus (USB) Interface ............... 29 Behavior ............................................ 99
2.11 Audio Interfaces .................................... 30 5.3 Power Supplies ..................................... 99
5.4 Reset .............................................. 101
2.12 UART Interface ..................................... 31 5.5 Oscillators and Clocks ............................ 102
2.13 I2C Interface ........................................ 32 5.6 General-Purpose Input/Output (GPIO) ............ 107
2.14 Serial Interface ..................................... 32 5.7 External Memory Interface (EMIF) ................ 109
2.15 Clock Interface ...................................... 33 5.8 MMC/SD ........................................... 117
2.16 Real Time Output (RTO) Interface ................. 34 5.9 Video Processing Sub-System (VPSS) Overview
..................................................... 119
2.17 Pulse Width Modulator (PWM) Interface ........... 34 5.10 USB 2.0 ........................................... 131
2.18 System Configuration Interface ..................... 35 5.11 Universal Asynchronous Receiver/Transmitter
2.19 Emulation ........................................... 36 (UART) ............................................ 133
2.20 Pin List .............................................. 37 5.12 Serial Port Interface (SPI) ......................... 135
2.21 Device Support ..................................... 56 5.13 Inter-Integrated Circuit (I2C) ...................... 138
3 Detailed Device Description ......................... 61 5.14 Audio Serial Port (ASP) ........................... 141
3.1 ARM Subsystem Overview ......................... 61 5.15 Timer .............................................. 149
3.2 ARM926EJ-S RISC CPU ........................... 62 5.16 Pulse Width Modulator (PWM) .................... 150
3.3 Memory Mapping ................................... 64 5.17 Real Time Out (RTO) ............................. 152
3.4 ARM Interrupt Controller (AINTC) .................. 65 5.18 IEEE 1149.1 JTAG ................................ 153
3.5 Device Clocking .................................... 67 6 Mechanical Data ...................................... 156
3.6 PLL Controller (PLLC) .............................. 74 6.1 Thermal Data for ZCE ............................. 156
3.7 Power and Sleep Controller (PSC) ................. 78 6.2 Packaging Information ............................ 156
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Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
This data sheet revision history highlights the technical changes made to the SPRS528B device-specific
data sheet to make it an SPRS528Crevision.
Scope: Applicable updates to the DM335 device family, specifically relating to the DM335 device, have
been incorporated. The A135 and A216 DM335 devices both support extended temperature.
Revision C Updates
ADDS/CHANGES/DELETES
Global Added SPI EEPROM Boot option to NAND.
Section 1.1 Changed Feature bullet from NAND Flash to NAND Flash (with SPI EEPROM Boot option).
Section 2.4 Table 2-9 and Table 2-11:
• Added "Used to drive boot status LED signal (active low) in ROM boot modes." to pin number
P16.
• Deleted "Used to drive boot status LED signal (active low) in ROM boot modes." from pin
number V19.
Section 2.20 Updated Table 2-23, changed Reset State values.
Section 2.21.2 Updated Figure 2-5 Device Nomenclature.
Section 3.2.4 Changed NAND to NAND (with SPI EEPROM Boot option).
Section 3.5 Table 3-4:
• Updated/Changed "(/2 or /1 programmable)" to "POSTDIV" and added "(/2 or /1
programmable)" to 2nd row.
Table 3-15 Updated BTSEL Function and NAND configuration in table.
Table 3-16 Updated table:
• Changed BTSEL[1:0] = 00 – Enable (NAND) to BTSEL[1:0] = 00 – Enable (NAND, SPI)
Changed SPI0 Module State from SyncRst to:
• BTSEL[1:0] = 00 – Enable (NAND, SPI)
• BTSEL[1:0] = 01 – SyncRst (OneNAND)
• BTSEL[1:0] = 10 – Enable (MMC/SD)
• BTSEL[1:0] = 11 – Enable (UART)
Section 3.12 Added Section 3.12.2, "RBL NAND Boot Process" and associated Standard and Compatibility
mode references throughout the document.
Section 3.12.1 Added ARM ROM Boot - SPI boot in NAND Mode bullet and sub-bullets.
Figure 3-6 Added SPI Flash to Diagram.
Section 4.2 Added last row to table including table note.
Section 4.3 Updated/Changed the following values in Section 4.3:
• IOH MAX value from "-100 mA" to "-4000 mA"
• IOZ TYP (IPU disabled) value from "±10 µA" to "±20 µA"
• IOZ TYP (IPU enabled) added value of ±100 µA"
Added "Test Conditions" for IOH and IOL parameters
Table 5-5 Changed parameter 4 on table and added table note.
Table 5-6 Changed parameter 4 on table and added table note.
Table 5-45 Changed parameter 4 on table and added table note.
Section 5.7.1.3 Added note to Table 5-14.
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2 Device Overview
2.1 Device Characteristics
Table 2-1 provides an overview of the DMSoC. The table shows significant features of the device,
including the peripherals, capacity of on-chip RAM, ARM operating frequency, the package type with pin
count, etc.
Table 2-1. Characteristics of the Processor
HARDWARE FEATURES DM335
DDR2 / mDDR Memory Controller DDR2 / mDDR (16-bit bus width)
Asynchronous (8/16-bit bus width)
Asynchronous EMIF (AEMIF) RAM, Flash (NAND, OneNAND)
Two MMC/SD
Flash Card Interfaces One SmartMedia/xD
64 independent DMA channels
EDMA Eight EDMA channels
Three 64-Bit General Purpose (each
configurable as two separate 32-bit
Timers timers)
Peripherals One 64-Bit Watch Dog
Not all peripherals pins are Three (one with RTS and CTS flow
available at the same time UART control)
(For more detail, see the
Device Configuration Three (each supports two slave
SPI
section). devices)
I2C One (Master/Slave)
Audio Serial Port [ASP] Two ASP
General-Purpose Input/Output Port Up to 104
Pulse width modulator (PWM) Four outputs
One Input (VPFE)
Configurable Video Ports One Output (VPBE)
High, Full Speed Device
USB 2.0 High, Full, Low Speed Host
ARM
On-Chip CPU Memory Organization 16-KB I-cache, 8-KB D-cache,
32-KB RAM, 8-KB ROM
JTAG BSDL_ID JTAGID register (address location: 0x01C4 0028) 0x0B73B01F
CPU Frequency (Maximum) MHz ARM 135, 216 MHz
Core (V) 1.3 V
Voltage I/O (V) 3.3 V, 1.8 V
Reference frequency options 24 MHz (typical), 36 MHz
PLL Options Configurable PLL controller PLL bypass, programmable PLL
BGA Package 13 x 13 mm 337-Pin BGA (ZCE)
Process Technology 90 nm
Product Preview (PP),
Product Status(1) Advance Information (AI), PD
or Production Data (PD)
(1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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2.2 Memory Map Summary
Table 2-3 shows the memory map address ranges of the device. Table 2-3 depicts the expanded map of
the Configuration Space (0x01C0 0000 through 0x01FF FFFF). The device has multiple on-chip memories
associated with its processor and various subsystems. To help simplify software development a unified
memory map is used where possible to maintain a consistent view of device resources across all bus
masters. The bus masters are the ARM, EDMA, USB, and VPSS.
Table 2-2. DM335 Memory Map
Start Address End Address Size (Bytes) ARM EDMA USB VPSS
Mem Map Mem Map Mem Map Mem Map
0x0000 0000 0x0000 3FFF 16K ARM RAM0
(Instruction)
0x0000 4000 0x0000 7FFF 16K ARM RAM1 Reserved Reserved
(Instruction)
0x0000 8000 0x0000 FFFF 32K ARM ROM
(Instruction)
- only 8K used
0x0001 0000 0x0001 3FFF 16K ARM RAM0 (Data) ARM RAM0 ARM RAM0
0x0001 4000 0x0001 7FFF 16K ARM RAM1 (Data) ARM RAM1 ARM RAM1
0x0001 8000 0x0001 FFFF 32K ARM ROM (Data) ARM ROM ARM ROM
- only 8K used
0x0002 0000 0x000F FFFF 896K Reserved
0x0010 0000 0x01BB FFFF 26M
0x01BC 0000 0x01BC 0FFF 4K ARM ETB Mem
0x01BC 1000 0x01BC 17FF 2K ARM ETB Reg Reserved
0x01BC 1800 0x01BC 18FF 256 ARM IceCrusher Reserved
0x01BC 1900 0x01BC FFFF 59136 Reserved
0x01BD 0000 0x01BF FFFF 192K
0x01C0 0000 0x01FF FFFF 4M CFG Bus CFG Bus Reserved
Peripherals Peripherals
0x0200 0000 0x09FF FFFF 128M ASYNC EMIF (Data) ASYNC EMIF (Data)
0x0A00 0000 0x11EF FFFF 127M - 16K
0x11F0 0000 0x11F1 FFFF 128K Reserved Reserved
0x11F2 0000 0x1FFF FFFF 141M-64K
0x2000 0000 0x2000 7FFF 32K DDR EMIF Control DDR EMIF Control
Regs Regs
0x2000 8000 0x41FF FFFF 544M-32K Reserved
0x4200 0000 0x49FF FFFF 128M Reserved Reserved
0x4A00 0000 0x7FFF FFFF 864M Reserved
0x8000 0000 0x8FFF FFFF 256M DDR EMIF DDR EMIF DDR EMIF DDR EMIF
0x9000 0000 0xFFFF FFFF 1792M Reserved Reserved Reserved Reserved
Table 2-3. DM335 ARM Configuration Bus Access to Peripherals
Address Accessibility
Region Start End Size ARM EDMA
EDMA CC 0x01C0 0000 0x01C0 FFFF 64K √ √
EDMA TC0 0x01C1 0000 0x01C1 03FF 1K √ √
EDMA TC1 0x01C1 0400 0x01C1 07FF 1K √ √
Reserved 0x01C1 0800 0x01C1 9FFF 38K √ √
Reserved 0x01C1 A000 0x01C1 FFFF 24K √ √
UART0 0x01C2 0000 0x01C2 03FF 1K √ √
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Table 2-3. DM335 ARM Configuration Bus Access to Peripherals (continued)
Address Accessibility
UART1 0x01C2 0400 0x01C2 07FF 1K √ √
Timer4/5 0x01C2 0800 0x01C2 0BFF 1K √ √
Real-time out 0x01C2 0C00 0x01C2 0FFF 1K √ √
I2C 0x01C2 1000 0x01C2 13FF 1K √ √
Timer0/1 0x01C2 1400 0x01C2 17FF 1K √ √
Timer2/3 0x01C2 1800 0x01C2 1BFF 1K √ √
WatchDog Timer 0x01C2 1C00 0x01C2 1FFF 1K √ √
PWM0 0x01C2 2000 0x01C2 23FF 1K √ √
PWM1 0x01C2 2400 0x01C2 27FF 1K √ √
PWM2 0x01C2 2800 0x01C2 2BFF 1K √ √
PWM3 0x01C2 2C00 0x01C2 2FFF 1K √ √
System Module 0x01C4 0000 0x01C4 07FF 2K √ √
PLL Controller 0 0x01C4 0800 0x01C4 0BFF 1K √ √
PLL Controller 1 0x01C4 0C00 0x01C4 0FFF 1K √ √
Power/Sleep Controller 0x01C4 1000 0x01C4 1FFF 4K √ √
Reserved 0x01C4 2000 0x01C4 7FFF 24K √ √
ARM Interrupt Controller 0x01C4 8000 0x01C4 83FF 1K √ √
Reserved 0x01C4 8400 0x01C6 3FFF 111K √ √
USB OTG 2.0 Regs / RAM 0x01C6 4000 0x01C6 5FFF 8K √ √
SPI0 0x01C6 6000 0x01C6 67FF 2K √ √
SPI1 0x01C6 6800 0x01C6 6FFF 2K √ √
GPIO 0x01C6 7000 0x01C6 77FF 2K √ √
SPI2 0x01C6 7800 0x01C6 FFFF 2K √ √
VPSS Subsystem 0x01C7 0000 0x01C7 FFFF 64K √ √
VPSS Clock Control 0x01C7 0000 0x01C7 007F 128 √ √
Hardware 3A 0x01C7 0080 0x01C7 00FF 128 √ √
Image Pipe (IPIPE) Interface 0x01C7 0100 0x01C7 01FF 256 √ √
On Screen Display 0x01C7 0200 0x01C7 02FF 256 √ √
Reserved 0x01C7 0300 0x01C7 03FF 256 √ √
Video Encoder 0x01C7 0400 0x01C7 05FF 512 √ √
CCD Controller 0x01C7 0600 0x01C7 07FF 256 √ √
VPSS Buffer Logic 0x01C7 0800 0x01C7 08FF 256 √ √
Reserved 0x01C7 0900 0x01C7 09FF 256 √ √
Image Pipe (IPIPE) 0x01C7 1000 0x01C7 3FFF 12K √ √
Reserved 0x01C7 4000 0x01CD FFFF 432K √ √
Multimedia / SD 1 0x01E0 0000 0x01E0 1FFF 8K √ √
ASP0 0x01E0 2000 0x01E0 3FFF 8K √ √
ASP1 0x01E0 4000 0x01E0 5FFF 8K √ √
UART2 0x01E0 6000 0x01E0 63FF 1K √ √
Reserved 0x01E0 6400 0x01E0 FFFF 39K √ √
ASYNC EMIF Control 0x01E1 0000 0x01E1 0FFF 4K √ √
Multimedia / SD 0 0x01E1 1000 0x01E1 FFFF 60K √ √
Reserved 0x01E2 0000 0x01FF FFFF 1792K √ √
ASYNC EMIF Data (CE0) 0x0200 0000 0x03FF FFFF 32M √ √
ASYNC EMIF Data (CE1) 0x0400 0000 0x05FF FFFF 32M √ √
Reserved 0x0600 0000 0x09FF FFFF 64M √ √
Reserved 0x0A00 0000 0x0BFF FFFF 32M √ √
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J
8
VSSA_PLL2
7
VDDA33_USB
6
5
4
31
H
G
VDDA13_USB
VSS
F
E
D
CIN2
C
B
A
VREF
CIN3CIN0
VDDA_PLL2
VSS
LCD_OE
FIELDVCLK
VSS
VSS
CVDD
VSYNCEXTCLKVFB
VDD_VOUT
VDD_VOUT
VDD_VOUT
HSYNCCOUT0COUT1TVOUT
TDOEMU0EMU1
VSS_USB
USB_VBUS
COUT2COUT3IOUT
TDITMS
VSS_USB
USB_IDCOUT4
VSS
TRST
VSS_USB_REF
USB_R1
VDDD13_USB
USB_DRV
VBUS
CVDD
YOUT7COUT5
MXO1
VSS
VSS_USB
VDDA33_USB_
PLL
VSS
YOUT5YOUT4YOUT0
MXI1
VSS
USB_DPUSB_DM
VSS
YOUT6YOUT2
CVDD
2
VSS
VSS
VSS
IBIAS
VSS
COUT6
COUT7
YOUT3
YOUT1
RSV01
VDD
VDD
NC
TMS320DM335
SPRS528C–JULY 2008–REVISED JUNE 2010
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Table 2-3. DM335 ARM Configuration Bus Access to Peripherals (continued)
Address Accessibility
Reserved 0x0C00 0000 0x0FFF FFFF 64M √ √
2.3 Pin Assignments
Extensive use of pin multiplexing is used to accommodate the largest number of peripheral functions in
the smallest possible package. Pin multiplexing is controlled using a combination of hardware
configuration at device reset and software programmable register settings.
2.3.1 Pin Map (Bottom View)
Figure 2-1 through Figure 2-4 show the pin assignments in four quadrants (A, B, C, and D). Note that
micro-vias are not required. Contact your TI representative for routing recommendations.
Figure 2-1. Pin Map [Quadrant A]
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W
9
DDR_CLK
8
DDR_CLK
7654
DDR_A05
32
DDR_A02
1
VDDR_A07DDR_A04DDR_A00
UVSS
TPCLK
R
P
N
M
L
K
DDR_A11DDR_A09DDR_A08
VSS
DDR_CAS
DDR_BA[2]
DDR_A12DDR_A10DDR_A01
VSS
DDR_BA[0]DDR_BA[1]
DDR_A13DDR_A06
DDR_A03
VSS
VSS
VSS
VSS
DDR_ZNDDR_CSDDR_RAS
VSS
VSS
MXO2
VDD_DDR
CVDD
CVDD
VSS
CAM_WEN_
FIELD
CAM_VDYIN3
VSS
MXI2
VDD_DDR
VDD_VIN
YIN0YIN2YIN4YIN1VSS_MX2
VSS
VSS
CVDD
CAM_HDCIN7
RSV05
VSS
VDD_DDR
VSS
VSS
VSS
YIN5
YIN6CIN5
RSV06
RSV04
VSS
VSS_DAC
VDDA18V_DAC
VDD
YIN7CIN4CIN1
VSS
RSV03
VSS
VDD
CVDD
CIN6
VSS
RSV07RSV02
VDD_VIN
VDD_VIN
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Figure 2-2. Pin Map [Quadrant B]
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CVDD
19
W
18
DDR_
DQGATE0
17
DDR_DQ15
16
DDR_DQ13
15
DDR_DQ11
14
DDR_DQ10
13
DDR_DQ07
12
DDR_DQ05
11
DDR_DQ01
10
DDR_WE
EM_A13 V
VSS
DDR_
DQGATE1
DDR_DQ14DDR_DQS[1]
DDR_DQ09DDR_DQ06
DDR_DQS[0]DDR_DQ00
DDR_CKE
EM_A12 U
UART0_RXD
VSS
DDR_DQ12DDR_DQM[1]
VSS
DDR_DQ08DDR_DQ04DDR_DQ02
DDR_VREF
EM_A08 T
UART0_TXD
CVDD
VSS
VDD_DDR
DDR_DQM[0]
DDR_DQ03
EM_A05 R
EM_A10
UART1_TXD
EM_A11
UART1_RXD
I2C_SCLI2C_SDA
VDD_DDR
VSSA_DLL
VDDA33_DDRDLL
EM_BA1 P
EM_A06
EM_A09EM_A07EM_A04
VDD_DDR
EM_BA0 N
EM_A03EM_A01EM_A02
VSS
VDD
VDD
EM_D14 M
EM_D15
VSS
EM_A00EM_D13
VSS
VDD
EM_D10 L
EM_D12EM_D11EM_D08EM_D04
CVDD
VSS
EM_D07 K
EM_D09EM_D06
VDD_DDR VDD_DDR VDD_DDR VDD_DDR
VDD
VDD
VDD
CVDD VDD
VSS CVDD CVDD
VSS
VSS VDD
TMS320DM335
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Figure 2-3. Pin Map [Quadrant C]
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19181716151413121110
EM_D05 J
EM_D02 H
EM_CE1 G
F
E
D
C
VDD
B
A
EM_D03EM_D01EM_CE0EM_WE
VSS
EM_D00
EM_ADV
ASP0_DX
VSSA_PLL1
CVDD
EM_WAIT
ASP0_FSX
GIO003
VDDA_PLL1
EM_OE
ASP0_CLKXASP0_CLKRASP0_FSR
GIO002
EM_CLK
ASP0_DRASP1_FSRASP1_FSX
GIO001
SPI1_
SDENA[0]
SPI1_SDORTCKTCK
ASP1_CLKXASP1_CLKRASP1_CLKS
GIO005
MMCSD0_
DATA1
CLKOUT1RESET
ASP1_DRASP1_DX
GIO007GIO000
MMCSD1_CLK
MMCSD0_CMDSPI1_SCLKSPI0_SCLK
CLKOUT3
VSS_MX1
GIO006
MMCSD1_
DATA0
MMCSD1_
DATA3
MMCSD1_
DATA2
GIO004
MMCSD1_
CMD
MMCSD1_
DATA1
MMCSD0_
CLK
MMCSD0_
DATA0
MMCSD0_
DATA3
MMCSD0_
DATA2
SPI1_SDI
SPI0_
SDENA[0]
SPI0_SDI
SPI0_SDO
CLKOUT2
VSS
CVDD CVDD CVDD VSS
CVDD VSS CVDD
CVDD
VDD
VDD
VDD
VDD
VDD
VSS
CVDD
VSS
VSS
CVDD
TMS320DM335
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SPRS528C–JULY 2008–REVISED JUNE 2010
Figure 2-4. Pin Map [Quadrant D]
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2.4 Pin Functions
The pin functions tables (Table 2-4 through Table 2-22) identify the external signal names, the associated
pin (ball) numbers along with the mechanical package designator, the pin type, whether the pin has any
internal pullup or pulldown resistors, and a functional pin description. For more detailed information on
device configuration, peripheral selection, multiplexed/shared pins, and debugging considerations, see
Section 3. For the list of all pin in chronological order see Section 2.20
2.4.1 Image Data Input - Video Processing Front End
The CCD Controller module in the Video Processing Front End has an external signal interface for image
data input. It supports YUV (YC) inputs as well as Bayer RGB and complementary input signals (I.e.,
image data input).
The definition of the CCD controller data input signals depend on the input mode selected.
• In 16-bit YCbCr mode, the Cb and Cr signals are multiplexed on the Cl signals and the order is
configurable (i.e., Cb first or Cr first).
• In 8-bit YCbCr mode, the Y, Cb, and Cr signals are multiplexed and not only is the order selectable,
but also the half of the bus used.
Table 2-4. CCD Controller Signals for Each Input Mode
PIN NAME CCD 16-BIT YCbCr 8-BIT YCbCr
Cl7 Cb7,Cr7 Y7,Cb7,Cr7
Cl6 Cb6,Cr6 Y6,Cb6,Cr6
Cl5 CCD13 Cb5,Cr5 Y5,Cb5,Cr5
Cl4 CCD12 Cb4,Cr4 Y4,Cb4,Cr4
Cl3 CCD11 Cb3,Cr3 Y3,Cb3,Cr3
Cl2 CCD10 Cb2,Cr2 Y2,Cb2,Cr2
Cl1 CCD9 Cb1,Cr1 Y1,Cb1,Cr1
Cl0 CCD8 Cb0,Cr0 Y0,Cb0,Cr0
Yl7 CCD7 Y7 Y7,Cb7,Cr7
Yl6 CCD6 Y6 Y6,Cb6,Cr6
Yl5 CCD5 Y5 Y5,Cb5,Cr5
Yl4 CCD4 Y4 Y4,Cb4,Cr4
Yl3 CCD3 Y3 Y3,Cb3,Cr3
Yl2 CCD2 Y2 Y2,Cb2,Cr2
Yl1 CCD1 Y1 Y1,Cb1,Cr1
Yl0 CCD0 Y0 Y0,Cb0,Cr0
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Table 2-5. CCD Controller/Video Input Terminal Functions
TERMINAL TYPE(1) OTHER(2) (3) DESCRIPTION
NAME NO.
Standard CCD/CMOS input: NOT USED
• YCC 16-bit: Time multiplexed between chroma: CB/SR[07]
CIN7/ PD • YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
GIO101/ N3 I/O/Z VDD_VIN multiplexed between luma and chroma of the upper channel. Y/CB/CR[07]
SPI2_SCLK SPI: SPI2 Clock
GIO: GIO[101]
Standard CCD/CMOS input: NOT USED
• YCC 16-bit: Time multiplexed between chroma: CB/SR[06]
CIN6/ PD • YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
GIO100/ K5 I/O/Z VDD_VIN multiplexed between luma and chroma of the upper channel. Y/CB/CR[06]
SPI2_SDO SPI: SPI2 Data Out
GIO: GIO[100]
Standard CCD/CMOS input: Raw[13]
CIN5/ • YCC 16-bit: Time multiplexed between chroma: CB/SR[05]
GIO099/ PD • YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
M3 I/O/Z
SPI2_SDEN VDD_VIN multiplexed between luma and chroma of the upper channel. Y/CB/CR[05]
A[0] SPI: SPI2 Chip Select
GIO: GIO[099]
Standard CCD/CMOS input: Raw[12]
CIN4/ • YCC 16-bit: Time multiplexed between chroma: CB/SR[04]
GIO098/ PD • YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
L4 I/O/Z
SPI2_SDEN VDD_VIN multiplexed between luma and chroma of the upper channel. Y/CB/CR[04]
A[1] SPI: SPI2 Data In
GIO: GIO[098]
Standard CCD/CMOS input(AFE): Raw[11]
• YCC 16-bit: Time multiplexed between chroma: CB/SR[03]
CIN3/ PD
J4 I/O/Z • YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
GIO097/ VDD_VIN multiplexed between luma and chroma of the upper channel. Y/CB/CR[03]
GIO: GIO[097]
Standard CCD/CMOS input: Raw[10]
• YCC 16-bit: Time multiplexed between chroma: CB/SR[02]
CIN2/ PD
J5 I/O/Z • YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
GIO096/ VDD_VIN multiplexed between luma and chroma of the upper channel. Y/CB/CR[02]
GIO: GIO[097]
Standard CCD/CMOS input: Raw[09]
• YCC 16-bit: Time multiplexed between chroma: CB/SR[01]
CIN1/ PD
L3 I/O/Z • YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
GIO095/ VDD_VIN multiplexed between luma and chroma of the upper channel. Y/CB/CR[01]
GIO: GIO[095]
Standard CCD/CMOS input: Raw[08]
• YCC 16-bit: Time multiplexed between chroma: CB/SR[00]
CIN0/ PD
J3 I/O/Z • YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
GIO094/ VDD_VIN multiplexed between luma and chroma of the upper channel. Y/CB/CR[00]
GIO: GIO[094]
Standard CCD/CMOS input: Raw[07]
• YCC 16-bit: Time multiplexed between chroma: Y[07]
YIN7/ PD
L5 I/O/Z • YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
GIO093 VDD_VIN multiplexed between luma and chroma of the upper channel. Y/CB/CR[07]
GIO: GIO[093]
Standard CCD/CMOS input: Raw[06]
• YCC 16-bit: Time multiplexed between chroma: Y[06]
YIN6/ PD
M4 I/O/Z • YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
GIO092 VDD_VIN multiplexed between luma and chroma of the upper channel. Y/CB/CR[06]
GIO: GIO[092]
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
(2) PD = internal pull-down, PU = internal pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩresistor should be used.)
(3) Specifies the operating I/O supply voltage for each signal. See Section 5.3 ,Power Supplies for more detail.
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Table 2-5. CCD Controller/Video Input Terminal Functions (continued)
TERMINAL TYPE(1) OTHER(2) (3) DESCRIPTION
NAME NO.
Standard CCD/CMOS input: Raw[05]
• YCC 16-bit: Time multiplexed between chroma: Y[05]
YIN5/ PD
M5 I/O/Z • YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
GIO091 VDD_VIN multiplexed between luma and chroma of the upper channel. Y/CB/CR[05]
GIO: GIO[091]
Standard CCD/CMOS input: Raw[04]
• YCC 16-bit: Time multiplexed between chroma: Y[04]
YIN4/ PD
P3 I/O/Z • YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
GIO090 VDD_VIN multiplexed between luma and chroma of the upper channel. Y/CB/CR[04]
GIO: GIO[090]
Standard CCD/CMOS input: Raw[03]
• YCC 16-bit: Time multiplexed between chroma: Y[03]
YIN3/ PD
R3 I/O/Z • YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
GIO089 VDD_VIN multiplexed between luma and chroma of the upper channel. Y/CB/CR[03]
GIO: GIO[089]
Standard CCD/CMOS input: Raw[02]
• YCC 16-bit: Time multiplexed between chroma: Y[02]
YIN2/ PD
P4 I/O/Z • YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
GIO088 VDD_VIN multiplexed between luma and chroma of the upper channel. Y/CB/CR[02]
GIO: GIO[088]
Standard CCD/CMOS input: Raw[01]
• YCC 16-bit: Time multiplexed between chroma: Y[01]
YIN1/ PD
P2 I/O/Z • YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
GIO087 VDD_VIN multiplexed between luma and chroma of the upper channel. Y/CB/CR[01]
GIO: GIO[087]
Standard CCD/CMOS input: Raw[00]
• YCC 16-bit: Time multiplexed between chroma: Y[00]
YIN0/ PD
P5 I/O/Z • YCC 8-bit (which allows for two simultaneous decoder inputs), it is time
GIO086 VDD_VIN multiplexed between luma and chroma of the upper channel. Y/CB/CR[00]
GIO: GIO[086]
Horizontal synchronization signal that can be either an input (slave mode) or an
CAM_HD/ PD
N5 I/O/Z output (master mode). Tells the CCDC when a new line starts.
GIO085 VDD_VIN GIO: GIO[085]
Vertical synchronization signal that can be either an input (slave mode) or an output
CAM_VD PD
R4 I/O/Z (master mode). Tells the CCDC when a new frame starts.
GIO084 VDD_VIN GIO: GIO[084]
Write enable input signal is used by external device (AFE/TG) to gate the DDR
output of the CCDC module. Alternately, the field identification input signal is used
CAM_WEN PD by external device (AFE/TG) to indicate which of two frames is input to the CCDC
_FIELD\ R5 I/O/Z VDD_VIN module for sensors with interlaced output. CCDC handles 1- or 2-field sensors in
GIO083 hardware.
GIO: GIO[083]
PCLK/ PD Pixel clock input (strobe for lines C17 through Y10)
T3 I/O/Z
GIO082 VDD_VIN GIO: GIO[0082]
2.5 Image Data Output - Video Processing Back End (VPBE)
The Video Encoder/Digital LCD interface module in the video processing back end has an external signal
interface for digital image data output as described in Table 2-7 and Table 2-8.
The digital image data output signals support multiple functions / interfaces, depending on the display
mode selected. The following table describes these modes. Parallel RGB mode with more than RGB565
signals requires enabling pin multiplexing to support (i.e., for RGB666 mode).
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Table 2-6. Signals for VPBE Display Modes
PIN NAME YCC16 YCC8/ PRGB SRGB
REC656
HSYNC HSYNC HSYNC HSYNC HSYNC
GIO073
VSYNC VSYNC VSYNC VSYNC VSYNC
GIO072
LCD_OE As needed As needed As needed As needed
GIO071
FIELD As needed As needed As needed As needed
GIO070
R2
PWM3C
EXTCLK As needed As needed As needed As needed
GIO069
B2
PWM3D
VCLK VCLK VCLK VCLK VCLK
GIO068
YOUT7 Y7 Y7,Cb7,Cr7 R7 Data7
YOUT6 Y6 Y6,Cb6,Cr6 R6 Data6
YOUT5 Y5 Y5,Cb5,Cr5 R5 Data5
YOUT4 Y4 Y4,Cb4,Cr4 R4 Data4
YOUT3 Y3 Y3,Cb3,Cr3 R3 Data3
YOUT2 Y2 Y2,Cb2,Cr2 G7 Data2
YOUT1 Y1 Y1,Cb1,Cr1 G6 Data1
YOUT0 Y0 Y0,Cb0,Cr0 G5 Data0
COUT7 C7 LCD_AC G4 LCD_AC
GIO081
PWM0
COUT6 C6 LCD_OE G3 LCD_OE
GIO080
PWM1
COUT5 C5 BRIGHT G2 BRIGHT
GIO079
PWM2A
RTO0
COUT4 C4 PWM B7 PWM
GIO078
PWM2B
RTO1
COUT3 C3 CSYNC B6 CSYNC
GIO077
PWM2C
RTO2
COUT2 C2 - B5 -
GIO076
PWM2D
RTO3
COUT1 C1 - B4 -
GIO075
PWM3A
COUT0 C0 - B3 -
GIO074
PWM3B
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Table 2-7. Digital Video Terminal Functions
TERMINAL TYPE(1) OTHER(2) (3) DESCRIPTION(4)
NAME NO.
YOUT7-R7 C3 I/O/Z VDD_VOUT Digital Video Out: VENC settings determine function
YOUT6-R6 A4 I/O/Z VDD_VOUT Digital Video Out: VENC settings determine function
YOUT5-R5 B4 I/O/Z VDD_VOUT Digital Video Out: VENC settings determine function
YOUT4-R4 B3 I/O/Z VDD_VOUT Digital Video Out: VENC settings determine function
YOUT3-R3 B2 I/O/Z VDD_VOUT Digital Video Out: VENC settings determine function
YOUT2-G7 A3 I/O/Z VDD_VOUT Digital Video Out: VENC settings determine function
YOUT1-G6 A2 I/O/Z VDD_VOUT Digital Video Out: VENC settings determine function
YOUT0-G5 B1 I/O/Z VDD_VOUT Digital Video Out: VENC settings determine function
COUT7-
G4/GIO081 C2 I/O/Z VDD_VOUT Digital Video Out: VENC settings determine function GIO: GIO[081] PWM0
/PWM0
COUT6-G3
/GIO080 D2 I/O/Z VDD_VOUT Digital Video Out: VENC settings determine function GIO: GIO[080] PWM1
/PWM1
COUT5-G2
/ GIO079 / C1 I/O/Z VDD_VOUT Digital Video Out: VENC settings determine function GIO: GIO[079] PWM2A RTO0
PWM2A /
RTO0
COUT4-B7 /
GIO078 / D3 I/O/Z VDD_VOUT Digital Video Out: VENC settings determine function GIO: GIO[078] PWM2B RTO1
PWM2B /
RTO1
COUT3-B6 /
GIO077 / E3 I/O/Z VDD_VOUT Digital Video Out: VENC settings determine function GIO: GIO[077] PWM2C RTO2
PWM2C /
RTO2
COUT2-B5 /
GIO076 / E4 I/O/Z VDD_VOUT Digital Video Out: VENC settings determine function GIO: GIO[076] PWM2D RTO3
PWM2D /
RTO3
COUT1-B4 / Digital Video Out: VENC settings determine function
GIO075 / F3 I/O/Z VDD_VOUT GIO: GIO[075]
PWM3A PWM3A
COUT0-B3 / Digital Video Out: VENC settings determine function
GIO074 / F4 I/O/Z VDD_VOUT GIO: GIO[074]
PWM3B PWM3B
HSYNC / PD Video Encoder: Horizontal Sync
F5 I/O/Z
GIO073 VDD_VOUT GIO: GIO[073]
VSYNC / PD Video Encoder: Vertical Sync
G5 I/O/Z
GIO072 VDD_VOUT GIO: GIO[072]
FIELD / Video Encoder: Field identifier for interlaced display formats
GIO070 / GIO: GIO[070]
H4 I/O/Z VDD_VOUT
R2 / Digital Video Out: R2
PWM3C PWM3C
Video Encoder: External clock input, used if clock rates > 27 MHz are needed, e.g.
EXTCLK / 74.25 MHz for HDTV digital output
GIO069 / PD
G3 I/O/Z GIO: GIO[069]
B2 / VDD_VOUT Digital Video Out: B2
PWM3D PWM3D
VCLK / Video Encoder: Video Output Clock
H3 I/O/Z VDD_VOUT
GIO068 GIO: GIO[068]
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
(2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 ,Power Supplies for more detail.
(3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩresistor should be used.)
(4) To reduce EMI and reflections, depending on the trace length, approximately 22 Ωto 50 Ωdamping resistors are recommend on the
following outputs placed near the DM335: YOUT(0-7),COUT(0-7), HSYNC,VSYNC,LCD_OE,FIELD,EXTCLK,VCLK. The trace lengths
should be minimized.
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Table 2-8. Analog Video Terminal Functions
TERMINAL TYPE(1) OTHER(2) DESCRIPTION
NAME NO.
Video DAC: Reference voltage output (0.45V, 0.1uF to GND). When the DAC is not
VREF J7 A I/O/Z used, the VREF signal should be connected to VSS.
Video DAC: Pre video buffer DAC output (1000 ohm to VFB). When the DAC is not
IOUT E1 A I/O/Z used, the IOUT signal should be connected to VSS.
Video DAC: External resistor (2550 Ohms to GND) connection for current bias
IBIAS F2 A I/O/Z configuration. When the DAC is not used, the IBIAS signal should be connected to
VSS.
Video DAC: Pre video buffer DAC output (1000 Ohms to IOUT, 1070 Ohms to
VFB G1 A I/O/Z TVOUT). When the DAC is not used, the VFB signal should be connected to VSS.
Video DAC: Analog Composite NTSC/PAL output (SeeFigure 5-31 andFigure 5-32 for
TVOUT F1 A I/O/Z V circuit connection). When the DAC is not used, the TVOUT signal should be left as a
No Connect or connected to VSS.
Video DAC: Analog 1.8V power. When the DAC is not used, the VDDA18_DAC signal
VDDA18_DAC L7 PWR should be connected to VSS.
Video DAC: Analog 1.8V ground. When the DAC is not used, the VSSA_DAC signal
VSSA_DAC L8 GND should be connected to VSS.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal. Specifies the operating I/O supply
voltage for each signal. See Section 5.3 ,Power Supplies for more detail.
(2) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩresistor should be used.)
2.6 Asynchronous External Memory Interface (AEMIF)
The Asynchronous External Memory Interface (AEMIF) signals support AEMIF, NAND, and OneNAND.
Table 2-9. Asynchronous EMIF/NAND/OneNAND Terminal Functions
TERMINAL TYPE(1) OTHER(2) (3) DESCRIPTION
NAME NO.
EM_A13/ Async EMIF: Address bus bit[13]
PD
GIO067/ V19 I/O/Z GIO: GIO[67]
VDD
BTSEL[1] System: BTSEL[1:0] sampled at power-on-reset to determine boot method.
EM_A12/ Async EMIF: Address bus bit[12]
PD
GIO066/ U19 I/O/Z GIO: GIO[66]
VDD
BTSEL[0] System: BTSEL[1:0] sampled at power-on-reset to determine boot method.
Async EMIF: Address bus bit[11]
EM_A11/ PU GIO: GIO[65]
GIO065/ R16 I/O/Z VDD AECFG[3:0] sampled at power-on-reset to AECFG configuration. AECFG[3] sets
AECFG[3] default for PinMux2_EM_D15_8: AEMIF default bus width (16 or 8 bits)
Async EMIF: Address bus bit[10]
EM_A10/ GIO: GIO[64]
PU
GIO064/ R18 I/O/Z AECFG[3:0] sampled at power-on-reset to AECFG configuration. AECFG[2:1]
VDD
AECFG[2] sets default for PinMux2_EM_BA0: AEMIF EM_BA0 definition (EM_BA0,
EM_A14, GIO[054], rsvd)
Async EMIF: Address bus bit[09]
EM_A09/ GIO: GIO[63]
PD
GIO063/ P17 I/O/Z AECFG[3:0] sampled at power-on-reset to AECFG configuration. AECFG[2:1]
VDD
AECFG[1] sets default for PinMux2_EM_BA0: AEMIF EM_BA0 definition (EM_BA0,
EM_A14, GIO[054], rsvd)
Async EMIF: Address bus bit[08]
GIO: GIO[62]
EM_A08/ PD AECFG[0] sets default for:
GIO062/ T19 I/O/Z VDD
AECFG[0] • PinMux2_EM_A0_BA1: AEMIF address width (OneNAND or NAND)
• PinMux2_EM_A13_3: AEMIF address width (OneNAND or NAND)
Async EMIF: Address bus bit[07]
EM_A07/ P16 I/O/Z VDD GIO: GIO[61]
GIO061 Used to drive boot status LED signal (active low) in ROM boot modes.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
(2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 ,Power Supplies for more detail.
(3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩresistor should be used.)
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Table 2-9. Asynchronous EMIF/NAND/OneNAND Terminal Functions (continued)
TERMINAL TYPE(1) OTHER(2) (3) DESCRIPTION
NAME NO.
EM_A06/ Async EMIF: Address bus bit[06]
P18 I/O/Z VDD
GIO060 GIO: GIO[60]
EM_A05/ Async EMIF: Address bus bit[05]
R19 I/O/Z VDD
GIO059 GIO: GIO[59]
EM_A04/ Async EMIF: Address bus bit[04]
P15 I/O/Z VDD
GIO058 GIO: GIO[58]
EM_A03/ Async EMIF: Address bus bit[03]
N18 I/O/Z VDD
GIO057 GIO: GIO[57]
Async EMIF: Address bus bit[02]
EM_A02/ N15 I/O/Z VDD NAND/SM/xD: CLE - Command latch enable output
Async EMIF: Address bus bit[01]
EM_A01/ N17 I/O/Z VDD NAND/SM/xD: ALE - Address latch enable output
EM_A00/ Async EMIF: Address bus bit[00]
M16 I/O/Z VDD
GIO056 GIO: GIO[56]
Async EMIF: Bank address 1 signal - 16-bit address:
EM_BA1/ • In 16-bit mode, lowest address bit.
P19 I/O/Z VDD
GIO055 • In 8-bit mode, second lowest address bit.
GIO: GIO[055]
Async EMIF: Bank address 0 signal - 8-bit address:
EM_BA0/ • In 8-bit mode, lowest address bit. or can be used as an extra address line
GIO054 N19 I/O/Z VDD (bit14) when using 16-bit memories.
EM_A14 GIO: GIO[054]
EM_D15/ Async EMIF: Data bus bit 15
M18 I/O/Z VDD
GIO053 GIO: GIO[053]
EM_D14/ Async EMIF: Data bus bit 14
M19 I/O/Z VDD
GIO052 GIO: GIO[052]
EM_D13/ Async EMIF: Data bus bit 13
M15 I/O/Z VDD
GIO051 GIO: GIO[051]
EM_D12/ Async EMIF: Data bus bit 12
L18 I/O/Z VDD
GIO050 GIO: GIO[050]
EM_D11/ Async EMIF: Data bus bit 11
L17 I/O/Z VDD
GIO049 GIO: GIO[049]
EM_D10/ Async EMIF: Data bus bit 10
L19 I/O/Z VDD
GIO048 GIO: GIO[048]
EM_D09/ Async EMIF: Data bus bit 09
K18 I/O/Z VDD
GIO047 GIO: GIO[047]
EM_D08/ Async EMIF: Data bus bit 08
L16 I/O/Z VDD
GIO046 GIO: GIO[046]
EM_D07/ Async EMIF: Data bus bit 07
K19 I/O/Z VDD
GIO045 GIO: GIO[045]
EM_D06/ Async EMIF: Data bus bit 06
K17 I/O/Z VDD
GIO044 GIO: GIO[044]
EM_D05/ Async EMIF: Data bus bit 05
J19 I/O/Z VDD
GIO043 GIO: GIO[043]
EM_D04/ Async EMIF: Data bus bit 04
L15 I/O/Z VDD
GIO042 GIO: GIO[042]
EM_D03/ Async EMIF: Data bus bit 03
J18 I/O/Z VDD
GIO041 GIO: GIO[041]
EM_D02/ Async EMIF: Data bus bit 02
H19 I/O/Z VDD
GIO040 GIO: GIO[040]
EM_D01/ Async EMIF: Data bus bit 01
J17 I/O/Z VDD
GIO039 GIO: GIO[039]
EM_D00/ Async EMIF: Data bus bit 00
H18 I/O/Z VDD
GIO038 GIO: GIO[038]
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Table 2-9. Asynchronous EMIF/NAND/OneNAND Terminal Functions (continued)
TERMINAL TYPE(1) OTHER(2) (3) DESCRIPTION
NAME NO.
Async EMIF: Lowest numbered chip select. Can be programmed to be used for
EM_CE0/ standard asynchronous memories (example: flash), OneNAND, or NAND
J16 I/O/Z VDD
GIO037 memory. Used for the default boot and ROM boot modes.
GIO: GIO[037]
Async EMIF: Second chip select. Can be programmed to be used for standard
EM_CE1/ G19 I/O/Z VDD asynchronous memories(example: flash), OneNAND, or NAND memory.
GIO036 GIO: GIO[036]
Async EMIF: Write Enable
EM_WE/ J15 I/O/Z VDD NAND/SM/xD: WE (Write Enable) output
GIO035 GIO: GIO[035]
Async EMIF: Output Enable
EM_OE/ F19 I/O/Z VDD NAND/SM/xD: RE (Read Enable) output
GIO034 GIO: GIO[034]
Async EMIF: Async WAIT
EM_WAIT/ G18 I/O/Z VDD NAND/SM/xD: RDY/ BSY input
GIO033 GIO: GIO[033]
EM_ADV/ OneNAND: Address valid detect for OneNAND interface
H16 I/O/Z VDD
GIO032 GIO: GIO[032]
EM_CLK/ OneNAND: Clock for OneNAND flash interface
E19 I/O/Z VDD
GIO031 GIO: GIO[031]
2.7 DDR Memory Interface
The DDR EMIF supports DDR2 and mobile DDR.
Table 2-10. DDR Terminal Functions
TERMINAL TYPE(1) OTHER(2) (3) DESCRIPTION
NAME NO.
DDR_CLK W9 I/O/Z VDD_DDR DDR Data Clock
DDR_CLK W8 I/O/Z VDD_DDR DDR Complementary Data Clock
DDR_RAS T6 I/O/Z VDD_DDR DDR Row Address Strobe
DDR_CAS V9 I/O/Z VDD_DDR DDR Column Address Strobe
DDR_WE W10 I/O/Z VDD_DDR DDR Write Enable
DDR_CS T8 I/O/Z VDD_DDR DDR Chip Select
DDR_CKE V10 I/O/Z VDD_DDR DDR Clock Enable
DDR_DQM[1] U15 I/O/Z VDD_DDR Data mask outputs:
• DDR_DQM[1] - For DDR_DQ[15:8]
DDR_DQM[0] T12 I/O/Z VDD_DDR • DDR_DQM[0] - For DDR_DQ[7:0]
DDR_DQS[1] V15 I/O/Z VDD_DDR Data strobe input/outputs for each byte of the 16-bit data bus used to
synchronize the data transfers. Output to DDR when writing and inputs when
reading.
DDR_DQS[0] V12 I/O/Z VDD_DDR • DDR_DQS[1] - For DDR_DQ[15:8]
• DDR_DQS[0] - For DDR_DQ[7:0]
DDR_BA[2] V8 I/O/Z VDD_DDR Bank select outputs. Two are required for 1Gb DDR2 memories.
DDR_BA[1] U7 I/O/Z VDD_DDR Bank select outputs. Two are required for 1Gb DDR2 memories.
DDR_BA[0] U8 I/O/Z VDD_DDR Bank select outputs. Two are required for 1Gb DDR2 memories.
DDR_A13 U6 I/O/Z VDD_DDR DDR Address Bus bit 13
DDR_A12 V7 I/O/Z VDD_DDR DDR Address Bus bit 12
DDR_A11 W7 I/O/Z VDD_DDR DDR Address Bus bit 11
DDR_A10 V6 I/O/Z VDD_DDR DDR Address Bus bit 10
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
(2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 ,Power Supplies for more detail.
(3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩresistor should be used.)
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Table 2-10. DDR Terminal Functions (continued)
TERMINAL TYPE(1) OTHER(2) (3) DESCRIPTION
NAME NO.
DDR_A09 W6 I/O/Z VDD_DDR DDR Address Bus bit 09
DDR_A08 W5 I/O/Z VDD_DDR DDR Address Bus bit 08
DDR_A07 V5 I/O/Z VDD_DDR DDR Address Bus bit 07
DDR_A06 U5 I/O/Z VDD_DDR DDR Address Bus bit 06
DDR_A05 W4 I/O/Z VDD_DDR DDR Address Bus bit 05
DDR_A04 V4 I/O/Z VDD_DDR DDR Address Bus bit 04
DDR_A03 W3 I/O/Z VDD_DDR DDR Address Bus bit 03
DDR_A02 W2 I/O/Z VDD_DDR DDR Address Bus bit 02
DDR_A01 V3 I/O/Z VDD_DDR DDR Address Bus bit 01
DDR_A00 V2 I/O/Z VDD_DDR DDR Address Bus bit 00
DDR_DQ15 W17 I/O/Z VDD_DDR DDR Data Bus bit 15
DDR_DQ14 V16 I/O/Z VDD_DDR DDR Data Bus bit 14
DDR_DQ13 W16 I/O/Z VDD_DDR DDR Data Bus bit 13
DDR_DQ12 U16 I/O/Z VDD_DDR DDR Data Bus bit 12
DDR_DQ11 W15 I/O/Z VDD_DDR DDR Data Bus bit 11
DDR_DQ10 W14 I/O/Z VDD_DDR DDR Data Bus bit 10
DDR_DQ09 V14 I/O/Z VDD_DDR DDR Data Bus bit 09
DDR_DQ08 U13 I/O/Z VDD_DDR DDR Data Bus bit 08
DDR_DQ07 W13 I/O/Z VDD_DDR DDR Data Bus bit 07
DDR_DQ06 V13 I/O/Z VDD_DDR DDR Data Bus bit 06
DDR_DQ05 W12 I/O/Z VDD_DDR DDR Data Bus bit 05
DDR_DQ04 U12 I/O/Z VDD_DDR DDR Data Bus bit 04
DDR_DQ03 T11 I/O/Z VDD_DDR DDR Data Bus bit 03
DDR_DQ02 U11 I/O/Z VDD_DDR DDR Data Bus bit 02
DDR_DQ01 W11 I/O/Z VDD_DDR DDR Data Bus bit 01
DDR_DQ00 V11 I/O/Z VDD_DDR DDR Data Bus bit 00
DDR_ DDR: Loopback signal for external DQS gating. Route to DDR and back to
W18 I/O/Z VDD_DDR
DQGATE0 DDR_DQGATE1 with same constraints as used for DDR clock and data.
DDR_ DDR: Loopback signal for external DQS gating. Route to DDR and back to
V17 I/O/Z VDD_DDR
DQGATE1 DDR_DQGATE0 with same constraints as used for DDR clock and data.
DDR: Voltage input for the SSTL_18 I/O buffers. Note even in the case of
DDR_VREF U10 I/O/Z VDD_DDR mDDR an external resistor divider connected to this pin is necessary.
VSSA_DLL R11 I/O/Z VDD_DDR DDR: Ground for the DDR DLL
VDDA33_DDRDL R10 I/O/Z VDD_DDR DDR: Power (3.3 V) for the DDR DLL
LDDR: Reference output for drive strength calibration of N and P channel
DDR_ZN T9 I/O/Z VDD_DDR outputs. Tie to ground via 50 ohm resistor @ 0.5% tolerance.
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2.8 GPIO
The General Purpose I/O signals provide generic I/O to external devices. Most of the GIO signals are
multiplexed with other functions.
Table 2-11. GPIO Terminal Functions
TERMINAL TYPE(1) OTHER(2) (3) DESCRIPTION
NAME NO.
GIO:GIO[000] is sampled at reset and stored in the GIO0_RESET bit of the
BOOTCFG register.
Active low during MMC/SD boot (can be used as MMC/SD power control).
GIO000 C16 I/O/Z VDD Can be used as external clock input for Timer 3.
Note: The GIO000 pin must be held high during NAND boot for the boot
process to fuction properly.
GIO001 E14 I/O/Z VDD GIO: GIO[001] Can be used as external clock input for Timer 3.
GIO002 F15 I/O/Z VDD GIO: GIO[002] Can be used as external clock input for Timer 3.
GIO003 G15 I/O/Z VDD GIO: GIO[003] Can be used as external clock input for Timer 3.
GIO004 B17 I/O/Z VDD GIO: GIO[004]
GIO005 D15 I/O/Z VDD GIO: GIO[005]
GIO006 B18 I/O/Z VDD GIO: GIO[006]
GIO007 / GIO: GIO[007]
SPI0_SDE C17 I/O/Z VDD SPI0: Chip Select 1
NA[1]
SPI1_SD SPI1: Data Out
O / E12 I/O/Z VDD GIO: GIO[008]
GIO008
SPI1_SDI
/ GIO009 / A13 I/O/Z VDD SPI1: Data In -OR- SPI1: Chip Select 1 GIO: GIO[009]
SPI1_SDE
NA[1]
SPI1_SCL SPI1: Clock GIO:
K / C13 I/O/Z VDD GIO[010]
GIO010
SPI1_SDE SPI1: Chip Select 0
NA[0] / E13 I/O/Z VDD GIO: GIO[011]
GIO011
UART1_T UART1: Transmit Data
XD / R17 I/O/Z VDD GIO: GIO[012]
GIO012
UART1_R UART1: Receive Data
XD / R15 I/O/Z VDD GIO: GIO[013]
GIO013
I2C_SCL / I2C: Serial Clock GIO:
R14 I/O/Z VDD
GIO014 GIO[014]
I2C_SDA / I2C: Serial Data
R13 I/O/Z VDD
GIO015 GIO: GIO[015]
CLKOUT3 CLKOUT: Output Clock 3
C11 I/O/Z VDD
/ GIO016 GIO: GIO[016]
CLKOUT2 CLKOUT: Output Clock 2
A11 I/O/Z VDD
/ GIO017 GIO: GIO[017]
CLKOUT1 CLKOUT: Output Clock 1
D12 I/O/Z VDD
/ GIO018 GIO: GIO[018]
MMCSD1
_DATA0 / MMCSD1: DATA0
GIO019 / A18 I/O/Z VDD GIO: GIO[019]
UART2_T UART2: Transmit Data
XD
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
(2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 ,Power Supplies for more detail.
(3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩresistor should be used.)
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Table 2-11. GPIO Terminal Functions (continued)
TERMINAL TYPE(1) OTHER(2) (3) DESCRIPTION
NAME NO.
MMCSD1
_DATA1 / MMCSD1: DATA1
GIO020 / B15 I/O/Z VDD GIO: GIO[020]
UART2_R UART2: Receive Data
XD
MMCSD1
_DATA2 / MMCSD1: DATA2
GIO021 / A16 I/O/Z VDD GIO: GIO[021]
UART2_C UART2: CTS
TS
MMCSD1
_DATA3 / MMCSD1: DATA3
GIO022 / B16 I/O/Z VDD GIO: GIO[022]
UART2_R UART2: RTS
TS
MMCSD1 MMCSD1: Command
_CMD / A17 I/O/Z VDD GIO: GIO[023]
GIO023
MMCSD1 MMCSD1: Clock
_CLK / C15 I/O/Z VDD GIO: GIO[024]
GIO024
ASP0_FS ASP0: Receive Frame Synch
R / F16 I/O/Z VDD GIO: GIO[025]
GIO025
ASP0_CL ASP0: Receive Clock
KR / F17 I/O/Z VDD GIO: GIO[026]
GIO026
ASP0_DR ASP0: Receive Data
E18 I/O/Z VDD
/ GIO027 GIO: GIO[027]
ASP0_FS ASP0: Transmit Frame Synch
X / G17 I/O/Z VDD GIO: GIO[028]
GIO028
ASP0_CL ASP0: Transmit Clock
KX / F18 I/O/Z VDD GIO: GIO[029]
GIO029
ASP0_DX ASP0: Transmit Data
H15 I/O/Z VDD
/ GIO030 GIO: GIO[030]
EM_CLK / E19 I/O/Z VDD OneNAND: Clock signal for OneNAND flash interface GIO: GIO[031]
GIO031
EM_ADV / PD OneNAND: Address Valid Detect for OneNAND interface
H16 I/O/Z
GIO032 VDD GIO: GIO[032]
EM_WAIT PU Async EMIF: Async WAIT NAND/SM/xD: RDY/_BSY input
G18 I/O/Z
/ GIO033 VDD GIO: GIO[033]
Async EMIF: Output Enable
EM_OE / F19 I/O/Z VDD NAND/SM/xD: RE (Read Enable) output
GIO034 GIO: GIO[034]
Async EMIF: Write Enable
EM_WE / J15 I/O/Z VDD NAND/SM/xD: WE (Write Enable) output
GIO035 GIO: GIO[035]
Async EMIF: Second Chip Select., Can be programmed to be used for standard
EM_CE1 / G19 I/O/Z VDD asynchronous memories (example: flash), OneNand or NAND memory.
GIO036 GIO: GIO[036]
Async EMIF: Lowest numbered Chip Select. Can be programmed to be used for
EM_CE0 / standard asynchronous memories (example: flash), OneNand or NAND memory.
J16 I/O/Z VDD
GIO037 Used for the default boot and ROM boot modes.
GIO: GIO[037]
EM_D00 / Async EMIF: Data Bus bit[00]
H18 I/O/Z VDD
GIO038 GIO: GIO[038]
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Table 2-11. GPIO Terminal Functions (continued)
TERMINAL TYPE(1) OTHER(2) (3) DESCRIPTION
NAME NO.
EM_D01 / Async EMIF: Data Bus bit[01]
J17 I/O/Z VDD
GIO039 GIO: GIO[039]
EM_D02 / Async EMIF: Data Bus bit[02]
H19 I/O/Z VDD
GIO040 GIO: GIO[040]
EM_D03 / Async EMIF: Data Bus bit[03]
J18 I/O/Z VDD
GIO041 GIO: GIO[041]
EM_D04 / Async EMIF: Data Bus bit[04]
L15 I/O/Z VDD
GIO042 GIO: GIO[042]
EM_D05 / Async EMIF: Data Bus bit[05]
J19 I/O/Z VDD
GIO043 GIO: GIO[043]
EM_D06 / Async EMIF: Data Bus bit[06]
K17 I/O/Z VDD
GIO044 GIO: GIO[044]
EM_D07 / Async EMIF: Data Bus bit[07]
K19 I/O/Z VDD
GIO045 GIO: GIO[045]
EM_D08 / Async EMIF: Data Bus bit[08]
L16 I/O/Z VDD
GIO046 GIO: GIO[046]
EM_D09 / Async EMIF: Data Bus bit[09]
K18 I/O/Z VDD
GIO047 GIO: GIO[047]
EM_D10 / Async EMIF: Data Bus bit[10]
L19 I/O/Z VDD
GIO048 GIO: GIO[048]
EM_D11 / Async EMIF: Data Bus bit[11]
L17 I/O/Z VDD
GIO049 GIO: GIO[049]
EM_D12 / Async EMIF: Data Bus bit[12]
L18 I/O/Z VDD
GIO050 GIO: GIO[050]
EM_D13 / Async EMIF: Data Bus bit[13]
M15 I/O/Z VDD
GIO051 GIO: GIO[051]
EM_D14 / Async EMIF: Data Bus bit[14]
M19 I/O/Z VDD
GIO052 GIO: GIO[052]
EM_D15 / Async EMIF: Data Bus bit[15]
M18 I/O/Z VDD
GIO053 GIO: GIO[053]
Async EMIF: Bank Address 0 signal = 8-bit address. In 8-bit mode, lowest
EM_BA0 / address bit. Or, can be used as an extra Address line (bit[14] when using 16-bit
GIO054 / N19 I/O/Z VDD memories.
EM_A14 GIO: GIO[054]
Async EMIF: Bank Address 1 signal = 16-bit address. In 16-bit mode, lowest
EM_BA1 / P19 I/O/Z VDD address bit. In 8-bit mode, second lowest address bit
GIO055 GIO: GIO[055]
Async EMIF: Address Bus bit[00] Note that the EM_A0 is always a 32-bit
EM_A00 / M16 I/O/Z VDD address
GIO056 GIO: GIO[056]
EM_A03 / Async EMIF: Address Bus bit[03]
N18 I/O/Z VDD
GIO057 GIO: GIO[057]
EM_A04 / Async EMIF: Address Bus bit[04]
P15 I/O/Z VDD
GIO058 GIO: GIO[058]
EM_A05 / Async EMIF: Address Bus bit[05]
R19 I/O/Z VDD
GIO059 GIO: GIO[059]
EM_A06 / Async EMIF: Address Bus bit[06]
P18 I/O/Z VDD
GIO060 GIO: GIO[060]
Async EMIF: Address Bus bit[07]
EM_A07 / P16 I/O/Z VDD GIO: GIO[061] - Used to drive Boot Status LED signal (active low) in ROM boot
GIO061 modes
Async EMIF: Address Bus bit[08]
EM_A08 / PU GIO: GIO[062] AECFG[0] sets default for - PinMux2.EM_A0_BA1: AEMIF
GIO062 / T19 I/O/Z VDD Address Width (OneNAND or NAND) - PinMux2.EM_A13_3: AEMIF Address
AECFG[0] Width (OneNAND or NAND)
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Table 2-11. GPIO Terminal Functions (continued)
TERMINAL TYPE(1) OTHER(2) (3) DESCRIPTION
NAME NO.
Async EMIF: Address Bus bit[09]
EM_A09 / PD GIO: GIO[063] System: AECFG[3:0] sampled at Power-on-Reset to set AEMIF
GIO063 / P17 I/O/Z VDD Configuration AECFG[2:1] sets default for PinMux2.EM_BA0: AEMIF EM_BA0
AECFG[1] Definition (EM_BA0, EM_A14, GIO[054], rsvd)
Async EMIF: Address Bus bit[10]
EM_A10 / PU GIO: GIO[064] System: AECFG[3:0] sampled at Power-on-Reset to set AEMIF
GIO064 / R18 I/O/Z VDD Configuration AECFG[2:1] sets default for PinMux2.EM_BA0: AEMIF EM_BA0
AECFG[2] Definition (EM_BA0, EM_A14, GIO[054], rsvd)
Async EMIF: Address Bus bit[11]
EM_A11 / PU GIO: GIO[065] System: AECFG[3:0] sampled at Power-on-Reset to set AEMIF
GIO065 / R16 I/O/Z VDD Configuration AECFG[3] sets default for PinMux2.EM_D15_8: AEMIF Default
AECFG[3] Bus Width (16 or 8 bits)
EM_A12 / Async EMIF: Address Bus bit[12]
PD
GIO066 / U19 I/O/Z GIO: GIO[066] System: BTSEL[1:0] sampled at Power-on-Reset to determine
VDD
BTSEL[0] Boot method
EM_A13 / Async EMIF: Address Bus bit[13]
PD
GIO067 / V19 I/O/Z GIO: GIO[067] System: BTSEL[1:0] sampled at Power-on-Reset to determine
VDD
BTSEL[1] Boot method.
VCLK / Video Encoder: Video Output Clock
H3 I/O/Z VDD_VOUT
GIO068 GIO: GIO[068]
EXTCLK / Video Encoder: External clock input, used if clock rates > 27 MHz are needed,
GIO069 / PD
G3 I/O/Z e.g. 74.25 MHz for HDTV digital output
B2 / VDD_VOUT GIO: GIO[069] Digital Video Out: B2 PWM3D
PWM3D
FIELD /
GIO070 / Video Encoder: Field identifier for interlaced display formats
H4 I/O/Z VDD_VOUT
R2 / GIO: GIO[070] Digital Video Out: R2 PWM3C
PWM3C
VSYNC / PD Video Encoder: Vertical Sync
G5 I/O/Z
GIO072 VDD_VOUT GIO: GIO[072]
HSYNC / PD Video Encoder: Horizontal Sync
F5 I/O/Z
GIO073 VDD_VOUT GIO: GIO[073]
COUT0-
B3 / Digital Video Out: VENC settings determine function GIO: GIO[074]
F4 I/O/Z VDD_VOUT
GIO074 / PWM3B
PWM3B
COUT1-
B4 / Digital Video Out: VENC settings determine function GIO: GIO[075]
F3 I/O/Z VDD_VOUT
GIO075 / PWM3A
PWM3A
COUT2-
B5 / Digital Video Out: VENC settings determine function GIO: GIO[076] PWM2D
GIO076 / E4 I/O/Z VDD_VOUT RTO3
PWM2D /
RTO3
COUT3-
B6 / Digital Video Out: VENC settings determine function GIO: GIO[077] PWM2C
GIO077 / E3 I/O/Z VDD_VOUT RTO2
PWM2C /
RTO2
COUT4-
B7 / Digital Video Out: VENC settings determine function GIO: GIO[078] PWM2B
GIO078 / D3 I/O/Z VDD_VOUT RTO1
PWM2B /
RTO1
COUT5-
G2 / Digital Video Out: VENC settings determine function GIO: GIO[079] PWM2A
GIO079 / C1 I/O/Z VDD_VOUT RTO0
PWM2A /
RTO0
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Table 2-11. GPIO Terminal Functions (continued)
TERMINAL TYPE(1) OTHER(2) (3) DESCRIPTION
NAME NO.
COUT6-
G3 / Digital Video Out: VENC settings determine function GIO: GIO[080]
D2 I/O/Z VDD_VOUT
GIO080 / PWM1
PWM1
COUT7-
G4 / Digital Video Out: VENC settings determine function GIO: GIO[081]
C2 I/O/Z VDD_VOUT
GIO081 / PWM0
PWM0
PCLK / PD
T3 I/O/Z Pixel clock input (strobe for lines CI7 through YI0) GIO: GIO[082]
GIO082 VDD_VIN Write enable input signal is used by external device (AFE/TG) to gate the DDR
CAM_WE output of the CCDC module. Alternately, the field identification input signal is
PD
N_FIELD / R5 I/O/Z used by external device (AFE/TG) to indicate the which of two frames is input to
VDD_VIN
GIO083 the CCDC module for sensors with interlaced output. CCDC handles 1- or 2-field
sensors in hardware. GIO: GIO[083]
Vertical synchronization signal that can be either an input (slave mode) or an
CAM_VD / PD
R4 I/O/Z output (master mode). Tells the CCDC when a new frame starts.
GIO084 VDD_VIN GIO: GIO[084]
Horizontal synchronization signal that can be either an input (slave mode) or an
CAM_HD / PD
N5 I/O/Z output (master mode). Tells the CCDC when a new line starts.
GIO085 VDD_VIN GIO: GIO[085]
Standard CCD/CMOS input: raw[00] YCC 16-bit: time multiplexed between luma:
YIN0 / PD Y[00] YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time
P5 I/O/Z
GIO086 VDD_VIN multiplexed between luma and chroma of the lower channel. Y/CB/CR[00]
GIO: GIO[086]
Standard CCD/CMOS input: raw[01] YCC 16-bit: time multiplexed between luma:
YIN1 / PD Y[01] YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time
P2 I/O/Z
GIO087 VDD_VIN multiplexed between luma and chroma of the lower channel. Y/CB/CR[01]
GIO: GIO[087]
Standard CCD/CMOS input: raw[02] YCC 16-bit: time multiplexed between luma:
YIN2 / PD Y[02] YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time
P4 I/O/Z
GIO088 VDD_VIN multiplexed between luma and chroma of the lower channel. Y/CB/CR[02]
GIO: GIO[088]
Standard CCD/CMOS input: raw[03] YCC 16-bit: time multiplexed between luma:
YIN3 / PD Y[03] YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time
R3 I/O/Z
GIO089 VDD_VIN multiplexed between luma and chroma of the lower channel. Y/CB/CR[03]
GIO: GIO[089]
Standard CCD/CMOS input: raw[04] YCC 16-bit: time multiplexed between luma:
YIN4 / PD Y[04] YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time
P3 I/O/Z
GIO090 VDD_VIN multiplexed between luma and chroma of the lower channel. Y/CB/CR[04]
GIO: GIO[090]
Standard CCD/CMOS input: raw[05] YCC 16-bit: time multiplexed between luma:
YIN5 / PD Y[05] YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time
M5 I/O/Z
GIO091 VDD_VIN multiplexed between luma and chroma of the lower channel. Y/CB/CR[05]
GIO: GIO[091]
Standard CCD/CMOS input: raw[06] YCC 16-bit: time multiplexed between luma:
YIN6 / PD Y[06] YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time
M4 I/O/Z
GIO092 VDD_VIN multiplexed between luma and chroma of the lower channel. Y/CB/CR[06]
GIO: GIO[092]
Standard CCD/CMOS input: raw[07] YCC 16-bit: time multiplexed between luma:
YIN7 / PD Y[07] YCC 08-bit (which allows for 2 simultaneous decoder inputs), it is time
L5 I/O/Z
GIO093 VDD_VIN multiplexed between luma and chroma of the lower channel. Y/CB/CR[07]
GIO: GIO[093]
Standard CCD/CMOS input: raw[08] YCC 16-bit: time multiplexed between
chroma: CB/CR[00] YCC 08-bit (which allows for 2 simultaneous decoder
CIN0 / PD
J3 I/O/Z inputs), it is time multiplexed between luma and chroma of the upper channel.
GIO094 VDD_VIN Y/CB/CR[00]
GIO: GIO[094]
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Table 2-11. GPIO Terminal Functions (continued)
TERMINAL TYPE(1) OTHER(2) (3) DESCRIPTION
NAME NO.
Standard CCD/CMOS input: raw[09] YCC 16-bit: time multiplexed between
chroma: CB/CR[01] YCC 08-bit (which allows for 2 simultaneous decoder
CIN1 / PD
L3 I/O/Z inputs), it is time multiplexed between luma and chroma of the upper channel.
GIO095 VDD_VIN Y/CB/CR[01]
GIO: GIO[095]
Standard CCD/CMOS input: raw[10] YCC 16-bit: time multiplexed between
chroma: CB/CR[02] YCC 08-bit (which allows for 2 simultaneous decoder
CIN2 / PD
J5 I/O/Z inputs), it is time multiplexed between luma and chroma of the upper channel.
GIO096 VDD_VIN Y/CB/CR[02]
GIO: GIO[096]
Standard CCD/CMOS input: raw[11] YCC 16-bit: time multiplexed between
chroma: CB/CR[03] YCC 08-bit (which allows for 2 simultaneous decoder
CIN3 / PD
J4 I/O/Z inputs), it is time multiplexed between luma and chroma of the upper channel.
GIO097 VDD_VIN Y/CB/CR[03]
GIO: GIO[097]
CIN4 / Standard CCD/CMOS input: raw[12] YCC 16-bit: time multiplexed between
GIO098 / chroma: CB/CR[04] YCC 08-bit (which allows for 2 simultaneous decoder
SPI2_SDI PD
L4 I/O/Z inputs), it is time multiplexed between luma and chroma of the upper channel.
/ VDD_VIN Y/CB/CR[04] SPI: SPI2 Data In -OR- SPI2 Chip select 1.
SPI2_SDE GIO: GIO[098]
NA[1] Standard CCD/CMOS input: raw[13] YCC 16-bit: time multiplexed between
CIN5 / chroma: CB/CR[05] YCC 08-bit (which allows for 2 simultaneous decoder
GIO099 / PD
M3 I/O/Z inputs), it is time multiplexed between luma and chroma of the upper channel.
SPI2_SDE VDD_VIN Y/CB/CR[05] SPI: SPI2 Chip Select 0.
NA[0] GIO: GIO[99]
Standard CCD/CMOS input: NOT USED YCC 16-bit: time multiplexed between
CIN6 / chroma: CB/CR[06] YCC 08-bit (which allows for 2 simultaneous decoder
GIO100 / PD
K5 I/O/Z inputs), it is time multiplexed between luma and chroma of the upper channel.
SPI2_SD VDD_VIN Y/CB/CR[06] SPI: SPI2 Data Out
OGIO: GIO[100]
Standard CCD/CMOS input: NOT USED YCC 16-bit: time multiplexed between
CIN7 / chroma: CB/CR[07] YCC 08-bit (which allows for 2 simultaneous decoder
GIO101 / PD
N3 I/O/Z inputs), it is time multiplexed between luma and chroma of the upper channel.
SPI2_SCL VDD_VIN Y/CB/CR[07] SPI: SPI2 Clock
KGIO: GIO[101]
SPI0_SDI SPI0: Data In
A12 I/O/Z VDD
/ GIO102 GIO: GIO[102]
SPI0_SDE SPI0: Chip Select 0
NA[0] / B12 I/O/Z VDD GIO: GIO[103]
GIO103
2.9 Multi-Media Card/Secure Digital (MMC/SD) Interfaces
The DM335 includes two Multi-Media Card/Secure Digital card interfaces that are compatible with the
MMC/SD and SDIO protocol.
Table 2-12. MMC/SD Terminal Functions
TERMINAL TYPE(1) OTHER(2) (3) DESCRIPTION
NAME NO.
MMCSD0_ A15 I/O/Z VDD MMCSD0: Clock
CLK
MMCSD0_ C14 I/O/Z VDD MMCSD0: Command
CMD
MMCSD0_ B14 I/O/Z VDD MMCSD0: DATA0
DATA0
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
(2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 ,Power Supplies for more detail.
(3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩresistor should be used.)
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Table 2-12. MMC/SD Terminal Functions (continued)
TERMINAL TYPE(1) OTHER(2) (3) DESCRIPTION
NAME NO.
MMCSD0_ D14 I/O/Z VDD MMCSD0: DATA1
DATA1
MMCSD0_ B13 I/O/Z VDD MMCSD0: DATA2
DATA2
MMCSD0_ A14 I/O/Z VDD MMCSD0: DATA3
DATA3
MMCSD1_ MMCSD1: Clock
CLK/ C15 I/O/Z VDD GIO: GIO[024]
GIO024
MMCSD1_ MMCSD1: Command
CMD/ A17 I/O/Z VDD GIO: GIO[023]
GIO023
MMCSD1_
DATA0/ MMCSD1: DATA0
GIO019/ A18 I/O/Z VDD GIO: GIO[019]
UART2_T UART2: Transmit data
XD
MMCSD1_
DATA1/ MMCSD1: DATA1
GIO020/ B15 I/O/Z VDD GIO: GIO[020]
UART2_R UART2: Receive data
XD
MMCSD1_
DATA2/ MMCSD1: DATA2
GIO021/ A16 I/O/Z VDD GIO: GIO[021]
UART2_C UART2: CTS
TS
MMCSD1_
DATA3/ MMCSD1: DATA3
GIO022/ B16 I/O/Z VDD GIO: GIO[022]
UART2_R UART2: RTS
TS
2.10 Universal Serial Bus (USB) Interface
The Universal Serial Bus (USB) interface supports the USB2.0 High-Speed protocol and includes dual-role
Host/Slave support. However, no charge pump is included.
Table 2-13. USB Terminal Functions
TERMINAL TYPE(1) OTHER(2) (3) DESCRIPTION
NAME NO.
USB D+ (differential signal pair).
USB_DP A7 A I/O/Z VDDA33_USB When USB is not used, this signal should be connected to VSS_USB.
USB D- (differential signal pair).
USB_DM A6 A I/O/Z VDDA33_USB When USB is not used, this signal should be connected to VSS_USB.
USB reference current output
Connect to VSS_USB_REF via 10K ohm , 1% resistor placed as close to the device
USB_R1 C7 A I/O/Z as possible.
When USB is not used, this signal should be connected to VSS_USB.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
(2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 , Power Supplies for more detail.
(3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩresistor should be used.)
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Table 2-13. USB Terminal Functions (continued)
TERMINAL TYPE(1) OTHER(2) (3) DESCRIPTION
NAME NO.
USB operating mode identification pin
For Device mode operation only, pull up this pin to VDD with a 1.5K ohm resistor.
For Host mode operation only, pull down this pin to ground (VSS) with a 1.5K ohm
USB_ID D5 A I/O/Z VDDA33_USB resistor.
If using an OTG or mini-USB connector, this pin will be set properly via the
cable/connector configuration.
When USB is not used, this signal should be connected to VSS_USB.
For host or device mode operation, tie the VBUS/USB power signal to the USB
connector.
USB_VBUS E5 A I/O/Z VDD When used in OTG mode operation, tie VBUS to the external charge pump and
to the VBUS signal on the USB connector.
When the USB is not used, tie VBUS to VSS_USB.
Digital output to control external 5 V supply
USB_DRVVBUS C5 O/Z VDD When USB is not used, this signal should be left as a No Connect.
USB Ground Reference
VSS_USB_REF C8 GND VDD Connect directly to ground and to USB_R1 via 10K ohm, 1% resistor placed as
close to the device as possible.
Analog 3.3 V power USBPHY
VDDA33_USB J8 PWR VDD When USB is not used, this signal should be connected to VSS_USB.
Common mode 3.3 V power for USB PHY (PLL)
VDDA33_USB_PLL B6 PWR VDD When USB is not used, this signal should be connected to VSS_USB.
Analog 1.3 V power for USB PHY
VDDA13_USB H7 PWR VDD When USB is not used, this signal should be connected to VSS_USB.
Digital 1.3 V power for USB PHY
VDDD13_USB C6 PWR VDD When USB is not used, this signal should be connected to VSS_USB.
2.11 Audio Interfaces
The DM335 includes two Audio Serial Ports (ASP ports), which are backward compatible with other TI
ASP serial ports and provide I2S audio interface. One interface is multiplexed with GIO signals.
Table 2-14. ASP Terminal Functions
TERMINAL TYPE(1) OTHER(2) (3) DESCRIPTION
NAME NO.
ASP0_CL ASP0: Receive Clock
KR/ F17 I/O/Z VDD GIO: GIO[026]
GIO026
ASP0_CL ASP0: Transmit Clock
KX / F18 I/O/Z VDD GIO: GIO[029]
GIO029
ASP0_DR ASP0: Receive DataF
/ E18 I/O/Z VDD GIO: GIO[027]
GIO027
ASP0_DX ASP0: Transmit Data
/ H15 I/O/Z VDD GIO: GIO[030]
GIO030
ASP0_FS ASP0: Receive Frame Synch
R / F16 I/O/Z VDD GIO: GIO[025]
GIO025
ASP0_FS
X / G17 I/O/Z VDD ASP0: Transmit Frame SynchGIO: GIO[028]
GIO028
ASP1_CL D18 I/O/Z VDD ASP1: Receive Clock
KR
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
(2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 ,Power Supplies for more detail.
(3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩresistor should be used.)
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Table 2-14. ASP Terminal Functions (continued)
TERMINAL TYPE(1) OTHER(2) (3) DESCRIPTION
NAME NO.
ASP1_CL D17 I/Z VDD ASP1: Master Clock
KS
ASP1_CL D19 I/O/Z VDD ASP1: Transmit Clock
KX
ASP1_DR C19 I/O/Z VDD ASP1: Receive Data
ASP1_DX C18 I/O/Z VDD ASP1: Transmit Data
ASP1_FS E17 I/O/Z VDD ASP1: Receive Frame Synch
R
ASP1_FS E16 I/O/Z VDD ASP1: Transmit Frame Sync
X
2.12 UART Interface
TheDM335 includes three UART ports. These ports are multiplexed with GIO and other signals.
Table 2-15. UART Terminal Functions
TERMINAL TYPE(1) OTHER(2) (3) DESCRIPTION
NAME NO.
UART0_RXD U18 I VDD UART0: Receive data. Used for UART boot mode
UART0_TXD T18 O VDD UART0: Transmit data. Used for UART boot mode
UART1_RXD/ UART1: Receive data.
R15 I/O/Z VDD
GIO013 GIO: GIO013
UART1_TXD/ UART1: Transmit data.
R17 I/O/Z VDD
GIO012 GIO: GIO012
MMCSD1_DA MMCSD1: DATA2
TA2/ A16 I/O/Z VDD GIO: GIO021
GIO021/ UART2: CTS
UART2_CTS
MMCSD1_DA MMCSD1: DATA3
TA3/ B16 I/O/Z VDD GIO: GIO022
GIO022/ UART2: RTS
UART2_RTS
MMCSD1_DA MMCSD1: DATA1
TA1/ B15 I/O/Z VDD GIO: GIO020
GIO020/ UART2: RXD
UART2_RXD
MMCSD1_DA MMCSD1: DATA0
TA0/ A18 I/O/Z VDD GIO: GIO019
GIO019/ UART2: TXD
UART2_TXD
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
(2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 ,Power Supplies for more detail.
(3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩresistor should be used.)
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2.13 I2C Interface
The DM335 includes an I2C two-wire serial interface for control of external peripherals. This interface is
multiplexed with GIO signals.
Table 2-16. I2C Terminal Functions
TERMINAL TYPE(1) OTHER(2) (3) DESCRIPTION
NAME NO.
I2C_SDA/ I2C: Serial data
R13 I/O/Z VDD
GIO015 GIO: GIO015
I2C_SCL/ I2C: Serial clock
R14 I/O/Z VDD
GIO014 GIO: GIO014
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
(2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 ,Power Supplies for more detail.
(3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩresistor should be used.)
2.14 Serial Interface
The DM335 includes three independent serial ports. These interfaces are multiplexed with GIO and other
signals.
Table 2-17. SPI Terminal Functions
TERMINAL OTHER(2)
TYPE(1) DESCRIPTION
(3)
NAME NO.
SPI0_SCLK C12 I/O/Z VDD SPI0: Clock
SPI0_SDENA[0]/ SPI0: Chip select 0
B12 I/O/Z VDD
GIO103 GIO: GIO[103]
GIO007 GIO: GIO[007]
C17 I/O/Z VDD
SPI0_SDENA[1] SPI0: Chip select 1
SPI0_SDI/ SPI0: Data in
A12 I/O/Z VDD
GIO102 GIO: GIO[102]
SPI0_SDO B11 I/O/Z VDD SPI0: Data out
SPI1_SCLK/ SPI1: Clock
C13 I/O/Z VDD
GIO010 GIO: GIO[010]
SPI1: Chip select 0
SPI1_SDENA[0]/ E13 I/O/Z VDD GIO: GIO[011] - Active low during MMC/SD boot (can be used as
GIO011 MMC/SD power control)
SPI1_SDI/ SPI1: Data in or
GIO009/ A13 I/O/Z VDD SPI1: Chip select 1
SPI1_SDENA[1] GIO: GIO[09]
SPI1_SDO/ SPI1: Data out
E12 I/O/Z VDD
GIO008 GIO: GIO[008]
Standard CCD/CMOS input: Not used
• YCC 16-bit: time multiplexed between chroma. CB/CR[07]
CIN7/ • YCC 8-bit (which allows for two simultaneous decoder inputs), it is
PD
GIO101/ N3 I/O/Z time multiplexed between luma and chroma of the upper channel.
VDD_VIN
SPI2_SCLK Y/CB/CR[07]
SPI: SPI2 clock
GIO: GIO[101]
Standard CCD/CMOS input: Raw[13]
• YCC 16-bit: time multiplexed between chroma. CB/CR[05]
CIN5/ • YCC 8-bit (which allows for two simultaneous decoder inputs), it is
PD
GIO099/ M3 I/O/Z time multiplexed between luma and chroma of the upper channel.
VDD_VIN
SPI2_SDENA[0] Y/CB/CR[07]
SPI: SPI2 chip select 0
GIO: GIO[099]
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
(2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 ,Power Supplies for more detail.
(3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩresistor should be used.)
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Table 2-17. SPI Terminal Functions (continued)
TERMINAL OTHER(2)
TYPE(1) DESCRIPTION
(3)
NAME NO.
Standard CCD/CMOS input: Raw[12]
• YCC 16-bit: time multiplexed between chroma. CB/CR[04]
CIN4/ • YCC 8-bit (which allows for two simultaneous decoder inputs), it is
GIO098/ PD
L4 I/O/Z time multiplexed between luma and chroma of the upper channel.
SPI2_SDI/ VDD_VIN Y/CB/CR[04]
SPI2_SDENA[1] SPI: SPI2 Data in -OR- SPI2 Chip select 1
GIO: GIO[0998]
Standard CCD/CMOS input: Not used
• YCC 16-bit: time multiplexed between chroma. CB/CR[06]
CIN6/ • YCC 8-bit (which allows for two simultaneous decoder inputs), it is
PD
GIO100/ K5 I/O/Z time multiplexed between luma and chroma of the upper channel.
VDD_VIN
SPI2_SDO/ Y/CB/CR[06]
SPI: SPI2 Data out
GIO: GIO[100]
2.15 Clock Interface
The DM335 provides interface with the system clocks.
Table 2-18. Clocks Terminal Functions
TERMINAL TYPE(1) OTHER(2) (3) DESCRIPTION
NAME NO.
CLKOUT1 CLKOUT: Output Clock 1
D12 I/O/Z VDD
/ GIO018 GIO: GIO[018]
CLKOUT2 CLKOUT: Output Clock 2
A11 I/O/Z VDD
/ GIO017 GIO: GIO[017]
CLKOUT3 CLKOUT: Output Clock 3
C11 I/O/Z VDD
/ GIO016 GIO: GIO[016]
MXI1 A9 I VDD Crystal input for system oscillator (24 MHz or 36 MHz)
Output for system oscillator (24 MHz or 36 MHz). When the MX02 is not used,
MXO1 B9 O VDD the MX02 signal can be left open.
Crystal input for video oscillator (27 MHz) Optional, use only if 27MHz derived
from MXI1 and PLL does not provide sufficient performance for Video DAC.
MXI2 R1 I VDD When the MXI2 is not used and powered down, the MXI2 signal should be left
as a No Connect
Output for video oscillator (27 MHz) Optional, use only if 27MHz derived from
MXI1 and PLL does not provide sufficient performance for Video DAC When the
MXO2 T1 O VDD MXO2 is not used and powered down, the MXO2 signal should be left as a No
Connect.
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
(2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 ,Power Supplies for more detail.
(3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩresistor should be used.)
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2.16 Real Time Output (RTO) Interface
The DM335 provides Real Time Output (RTO) interface.
Table 2-19. RTO Terminal Functions
TERMINAL TYPE(1) OTHER(2) (3) DESCRIPTION
NAME NO.
COUT5-
G2 / Digital Video Out: VENC settings determine function GIO: GIO[079]
GIO079 / C1 I/O/Z VDD_VOUT PWM2A
PWM2A / RTO0
RTO0
COUT4-
B7 / Digital Video Out: VENC settings determine function GIO: GIO[078]
GIO078 / D3 I/O/Z VDD_VOUT PWM2B
PWM2B / RTO1
RTO1
COUT3-
B6 / Digital Video Out: VENC settings determine function GIO: GIO[077]
GIO077 / E3 I/O/Z VDD_VOUT PWM2C
PWM2C / RTO2
RTO2
COUT2-
B5 / Digital Video Out: VENC settings determine function GIO: GIO[076]
GIO076 / E4 I/O/Z VDD_VOUT PWM2D
PWM2D / RTO3
RTO3
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
(2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 ,Power Supplies for more detail.
(3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩresistor should be used.)
2.17 Pulse Width Modulator (PWM) Interface
The DM335 provides Pulse Width Modulator (PWM) interface.
Table 2-20. PWM Terminal Functions
TERMINAL TYPE(1) OTHER(2) (3) DESCRIPTION
NAME NO.
COUT7-
G4 / Digital Video Out: VENC settings determine function GIO: GIO[081]
C2 I/O/Z VDD_VOUT
GIO081 / PWM0
PWM0
COUT6-
G3 / Digital Video Out: VENC settings determine function GIO: GIO[080]
D2 I/O/Z VDD_VOUT
GIO080 / PWM1
PWM1
COUT5-
G2 / Digital Video Out: VENC settings determine function GIO: GIO[079]
GIO079 / C1 I/O/Z VDD_VOUT PWM2A
PWM2A / RTO0
RTO0
COUT4-
B7 / Digital Video Out: VENC settings determine function GIO: GIO[078]
GIO078 / D3 I/O/Z VDD_VOUT PWM2B
PWM2B / RTO1
RTO1
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
(2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 ,Power Supplies for more detail.
(3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩresistor should be used.)
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Table 2-20. PWM Terminal Functions (continued)
TERMINAL TYPE(1) OTHER(2) (3) DESCRIPTION
NAME NO.
COUT3-
B6 / Digital Video Out: VENC settings determine function GIO: GIO[077]
GIO077 / E3 I/O/Z VDD_VOUT PWM2C
PWM2C / RTO2
RTO2
COUT2-
B5 / Digital Video Out: VENC settings determine function GIO: GIO[076]
GIO076 / E4 I/O/Z VDD_VOUT PWM2D
PWM2D / RTO3
RTO3
COUT1-
B4 / Digital Video Out: VENC settings determine function GIO: GIO[075]
F3 I/O/Z VDD_VOUT
GIO075 / PWM3A
PWM3A
COUT0-
B3 / Digital Video Out: VENC settings determine function GIO: GIO[074]
F4 I/O/Z VDD_VOUT
GIO074 / PWM3B
PWM3B
FIELD / Video Encoder: Field identifier for interlaced display formats GIO: GIO[070]
GIO070 / H4 I/O/Z VDD_VOUT Digital Video Out: R2
R2 / PWM3C
PWM3C
EXTCLK / Video Encoder: External clock input, used if clock rates > 27 MHz are needed,
GIO069 / PD
G3 I/O/Z e.g. 74.25 MHz for HDTV digital output GIO: GIO[069] Digital Video Out: B2
B2 / VDD_VOUT PWM3D
PWM3D
2.18 System Configuration Interface
The DM335 provides interfaces for system configuration and boot load.
Table 2-21. System/Boot Terminal Functions
TERMINAL TYPE(1) OTHER(2) (3) DESCRIPTION
NAME NO.
EM_A13/ Async EMIF: Address bus bit 13
PD
GIO067/ V19 I/O/Z GIO: GIO[067]
VDD
BTSEL[1] System: BTSEL[1:0] sampled at power-on-reset to determine boot method.
EM_A12/ Async EMIF: Address bus bit 12
PD
GIO066/ U19 I/O/Z GIO: GIO[066]
VDD
BTSEL[0] System: BTSEL[1:0] sampled at power-on-reset to determine boot method.
Async EMIF: Address bus bit 11
EM_A11/ GIO: GIO[065]
PU
GIO065/ R16 I/O/Z System: AECFG[3:0] sampled a power-on-reset to set AEMIF configuration.
VDD
AECFG[3] AECFG[3] sets default fo PinMux2.EM_D15_8. AEMIF default bus width (16 or 8
bits).
Async EMIF: Address bus bit 10
EM_A10/ GIO: GIO[064]
PU
GIO064/ R18 I/O/Z System: AECFG[3:0] sampled a power-on-reset to set AEMIF configuration.
VDD
AECFG[2] AECFG[2:1] sets default fo PinMux2.EM_BA0. AEMIF EM_BA0 definition:
(EM,_BA0, EM_A14, GIO[054], rsvd)
Async EMIF: Address bus bit 09
EM_A09/ GIO: GIO[063]
PD
GIO063/ P17 I/O/Z System: AECFG[3:0] sampled a power-on-reset to set AEMIF configuration.
VDD
AECFG[1] AECFG[2:1] sets default fo PinMux2.EM_BA0. AEMIF EM_BA0 definition:
(EM,_BA0, EM_A14, GIO[054], rsvd)
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
(2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 ,Power Supplies for more detail.
(3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩresistor should be used.)
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Table 2-21. System/Boot Terminal Functions (continued)
TERMINAL TYPE(1) OTHER(2) (3) DESCRIPTION
NAME NO.
Async EMIF: Address bus bit 08
GIO: GIO[062]
EM_A08/ PD System: AECFG[0] sets default for:
GIO062/ T19 I/O/Z VDD
AECFG[0] • PinMux2.EM_A0_BA1 - AEMIF address width (OneNAND, or NAND)
• PinMux2.EM_A13_3 - AEMIF address width (OneNAND, or NAND)
2.19 Emulation
The emulation interface allow software and hardware debugging.
Table 2-22. Emulation Terminal Functions
TERMINAL TYPE(1) OTHER(2) (3) DESCRIPTION
NAME NO.
TCK E10 I VDD JTAG test clock input
PU
TDI D9 I JTAG test data input
VDD
TDO E9 O VDD JTAG test data output
PU
TMS D8 I JTAG test mode select
VDD
PD
TRST C9 I JTAG test logic reset (active low)
VDD
RTCK E11 O VDD JTAG test clock output
JTAG emulation 0 I/O
PU
EMU0 E8 I/O/Z EMU[1:0] = 00 - Force Debug Scan chain (ARM and ARM ETB TAPs connected)
VDD EMU[1:0] = 11 - Normal Scan chain (ICEpick only)
JTAG emulation 1 I/O
PU
EMU1 E7 I/O/Z EMU[1:0] = 00 - Force Debug Scan chain (ARM and ARM ETB TAPs connected)
VDD EMU[1:0] = 11 - Normal Scan chain (ICEpick only)
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
(2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 ,Power Supplies for more detail.
(3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩresistor should be used.)
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2.20 Pin List
Table 2-23 provides a complete pin description list in pin number order.
Table 2-23. DM335 Pin Descriptions
Name BGA Type Group Power PU Reset Description(4) Mux Control
ID (1) Supply(2) PD(3) State
CIN7 / GIO101 / N3 I/O CCDC VDD_VIN PD in Standard CCD/CMOS input: NOT USED PINMUX0[1:0].CIN_
SPI2_SCLK / GIO / 7
YCC 16-bit: time multiplexed between
SPI2 chroma: CB/CR[07]
YCC 08-bit (which allows for 2 simultaneous
decoder inputs), it is time multiplexed
between
luma and chroma of the upper channel.
Y/CB/CR[07]
SPI: SPI2 Clock
GIO: GIO[101]
CIN6 / GIO100 / K5 I/O CCDC VDD_VIN PD in Standard CCD/CMOS input: NOT USED PINMUX0[3:2].CIN_
SPI2_SDO / GIO / 6
YCC 16-bit: time multiplexed between
SPI2 chroma: CB/CR[06]
YCC 08-bit (which allows for 2 simultaneous
decoder inputs), it is time multiplexed
between luma and chroma of the upper
channel. Y/CB/CR[06]
SPI: SPI2 Data Out
GIO: GIO[100]
CIN5 / GIO099 / M3 I/O CCDC VDD_VIN PD in Standard CCD/CMOS input: raw[13] PINMUX0[5:4].CIN_
SPI2_SDENA[0] / GIO / 5
SPI2 YCC 16-bit: time multiplexed between
chroma: CB/CR[05]
YCC 08-bit (which allows for 2 simultaneous
decoder inputs), it is time multiplexed
between luma and chroma of the upper
channel. Y/CB/CR[05]
SPI: SPI2 Chip Select 0
GIO: GIO[99]
CIN4 / GIO098 / L4 I/O CCDC VDD_VIN PD in Standard CCD/CMOS input: raw[12] PINMUX0[7:6].CIN_
SPI2_SDI / / GIO / 4
SPI2_SDENA[1] SPI2 /
SPI2 YCC 16-bit: time multiplexed between
chroma: CB/CR[04]
YCC 08-bit (which allows for 2 simultaneous
decoder inputs), it is time multiplexed
between luma and chroma of the upper
channel. Y/CB/CR[04]
SPI: SPI2 Data In -OR- SPI2 Chip select 1
GIO: GIO[098]
(1) I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal.
(2) Specifies the operating I/O supply voltage for each signal. See Section 5.3 ,Power Supplies for more detail.
(3) PD = pull-down, PU = pull-up. (To pull up a signal to the opposite supply rail, a 1 kΩresistor should be used.)
(4) To reduce EMI and reflections, depending on the trace length, approximately 22 Ωto 50 Ωdamping resistors are recommend on the
following outputs placed near the DM335: YOUT(0-7),COUT(0-7), HSYNC,VSYNC,LCD_OE,FIELD,EXTCLK,VCLK. The trace lengths
should be minimized.
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Table 2-23. DM335 Pin Descriptions (continued)
Name BGA Type Group Power PU Reset Description(4) Mux Control
ID (1) Supply(2) PD(3) State
CIN3 / GIO097 J4 I/O CCDC VDD_VIN PD in Standard CCD/CMOS input: raw[11] PINMUX0[8].CIN_32
/ GIO YCC 16-bit: time multiplexed between
chroma: CB/CR[03]
YCC 08-bit (which allows for 2 simultaneous
decoder inputs), it is time multiplexed
between luma and chroma of the upper
channel. Y/CB/CR[03]
GIO: GIO[097]
CIN2 / GIO096 J5 I/O CCDC VDD_VIN PD in Standard CCD/CMOS input: raw[10] PINMUX0[8].CIN_32
/ GIO YCC 16-bit: time multiplexed between
chroma: CB/CR[02]
YCC 08-bit (which allows for 2 simultaneous
decoder inputs), it is time multiplexed
between luma and chroma of the upper
channel. Y/CB/CR[02]
GIO: GIO[096]
CIN1 / GIO095 L3 I/O CCDC VDD_VIN PD in Standard CCD/CMOS input: raw[09] PINMUX0[9].CIN_10
/ GIO YCC 16-bit: time multiplexed between
chroma: CB/CR[01]
YCC 08-bit (which allows for 2 simultaneous
decoder inputs), it is time multiplexed
between luma and chroma of the upper
channel. Y/CB/CR[01]
GIO: GIO[095]
CIN0 / GIO094 J3 I/O CCDC VDD_VIN PD in Standard CCD/CMOS input: raw[08] PINMUX0[9].CIN_10
/ GIO YCC 16-bit: time multiplexed between
chroma: CB/CR[00]
YCC 08-bit (which allows for 2 simultaneous
decoder inputs), it is time multiplexed
between luma and chroma of the upper
channel. Y/CB/CR[00]
GIO: GIO[094]
YIN7 / GIO093 L5 I/O CCDC VDD_VIN PD in Standard CCD/CMOS input: raw[07] PINMUX0[10].YIN_7
/ GIO 0
YCC 16-bit: time multiplexed between luma:
Y[07]
YCC 08-bit (which allows for 2 simultaneous
decoder inputs), it is time multiplexed
between luma and chroma of the lower
channel. Y/CB/CR[07]
GIO: GIO[093]
YIN6 / GIO092 M4 I/O CCDC VDD_VIN PD in Standard CCD/CMOS input: raw[06] PINMUX0[10].YIN_7
/ GIO 0
YCC 16-bit: time multiplexed between luma:
Y[06]
YCC 08-bit (which allows for 2 simultaneous
decoder inputs), it is time multiplexed
between luma and chroma of the lower
channel. Y/CB/CR[06]
GIO: GIO[092]
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Table 2-23. DM335 Pin Descriptions (continued)
Name BGA Type Group Power PU Reset Description(4) Mux Control
ID (1) Supply(2) PD(3) State
YIN5 / GIO091 M5 I/O CCDC VDD_VIN PD in Standard CCD/CMOS input: raw[05] PINMUX0[10].YIN_7
/ GIO 0
YCC 16-bit: time multiplexed between luma:
Y[05]
YCC 08-bit (which allows for 2 simultaneous
decoder inputs), it is time multiplexed
between luma and chroma of the lower
channel. Y/CB/CR[05]
GIO: GIO[091]
YIN4 / GIO090 P3 I/O CCDC VDD_VIN PD in Standard CCD/CMOS input: raw[04] PINMUX0[10].YIN_7
/ GIO 0
YCC 16-bit: time multiplexed between luma:
Y[04]
YCC 08-bit (which allows for 2 simultaneous
decoder inputs), it is time multiplexed
between luma and chroma of the lower
channel. Y/CB/CR[04]
GIO: GIO[090]
YIN3 / GIO089 R3 I/O CCDC VDD_VIN PD in Standard CCD/CMOS input: raw[03] PINMUX0[10].YIN_7
/ GIO 0
YCC 16-bit: time multiplexed between luma:
Y[03]
YCC 08-bit (which allows for 2 simultaneous
decoder inputs), it is time multiplexed
between luma and chroma of the lower
channel. Y/CB/CR[03]
GIO: GIO[089]
YIN2 / GIO088 P4 I/O CCDC VDD_VIN PD in Standard CCD/CMOS input: raw[02] PINMUX0[10].YIN_7
/ GIO 0
YCC 16-bit: time multiplexed between luma:
Y[02]
YCC 08-bit (which allows for 2 simultaneous
decoder inputs), it is time multiplexed
between luma and chroma of the lower
channel. Y/CB/CR[02]
GIO: GIO[088]
YIN1 / GIO087 P2 I/O CCDC VDD_VIN PD in Standard CCD/CMOS input: raw[01] PINMUX0[10].YIN_7
/ GIO 0
YCC 16-bit: time multiplexed between luma:
Y[01]
YCC 08-bit (which allows for 2 simultaneous
decoder inputs), it is time multiplexed
between luma and chroma of the lower
channel. Y/CB/CR[01]
GIO: GIO[087]
YIN0 / GIO086 P5 I/O CCDC VDD_VIN PD in Standard CCD/CMOS input: raw[00] PINMUX0[10].YIN_7
/ GIO 0
YCC 16-bit: time multiplexed between luma:
Y[00]
YCC 08-bit (which allows for 2 simultaneous
decoder inputs), it is time multiplexed
between luma and chroma of the lower
channel. Y/CB/CR[00]
GIO: GIO[086]
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Table 2-23. DM335 Pin Descriptions (continued)
Name BGA Type Group Power PU Reset Description(4) Mux Control
ID (1) Supply(2) PD(3) State
CAM_HD / N5 I/O CCDC VDD_VIN PD in Horizontal synchronization signal that can be PINMUX0[11].CAM_
GIO085 / GIO either an input (slave mode) or an output HD
(master mode). Tells the CCDC when a new
line starts.
GIO: GIO[085]
CAM_VD / R4 I/O CCDC VDD_VIN PD in Vertical synchronization signal that can be PINMUX0[12].CAM_
GIO084 / GIO either an input (slave mode) or an output VD
(master mode). Tells the CCDC when a new
frame starts.
GIO: GIO[084]
CAM_WEN_FIE R5 I/O CCDC VDD_VIN PD in Write enable input signal is used by external PINMUX0[13].CAM_
LD / GIO083 / GIO device (AFE/TG) to gate the DDR output of WEN
the CCDC module.
Alternately, the field identification input plus
signal is used by external device (AFE/TG)
to indicate the which of two frames is input
to the CCDC module for sensors with
interlaced output. CCDC handles 1- or
2-field sensors in hardware.
GIO: GIO[083] CCDC.MODE[7].CC
DMD &
CCDC.MODE[5].SW
EN
PCLK / GIO082 T3 I/O CCDC VDD_VIN PD in Pixel clock input (strobe for lines CI7 through PINMUX0[14].PCLK
/ GIO YI0)
GIO: GIO[082]
YOUT7-R7 C3 I/O VENC VDD_VOUT in Digital Video Out: VENC settings determine
function(5)
YOUT6-R6 A4 I/O VENC VDD_VOUT in Digital Video Out: VENC settings determine
function(5)
YOUT5-R5 B4 I/O VENC VDD_VOUT in Digital Video Out: VENC settings determine
function(5)
YOUT4-R4 B3 I/O VENC VDD_VOUT in Digital Video Out: VENC settings determine
function(5)
YOUT3-R3 B2 I/O VENC VDD_VOUT in Digital Video Out: VENC settings determine
function(5)
YOUT2-G7 A3 I/O VENC VDD_VOUT in Digital Video Out: VENC settings determine
function(5)
YOUT1-G6 A2 I/O VENC VDD_VOUT in Digital Video Out: VENC settings determine
function(5)
YOUT0-G5 B1 I/O VENC VDD_VOUT in Digital Video Out: VENC settings determine
function(5)
COUT7-G4 / C2 I/O VENC VDD_VOUT in Digital Video Out: VENC settings determine PINMUX1[1:0].COU
GIO081 / PWM0 / GIO / function T_7
PWM0 GIO: GIO[081]
PWM0
COUT6-G3 / D2 I/O VENC VDD_VOUT in Digital Video Out: VENC settings determine PINMUX1[3:2].COU
GIO080 / PWM1 / GIO / function T_6
PWM1 GIO: GIO[080]
PWM1(5)
(5) To reduce EMI and reflections, depending on the trace length, approximately 22 Ωto 50 Ωdamping resistors are recommend on the
following outputs placed near the DM335: YOUT(0-7),COUT(0-7), HSYNC,VSYNC,LCD_OE,FIELD,EXTCLK,VCLK. The trace lengths
should be minimized.
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Table 2-23. DM335 Pin Descriptions (continued)
Name BGA Type Group Power PU Reset Description(4) Mux Control
ID (1) Supply(2) PD(3) State
COUT5-G2 / C1 I/O VENC VDD_VOUT in Digital Video Out: VENC settings determine PINMUX1[5:4].COU
GIO079 / / GIO / function T_5
PWM2A / RTO0 PWM2
/ RTO GIO: GIO[079]
PWM2A
RTO0(5)
COUT4-B7 / D3 I/O VENC VDD_VOUT in Digital Video Out: VENC settings determine PINMUX1[7:6].COU
GIO078 / / GIO / function T_4
PWM2B / RTO1 PWM2
/ RTO GIO: GIO[078]
PWM2B
RTO1(5)
COUT3-B6 / E3 I/O VENC VDD_VOUT in Digital Video Out: VENC settings determine PINMUX1[9:8].COU
GIO077 / / GIO / function T_3
PWM2C / RTO2 PWM2
/ RTO GIO: GIO[077]
PWM2C
RTO2(5)
COUT2-B5 / E4 I/O VENC VDD_VOUT in Digital Video Out: VENC settings determine PINMUX1[11:10].CO
GIO076 / / GIO / function UT_2
PWM2D / RTO3 PWM2
/ RTO GIO: GIO[076]
PWM2D
RTO3(6)
COUT1-B4 / F3 I/O VENC VDD_VOUT in Digital Video Out: VENC settings determine PINMUX1[13:12].CO
GIO075 / / GIO / function UT_1
PWM3A PWM3 GIO: GIO[075]
PWM3A(6)
COUT0-B3 / F4 I/O VENC VDD_VOUT in Digital Video Out: VENC settings determine PINMUX1[15:14].CO
GIO074 / / GIO / function UT_0
PWM3B PWM3 GIO: GIO[074]
PWM3B(6)
HSYNC / F5 I/O VENC VDD_VOUT PD in Video Encoder: Horizontal Sync PINMUX1[16].HVSY
GIO073 / GIO NC
GIO: GIO[073](6)
VSYNC / G5 I/O VENC VDD_VOUT PD in Video Encoder: Vertical Sync PINMUX1[16].HVSY
GIO072 / GIO NC
GIO: GIO[072](6)
LCD_OE / H5 I/O VENC VDD_VOUT out Video Encoder: LCD Output Enable or PINMUX1[17].DLCD
GIO071 / GIO BRIGHT signal
GIO: GIO[071](6)
(6) To reduce EMI and reflections, depending on the trace length, approximately 22 Ωto 50 Ωdamping resistors are recommend on the
following outputs placed near the DM335: YOUT(0-7),COUT(0-7), HSYNC,VSYNC,LCD_OE,FIELD,EXTCLK,VCLK. The trace lengths
should be minimized.
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Table 2-23. DM335 Pin Descriptions (continued)
Name BGA Type Group Power PU Reset Description(4) Mux Control
ID (1) Supply(2) PD(3) State
FIELD / GIO070 H4 I/O VENC VDD_VOUT in Video Encoder: Field identifier for interlaced PINMUX1[19:18].FI
/ R2 / PWM3C / GIO / display formats ELD
VENC
/
PWM3 GIO: GIO[070]
Digital Video Out: R2
PWM3C(6)
EXTCLK / G3 I/O VENC VDD_VOUT PD in Video Encoder: External clock input, used if PINMUX1[21:20].EX
GIO069 / B2 / / GIO / clock rates > 27 MHz are needed, e.g. 74.25 TCLK
PWM3D VENC MHz for HDTV digital output
/
PWM3 GIO: GIO[069]
Digital Video Out: B2
PWM3D(6)
VCLK / GIO068 H3 I/O VENC VDD_VOUT in Video Encoder: Video Output Clock PINMUX1[22].VCLK
/ GIO GIO: GIO[068](6)
VREF J7 A I/O Video Video DAC: Reference voltage output
DAC (0.45V, 0.1uF to GND)
IOUT E1 A I/O Video Video DAC: Pre video buffer DAC output
DAC (1000 ohm to VFB)
IBIAS F2 A I/O Video Video DAC: External resistor (2550 Ohms to
DAC GND) connection for current bias
configuration
VFB G1 A I/O Video Video DAC: Pre video buffer DAC output
DAC (1000 ohm to IOUT, 1070 ohm to TVOUT)
TVOUT F1 A I/O Video VDDA18_DAC Video DAC: Analog Composite NTSC/PAL
DAC output (SeeFigure 5-31 andFigure 5-32 for
circuit connection)
VDDA18V_DAC L7 PWR Video Video DAC: Analog 1.8V power
DAC
VSSA_DAC L8 GND Video Video DAC: Analog 1.8V ground
DAC
DDR_CLK W9 I/O DDR VDD_DDR out L DDR Data Clock
DDR_CLK W8 I/O DDR VDD_DDR out H DDR Complementary Data Clock
DDR_RAS T6 I/O DDR VDD_DDR out H DDR Row Address Strobe
DDR_CAS V9 I/O DDR VDD_DDR out H DDR Column Address Strobe
DDR_WE W10 I/O DDR VDD_DDR out H DDR Write Enable (active low)
DDR_CS T8 I/O DDR VDD_DDR out H DDR Chip Select (active low)
DDR_CKE V10 I/O DDR VDD_DDR out L DDR Clock Enable
DDR_DQM[1] U15 I/O DDR VDD_DDR in Data mask outputs: DDR_DQM1: For
DDR_DQ[15:8]
DDR_DQM[0] T12 I/O DDR VDD_DDR in Data mask outputs: DDR_DQM0: For
DDR_DQ[7:0]
DDR_DQS[1] V15 I/O DDR VDD_DDR in Data strobe input/outputs for each byte of
the 16 bit data bus used to synchronize the
data transfers. Output to DDR when writing
and inputs when reading.
DDR_DQS1: For DDR_DQ[15:8]
42 Device Overview Copyright © 2008–2010, Texas Instruments Incorporated
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SPRS528C–JULY 2008–REVISED JUNE 2010
Table 2-23. DM335 Pin Descriptions (continued)
Name BGA Type Group Power PU Reset Description(4) Mux Control
ID (1) Supply(2) PD(3) State
DDR_DQS[0] V12 I/O DDR VDD_DDR in Data strobe input/outputs for each byte of
the 16 bit data bus used to synchronize the
data transfers. Output to DDR when writing
and inputs when reading.
DDR_DQS0: For DDR_DQ[7:0]
DDR_BA[2] V8 I/O DDR VDD_DDR out L Bank select outputs. Two are required for
1Gb DDR2 memories.
DDR_BA[1] U7 I/O DDR VDD_DDR out L Bank select outputs. Two are required for
1Gb DDR2 memories.
DDR_BA[0] U8 I/O DDR VDD_DDR out L Bank select outputs. Two are required for
1Gb DDR2 memories.
DDR_A13 U6 I/O DDR VDD_DDR out L DDR Address Bus bit 13
DDR_A12 V7 I/O DDR VDD_DDR out L DDR Address Bus bit 12
DDR_A11 W7 I/O DDR VDD_DDR out L DDR Address Bus bit 11
DDR_A10 V6 I/O DDR VDD_DDR out L DDR Address Bus bit 10
DDR_A09 W6 I/O DDR VDD_DDR out L DDR Address Bus bit 09
DDR_A08 W5 I/O DDR VDD_DDR out L DDR Address Bus bit 08
DDR_A07 V5 I/O DDR VDD_DDR out L DDR Address Bus bit 07
DDR_A06 U5 I/O DDR VDD_DDR out L DDR Address Bus bit 06
DDR_A05 W4 I/O DDR VDD_DDR out L DDR Address Bus bit 05
DDR_A04 V4 I/O DDR VDD_DDR out L DDR Address Bus bit 04
DDR_A03 W3 I/O DDR VDD_DDR out L DDR Address Bus bit 03
DDR_A02 W2 I/O DDR VDD_DDR out L DDR Address Bus bit 02
DDR_A01 V3 I/O DDR VDD_DDR out L DDR Address Bus bit 01
DDR_A00 V2 I/O DDR VDD_DDR out L DDR Address Bus bit 00
DDR_DQ15 W17 I/O DDR VDD_DDR in DDR Data Bus bit 15
DDR_DQ14 V16 I/O DDR VDD_DDR in DDR Data Bus bit 14
DDR_DQ13 W16 I/O DDR VDD_DDR in DDR Data Bus bit 13
DDR_DQ12 U16 I/O DDR VDD_DDR in DDR Data Bus bit 12
DDR_DQ11 W15 I/O DDR VDD_DDR in DDR Data Bus bit 11
DDR_DQ10 W14 I/O DDR VDD_DDR in DDR Data Bus bit 10
DDR_DQ09 V14 I/O DDR VDD_DDR in DDR Data Bus bit 09
DDR_DQ08 U13 I/O DDR VDD_DDR in DDR Data Bus bit 08
DDR_DQ07 W13 I/O DDR VDD_DDR in DDR Data Bus bit 07
DDR_DQ06 V13 I/O DDR VDD_DDR in DDR Data Bus bit 06
DDR_DQ05 W12 I/O DDR VDD_DDR in DDR Data Bus bit 05
DDR_DQ04 U12 I/O DDR VDD_DDR in DDR Data Bus bit 04
DDR_DQ03 T11 I/O DDR VDD_DDR in DDR Data Bus bit 03
DDR_DQ02 U11 I/O DDR VDD_DDR in DDR Data Bus bit 02
DDR_DQ01 W11 I/O DDR VDD_DDR in DDR Data Bus bit 01
DDR_DQ00 V11 I/O DDR VDD_DDR in DDR Data Bus bit 00
DDR_ W18 I/O DDR VDD_DDR out DDR: Loopback signal for external DQS
DQGATE0 gating. Route to DDR and back to
DDR_DQGATE1 with same constraints as
used for DDR clock and data.
DDR_ V17 I/O DDR VDD_DDR in DDR: Loopback signal for external DQS
DQGATE1 gating. Route to DDR and back to
DDR_DQGATE0 with same constraints as
used for DDR clock and data.
Copyright © 2008–2010, Texas Instruments Incorporated Device Overview 43
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Table 2-23. DM335 Pin Descriptions (continued)
Name BGA Type Group Power PU Reset Description(4) Mux Control
ID (1) Supply(2) PD(3) State
DDR_VREF U10 PWR DDRI VDD_DDR DDR: Voltage input for the SSTL_18 IO
O buffers
VSSA_DLL R11 GND DDRD VDD_DDR DDR: Ground for the DDR DLL
LL
VDDA33_DDRDLL R10 PWR DDRD VDD_DDR DDR: Power (3.3 Volts) for the DDR DLL
LL
DDR_ZN T9 I/O DDRI VDD_DDR DDR: Reference output for drive strength
O calibration of N and P channel outputs. Tie
to ground via 50 ohm resistor @ 0.5%
tolerance.
EM_A13 / V19 I/O AEMI VDD PD in L Async EMIF: Address Bus bit[13] PINMUX2[0].EM_A1
GIO067 / F / 3_3,
BTSEL[1] GIO /
syste
mGIO: GIO[067] default set by
AECFG[0]
System: BTSEL[1:0] sampled at
Power-on-Reset to determine Boot method
(00:NAND, 01:Flash, 10:MMC/SD, 11:UART
)
EM_A12 / U19 I/O AEMI VDD PD in L Async EMIF: Address Bus bit[12] PINMUX2[0].EM_A1
GIO066 / F / 3_3,
BTSEL[0] GIO /
syste
mGIO: GIO[066] default set by
AECFG[0]
System: BTSEL[1:0] sampled at
Power-on-Reset to determine Boot method
(00:NAND, 01:Flash, 10:MMC/SD, 11:UART)
EM_A11 / R16 I/O AEMI VDD PU in H Async EMIF: Address Bus bit[11] PINMUX2[0].EM_A1
GIO065 / F / 3_3,
AECFG[3] GIO /
syste
mGIO: GIO[065] default set by
AECFG[0]
System: AECFG[3:0] sampled at
Power-on-Reset to set AEMIF Configuration
AECFG[3] sets default for
PinMux2.EM_D15_8: AEMIF Default Bus
Width (0:16 or 1:8 bits)
EM_A10 / R18 I/O AEMI VDD PU in H Async EMIF: Address Bus bit[10] PINMUX2[0].EM_A1
GIO064 / F / 3_3,
AECFG[2] GIO /
syste
mGIO: GIO[064] default set by
AECFG[0]
System: AECFG[3:0] sampled at
Power-on-Reset to set AEMIF Configuration
AECFG[2:1] sets default for
PinMux2.EM_BA0: AEMIF EM_BA0
Definition (00: EM_BA0, 01: EM_A14,
10:GIO[054], 11:rsvd)
44 Device Overview Copyright © 2008–2010, Texas Instruments Incorporated
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SPRS528C–JULY 2008–REVISED JUNE 2010
Table 2-23. DM335 Pin Descriptions (continued)
Name BGA Type Group Power PU Reset Description(4) Mux Control
ID (1) Supply(2) PD(3) State
EM_A09 / P17 I/O AEMI VDD PD in L Async EMIF: Address Bus bit[09] PINMUX2[0].EM_A1
GIO063 / F / 3_3,
AECFG[1] GIO /
syste
mGIO: GIO[063] default set by
AECFG[0]
System: AECFG[3:0] sampled at
Power-on-Reset to set AEMIF Configuration
AECFG[2:1] sets default for
PinMux2.EM_BA0: AEMIF EM_BA0
Definition (00: EM_BA0, 01: EM_A14,
10:GIO[054], 11:rsvd)
EM_A08 / T19 I/O AEMI VDD PU in H Async EMIF: Address Bus bit[08] PINMUX2[0].EM_A1
GIO062 / F / 3_3,
AECFG[0] GIO /
syste
mGIO: GIO[062] default set by
AECFG[0]
AECFG[0] sets default for
- PinMux2.EM_A0_BA1: AEMIF Address
Width (OneNAND or NAND)
- PinMux2.EM_A13_3: AEMIF Address
Width (OneNAND or NAND)
(0:AEMIF address bits, 1:GIO[67:57])
EM_A07 / P16 I/O AEMI VDD out L Async EMIF: Address Bus bit[07] PINMUX2[0].EM_A1
GIO061 F / 3_3,
GIO GIO: GIO[061] - Used to drive Boot Status default set by
LED signal (active low) in ROM boot modes AECFG[0]
EM_A06 / P18 I/O AEMI VDD out L Async EMIF: Address Bus bit[06] PINMUX2[0].EM_A1
GIO060 F / 3_3,
GIO GIO: GIO[060] default set by
AECFG[0]
EM_A05 / R19 I/O AEMI VDD out L Async EMIF: Address Bus bit[05] PINMUX2[0].EM_A1
GIO059 F / 3_3,
GIO GIO: GIO[059] default set by
AECFG[0]
EM_A04 / P15 I/O AEMI VDD out L Async EMIF: Address Bus bit[04] PINMUX2[0].EM_A1
GIO058 F / 3_3,
GIO GIO: GIO[058] default set by
AECFG[0]
EM_A03 / N18 I/O AEMI VDD out L Async EMIF: Address Bus bit[03] PINMUX2[0].EM_A1
GIO057 F / 3_3,
GIO GIO: GIO[057] default set by
AECFG[0]
EM_A02 N15 I/O AEMI VDD out L Async EMIF: Address Bus bit[02]
FNAND/SM/xD: CLE - Command Latch
Enable output
Copyright © 2008–2010, Texas Instruments Incorporated Device Overview 45
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Table 2-23. DM335 Pin Descriptions (continued)
Name BGA Type Group Power PU Reset Description(4) Mux Control
ID (1) Supply(2) PD(3) State
EM_A01 N17 I/O AEMI VDD out L Async EMIF: Address Bus bit[01]
FNAND/SM/xD: ALE - Address Latch Enable
output
EM_A00 / M16 I/O AEMI VDD out L Async EMIF: Address Bus bit[00] Note that PINMUX2[1].EM_A0
GIO056 F / the EM_A0 is always a 32-bit address _BA1,
GIO GIO: GIO[056] default set by
AECFG[0]
EM_BA1 / P19 I/O AEMI VDD out H Async EMIF: Bank Address 1 signal = 16-bit PINMUX2[1].EM_A0
GIO055 F / address. _BA1,
GIO In 16-bit mode, lowest address bit. default set by
AECFG[0]
In 8-bit mode, second lowest address bit
GIO: GIO[055]
EM_BA0 / N19 I/O AEMI VDD out H Async EMIF: Bank Address 0 signal = 8-bit PINMUX2[3:2].EM_
GIO054 / F / address. BA0,
EM_A14 GIO /
EMIF2
.30 In 8-bit mode, lowest address bit. default set by
AECFG[2:1]
Or, can be used as an extra Address line
(bit[14] when using 16-bit memories.
GIO: GIO[054]
EM_D15 / M18 I/O AEMI VDD in Async EMIF: Data Bus bit[15] PINMUX2[4].EM_D1
GIO053 F / 5_8,
GIO GIO: GIO[053] default set by
AECFG[3]
EM_D14 / M19 I/O AEMI VDD in Async EMIF: Data Bus bit[14] PINMUX2[4].EM_D1
GIO052 F / 5_8,
GIO GIO: GIO[052] default set by
AECFG[3]
EM_D13 / M15 I/O AEMI VDD in Async EMIF: Data Bus bit[13] PINMUX2[4].EM_D1
GIO051 F / 5_8,
GIO GIO: GIO[051] default set by
AECFG[3]
EM_D12 / L18 I/O AEMI VDD in Async EMIF: Data Bus bit[12] PINMUX2[4].EM_D1
GIO050 F / 5_8,
GIO GIO: GIO[050] default set by
AECFG[3]
EM_D11 / L17 I/O AEMI VDD in Async EMIF: Data Bus bit[11] PINMUX2[4].EM_D1
GIO049 F / 5_8,
GIO GIO: GIO[049] default set by
AECFG[3]
EM_D10 / L19 I/O AEMI VDD in Async EMIF: Data Bus bit[10] PINMUX2[4].EM_D1
GIO048 F / 5_8,
GIO GIO: GIO[048] default set by
AECFG[3]
46 Device Overview Copyright © 2008–2010, Texas Instruments Incorporated
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SPRS528C–JULY 2008–REVISED JUNE 2010
Table 2-23. DM335 Pin Descriptions (continued)
Name BGA Type Group Power PU Reset Description(4) Mux Control
ID (1) Supply(2) PD(3) State
EM_D09 / K18 I/O AEMI VDD in Async EMIF: Data Bus bit[09] PINMUX2[4].EM_D1
GIO047 F / 5_8,
GIO GIO: GIO[047] default set by
AECFG[3]
EM_D08 / L16 I/O AEMI VDD in Async EMIF: Data Bus bit[08] PINMUX2[4].EM_D1
GIO046 F / 5_8,
GIO GIO: GIO[046] default set by
AECFG[3]
EM_D07 / K19 I/O AEMI VDD in Async EMIF: Data Bus bit[07] PINMUX2[5].EM_D7
GIO045 F / _0
GIO GIO: GIO[045]
EM_D06 / K17 I/O AEMI VDD in Async EMIF: Data Bus bit[06] PINMUX2[5].EM_D7
GIO044 F / _0
GIO GIO: GIO[044]
EM_D05 / J19 I/O AEMI VDD in Async EMIF: Data Bus bit[05] PINMUX2[5].EM_D7
GIO043 F / _0
GIO GIO: GIO[043]
EM_D04 / L15 I/O AEMI VDD in Async EMIF: Data Bus bit[04] PINMUX2[5].EM_D7
GIO042 F / _0
GIO GIO: GIO[042]
EM_D03 / J18 I/O AEMI VDD in Async EMIF: Data Bus bit[03] PINMUX2[5].EM_D7
GIO041 F / _0
GIO GIO: GIO[041]
EM_D02 / H19 I/O AEMI VDD in Async EMIF: Data Bus bit[02] PINMUX2[5].EM_D7
GIO040 F / _0
GIO GIO: GIO[040]
EM_D01 / J17 I/O AEMI VDD in Async EMIF: Data Bus bit[01] PINMUX2[5].EM_D7
GIO039 F / _0
GIO GIO: GIO[039]
EM_D00 / H18 I/O AEMI VDD in Async EMIF: Data Bus bit[00] PINMUX2[5].EM_D7
GIO038 F / _0
GIO GIO: GIO[038]
EM_CE0 / J16 I/O AEMI VDD out H Async EMIF: Lowest numbered Chip Select. PINMUX2[6].EM_CE
GIO037 F / Can be programmed to be used for standard 0
GIO asynchronous memories (example:flash),
OneNand or NAND memory. Used for the
default boot and ROM boot modes.
GIO: GIO[037]
EM_CE1 / G19 I/O AEMI VDD out H Async EMIF: Second Chip Select., Can be PINMUX2[7].EM_CE
GIO036 F / programmed to be used for standard 1
GIO asynchronous memories (example: flash),
OneNand or NAND memory.
GIO: GIO[036]
Copyright © 2008–2010, Texas Instruments Incorporated Device Overview 47
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Table 2-23. DM335 Pin Descriptions (continued)
Name BGA Type Group Power PU Reset Description(4) Mux Control
ID (1) Supply(2) PD(3) State
EM_WE / J15 I/O AEMI VDD out H Async EMIF: Write Enable PINMUX2[8].EM_W
GIO035 F / E_OE
GIO NAND/SM/xD: WE (Write Enable) output
GIO: GIO[035]
EM_OE / F19 I/O AEMI VDD out H Async EMIF: Output Enable PINMUX2[8].EM_W
GIO034 F / E_OE
GIO NAND/SM/xD: RE (Read Enable) output
GIO: GIO[034]
EM_WAIT / G18 I/O AEMI VDD PU in H Async EMIF: Async WAIT PINMUX2[9].EM_W
GIO033 F / AIT
GIO NAND/SM/xD: RDY/_BSY input
GIO: GIO[033]
EM_ADV / H16 I/O AEMI VDD PD in L OneNAND: Address Valid Detect for PINMUX2[10].EM_A
GIO032 F / OneNAND interface DV
GIO GIO: GIO[032]
EM_CLK / E19 I/O AEMI VDD out L OneNAND: Clock signal for OneNAND flash PINMUX2[11].EM_C
GIO031 F / interface LK
GIO GIO: GIO[031]
ASP0_DX / H15 I/O ASP5 VDD in ASP0: Transmit Data PINMUX3[0].GIO30
GIO030 120 /
GIO GIO: GIO[030]
ASP0_CLKX / F18 I/O ASP5 VDD in ASP0: Transmit Clock PINMUX3[1].GIO29
GIO029 120 /
GIO GIO: GIO[029]
ASP0_FSX / G17 I/O ASP5 VDD in ASP0: Transmit Frame Synch PINMUX3[2].GIO28
GIO028 120 /
GIO GIO: GIO[028]
ASP0_DR / E18 I/O ASP5 VDD in ASP0: Receive Data PINMUX3[3].GIO27
GIO027 120 /
GIO GIO: GIO[027]
ASP0_CLKR / F17 I/O ASP5 VDD in ASP0: Receive Clock PINMUX3[4].GIO26
GIO026 120 /
GIO GIO: GIO[026]
ASP0_FSR / F16 I/O ASP5 VDD in ASP0: Receive Frame Synch PINMUX3[5].GIO25
GIO025 120 /
GIO GIO: GIO[025]
MMCSD1_CLK / C15 I/O MMC VDD in MMCSD1: Clock PINMUX3[6].GIO24
GIO024 SD /
GIO GIO: GIO[024]
MMCSD1_CMD A17 I/O MMC VDD in MMCSD1: Command PINMUX3[7].GIO23
/ GIO023 SD /
GIO GIO: GIO[023]
48 Device Overview Copyright © 2008–2010, Texas Instruments Incorporated
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SPRS528C–JULY 2008–REVISED JUNE 2010
Table 2-23. DM335 Pin Descriptions (continued)
Name BGA Type Group Power PU Reset Description(4) Mux Control
ID (1) Supply(2) PD(3) State
MMCSD1_DAT B16 I/O MMC VDD in MMCSD1: DATA3 PINMUX3[9:8].GIO2
A3 / GIO022 / SD / 2
UART2_RTS GIO /
UART
2GIO: GIO[022]
UART2: RTS
MMCSD1_DAT A16 I/O MMC VDD in MMCSD1: DATA2 PINMUX3[11:10].GI
A2 / GIO021 / SD / O21
UART2_CTS GIO /
UART
2GIO: GIO[021]
UART2: CTS
MMCSD1_DAT B15 I/O MMC VDD in MMCSD1: DATA1 PINMUX3[13:12].GI
A1 / GIO020 / SD / O20
UART2_RXD GIO /
UART
2GIO: GIO[020]
UART2: Receive Data
MMCSD1_DAT A18 I/O MMC VDD in MMCSD1: DATA0 PINMUX3[15:14].GI
A0 / GIO019 / SD / O19
UART2_TXD GIO /
UART
2GIO: GIO[019]
UART2: Transmit Data
CLKOUT1 / D12 I/O Clocks VDD in CLKOUT: Output Clock 1 PINMUX3[16].GIO1
GIO018 / GIO 8
GIO: GIO[018]
CLKOUT2 / A11 I/O Clocks VDD in CLKOUT: Output Clock 2 PINMUX3[17].GIO1
GIO017 / GIO 7
GIO: GIO[017]
CLKOUT3 / C11 I/O Clocks VDD in CLKOUT: Output Clock 3 PINMUX3[18].GIO1
GIO016 / GIO 6
GIO: GIO[016]
I2C_SDA / R13 I/O I2C / VDD in I2C: Serial Data PINMUX3[19].GIO1
GIO015 GIO 5
GIO: GIO[015]
I2C_SCL / R14 I/O I2C / VDD in I2C: Serial Clock PINMUX3[20].GIO1
GIO014 GIO 4
GIO: GIO[014]
UART1_RXD / R15 I/O UART VDD in UART1: Receive Data PINMUX3[21].GIO1
GIO013 1 / 3
GIO GIO: GIO[013]
UART1_TXD / R17 I/O UART VDD in UART1: Transmit Data PINMUX3[22].GIO1
GIO012 1 / 2
GIO GIO: GIO[012]
SPI1_SDENA[0] E13 I/O SPI1 / VDD in SPI1: Chip Select 0 PINMUX3[23].GIO1
/ GIO011 GIO 1
GIO: GIO[011]
Copyright © 2008–2010, Texas Instruments Incorporated Device Overview 49
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Table 2-23. DM335 Pin Descriptions (continued)
Name BGA Type Group Power PU Reset Description(4) Mux Control
ID (1) Supply(2) PD(3) State
SPI1_SCLK / C13 I/O SPI1 / VDD in SPI1: Clock PINMUX3[24].GIO1
GIO010 GIO 0
GIO: GIO[010]
SPI1_SDI / A13 I/O SPI1 / VDD in SPI1: Data In -OR- SPI1: Chip Select 1 PINMUX3[26:25].GI
GIO009 / GIO / O9
SPI1_SDENA[1] SPI1 GIO: GIO[009]
SPI1_SDO / E12 I/O SPI1 / VDD in SPI1: Data Out PINMUX3[27].GIO8
GIO008 GIO GIO: GIO[008]
GIO007 / C17 I/O GIO VDD in GIO: GIO[007] PINMUX3[28].GIO7
SPI0_SDENA[1] debou
nce /
SPI0 SPI0: Chip Select 1
GIO006 B18 I/O GIO VDD in GIO: GIO[006]
debou
nce
GIO005 D15 I/O GIO VDD in GIO: GIO[005]
debou
nce
GIO004 B17 I/O GIO VDD in GIO: GIO[004]
debou
nce
GIO003 G15 I/O GIO VDD in GIO: GIO[003]
debou
nce
GIO002 F15 I/O GIO VDD in GIO: GIO[002]
debou
nce
GIO001 E14 I/O GIO VDD in GIO: GIO[001]
debou
nce
GIO000 C16 I/O GIO VDD in GIO: GIO[000]
debou Note: The GIO000 pin must be held high
nce during NAND boot for the boot process to
fuction properly.
USB_DP A7 A I/O USBP VDDA33_USB USB D+ (differential signal pair)
HY
USB_DM A6 A I/O USBP VDDA33_USB USB D- (differential signal pair)
HY
USB_R1 C7 A I/O USBP USB Reference current output
HY Connect to VSS_USB_REF via 10K Ω±1%
resistor placed as close to the device as
possible.
USB_ID D5 A I/O USBP VDDA33_USB USB operating mode identification pin
HY For Device mode operation only, pull up this
pin to VDD with a 1.5K ohm resistor.
For Host mode operation only, pull down this
pin to ground (VSS) with a 1.5K ohm resistor.
If using an OTG or mini-USB connector, this
pin will be set properly via the
cable/connector configuration.
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SPRS528C–JULY 2008–REVISED JUNE 2010
Table 2-23. DM335 Pin Descriptions (continued)
Name BGA Type Group Power PU Reset Description(4) Mux Control
ID (1) Supply(2) PD(3) State
USB_VBUS E5 A I/O USBP For host or device mode operation, tie the
HY VBUS/USB power signal to the USB
connector.
When used in OTG mode operation, tie
VBUS to the external charge pump and to
the VBUS signal on the USB connector.
When the USB is not used, tie VBUS to
VSS_USB.
USB_DRVVBU C5 O USBP VDD Digital output to control external 5 V supply
S HY
VSS_USB_REF C8 GND USBP VDD USB Ground Reference
HY Connect directly to ground and to USB_R1
via 10K Ω±1% resistor placed as close to
the device as possible.
VDDA33_USB J8 PWR USBP VDD Analog 3.3 V power USB PHY (Transceiver)
HY
VSS_USB B7 GND USBP VDD Analog 3.3 V ground for USB PHY
HY (Transceiver)
VDDA33_USB_PLL B6 PWR USBP VDD Common mode 3.3 V power for USB PHY
HY (PLL)
VSS_USB D6 GND USBP VDD Common mode 3.3 V ground for USB PHY
HY (PLL)
VDDA13_USB H7 PWR USBP VDD Analog 1.3 V power for USB PHY
HY
VSS_USB E6 GND USBP VDD Analog 1.3 V ground for USB PHY
HY
VDDD13_USB C6 PWR USBP VDD Digital 1.3 V power for USB PHY
HY
MMCSD0_CLK A15 I/O MMC VDD out L MMCSD0: Clock PINMUX4[2].MMCS
SD0 D0_MS
MMCSD0_CMD C14 I/O MMC VDD in MMCSD0: Command PINMUX4[2].MMCS
SD0 D0_MS
MMCSD0_DAT A14 I/O MMC VDD in MMCSD0: DATA3 PINMUX4[2].MMCS
A3 SD0 D0_MS
MMCSD0_DAT B13 I/O MMC VDD in MMCSD0: DATA2 PINMUX4[2].MMCS
A2 SD0 D0_MS
MMCSD0_DAT D14 I/O MMC VDD in MMCSD0: DATA1 PINMUX4[2].MMCS
A1 SD0 D0_MS
MMCSD0_DAT B14 I/O MMC VDD in MMCSD0: DATA0 PINMUX4[2].MMCS
A0 SD0 D0_MS
UART0_RXD U18 I UART VDD in UART0: Receive Data
0Used for UART boot mode
UART0_TXD T18 O UART VDD out H UART0: Transmit Data
0Used for UART boot mode
SPI0_SDENA[0] B12 I/O SPI0 / VDD in SPI0: Enable / Chip Select 0 PINMUX4[0].SPI0_S
/ GIO103 GIO DENA
GIO: GIO[103]
SPI0_SCLK C12 I/O SPI0 VDD in SPI0: Clock
SPI0_SDI / A12 I/O SPI0 / VDD in SPI0: Data In PINMUX4[1].SPI0_S
GIO102 GIO DI
GIO: GIO[102]
SPI0_SDO B11 I/O SPI0 VDD in SPI0: Data Out
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Table 2-23. DM335 Pin Descriptions (continued)
Name BGA Type Group Power PU Reset Description(4) Mux Control
ID (1) Supply(2) PD(3) State
ASP1_DX C18 I/O ASP5 VDD in ASP1: Transmit Data
121
ASP1_CLKX D19 I/O ASP5 VDD in ASP1: Transmit Clock
121
ASP1_FSX E16 I/O ASP5 VDD in ASP1: Transmit Frame Sync
121
ASP1_DR C19 I/O ASP5 VDD in ASP1: Receive Data
121
ASP1_CLKR D18 I/O ASP5 VDD in ASP1: Receive Clock
121
ASP1_FSR E17 I/O ASP5 VDD in ASP1: Receive Frame Synch
121
ASP1_CLKS D17 I ASP5 VDD in ASP1: Master Clock
121
RESET D11 I VDD PU in Global Chip Reset (active low)
MXI1 A9 I Clocks VDD in Crystal input for system oscillator (24 MHz)
MXO1 B9 O Clocks VDD out Output for system oscillator (24 MHz)
MXI2 R1 I Clocks VDD in Crystal input for video oscillator (27 MHz).
This crystal is not required
VDD
MXO2 T1 O Clocks VDD out Output for video oscillator (27 MHz). This
crystal is not required.
VDD
TCK E10 I EMUL VDD PU in JTAG test clock input
ATIO
N
TDI D9 I EMUL VDD PU in JTAG test data input
ATIO
N
TDO E9 O EMUL VDD out L JTAG test data output
ATIO
N
TMS D8 I EMUL VDD PU in JTAG test mode select
ATIO
N
TRST C9 I EMUL VDD PD in JTAG test logic reset (active low)
ATIO
N
RTCK E11 O EMUL VDD out L JTAG test clock output
ATIO
N
EMU0 E8 I/O EMUL VDD PU in JTAG emulation 0 I/O
ATIO VDD
NVDD
EMU1 E7 I/O EMUL VDD PU in JTAG emulation 1 I/O
ATIO EMU[1:0] = 00 - Force Debug Scan chain
N(ARM and ARM ETB TAPs connected)
EMU[1:0] = 11 - Normal Scan chain (ICEpick
only)
RSV01 J1 A Reserved. This signal should be left as a No
I/O/Z Connect or connected to VSS.
RSV02 K1 A Reserved. This signal should be left as a No
I/O/Z Connect or connected to VSS.
RSV03 L1 A Reserved. This signal should be left as a No
I/O/Z Connect or connected to VSS.
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Table 2-23. DM335 Pin Descriptions (continued)
Name BGA Type Group Power PU Reset Description(4) Mux Control
ID (1) Supply(2) PD(3) State
RSV04 M1 A Reserved. This signal should be left as a No
I/O/Z Connect or connected to VSS.
RSV05 N2 A Reserved. This signal should be connected
I/O/Z to VSS.
RSV06 M2 PWR Reserved. This signal should be connected
to VSS.
RSV07 K2 GND Reserved. This signal should be connected
to VSS.
NC H8 No connect
VDD_VIN P6 PWR Power for Digital Video Input IO (3.3 V)
VDD_VIN P7 PWR Power for Digital Video Input IO (3.3 V)
VDD_VIN P8 PWR Power for Digital Video Input IO (3.3 V)
VDD_VOUT F6 PWR Power for Digital Video Output IO (3.3 V)
VDD_VOUT F7 PWR Power for Digital Video Output IO (3.3 V)
VDD_VOUT F8 PWR Power for Digital Video Output IO (3.3 V)
VDD_DDR M9 PWR Power for DDR I/O (1.8 V)
VDD_DDR P9 PWR Power for DDR I/O (1.8 V)
VDD_DDR P10 PWR Power for DDR I/O (1.8 V)
VDD_DDR P11 PWR Power for DDR I/O (1.8 V)
VDD_DDR P12 PWR Power for DDR I/O (1.8 V)
VDD_DDR P13 PWR Power for DDR I/O (1.8 V)
VDD_DDR P14 PWR Power for DDR I/O (1.8 V)
VDD_DDR R9 PWR Power for DDR I/O (1.8 V)
VDD_DDR R12 PWR Power for DDR I/O (1.8 V)
VDD_DDR T14 PWR Power for DDR I/O (1.8 V)
VDDA_PLL1 G12 PWR Analog Power for PLL1 (1.3 V)
VDDA_PLL2 H9 PWR Analog Power for PLL2 (1.3 V)
CVDD A1 PWR Core power (1.3 V)
CVDD A10 PWR Core power (1.3 V)
CVDD B19 PWR Core power (1.3 V)
CVDD C4 PWR Core power (1.3 V)
CVDD G6 PWR Core power (1.3 V)
CVDD G11 PWR Core power (1.3 V)
CVDD H10 PWR Core power (1.3 V)
CVDD H13 PWR Core power (1.3 V)
CVDD H17 PWR Core power (1.3 V)
CVDD J11 PWR Core power (1.3 V)
CVDD J12 PWR Core power (1.3 V)
CVDD J13 PWR Core power (1.3 V)
CVDD K6 PWR Core power (1.3 V)
CVDD K11 PWR Core power (1.3 V)
CVDD K12 PWR Core power (1.3 V)
CVDD L11 PWR Core power (1.3 V)
CVDD L12 PWR Core power (1.3 V)
CVDD N6 PWR Core power (1.3 V)
CVDD R7 PWR Core power (1.3 V)
CVDD R8 PWR Core power (1.3 V)
CVDD T17 PWR Core power (1.3 V)
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Table 2-23. DM335 Pin Descriptions (continued)
Name BGA Type Group Power PU Reset Description(4) Mux Control
ID (1) Supply(2) PD(3) State
CVDD W19 PWR Core power (1.3 V)
VDD F9 PWR Power for Digital IO (3.3 V)
VDD F10 PWR Power for Digital IO (3.3 V)
VDD F11 PWR Power for Digital IO (3.3 V)
VDD F12 PWR Power for Digital IO (3.3 V)
VDD F13 PWR Power for Digital IO (3.3 V)
VDD F14 PWR Power for Digital IO (3.3 V)
VDD G8 PWR Power for Digital IO (3.3 V)
VDD G14 PWR Power for Digital IO (3.3 V)
VDD K8 PWR Power for Digital IO (3.3 V)
VDD K15 PWR Power for Digital IO (3.3 V)
VDD L6 PWR Power for Digital IO (3.3 V)
VDD L13 PWR Power for Digital IO (3.3 V)
VDD M10 PWR Power for Digital IO (3.3 V)
VDD M11 PWR Power for Digital IO (3.3 V)
VDD M12 PWR Power for Digital IO (3.3 V)
VDD M13 PWR Power for Digital IO (3.3 V)
VDD N11 PWR Power for Digital IO (3.3 V)
VDD N12 PWR Power for Digital IO (3.3 V)
VSS_MX1 C10 GND System oscillator (24 MHz) - ground
VSS_MX2 P1 GND Video oscillator (27 MHz) - ground
VSSA_PLL1 H12 GND Analog Ground for PLL1
VSSA_PLL2 J9 GND Analog Ground for PLL2
VSS A5 GND Digital ground
VSS A8 GND Digital ground
VSS A19 GND Digital ground
VSS B5 GND Digital ground
VSS B8 GND Digital ground
VSS B10 GND Digital ground
VSS D1 GND Digital ground
VSS E2 GND Digital ground
VSS E15 GND Digital ground
VSS G2 GND Digital ground
VSS G9 GND Digital ground
VSS H1 GND Digital ground
VSS H2 GND Digital ground
VSS H6 GND Digital ground
VSS H11 GND Digital ground
VSS H14 GND Digital ground
VSS J2 GND Digital ground
VSS J6 GND Digital ground
VSS J10 GND Digital ground
VSS J14 GND Digital ground
VSS K3 GND Digital ground
VSS K9 GND Digital ground
VSS K10 GND Digital ground
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Table 2-23. DM335 Pin Descriptions (continued)
Name BGA Type Group Power PU Reset Description(4) Mux Control
ID (1) Supply(2) PD(3) State
VSS K14 GND Digital ground
VSS L2 GND Digital ground
VSS L9 GND Digital ground
VSS L10 GND Digital ground
VSS L14 GND Digital ground
VSS M6 GND Digital ground
VSS M7 GND Digital ground
VSS M8 GND Digital ground
VSS M14 GND Digital ground
VSS M17 GND Digital ground
VSS N1 GND Digital ground
VSS N8 GND Digital ground
VSS N9 GND Digital ground
VSS N14 GND Digital ground
VSS R2 GND Digital ground
VSS R6 GND Digital ground
VSS T2 GND Digital ground
VSS T5 GND Digital ground
VSS T15 GND Digital ground
VSS U1 GND Digital ground
VSS U2 GND Digital ground
VSS U3 GND Digital ground
VSS U4 GND Digital ground
VSS U9 GND Digital ground
VSS U14 GND Digital ground
VSS U17 GND Digital ground
VSS V1 GND Digital ground
VSS V18 GND Digital ground
VSS W1 GND Digital ground
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2.21 Device Support
2.21.1 Development Tools
TI offers an extensive line of development tools for DM335 systems, including tools to evaluate the
performance of the processors, generate code, develop algorithm implementations, and fully integrate and
debug software and hardware modules. The tools support documentation is electronically available within
the Code Composer Studio™ Integrated Development Environment (IDE).
The following products support development of DM335 based applications:
Software Development Tools:
Code Composer Studio™ Integrated Development Environment (IDE): including Editor
C/C++/Assembly Code Generation, and Debug plus additional development tools
Hardware Development Tools:
Extended Development System (XDS™) Emulator (supports TMS320DM335 DMSoC multiprocessor
system debug) EVM (Evaluation Module)
For a complete listing of development-support tools for the TMS320DM335 DMSoC platform, visit the
Texas Instruments web site on the Worldwide Web at http://www.ti.com. For information on pricing and
availability, contact the nearest TI field sales office or authorized distributor.
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2.21.2 Device Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
DSP devices and support tools. Each DSP commercial family member has one of three prefixes: TMX,
TMP, or TMS (e.g., ). Texas Instruments recommends two of three possible prefix designators for its
support tools: TMDX and TMDS. These prefixes represent evolutionary stages of product development
from engineering prototypes (TMX/TMDX) through fully qualified production devices/tools (TMS/TMDS).
Device development evolutionary flow:
TMX Experimental device that is not necessarily representative of the final device's electrical
specifications.
TMP Final silicon die that conforms to the device's electrical specifications but has not completed
quality and reliability verification.
TMS Fully-qualified production device.
Support tool development evolutionary flow:
TMDX Development-support product that has not yet completed Texas Instruments internal
qualification testing.
TMDS Fully qualified development-support product.
TMX and TMP devices and TMDX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
TMS devices and TMDS development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (TMX or TMP) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate is undefined. Only qualified production devices are to
be used in production.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, ZCE), the temperature range (for example, "Blank" is the commercial
temperature range), and the device speed range in megahertz (for example, 202 is 202.5 MHz). The
following figure provides a legend for reading the complete device name for any DM335 DMSoC platform
member.
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DM335
PREFIX
TMS 320 DM335 ZCE
TMX = Experimental device
TMS = Qualified device
DEVICE FAMILY
320 = TMS320 DSPfamily
PACKAGE TYPE (A)
ZCE = 337-pin plastic BGA, with Pb-free soldered balls
DEVICE(B)
( )
SILICON REVISION
SPEED GRADE
135 or 13 = 135 MHz
216 or 21 = 216 MHz
( ) ( )
TEMPERATURE RANGE (DEFAULT: 0°C TO 85°C)
Blank = 0
A = -40 to 100 , extended temperature
°C to 85°C, commercial temperature
°C °C
A. BGA = Ball Grid Array
B. For actual device part numbers (P/Ns) and ordering information, contact your nearest TI Sales representative.
C. For more information on silicon revision, see (literature number SPRZ287).TMS320DM335 DMSoC Silicon Errata
(C)
TMS320DM335
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Figure 2-5. Device Nomenclature
2.21.3 Device Documentation
2.21.3.1 Related Documentation From Texas Instruments
The following documents describe the TMS320DM335 Digital Media System-on-Chip (DMSoC). Copies of
these documents are available on the internet at www.ti.com.
SPRS528 TMS320DM335 Digital Media System-on-Chip (DMSoC) Data Manual This document
describes the overall TMS320DM335 system, including device architecture and features,
memory map, pin descriptions, timing characteristics and requirements, device mechanicals,
etc.
SPRZ287 TMS320DM335 DMSoC Silicon Errata Describes the known exceptions to the functional
specifications for the TMS320DM335 DMSoC.
SPRUFX7 TMS320DM335 Digital Media System-on-Chip (DMSoC) ARM Subsystem Reference
Guide This document describes the ARM Subsystem in the TMS320DM335 Digital Media
System-on-Chip (DMSoC). The ARM subsystem is designed to give the ARM926EJ-S
(ARM9) master control of the device. In general, the ARM is responsible for configuration
and control of the device; including the components of the ARM Subsystem, the peripherals,
and the external memories.
SPRUFZ1 TMS320DM335 Digital Media System-on-Chip (DMSoC) Asynchronous External
Memory Interface (EMIF) Reference Guide This document describes the asynchronous
external memory interface (EMIF) in the TMS320DM335 Digital Media System-on-Chip
(DMSoC). The EMIF supports a glueless interface to a variety of external devices.
SPRUFY9 TMS320DM335 Digital Media System-on-Chip (DMSoC) Universal Serial Bus (USB)
Controller Reference Guide This document describes the universal serial bus (USB)
controller in the TMS320DM335 Digital Media System-on-Chip (DMSoC). The USB controller
supports data throughput rates up to 480 Mbps. It provides a mechanism for data transfer
between USB devices and also supports host negotiation.
SPRUFZ3 TMS320DM335 Digital Media System-on-Chip (DMSoC) Audio Serial Port (ASP)
Reference Guide This document describes the operation of the audio serial port (ASP)
audio interface in the TMS320DM335 Digital Media System-on-Chip (DMSoC). The primary
audio modes that are supported by the ASP are the AC97 and IIS modes. In addition to the
primary audio modes, the ASP supports general serial port receive and transmit operation,
but is not intended to be used as a high-speed interface.
SPRUFY1 TMS320DM335 Digital Media System-on-Chip (DMSoC) Serial Peripheral Interface (SPI)
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Reference Guide This document describes the serial peripheral interface (SPI) in the
TMS320DM335 Digital Media System-on-Chip (DMSoC). The SPI is a high-speed
synchronous serial input/output port that allows a serial bit stream of programmed length (1
to 16 bits) to be shifted into and out of the device at a programmed bit-transfer rate. The SPI
is normally used for communication between the DMSoC and external peripherals. Typical
applications include an interface to external I/O or peripheral expansion via devices such as
shift registers, display drivers, SPI EPROMs and analog-to-digital converters.
SPRUFY2 TMS320DM335 Digital Media System-on-Chip (DMSoC) Universal Asynchronous
Receiver/Transmitter (UART) Reference Guide This document describes the universal
asynchronous receiver/transmitter (UART) peripheral in the TMS320DM335 Digital Media
System-on-Chip (DMSoC). The UART peripheral performs serial-to-parallel conversion on
data received from a peripheral device, and parallel-to-serial conversion on data received
from the CPU.
SPRUFY3 TMS320DM335 Digital Media System-on-Chip (DMSoC) Inter-Integrated Circuit (I2C)
Peripheral Reference Guide This document describes the inter-integrated circuit (I2C)
peripheral in the TMS320DM335 Digital Media System-on-Chip (DMSoC). The I2C
peripheral provides an interface between the DMSoC and other devices compliant with the
I2C-bus specification and connected by way of an I2C-bus. External components attached to
this 2-wire serial bus can transmit and receive up to 8-bit wide data to and from the DMSoC
through the I2C peripheral. This document assumes the reader is familiar with the I2C-bus
specification.
SPRUFY5 TMS320DM335 Digital Media System-on-Chip (DMSoC) Multimedia Card (MMC)/Secure
Digital (SD) Card Controller Reference Guide This document describes the multimedia
card (MMC)/secure digital (SD) card controller in the TMS320DM335 Digital Media
System-on-Chip (DMSoC). The MMC/SD card is used in a number of applications to provide
removable data storage. The MMC/SD controller provides an interface to external MMC and
SD cards. The communication between the MMC/SD controller and MMC/SD card(s) is
performed by the MMC/SD protocol.
SPRUFZ20 TMS320DM335 Digital Media System-on-Chip (DMSoC) Enhanced Direct Memory
Access (EDMA) Controller Reference Guide This document describes the operation of the
enhanced direct memory access (EDMA3) controller in the TMS320DM335 Digital Media
System-on-Chip (DMSoC). The EDMA controller's primary purpose is to service
user-programmed data transfers between two memory-mapped slave endpoints on the
DMSoC.
SPRUFY0 TMS320DM335 Digital Media System-on-Chip (DMSoC) 64-bit Timer Reference Guide
This document describes the operation of the software-programmable 64-bit timers in the
TMS320DM335 Digital Media System-on-Chip (DMSoC). Timer 0, Timer 1, and Timer 3 are
used as general-purpose (GP) timers and can be programmed in 64-bit mode, dual 32-bit
unchained mode, or dual 32-bit chained mode; Timer 2 is used only as a watchdog timer.
The GP timer modes can be used to generate periodic interrupts or enhanced direct memory
access (EDMA) synchronization events and Real Time Output (RTO) events (Timer 3 only).
The watchdog timer mode is used to provide a recovery mechanism for the device in the
event of a fault condition, such as a non-exiting code loop.
SPRUFY8 TMS320DM335 Digital Media System-on-Chip (DMSoC) General-Purpose Input/Output
(GPIO) Reference Guide This document describes the general-purpose input/output (GPIO)
peripheral in the TMS320DM335 Digital Media System-on-Chip (DMSoC). The GPIO
peripheral provides dedicated general-purpose pins that can be configured as either inputs
or outputs. When configured as an input, you can detect the state of the input by reading the
state of an internal register. When configured as an output, you can write to an internal
register to control the state driven on the output pin.
SPRUFY6 TMS320DM335 Digital Media System-on-Chip (DMSoC) Pulse-Width Modulator (PWM)
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Reference Guide This document describes the pulse-width modulator (PWM) peripheral in
the TMS320DM335 Digital Media System-on-Chip (DMSoC).
SPRUFZ2 TMS320DM335 Digital Media System-on-Chip (DMSoC) DDR2/Mobile DDR
(DDR2/mDDR) Memory Controller Reference Guide This document describes the
DDR2/mDDR memory controller in the TMS320DM335 Digital Media System-on-Chip
(DMSoC). The DDR2/mDDR memory controller is used to interface with JESD79D-2A
standard compliant DDR2 SDRAM and mobile DDR devices.
SPRUFX8 TMS320DM335 Digital Media System-on-Chip (DMSoC) Video Processing Front End
(VPFE) Reference Guide This document describes the Video Processing Front End (VPFE)
in the TMS320DM335 Digital Media System-on-Chip (DMSoC).
SPRUFX9 TMS320DM335 Digital Media System-on-Chip (DMSoC) Video Processing Back End
(VPBE) Reference Guide This document describes the Video Processing Back End (VPBE)
in the TMS320DM335 Digital Media System-on-Chip (DMSoC).
SPRUFY7 TMS320DM335 Digital Media System-on-Chip (DMSoC) Real-Time Out (RTO) Controller
Reference Guide This document describes the Real Time Out (RTO) controller in the
TMS320DM335 Digital Media System-on-Chip (DMSoC).
SPRAAL2 Implementing DDR2/mDDR PCB Layout on the TMS320DM335 DMSoC This provides
board design recommendations and guidelines for DDR2 and mobile DDR.
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3 Detailed Device Description
This section provides a detailed overview of the DM335 device.
3.1 ARM Subsystem Overview
The ARM Subsystem contains components required to provide the ARM926EJ-S (ARM) master control of
the overall DM335 system, including the components of the ARM Subsystem, the peripherals, and the
external memories.
The ARM is responsible for handling system functions such as system-level initialization, configuration,
user interface, user command execution, connectivity functions, interface and control of the subsystem,
etc. The ARM is master and performs these functions because it has a large program memory space and
fast context switching capability, and is thus suitable for complex, multi-tasking, and general-purpose
control tasks.
3.1.1 Components of the ARM Subsystem
The ARM Subsystem in DM335 consists of the following components:
• ARM926EJ-S RISC processor, including:
– coprocessor 15 (CP15)
– MMU
– 16KB Instruction cache
– 8KB Data cache
– Write Buffer
– Java accelerator
• ARM Internal Memories
– 32KB Internal RAM (32-bit wide access)
– 8KB Internal ROM (ARM bootloader for non-AEMIF boot options)
• Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)
• System Control Peripherals
– ARM Interrupt Controller
– PLL Controller
– Power and Sleep Controller
– System Control Module
The ARM also manages/controls all the device peripherals:
• DDR2 / mDDR EMIF Controller
• AEMIF Controller, including the OneNAND and NAND flash interface
• Enhanced DMA (EDMA)
• UART
• Timers
• Real Time Out (RTO)
• Pulse Width Modulator (PWM)
• Inter-IC Communication (I2C)
• Multi-Media Card/Secure Digital (MMC/SD)
• Audio Serial Port (ASP)
• Universal Serial Bus Controller (USB)
• Serial Port Interface (SPI)
• Video Processing Front End (VPFE)
– CCD Controller (CCDC)
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ARM926EJ-S
16KI$
8KD$ MMU
CP15
Arbiter Arbiter
I-AHB
D-AHB
Master
IF
DMA Bus
I-TCM
D-TCM
16K
RAM0
RAM1
16K
ROM
8K
Arbiter
Slave
IF
MasterIF
CFGBus
ARM
Interrupt
Controller
(AINTC)
Control
System
PLLC2
PLLC1
(PSC)
Controller
Sleep
Power
Peripherals
...
TMS320DM335
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– Image Pipe (IPIPE)
– H3A Engine (Hardware engine for computing Auto-focus, Auto white balance, and Auto exposure)
• Video Processing Back End (VPBE)
– On Screen Display (OSD)
– Video Encoder Engine (VENC)
Figure 3-1 shows the functional block diagram of the DM335 ARM Subsystem.
Figure 3-1. DM335 ARM Subsystem Block Diagram
3.2 ARM926EJ-S RISC CPU
The ARM Subsystem integrates the ARM926EJ-S processor. The ARM926EJ-S processor is a member of
ARM9 family of general-purpose microprocessors. This processor is targeted at multi-tasking applications
where full memory management, high performance, low die size, and low power are all important. The
ARM926EJ-S processor supports the 32-bit ARM and 16 bit THUMB instruction sets, enabling the user to
trade off between high performance and high code density. Specifically, the ARM926EJ-S processor
supports the ARMv5TEJ instruction set, which includes features for efficient execution of Java byte codes,
providing Java performance similar to Just in Time (JIT) Java interpreter, but without associated code
overhead.
The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both
hardware and software debug. The ARM926EJ-S processor has a Harvard architecture and provides a
complete high performance subsystem, including:
• ARM926EJ -S integer core
• CP15 system control coprocessor
• Memory Management Unit (MMU)
• Separate instruction and data Caches
• Write buffer
• Separate instruction and data Tightly-Coupled Memories (TCMs) [internal RAM] interfaces
• Separate instruction and data AHB bus interfaces
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• Embedded Trace Module and Embedded Trace Buffer (ETM/ETB)
For more complete details on the ARM9, refer to the ARM926EJ-S Technical Reference Manual, available
at http://www.arm.com
3.2.1 CP15
The ARM926EJ-S system control coprocessor (CP15) is used to configure and control instruction and
data caches, Tightly-Coupled Memories (TCMs), Memory Management Unit (MMU), and other ARM
subsystem functions. The CP15 registers are programmed using the MRC and MCR ARM instructions,
when the ARM in a privileged mode such as supervisor or system mode.
3.2.2 MMU
The ARM926EJ-S MMU provides virtual memory features required by operating systems such as Linux,
WindowCE, ultron, ThreadX, etc. A single set of two level page tables stored in main memory is used to
control the address translation, permission checks and memory region attributes for both data and
instruction accesses. The MMU uses a single unified Translation Lookaside Buffer (TLB) to cache the
information held in the page tables. The MMU features are:
• Standard ARM architecture v4 and v5 MMU mapping sizes, domains and access protection scheme.
• Mapping sizes are:
– 1MB (sections)
– 64KB (large pages)
– 4KB (small pages)
– 1KB (tiny pages)
• Access permissions for large pages and small pages can be specified separately for each quarter of
the page (subpage permissions)
• Hardware page table walks
• Invalidate entire TLB, using CP15 register 8
• Invalidate TLB entry, selected by MVA, using CP15 register 8
• Lockdown of TLB entries, using CP15 register 10
3.2.3 Caches and Write Buffer
The size of the Instruction Cache is 16KB, Data cache is 8KB. Additionally, the Caches have the following
features:
• Virtual index, virtual tag, and addressed using the Modified Virtual Address (MVA)
• Four-way set associative, with a cache line length of eight words per line (32-bytes per line) and with
two dirty bits in the Dcache
• Dcache supports write-through and write-back (or copy back) cache operation, selected by memory
region using the C and B bits in the MMU translation tables.
• Critical-word first cache refilling
• Cache lockdown registers enable control over which cache ways are used for allocation on a line fill,
providing a mechanism for both lockdown, and controlling cache corruption
• Dcache stores the Physical Address TAG (PA TAG) corresponding to each Dcache entry in the TAG
RAM for use during the cache line write-backs, in addition to the Virtual Address TAG stored in the
TAG RAM. This means that the MMU is not involved in Dcache write-back operations, removing the
possibility of TLB misses related to the write-back address.
• Cache maintenance operations provide efficient invalidation of, the entire Dcache or Icache, regions of
the Dcache or Icache, and regions of virtual memory.
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The write buffer is used for all writes to a noncachable bufferable region, write-through region and write
misses to a write-back region. A separate buffer is incorporated in the Dcache for holding write-back for
cache line evictions or cleaning of dirty cache lines. The main write buffer has 16-word data buffer and a
four-address buffer. The Dcache write-back has eight data word entries and a single address entry.
3.2.4 Tightly Coupled Memory (TCM)
ARM internal RAM is provided for storing real-time and performance-critical code/data and the Interrupt
Vector table. ARM internal ROM boot options include—NAND (with SPI EEPROM Boot option), SPI,
UART and MMC/SD. The RAM and ROM memories interfaced to the ARM926EJ-S via the tightly coupled
memory interface that provides for separate instruction and data bus connections. Since the ARM TCM
does not allow instructions on the D-TCM bus or data on the I-TCM bus, an arbiter is included so that both
data and instructions can be stored in the internal RAM/ROM. The arbiter also allows accesses to the
RAM/ROM from extra-ARM sources (e.g., EDMA or other masters). The ARM926EJ-S has built-in DMA
support for direct accesses to the ARM internal memory from a non-ARM master. Because of the
time-critical nature of the TCM link to the ARM internal memory, all accesses from non-ARM devices are
treated as DMA transfers.
Instruction and Data accesses are differentiated via accessing different memory map regions, with the
instruction region from 0x0000 through 0x7FFF and data from 0x10000 through 0x17FFF. Placing the
instruction region at 0x0000 is necessary to allow the ARM Interrupt Vector table to be placed at 0x0000,
as required by the ARM architecture. The internal 32-KB RAM is split into two physical banks of 16KB
each, which allows simultaneous instruction and data accesses to be accomplished if the code and data
are in separate banks.
3.2.5 Advanced High-performance Bus (AHB)
The ARM Subsystem uses the AHB port of the ARM926EJ-S to connect the ARM to the configuration bus
and the external memories. Arbiters are employed to arbitrate access to the separate D-AHB and I-AHB
by the configuration bus and the external memories bus.
3.2.6 Embedded Trace Macrocell (ETM) and Embedded Trace Buffer (ETB)
To support real-time trace, the ARM926EJ-S processor provides an interface to enable connection of an
Embedded Trace Macrocell (ETM). The ARM926ES-J Subsystem in DM335 also includes the Embedded
Trace Buffer (ETB). The ETM consists of two parts:
• Trace Port provides real-time trace capability for the ARM9.
• Triggering facilities provide trigger resources, which include address and data comparators, counter,
and sequencers.
The DM335 trace port is not pinned out and is instead only connected to the Embedded Trace Buffer. The
ETB has a 4KB buffer memory. ETB enabled debug tools are required to read/interpret the captured trace
data.
3.3 Memory Mapping
The ARM memory map is shown in Table 2-2 and Table 2-3. This section describes the memories and
interfaces within the ARM's memory map.
3.3.1 ARM Internal Memories
The ARM has access to the following ARM internal memories:
• 32KB ARM Internal RAM on TCM interface, logically separated into two 16KB pages to allow
simultaneous access on any given cycle if there are separate accesses for code (I-TCM bus) and data
(D-TCM) to the different memory regions.
• 8KB ARM Internal ROM
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3.3.2 External Memories
The ARM has access to the following External memories:
• DDR2 / mDDR Synchronous DRAM
• Asynchronous EMIF / OneNAND
• NAND Flash
• Flash card devices:
– MMC/SD
– xD
– SmartMedia
3.3.3 Peripherals
The ARM has access to all of the peripherals on the DM335 device.
3.4 ARM Interrupt Controller (AINTC)
The DM335 ARM Interrupt Controller (AINTC) has the following features:
• Supports up to 64 interrupt channels (16 external channels)
• Interrupt mask for each channel
• Each interrupt channel can be mapped to a Fast Interrupt Request (FIQ) or to an Interrupt Request
(IRQ) type of interrupt.
• Hardware prioritization of simultaneous interrupts
• Configurable interrupt priority (2 levels of FIQ and 6 levels of IRQ)
• Configurable interrupt entry table (FIQ and IRQ priority table entry) to reduce interrupt processing time
The ARM core supports two interrupt types: FIQ and IRQ. See the ARM926EJ-S Technical Reference
Manual for detailed information about the ARM’s FIQ and IRQ interrupts. Each interrupt channel is
mappable to an FIQ or to an IRQ type of interrupt, and each channel can be enabled or disabled. The
INTC supports user-configurable interrupt-priority and interrupt entry addresses. Entry addresses minimize
the time spent jumping to interrupt service routines (ISRs). When an interrupt occurs, the corresponding
highest priority ISR’s address is stored in the INTC’s ENTRY register. The IRQ or FIQ interrupt routine can
read the ENTRY register and jump to the corresponding ISR directly. Thus, the ARM does not require a
software dispatcher to determine the asserted interrupt.
3.4.1 Interrupt Mapping
The AINTC takes up to 64 ARM device interrupts and maps them to either the IRQ or to the FIQ of the
ARM. Each interrupt is also assigned one of 8 priority levels (2 for FIQ, 6 for IRQ). For interrupts with the
same priority level, the priority is determined by the hardware interrupt number (the lowest number has the
highest priority). Table 3-1 shows the connection of device interrupts to the ARM.
Table 3-1. AINTC Interrupt Connections(1)
Interrupt Acronym Source Interrupt Acronym Source
Number Number
0 VPSSINT0 VPSS - INT0, 32 TINT0 Timer 0 - TINT12
Configurable via
VPSSBL register:
INTSEL
1 VPSSINT1 VPSS - INT1 33 TINT1 Timer 0 - TINT34
2 VPSSINT2 VPSS - INT2 34 TINT2 Timer 1 - TINT12
(1) The total number of interrupts in DM335 exceeds 64, which is the maximum value of the AINTC module. Therefore, several interrupts
are multiplexed and you must use the register ARM_INTMUX in the System Control Module to select the interrupt source for multiplexed
interrupts. Refer to the TMS320DM335 Digital Media System-on-Chip (DMSoC) ARM Subsystem Reference Guide (literature number
SPRUFX7 ) for more information on the System Control Module register ARM_INTMUX.
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Table 3-1. AINTC Interrupt Connections (1) (continued)
Interrupt Acronym Source Interrupt Acronym Source
Number Number
3 VPSSINT3 VPSS - INT3 35 TINT3 Timer 1 - TINT34
4 VPSSINT4 VPSS - INT4 36 PWMINT0 PWM0
5 VPSSINT5 VPSS - INT5 37 PWMINT1 PWM 1
6 VPSSINT6 VPSS - INT6 38 PWMINT2 PWM2
7 VPSSINT7 VPSS - INT7 39 I2CINT I2C
8 VPSSINT8 VPSS - INT8 40 UARTINT0 UART0
9 Reserved 41 UARTINT1 UART1
10 Reserved 42 SPINT0-0 SPI0
11 Reserved 43 SPINT0-1 SPI0
12 USBINT USB OTG Collector 44 GPIO0 GPIO
13 RTOINT or RTO or 45 GPIO1 GPIO
TINT4 Timer 2 - TINT12
SYS.ARM_INTMUX
14 UARTINT2 or UART2 or 46 GPIO2 GPIO
TINT5 Timer 2 - TINT34
15 TINT6 Timer 3 TINT12 47 GPIO3 GPIO
16 CCINT0 EDMA CC Region 0 48 GPIO4 GPIO
17 SPINT1-0 or SPI1 or 49 GPIO5 GPIO
CCERRINT EDMA CC Error
18 SPINT1-1 or SPI1 or 50 GPIO6 GPIO
TCERRINT0 EDMA TC0 Error
19 SPINT2-0 or SPI2 or 51 GPIO7 GPIO
TCERRINT1 EDMA TC1 Error
20 PSCINT PSC - ALLINT 52 GPIO8 GPIO
21 SPINT2-1 SPI2 53 GPIO9 GPIO
22 TINT7 Timer3 - TINT34 54 GPIOBNK0 GPIO
23 SDIOINT0 MMC/SD0 55 GPIOBNK1 GPIO
24 MBXINT0 or ASP0 or 56 GPIOBNK2 GPIO
MBXINT1 ASP1
25 MBRINT0 or ASP0 or 57 GPIOBNK3 GPIO
MBRINT1 ASP1
26 MMCINT0 MMC/SD0 58 GPIOBNK4 GPIO
27 MMCINT1 MMC/SC1 59 GPIOBNK5 GPIO
28 PWMINT3 PWM3 60 GPIOBNK6 GPIO
29 DDRINT DDR EMIF 61 COMMTX ARMSS
30 AEMIFINT Async EMIF 62 COMMRX ARMSS
31 SDIOINT1 SDIO1 63 EMUINT E2ICE
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3.5 Device Clocking
3.5.1 Overview
The DM335 requires one primary reference clock . The reference clock frequency may be generated
either by crystal input or by external oscillator. The reference clock is the clock at the pins named
MXI1/MXO1. The reference clock drives two separate PLL controllers (PLLC1 and PLLC2). PLLC1
generates the clocks required by the ARM, VPBE,VPSS, and peripherals. PLL2 generates the clock
required by the DDR PHY. A block diagram of DM335's clocking architecture is shown in Figure 3-2 . The
PLLs are described further in Section 3.6.
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ARMSubsystem
SYSCLK1
SYSCLK2
VPFE
VPBE
DAC
DDRPHY
DDR
PLLDIV1(/1)
BPDIV(/8)
PLL Controller2
PLL Controller1
PLLDIV3(/n)
PLLDIV2(/4)
PLLDIV1(/2)
SYSCLK3
I2C
Timers(x4)
PWMs(x4)
SPI(x3)
MMC/SD(x2)
EMIF/NAND
ASP (x2)
GPIO
UART2
ARMINTC
USB
60MHz
Reference
Clock
(MXI/MXO)
(24MHzor
36MHz)
ReferenceClock
(MXI/MXO)
24MHzor36MHz
PCLK
AUXCLK(/1)
BPDIV(/3)
SYSCLK1
CLKOUT3
SYSCLKBP
CLKOUT2
EDMA
BusLogic
SysLogic
PSC
IcePick
EXTCLK
RTO
USBPhy
SYSCLKBP
AUXCLK
PLLDIV4(/4or/2) VPSS
UART0,1
CLKOUT1
Sequencer
SYSCLK4
TMS320DM335
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Figure 3-2. Device Clocking Block Diagram
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3.5.2 Supported Clocking Configurations for DM335-135
This section describes the only supported device clocking configurations for DM335-135. The DM335
supports either 24 MHz (typical) or 36 MHz reference clock (crystal or external oscillator input).
Configurations are shown for both cases.
3.5.2.1 Supported Clocking Configurations for DM335-135 (24 MHz reference)
3.5.2.1.1 DM335-135 PLL1 (24 MHz reference)
All supported clocking configurations for DM335-135 PLL1 with 24 MHz reference clock are shown in
Table 3-2.
Table 3-2. PLL1 Supported Clocking Configurations for DM335-135 (24 MHz reference)
PREDIV PLLM POSTDIV PLL1 ARM Peripherals VENC VPSS
VCO
(/8 fixed) (m programmable) (/2 or /1 (MHz) PLLDIV1 SYSCLK1 PLLDIV2 SYSCLK2 PLLDIV3 SYSCLK3 PLLDIV4 SYSCLK4
programmable) (/2 fixed) (MHz) (/4 fixed) (MHz) (/n (MHz) (/4 or /2 (MHz)
programmable) programmable)
bypass bypass bypass bypass 2 12 4 6 10 2.4 4 6
8 180 2 270 2 135 4 67.5 10 27 2 135
8 162 2 243 2 121.5 4 60.75 9 27 2 121.5
8 144 2 216 2 108 4 54 8 27 2 108
8 126 2 189 2 94.5 4 47.25 7 27 2 94.5
8 108 2 162 2 81 4 40.5 6 27 2 81
3.5.2.1.2 DM335-135 PLL2 (24 MHz reference)
All supported clocking configurations for DM335-135 PLL2 with 24 MHz reference clock are shown in
Table 3-3.
Table 3-3. PLL2 Supported Clocking Configurations for DM335-135 (24 MHz reference)
PREDIV PLLM POSTDIV PLL2 VCO DDR PHY DDR Clock
(/n programmable) (m programmable) (/1 fixed) (MHz) PLLDIV1 SYSCLK1 DDR_CLK
(/1 fixed) (MHz) (MHz)
bypass bypass bypass bypass 1 24 12
12 133 1 266 1 266 133
12 100 1 200 1 200 100
15 100 1 160 1 160 80
3.5.2.2 Supported Clocking Configurations for DM335-135 (36 MHz reference)
3.5.2.2.1 DM335-135PLL1 (36 MHz reference)
All supported clocking configurations for DM335-135 PLL1 with 36 MHz reference clock are shown in
Table 3-4.
Table 3-4. PLL1 Supported Clocking Configurations DM335-135 (36 MHz reference)
PREDIV PLLM POSTDIV PLL1 ARM coprocessor Peripherals VENC VPSS
VCO
(/8 fixed) (m (/2 or /1 (MHz) PLLDIV1 SYSCLK1 PLLDIV2 SYSCLK2 PLLDIV3 SYSCLK3 PLLDIV4 SYSCLK4
programmable) programmable) (/2 fixed) (MHz) (/4 fixed) (MHz) (/n (MHz) (/4 or /2 programmable) (MHz)
programmable)
bypass bypass bypass bypass 2 18 4 9 10 3.6 4 18
8 120 2 270 2 135 4 67.5 10 27 2 135
8 108 2 243 2 121.5 4 60.75 9 27 2 121.5
8 96 2 216 2 108 4 54 8 27 2 108
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3.5.2.2.2 DM335-135 PLL2 (36 MHz reference)
All supported clocking configurations for DM335-135 PLL2 with 36 MHz reference clock are shown in
Table 3-5.
Table 3-5. PLL2 Supported Clocking Configurations for DM335-135 (36 MHz reference)
PREDIV PLLM POSTDIV PLL2 VCO DDR PHY DDR Clock
(/n programmable) (m programmable) (/1 fixed) (MHz) PLLDIV1 SYSCLK1 DDR_CLK
(/1 fixed) (MHz) (MHz)
bypass bypass bypass bypass 1 36 18
18 133 1 266 1 266 133
27 150 1 200 1 200 100
27 120 1 160 1 160 80
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3.5.3 Supported Clocking Configurations for DM335-216
This section describes the only supported device clocking configurations for DM335-216. The DM335
supports either 24 MHz (typical) or 36 MHz reference clock (crystal or external oscillator input).
Configurations are shown for both cases.
3.5.3.1 Supported Clocking Configurations for DM335-216 (24 MHz reference)
3.5.3.1.1 DM335-216 PLL1 (24 MHz reference)
All supported clocking configurations for DM335-216 PLL1 with 24 MHz reference clock are shown in
Table 3-2.
Table 3-6. PLL1 Supported Clocking Configurations for DM335-216 (24 MHz reference)
PREDIV PLLM POSTDIV PLL1 ARM Peripherals VENC VPSS
VCO
(/8 fixed) (m programmable) (/2 or /1 (MHz) PLLDIV1 SYSCLK1 PLLDIV2 SYSCLK2 PLLDIV3 SYSCLK3 PLLDIV4 SYSCLK4
programmable) (/2 fixed) (MHz) (/4 fixed) (MHz) (/n (MHz) (/4 or /2 (MHz)
programmable) programmable)
bypass bypass bypass bypass 2 12 4 6 10 2.4 4 6
8 144 1 432 2 216 4 108 16 27 4 108
8 135 1 405 2 202.5 4 101.25 15 27 4 101.25
8 126 1 378 2 189 4 94.5 14 27 4 94.5
8 117 1 351 2 175.5 4 87.75 13 27 4 87.75
8 108 1 324 2 162 4 81 12 27 4 81
8 99 1 297 2 148.5 4 74.25 11 27 4 74.25
8 180 2 270 2 135 4 67.5 10 27 2 135
8 162 2 243 2 121.5 4 60.75 9 27 2 121.5
8 144 2 216 2 108 4 54 8 27 2 108
8 126 2 189 2 94.5 4 47.25 7 27 2 94.5
8 108 2 162 2 81 4 40.5 6 27 2 81
3.5.3.1.2 DM335-216 PLL2 (24 MHz reference)
All supported clocking configurations for DM335-216 PLL2 with 24 MHz reference clock are shown in
Table 3-3.
Table 3-7. PLL2 Supported Clocking Configurations for DM335-216 (24 MHz reference)
PREDIV PLLM POSTDIV PLL2 VCO DDR PHY DDR Clock
(/n programmable) (m programmable) (/1 fixed) (MHz) PLLDIV1 SYSCLK1 DDR_CLK
(/1 fixed) (MHz) (MHz)
bypass bypass bypass bypass 1 24 12
8 114 1 342 1 342 171
8 108 1 324 1 324 162
8 102 1 306 1 306 153
8 96 1 288 1 288 144
12 133 1 266 1 266 133
12 100 1 200 1 200 100
15 100 1 160 1 160 80
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3.5.3.2 Supported Clocking Configurations for DM335-216 (36 MHz reference)
3.5.3.2.1 DM335-216 PLL1 (36 MHz reference)
All supported clocking configurations for DM335-216 PLL1 with 36 MHz reference clock are shown in
Table 3-4.
Table 3-8. PLL1 Supported Clocking Configurations DM335-216 (36 MHz reference)
PREDIV PLLM POSTDIV PLL1 VCO ARM Peripherals VENC VPSS
(/8 fixed) (m programmable) (/2 or /1 (MHz) PLLDIV1 SYSCLK1 PLLDIV2 SYSCLK2 PLLDIV3 SYSCLK3 PLLDIV4 SYSCLK4
programmable) (/2 fixed) (MHz) (/4 fixed) (MHz) (/n (MHz) (/4 or /2 (MHz)
programmable) programmable)
bypass bypass bypass bypass 2 18 4 9 10 3.6 4 9
8 96 1 432 2 216 4 108 16 27 4 108
8 180 2 405 2 202.5 4 101.25 15 27 4 101.25
8 168 2 378 2 189 4 94.5 14 27 4 94.5
8 156 2 351 2 175.5 4 87.75 13 27 4 87.75
8 144 2 324 2 162 4 81 12 27 4 81
8 132 2 297 2 148.5 4 74.25 11 27 4 74.25
8 120 2 270 2 135 4 67.5 10 27 2 135
8 108 2 243 2 121.5 4 60.75 9 27 2 121.5
8 96 2 216 2 108 4 54 8 27 2 108
3.5.3.2.2 DM335-216 PLL2 (36 MHz reference)
All supported clocking configurations for DM335-216 PLL2 with 36 MHz reference clock are shown in
Table 3-5.
Table 3-9. PLL2 Supported Clocking Configurations for DM335-216 (36 MHz reference)
PREDIV PLLM POSTDIV PLL2 VCO DDR PHY DDR Clock
(/n programmable) (m programmable) (/1 fixed) (MHz) PLLDIV1 SYSCLK1 DDR_CLK
(/1 fixed) (MHz) (MHz)
bypass bypass bypass bypass 1 36 18
12 114 1 342 1 342 171
12 108 1 324 1 324 162
12 102 1 306 1 306 153
12 96 1 288 1 288 144
18 133 1 266 1 266 133
27 150 1 200 1 200 100
27 120 1 160 1 160 80
3.5.4 Peripheral Clocking Considerations
3.5.4.1 Video Processing Back End Clocking
The Video Processing Back End (VPBE) is a sub-module of the Video Processing Subsystem (VPSS).
The VPBE is designed to interface with a variety of LCDs and an internal DAC module. There are two
asynchronous clock domains in the VPBE: an internal clock domain and an external clock domain. The
internal clock domain is driven by the VPSS clock (PLL1 SYSCLK4). The external clock domain is
configurable; you can select one of five source:
• 24 MHz crystal input at MXI1
• 27 MHz crystal input at MXI2 (optional feature, not typically used)
• PLL1 SYSCLK3
• EXTCLK pin (external VPBE clock input pin)
• PCLK pin (VPFE pixel clock input pin)
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See the TMS320DM335 Digital Media System-on-Chip (DMSoC) Video Processing Back End (VPBE)
Reference Guide (literature number SPRUFX9) for complete information on VPBE clocking.
3.5.4.2 USB Clocking
The USB Controller is driven by two clocks: an output clock of PLL1 (SYSCLK2) and an output clock of
the USB PHY.
NOTE
For proper USB 2.0 function, SYSCLK2 must be greater than 60 MHz.
The USB PHY takes an input clock that is configurable by the USB PHY clock source bits (PHYCLKSRC)
in the USB PHY control register (USB_PHY_CTL) in the System Control Module. When a 24 MHz crystal
is used at MXI1/MXO1, set PHYCLKSRC to 0. This will present a 24 MHz clock to the USB PHY. When a
36 MHz crystal is used at MXI1/MXO1, set PHYCLKSRC to 1. This will present a 12 MHz clock (36 MHz
divided internally by three) to the USB PHY. The USB PHY is capable of accepting only 24 MHz and 12
MHz; thus you must use either a 24 MHz or 36 MHz crystal at MXI1/MXO1. See the TMS320DM335
Digital Media System-on-Chip (DMSoC) Universal Serial Bus (USB) Controller Reference Guide (literature
number SPRUFY9) for more information. See the TMS320DM335 Digital Media System-on-Chip (DMSoC)
ARM Subsystem Reference Guide (literature number SPRUFX7) for more information on the System
Control Module.
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3.6 PLL Controller (PLLC)
This section describes the PLL Controllers for PLL1 and PLL2. See the TMS320DM335 Digital Media
System-on-Chip (DMSoC) ARM Subsystem Reference Guide (literature number SPRUFX7) for more
information on the PLL controllers.
3.6.1 PLL Controller Module
The DM335 has two PLL controllers that provide clocks to different components of the chip. PLL controller
1 (PLLC1) provides clocks to most of the components of the chip. PLL controller 2 (PLLC2) provides
clocks to the DDR PHY.
As a module, the PLL controller provides the following:
• Glitch-free transitions (on changing PLL settings)
• Domain clocks alignment
• Clock gating
• PLL bypass
• PLL power down
The various clock outputs given by the PLL controller are as follows:
• Domain clocks: SYSCLKn
• Bypass domain clock: SYSCLKBP
• Auxiliary clock from reference clock: AUXCLK
Various dividers that can be used are as follows:
• Pre-PLL divider: PREDIV
• Post-PLL divider: POSTDIV
• SYSCLK divider: PLLDIV1, …, PLLDIVn
• SYSCLKBP divider: BPDIV
Multipliers supported are as follows:
• PLL multiplier control: PLLM
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3.6.2 PLLC1
PLLC1 provides most of the DM335 clocks. Software controls PLLC1 operation through the PLLC1
registers. The following list, Table 3-10, and Figure 3-3 describe the customizations of PLLC1 in the
DM335.
• Provides primary DM335 system clock
• Software configurable
• Accepts clock input or internal oscillator input
• PLL pre-divider value is fixed to (/8)
• PLL multiplier value is programmable
• PLL post-divider
• Only SYSCLK[4:1] are used
• SYSCLK1 divider value is fixed to (/2)
• SYSCLK2 divider value is fixed to (/4)
• SYSCLK3 divider value is programmable
• SYSCLK4 divider value is programmable to (/4) or (/2)
• SYSCLKBP divider value is fixed to (/3)
• SYSCLK1 is routed to the ARM Subsystem
• SYSCLK2 is routed to peripherals
• SYSCLK3 is routed to the VPBE module
• SYSCLK4 is routed to the VPSS module
• AUXCLK is routed to peripherals with fixed clock domain and also to the output pin CLKOUT1
• SYSCLKBP is routed to the output pin CLKOUT2
Table 3-10. PLLC1 Output Clocks
Output Clock Used By PLLDIV Notes
Divider
SYSCLK1 ARM Subsystem /2 Fixed divider
SYSCLK2 Peripherals /4 Fixed divider
SYSCLK3 VPBE (VENC module) /n Programmable divider (used to get 27
MHz for VENC)
SYSCLK4 VPSS /4 or /2 Programmable divider
AUXCLK Peripherals, CLKOUT1 none No divider
SYSCLKBP CLKOUT2 /3 Fixed divider
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PLLDIV1(/2)
PLLDIV2(/4)
PLLDIV3(/3)
SYSCLK1
(ARM)
SYSCLK2
(Peripherals)
SYSCLK3
(VPBE)
1
0
PLL
0
1
CLKMODE
CLKIN
OSCIN
PLLEN
AUXCLK
(Peripherals,
CLKOUT1)
SYSCLKBP
(CLKOUT2)
Pre-DIV
(/8)
Post-DIV
(/2or/1)
PLLM
(Programmable)
BPDIV(/3)
PLLDIV4
(/4or/2)
SYSCLK4
(VPSS)
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Figure 3-3. PLLC1 Configuration in DM335
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3.6.3 PLLC2
PLLC2 provides the DDR PHY clock and CLKOUT3. Software controls PLLC2 operation through the
PLLC2 registers. The following list, Table 3-11, and Figure 3-4 describe the customizations of PLLC2 in
the DM335.
• Provides DDR PHY clock and CLKOUT3
• Software configurable
• Accepts clock input or internal oscillator input (same input as PLLC1)
• PLL pre-divider value is programmable
• PLL multiplier value is programmable
• PLL post-divider value is fixed to (/1)
• Only SYSCLK[1] is used
• SYSCLK1 divider value is fixed to (/1)
• SYSCLKBP divider value is fixed to (/8)
• SYSCLK1 is routed to the DDR PHY
• SYSCLKBP is routed to the output pin CLKOUT3
• AUXCLK is not used.
Table 3-11. PLLC2 Output Clocks
Output Clock Used by PLLDIV Divider Notes
SYSCLK1 DDR PHY /1 Fixed divider
SYSCLKBP CLKOUT3 /8 Fixed divider
Figure 3-4. PLLC2 Configuration in DM335
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arm_clock
arm_mreset
arm_power
AINTC
ARM
module_power
module_mreset
MODx
module_clock
Alwayson
domain
Interrupt
PSC
clks
PLLC
Emulation
RESET
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3.7 Power and Sleep Controller (PSC)
In the DM335 system, the Power and Sleep Controller (PSC) is responsible for managing transitions of
system power on/off, clock on/off, and reset. A block diagram of the PSC is shown in Figure 3-5. Many of
the operations of the PSC are transparent to software, such as power-on-reset operations. However, the
PSC provides you with an interface to control several important clock and reset operations.
The PSC includes the following features:
• Manages chip power-on/off, clock on/off, and resets
• Provides a software interface to:
– Control module clock ON/OFF
– Control module resets
• Supports IcePick emulation features: power, clock, and reset
For more information on the PSC, see the TMS320DM335 Digital Media System-on-Chip (DMSoC) ARM
Subsystem Reference Guide (literature number SPRUFX7).
Figure 3-5. DM335 Power and Sleep Controller (PSC)
3.8 System Control Module
The DM335’s system control module is a system-level module containing status and top-level control logic
required by the device. The system control module consists of a miscellaneous set of status and control
registers, accessible by the ARM and supporting all of the following system features and operations:
• Device identification
• Device configuration
– Pin multiplexing control
– Device boot configuration status
• ARM interrupt and EDMA event multiplexing control
• Special peripheral status and control
– Timer64+
– USB PHY control
– VPSS clock and video DAC control and status
– DDR VTP control
– Clockout circuitry
– GIO de-bounce control
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• Power management
– Deep sleep and fast NAND boot control
• Bandwidth Management
– Bus master DMA priority control
For more information on the System Control Module refer to the TMS320DM335 Digital Media
System-on-Chip (DMSoC) ARM Subsystem Reference Guide (literature number SPRUFX7).
3.9 Pin Multiplexing
The DM335 makes extensive use of pin multiplexing to accommodate the large number of peripheral
functions in the smallest possible package. In order to accomplish this, pin multiplexing is controlled using
a combination of hardware configuration (at device reset) and software control. No attempt is made by the
DM335 hardware to ensure that the proper pin muxing has been selected for the peripherals or interface
mode being used, thus proper pin muxing configuration is the responsibility of the board and software
designers. An overview of the pin multiplexing is shown in Table 3-12.
Table 3-12. Peripheral Pin Mux Overview
Peripheral Muxed With Primary Function Secondary Function Tertiary Function
VPFE (video in) GPIO and SPI2 VPFE (video in) SPI2 GPIO
VPBE (video out) GPIO, PWM, and RTO VPBE (video out) PWM and RTO GPIO
AEMIF GPIO AEMIF GPIO none
ASP0 GPIO ASP0 GPIO none
MMC/SD1 GPIO and UART2 MMC/SD1 GPIO UART2
CLKOUT GPIO CLKOUT GPIO none
I2C GPIO I2C GPIO none
UART1 GPIO UART1 GPIO none
SPI1 GPIO SPI1 GPIO none
SPI0 GPIO SPI0 GPIO none
3.9.1 Hardware Controlled Pin Multiplexing
Use the Asynchronous EMIF configuration pins (AECFG[3:0]) for hardware pin mux control. AECFG[3:0]
control the partitioning of the AEMIF addresses and GPIOs at reset, which allows you to properly
configure the number of AEMIF address pins required by the boot device while unused addresses pins are
available as GPIOs. These settings may be changed by software after reset by programming the PinMux2
register The PinMux2 register is in the System Control Module. As shown in Table 3-13, the number of
address bits enabled on the AEMIF is selectable from 0 to 16. Pins that are not assigned to another
peripheral and not enabled as address signals become GPIOs (except EM_A[2:1]). The enabled address
signals are always contiguous from EM_BA[1] upwards; bits cannot be skipped. The exception to this are
EM_A[2:1]. These signals (can be used to) represent the ALE and CLE signals for the NAND Flash mode
of the AEMIF and are always enabled. Note that EM_A[0] does not represent the lowest AEMIF address
bit. DM335 supports only 16-bit and 8-bit data widths for the AEMIF. In 16-bit mode, EM_BA[1] represents
the LS address bit (the half-word address) and EM_BA[0] represents the MS address bit (A[14]). In 8-bit
mode, EM_BA[1:0] represent the 2 LS address bits. Note that additional selections are available by
programming the PinMux2 register in software after boot. Note that AECFG selection of ‘0010’ selects
OneNAND interface. The AEMIF needs to operate in the half-rate mode (full_rate = 0) to meet frequency
requirements. Software should not change the PINMUX2 register setting to affect the AEMIF rate
operation. A soft reset of the AEMIF should be performed any time a rate change is made.
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Table 3-13. AECFG (Async EMIF Configuration) Pin Mux Coding
1101(NAND) 1100 1010 1000 (8-bit SRAM) 0010 (16-bit SRAM, 0000
OneNAND)
GPIO[54] GPIO[54] EM_A[14] EM_BA[0] EM_A[14] EM_BA[0]
GPIO[55] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1]
GPIO[56] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0]
EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1]
EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2]
GPIO[57] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[3]
GPIO[58] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[4]
GPIO[59] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[5]
GPIO[60] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[6]
GPIO[61] EM_A[7] EM_A[7] EM_A[7] EM_A[7] EM_A[7]
GPIO[62] EM_A[8] EM_A[8] EM_A[8] EM_A[8] EM_A[8]
GPIO[63] EM_A[9] EM_A[9] EM_A[9] EM_A[9] EM_A[9]
GPIO[64] EM_A[10] EM_A[10] EM_A[10] EM_A[10] EM_A[10]
GPIO[65] EM_A[11] EM_A[11] EM_A[11] EM_A[11] EM_A[11]
GPIO[66] EM_A[12] EM_A[12] EM_A[12] EM_A[12] EM_A[12]
GPIO[67] EM_A[13] EM_A[13] EM_A[13] EM_A[13] EM_A[13]
GPIO[46] GPIO[46] GPIO[46] GPIO[46] EM_D[8] EM_D[8]
GPIO[47] GPIO[47] GPIO[47] GPIO[47] EM_D[9] EM_D[9]
GPIO[48] GPIO[48] GPIO[48] GPIO[48] EM_D[10] EM_D[10]
GPIO[49] GPIO[49] GPIO[49] GPIO[49] EM_D[11] EM_D[11]
GPIO[50] GPIO[50] GPIO[50] GPIO[50] EM_D[12] EM_D[12]
GPIO[51] GPIO[51] GPIO[51] GPIO[51] EM_D[13] EM_D[13]
GPIO[52] GPIO[52] GPIO[52] GPIO[52] EM_D[14] EM_D[14]
GPIO[53] GPIO[53] GPIO[53] GPIO[53] EM_D[15] EM_D[15]
3.9.2 Software Controlled Pin Multiplexing
All pin multiplexing options are configurable by software via pin mux registers that reside in the System
Control Module. The PinMux0 Register controls the Video In muxing, PinMux1 register controls Video Out
signals, PinMux2 register controls AEMIF signals, PinMux3 registers control the multiplexing of the GIO
signals, the PinMux4 register controls the SPI and MMC/SD0 signals. Refer to the TMS320DM335 Digital
Media System-on-Chip (DMSoC) ARM Subsystem Reference Guide (literature number SPRUFX7) for
complete descriptions of the pin mux registers.
3.10 Device Reset
There are five types of reset in DM335. The types of reset differ by how they are initiated and/or by their
effect on the chip. Each type is briefly described in Table 3-14. They are further described in the
TMS320DM335 Digital Media System-on-Chip (DMSoC) ARM Subsystem Reference Guide (literature
number SPRUFX7).
Table 3-14. Reset Types
Type Initiator Effect
POR (Power-On-Reset) RESET pin low and TRST low Total reset of the chip (cold reset). Resets all modules
including memory and emulation.
Warm Reset RESET pin low and TRST high (initiated by ARM Resets all modules including memory, except ARM
emulator). emulation.
Max Reset ARM emulator or Watchdog Timer (WDT). Same effect as warm reset.
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Table 3-14. Reset Types (continued)
Type Initiator Effect
System Reset ARM emulator Resets all modules except memory and ARM
emulation. It is a soft reset that maintains memory
contents and does not affect or reset clocks or power
states.
Module Reset ARM software Resets a specific module. Allows the ARM to
independently reset any module. Module reset is
intended as a debug tool not as a tool to use in
production.
3.11 Default Device Configurations
After POR, warm reset, and max reset, the chip is in its default configuration. This section highlights the
default configurations associated with PLLs, clocks, ARM boot mode, and AEMIF.
NOTE
Default configuration is the configuration immediately after POR, warm reset, and max reset
and just before the boot process begins. The boot ROM updates the configuration. See
Section 3.12 for more information on the boot process.
3.11.1 Device Configuration Pins
The device configuration pins are described in Table 3-15. The device configuration pins are latched at
reset and allow you to configure all of the following options at reset:
• ARM Boot Mode
• Asynchronous EMIF pin configuration
These pins are described further in the following sections.
NOTE
The device configuration pins are multiplexed with AEMIF pins. After the device configuration
pins are sampled at reset, they automatically change to function as AEMIF pins. Pin
multiplexing is described in Section 3.8.
Table 3-15. Device Configuration
Default Setting (by
internal
Device Sampled pull-up/
Configuration Input Function Pin pull-down) Device Configuration Affected
BTSEL[1:0] Selects ARM boot mode EM_A[13:12] 00 If any ROM boot mode is selected, GIO61
00 = Boot from ROM (NAND (NAND) is used to indicated boot status.
with SPI EEPROM boot If NAND boot is selected, CE0 is used for
option) NAND and SPI0 is used for SPI boot
01 = Boot from AEMIF option. Use AECFG[3:0] to configure
10 = Boot from ROM AEMIF pins for NAND.
(MMC/SD) If AEMIF boot is selected, CE0 is used for
11 = Boot from ROM (UART) AEMIF device (OneNAND, ROM). Use
AECFG[3:0] to configure AEMIF pins for
NAND.
If MMC/SD boot is selected, MMC/SD0 is
used.
AECFG[3:0] Selects AEMIF pin EM_A[11:8] 1101 Selects the AEMIF pin configuration. Refer
configuration (NAND) to pin-muxing information in Section 3.9.1.
Note that AECFG[3:0] affects both AEMIF
(BTSEL[1:0]=01) and NAND
(BTSEL[1:0]=00) boot modes.
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3.11.2 PLL Configuration
After POR, warm reset, and max reset, the PLLs and clocks are set to their default configurations. The
PLLs are in bypass mode and disabled by default. This means that the input reference clock at MXI1
(typically 24 MHz) drives the chip after reset. For more information on device clocking, see Section 3.5
and Section 3.6. The default state of the PLLs is reflected in the default state of the register bits in the
PLLC registers. Refer to the TMS320DM335 Digital Media System-on-Chip (DMSoC) ARM Subsystem
Reference Guide (literature number SPRUFX7) for PLLC register descriptions.
3.11.3 Power Domain and Module State Configuration
Only a subset of modules are enabled after reset by default. Table 3-16 shows which modules are
enabled after reset. Table 3-16 as shows that the following modules are enabled depending on the
sampled state of the device configuration pins: EDMA (CC and TC0), AEMIF, MMC/SD0, UART0, and
Timer0. For example, UART0 is enabled after reset when the device configuration pins (BTSEL[1:0] = 11 -
Enable UART) select UART boot mode. For more information on module configuration refer to .
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Table 3-16. Module Configuration
Default States
Module Module Name Power Domain Power Domain State Module State
Number
0 VPSS Master AlwaysOn ON SyncRst
1 VPSS Slave AlwaysOn ON SyncRst
2 EDMA (CC) AlwaysOn ON BTSEL[1:0] = 00 – Enable (NAND, SPI)
BTSEL[1:0] = 01 – Enable (OneNAND)
3 EDMA (TC0) AlwaysOn ON BTSEL[1:0] = 10 – SyncRst (MMC/SD)
BTSEL[1:0] = 11 – Enable (UART)
4 EDMA (TC1) AlwaysOn ON
5 Timer3 AlwaysOn ON SyncRst
6 SPI1 AlwaysOn ON SyncRst
7 MMC/SD1 AlwaysOn ON SyncRst
8 ASP1 AlwaysOn ON SyncRst
9 USB AlwaysOn ON SyncRst
10 PWM3 AlwaysOn ON SyncRst
11 SPI2 AlwaysOn ON SyncRst
12 RTO AlwaysOn ON SyncRst
13 DDR EMIF AlwaysOn ON SyncRst
14 AEMIF AlwaysOn ON BTSEL[1:0] = 00 – Enable (NAND, SPI)
BTSEL[1:0] = 01 – Enable (OneNAND)
BTSEL[1:0] = 10 – SyncRst (MMC/SD)
BTSEL[1:0] = 11 – Enable (UART)
15 MMC/SD0 AlwaysOn ON BTSEL[1:0] = 00 – SyncRst (NAND, SPI)
BTSEL[1:0] = 01 – SyncRst (OneNAND)
BTSEL[1:0] = 10 – Enable (MMC/SD)
BTSEL[1:0] = 11 – SyncRst (UART)
16 Reserved Reserved Reserved Reserved
17 ASP AlwaysOn ON SyncRst
18 I2C AlwaysOn ON SyncRst
19 UART0 AlwaysOn ON BTSEL[1:0] = 00 – SyncRst (NAND, SPI)
BTSEL[1:0] = 01 – SyncRst (OneNAND)
BTSEL[1:0] = 10 – SyncRst (MMC/SD)
BTSEL[1:0] = 11 – Enable (UART)
20 UART1 AlwaysOn ON SyncRst
21 UART2 AlwaysOn ON SyncRst
22 SPI0 AlwaysOn ON BTSEL[1:0] = 00 – Enable (NAND, SPI)
BTSEL[1:0] = 01 – SyncRst (OneNAND)
BTSEL[1:0] = 10 – Enable (MMC/SD)
BTSEL[1:0] = 11 – Enable (UART)
23 PWM0 AlwaysOn ON SyncRst
24 PWM1 AlwaysOn ON SyncRst
25 PWM2 AlwaysOn ON SyncRst
26 GPIO AlwaysOn ON SyncRst
27 TIMER0 AlwaysOn ON BTSEL[1:0] = 00 – Enable (NAND, SPI)
BTSEL[1:0] = 01 – Enable (OneNAND)
BTSEL[1:0] = 10 – Enable (MMC/SD)
BTSEL[1:0] = 11 – Enable (UART)
28 TIMER1 AlwaysOn ON SyncRst
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Table 3-16. Module Configuration (continued)
Default States
29 TIMER2 AlwaysOn ON Enable
30 System Module AlwaysOn ON Enable
31 ARM AlwaysOn ON Enable
32 BUS AlwaysOn ON Enable
33 BUS AlwaysOn ON Enable
34 BUS AlwaysOn ON Enable
35 BUS AlwaysOn ON Enable
36 BUS AlwaysOn ON Enable
37 BUS AlwaysOn ON Enable
38 BUS AlwaysOn ON Enable
39 Reserved Reserved Reserved Reserved
40 VPSS DAC Always On ON SyncRst
3.11.4 ARM Boot Mode Configuration
The input pins BTSEL[1:0] determine whether the ARM will boot from its ROM or from the Asynchronous
EMIF (AEMIF). When ROM boot is selected (BTSEL[1:0] = 00, 10, or 11), a jump to the start of internal
ROM (address 0x0000: 8000) is forced into the first fetched instruction word. The embedded ROM boot
loader code (RBL) then performs certain configuration steps, reads the BOOTCFG register to determine
the desired boot method, and branches to the appropriate boot routine (i.e., a NAND/SPI, MMC/SD, or
UART loader routine).
If AEMIF boot is selected (BTSEL[1:0] = 01), a jump to the start of AEMIF (address 0x0200: 0000) is
forced into the first fetched instruction word. The ARM then continues executing from external
asynchronous memory using the default AEMIF timings until modified by software.
NOTE
For AEMIF boot, the OneNAND must be connected to the first AEMIF chip select space
(EM_CE0). Also, the AEMIF does not support direct execution from NAND Flash.
Boot modes are further described in Section 3.12.
3.11.5 AEMIF Configuration
3.11.5.1 AEMIF Pin Configuration
The input pins AECFG[3:0] determine the AEMIF configuration immediately after reset. Use AECFG[3:0]
to properly configure the pins of the AEMIF. Refer to the section on pin multiplexing in Section 3.9.
Also, see the TMS320DM335 Digital Media System-on-Chip (DMSoC) Asynchronous External Memory
Interface (EMIF) Reference Guide (SPRUFZ1) for more information on the AEMIF.
3.11.5.2 AEMIF Timing Configuration
When AEMIF is enabled, the wait state registers are reset to the slowest possible configuration, which is
88 cycles per access (16 cycles of setup, 64 cycles of strobe, and 8 cycles of hold). Thus, with a 24 MHz
clock at MXI1, the AEMIF is configured to run at 6 MHz/88 which equals approximately 68 kHz by default.
See the TMS320DM335 Digital Media System-on-Chip (DMSoC) Asynchronous External Memory
Interface (EMIF) Reference Guide (SPRUFZ1) for more information on the AEMIF.
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3.12 Device Boot Modes
The DM335 ARM can boot from either Async EMIF (AEMIF/OneNand) or from ARM ROM, as determined
by the setting of the device configuration pins BTSEL[1:0]. The BTSEL[1:0] pins can define the ROM boot
mode further as well.
The boot selection pins (BTSEL[1:0]) determine the ARM boot process. After reset (POR, warm reset, or
max reset), ARM program execution begins in ARM ROM at 0x0000: 8000, except when BTSEL[1:0] = 01,
indicating AEMIF (AEMIF/OneNand) boot. See Section 3.11.1 for information on the boot selection pins.
3.12.1 Boot Modes Overview
DM335’s ARM ROM boot loader (RBL) executes when the BTSEL[1:0] pins indicate a condition other than
the normal ARM EMIF boot.
• If BTSEL[1:0] = 01 - Asynchronous EMIF (AEMIF) boot. This mode is handled by hardware control and
does not involve the ROM. In the case of OneNAND, the user is responsible for putting any necessary
boot code in the OneNAND's boot page. This code shall configure the AEMIF module for the
OneNAND device. After the AEMIF module is configured, booting will continue immediately after the
OneNAND’s boot page with the AEMIF module managing pages thereafter.
• The RBL supports 3 distinct boot modes:
– BTSEL[1:0] = 00 - ARM NAND/SPI Boot
– BTSEL[1:0] = 10 - ARM MMC/SD Boot
– BTSEL[1:0] = 11 - ARM UART Boot
• In NAND mode if SPI boot fails, then NAND mode is tried. If NAND boot fails, then MMC/SD mode is
tried.
• If MMC/SD boot fails, then MMC/SD boot is tried again.
• If UART boot fails, then UART boot is tried again.
• RBL uses GIO61 to indicate boot status (can use to blink LED):
– After reset, GIO61 is initially driven low (e.g LED off)
– If NAND boot fails, then GIO61 shall toggle at 4Hz while MMC/SD boot is tried.
– If MMC/SD boot fails, then GIO61 shall toggle at 4Hz while MMC/SD boot is retried.
– If UART boot fails, then GIO61 shall toggle at 2Hz while UART boot is retried.
– When boot is successful, just before program control is given to UBL, GIO61 is driven high (e.g.
LED on).
– DM335 Timer0 shall be used to accurately toggle GIO61 at 4Hz and 2Hz.
• ARM ROM Boot - SPI boot in NAND Mode
– No support for a full firmware boot. Instead, copies a second stage User Boot Loader (UBL) from
SPI to ARM Internal RAM (AIM) and transfers control to the user software.
– Support for 16 and 24 bit SPI EEPROMs
– Support for up to 30KB UBL (32KB - ~2KB for RBL stack)
– RBL will copy UBL to ARM Internal RAM (AIM) via SPI interface from a SPI peripheral like SPI
EEPROM. RBL will then transfer control to the UBL.
• ARM ROM Boot - NAND Mode (See Section 3.12.2 for a full explanation of the differences between
Standard Mode and Compatibility Mode.):
– No support for a full firmware boot. Instead, copies a second stage User Boot Loader (UBL) from
NAND flash to ARM internal RAM (AIM) and transfers control to the user-defined UBL
– Support for NAND with page sizes up to 8192 bytes in Standard Mode and 2048 bytes in
Compatibility Mode
Note: At the time of documentation for this device, 8192-byte devices were not available for testing.
The code does contain support for these devices; however, it has not yet been tested.
– Support for magic number error detection and retry (up to 24 times) when loading UBL
– Support for up to 30KB UBL (32KB IRAM - ~2KB for RBL stack)
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– Optional, user-selectable, support for use of DMA and I-cache during RBL execution (i.e.,while
loading UBL)
– Supports booting from 8-bit NAND devices (16-bit NAND devices are not supported)
– Uses/Requires 4-bit HW ECC (NAND devices with ECC requirements ≤4 bits per 512 bytes are
supported)
– Supports NAND flash that requires chip select to stay low during the tR read time
Notes:
– See Section 3.12.2 for a full explanation of the differences between Standard Mode and
Compatibility Mode.
– The GIO000 pin must be held high during NAND boot for the boot process to fuction properly.
• ARM ROM Boot - MMC/SD Mode
– No support for a full firmware boot. Instead, copies a second stage User Boot Loader (UBL) from
MMC/SD to ARM Internal RAM (AIM) and transfers control to the user software.
– Support for MMC/SD Native protocol (MMC/SD SPI protocol is not supported)
– Support for descriptor error detection and retry (up to 24 times) when loading UBL
– Support for up to 30KB UBL (32KB - ~2KB for RBL stack)
• ARM ROM Boot - UART mode
– No support for a full firmware boot. Instead, loads a second stage User Boot Loader (UBL) via
UART to ARM internal RAM (AIM) and transfers control to the user software.
– Support for up to 30KB UBL (32KB - ~2KB for RBL stack)
The general boot sequence is shown in Figure 3-6. For more information, refer to the TMS320DM335
Digital Media System-on-Chip (DMSoC) ARM Subsystem Reference Guide (literature number SPRUFX7).
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Boot
mode
?
Boot
mode
?
Internal ROM
Invoke loaded
Program
Invoke
OneNAND
Yes
Boot from
UART
Boot OK ? No
Boot from
NAND flash
Boot OK ? No
Yes Boot from
MMC/SD
Boot OK ?
Yes
No
Reset
Boot from
SPI flash
Boot OK ?
No
Yes
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Figure 3-6. Boot Mode Functional Block Diagram
3.12.2 RBL NAND Boot Process
The RBL NAND boot process is described as follows:
• Upon NAND boot, if a SPI EEPROM is present, RBL reads first 32 bytes and look for magic pattern at
offset 0x8. This magic number indicates if this is a SPI boot or beginning of NAND parameters.
• If SPI boot, then NAND boot is bypassed.
• Otherwise NAND boot is continued. If NAND parameters are found in the SPI EEPROM (as indicated
by magic number), these parameters are used.
• Else the following steps are used to determine NAND parameters:
– If the device is ONFI, read the parameters page. Else command is sent to the NAND device
requesting four bytes (called the NAND READ_ID) which contain the manufacturer, device and 4th
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ID.
– The RBL contains an internal table with a list of known NAND devices. Table 3-23 shows the
devices contained in the tables.
– If the device ID is not found in the table, then the RBL use the fourth byte of the NAND to decode
this to obtain the necessary parameters.
• Once a device ID is identified, the first 24 blocks of the NAND are read sequentially starting with page
0 with an offset of 512 bytes. The purpose of the read is to locate a magic number which will identify
the revision of the silicon. Table 3-18 contains magic numbers and their functions. In addition to the
modes listed in Table 3-18, the magic number will determine whether the device runs in Standard or
Compatibility mode. Magic numbers of the form 0xA1ACEDxx place the device in Compatibility mode,
while magic numbers of the form 0xA1BCEDxx place the device in Standard mode. This should be
kept in mind when reviewing the values in Table 3-18.
• If a Compatibility mode magic number is read, then the device enters compatibility mode. In
compatibility mode, NAND layout is identical to that used in previous revisions of the silicon as shown
in Table 3-19. Only 512-byte small blocks and 2048-byte big blocks are supported.
• If a Standard mode magic number is read, the NAND layout is as shown in Table 3-20: 512-bytes
small block and 2048- and 4096- big block devices are supported. 8192-block devices are also
supported. Note: At the time of production of this document revision, only 4096-block devices were
available for testing.
• Once a magic number is identified, the User Boot Loader (UBL) is loaded from the NAND, stored to
internal RAM, and executed.
Table 3-17. NAND Devices in NAND Device ID Table
DEVICE ID PAGES PER BLOCK BYTES PER PAGE BLOCK SHIFT VALUE NUMBER OF ADDRESS
FOR ADDRESS CYCLES
0xE3 16 512+16 12 3
0xE5 16 512+16 12 3
0xE6 16 512+16 12 3
0x39(1) 16 512+16 13 3
0x6B 16 512+16 13 3
0x73 32 512+16 13 3
0x33 32 512+16 13 3
0x75 32 512+16 13 3
0x35 32 512+16 13 3
0x43 32 512+16 13 4
0x45 32 512+16 13 4
0x53 32 512+16 13 4
0x55 32 512+16 13 4
0x76 32 512+16 13 4
0x36 32 512+16 13 4
0x79 32 512+16 13 4
0x71 32 512+16 13 4
0x46 32 512+16 13 4
0x56 32 512+16 13 4
0x74 32 512+16 13 4
0xF1 64 2048+64 22 4
0xA1 64 2048+64 22 4
0xAA 64 2048+64 22 5
0xDA 64 2048+64 22 5
(1) Present only on silicon revision 1.1.
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Table 3-17. NAND Devices in NAND Device ID Table (continued)
0xAC 64 2048+64 22 5
0xDC 64 2048+64 22 5
0xB1 64 2048+64 22 5
0xC1 64 2048+64 22 5
Table 3-18. UBL Signature and Special Modes for NAND Boot Mode
MODE VALUE(1) DESCRIPTION
UBL_MAGIC_SAFE 0xA1AC ED00 Safe boot mode
UBL_MAGIC_DMA 0xA1AC ED11 DMA boot mode
UBL_MAGIC_IC 0xA1AC ED22 I Cache boot mode
UBL_MAGIC_FAST 0xA1AC ED33 Fast EMIF boot mode
UBL_MAGIC_DMA_IC 0xA1AC ED44 DMA + I Cache boot mode
UBL_MAGIC_DMA_IC_FAST 0xA1AC ED55 DMA + I Cache + Fast EMIF boot mode
UBL_MAGIC_SPI_PARAMS 0xA1AC EDAA NAND parameters from SPI EEPROM
(1) The values listed only apply when operating in compatibility mode. These values follow the form 0xA1BCEDxx when operating in
standard mode.
Example: UBL_MAGIC_SAFE VALUE = 0xA1ACED00; Safe boot mode will configure the device to run in safe boot mode and in
compatibility mode. However, when using standard mode, the value should be 0xA1BCD00.
Table 3-19. NAND Layout (Compatibility Mode)
512 Byte Page Size 2048 Byte Page Size
512 bytes Data 512 bytes Data
16 bytes ECC Data 16 bytes ECC Data
512 bytes Data
16 bytes ECC Data
512 bytes Data
16 bytes ECC Data
512 bytes Data
16 bytes ECC Data
Table 3-20. NAND Layout (Standard Mode)
512 Byte Page Size 2048 Byte Page Size 4096 Byte Page Size
512 bytes Data 2048 bytes Data 4096 bytes Data
16 bytes ECC Data 64 bytes ECC Data 128 bytes ECC Data
3.13 Power Management
The DM335 is designed for minimal power consumption. There are two components to power
consumption: active power and leakage power. Active power is the power consumed to perform work and
scales with clock frequency and the amount of computations being performed. Active power can be
reduced by controlling the clocks in such a way as to either operate at a clock setting just high enough to
complete the required operation in the required timeline or to run at a clock setting until the work is
complete and then drastically cut the clocks (e.g. to PLL Bypass mode) until additional work must be
performed. Leakage power is due to static current leakage and occurs regardless of the clock rate.
Leakage, or standby power, is unavoidable while power is applied and scales roughly with the operating
junction temperatures. Leakage power can only be avoided by removing power completely from a device
or subsystem. The DM335 includes several power management features which are briefly described in
Table 3-17. Refer to the TMS320DM335 Digital Media System-on-Chip (DMSoC) ARM Subsystem
Reference Guide (literature number SPRUFX7) for more information on power management.
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Table 3-21. Power Management Features
Power Management Features Description
Clock Management
Module clock disable Module clocks can be disabled to reduce switching power
Module clock frequency scaling Module clock frequency can be scaled to reduce switching power
PLL power-down The PLLs can be powered-down when not in use to reduce
switching power
ARM Sleep Mode
ARM Wait-for-Interrupt sleep mode Disable ARM clock to reduce active power
System Sleep Modes
Deep Sleep mode Stop all device clocks and power down internal oscillators to reduce
active power to a minimum. Registers and memory are preserved.
I/O Management
USB Phy power-down The USB Phy can be powered-down to reduce USB I/O power
DAC power-down The DAC's can be powered-down to reduce DAC power
DDR self-refresh and power down The DDR / mDDR device can be put into self-refresh and power
down states
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3.14 64-Bit Crossbar Architecture
The DM335 uses a 64-bit crossbar architecture to control access between device processors, subsystems
and peripherals. It includes an EDMA Controller consisting of a DMA Transfer Controller (TC) and a DMA
Channel Controller (CC). The TC provides two DMA channels for transfer between slave peripherals. The
CC provides a user and event interface to the EDMA system. It includes up to 64 event channels to which
all system synchronization events can be mapped and 8 auto submit “quick” channels (QDMA). In most
ways, these channels are identical. A channel refers to a specific ‘event’ that can cause a transfer to be
submitted to the TC as a Transfer Request.
3.14.1 Crossbar Connections
There are five transfer masters (TCs have separate read and write connections) connected to the
crossbar; ARM, the Video Processing Sub-system (VPSS), the master peripherals (USB), and two EDMA
transfer controllers. These can be connected to four separate slave ports; ARM, the DDR EMIF, and CFG
bus peripherals. Not all masters may connect to all slaves. Connection paths are indicated by √at
intersection points shown in Table 3-22
Table 3-22. Crossbar Connection Matrix
Slave Module
DMA Master ARM Internal Config Bus Registers and Memory DDR EMIF Memory
Memory
ARM √ √ √
VPSS √
DMA Master Peripherals (USB) √ √ √
EDMA3TC0 √ √ √
EDMA3TC1 √ √ √
3.14.2 EDMA Controller
The EDMA controller handles all data transfers between memories and the device slave peripherals on
the DM335 device. These are summarized as follows:
• Transfer to/from on-chip memories
– ARM program/data RAM
• Transfer to/from external storage
– DDR2 / mDDR SDRAM
– Asynchronous EMIF
– OneNAND flash
– NAND flash
– Smart Media, SD, MMC, xD media storage
• Transfer to/from peripherals
– ASP
– SPI
– I2C
– PWM
– RTO
– GPIO
– Timer/WDT
– UART
– MMC/SD
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The EDMA Controller consists of two major blocks: the Transfer Controller (TC) and the Channel
Controller (CC). The CC is a highly flexible Channel Controller that serves as the user interface and event
interface for the EDMA system. The CC supports 64-event channels and 8 QDMA channels. The CC
consists of a scalable Parameter RAM (PaRAM) that supports flexible ping-pong, circular buffering,
channel-chaining, auto-reloading, and memory protection.
The EDMA Channel Controller has the following features:
• Fully orthogonal transfer description
– Three transfer dimensions
– A-synchronized transfers: one dimension serviced per event
– AB- synchronized transfers: two dimensions serviced per event
– Independent indexes on source and destination
– Chaining feature allows 3-D transfer based on single event
• Flexible transfer definition
– Increment and constant addressing modes
– Linking mechanism allows automatic PaRAM set update
– Chaining allows multiple transfers to execute with one event
• Interrupt generation for:
– DMA completion
– Error conditions
• Debug visibility
– Queue watermarking/threshold
– Error and status recording to facilitate debug
• 64 DMA channels
– Event synchronization
– Manual synchronization (CPU(s) write to event set register)
– Chain synchronization (completion of one transfer chains to next)
• 8 QDMA channels
– QDMA channels are triggered automatically upon writing to a PaRAM set entry
– Support for programmable QDMA channel to PaRAM mapping
• 128 PaRAM sets
– Each PaRAM set can be used for a DMA channel, QDMA channel, or link set (remaining)
• Two transfer controllers/event queues. The system-level priority of these queues is user programmable
• 16 event entries per event queue
• External events (for example, ASP TX Evt and RX Evt)
The EDMA Transfer Controller has the following features:
• Two transfer controllers
• 64-bit wide read and write ports per channel
• Up to four in-flight transfer requests (TR)
• Programmable priority level
• Supports two dimensional transfers with independent indexes on source and destination (EDMA3CC
manages the 3rd dimension)
• Support for increment and constant addressing modes
• Interrupt and error support
Parameter RAM: Each EDMA is specified by an eight word (32-byte) parameter table contained in
Parameter RAM (PaRAM) within the CC. DM335 provides 128 PaRAM entries, one for each of the 64
DMA channels and for 64 QDMA / Linked DMA entries.
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DMA Channels: Can be triggered by: " External events (for example, ASP TX Evt and RX Evt), " Software
writing a '1' to the given bit location, or channel, of the Event Set register, or, " Chaining to other DMAs.
QDMA: The Quick DMA (QDMA) function is contained within the CC. DM335 implements 8 QDMA
channels. Each QDMA channel has a selectable PaRAM entry used to specify the transfer. A QDMA
transfer is submitted immediately upon writing of the "trigger" parameter (as opposed to the occurrence of
an event as with EDMA). The QDMA parameter RAM may be written by any Config bus master through
the Config Bus and by DMAs through the Config Bus bridge.
QDMA Channels: Triggered by a configuration bus write to a designated 'QDMA trigger word'. QDMAs
allow a minimum number of linear writes (optimized for GEM IDMA feature) to be issued to the CC to
force a series of transfers to take place.
3.14.2.1 EDMA Channel Synchronization Events
The EDMA supports up to 64 EDMA channels which service peripheral devices and external memory.
Table 3-23 lists the source of EDMA synchronization events associated with each of the programmable
EDMA channels. For the DM335 device, the association of an event to a channel is fixed; each of the
EDMA channels has one specific event associated with it. These specific events are captured in the
EDMA event registers (ER, ERH) even if the events are disabled by the EDMA event enable registers
(EER, EERH). For more detailed information on the EDMA module and how EDMA events are enabled,
captured, processed, linked, chained, and cleared, etc., see the TMS320DM335 Digital Media
System-on-Chip (DMSoC) Enhanced Direct Memory Access (EDMA) Controller Reference Guide
(literature number SPRUFZ20).
Table 3-23. DM335 EDMA Channel Synchronization Events(1) (2)
EDMA EVENT NAME EVENT DESCRIPTION
CHANNEL
0 TIMER3: TINT6 Timer 3 Interrupt (TINT6) Event
1 TIMER3 TINT7 Timer 3 Interrupt (TINT7) Event
2 ASP0: XEVT ASP0 Transmit Event
3 ASP0: REVT ASP0 Receive Event
4 VPSS: EVT1 VPSS Event 1
5 VPSS: EVT2 VPSS Event 2
6 VPSS: EVT3 VPSS Event 3
7 VPSS: EVT4 VPSS Event 4
ASP1: XEVT or TIMER2:
8 ASP1 Transmit Event or Timer 2 interrupt (TINT4) Event
TINT4
ASP1: REVT or TIMER2:
9 ASP1 Receive Event or Timer 2 interrupt (TINT5) Event
TINT5
10 SPI2: SPI2XEVT SPI2 Transmit Event
11 SPI2: SPI2REVT SPI2 Receive Event
12 Reserved
13 Reserved
14 SPI1: SPI1XEVT SPI1 Transmit Event
15 SPI1: SPI1REVT SPI1 Receive Event
16 SPI0: SPI0XEVT SP0I Transmit Event
17 SPI0: SPI0REVT SPI0 Receive Event
18 UART0: URXEVT0 UART 0 Receive Event
(1) In addition to the events shown in this table, each of the 64 channels can also be synchronized with the transfer completion or
intermediate transfer completion events. For more detailed information on EDMA event-transfer chaining, see the TMS320DM335 Digital
Media System-on-Chip (DMSoC) Enhanced Direct Memory Access (EDMA) Controller Reference Guide (literature number SPRUFZ20).
(2) The total number of EDMA events in DM335 exceeds 64, which is the maximum value of the EDMA module. Therefore, several events
are multiplexed and you must use the register EDMA_EVTMUX in the System Control Module to select the event source for multiplexed
events. Refer to the TMS320DM335 Digital Media System-on-Chip (DMSoC) ARM Subsystem Reference Guide (literature number
SPRUFX7) for more information on the System Control Module register EDMA_EVTMUX.
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Table 3-23. DM335 EDMA Channel Synchronization Events (1) (2) (continued)
EDMA EVENT NAME EVENT DESCRIPTION
CHANNEL
19 UART0: UTXEVT0 UART 0 Transmit Event
20 UART1: URXEVT1 UART 1 Receive Event
21 UART1: UTXEVT1 UART 1 Transmit Event
22 UART2: URXEVT2 UART 2 Receive Event
23 UART2: UTXEVT2 UART 2 Transmit Event
24 Reserved
25 GPIO: GPINT9 GPIO 9 Interrupt Event
26 MMC0RXEVT MMC/SD0 Receive Event
27 MMC0TXEVT MMC/SD0 Transmit Event
28 I2CREVT I2C Receive Event
29 I2CXEVT I2C Transmit Event
30 MMC1RXEVT MMC/SD1 Receive Event
31 MMC1TXEVT MMC/SD1 Transmit Event
32 GPINT0 GPIO 0 Interrupt Event
33 GPINT1 GPIO 1 Interrupt Event
34 GPINT2 GPIO 2 Interrupt Event
35 GPINT3 GPIO 3 Interrupt Event
36 GPINT4 GPIO 4 Interrupt Event
37 GPINT5 GPIO 5 Interrupt Event
38 GPINT6 GPIO 6 Interrupt Event
39 GPINT7 GPIO 7 Interrupt Event
40 GPBNKINT0 GPIO Bank 0 Interrupt Event
41 GPBNKINT1 GPIO Bank 1 Interrupt Event
42 GPBNKINT2 GPIO Bank 2 Interrupt Event
43 GPBNKINT3 GPIO Bank 3 Interrupt Event
44 GPBNKINT4 GPIO Bank 4 Interrupt Event
45 GPBNKINT5 GPIO Bank 5 Interrupt Event
46 GPBNKINT6 GPIO Bank 6 Interrupt Event
47 GPINT8 GPIO 8 Interrupt Event
48 TIMER0: TINT0 Timer 0 Interrupt Event
49 TIMER0: TINT1 Timer 1 Interrupt Event
50 TIMER1: TINT2 Timer 2 Interrupt Event
51 TIMER1: TINT3 Timer 3 Interrupt Event
52 PWM0 PWM 0 Event
53 PWM1 PWM 1 Event
54 PWM2 PWM 2 Event
55 PWM3 PWM 3 Event
56 - 63 Reserved
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4 Device Operating Conditions
4.1 Absolute Maximum Ratings Over Operating Case Temperature Range
(Unless Otherwise Noted) (1) (2)
All 1.3 V supplies -0.5 V to 1.7 V
All digital 1.8 V supplies -0.5 V to 2.5 V
Supply voltage ranges All analog 1.8 V supplies -0.5 V to 1.89 V
All 3.3 V supplies -0.5 V to 4.4 V
All 1.8 V I/Os -0.5 V to 2.3 V
Input voltage ranges All 3.3 V I/Os -0.5 V to 3.8 V
VBUS 0.0 V to 5.5 V
Clamp current for input or output(3) Iclamp -20 mA to 20 mA
Commercial Tc0°C to 85 °C
Operating case temperature ranges Extended Temperature [A135/A216 devices] Tc-40°C to 100°C
Storage temperature ranges Tstg -65°C to 150 °C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS.
(3) Clamp current flows from an input or output pad to a supply rail through a clamp circuit or an intrinsic diode. Positive current results from
an applied input or output voltage that is more than 0.5 V higher (more positive) than the supply voltage,
VDD/VDDA_PLL1/2/VDD_USB/VDD_DDR for dual-supply macros. Negative current results from an applied voltage that is more than 0.5 V less
(more negative) than the VSS voltage..
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4.2 Recommended Operating Conditions
NAME DESCRIPTION MIN NOM MAX UNIT
CVDD Supply voltage, Core 1.235 1.3 1.365 V
VDDA_PLL1 Supply voltage, PLL1 1.235 1.3 1.365 V
VDDA_PLL2 Supply voltage, PLL2 1.235 1.3 1.365 V
VDDD13_USB Supply voltage, USB Digital 1.235 1.3 1.365 V
VDDA13_USB Supply voltage, USB Analog 1.235 1.3 1.365 V
VDDA33_USB Supply voltage, USB Analog 3.135 3.3 3.465 V
Supply Voltage VDDA33_USB_PLL Supply voltage, USB Common PLL 3.135 3.3 3.465 V
VDD_DDR Supply voltage, DDR2 / MDDR 1.71 1.8 1.89 V
VDDA33_DDRDLL Supply voltage, DDR DLL Analog 3.135 3.3 3.465 V
VDD_VIN Supply voltage, Digital video In 3.135 3.3 3.465 V
VDD_VOUT Supply voltage, Digital Video Out 3.135 3.3 3.465 V
VDDA18_DAC Supply voltage, DAC Analog 1.71 1.8 1.89 V
VDD Supply voltage, I/Os 3.135 3.3 3.465 V
VSS Supply ground, Core, USB Digital 0 0 0 V
VSSA_PLL1 Supply ground, PLL1 0 0 0 V
VSSA_PLL2 Supply ground, PLL2 0 0 0 V
VSS_USB Supply ground, USB 0 0 0 V
Supply Ground VSSA_DLL Supply ground, DLL 0 0 0 V
VSSA_DAC Supply ground, DAC Analog 0 0 0 V
VSS_MX1 MXI1 osc ground(1) 0 0 0 V
VSS_MX2 MXI2 osc ground(1) 0 0 0 V
Voltage Input High VIH High-level input voltage(2) 2 V
Voltage Input Low VIL Low-level input voltage(2) 0.8 V
VREF DAC reference voltage 450 mV
RBIAS DAC full-scale current adjust resistor 2550 Ω
DAC(3) RLOAD Output resistor 499 Ω
CBG Bypass capacitor 0.1 mF
Output resistor (ROUT), between TVOUT and VFB
ROUT 1070
pins Ω
RFB Feedback resistor, between VFB and IOUT pins. 1000
Video Buffer(3)
RBIAS DAC full-scale current adjust resistor 2550 Ω
CBG Bypass capacitor 0.1 mA
USB_VBUS USB external charge pump input 4.85 5 5.25 V
USB R1 USB reference resistor(4) 9.9 10 10.1 kΩ
Commercial 0 85 °C
Extended
Temperature TcOperating case temperature range [A135/A216 -40 100 °C
devices]
Transition time, 10% - 90%, All
Transition Time ttInputs (unless otherwise specified in 0.25P or 10(5) ns
the electrical data sections)
(1) Oscillator ground must be kept separate from other grounds and connected directly to the crystal load capacitor ground (see
Section 5.5.1 ).
(2) These I/O specifications apply to regular 3.3 V I/Os and do not apply to DDR2/mDDR, USB I/Os. DDR2/mDDR I/Os are 1.8 V I/Os and
adhere to JESD79-2A standard, USB I/Os adhere to USB2.0 spec.
(3) See Section 5.9.2.4 . Also, resistors should be E-96 spec line (3 digits with 1% accuracy).
(4) Connect USB_R1 to VSS_USB_REF via 10K ohm, 1% resistor placed as close to the device as possible.
(5) Whichever is smaller. P = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve
noise immunity on input signals.
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4.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and
Operating Case Temperature (Unless Otherwise Noted)
PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT
VOH High-level output voltage(2) VDD=MIN, IOH=MAX 2.4
Voltage V
Output VOL Low-level output voltage(2) VDD=MIN, IOL=MAX 0.6
Input current for I/O without
IIVI= VSS to VDD -1 1
internal pull-up/pull-down
Input current for I/O with
II(pullup) VI= VSS to VDD 40 190
internal pull-up(3) (4)
Input current for I/O with
II(pulldown) VI= VSS to VDD -190 -40
internal pull-down(3) (4)
Current Current sink of high-level output
IOH VOH = 2.4 V -4000 mA
Input/Output current
Current sink of low-level output
IOL VOL = 0.6 V 4000
current VO= VDD or VSS; internal pull ±20
disabled
IOZ I/O off-state output current VO= VDD or VSS; internal pull ±100
enabled
CIInput capacitance 4
Capacitance pF
COOutput capacitance 4
Resolution Resolution 10 Bits
RLOAD = 499 Ω, Video buffer
INL Integral non-linearity, best fit 1 LSB
disabled
DAC RLOAD = 499 Ω, Video buffer
DNL Differential non-linearity 0.5 LSB
disabled
Compliance Output compliance range IFS = 1.4 mA, RLOAD = 499 Ω0 0.700 V
Output high voltage (top of 75%
VOH(VIDBUF) 1.55
NTSC or PAL colorbar)(5)
Video Buffer V
Output low voltage (bottom of
VOL(VIDBUF) 0.470
sync tip)
(1) For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.
(2) These I/O specifications apply to regular 3.3 V I/Os and do not apply to DDR2/mDDR, USB I/Os. DDR2/mDDR I/Os are 1.8 V I/Os and
adhere to JESD79-2A standard, USB I/Os adhere to USB2.0 spec.
(3) This specification applies only to pins with an internal pullup (PU) or pulldown (PD). See Section 2.4 or Section 2.20 for pin descriptions.
(4) To pull up a signal to the opposite supply rail, a 1 kΩresistor is recommended.
(5) 100% color bars are not supported. 100% color bars require 1.2 V peak-to-peak. The video buffer only provides 1.0 V peak-to-peak.
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TransmissionLine
4.0pF 1.85pF
Z0=50 Ω
(seenote)
Tester PinElectronics Data SheetTimingReferencePoint
Output
Under
Test
42 Ω3.5nH
DevicePin
(seenote)
Vref
Vref =VIL MAX(orVOL MAX)
Vref =VIH MIN(orVOH MIN)
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5 DM335 Peripheral Information and Electrical Specifications
5.1 Parameter Information Device-Specific Information
A. The data sheet provides timing at the device pin. For output timing analysis, the tester pin electronics and its
transmission line effects must be taken into account. A transmission line with a delay of 2 ns or longer can be used to
produce the desired transmission line effect. The transmission line is intended as a load only. It is not necessary to
add or subtract the transmission line delay (2 ns or longer) from the data sheet timings.
Input requirements in this data sheet are tested with an input slew rate of < 4 Volts per nanosecond (4 V/ns) at the
device pin.
Figure 5-1. Test Load Circuit for AC Timing Measurements
The load capacitance value stated is only for characterization and measurement of AC timing signals. This
load capacitance value does not indicate the maximum load the device is capable of driving.
5.1.1 Signal Transition Levels
All input and output timing parameters are referenced to Vref for both "0" and "1" logic levels. For 3.3 V I/O,
Vref = 1.65 V. For 1.8 V I/O, Vref = 0.9 V.
Figure 5-2. Input and Output Voltage Reference Levels for AC Timing Measurements
All rise and fall transition timing parameters are referenced to VIL MAX and VIH MIN for input clocks,
VOLMAX and VOH MIN for output clocks.
Figure 5-3. Rise and Fall Transition Time Voltage Reference Levels
5.1.2 Timing Parameters and Board Routing Analysis
The timing parameter values specified in this data sheet do not include delays by board routings. As a
good board design practice, such delays must always be taken into account. Timing values may be
adjusted by increasing/decreasing such delays. TI recommends utilizing the available I/O buffer
information specification (IBIS) models to analyze the timing characteristics correctly. To properly use IBIS
models to attain accurate timing analysis for a given system, see the Using IBIS Models for Timing
Analysis application report (literature number SPRA839). If needed, external logic hardware such as
buffers may be used to compensate any timing differences.
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5.2 Recommended Clock and Control Signal Transition Behavior
All clocks and control signals should transition between VIH and VIL (or between VIL and VIH) in a
monotonic manner.
5.3 Power Supplies
The power supplies of DM335 are summarized in Table 5-1.
Table 5-1. Power Supplies
Customer Tolerance Package Chip Plane Description Comments
Board Plane Name
Supply
1.3 V ±5% 1.3 V CVDD Core VDD
VDDA_PLL1 PLL1 VDDA
VDDA_PLL2 PLL2 VDDA
VDDD13_USB USB 1.3 V supply
VDDA13_USB USB 1.3 V supply
3.3 V ±5% 3.3 V VDD IO VDD for LVCMOS VDDSHV
VDD IO VDD for MXI/O1 VDDSHV
VDD IO VDD for MXI/O2 VDDSHV1
VDD IO VDD for ISB DRVVBUS VDDSHV2
VDDA33_DDRDLL DDR DLL analog VDD
VDDA33_USB Analog 3.3 V power USB PHY
VDDA33_USB_PLL Common mode 3.3 V power for USB
PHY (PLL)
VDD IO VDD for peripherals
3.3 V ±5% 3.3 V VDD_VIN IO VDD for VideoIN I/F
VDD_VOUT IO VDD for VideoOUT I/F
1.8 V ±5% 1.8 V VDD_DDR
1.8 V ±5% 1.8 V VDDA18 Analog 1.8 V power
1.8 V ±5% 1.8 V VDDA18_DAC Place decoupling caps (0.1mF/10mf) close
to chip
0 V n/a 0 V VSS_MX1 Connect to external crystal capacitor
ground
0 V n/a 0 V VSS_MX2 Connect to external crystal capacitor
ground
0 V n/a 0 V VSS Chip ground
USB ESD ground
ground VSS
0 V n/a 0 V VSSA ground Keep separate from digital ground VSS
0 V n/a 0 V VSSA_PLL1 PLL1 VSSA
0 V n/a 0 V VSSA_PLL2 PLL2 VSSA
0 V n/a 0 V VSSA_DLL DLL ground
0 V n/a 0 V VSS_USB USB ground VSSA13_USB
VSSA13_USB
VSSA33_USB
VSSA33_USB_PLL
0 V n/a 0 V VSS_USB_REF USB PHY reference ground VSSREF
0 V n/a 0 V VSSA_DAC DAC ground Keep separate from digital ground VSS
VDDS*0.5 VDDS*0.5 VREFSSTL DRR ref voltage VDDS divided by 2, through board resistors
5 V 5 V USB_VBUS VBUS Connect to external charge pump
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5.3.1 Power-Supply Sequencing
In order to ensure device reliability, the DM335 requires the following power supply power-on and
power-off sequences. See table Table 5-1 for a description of DM335 power supplies.
Power-On:
1. Power on 1.3 V: CVDD, VDDA_PLL1/2, VDDD13_USB, VDDA13_USB
2. Power on 1.8 V: VDD_DDR, VDDA18_DAC
3. Power on 3.3 V: DVDD, VDDA33_DDRDLL, VDDA33_USB, VDDA33_USB_PLL, VDD_VIN, VDD_VOUT
You may power-on the 1.8 V and 3.3 V power supplies simultaneously.
Power-Off:
1. Power off 3.3 V: DVDD, VDDA33_DDRDLL, VDDA33_USB, VDDA33_USB_PLL, VDD_VIN, VDD_VOUT
2. Power off 1.8 V: VDD_DDR, VDDA18_DAC
3. Power off 1.3 V: CVDD, VDDA_PLL1/2, VDDD13_USB, VDDA13_USB
You may power-off the 1.8 V and 3.3 V power supplies simultaneously.
Power-off the 1.8v/3.3V supply before or within 10usec of power-off of the 1.3 V supply.
Note that when booting the DM335 from OneNAND, you must ensure that the OneNAND device is ready
with valid program instructions before the DM335 attempts to read program instructions from it. In
particular, before you release DM335 reset, you must allow time for OneNAND device power to stabilize
and for the OneNAND device to complete its internal copy routine. During the internal copy routine, the
OneNAND device copies boot code from its internal non-volatile memory to its internal boot memory
section. Board designers typically achieve this requirement by design of the system power and reset
supervisor circuit. Refer to your OneNAND device datasheet for OneNAND power ramp and stabilization
times and for OneNAND boot copy times.
5.3.1.1 Power-Supply Design Considerations
Core and I/O supply voltage regulators should be located close to the DM335 to minimize inductance and
resistance in the power delivery path. Additionally, when designing for high-performance applications
utilizing the DM335 device, the PC board should include separate power planes for core, I/O, and ground,
all bypassed with high-quality low-ESL/ESR capacitors.
5.3.1.2 Power-Supply Decoupling
In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as
possible close to DM335. These caps need to be close to the DM335 power pins, no more than 1.25 cm
maximum distance to be effective. Physically smaller caps, such as 0402, are better because of their
lower parasitic inductance. Proper capacitance values are also important. Small bypass caps (near 560
pF) should be closest to the power pins. Medium bypass caps (220 nF or as large as can be obtained in a
small package) should be next closest. TI recommends no less than 8 small and 8 medium caps per
supply be placed immediately next to the BGA vias, using the "interior" BGA space and at least the
corners of the "exterior".
Larger caps for each supply can be placed further away for bulk decoupling. Large bulk caps (on the order
of 100 mF) should be furthest away, but still as close as possible. Large caps for each supply should be
placed outside of the BGA footprint.
Any cap selection needs to be evaluated from a yield/manufacturing point-of-view. As with the selection of
any component, verification of capacitor availability over the product’s production lifetime should be
considered. See also Section 5.5.1 and Section 5.5.2 for additional recommendations on power supplies
for the oscillator/PLL supplies.
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1
23
RESET
BootConfigurationPins
(BTSEL[1:0],AECFG[3:0])
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5.4 Reset
5.4.1 Reset Electrical Data/Timing
Table 5-2. Timing Requirements for Reset (1) (2) (see Figure 5-4)
DM335
NO. PARAMETER UNIT
MIN MAX
1 tw(RESET) Active low width of the RESET pulse 12C ns
2 tsu(BOOT) Setup time, boot configuration pins valid before RESET rising edge 12C ns
3 th(BOOT) Hold time, boot configuration pins valid after RESET rising edge 12C ns
(1) BTSEL[1:0] and AECFG[4:0] are the boot configuration pins during device reset.
(2) C = MXI/CLKIN cycle time in ns. For example, when MXI/CLKIN frequency is 24 MHz use C = 41.6 ns.
Figure 5-4. Reset Timing
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Crystal
24MHzor
36MHz
C1 C2
MXI1/CLKIN MXO1 VSS_MX1
0.1 F
1 F
L1
VDDA_PLL1 VSSA_PLL1
CL
C1C2
(C1C2)
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5.5 Oscillators and Clocks
DM335 has two oscillator input/output pairs (MXI1/MXO1 and MXI2/MXO2) usable with external crystals
or ceramic resonators to provide clock inputs. The optimal frequencies for the crystals are 24 MHz
(MXI1/MXO1) and 27 MHz (MXI2/MXO2). Optionally, the oscillator inputs are configurable for use with
external clock oscillators. If external clock oscillators are used, to minimize the clock jitter, a single clean
power supply should power both the DM335 and the external oscillator circuit and the minimum CLKIN
rise and fall times must be observed. The electrical requirements and characteristics are described in this
section.
The timing parameters for CLKOUT[3:1] are also described in this section. The DM335 has three output
clock pins (CLKOUT[3:1]). See Section 3.5 and Section 3.6 for more information on CLKOUT[3:1].
5.5.1 MXI1 (24-MHz) Oscillator
The MXI1 (typically 24 MHz, can also be 36 MHz) oscillator provides the primary reference clock for the
DM335 device. The on-chip oscillator requires an external crystal connected across the MXI1 and MXO1
pins, along with two load capacitors, as shown in Figure 5-5. The external crystal load capacitors must be
connected only to the oscillator ground pin (VSS_MX1). Do not connect to board ground (VSS). Also, the PLL
power pin (VDDA_PLL1) should be connected to the power supply through a ferrite bead, L1 in the example
circuit shown in Figure 5-5.
Figure 5-5. MXI1 (24-MHz) Oscillator
The load capacitors, C1 and C2, should be chosen such that the equation is satisfied (typical values are
C1 = C2 = 10 pF). CL in the equation is the load specified by the crystal manufacturer. All discrete
components used to implement the oscillator circuit should be placed as close as possible to the
associated oscillator pins (MXI1 and MXO1) and to the VSS_MX1 pin.
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Crystal
27MHz
C1 C2
MXI2 MXO2 VSS_MX2
L1
VDDA_PLL2 VSSA_PLL2
0.1 F
1 F
CL
C1C2
(C1C2)
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Table 5-3. Switching Characteristics Over Recommended Operating Conditions for 24-MHz System
Oscillator
PARAMETER MIN TYP MAX UNIT
Start-up time (from power up until oscillating at stable frequency) 4 ms
Oscillation frequency 24 or 36 MHz
ESR 60 Ω
Frequency stability +/-50 ppm
5.5.2 MXI2 (27-MHz) Oscillator (optional oscillator)
The MXI2 (27 MHz) oscillator provides an optional reference clock for the DM335's VPSS module. The
on-chip oscillator requires an external 27-MHz crystal connected across the MXI2 and MXO2 pins, along
with two load capacitors, as shown in Figure 5-6. The external crystal load capacitors must be connected
only to the 27-MHz oscillator ground pin (VSS_MX2). Do not connect to board ground (VSS). Also, the PLL
power pin (VDDA_PLL2) should be connected to the power supply through a ferrite bead, L1 in the example
circuit shown in Figure 5-6.
Figure 5-6. MXI2 (27-MHz) System Oscillator
The load capacitors, C1 and C2, should be chosen such that the equation is satisfied (typical values are
C1 = C2 = 10 pF). CL in the equation is the load specified by the crystal manufacturer. All discrete
components used to implement the oscillator circuit should be placed as close as possible to the
associated oscillator pins (MXI and MXO) and to the VSS_MX2 pin.
Table 5-4. Switching Characteristics Over Recommended Operating Conditions for 27-MHz System
Oscillator
PARAMETER MIN TYP MAX UNIT
Start-up time (from power up until oscillating at stable frequency) 4 ms
Oscillation frequency 27 MHz
ESR 60 Ω
Frequency stability +/-50 ppm
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MXI/CLKIN
2
3
4
4
51
MXI/CLKIN
2
3
4
4
51
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5.5.3 Clock PLL Electrical Data/Timing (Input and Output Clocks)
Table 5-5. Timing Requirements for MXI1/CLKIN1(1) (2) (see Figure 5-7)
DM335
NO. PARAMETER UNIT
MIN TYP MAX
1 tc(MXI1) Cycle time, MXI1/CLKIN1 27.7 (3) 41.6 (3) ns
2 tw(MXI1H) Pulse duration, MXI1/CLKIN1 high 0.45C 0.55C ns
3 tw(MXI1L) Pulse duration, MXI1/CLKIN1 low 0.45C 0.55C ns
0.25C or
4 tt(MXI1) Transition time, MXI1/CLKIN1 ns
10(4)
5 tJ(MXI1) Period jitter, MXI1/CLKIN1 0.02C ns
(1) The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
(2) C = MXI1/CLKIN1 cycle time in ns. For example, when MXI1/CLKIN1 frequency is 24 MHz use C = 41.6 ns.
(3) tc(MXI1) = 41.6 ns and tc(MXI1) = 27.7 ns are the only supported cycle times for MXI1/CLKIN1.
(4) Whichever is smaller. C = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve
noise immunity on input signals.
Figure 5-7. MXI1/CLKIN1 Timing
Table 5-6. Timing Requirements for MXI2/CLKIN2(1) (2) (see Figure 5-7)
DM335
NO. PARAMETER UNIT
MIN TYP MAX
1 tc(MXI2) Cycle time, MXI2/CLKIN2 37.037 (3) 37.037 (3) ns
2 tw(MXI2H) Pulse duration, MXI2/CLKIN2 high 0.45C 0.55C ns
3 tw(MXI2L) Pulse duration, MXI2/CLKIN2 low 0.45C 0.55C ns
0.25C or
4 tt(MXI2) Transition time, MXI2/CLKIN2 ns
10(4)
5 tJ(MXI2) Period jitter, MXI2/CLKIN2 0.02C ns
(1) The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.
(2) C = MXI2/CLKIN2 cycle time in ns. For example, when MXI2/CLKIN2 frequency is 27 MHz use C = 37.037 ns.
(3) tc(MXI2) = 37.037 ns is the only supported cycle time for MXI2/CLKIN2.
(4) Whichever is smaller. C = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve
noise immunity on input signals.
Figure 5-8. MXI2/CLKIN2 Timing
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CLKOUT1
1
24
4
MXI/CLKIN
5 6
3
MXI/CLKIN
CLKOUT2
1
2
3
4
5
6
4
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Table 5-7. Switching Characteristics Over Recommended Operating Conditions for CLKOUT1(1) (2) (see
Figure 5-9)
DM335
NO. PARAMETER UNIT
MIN TYP MAX
1 tC(CLKOUT1) Cycle time, CLKOUT1 tc(MXI1) ns
2 tw(CLKOUT1H) Pulse duration, CLKOUT1 high 0.45P 0.55P ns
3 tw(CLKOUT1L) Pulse duration, CLKOUT1 low 0.45P 0.55P ns
4 tt(CLKOUT1) Transition time, CLKOUT1 0.05P ns
5 td(MXI1H-CLKOUT1H) Delay time, MXI1/CLKIN1 high to CLKOUT1 high 1 8 ns
6 td(MXI1L-CLKOUT1L) Delay time, MXI1/CLKIN1I low to CLKOUT1 low 1 8 ns
(1) The reference points for the rise and fall transitions are measured at VOL MAX and VOHMIN.
(2) P = 1/CLKOUT1 clock frequency in nanoseconds (ns). For example, when CLKOUT1 frequency is 24 MHz use P = 41.6 ns.
Figure 5-9. CLKOUT1 Timing
Table 5-8. Switching Characteristics Over Recommended Operating Conditions for CLKOUT2(1) (2) (see
Figure 5-10)
DM335
NO. PARAMETER UNIT
MIN TYP MAX
1 tC(CLKOUT2) Cycle time, CLKOUT2 tc(MXI1) /3
2 tw(CLKOUT2H) Pulse duration, CLKOUT2 high 0.45P 0.55P ns
3 tw(CLKOUT2L) Pulse duration, CLKOUT2 low 0.45P 0.55P ns
4 tt(CLKOUT2) Transition time, CLKOUT2 0.05P ns
5 td(MXI1H-CLKOUT2H) Delay time, MXI1/CLKIN1 high to CLKOUT2 high 1 8 ns
6 td(MXI1L-CLKOUT2L) Delay time, MXI1/CLKIN1 low to CLKOUT2 low 1 8 ns
(1) The reference points for the rise and fall transitions are measured at VOL MAX and VOHMIN.
(2) P = 1/CLKOUT2 clock frequency in nanoseconds (ns). For example, when CLKOUT2 frequency is 8 MHz use P = 125 ns.
Figure 5-10. CLKOUT2 Timing
Table 5-9. Switching Characteristics Over Recommended Operating Conditions for CLKOUT3(1) (2) (see
(1) The reference points for the rise and fall transitions are measured at VOL MAX and VOHMIN.
(2) P = 1/CLKOUT3 clock frequency in nanoseconds (ns). For example, when CLKOUT3 frequency is 3 MHz use P = 333.3 ns.
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5 6
1
2 3
4
4
MXI/CLKIN
CLKOUT3
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Table 5-9. Switching Characteristics Over Recommended Operating Conditions for CLKOUT3 (1) (2) (see
Figure 5-11 ) (continued)
Figure 5-11)
DM335
NO. PARAMETER UNIT
MIN TYP MAX
1 tC(CLKOUT3) Cycle time, CLKOUT3 tc(MXI1) /8
2 tw(CLKOUT3H) Pulse duration, CLKOUT3 high 0.45P 0.55P ns
3 tw(CLKOUT3L) Pulse duration, CLKOUT3 low 0.45P 0.55P ns
4 tt(CLKOUT3) Transition time, CLKOUT3 0.05P ns
5 td(MXI2H-CLKOUT3H) Delay time, CLKIN/MXI high to CLKOUT3 high 1 8 ns
6 td(MXI2L-CLKOUT3L) Delay time, CLKIN/MXI low to CLKOUT3 low 1 8 ns
Figure 5-11. CLKOUT3 Timing
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5.6 General-Purpose Input/Output (GPIO)
The GPIO peripheral provides general-purpose pins that can be configured as either inputs or outputs.
When configured as an output, a write to an internal register can control the state driven on the output pin.
When configured as an input, the state of the input is detectable by reading the state of an internal
register. In addition, the GPIO peripheral can produce CPU interrupts and EDMA events in different
interrupt/event generation modes. The GPIO peripheral provides generic connections to external devices.
The GPIO pins are grouped into banks of 16 pins per bank (i.e., bank 0 consists of GPIO [0:15]). There
are a total of 7 GPIO banks in the DM335, because the DM335 has 104 GPIOs.
The DM335 GPIO peripheral supports the following:
• Up to 104 3.3v GPIO pins, GPIO[103:0]
• Interrupts:
– Up to 10 unique GPIO[9:0] interrupts from Bank 0
– Up to 7 GPIO (bank aggregated) interrupt signals, one from each of the 7 banks of GPIOs
– Interrupts can be triggered by rising and/or falling edge, specified for each interrupt capable GPIO
signal
• DMA events:
– Up to 10 unique GPIO DMA events from Bank 0
– Up to 7 GPIO (bank aggregated) DMA event signals, one from each of the 7 banks of GPIOs
• Set/clear functionality: Firmware writes 1 to corresponding bit position(s) to set or to clear GPIO
signal(s). This allows multiple firmware processes to toggle GPIO output signals without critical section
protection (disable interrupts, program GPIO, re-enable interrupts, to prevent context switching to
anther process during GPIO programming).
• Separate Input/Output registers
• Output register in addition to set/clear so that, if preferred by firmware, some GPIO output signals can
be toggled by direct write to the output register(s).
• Output register, when read, reflects output drive status. This, in addition to the input register reflecting
pin status and open-drain I/O cell, allows wired logic be implemented.
For more detailed information on GPIOs, see the TMS320DM335 Digital Media System-on-Chip (DMSoC)
General-Purpose Input/Output (GPIO) Reference Guide (literature number SPRUFY8).
5.6.1 GPIO Peripheral Input/Output Electrical Data/Timing
Table 5-10. Timing Requirements for GPIO Inputs (see Figure 5-12)
DM335
NO. PARAMETER UNIT
MIN MAX
1 tw(GPIH) Pulse duration, GPIx high 52 ns
2 tw(GPIL) Pulse duration, GPIx low 52 ns
Table 5-11. Switching Characteristics Over Recommended Operating Conditions for GPIO Outputs
(see Figure 5-12)
DM335
NO. PARAMETER UNIT
MIN MAX
3 tw(GPOH) Pulse duration, GPOx high 26(1) ns
4 tw(GPOL) Pulse duration, GPOx low 26(1) ns
(1) This parameter value should not be used as a maximum performance specification. Actual performance of back-to-back accesses of the
GPIO is dependent upon internal bus activity.
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GPIx
GPOx
4
3
2
1
EXT_INTx
2
1
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Figure 5-12. GPIO Port Timing
5.6.2 GPIO Peripheral External Interrupts Electrical Data/Timing
Table 5-12. Timing Requirements for External Interrupts/EDMA Events(1) (see Figure 5-13)
DM335
NO. PARAMETER UNIT
MIN MAX
1 tw(ILOW) Width of the external interrupt pulse low 52 ns
2 tw(IHIGH) Width of the external interrupt pulse high 52 ns
(1) The pulse width given is sufficient to generate an interrupt or an EDMA event. However, if a user wants to have DM335 to recognize the
GPIO changes through software polling of the GPIO register, the GPIO duration must be extended to allow DM335 enough time to
access the GPIO register through the internal bus.
Figure 5-13. GPIO External Interrupt Timing
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5.7 External Memory Interface (EMIF)
DM335 supports several memory and external device interfaces, including:
• Asynchronous EMIF (AEMIF) for interfacing to SRAM.
– OneNAND flash memories
– NAND flash memories
• DDR2/mDDR Memory Controller for interfacing to SDRAM.
5.7.1 Asynchronous EMIF (AEMIF)
The EMIF supports the following features:
• SRAM, etc. on up to 2 asynchronous chip selects addressable up to 64KB each
• Supports 8-bit or 16-bit data bus widths
• Programmable asynchronous cycle timings
• Supports extended wait mode
• Supports Select Strobe mode
5.7.1.1 NAND (NAND, SmartMedia, xD)
The NAND features of the EMIF are as follows:
• NAND flash on up to 2 asynchronous chip selects
• 8 and 16-bit data bus widths
• Programmable cycle timings
• Performs 1-bit and 4-bit ECC calculation
• NAND Mode also supports SmartMedia/SSFDC (Solid State Floppy Disk Controller) and xD memory
cards
5.7.1.2 OneNAND
The OneNAND features supported are as follows.
• NAND flash on up to 2 asynchronous chip selects
• Only 16-bit data bus widths
• Supports asynchronous writes and reads
• Supports synchronous reads with continuous linear burst mode (Does not support synchronous reads
with wrap burst modes)
• Programmable cycle timings for each chip select in asynchronous mode
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5.7.1.3 AEMIF Electrical Data/Timing
Table 5-13. Timing Requirements for Asynchronous Memory Cycles for AEMIF Module(1) (see Figure 5-14
and Figure 5-15)
DM335
NO PARAMETER UNIT
.MIN Nom MAX
READS and WRITES
Pulse duration, EM_WAIT assertion and
2 tw(EM_WAIT) 2E ns
deassertion
READS
12 tsu(EMDV-EMOEH) Setup time, EM_D[15:0] valid before EM_OE high 5 ns
13 th(EMOEH-EMDIV) Hold time, EM_D[15:0] valid after EM_OE high 0 ns
tsu Setup time EM_WAIT asserted before EM_OE
14 4E ns
(EMOEL-EMWAIT) high(2)
READS (OneNAND Synchronous Burst Read)
Setup time, EM_D[15:0] valid before EM_CLK
30 tsu(EMDV-EMCLKH) 4 ns
high
31 th(EMCLKH-EMDIV) Hold time, EM_D[15:0] valid after EM_CLK high 4 ns
WRITES
tsu Setup time, EM_WAIT asserted before EM_WE
28 4E ns
(EMWEL-EMWAIT) high(2)
(1) E = PLLC1 SYSCLK2 period in ns. SYSCLK2 is the EMIF peripheral clock. SYSCLK2 is one-fourth the PLLC output clock. For example,
when PLLC output clock = 432 MHz, E = 9.259 ns. See Section 3.5 for more information.
(2) Setup before end of STROBE phase (if no extended wait states are inserted) by which EM_WAIT must be asserted to add extended
wait states. Figure 5-16 and Figure 5-17 describe EMIF transactions that include extended wait states inserted during the STROBE
phase. However, cycles inserted as part of this extended wait period should not be counted; the 4E requirement is to the start of where
the HOLD phase would begin if there were no extended wait cycles.
Table 5-14. Switching Characteristics Over Recommended Operating Conditions for Asynchronous
Memory Cycles for AEMIF Module(1) (2) (3) (see Figure 5-14 and Figure 5-15)
DM335 UNI
NO. PARAMETER T
MIN Nom MAX
READS and WRITES
1 td(TURNAROUND) Turn around time (TA)*E ns
READS
EMIF read cycle time (EW = 0) (RS+RST+RH)*E ns
3 tc(EMRCYCLE) (RS+RST+RH+(EWC*
EMIF read cycle time (EW = 1) ns
16))*E
Output setup time, EM_CE[1:0] low to (RS)*E ns
EM_OE low (SS = 0)
4 tsu(EMCEL-EMOEL) Output setup time, EM_CE[1:0] low to 0 ns
EM_OE low (SS = 1)
Output hold time, EM_OE high to (RH)*E ns
EM_CE[1:0] high (SS = 0)
5 th(EMOEH-EMCEH) Output hold time, EM_OE high to 0 ns
EM_CE[1:0] high (SS = 1)
(1) TA = Turn around, RS = Read setup, RST = Read strobe, RH = Read hold, WS = Write setup, WST = Write strobe, WH = Write hold,
MEWC = Maximum external wait cycles. These parameters are programmed via the Asynchronous Bank and Asynchronous Wait Cycle
Configuration Registers. These support the following range of values: TA[4-1], RS[16-1], RST[64-1], RH[8-1], WS[16-1], WST[64-1],
WH[8-1], and MEW[1-256]. See the TMS320DM335 Digital Media System-on-Chip (DMSoC) Asynchronous External Memory Interface
(EMIF) Reference Guide (SPRUFZ1) for more information.
(2) E = PLLC1 SYSCLK2 period in ns. SYSCLK2 is the EMIF peripheral clock. SYSCLK2 is one-fourth the PLLC output clock. For example,
when PLLC output clock = 432 MHz, E = 9.259 ns. See Section 3.5 for more information
(3) EWC = external wait cycles determined by EM_WAIT input signal. EWC supports the following range of values EWC[256-1]. Note that
the maximum wait time before timeout is specified by bit field MEWC in the Asynchronous Wait Cycle Configuration Register. See the
TMS320DM335 Digital Media System-on-Chip (DMSoC) Asynchronous External Memory Interface (EMIF) Reference Guide
(SPRUFZ1).
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Table 5-14. Switching Characteristics Over Recommended Operating Conditions for Asynchronous
Memory Cycles for AEMIF Module (1) (2) (3) (see Figure 5-14 and Figure 5-15 ) (continued)
DM335 UNI
NO. PARAMETER T
MIN Nom MAX
Output setup time, EM_BA[1:0] valid to
6 tsu(EMBAV-EMOEL) (RS)*E ns
EM_OE low
Output hold time, EM_OE high to
7 th(EMOEH-EMBAIV) (RH)*E ns
EM_BA[1:0] invalid
Output setup time, EM_A[13:0] valid to
8 tsu(EMBAV-EMOEL) (RS)*E ns
EM_OE low
Output hold time, EM_OE high to
9 th(EMOEH-EMAIV) (RH)*E ns
EM_A[13:0] invalid
EM_OE active low width (EW = 0) (RST)*E ns
10 tw(EMOEL) EM_OE active low width (EW = 1) (RST+(EWC*16))*E ns
td(EMWAITH- Delay time from EM_WAIT deasserted to
11 4E ns
EMOEH) EM_OE high
READS (OneNAND Synchronous Burst Read)(4)
MH
32 fc(EM_CLK) Frequency, EM_CLK 1 66 z
33 tc(EM_CLK) Cycle time, EM_CLK 15 1000 ns
tsu(EM_ADVV- Output setup time, EM_ADV valid before
34 5 ns
EM_CLKH) EM_CLK high
th(EM_CLKH- Output hold time, EM_CLK high to EM_ADV
35 6 ns
EM_ADVIV) invalid
tsu(EM_AV- Output setup time, EM_A[13:0]/EM_BA[1]
36 5 ns
EM_CLKH) valid before EM_CLK high
th(EM_CLKH- Output hold time, EM_CLK high to
37 6 ns
EM_AIV) EM_A[13:0]/EM_BA[1] invalid
38 tw(EM_CLKH) Pulse duration, EM_CLK high tc(EM_CLK)/3 ns
39 tw(EM_CLKL) Pulse duration, EM_CLK low tc(EM_CLK)/3 ns
WRITES
EMIF write cycle time (EW = 0) (WS+WST+WH)*E ns
15 tc(EMWCYCLE) (WS+WST+WH+(EW
EMIF write cycle time (EW = 1) ns
C*16))*E
Output setup time, EM_CE[1:0] low to (WS)*E ns
EM_WE low (SS = 0)
16 tsu(EMCEL-EMWEL) Output setup time, EM_CE[1:0] low to 0 ns
EM_WE low (SS = 1)
Output hold time, EM_WE high to (WH)*E ns
EM_CE[1:0] high (SS = 0)
17 th(EMWEH-EMCEH) Output hold time, EM_WE high to 0 ns
EM_CE[1:0] high (SS = 1)
Output setup time, EM_BA[1:0] valid to
20 tsu(EMBAV-EMWEL) (WS)*E ns
EM_WE low
Output hold time, EM_WE high to
21 th(EMWEH-EMBAIV) (WH)*E ns
EM_BA[1:0] invalid
Output setup time, EM_A[13:0] valid to
22 tsu(EMAV-EMWEL) (WS)*E ns
EM_WE low
Output hold time, EM_WE high to
23 th(EMWEH-EMAIV) (WH)*E ns
EM_A[13:0] invalid
EM_WE active low width (EW = 0) (WST)*E ns
24 tw(EMWEL) EM_WE active low width (EW = 1) (WST+(EWC*16))*E ns
td(EMWAITH- Delay time from EM_WAIT deasserted to
25 4E ns
EMWEH) EM_WE high
(4) During OneNAND Mode the EM_CLK is driven by 1/2 PLLC1SYSCLK2 clk.
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EM_CE[1:0]
EM_BA[1:0]
13
12
EM_A[13:0]
EM_OE
EM_D[15:0]
EM_WE
10
5
9
7
4
8
6
3
1
TMS320DM335
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Table 5-14. Switching Characteristics Over Recommended Operating Conditions for Asynchronous
Memory Cycles for AEMIF Module (1) (2) (3) (see Figure 5-14 and Figure 5-15 ) (continued)
DM335 UNI
NO. PARAMETER T
MIN Nom MAX
Output setup time, EM_D[15:0] valid to
26 tsu(EMDV-EMWEL) (WS)*E ns
EM_WE low
Output hold time, EM_WE high to
27 th(EMWEH-EMDIV) (WH)*E ns
EM_D[15:0] invalid
Figure 5-14. Asynchronous Memory Read Timing for EMIF
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EM_CE[1:0]
EM_BA[1:0]
EM_A[13:0]
EM_WE
EM_D[15:0]
EM_OE
15
1
16
18
20
22 24
17
19
21
23
26
27
EM_CE[1:0]
11
Asserted Deasserted
2
2
14
EM_BA[1:0]
EM_A[13:0]
EM_D[15:0]
EM_OE
EM_WAIT
SETUP STROBE Extended Due to EM_WAIT STROBE HOLD
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Figure 5-15. Asynchronous Memory Write Timing for EMIF
Figure 5-16. EM_WAIT Read Timing Requirements
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EM_CE[1:0]
25
Asserted Deasserted
2
2
EM_BA[1:0]
EM_A[13:0]
EM_D[15:0]
EM_WE
EM_WAIT
SETUP STROBE Extended Due to EM_WAIT STROBE HOLD
28
34
33
35
36
37 30
31
Da Da+1 Da+2 Da+3 Da+4 Da+5 Da+n
Da+n+1
EM_CLK
EM_CE[1:0]
EM_ADV
EM_BA0,
EM_A[13:0],
EM_BA1
EM_D[15:0]
EM_OE
EM_WAIT
38
39
TMS320DM335
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Figure 5-17. EM_WAIT Write Timing Requirements
Figure 5-18. Synchronous OneNAND Flash Read Timing
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5.7.2 DDR2/mDDR Memory Controller
The DDR2 / mDDR Memory Controller is a dedicated interface to DDR2 / mDDR SDRAM. It supports
JESD79D-2A standard compliant DDR2 SDRAM devices and compliant Mobile DDR SDRAM devices.
DDR2 / mDDR SDRAM plays a key role in a DM335-based system. Such a system is expected to require
a significant amount of high-speed external memory for all of the following functions:
• Buffering of input image data from sensors or video sources
• Intermediate buffering for processing/resizing of image data in the VPFE
• Numerous OSD display buffers
• Intermediate buffering for large raw Bayer data image files while performing image processing
functions
• Buffering for intermediate data while performing video encode and decode functions
• Storage of executable code for the ARM
The DDR2 / mDDR Memory Controller supports the following features:
• JESD79D-2A standard compliant DDR2 SDRAM
• Mobile DDR SDRAM
• 256 MByte memory space
• Data bus width 16 bits
• CAS latencies:
– DDR2: 2, 3, 4, and 5
– mDDR: 2 and 3
• Internal banks:
– DDR2: 1, 2, 4, and 8
– mDDR: 1, 2, and 4
• Burst length: 8
• Burst type: sequential
• 1 CS signal
• Page sizes: 256, 512, 1024, and 2048
• SDRAM autoinitialization
• Self-refresh mode
• Partial array self-refresh (for mDDR)
• Power down mode
• Prioritized refresh
• Programmable refresh rate and backlog counter
• Programmable timing parameters
• Little endian
For details on the DDR2 Memory Controller, refer to TMS320DM335 Digital Media System-on-Chip
(DMSoC) DDR2/Mobile DDR (DDR2/mDDR) Memory Controller Reference Guide (literature number
SPRUFZ2).
5.7.2.1 DDR2/mDDR Memory Controller Electrical Data/Timing
The Implementing DDR2/mDDR PCB Layout on the TMS320DM335 DMSoC Application Report (literature
number SPRAAL2) specifies a complete DDR2 and mDDR interface solution for the DM335 as well as a
list of compatible DDR2/mDDR devices. TI has performed the simulation and system characterization to
ensure all DDR2 and mDDR interface timings in this solution are met.
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TI only supports board designs that follow the guidelines outlined in the implementing DDR2/mDDR PCB
Layout on the TMS320DM335 DMSoC Application Report (literature number SPRAAL2).
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5.8 MMC/SD
The DM335 includes two separate MMC/SD Controllers which are compliant with MMC V3.31, Secure
Digital Part 1 Physical Layer Specification V1.1 and Secure Digital Input Output (SDIO) V1.0
specifications.
The DM335 MMC/SD Controller has following features:
• MultiMediaCard (MMC).
• Secure Digital (SD) Memory Card.
• MMC/SD protocol support.
• SDIO protocol support.
• Programmable clock frequency.
• 256 bit Read/Write FIFO to lower system overhead.
• Slave EDMA transfer capability.
The DM335 MMC/SD Controller does not support SPI mode.
5.8.1 MMC/SD Electrical Data/Timing
Table 5-15. Timing Requirements for MMC/SD Module
(see Figure 5-20 and Figure 5-22)
DM335
STANDARD
NO. PARAMETER FAST MODE UNIT
MODE
MIN MAX MIN MAX
1 tsu(CMDV-CLKH) Setup time, SD_CMD valid before SD_CLK high 6 5 ns
2 th(CLKH-CMDV) Hold time, SD_CMD valid after SD_CLK high 2.5(1) 5 ns
3 tsu(DATV-CLKH) Setup time, SD_DATx valid before SD_CLK high 6 5 ns
4 th(CLKH-DATV) Hold time, SD_DATx valid after SD_CLK high 2.5 5 ns
(1) For this parameter, you may include margin in your board design so that the toh = 2.5 ns of the MMC/SD device is not degraded at the
DM335 input pin.
Table 5-16. Switching Characteristics Over Recommended Operating Conditions for MMC/SD Module
(see Figure 5-19 through Figure 5-22)
DM335
STANDARD
NO. PARAMETER FAST MODE UNIT
MODE
MIN MAX MIN MAX
7 f(CLK) Operating frequency, SD_CLK 0 50 0 25 MHz
8 f(CLK_ID) Identification mode frequency, SD_CLK 0 400 0 400 KHz
9 tW(CLKL) Pulse width, SD_CLK low 7 10 ns
10 tW(CLKH) Pulse width, SD_CLK high 7 10 ns
11 tr(CLK) Rise time, SD_CLK 3 10 ns
12 tf(CLK) Fall time, SD_CLK 3 10 ns
13 td(CLKL-CMD) Delay time, SD_CLK low to SD_CMD transition -7.5 4 -7.5 14 ns
14 td(CLKL-DAT) Delay time, SD_CLK low to SD_DATx transition -7.5 4 -7.5 14 ns
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START XMIT Valid Valid Valid END
SD_CLK
SD_CMD
13
7
10
9
13 13 13
START XMIT Valid Valid Valid END
SD_CLK
SD_CMD
10
9
7
1
2
START D0 D1 Dx END
SD_CLK
SD_DATx
7
1414
10
9
14 14
Start D0 D1 Dx End
7
SD_CLK
SD_DATx
9
10
4
3 3
4
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Figure 5-19. MMC/SD Host Command Timing
Figure 5-20. MMC/SD Card Response Timing
Figure 5-21. MMC/SD Host Write Timing
Figure 5-22. MMC/SD Host Read and Card CRC Status Timing
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5.9 Video Processing Sub-System (VPSS) Overview
The DM335 contains a Video Processing Sub-System (VPSS) that provides an input interface (Video
Processing Front End or VPFE) for external imaging peripherals such as image sensors, video decoders,
etc.; and an output interface (Video Processing Back End or VPBE) for display devices, such as analog
SDTV displays, digital LCD panels, HDTV video encoders, etc.
In addition to these peripherals, there is a set of common buffer memory and DMA control to ensure
efficient use of the DDR2 burst bandwidth. The shared buffer logic/memory is a unique block that is
tailored for seamlessly integrating the VPSS into an image/video processing system. It acts as the primary
source or sink to all the VPFE and VPBE modules that are either requesting or transferring data from/to
DDR2. In order to efficiently utilize the external DDR2 bandwidth, the shared buffer logic/memory
interfaces with the DMA system via a high bandwidth bus (64-bit wide). The shared buffer logic/memory
also interfaces with all the VPFE and VPBE modules via a 128-bit wide bus. The shared buffer
logic/memory (divided into the read & write buffers and arbitration logic) is capable of performing the
following functions. It is imperative that the VPSS utilize DDR2 bandwidth efficiently due to both its large
bandwidth requirements and the real-time requirements of the VPSS modules. Because it is possible to
configure the VPSS modules in such a way that DDR2 bandwidth is exceeded, a set of user accessible
registers is provided to monitor overflows or failures in data transfers.
5.9.1 Video Processing Front-End (VPFE)
The VPFE or Video Processing Front-End block is comprised of the CCD Controller (CCDC), Image Pipe
(IPIPE), and Hardware 3A Statistic Generator (H3A). These modules are described in the sections that
follow.
5.9.1.1 CCD Controller (CCDC)
The CCDC is responsible for accepting raw (unprocessed) image/video data from a sensor (CMOS or
CCD). In addition, the CCDC can accept YUV video data in numerous formats, typically from so-called
video decoder devices. In the case of raw inputs, the CCDC output requires additional image processing
to transform the raw input image to the final processed image. This processing can be done either
on-the-fly in the Preview Engine hardware ISP or in software on the ARM. In parallel, raw data input to the
CCDC can also used for computing various statistics (3A, Histogram) to eventually control the image/video
tuning parameters. The CCDC is programmed via control and parameter registers. The following features
are supported by the CCDC module.
• Support for conventional Bayer pattern.
• Generates HD/VD timing signals and field ID to an external timing generator or can synchronize to the
external timing generator.
• Support for progressive and interlaced sensors (hardware support for up to 2 fields and firmware
support for higher number of fields, typically 3-, 4-, and 5-field sensors).
• Support for up to 75-MHZ sensor pixel clock if H3A is not used, otherwise the pixel clock must be less
than 67.5 MHZ
• Support for ITU-R BT.656 standard format, either 8-bit or 16-bit.
• Support for YCbCr 422 format, either 8- or 16-bit with discrete HSYNC and VSYNC signals.
• Support for up to 14-bit input.
• Support for color space conversion
• Generates optical black clamping signals.
• Support for shutter signal control.
• Support for digital clamping and black level compensation.
• Fault pixel correction based on a lookup table that contains row and column position of the pixel to be
corrected.
• Support for program lens shading correction.
• Support for 10-bit to 8-bit A-law compression.
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• Support for a low-pass filter prior to writing to SDRAM. If this filter is enabled, 2 pixels each in the left
and right edges of each line are cropped from the output.
• Support for generating output to range from 14-bits to 8-bits wide (8-bits wide allows for 50% saving in
storage area).
• Support for down sampling via programmable culling patterns.
• Ability to control output to the DDR2 via an external write enable signal.
• Support for up to 32K pixels (image size) in both the horizontal and vertical direction.
5.9.1.2 IPIPE - Image Pipe
The hardware Image Pipe (IPIPE) is a programmable hardware image processing module that is
responsible for transforming raw (unprocessed) image/video data from a sensor (CMOS or CCD) into
YCbCr 422 data that is amenable for compression or display. The IPIPE can also be configured to operate
in a resize only mode, which allows YCbCr 422 to be resized without applying the processing of every
module in the IPIPE. Typically, the output of the IPIPE is used for both video compression and displaying
it on an external display device such as a NTSC/PAL analog encoder or a digital LCD. The IPIPE is
programmed via control and parameter registers. The following features are supported by the IPIPE.
• The input interface extracts valid raw data from the CCD raw data, and then various modules in IPIPE
process the raw CCD data.
• The 2D noise filter module reduces impulse noise in the raw data and adjusts the resolution of the
input image.
• The 2D pre-filter adjusts the resolution of the input image and remove line crawl noise.
• The white balance module applies two gain adjustments to the data: a digital gain (total gain) and a
white balance gain.
• The Color Filter Array (CFA) interpolation module implements CFA interpolation. The output from the
CFA interpolation module is always RGB formatted data.
• The RGB2RGB blending module applies a 3x3 matrix transform to the RGB data generated by the
CFA interpolation module.
• The gamma correction module independently applies gamma correction to each RGB component.
Gamma is implemented using a piece-wise linear interpolation approach with a 512 entry look up table
for each color.
• The RGB2YCbCr conversion module applies 3x3 matrix transformation to the RGB data to convert it to
YCbCr data. This module also implements offset.
• The 4:2:2 conversion module applies the chroma low pass filter and down samples Cb and Cr, so that
IPIPE output data is in YCbCr-4:2:2 format.
• The 2D edge enhancer module improves image clarity with luminance non-linear filter. This module
also has contrast and brightness adjustment functions.
• The chroma suppression module reduces faulty-color using luminance (Y) value or high-pass-filtering Y
value. The H-resizer and V-resizer modules resize horizontal and vertical image sizes, respectively.
• The output interface module transfers data from IPIPE to SDRAM, in the form of YCbCr-422 or RGB
(32bit/16bit).
• The histogram function can record histograms of up to 4 distinct areas into up to 256 bins.
• IPIPE has three different processing paths:
– Case 1: The CCD raw data directly leads to IPIPE and stores the YCbCr (or RGB) data to SDRAM.
– Case 2: IPIPE reads CCD raw data and stores the Bayer pattern data after white balance to
SDRAM.
– Case 3: IPIPE reads YCbCr-422 data and apply edge enhance, chroma suppression and Resize to
output YCbCr (or RGB) data to SDRAM.
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5.9.1.3 Hardware 3A (H3A)
The H3A module is designed to support the control loops for Auto Focus, Auto White Balance and Auto
Exposure by collecting metrics about the imaging/video data. The metrics are to adjust the various
parameters for processing the imaging/video data. There are 2 main blocks in the H3A module:
• Auto Focus (AF) engine
• Auto Exposure (AE) Auto White Balance (AWB) engine
The AF engine extracts and filters the red, green, and blue data from the input image/video data and
provides either the accumulation or peaks of the data in a specified region. The specified region is a
two-dimensional block of data and is referred to as a "paxel" for the case of AF.
The AE/AWB Engine accumulates the values and checks for saturated values in a sub sampling of the
video data. In the case of the AE/AWB, the two-dimensional block of data is referred to as a "window".
Thus, other than referring them by different names, a paxel and a window are essentially the same thing.
However, the number, dimensions, and starting position of the AF paxels and the AE/AWB windows are
separately programmable.
The following features are supported by the AF engine:
• Support for input from DDR2 / mDDR SDRAM (in addition to the CCDC port)
• Support for a Peak Mode in a Paxel (a Paxel is defined as a two dimensional block of pixels).
• Accumulate the maximum Focus Value of each line in a Paxel
• Support for an Accumulation/Sum Mode (instead of Peak mode).
• Accumulate Focus Value in a Paxel.
• Support for up to 36 Paxels in the horizontal direction and up to 128 Paxels in the vertical direction.
The number of horizontal paxels is limited by the memory size (and cost), while the vertical number of
paxels is not. Therefore, the number of paxels in horizontal direction is smaller than the number of
paxels in vertical direction.
• Programmable width and height for the Paxel. All paxels in the frame will be of same size.
• Programmable red, green, and blue position within a 2x2 matrix.
• Separate horizontal start for paxel and filtering.
• Programmable vertical line increments within a paxel.
• Parallel IIR filters configured in a dual-biquad configuration with individual coefficients (2 filters with 11
coefficients each). The filters are intended to compute the sharpness/peaks in the frame to focus on.
The following features are supported by the AE/AWB engine:
• Support for input from DDR2 / mDDR SDRAM (in addition to the CCDC port)
• Accumulate clipped pixels along with all non-saturated pixels
• Support for up to 36 horizontal windows.
• Support for up to 128 vertical windows.
• Programmable width and height for the windows. All windows in the frame will be of same size.
• Separate vertical start co-ordinate and height for a black row of paxels that is different than the
remaining color paxels.
• Programmable Horizontal Sampling Points in a window
• Programmable Vertical Sampling Points in a window
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2
1
3
4
4
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5.9.1.4 VPFE Electrical Data/Timing
Table 5-17. Timing Requirements for VPFE PCLK Master/Slave Mode(1) (see Figure 5-23)
NO. PARAMETER MIN MAX UNIT
H3A not used 13.33 or P(2) 100 ns
1 tc(PCLK) Cycle time, PCLK H3A used 2P + 1 100 ns
2 tw(PCLKH) Pulse duration, PCLK high 5.7 ns
3 tw(PCLKL) Pulse duration, PCLK low 5.7 ns
4 tt(PCLK) Transition time, PCLK 3 ns
(1) P = 1/SYSCLK4 in nanoseconds (ns). For example, if the SYSCLK4 frequency is 216 MHz, use P = 4.63 ns. See Section 3.5 ,Device
Clocking, for more information on the supported clock configurations of the DM335.
(2) Use whichever value is greater.
Figure 5-23. VPFE PCLK Timing
Table 5-18. Timing Requirements for VPFE (CCD) Slave Mode (see Figure 5-24)
DM335
NO. PARAMETER UNIT
MIN MAX
5 tsu(CCDV-PCLK) Setup time, CCD valid before PCLK edge 3 ns
6 th(PCLK-CCDV) Hold time, CCD valid after PCLK edge 2 ns
7 tsu(HDV-PCLK) Setup time, HD valid before PCLK edge 3 ns
8 th(PCLK-HDV) Hold time, HD valid after PCLK edge 2 ns
9 tsu(VDV-PCLK) Setup time, VD valid before PCLK edge 3 ns
10 th(PCLK-VDV) Hold time, VD valid after PCLK edge 2 ns
11 tsu(CAM_WEN_FIELDV-PCLK) Setup time, CAM_WEN_FIELD valid before PCLK edge 3 ns
12 th(CAM_WEN_FIELDV-PCLK) Hold time, C_WEN_FIELD valid after PCLK edge 2 ns
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PCLK
(PositiveEdgeClocking)
PCLK
(NegativeEdgeClocking)
7,9
HD/VD
CI[7:0]/YI[7:0]/
CCD[13:0]
8,10
11
12
5
6
CAM_WEN_FIELD
PCLK
(PositiveEdgeClocking)
15 16
23 24
CI[7:0]/YI[7:0]/
CCD[13:0]
CAM_WEN_FIELD
PCLK
(PositiveEdgeClocking)
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Figure 5-24. VPFE (CCD) Slave Mode Input Data Timing
Table 5-19. Timing Requirements for VPFE (CCD) Master Mode(1) (see Figure 5-25)
DM335
NO. PARAMETER UNIT
MIN MAX
15 tsu(CCDV-PCLK) Setup time, CCD valid before PCLK edge 3 ns
16 th(PCLK-CCDV) Hold time, CCD valid after PCLK edge 2 ns
23 tsu(CAM_WEN_FIELDV-PCLK) Setup time, CAM_WEN_FIELD valid before PCLK edge 3 ns
24 th(PCLK-CAM_WEN_FIELDV) Hold time, CAM_WEN_FIELD valid after PCLK edge 2 ns
(1) The VPFE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode the
rising edge of PCLK is referenced. When in negative edge clocking mode the falling edge of PCLK is referenced.
Figure 5-25. VPFE (CCD) Master Mode Input Data Timing
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PCLK
(PositiveEdgeClocking)
18
20
HD
VD
PCLK
(NegativeEdgeClocking)
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Table 5-20. Switching Characteristics Over Recommended Operating Conditions for VPFE (CCD) Master
Mode (see Figure 5-26)
DM335
NO. PARAMETER UNIT
MIN MAX
18 td(PCLKL-HDIV) Delay time, PCLK edge to HD invalid 3 11 ns
20 td(PCLKL-VDIV) Delay time, PCLK edge to VD invalid 3 11 ns
Figure 5-26. VPFE (CCD) Master Mode Control Output Data Timing
5.9.2 Video Processing Back-End (VPBE)
The Video Processing Back-End of VPBE module is comprised of the On Screen Display (OSD) module
and the Video Encoder / Digital LCD Controller (VENC/DLCD).
5.9.2.1 On-Screen Display (OSD)
The primary function of the OSD module is to gather and blend video data and display/bitmap data and
then pass it to the Video Encoder (VENC) in YCbCr format. The video and display data is read from
external DDR2/mDDR memory. The OSD is programmed via control and parameter registers. The
following are the primary features that are supported by the OSD.
• Support for two video windows and two OSD bitmapped windows that can be displayed simultaneously
(VIDWIN0/VIDWIN1 and OSDWIN0/OSDWIN1).
• Video windows supports YCbCr data in 422 format from external memory, with the ability to
interchange the order of the CbCr component in the 32-bit word
• OSD bitmap windows support ½/4/8 bit width index data of color palette
• In addition one OSD bitmap window at a time can be configured to one of the following:
– YUV422 (same as video data)
– RGB format data in 16-bit mode (R=5bit, G=6bit, B=5bit)
– 24-bit mode (each R/G/B=8bit) with pixel level blending with video windows
• Programmable color palette with the ability to select between a RAM/ROM table with support for 256
colors.
• Support for 2 ROM tables, one of which can be selected at a given time
• Separate enable/disable control for each window
• Programmable width, height, and base starting coordinates for each window
• External memory address and offset registers for each window
• Support for x2 and x4 zoom in both the horizontal and vertical direction
• Pixel-level blending/transparency/blinking attributes can be defined for OSDWIN0 when OSDWIN1 is
configured as an attribute window for OSDWIN0.
• Support for blinking intervals to the attribute window
• Ability to select either field/frame mode for the windows (interlaced/progressive)
• An eight step blending process between the bitmap and video windows
• Transparency support for the bitmap and video data (when a bitmap pixel is zero, there will be no
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blending for that corresponding video pixel)
• Ability to resize from VGA to NTSC/PAL (640x480 to 720x576) for both the OSD and video windows
• Horizontal rescaling x1.5 is supported
• Support for a rectangular cursor window and a programmable background color selection.
• The width, height, and color of the cursor is selectable
• The display priority is: Rectangular-Cursor > OSDWIN1 > OSDWIN0 > VIDWIN1 > VIDWIN0 >
background color
• Support for attenuation of the YCbCr values for the REC601 standard.
The following restrictions exist in the OSD module.
• If the vertical resize filter is enabled for either of the video windows, the maximum horizontal window
dimension cannot be greater than 720 currently. This is due to the limitation in the size of the line
memory.
• It is not possible to use both of the CLUT ROMs at the same time. However, a window can use RAM
while another uses ROM.
5.9.2.2 Video Encoder / Digital LCD Controller (VENC/DLCD)
The VENC/DLCD consists of three major blocks; a) the video encoder that generates analog video output,
b) the digital LCD controller that generates digital RGB/YCbCr data output and timing signals, and c) the
timing generator.
The video encoder for analog video supports the following features:
• Master Clock Input - 27 MHz (x2 Upsampling)
• Programmable Timing Generator
• SDTV Support
– Composite NTSC-M, PAL-B/D/G/H/I
– Non-Interlace option
– CGMS/WSS
– Line 21 Closed Caption Data Encoding
– Chroma Low Pass Filter 1.5MHz/3MHz
– Programmable SC-H phase
• 10-bit Over-Sampling D/A Converter (27MHz)
• Internal analog video buffer
• Optional 7.5% Pedestal
• 16-235/0-255 Input Amplitude Selectable
• Programmable Luma Delay
• Master/Slave Operation
• Internal Color Bar Generation (75%)
The digital LCD controller supports the following features:
• Programmable DCLK
• Programmable Timing Generator
• Various Output Format
– YCbCr 16bit
– YCbCr 8bit
– ITU-R BT. 656
– Parallel RGB 16-bit/18-bit
– Serial 8-bit RGB
• Low Pass Filter for Digital RGB Output
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1
PCLK
2
3
7
5
64
8
EXTCLK
4
8
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• Master/Slave Operation
• Internal Color Bar Generation (100%/75%)
• YUV/RGB modes support HDTV output (720p/1080i) with 74.25 MHz external clock input
5.9.2.3 VPBE Electrical Data/Timing
Table 5-21. Timing Requirements for VPBE CLK Inputs (see Figure 5-27)
DM335
NO. PARAMETER UNIT
MIN MAX
1 tc(PCLK) Cycle time, PCLK(1) 13.33 160 ns
2 tw(PCLKH) Pulse duration, PCLK high 5.7 ns
3 tw(PCLKL) Pulse duration, PCLK low 5.7 ns
4 tt(PCLK) Transition time, PCLK 3 ns
5 tc(EXTCLK) Cycle time, EXTCLK 13.33 160 ns
6 tw(EXTCLKH) Pulse duration, EXTCLK high 5.7 ns
7 tw(EXTCLKL) Pulse duration, EXTCLK low 5.7 ns
8 tt(EXTCLK) Transition time, EXTCLK 3 ns
(1) For timing specifications relating to PCLK see Table 5-17 ,Timing Requirements for VPFE PCLK Master/Slave Mode.
Figure 5-27. VPBE PCLK and EXTCLK Timing
Table 5-22. Timing Requirements for VPBE Control Input With Respect to PCLK and EXTCLK(1) (2) (3) (see
Figure 5-28)
DM335
NO. PARAMETER UNIT
MIN MAX
9 tsu(VCTLV-VCLKIN) Setup time, VCTL valid before VCLKIN edge 2 ns
10 th(VCLKIN-VCTLV) Hold time, VCTL valid after VCLKIN edge 1 ns
(1) The VPBE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the
rising edge of VCLKIN is referenced. When in negative edge clocking mode, the falling edge of VCLKIN is referenced.
(2) VCTL = HSYNC, VSYNC, and FIELD
(3) VCLKIN = PCLK or EXTCLK
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VCLKIN(A)
(Positive Edge Clocking)
9
VCLKIN(A)
(Negative Edge Clocking)
10
VCTL(B)
A. VCLKIN=PCLKorEXTCLK
B. VCTL=HSYNC,VSYNC,andFIELD
VCLKIN(A)
(Positive Edge Clocking)
13
VCLKIN(A)
(Negative Edge Clocking)
11
VCTL(B)
A. VCLKIN=PCLKorEXTCLK
B. VCTL=HSYNC,VSYNC,FIELD,andLCD_OE
C. VDATA=COUT[7:0],YOUT[7:0],R[7:3],G[7:2],andB[7:3]
VDATA(C)
14
12
TMS320DM335
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Figure 5-28. VPBE Input Timing With Respect to PCLK and EXTCLK
Table 5-23. Switching Characteristics Over Recommended Operating Conditions for VPBE Control and
Data Output With Respect to PCLK and EXTCLK(1) (2) (3) (see Figure 5-29)
DM335
NO. PARAMETER UNIT
MIN MAX
11 td(VCLKIN-VCTLV) Delay time, VCLKIN edge to VCTL valid 13.3 ns
12 td(VCLKIN-VCTLIV) Delay time, VCLKIN edge to VCTL invalid 2 ns
13 td(VCLKIN-VDATAV) Delay time, VCLKIN edge to VDATA valid 13.3 ns
14 td(VCLKIN-VDATAIV) Delay time, VCLKIN edge to VDATA invalid 2 ns
(1) The VPBE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the
rising edge of VCLKIN is referenced. When in negative edge clocking mode, the falling edge of VCLKIN is referenced.
(2) VCLKIN = PCLK or EXTCLK
(3) VCTL = HSYNC, VSYNC, FIELD, and LCD_OE
Figure 5-29. VPBE Control and Data Output With Respect to PCLK and EXTCLK
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VCLK
(Positive Edge
Clocking)
VCLK
(Negative Edge
Clocking)
17
VCTL(B)
VDATA(C)
19
1822
21
23 24
25 26
VCLKIN(A)
A. VCLKIN=PCLKorEXTCLK
B. VCTL=HSYNC,VSYNC,FIELD,andLCD_OE
C. VDATA=COUT[7:0],YOUT[7:0],R[7:3],G[7:2],andB[7:3]
20
20
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Table 5-24. Switching Characteristics Over Recommended Operating Conditions for VPBE Control and
Data Output With Respect to VCLK(1) (2) (see Figure 5-30)
DM335
NO. PARAMETER UNIT
MIN MAX
17 tc(VCLK) Cycle time, VCLK 13.33 160 ns
18 tw(VCLKH) Pulse duration, VCLK high 5.7 ns
19 tw(VCLKL) Pulse duration, VCLK low 5.7 ns
20 tt(VCLK) Transition time, VCLK 3 ns
21 td(VCLKINH-VCLKH) Delay time, VCLKIN high to VCLK high 2 12 ns
22 td(VCLKINL-VCLKL) Delay time, VCLKIN low to VCLK low 2 12 ns
23 td(VCLK-VCTLV) Delay time, VCLK edge to VCTL valid 4 ns
24 td(VCLK-VCTLIV) Delay time, VCLK edge to VCTL invalid 0 ns
25 td(VCLK-VDATAV) Delay time, VCLK edge to VDATA valid 4 ns
26 td(VCLK-VDATAIV) Delay time, VCLK edge to VDATA invalid 0 ns
(1) The VPBE may be configured to operate in either positive or negative edge clocking mode. When in positive edge clocking mode, the
rising edge of VCLK is referenced. When in negative edge clocking mode, the falling edge of VCLK is referenced.
(2) VCLKIN = PCLK or EXTCLK. For timing specifications relating to PCLK, see Table 5-17 ,Timing Requirements for VPFE PCLK
Master/Slave Mode.
Figure 5-30. VPBE Control and Data Output Timing With Respect to VCLK
5.9.2.4 DAC and Video Buffer Electrical Data/Timing
The DAC and video buffer can be configured in a DAC only configuration or in a DAC and video buffer
configuration. In the DAC only configuration the internal video buffer is not used and an external video
buffer is attached to the DAC. In the DAC and video buffer configuration, the DAC and internal video
buffer are both used and a TV cable may be attached directly to the output of the video buffer. See
Figure 5-31 and Figure 5-32 for recommenced circuits for each configuration.
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DIN<9:0>
MSB
LSB
DACDigitalInput
ExampleforExternalCircuit
Iout[mA]
1.4mA
0
DACOutputCurrent
CBG
0.1 Fm
VREF
V
ideoDAC
RBIAS
2550W
IBIAS
RLOAD
499W
IOUT
Buffer
VFB TVOUT
TMS320DM335
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A. Connect IOUT to a high-impedance video buffer device.
B. Place capacitors and resistors as close as possible to the DM335.
C. Configure the VDAC_CONFIG register in the system control module as follows: DINV = 0, PWD_GBZ = 1,
PWD_VBUFZ = 0, ACCUP_EN = X. See the TMS320DM335 Digital Media System-on-Chip (DMSoC) ARM
Subsystem Reference Guide (literature number SPRUFX7) and the TMS320DM335 Digital Media System-on-Chip
(DMSoC) Video Processing Back End (VPBE) Reference Guide (literature number SPRUFX9) for more information
on VDAC_CONFIG.
Figure 5-31. DAC Only Application Example
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DIN<9:0>
DACDigitalInput
CBG
0.1 Fm
VREF
VideoDACandBuffer
RBIAS
2550 Ω
IBIAS
Rfb = 1000 Ω
IOUT VFB TVOUT
Rout =1070 Ω
TVmonitor
TVOUT[V]
VideoBufferOutputVoltage
MSB
LSB VOL(VIDBUF)
VOH(VIDBUF)
0
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A. Place capacitors and resistors as close as possible to the DM335.
B. You must use the circuit shown in this diagram. Also you must configure the VDAC_CONFIG register in the System
Control module as follows: TRESB4R4 = 0x3, TRESB4R2 = 0x8, TRESB4R1 = 0x8, TRIMBITS = 0x34, PWD_BGZ =
1 (power up VREF), SPEED = 1 (faster), TVINT = don't care, PWD_VBUFZ = 1 (power up video buffer), VREFSET =
don't care, ACCUP_EN = 0 (no A/C coupling), DINV = 1 (invert). See the TMS320DM335 Digital Media
System-on-Chip (DMSoC) ARM Subsystem Reference Guide (literature number SPRUFX7) and the TMS320DM335
Digital Media System-on-Chip (DMSoC) Video Processing Back End (VPBE) Reference Guide (literature number
SPRUFX9) for more information on the VDAC_CONFIG register and Video Buffer.
C. For proper TVOUT voltage, you must connect the pin TVOUT directly to the TV. No A/C coupling capacitor or
termination resistor is necessary on your DM335 board. Also, it is assumed that the TV has no internal A/C coupling
capacitor but does have an internal termination resistor, as shown in this diagram. TVOUT voltage will range from
VOL(VIDBUF) to VOH(VIDBUF). See Section 4.3 for the voltage specifications.
Figure 5-32. DAC With Buffer Circuit
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tr
tf
VCRS 90%VOH
10%VOL
USB_DM
USB_DP
tper − tjr
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5.10 USB 2.0
The DM335 USB2.0 peripheral supports the following features:
• USB 2.0 peripheral at speeds high speed (HS: 480 Mb/s) and full speed (FS: 12 Mb/s)
• USB 2.0 host at speeds HS, FS, and low speed (LS: 1.5 Mb/s)
• All transfer modes (control, bulk, interrupt, and isochronous)
• Four Transmit (TX) and four Receive (RX) endpoints in addition to endpoint 0
• FIFO RAM
– 4K bytes shared by all endpoints.
– Programmable FIFO size
• Includes a DMA sub-module that supports four TX and four RX channels of CPPI 3.0 DMAs
• RNDIS mode for accelerating RNDIS type protocols using short packet termination over USB
• USB OTG extensions, i.e. session request protocol (SRP) and host negotiation protocol (HNP)
The DM335 USB2.0 peripheral does not support the following features:
• On-chip charge pump
• High bandwidth ISO mode is not supported (triple buffering)
• RNDIS mode acceleration for USB sizes that are not multiples of 64 bytes
• Endpoint max USB packet sizes that do not conform to the USB 2.0 spec (for FS/LS: 8, 16, 32, 64,
and 1023 are defined; for HS: 64, 128, 512, and 1024 are defined)
5.10.1 USB2.0 Electrical Data/Timing
Table 5-25. Switching Characteristics Over Recommended Operating Conditions for USB2.0 (see
Figure 5-33)
DM335
LOW SPEED FULL SPEED HIGH SPEED(1)
NO. PARAMETER UNIT
1.5 Mbps 12 Mbps 480 Mbps
MIN MAX MIN MAX MIN MAX
1 tr(D) Rise time, USB_DP and USB_DM signals(2) 75 300 4 20 0.5 ns
2 tf(D) Fall time, USB_DP and USB_DM signals(2) 75 300 4 20 0.5 ns
3 tfrfm Rise/Fall time, matching(3) 80 125 90 111.11 %
4 VCRS Output signal cross-over voltage(2) 1.3 2 1.3 2 V
5 tjr(source)NT Source (Host) Driver jitter, next transition 2 2 ns
tjr(FUNC)NT Function Driver jitter, next transition 25 2 ns
6 tjr(source)PT Source (Host) Driver jitter, paired transition(4) 1 1 ns
tjr(FUNC)PT Function Driver jitter, paired transition 10 1 ns
7 tw(EOPT) Pulse duration, EOP transmitter 1250 1500 160 175 ns
8 tw(EOPR) Pulse duration, EOP receiver 670 82 ns
9 t(DRATE) Data Rate 1.5 12 480 Mb/s
10 ZDRV Driver Output Resistance – – 28 49.5 40.5 49.5 Ω
(1) For more detailed specification information, see the Universal Serial Bus Specification Revision 2.0, Chapter 7. Electrical.
(2) Low Speed: CL= 200 pF, Full Speed: CL= 50 pF, High Speed: CL= 50 pF
(3) tfrfm = (tr/tf) x 100. [Excluding the first transaction from the Idle state.]
(4) tjr = tpx(1) - tpx(0)
Figure 5-33. USB2.0 Integrated Transceiver Interface Timing
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VSS_USB_REF USB_R1
USB
10K ±1%Ω
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Figure 5-34. USB Reference Resistor Routing
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5.11 Universal Asynchronous Receiver/Transmitter (UART)
The DM335 contains 3 separate UART modules (1 with hardware flow control). These modules performs
serial-to-parallel conversion on data received from a peripheral device or modem, and parallel-to-serial
conversion on data received from the CPU. Each UART also includes a programmable baud rate
generator capable of dividing the 24MHz reference clock by divisors from 1 to 65,535 to produce a 16 x
clock driving the internal logic. The UART modules support the following features:
• Frequency pre-scale values from 1 to 65,535 to generate appropriate baud rates
• 16-byte storage space for both the transmitter and receiver FIFOs
• Unique interrupts, one for each UART
• Unique EDMA events, both received and transmitted data for each UART
• 1, 4, 8, or 14 byte selectable receiver FIFO trigger level for autoflow control and DMA
• Programmable auto-rts and auto-cts for autoflow control (supported on UART2)
• Programmable serial data formats
– 5, 6, 7, or 8-bit characters
– Even, odd, or no parity bit generation and detection
– 1, 1.5, or 2 stop bit generation
• False start bit detection
• Line break generation and detection
• Internal diagnostic capabilities
– Loopback controls for communications link fault isolation
– Break, parity, overrun, and framing error simulation
• Modem control functions: CTS, RTS (supported on UART2)
5.11.1 UART Electrical Data/Timing
Table 5-26. Timing Requirements for UARTx Receive (see Figure 5-35)
DM335
NO. UNIT
MIN MAX
4 tw(URXDB) Pulse duration, receive data bit (RXDn) 0.99U(1) 1.05U(1) ns
5 tw(URXSB) Pulse duration, receive start bit 0.99U(1) 1.05U(1) ns
(1) U = UART baud time = 1/programmed baud rate. ote>
Table 5-27. Switching Characteristics Over Recommended Operating Conditions for UARTx Transmit
(see Figure 5-35)
DM335
NO. PARAMETER UNIT
MIN MAX
UART0/1 Maximum programmable baud rate 1.5
1 f(baud) MHz
UART2 Maximum programmable baud rate 5
2 tw(UTXDB) Pulse duration, transmit data bit (TXDn) U - 2(1) U + 2(1) ns
3 tw(UTXSB) Pulse duration, transmit start bit U - 2(1) U + 2(1) ns
(1) U = UART baud time = 1/programmed baud rate.
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3
2
Start
Bit
DataBits
UART_TXDn
UART_RXDn
5
DataBits
Bit
Start
4
TMS320DM335
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Figure 5-35. UART Transmit/Receive Timing
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SPIx_CLK
(ClockPolarity=0)
1
2
3
SPIx_CLK
(ClockPolarity=1)
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5.12 Serial Port Interface (SPI)
The DM335 contains 3 separate SPI modules. These modules provide a programmable length shift
register which allows serial communication with other SPI devices through a 3 or 4 wire interface (Clock,
Data In, Data Out, and Enable). The SPI supports the following features:
• Master mode operation
• 2 chip selects for interfacing to multiple slave SPI devices.
• 3 or 4 wire interface (Clock, Data In, Data Out, and Enable)
• Unique interrupt for each SPI port
• Separate DMA events for SPI Receive and Transmit
• 16-bit shift register
• Receive buffer register
• Programmable character length (2 to 16 bits)
• Programmable SPI clock frequency range
• 8-bit clock prescaler
• Programmable clock phase (delay or no delay)
• Programmable clock polarity
The SPI modules do not support the following features:
• Slave mode. Only Master mode is supported in DM335 (Master mode means that DM335 provides the
serial clock).
• GPIO mode. GPIO functionality is supported by the GIO modules for those SPI pins that are
multiplexed with GPIO signals.
5.12.1 SPI Electrical Data/Timing
Table 5-28. Timing Requirements for SPI (All Modes)(1) (see Figure 5-36)
DM335
NO. UNIT
MIN MAX
1 tc(CLK) Cycle time, SPI_CLK 37.037 ns ns
2 tw(CLKH) Pulse duration, SPI_CLK high (All Master Modes) 0.45*T 0.55*T ns
3 tw(CLKL) Pulse duration, SPI_CLK low (All Master Modes 0.45*T 0.55*T ns
(1) T = tc(CLK) = SPI_CLK period is equal to the SPI module clock divided by a configurable divider.
Figure 5-36. SPI_CLK Timing
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SPI_CLK
(ClockPolarity=0)
SPI_CLK
(ClockPolarity=1)
SPI_DI
(Input)
SPI_DO
(Output)
4
MSBIN DATA LSBIN
LSBOUTMSBOUT DATA
9
10
8
6
5
7
SPI_EN
11
TMS320DM335
SPRS528C–JULY 2008–REVISED JUNE 2010
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SPI Master Mode Timings (Clock Phase = 0)
Table 5-29. Timing Requirements for SPI Master Mode [Clock Phase = 0] (1)(see Figure 5-37)
DM335
NO. UNIT
MIN MAX
Setup time, SPI_DI (input) valid before SPI_CLK (output)
4 tsu(DIV-CLKL) Clock Polarity = 0 .5P + 3 ns
falling edge
Setup time, SPI_DI (in put) valid before SPI_CLK (output)
5 tsu(DIV-CLKH) Clock Polarity = 1 .5P + 3 ns
rising edge
Hold time, SPI_DI (input) valid after SPI_CLK (output) falling
6 th(CLKL-DIV) Clock Polarity = 0 .5P + 3 ns
edge
Hold time, SPI_DI (input) valid after SPI_CLK (output) rising
7 th(CLKH-DIV) Clock Polarity = 1 2.5P + 3 ns
edge
(1) P = 1/SYSCLK2 in nanoseconds (ns). For example, if the SYSCLK2 frequency is 216 MHz, use P = 4.63 ns. See Section 3.5 ,Device
Clocking, for more information on the supported clock configurations of the DM335.
Table 5-30. Switching Characteristics Over Recommended Operating Conditions for SPI Master Mode
[Clock Phase = 0] (see Figure 5-37)
DM335
NO. PARAMETER UNIT
MIN MAX
Delay time, SPI_CLK (output) rising edge to SPI_DO
8 td(CLKH-DOV) Clock Polarity = 0 -4 5 ns
(output) transition
Delay time, SPI_CLK (output) falling edge to SPI_DO
9 td(CLKL-DOV) Clock Polarity = 1 -4 5 ns
(output) transition
Delay time, SPI_EN[1:0] (output) falling edge to first SPI_CLK (output) rising or falling
10 td(ENL-CLKH/L) 2P(1) (1) ns
edge P+.5C(2
11 td(CLKH/L-ENH) Delay time, SPI_CLK (output) rising or falling edge to SPI_EN[1:0] (output) rising edge (2) ns
)
(1) The delay time can be adjusted using the SPI module register C2TDELAY. See the TMS320DM335 Digital Media System-on-Chip
(DMSoC) Serial Peripheral Interface (SPI) Reference Guide ( literature number SPRUFY1).
(2) The delay time can be adjusted using the SPI module register T2CDELAY. See the TMS320DM335 Digital Media System-on-Chip
(DMSoC) Serial Peripheral Interface (SPI) Reference Guide ( literature number SPRUFY1).
Figure 5-37. SPI Master Mode External Timing (Clock Phase = 0)
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SPI_CLK
(ClockPolarity=0)
SPI_CLK
(ClockPolarity=1)
SPI_DI
(Input)
SPI_DO
(Output)
13
MSBIN DATA LSBIN
LSBOUTMSBOUT DATA
17
15
14 16
SPI_EN
19
18
TMS320DM335
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SPI Master Mode Timings (Clock Phase = 1)
Table 5-31. Timing Requirements for SPI Master Mode [Clock Phase = 1] (see Figure 5-38)
DM335
NO. UNIT
MIN MAX
Setup time, SPI_DI (input) valid before SPI_CLK (output)
13 tsu(DIV-CLKL) Clock Polarity = 0 .5P + 3 ns
rising edge
Setup time, SPI_DI (in put) valid before SPI_CLK (output)
14 tsu(DIV-CLKH) Clock Polarity = 1 .5P + 3 ns
falling edge
Hold time, SPI_DI (input) valid after SPI_CLK (output) rising
15 th(CLKL-DIV) Clock Polarity = 0 .5P + 3 ns
edge
Hold time, SPI_DI (input) valid after SPI_CLK (output) falling
16 th(CLKH-DIV) Clock Polarity = 1 .5P + 3 ns
edge
Table 5-32. Switching Characteristics Over Recommended Operating Conditions for SPI Master Mode
[Clock Phase = 1] (see Figure 5-38)
DM335
NO. PARAMETER UNIT
MIN MAX
Delay time, SPI_CLK (output) falling edge to SPI_DO
17 td(CLKL-DOV) Clock Polarity = 0 -4 5 ns
(output) transition
Delay time, SPI_CLK (output) rising edge to SPI_DO
18 td(CLKH-DOV) Clock Polarity = 1 -4 5 ns
(output) transition
Delay time, SPI_EN[1:0] (output) falling edge to first SPI_CLK (output) rising or falling 2P+.5C
19 td(ENL-CLKH/L) (1) ns
edge (1)
20 td(CLKL/H-DOHz) Delay time, SPI_CLK (output) falling or rising edge to SPI_DO (output) high impedance P(2) (2) ns
(1) The delay time can be adjusted using the SPI module register C2TDELAY. See the TMS320DM335 Digital Media System-on-Chip
(DMSoC) Serial Peripheral Interface (SPI) Reference Guide ( literature number SPRUFY1).
(2) The delay time can be adjusted using the SPI module register T2CDELAY. See the TMS320DM335 Digital Media System-on-Chip
(DMSoC) Serial Peripheral Interface (SPI) Reference Guide ( literature number SPRUFY1).
Figure 5-38. SPI Master Mode External Timing (Clock Phase = 1)
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5.13 Inter-Integrated Circuit (I2C)
The inter-integrated circuit (I2C) module provides an interface between DM335 and other devices
compliant with Philips Semiconductors Inter-IC bus (I2C-bus) specification version 2.1 and connected by
way of an I2C-bus. External components attached to this 2-wire serial bus can transmit/receive up to 8-bit
data to/from the DM335 through the I2C module.
The I2C port supports:
• Compatible with Philips I2C Specification Revision 2.1 (January 2000)
• Fast Mode up to 400 Kbps (no fail-safe I/O buffers)
• Noise Filter to Remove Noise 50 ns or less
• Seven- and Ten-Bit Device Addressing Modes
• Master (Transmit/Receive) and Slave (Transmit/Receive) Functionality
• Events: DMA, Interrupt, or Polling
• Slew-Rate Limited Open-Drain Output Buffers
For more detailed information on the I2C peripheral, see the TMS320DM335 Digital Media
System-on-Chip (DMSoC) Inter-Integrated Circuit (I2C) Peripheral Reference Guide (literature number
SPRUFY3).
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10
8
4
3
7
12
5
614
2
3
13
Stop Start Repeated
Start
Stop
SDA
SCL
1
11 9
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5.13.1 I2C Electrical Data/Timing
5.13.1.1 Inter-Integrated Circuits (I2C) Timing
Table 5-33. Timing Requirements for I2C Timings(1) (see Figure 5-39)
DM335
STANDARD
NO. FAST MODE UNIT
MODE
MIN MAX MIN MAX
1 tc(SCL) Cycle time, SCL 10 2.5 ms
Setup time, SCL high before SDA low (for a repeated START
2 tsu(SCLH-SDAL) 4.7 0.6 ms
condition)
Hold time, SCL low after SDA low (for a START and a repeated
3 th(SCLL-SDAL) 4 0.6 ms
START condition)
4 tw(SCLL) Pulse duration, SCL low 4.7 1.3 ms
5 tw(SCLH) Pulse duration, SCL high 4 0.6 ms
6 tsu(SDAV-SCLH) Setup time, SDA valid before SCL high 250 100(2) ns
7 th(SDA-SCLL) Hold time, SDA valid after SCL low (For I2C bus devices) 0(3) 0(3) 0.9(4) ms
Pulse duration, SDA high between STOP and START
8 tw(SDAH) 4.7 1.3 ms
conditions 20 + 0.1Cb
9 tr(SDA) Rise time, SDA 1000 300 ns
(5)
20 + 0.1Cb
10 tr(SCL) Rise time, SCL 1000 300 ns
(5)
20 + 0.1Cb
11 tf(SDA) Fall time, SDA 300 300 ns
(5)
20 + 0.1Cb
12 tf(SCL) Fall time, SCL 300 300 ns
(5)
13 tsu(SCLH-SDAH) Setup time, SCL high before SDA high (for STOP condition) 4 0.6 ms
14 tw(SP) Pulse duration, spike (must be suppressed) 0 50 ns
15 Cb(5) Capacitive load for each bus line 400 400 pF
(1) The I2C pins SDA and SCL do not feature fail-safe I/O buffers. These pins could potentially draw current when the device is powered
down.
(2) A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tsu(SDA-SCLH)≥250 ns must then be
met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch
the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tsu(SDA-SCLH)= 1000 + 250 = 1250 ns
(according to the Standard-mode I2C-Bus Specification) before the SCL line is released.
(3) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
(4) The maximum th(SDA-SCLL) has only to be met if the device does not stretch the low period [tw(SCLL)] of the SCL signal.
(5) Cb= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
Figure 5-39. I2C Receive Timings
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19
18
22
20
21
17
18
28
Stop Start Repeated
Start
Stop
SDA
SCL
16
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Table 5-34. Switching Characteristics for I2C Timings(1) (see Figure 5-40)
DM335
STANDARD
NO. PARAMETER FAST MODE UNIT
MODE
MIN MAX MIN MAX
16 tc(SCL) Cycle time, SCL 10 2.5 ms
17 td(SCLH-SDAL) Delay time, SCL high to SDA low (for a repeated START condition) 4.7 0.6 ms
Delay time, SDA low to SCL low (for a START and a repeated
18 td(SDAL-SCLL) 4 0.6 ms
START condition)
19 tw(SCLL) Pulse duration, SCL low 4.7 1.3 ms
20 tw(SCLH) Pulse duration, SCL high 4 0.6 ms
21 td(SDAV-SCLH) Delay time, SDA valid to SCL high 250 100 ns
22 tv(SCLL-SDAV) Valid time, SDA valid after SCL low (For I2C devices) 0 0 0.9 ms
23 tw(SDAH) Pulse duration, SDA high between STOP and START conditions 4.7 1.3 ms
28 td(SCLH-SDAH) Delay time, SCL high to SDA high (for STOP condition) 4 0.6 ms
29 CpCapacitance for each I2C pin 10 10 pF
(1) Cb= total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times are allowed.
CAUTION
The DM335 I2C pins use a standard ±4-mA LVCMOS buffer, not the slow I/OP buffer
defined in the I2C specification. Series resistors may be necessary to reduce noise at
the system level.
Figure 5-40. I2C Transmit Timings
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5.14 Audio Serial Port (ASP)
DM335 includes two separate ASP controllers. The primary use for the audio serial port (ASP) is for audio
interface purposes. The primary audio modes that are supported by the ASP are the AC97 and IIS modes.
In addition to the primary audio modes, the ASP supports general serial port receive and transmit
operation, but is not intended to be used as a high-speed interface. The ASP is backward compatible with
other TI ASPs. The ASP supports the following features:
• Full-duplex communication
• Double-buffered data registers, which allow a continuous data stream
• Independent framing and clocking for receive and transmit
• External shift clock generation or an internal programmable frequency shift clock
• Double-buffered data registers, which allow a continuous data stream
• Independent framing and clocking for receive and transmit
• Direct interface to industry-standard codecs, analog interface chips (AICs), and other serially
connected analog-to-digital (A/D) and digital-to-analog (D/A) devices
• Direct interface to AC97 compliant devices (the necessary multiphase frame synchronization capability
is provided)
• Direct interface to IIS compliant devices
• Direct interface to SPI protocol in master mode only
• A wide selection of data sizes, including 8, 12, 16, 20, 24, and 32 bits
•m-Law and A-Law companding
• 8-bit data transfers with the option of LSB or MSB first
• Programmable polarity for both frame synchronization and data clocks
• Highly programmable internal clock and frame generation
For more detailed information on the ASP peripheral, see the TMS320DM335 Digital Media
System-on-Chip (DMSoC) Audio Serial Port (ASP) Reference Guide (literature number SPRUFZ3).
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5.14.1 ASP Electrical Data/Timing
5.14.1.1 Audio Serial Port (ASP) Timing
Table 5-35. Timing Requirements for ASP(1) (see Figure 5-41)
DM335
NO. UNIT
MIN MAX
38.5 or
15 tc(CLK) Cycle time, CLK CLK ext ns
2P(2) (3)
19.25 or
16 OTG(CLKS) Pulse duration, CLKR/X high or CLKR/X low CLKS ext P(2) (3) ns
(4)
CLKR int 21
5 tsu(FRH-CKRL) Setup time, external FSR high before CLKR low ns
CLKR ext 6
CLKR int 0
6 th(CKRL-FRH) Hold time, external FSR high after CLKR low ns
CLKR ext 6
CLKR int 21
7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low ns
CLKR ext 6
CLKR int 0
8 th(CKRL-DRV) Hold time, DR valid after CLKR low ns
CLKR ext 6
CLKX int 21
10 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low ns
CLKX ext 6
CLKX int 0
11 th(CKXL-FXH) Hold time, external FSX high after CLKX low ns
CLKX ext 10
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) P = (1/SYSCLK2), where SYSCLK2 is an output clock of PLLC1 (see Section 3.5 ) .
(3) Use which ever value is greater.
(4) The ASP does not have a duty cycle specification, just ensure that the minimum pulse duration specification is met.
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Table 5-36. Switching Characteristics Over Recommended Operating Conditions for ASP(1) (2)
(see Figure 5-41)
DM335
NO. PARAMETER UNIT
MIN MAX
38.5 or
2 tc(CKRX) Cycle time, CLKR/X CLKR/X int 2P(3) (4) ns
(5)
17 td(CLKS-CLKRX) Delay time, CLKS high to internal CLKR/X CLKR/X int 1 24
3 tw(CKRX) Pulse duration, CLKR/X high or CLKR/X low CLKR/X int C - 1(6) C + 1(6) ns
CLKR int 3 25
4 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid ns
CLKR ext 3 25
CLKX int -4 8
9 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid ns
CLKX ext 3 25
CLKX int 12 ns
Disable time, DX high impedance following last data bit from
12 tdis(CKXH-DXHZ) CLKX high CLKX ext 12 ns
CLKX int -5 12 ns
13 td(CKXH-DXV) Delay time, CLKX high to DX valid CLKX ext 3 25 ns
Delay time, FSX high to DX valid FSX int 14
14 td(FXH-DXV) ONLY applies when in data ns
FSX ext 25
delay 0 (XDATDLY = 00b) mode
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) Minimum delay times also represent minimum output hold times.
(3) Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock source. Minimum CLKR/X cycle times
are based on internal logic speed; the maximum usable speed may be lower due to EDMA limitations and AC timing requirements.
(4) P = (1/SYSCLK2), where SYSCLK2 is an output clock of PLLC1 (see Section 3.5 ) .
(5) Use which ever value is greater.
(6) C = H or L
S = sample rate generator input clock = P if CLKSM = 1 (P = 1/SYSCLK2, where SYSCLK2 is an output of PLLC1 (see Section 3.5 ) )
S = sample rate generator input clock = CLKS if CLKSM = 0
H = CLKX high pulse width = (CLKGDV/2 + 1) * S if CLKGDV is even
H = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
L = CLKX low pulse width = (CLKGDV/2) * S if CLKGDV is even
L = (CLKGDV + 1)/2 * S if CLKGDV is odd or zero
CLKGDV should be set appropriately to ensure the ASP bit rate does not exceed the maximum limit (see footnote (3) above).
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Bit(n-1) (n-2) (n-3)
Bit0 Bit(n-1) (n-2) (n-3)
14
11
10
9
3
3
2
8
6
5
4
4
13(A)
13(A)
A. ParameterNo.13appliestothefirstdatabitonly whenXDATDLY ≠0.
CLKR
FSR(int)
FSR(ext)
DR
CLKX
FSX(int)
FSX(ext)
FSX
(XDATDLY=00b)
DX
15
CLKS
16
16
17
17
3
2
3
7
12
TMS320DM335
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Figure 5-41. ASP Timing
Table 5-37. ASP as SPI Timing Requirements
CLKSTP = 10b, CLKXP = 0 (see Figure 5-42)MASTER
NO. PARAMETER UNIT
MIN MAX
M30 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 11 ns
M31 th(CKXL-DRV) Hold time, DR valid after CLKX low 0 ns
Table 5-38. ASP as SPI Switching Characteristics(1) (2)
CLKSTP = 10b, CLKXP = 0 (see Figure 5-42)MASTER
NO. PARAMETER UNIT
MIN MAX
38.5 or
M33 tc(CKX) Cycle time, CLKX ns
2P(1) (3)
M24 td(CKXL-FXH) Delay time, CLKX low to FSX high(2) T – 2 T + 3 ns
M25 td(FXL-CKXH) Delay time, FSX low to CLKX high(4) L1– 2 L1+ 2 ns
M26 td(CKXH-DXV) Delay time, CLKX high to DX valid –2 6 ns
M27 tdis(CKXL-DXHZ) Disable time, DX high impedance following last data bit from CLKX low L1– 3 L1+3 ns
(1) P = (1/SYSCLK2), where SYSCLK2 is an output clock of PLLC1 (see Section 3.5 ) .
(2) T = CLKX period = (1 + CLKGDV) × 2P
L1= CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) × 2P when CLKGDV is even
(3) Use which ever value is greater.
(4) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master
clock (CLKX).
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Bit0 Bit(n-1) (n-2) (n-3) (n-4)
Bit0 Bit(n-1) (n-2) (n-3) (n-4)
M31
M30
M26M27
M25
M24
CLKX
FSX
DX
DR
M33
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Figure 5-42. ASP as SPI: CLKSTP = 10b, CLKXP = 0
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Bit0 Bit(n-1) (n-2) (n-3) (n-4)
Bit0 Bit(n-1) (n-2) (n-3) (n-4)
M39
M36
M38
M37
M35
M34
CLKX
FSX
DX
DR
M40
M42
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Table 5-39. ASP as SPI Timing Requirements
CLKSTP = 11b, CLKXP = 0 MASTER
NO. PARAMETER UNIT
MIN MAX
M39 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 11 ns
M40 th(CKXH-DRV) Hold time, DR valid after CLKX high 1 ns
Table 5-40. ASP as SPI Switching Characteristics(1) (2)
CLKSTP = 11b, CLKXP = 0 (see Figure 5-43)MASTER
NO. PARAMETER UNIT
MIN MAX
38.5 or 2P(1)
M42 tc(CKX) Cycle time, CLKX ns
(3)
M34 td(CKXL-FXH) Delay time, CLKX low to FSX high(4) L1– 2 L1+ 3 ns
M35 td(FXL-CKXH) Delay time, FSX low to CLKX high(5) T – 2 T + 2 ns
M36 td(CKXL-DXV) Delay time, CLKX low to DX valid –2 6 ns
Disable time, DX high impedance following last data bit from
M37 tdis(CKXL-DXHZ) –3 3 ns
CLKX low
M38 td(FXL-DXV) Delay time, FSX low to DX valid H1– 2 H1+ 10 ns
(1) P = (1/SYSCLK2), where SYSCLK2 is an output clock of PLLC1 (see Section 3.5 ) .
(2) T = CLKX period = (1 + CLKGDV) × 2P
L1= CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) × 2P when CLKGDV is even
H1= CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) × 2P when CLKGDV is even
(3) Use which ever value is greater.
(4) FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master ASP
(5) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master
clock (CLKX).
Figure 5-43. ASP as SPI: CLKSTP = 11b, CLKXP = 0
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Bit0 Bit(n-1) (n-2) (n-3) (n-4)
M50
M49
M45
M46
M44
M43
CLKX
FSX
DX
DR
M52
TMS320DM335
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Table 5-41. ASP as SPI Timing Requirements
CLKSTP = 10b, CLKXP = 1 (see Figure 5-44)MASTER
NO. PARAMETER UNIT
MIN MAX
M49 tsu(DRV-CKXH) Setup time, DR valid before CLKX high 11 ns
M50 th(CKXH-DRV) Hold time, DR valid after CLKX high 0 ns
Table 5-42. ASP as SPI Switching Characteristics(1) (2)
CLKSTP = 10b, CLKXP = 1 (see Figure 5-44)MASTER
NO. PARAMETER UNIT
MIN MAX
38.5 or 2P(1)
M52 tc(CKX) Cycle time, CLKX ns
(3)
M43 td(CKXH-FXH) Delay time, CLKX high to FSX high(4) T – 1 T + 3 ns
M44 td(FXL-CKXL) Delay time, FSX low to CLKX low(5) H1– 2 H1+ 2 ns
M45 td(CKXL-DXV) Delay time, CLKX low to DX valid –2 6 ns
Disable time, DX high impedance following last data bit from
M46 tdis(CKXH-DXHZ) H1– 3 H1+ 3 ns
CLKX high
(1) P = (1/SYSCLK2), where SYSCLK2 is an output clock of PLLC1 (see Section 3.5 ) .
(2) T = CLKX period = (1 + CLKGDV) × 2P
H1= CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) × 2P when CLKGDV is even
(3) Use which ever value is greater.
(4) FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master ASP
(5) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master
clock (CLKX).
Figure 5-44. ASP as SPI: CLKSTP = 10b, CLKXP = 1
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Bit0 Bit(n-1) (n-2) (n-3) (n-4)
Bit0 Bit(n-1) (n-2) (n-3) (n-4)
M59
M58
M55
M57
M56
M54M53
CLKX
FSX
DX
DR
M62
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Table 5-43. ASP as SPI Timing Requirements
CLKSTP = 11b, CLKXP = 1 (see Figure 5-45)MASTER
NO. PARAMETER UNIT
MIN MAX
M58 tsu(DRV-CKXL) Setup time, DR valid before CLKX low 11 ns
M59 th(CKXL-DRV) Hold time, DR valid after CLKX low 0 ns
Table 5-44. ASP as SPI Switching Characteristics(1) (2)
CLKSTP = 11b, CLKXP = 1 (see Figure 5-45)MASTER
NO. PARAMETER UNIT
MIN MAX
38.5 or 2P(3)
M62 tc(CKX) Cycle time, CLKX ns
(3)
M53 td(CKXH-FXH) Delay time, CLKX high to FSX high(4) H1– 1 H1+ 3 ns
M54 td(FXL-CKXL) Delay time, FSX low to CLKX low(5) T – 2 T + 2 ns
M55 td(CKXL-DXV) Delay time, CLKX low to DX valid –2 6 ns
Disable time, DX high impedance following last data bit from
M56 tdis(CKXH-DXHZ) – 3 + 3 ns
CLKX high
M57 td(FXL-DXV) Delay time, FSX low to DX valid L1– 1 L1+ 10 ns
(1) P = (1/SYSCLK2), where SYSCLK2 is an output clock of PLLC1 (see Section 3.5 ) .
(2) T = CLKX period = (1 + CLKGDV) × 2P
L1= CLKX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) × 2P when CLKGDV is even
H1= CLKX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) × 2P when CLKGDV is even
(3) Use which ever value is greater.
(4) FSRP = FSXP = 1. As a SPI master, FSX is inverted to provide active-low slave-enable output.
CLKXM = FSXM = 1, CLKRM = FSRM = 0 for master ASP
(5) FSX should be low before the rising edge of clock to enable slave devices and then begin a SPI transfer at the rising edge of the master
clock (CLKX).
Figure 5-45. ASP as SPI: CLKSTP = 11b, CLKXP = 1
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2
4
4
3
TIM_IN
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5.15 Timer
The DM335 contains four software-programmable timers. Timer 0, Timer 1, and Timer 3 (general-purpose
timers) can be programmed in 64-bit mode, dual 32-bit unchained mode, or dual 32-bit chained mode.
Timer 3 supports additional features over the other timers: external clock/event input, period reload, output
event tied to Real Time Out (RTO) module, external event capture, and timer counter register read reset.
Timer 2 is used only as a watchdog timer. Timer 2 is tied to device reset.
• 64-bit count-up counter
• Timer modes:
– 64-bit general-purpose timer mode (Timer 0, 1, 3)
– Dual 32-bit general-purpose timer mode (Timer 0, 1, 3)
– Watchdog timer mode (Timer 2)
• Two possible clock sources:
– Internal clock
– External clock/event input via timer input pins (Timer 3)
• Three possible operation modes:
– One-time operation (timer runs for one period then stops)
– Continuous operation (timer automatically resets after each period)
– Continuous operation with period reload (Timer 3)
• Generates interrupts to the ARM CPU
• Generates sync event to EDMA
• Generates output event to device reset (Timer 2)
• Generates output event to Real Timer Out (RTO) module (Timer 3)
• External event capture via timer input pins (Timer 3)
For more detailed information, see the TMS320DM335 Digital Media System-on-Chip (DMSoC) 64-bit
Timer Reference Guide (literature number SPRUFY0).
5.15.1 Timer Electrical Data/Timing
Table 5-45. Timing Requirements for Timer Input(1) (2) (3) (see Figure 5-46)
DM335
NO. PARAMETER UNIT
MIN MAX
1 tc(TIN) Cycle time, TIM_IN 4P ns
2 tw(TINPH) Pulse duration, TIM_IN high 0.45C 0.55C ns
3 tw(TINPL) Pulse duration, TIM_IN low 0.45C 0.55C ns
0.25C
4 tt(TIN) Transition time, TIM_IN ns
or 10(4)
(1) GPIO000, GPIO001, GPIO002, and GPIO003 can be used as external clock inputs for Timer 3. See the TMS320DM335 Digital Media
System-on-Chip (DMSoC) 64-bit Timer Reference Guide (literature number SPRUFY0).
(2) P = MXI1/CLKIN cycle time in ns. For example, when MXI1/CLKIN frequency is 24 MHz use P = 41.6 ns.
(3) C = TIM_IN cycle time in ns. For example, when TIM_IN frequency is 24 MHz use C = 41.6 ns
(4) Whichever is smaller. C = the period of the applied signal. Maintaining transition times as fast as possible is recommended to improve
noise immunity on input signals.
Figure 5-46. Timer Input Timing
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PWM0/1/2/3
1
3
3
2
TMS320DM335
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5.16 Pulse Width Modulator (PWM)
The DM335 contains 4 separate Pulse Width Modulator (PWM) modules. The pulse width modulator
(PWM) feature is very common in embedded systems. It provides a way to generate a pulse periodic
waveform for motor control or can act as a digital-to-analog converter with some external components.
This PWM peripheral is basically a timer with a period counter and a first-phase duration comparator,
where bit width of the period and first-phase duration are both programmable. The Pulse Width Modulator
(PWM) modules support the following features:
• 32-bit period counter
• 32-bit first-phase duration counter
• 8-bit repeat count for one-shot operation. One-shot operation will produce N + 1 periods of the
waveform, where N is the repeat counter value.
• Configurable to operate in either one-shot or continuous mode
• Buffered period and first-phase duration registers
• One-shot operation triggerable by hardware events with programmable edge transitions. (low-to-high or
high-to-low).
• One-shot operation triggerable by the CCD VSYNC output of the video processing subsystem (VPSS),
which allows any of the PWM instantiations to be used as a CCD timer. This allows the DM335 module
to support the functions provided by the CCD timer feature (generating strobe and shutter signals).
• One-shot operation generates N+1 periods of waveform, N being the repeat count register value
• Configurable PWM output pin inactive state
• Interrupt and EDMA synchronization events
5.16.1 PWM0/1/2/3 Electrical/Timing Data
Table 5-46. Switching Characteristics Over Recommended Operating Conditions for PWM0/1/2/3
Outputs(1) (see Figure 5-47 and Figure 5-48)
DM335
NO. PARAMETER UNIT
MIN MAX
1 tw(PWMH) Pulse duration, PWMx high P ns
2 tw(PWML) Pulse duration, PWMx low P ns
3 tt(PWM) Transition time, PWMx .05P ns
4 td(CCDC-PWMV) Delay time, CCDC(VD) trigger event to PWMx valid 10 ns
(1) P = MXI1/CLKIN cycle time in ns. For example, when MXI1/CLKIN frequency is 24 MHz use P = 41.6 ns.
Figure 5-47. PWM Output Timing
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4
VD(CCDC)
4
4
INVALID
INVALID
INVALID
VALID
VALID
VALID
PWM0
PWM1
PWM2
4
INVALID VALID
PWM3
TMS320DM335
www.ti.com
SPRS528C–JULY 2008–REVISED JUNE 2010
Figure 5-48. PWM Output Delay Timing
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RTO0/1/2/3
1
3
3
2
4
TINT12/TINT34
(Timer3)
4
4
INVALID
INVALID
INVALID
VALID
VALID
VALID
RTO0
4
INVALID VALID
RTO1
RTO2
RTO3
TMS320DM335
SPRS528C–JULY 2008–REVISED JUNE 2010
www.ti.com
5.17 Real Time Out (RTO)
The DM335 Real Time Out (RTO) peripheral supports the following features:
• Four separate outputs
• Trigger on Timer3 event
5.17.1 RTO Electrical/Timing Data
Table 5-47. Switching Characteristics Over Recommended Operating Conditions for RTO Outputs (see
Figure 5-49 and Figure 5-50)
DM335
NO. PARAMETER UNIT
MIN MAX
1 tw(RTOH) Pulse duration, RTOx high P ns
2 tw(RTOL) Pulse duration, RTOx low P ns
3 tt(RTO) Transition time, RTOx .1P ns
4 td(TIMER3-RTOV) Delay time, Timer 3 (TINT12 or TINT34) trigger event to RTOx valid 10 ns
Figure 5-49. RTO Output Timing
Figure 5-50. RTO Output Delay Timing
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5.18 IEEE 1149.1 JTAG
The JTAG(1) interface is used for BSDL testing and emulation of the DM335 device.
The DM335 device requires that both TRST and RESET be asserted upon power up to be properly
initialized. While RESET initializes the device, TRST initializes the device's emulation logic. Both resets
are required for proper operation.
While both TRST and RESET need to be asserted upon power up, only RESET needs to be released for
the device to boot properly. TRST may be asserted indefinitely for normal operation, keeping the JTAG
port interface and device's emulation logic in the reset state.
TRST only needs to be released when it is necessary to use a JTAG controller to debug the device or
exercise the device's boundary scan functionality. Note: TRST is synchronous and must be clocked by
TCK; otherwise, the boundary scan logic may not respond as expected after TRST is asserted.
RESET must be released only in order for boundary-scan JTAG to read the variant field of IDCODE
correctly. Other boundary-scan instructions work correctly independent of current state of RESET.
For maximum reliability, DM335 includes an internal pulldown (PD) on the TRST pin to ensure that TRST
will always be asserted upon power up and the device's internal emulation logic will always be properly
initialized.
JTAG controllers from Texas Instruments actively drive TRST high. However, some third-party JTAG
controllers may not drive TRST high but expect the use of a pullup resistor on TRST.
When using this type of JTAG controller, assert TRST to initialize the device after powerup and externally
drive TRST high before attempting any emulation or boundary scan operations. Following the release of
RESET, the low-to-high transition of TRST must be "seen" to latch the state of EMU1 and EMU0. The
EMU[1:0] pins configure the device for either Boundary Scan mode or Emulation mode. For more detailed
information, see the terminal functions section of this data sheet.
(1) IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
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RTCK
TDO
TDI
4
5
TMS
6
7
TCK
1
23
TMS320DM335
SPRS528C–JULY 2008–REVISED JUNE 2010
www.ti.com
5.18.1 JTAG Test-Port Electrical Data/Timing
Table 5-48. Timing Requirements for JTAG Test Port (see Figure 5-51)
DM335
NO. PARAMETER UNIT
MIN MAX
1 tc(TCK) Cycle time, TCK 20 ns
2 tw(TCKH) Pulse duration, TCK high 8 ns
3 tw(TCKL) Pulse duration, TCK low 8 ns
4 tsu(TDIV-RTCKH) Setup time, TDI valid before RTCK high 10 ns
5 th(RTCKH-TDIIV) Hold time, TDI valid after RTCK high 9 ns
6 tsu(TMSV-RTCKH) Setup time, TMS valid before RTCK high 2 ns
7 th(RTCKH-TMSIV) Hold time, TMS valid after RTCK high 5 ns
Figure 5-51. JTAG Input Timing
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RTCK
TDO
13
8
910
TMS320DM335
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SPRS528C–JULY 2008–REVISED JUNE 2010
Table 5-49. Switching Characteristics Over Recommended Operating Conditions for JTAG Test Port
(see Figure 5-51)
DM335
NO. PARAMETER UNIT
MIN MAX
8 tc(RTCK) Cycle time, RTCK 20 ns
9 tw(RTCKH) Pulse duration, RTCK high 10
10 tw(RTCKL) Pulse duration, RTCK low 10
11 tr(all JTAG outputs) Rise time, all JTAG outputs 1.3 ns
12 tf(all JTAG outputs) Fall time, all JTAG outputs 1.3 ns
0.25*tc(RT
13 td(RTCKL-TDOV) Delay time, TCK low to TDO valid 0 ns
CK)
Figure 5-52. JTAG Output Timing
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6 Mechanical Data
The following table(s) show the thermal resistance characteristics for the PBGA −ZCE mechanical
package. Note that micro-vias are not required. Contact your TI representative for routing
recommendations.
6.1 Thermal Data for ZCE
The following table shows the thermal resistance characteristics for the PBGA −ZCE mechanical
package.
Table 6-1. Thermal Resistance Characteristics (PBGA Package) [ZCE]
NO. °C/W(1)
1 RΘJC Junction-to-case 7.2
2 RΘJB Junction-to-board 11.4
3 RΘJA Junction-to-free air 27.0
4 PsiJT Junction-to-package top 0.1
5 PsiJB Junction-to-board 11.3
(1) The junction-to-case measurement was conducted in a JEDEC defined 2S2P system and will change based on environment as well as
application. For more information, see these three EIA/JEDEC standards:
• EIA/JESD51-2, Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air)
• EIA/JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages
6.2 Packaging Information
The following packaging information and addendum reflect the most current data available for the
designated device(s). This data is subject to change without notice and without revision of this document.
Note that micro-vias are not required for this package.
156 Mechanical Data Copyright © 2008–2010, Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com 2-Jan-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TMS320DM335CZCE216 NRND NFBGA ZCE 337 160 Pb-Free (RoHS) Call TI Level-3-260C-168 HR
TMS320DM335DZCE135 ACTIVE NFBGA ZCE 337 160 Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR
TMS320DM335DZCE216 ACTIVE NFBGA ZCE 337 160 Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR
TMS320DM335DZCEA13 ACTIVE NFBGA ZCE 337 160 Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR
TMS320DM335DZCEA21 ACTIVE NFBGA ZCE 337 160 Pb-Free (RoHS) SNAGCU Level-3-260C-168 HR
TMS320DM335ZCEA135 OBSOLETE NFBGA ZCE 337 TBD Call TI Call TI
TMS320DM335ZCEA216 OBSOLETE NFBGA ZCE 337 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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