80V, 500mA, 3-Phase MOSFET Driver HIP4086, HIP4086A Features The HIP4086 and HIP4086A (referred to as the HIP4086/A) are three phase N-Channel MOSFET drivers. Both parts are specifically targeted for PWM motor control. These drivers have flexible input protocol for driving every possible switch combination. The user can even override the shoot-through protection for switched reluctance applications. * Independently drives 6 N-Channel MOSFETs in three phase bridge configuration The HIP4086/A have a wide range of programmable dead times (0.5ms to 4.5ms) which makes them very suitable for the low frequencies (up to 100kHz) typically used for motor drives. * Bootstrap supply max voltage up to 95VDC with bias supply from 7V to 15V * 1.25A peak turn-off current * User programmable dead time (0.5s to 4.5s) * Bootstrap and optional charge pump maintain the high-side driver bias voltage. The only difference between the HIP4086 and the HIP4086A is that the HIP4086A has the built-in charge pumps disabled. This is useful in applications that require very quiet EMI performance (the charge pumps operate at 10MHz). The advantage of the HIP4086 is that the built-in charge pumps allow indefinitely long on times for the high-side drivers. * Programmable bootstrap refresh time To insure that the high-side driver boot capacitors are fully charged prior to turning on, a programmable bootstrap refresh pulse is activated when VDD is first applied. When active, the refresh pulse turns on all three of the low-side bridge FETs while holding off the three high-side bridge FETs to charge the high-side boot capacitors. After the refresh pulse clears, normal operation begins. * Brushless Motors (BLDC) Another useful feature of the HIP4086/A is the programmable undervoltage set point. The set point range varies from 6.6V to 8.5V. Related Literature * Drives 1000pF load with typical rise time of 20ns and Fall Time of 10ns * Programmable undervoltage set point Applications * 3-phase AC motors * Switched reluctance motor drives * Battery powered vehicles * Battery powered tools AN9642 "HIP4086 3-Phase Bridge Driver Configurations and Applications" "HIP4086EVAL Evaluation Board Application Note" (Coming Soon) 200 VDD CHB RDEL BHB VxHB - VxHS = 10V AHB Speed AHI ALI Controller BHI BLI Brake HIP4086/A AHO BHO Battery 24V...48V CHO CHS BHS AHS CHI CLI VSS ALO BLO CLO OUTPUT CURRENT (A) VDD 150 100 50 0 -60 -40 -20 0 20 40 60 80 100 120 140 160 JUNCTION TEMPERATURE (C) FIGURE 1. TYPICAL APPLICATION June 1, 2011 FN4220.7 1 FIGURE 2. CHARGE PUMP OUTPUT CURRENT CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2011. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. HIP4086, HIP4086A Block Diagram (for clarity, only one phase is shown) If under voltage is active or if DIS is asserted, the high and low-side drivers are turned off. drive enable common with all phases DIS 10 UVLO 8 Charge Pump* 16 xHB EN Adjustable Turn-on Delay xHI 5 VDD 20 VDD Level Shifter 10 nSec delay 17 xHO *The charge pump is permanently disabled in the HIP4086A. Under Voltage Detector delay disable Refresh Pulse RFSH 9 common with all phases 18 xHS VDD common with all phases Adjustable Turn-on Delay xLI 4 21 xLO 6 VSS common with all phases RDEL 7 2 uSec Delay If the voltage on RDEL is less than 100 mV, the turn-on delay timers are disabled and the high and low-side drivers can be turned on simultaneously. 100 mV Truth Table INPUT OUTPUT ALI, BLI, CLI AHI, BHI, CHI UV DIS RDEL ALO, BLO, CLO AHO, BHO, CHO X X X 1 X 0 0 X X 1 X X 0 0 1 X 0 0 >100mV 1 0 0 0 0 0 X 0 1 0 1 0 0 X 0 0 1 0 0 0 <100mV 1 1 NOTE: X signifies that input can be either a "1" or "0". 2 FN4220.7 June 1, 2011 HIP4086, HIP4086A Pin Configuration HIP4086, HIP4086A (PDIP, SOIC) TOP VIEW BHB 1 24 BHO BHI 2 23 BHS BLI 3 22 BLO ALI 4 21 ALO AHI 5 20 VDD VSS 6 19 CLO RDEL 7 18 AHS UVLO 8 17 AHC RFSH 9 16 AHB DIS 10 15 CHS CLI 11 14 CHO CHI 12 13 CHB Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION 16 1 13 AHB BHB CHB (xHB) High-Side Bias Connections. One external bootstrap diode and one capacitor are required for each. Connect cathode of bootstrap diode and positive side of bootstrap capacitor to each xHB pin. 15 23 15 AHS BHS CHS (xHS) High-Side Source Connections. Connect the sources of the High-Side power MOSFETs to these pins. The negative side of the bootstrap capacitors are also connected to these pins. 5 2 12 AHI BHI CHI (xHI) High-Side Logic Level Inputs. Logic at these three pins controls the three high side output drivers, AHO (Pin 17), BHO (Pin 24) and CHO (Pin 14). When xHI is low, xHO is high. When xHI is high, xHO is low. Unless the dead time is disabled by connecting RDEL (Pin 7) to ground, the low side input of each phase will override the corresponding high side input on that phase see "Truth Table" on page 2. If RDEL is tied to ground, dead time is disabled and the outputs follow the inputs with no shoot-thru protection. DIS (Pin 10) also overrides the high side inputs. xHI can be driven by signal levels of 0V to 15V (no greater than VDD). 4 3 11 ALI BLI CLI (xLI) Low-Side Logic Level Inputs. Logic at these three pins controls the three low-side output drivers ALO (Pin 21), BLO (Pin 22) and CLO (Pin 19). If the upper inputs are grounded then the lower inputs control both xLO and xHO drivers, with the dead time set by the resistor at RDEL (Pin 7). DIS (Pin 10) high level input overrides xLI, forcing all outputs low. xLI can be driven by signal levels of 0V to 15V (no greater than VDD). 6 VSS Ground. Connect the sources of the Low-Side power MOSFETs to this pin. 7 RDEL Delay Time Set point. Connect a resistor from this pin to VDD to set timing current that defines the dead time between drivers - see Figure 17. All drivers turn-off with minimal delay, RDEL resistor prevents shoot-through by delaying the turn-on of all drivers. When RDEL is tied to VSS, both upper and lowers can be commanded on simultaneously. While not necessary in most applications, a decoupling capacitor of 0.1F or smaller may be connected between RDEL and VSS. 8 UVLO Under voltage Set point. A resistor can be connected between this pin and VSS to program the under voltage set point, see Figure 18. With this pin not connected, the under voltage disable is typically 6.6V. When this pin is tied to VDD , the under voltage disable is typically 6.2V. 9 RFSH Refresh Pulse Setting. An external capacitor can be connected from this pin to VSS to increase the length of the start up refresh pulse - see Figure 16. If this pin is not connected, the refresh pulse is typically 1.5s. 10 DIS Disable Input. Logic level input that when taken high sets all six outputs low. DIS high overrides all other inputs. With DIS low, the outputs are controlled by the other inputs. DIS can be driven by signal levels of 0V to 15V (no greater than VDD). 3 FN4220.7 June 1, 2011 HIP4086, HIP4086A Pin Descriptions PIN NUMBER SYMBOL DESCRIPTION 17 24 14 AHO BHO CHO (xHO) High-Side Outputs. Connect to the gates of the High-Side power MOSFETs in each phase. 20 VDD Positive Supply. Decouple this pin to VSS (Pin 6). 21 22 19 ALO BLO CLO (xLO) Low-Side Outputs. Connect the gates of the Low-Side power MOSFETs to these pins. NOTE: x = A, B or C. Ordering Information PART NUMBER (Notes 1, 3) PART MARKING TEMP RANGE (C) CHARGE PUMP PACKAGE PKG. DWG. # HIP4086AB HIP4086AB -40 to +125 Yes 24 Ld SOIC M24.3 HIP4086ABZ (Note 2) HIP4086ABZ -40 to +125 Yes 24 Ld SOIC (Pb-free) M24.3 HIP4086APZ (Note 2) HIP4086APZ -40 to +125 Yes 24 Ld PDIP (Pb-free) E24.3 HIP4086AABZ (Note 2) HIP4086AABZ -40 to +125 No 24 Ld SOIC (Pb-free) M24.3 HIP4086EVAL Evaluation Board NOTES: 1. Add "-T*", suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for HIP4086, HIP4086A. For more information on MSL, please see Technical Brief TB363. 4 FN4220.7 June 1, 2011 HIP4086, HIP4086A Absolute Maximum Ratings Thermal Information (Note 7) Supply Voltage, VDD Relative to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V Logic Inputs (xLI, xHI) . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3v to VDD + 0.3V Voltage on xHS . . . . . . . . . . . . . . -6V (Transient) to 85V (-40C to +150C) Voltage on xHB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VxHS - 0.3V to VxHS +VDD Voltage on xLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSS - 0.3V to VDD +0.3V Voltage on xHO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VxHS - 0.3V to VxHB +0.3V Phase slew rate (on xHS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V/ns Thermal Resistance (Typical) JA (C/W) JC (C/W) SOIC Package (Notes 4, 6) . . . . . . . . . . . . . 75 22 SOIC Package HIP4086AABZ (Notes 5, 6) 51 22 PDIP* Package (Notes 4, 6) . . . . . . . . . . . . 70 29 Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Operating Junction Temp Range . . . . . . . . . . . . . . . . . . . .-40C to +150C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for through-hole wave solder processing only. They are not intended for use in Reflow solder processing applications. Maximum Recommended Operating Conditions Supply Voltage, VDD Relative to GND . . . . . . . . . . . . . . . . . . . . . . . 7V to 15V Logic Inputs (xLI, xHI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to VDD Voltage on xHB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VxHS + VDD Voltage on xHS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 80V Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40C to +125C Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-40C to +150C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 6. For JC, the "case temp" location is taken at the package top center. 7. Replace x with A, B, or C. VDD = VxHB = 12V, VSS = VxHS = 0V, RDEL = 20k, RUV = , Gate Capacitance (CGATE) = 1000pF, unless otherwise specified. Boldface limits apply over the operating junction temperature range, -40C to +150C. DC Electrical Specifications TJ = +25C PARAMETER TEST CONDITIONS TJ = -40C TO +150C MIN (Note 9) TYP MAX (Note 9) MIN (Note 9) MAX (Note 9) UNITS 2.7 3.4 4.2 2.1 4.3 mA SUPPLY CURRENTS xHI = 5V, xLI = 5V (HIP4086) VDD Quiescent Current VDD Operating Current xHI = 5V, xLI = 5V (HIP4086A) 2.3 2.4 2.6 2.1 2.7 mA f = 20kHz, 50% Duty Cycle (HIP4086) 6.3 8.25 10.5 5 11 mA f = 20kHz, 50% Duty Cycle (HIP4086A) 3.1 3.6 4.1 2.8 4.4 mA - 40 80 - 100 A 80 100 200 A 0.6 0.8 1.3 0.5 1.4 mA xHI = 0V (HIP4086) xHB On Quiescent Current xHI = 0V (HIP4086A) xHI = VDD (HIP4086) xHB Off Quiescent Current xHB Operating Current xHI = VDD (HIP4086A) 0.8 0.9 1 0.7 1.2 mA f = 20kHz, 50% Duty Cycle (HIP4086) 0.7 0.9 1.3 - 2.0 mA f = 20kHz, 50% Duty Cycle (HIP4086A) 0.8 0.9 1 - 1.2 mA 7 24 45 - 50 A 11.5 12.5 14 10.5 14.5 V 50 100 130 - 140 A VxHS = 80V, VxHB = 93V xHB, xHS Leakage Current Charge Pump, HIP4086 only, (Note 8) QPUMP Output Voltage No Load QPUMP Output Current VxHS = 12V, VxHB = 22V UNDERVOLTAGE PROTECTION VDD Rising Undervoltage Threshold RUV open 6.2 7.1 8.0 6.1 8.1 V VDD Falling Undervoltage Threshold RUV open 5.75 6.6 7.5 5.6 7.6 V Minimum Undervoltage Threshold RUV = VDD 5 6.2 6.8 4.9 6.9 V 5 FN4220.7 June 1, 2011 HIP4086, HIP4086A VDD = VxHB = 12V, VSS = VxHS = 0V, RDEL = 20k, RUV = , Gate Capacitance (CGATE) = 1000pF, unless otherwise specified. Boldface limits apply over the operating junction temperature range, -40C to +150C. (Continued) DC Electrical Specifications TJ = +25C TJ = -40C TO +150C MIN (Note 9) TYP MAX (Note 9) MIN (Note 9) MAX (Note 9) UNITS Low Level Input Voltage - - 1.0 - 0.8 V High Level Input Voltage 2.5 - - 2.7 - V Input Voltage Hysteresis - 35 - - - mV PARAMETER TEST CONDITIONS INPUT PINS: ALI, BLI, CLI, AHI, BHI, CHI, AND DIS Low Level Input Current VIN = 0V -60 -100 -135 -55 -140 A High Level Input Current VIN = 5V -1 - +1 -10 +10 A - 100 - - 200 mV 0.3 0.5 0.7 - 1.0 A GATE DRIVER OUTPUT PINS: ALO, BLO, CLO, AHO, BHO, AND CHO Low Level Output Voltage (VOUT - VSS) ISINKING = 30mA VOUT = 0V Peak Turn-On Current NOTES: 8. the specified charge pump current is the total amount available to drive external loads across xHO and xHS. 9. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. AC Electrical Specifications VDD = VxHB = 12V, VSS = VxHS = 0V, CGATE = 1000pF, RDEL = 10k, unless otherwise specified. Boldface limits apply over the operating junction temperature range, -40C to +150C. TJ = +25C TJ = -40C TO +150C MIN (Note 9) TYP MAX (Note 9) MIN (Note 9) MAX (Note 9) UNITS RDEL = 100k 3.8 4.5 6 3 7 s RDEL = 10k 0.38 0.5 0.65 0.3 0.7 s Dead Time Channel Matching RDEL = 10k - 7 15 - 20 % Lower Turn-Off Propagation Delay (xLI to xLO turn-off) (Figure 3 or 4) No Load - 30 45 - 65 ns Upper Turn-Off Propagation Delay (xHI to xHO turn-off) (Figure 3 or 4) No Load - 75 90 - 100 ns Lower Turn-On Propagation Delay (xLI to xLO turn-on) (Figure 3 or 4) No Load - 45 75 - 90 ns Upper Turn-On Propagation Delay (xHI to xHO turn-on) (Figure 3 or 4) No Load - 65 90 - 100 ns Rise Time CGATE = 1000pF - 20 40 - 50 ns Fall Time CGATE = 1000pF - 10 20 - 25 ns Disable Turn-Off Propagation Delay (DIS to xLO turn-off) (Figure 5) - 55 80 - 90 ns Disable Turn-Off Propagation Delay (DIS to xHO turn-off) (Figure 5) - 80 90 - 100 ns Disable to Lower Turn-On Propagation Delay (DIS to xLO turn-on) (Figure 5) - 55 80 - 100 ns - 2.0 - - - s PARAMETER TEST CONDITIONS TURN-ON DELAY AND PROPAGATION DELAY Dead Time (Figure 3) RDEL = 10k, CRFSH Open Disable to Upper Enable (DIS to xHO turn-on) (Figure 5) 6 FN4220.7 June 1, 2011 HIP4086, HIP4086A Test Waveforms and Timing Diagrams xLI to xLO turn-off xLI to xLO turn-on + delay xLI to xLO turn-off xLI to xHO turn-off xLI xHI xLO xHO xHI to xHO turn-on + delay Dead time xHI to xHO turn-off Dead time FIGURE 3. PROP DELAYS WITH PROGRAMMED TURN-ON DELAYS (RDEL CONNECTED TO VDD WITH A RESISTOR) xLI to xLO turn-off xLI to xLO turn-on xLI to xLO turn-off xLI to xLO turn-on xLI xHI xLO and xHO are on simulateously xLO xHO xHI to xHO turn-on xHI to xHO turn-off xHI to xHO turn-on FIGURE 4. PROP DELAYS WITH NO PROGRAMMED TURN-ON DELAYS (RDEL CONNECTED TO VSS) DIS to xLO turn-on delay DIS or UV DIS to xHO turn-off delay DIS to xLO turn-on delay refresh pulse refresh pulse xHI, xLI xLO xHO xHO turn-on delay FIGURE 5. DISABLE FUNCTION 7 FN4220.7 June 1, 2011 HIP4086, HIP4086A Typical Performance Curves 6 30 4 VDD SUPPLY CURRENT (mA) VDD SUPPLY CURRENT (mA) 5 VDD = 15V VDD = 12V VDD = 10V 3 CGATE = 1000pF ALL GATE CONTROL INPUTS = 5V VDD = 16V VDD = 8V 200kHz 25 100kHz 20 50kHz 20kHz 10kHz 15 VDD = 7V 2 -60 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (C) 120 140 10 -60 160 FIGURE 6. VDD SUPPLY CURRENT vs VDD SUPPLY VOLTAGE 120 140 160 VDD = 15V 1.6 3000 BIAS CURRENT (mA) FLOATING BIAS CURRENT (A) 0 20 40 60 80 100 JUNCTION TEMPERATURE (C) 1.8 TJ = +25C CGATE = 1000pF 2000 1000 CGATE = NO LOAD 0 20 40 60 80 100 120 140 160 SWITCHING FREQUENCY (kHz) 1.4 1.2 VDD = 12V 0.8 180 0.6 -60 200 -40 -20 0 20 40 60 80 100 120 140 160 140 160 JUNCTION TEMPERATURE (C) FIGURE 9. OFF-STATE IXHB BIAS CURRENT 14 CHARGE PUMP OUTPUT VOLTAGE (V) 200 VxHB - VxHS = 10V 150 100 50 0 -60 VDD = 10V VDD = 8V VDD = 7V 1.0 FIGURE 8. FLOATING IXHB BIAS CURRENT OUTPUT CURRENT (A) -20 FIGURE 7. VDD SUPPLY CURRENT vs SWITCHING FREQUENCY 4000 0 -40 -40 -20 0 20 40 60 80 100 120 140 160 JUNCTION TEMPERATURE (C) FIGURE 10. CHARGE PUMP OUTPUT CURRENT (HIP4086 only) 8 VDD = 15V 13 12 VDD = 12V VDD = 10V 11 10 VDD = 8V 9 8 VDD = 7V 7 6 -60 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (C) FIGURE 11. CHARGE PUMP OUTPUT VOLTAGE(HIP4086 only)( FN4220.7 June 1, 2011 HIP4086, HIP4086A Typical Performance Curves (Continued) 2 CGATE = 1000pF AVERAGE TURN-OFF CURRENT (A) AVERAGE TURN-ON CURRENT (A) 1 0.8 VDD = 15V 0.6 VDD = 12V VDD = 10V 0.4 V DD = 8V VDD = 7V 0.2 0 -60 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (C) 120 140 1.6 VDD = 12V 1.2 VDD = 10V VDD = 8V 0.8 VDD = 7V 0.4 0 -60 160 CGATE = 1000pF VDD = 15V FIGURE 12. AVERAGE TURN-ON CURRENT (0 TO 5V) -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (C) 120 140 160 FIGURE 13. AVERAGE TURN-OFF CURRENT (V DD TO 4V) 100 40 PROPAGATION DELAY (ns) RISE AND FALL TIMES (ns) VDD = XHB-XHS = 12V, CGATE = 1000pF 30 RISE 20 FALL 10 0 -60 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (C) 120 140 80 xHI to xHO 60 40 xLI to xLO 20 -60 160 -40 0 20 40 60 80 100 120 140 160 450 500 JUNCTION TEMPERATURE (C) FIGURE 14. RISE AND FALL TIMES (10 to 90%) FIGURE 15. PROPAGATION DELAY 80 100 TJ = +25C REFRESH TIME (s) UPPER DISABLE TURN-OFF PROPAGATION DELAY (ns) -20 LOWER DISABLE TURN-OFF LOWER ENABLE TURN-ON 10 -60 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (C) 120 FIGURE 16. DISABLE PIN PROPAGATION DELAY 9 140 160 60 40 20 0 0 50 100 150 200 250 300 CRFSH (pF) 350 400 FIGURE 17. REFRESH TIME FN4220.7 June 1, 2011 HIP4086, HIP4086A Typical Performance Curves (Continued) 11.0 6 10.5 UNDERVOLTAGE SHUTDOWN/ ENABLE VOLTAGE RDEL = 100k DEAD TIME (s) 10.0 4 2 RDEL = 10k 0 -60 -40 -20 ENABLE (50k, UVLO TO GND) 9.5 9.0 8.5 8.0 7.5 TRIP (50k, UVLO TO GND) TRIP/ENABLE (0k, UVLO TO VDD) 7.0 ENABLE (UVLO OPEN) TRIP (UVLO OPEN) 6.5 0 20 40 60 80 100 JUNCTION TEMPERATURE (C) 120 140 160 FIGURE 18. DEAD TIME 6.0 -60 -40 -20 0 20 40 60 80 100 120 JUNCTION TEMPERATURE (C) 140 160 FIGURE 19. UNDERVOLTAGE THRESHOLD LEAKAGE CURRENT (A) 25 VxHS = 80V 20 15 10 -60 -40 -20 0 20 40 60 80 100 JUNCTION TEMPERATURE (C) 120 140 160 FIGURE 20. IxHS LEAKAGE CURRENT Functional Description Input Logic NOTE: When appropriate for brevity, input and output pins will be prefixed with an "x" as a substitute for A, B, or C. For example, xHS refers to pins AHS, BHS, and CHS. The HIP4086/A is a three phase bridge driver designed specifically for motor drive applications. Three identical half bridge sections, A, B, and C, can be controlled individually by their input pins, ALI, AHI, BLI, BHI, and CLI, CHI (xLI, xHI) or the 2 corresponding input pins for each section can be tied together to form a PWM input (xLI connected to xHI = xPWM). When controlling individual inputs, the programmable dead time is optional but shoot-thru protection must then be incorporated in the timing of the input signals. If the PWM mode is chosen, then the internal programmable dead time must be used. Shoot-Thru Protection enabled if the voltage on the RDEL pin is greater than 100mV. The voltage on RDEL will be greater than 100mV for any value of programming resistor in the specified range. If the voltage on RDEL is less than 100mV, the delay timers are disabled and no shoot-thru protection is provided by the internal logic of the HIP4086/A. When the dead time is to be disabled, RDEL should be shorted to VSS. Refresh Pulse To insure that the boot capacitors are charged prior to turning on the high-side drivers, a refresh pulse is triggered when DIS is low or when the UV comparator transitions low (VDD is greater than the programmed undervoltage threshold). Please refer to the "Block Diagram (for clarity, only one phase is shown)" on page 2. When triggered, the refresh pulse turns on all of the low-side drivers (xLO = 1) and turns off all of the high-side drivers (xHO = 0) for a duration set by a resistor tied between RDEL and VSS. When xLO = 1, the low-side bridge FETs charge the boot caps from VDD through the boot diodes. Dead time, to prevent shoot-thru, is implemented by delaying the turn-on of the high-side and low-side drivers. The delay timers are 10 FN4220.7 June 1, 2011 HIP4086, HIP4086A Charge Pump The internal charge pump of the HIP4086/A is used to maintain the bias on the boot cap for 100% duty cycle. There is no limit for the duration of this period. The user must understand that this charge pump is only intended to provide the static bias current of the high-side drivers and the gate leakage current of the high-side bridge FETs. It cannot provide in a reasonable time, the majority of the charge on the boot cap that is consumed, when the xHO drivers source the gate charge to turn on the high-side bridge FETs. The boot caps should be sized so that they do not discharge excessively when sourcing the gate charge. See "Application Information" on page 11 for methods to size the boot caps. The charge pump has sufficient capacity to source a worst-case minimum of 50A to the external load. The gate leakage current of most power MOSFETs is about 100nA so there is more than sufficient current to maintain the charge on the boot caps. Because the charge pump current is small, a gate-source resistor on the high-side bridge FETs is not recommended. When calculating the leakage load on the outputs of xHS, also include the leakage current of the boot capacitor. This is rarely a problem but it could be an issue with electrolytic capacitors at high temperatures. Application Information Equation 1 calculates the total charge required for the Period duration. This equation assumes that all of the parameters are constant during the Period duration. The error is insignificant if Ripple is small. Q C = Q gate80V + Period x (I HB + V HO R GS + I gate_leak ) C boot = Q C ( Ripple VDD ) (EQ. 1) C boot = 0.52F If the gate to source resistor is removed (RGS is usually not needed or recommended), then: Cboot = 0.33F These values of Cboot will sustain the high side driver bias during Period with only a small amount of Ripple. But in the case of the HIP4086, the charge pump reduces the value of Cboot even more. The specified charge pump current is a minimum of 50A which is more than sufficient to source Igate_leak. Also, because the specified charge pump current is in excess of what is needed for IHB, the total charge required to be sourced by the boot capacitor is just (EQ. 2) Q C = Q gate80V or Cboot = 0.13F Not only is the required boot cap smaller in value, there is no restriction on the duration of Period. Selecting the Boot Capacitor Value The boot capacitor value is chosen not only to supply the internal bias current of the high-side driver but also, and more significantly, to provide the gate charge of the driven FET without causing the boot voltage to sag excessively. In practice, the boot capacitor should have a total charge that is about 20 times the gate charge of the driven power FET for approximately a 5% drop in voltage after charge has been transferred from the boot capacitor to the gate capacitance. The following parameters shown in Table 1, are required to calculate the value of the boot capacitor for a specific amount of voltage droop when using the HIP4086/A (no charge pump). In Table 1, the values used are arbitrary. They should be changed to comply with the actual application. TABLE 1. VDD = 10V VDD can be any value between 7 and 15VDC VHB = VDD - 0.6V = VHO High side driver bias voltage (VDD - boot diode voltage) referenced to VHS Period = 1ms This is the longest expected switching period IHB= 100A Worst case high side driver current when xHO = high (this value is specified for VDD = 12V but the error is not significant) RGS = 100k Gate-source resistor (usually not needed) Ripple = 5% Desired ripple voltage on the boot cap (larger ripple is not recommended) Igate_leak = 100nA From the FET vendor's datasheet Qgate80V = 64nC From Figure L 11 FIGURE 21. TYPICAL GATE VOLTAGE vs GATE CHARGE FN4220.7 June 1, 2011 HIP4086, HIP4086A Typical Application Circuit VDD VDD CHB RDEL BHB AHB Speed AHI ALI Controller BHI HIP4086/A AHO BLI Brake BHO Battery 24V...48V CHO CHS BHS AHS CHI CLI VSS ALO BLO CLO FIGURE 22. TYPICAL APPLICATION CIRCUIT Figure 22 is an example of how the HIP4086 and HIP4086A 3-phase drivers can be applied to drive a 3-phase motor. Depending on the application, the switching speed of the bridge FETs can be reduced by adding series connected resistors between the xHO outputs and the FET gates. Gate-Source resistors are recommended on the low-side FETs to prevent unexpected turn-on of the bridge should the bridge voltage be applied before VDD. Gate-source resistors on the high-side FETs are not usually required if low-side gate-source resistors are used. If relatively small gate-source resistors are used on the high-side FETs, be aware that they will load the charge pump of the HIP4086 negating the ability of the charge pump to keep the high-side driver biased during very long periods. An important operating condition that is frequently overlooked by designers is the negative transient on the xHS pins that occurs when the high-side bridge FET turns off. The Absolute Maximum transient allowed on the xHS pin is -6V but it is wise to minimize the amplitude to lower levels. This transient is the result of the parasitic inductance of the low-side drain-source conductor on the PCB. Even the parasitic inductance of the low-side FET contributes to this transient. xHO IN D U C T IV E LO AD xHS + xLO + VSS FIGURE 23. BRIDGE WITH PARASITIC INDUCTANCES 12 When the high-side bridge FET turns off, because of the inductive characteristics of a motor load, the current that was flowing in the high-side FET (blue) must rapidly commutate to flow through the low-side FET (red). The amplitude of the negative transient impressed on the xHS node is (di/dt x L) where L is the total parasitic inductance of the low-side FET drain-source path and di/ddt is the rate at which the high-side FET is turned off. With the increasing power levels of new generation motor drives, clamping this transient becomes more and more significant for the proper operation of the HIP4086/A. There are several ways of reducing the amplitude of this transient. If the bridge FETs are turned off more slowly to reduce di/dt, the amplitude will be reduced but at the expense of more switching losses in the FETs. Careful PCB design will also reduce the value of the parasitic inductance. However, these two solutions by themselves may not be sufficient. Figure 23 illustrates a simple method for clamping the negative transient. Two series connected, fast PN junction, 1A diodes are connected between xHS and VSS as shown. It is important that the components be placed as close as possible to the xHS and VSS pins to minimize the parasitic inductance of this current path. Two series connected diodes are required because they are in parallel with the body diode of the low-side FET. If only one diode is used for the clamp, it will conduct some of the negative load current that is flowing in the low-side FET. In severe cases, a small value resistor in series with the xHS pin as shown, will further reduce the amplitude of the negative transient. Please note that a similar transient with a positive polarity occurs when the low-side FET turns off. This is less frequently a problem because xHS node is floating up toward the bridge bias voltage. The Absolute Max voltage rating for the xHS node does need to be observed when the positive transient occurs. FN4220.7 June 1, 2011 HIP4086, HIP4086A General PCB Layout Guidelines The AC performance of the HIP4086/A depends significantly on the design of the PC board. The following layout design guidelines are recommended to achieve optimum performance: * Place the driver as close as possible to the driven power FETs. * Understand where the switching power currents flow. The high amplitude di/dt currents of the driven power FET will induce significant voltage transients on the associated traces. * Keep power loops as short as possible by paralleling the source and return traces. * Use planes where practical; they are usually more effective than parallel traces. * Avoid paralleling high amplitude di/dt traces with low level signal lines. High di/dt will induce currents and consequently, noise voltages in the low level signal lines. * When practical, minimize impedances in low level signal circuits. The noise, magnetically induced on a 10k resistor, is 10x larger than the noise on a 1k resistor. * Be aware of magnetic fields emanating from motors, transformers and inductors. Gaps in these magnetic structures are especially bad for emitting flux. * It may be necessary to add resistance to dampen resonating parasitic circuits especially on xHO and xLO. If an external gate resistor is unacceptable, then the layout must be improved to minimize lead inductance. * Keep high dv/dt nodes away from low level circuits. Guard banding can be used to shunt away dv/dt injected currents from sensitive circuits. This is especially true for control circuits that source the input signals to the HIP4086/A. * Avoid having a signal ground plane under a high amplitude dv/dt circuit. This will inject di/dt currents into the signal ground paths. * Do power dissipation and voltage drop calculations of the power traces. Many PCB/CAD programs have built in tools for calculation of trace resistance. * Large power components (Power FETs, Electrolytic caps, power resistors, etc.) will have internal parasitic inductance which cannot be eliminated. This must be accounted for in the PCB layout and circuit design. * If you simulate your circuits, consider including parasitic components especially parasitic lead inductance. * If you must have traces close to magnetic devices, align the traces so that they are parallel to the flux lines to minimize coupling. * The use of low inductance components such as chip resistors and chip capacitors is highly recommended. * Use decoupling capacitors to reduce the influence of parasitic inductance in the VDD and GND leads. To be effective, these caps must also have the shortest possible conduction paths. If vias are used, connect several paralleled vias to reduce the inductance of the vias. 13 FN4220.7 June 1, 2011 HIP4086, HIP4086A Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION 5/10/11 FN4220.7 3/18/11 CHANGE Added alternate parameters for HIP4086A in DC Electrical Spec Table Supply Currents on page 5. Added to Charge Pump Figures 10 and 11 in Typical Performance Curves "HIP4086 Only" -Converted to new Intersil Template per PL request. -Changed Title from "80V, 500mA, 3-Phase Driver" to "80V, 500mA, 3-Phase MOSFET Driver" -Rewrote description on page 1 by adding HIP4086A and stating the differences between parts. -Updated ordering information by adding part number HIP4086AABZ and EVAL Board. Added MSL note and numbered all notes to meet new standard, Removed obsolete part HIP4086AP -Updated Application Block Diagram on page 1 -Added Charge Pump Current Curve on page 1 -Updated Features and Applications Section -Added Related Literature -Updated Functional Block Diagram by adding color and notes -Updated Thermal Information and notes on page 5 -Added Boldface limits note to Electrical Spec Table conditions, added note to MIN and MAX columns to reference new standard compliance note. -Updated all timing diagrams for better clarification on page 7 -Added Functional Description, Applications Information and General PCB Layout Guidelines sections beginning on page 10 -Updated POD M24.3 by removing table listing dimensions and putting dimensions on drawing. Added Land Pattern. Added Revision History and Products Information. 7/26/04 FN4220.6 Pb-Free Parts added 2/18/03 FN4220.5 Updated Datasheet 6/21/02 FN4220.4 Initial Release. Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: HIP4086, HIP4086A To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff FITs are available from our website at: http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 14 FN4220.7 June 1, 2011 HIP4086, HIP4086A Dual-In-Line Plastic Packages (PDIP) E24.3 (JEDEC MS-001-AF ISSUE D) N 24 LEAD NARROW BODY DUAL-IN-LINE PLASTIC PACKAGE E1 INDEX AREA 1 2 3 N/2 INCHES -B- SYMBOL -AD -C- SEATING PLANE A2 e B1 D1 A1 eC B 0.010 (0.25) M C A B S MIN MAX - NOTES A - 0.210 5.33 4 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - C L B 0.014 0.022 0.356 0.558 - eA B1 0.045 0.070 1.15 1.77 8 C 0.008 0.014 0.204 0.355 - D 1.230 1.280 31.24 D1 0.005 - 0.13 A L D1 MAX A1 E BASE PLANE MILLIMETERS MIN C eB NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 32.51 5 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC 6 eB - 0.430 L 0.115 0.150 N 24 2.93 24 10.92 7 3.81 4 9 Rev. 0 12/93 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 15 FN4220.7 June 1, 2011 HIP4086, HIP4086A Package Outline Drawing M24.3 24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE (SOIC) Rev 2, 3/11 24 INDEX AREA 7.60 (0.299) 7.40 (0.291) 10.65 (0.419) 10.00 (0.394) DETAIL "A" 1 2 3 TOP VIEW 1.27 (0.050) 0.40 (0.016) SEATING PLANE 2.65 (0.104) 2.35 (0.093) 15.60 (0.614) 15.20 (0.598) 0.75 (0.029) x 45 0.25 (0.010) 0.30 (0.012) 0.10 (0.004) 1.27 (0.050) 0.51 (0.020) 0.33 (0.013) 8 0 0.32 (0.012) 0.23 (0.009) SIDE VIEW "B" SIDE VIEW "A" 1.981 (0.078) 9.373 (0.369) 1.27 (0.050) NOTES: 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 3. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Terminal numbers are shown for reference only. 6. The lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. Controlling dimension: MILLIMETER. Converted inch dimensions in ( ) are not necessarily exact. 8. This outline conforms to JEDEC publication MS-013-AD ISSUE C. 0.533 (0.021) TYPICAL RECOMMENDED LAND PATTERN 16 FN4220.7 June 1, 2011