CCD area image sensor S10140/S10141 series
2
General ratings
Absolute maximum ratings (Ta=25 °C)
Operating conditions (MPP mode, Ta=25 °C)
Parameter S10140 series S10141 series
Pixel size 12 (H) × 12 (V) m
Vertical clock phase 2 phases
Horizontal clock phase 2 phases
Output circuit One-stage MOSFET source follower
Package 24-pin ceramic DIP (refer to dimensional outlines)
Window*1Quartz glass AR-coated sapphire
*1: Temporary window type (ex. S10140-1107N) is available upon request.
Parameter Symbol Min. Typ. Max. Unit
Operating temperature*2To pr -50 - +50 ° C
Storage temperature Tstg -50 - +70 °C
Output transistor drain voltage VOD -0.5 - +30 V
Reset drain voltage VRD -0.5 - +18 V
Vertical input source voltage VISV -0.5 - +18 V
Horizontal input source voltage VISH -0.5 - +18 V
Vertical input gate voltage VIG1V, VIG2V -10 - +15 V
Horizontal input gate voltage VIG1H, VIG2H -10 - +15 V
Summing gate voltage VSG -10 - +15 V
Output gate voltage VOG -10 - +15 V
Reset gate voltage VRG -10 - +15 V
Transfer gate voltage VTG -10 - +15 V
Vertical shift register clock voltage VP1V, VP2V -10 - +15 V
Horizontal shift register clock voltage VP1H, VP2H -10 - +15 V
*2: Package temperature (S10140 series), chip temperature (S10141 series)
Parameter Symbol Min. Typ. Max. Unit
Output transistor drain voltage VOD 23 24 25 V
Reset drain voltage VRD 11 12 13 V
Output gate voltage VOG 2.5 3 3.5 V
Substrate voltage VSS -0-V
Test point
vertical input source VISV -VRD -V
horizontal input source VISH -VRD -V
vertical input gate VIG1V, VIG2V -9 -8 - V
horizontal input gate VIG1H, VIG2H -9 -8 - V
Vertical shift register
clock voltage
High VP1VH, VP2VH 2.5 3 3.5 V
Low VP1VL, VP2VL -9 -8 -7
Horizontal shift register
clock voltage
High VP1HH, VP2HH 456
V
Low VP1HL, VP2HL -9 -8 -7
Summing gate voltage High VSGH 456
V
Low VSGL -9 -8 -7
Reset gate voltage High VRGH 456
V
Low VRGL -9 -8 -7
Transfer gate voltage High VTGH 2.5 3 3.5 V
Low VTGL -9 -8 -7
External load resistance RL90 100 110 k: