71M6534-IGT/F - Maxim - Product.Network

71M6533/G/

H and 71M6534/H

Energy Meter ICs

DATA SHEET

Rev 2 1

GENERAL DESCRIPTION

The Teridian™ 71M6533 and 71M6534 are third-generation

polyphase metering systems-on-chips (SoCs) with a 10MHz 8051-

compatible MPU core, low-power RTC, flash, and LCD driver. The

Single Converter Technology® with a 22-bit delta-sigma ADC, seven

analog inputs, digital temperature compensation, precision voltage

reference, and a 32-bit computation engine (CE) supports a wide

range of metering applications with very few external components.

The 71M6533 and 71M6534 add several new features to the

Teridian flagship 71M6513 polyphase meters, including an SPI

interface, advanced power management with < 1µA sleep current,

4KB shared RAM, and 128KB (71M6533/H, 71M6534), or 256KB

(71M6533G, 71M6534H) flash, which can be programmed in the

field with new code and/or data during meter operation. Higher

processing and sampling rates and larger memory offer a

powerful metering platform for commercial and industrial meters

with up to class 0.2 accuracy.

A complete array of ICE and development tools, programming

libraries and reference designs enable rapid development and

certification of meters that meet all ANSI and IEC electricity metering

standards worldwide.

FEATURES

• Wh Accuracy < 0.1% Over 2000:1 Range

• Exceeds IEC 62053/ANSI C12.20 Standards

• Seven Sensor Inputs with Neutral Current

Measurement

• Low-Jitter Wh and VARh Plus Two Additional

Pulse Test Outputs (4 Total, 10kHz max) with

Pulse Count

• Four-Quadrant Metering

• Phase Sequencing

• Line Frequency Count for RTC

• Digital Temperature Compensation

• Independent 32-Bit CE

• 46-64 Hz Line Frequency Range with Same

Calibration; Phase Compensation (± 7°)

• Three Battery-Backup Modes with Wake-Up

on Timer or Pushbutton:

Brownout Mode (82µA typ, 71M6533)

LCD Mode (21µA typ, DAC active)

Sleep Mode (0.7µA typ)

• Energy Display During Mains Power Failure

• 39mW (typ) Consumption at 3.3V, MPU

Clock Frequency 614kHz

• 8-Bit MPU (80515), 10MHz (max), One

Clock Cycle per Instruction with Integrated

ICE for Debug

• LCD Driver with Four Common Segment

Drivers:

Up to 228 Pixels (71M6533) or 300 Pixels

(71M6534)

• Four Dedicated + 35 (71M6533) or 48

(71M6534) Multifunction DIO Pins

• RTC for TOU Functions with Clock-Rate Adjust

• Hardware Watchdog Timer, Power-Fail Monitor

• I2C/MICROWIRE® EEPROM Interface

• High-Speed Slave SPI Interface to Data RAM

• Two UARTs for IR and AMR, IR Driver with

Modulation

• Flash Memory with Security and In-System

Program Update:

128KB (71M6533/H, 71M6534)

256KB (71M6533G, 71M6534H)

• 4KB RAM

• Industrial Temperature Range

• 100-Pin (71M6533/G/H) or 120-Pin

(71M6534/H) Lead(Pb)-Free LQFP Package

MPU

RTC

TIMERS

XIN

XOUT

COM0..3

V3P3A V3P3SYS

VBAT

V2P5

SEG

GNDA GNDD

SEG/DIO

DIO

ICE

LIVE

NEUT

LOAD

8888.8888

PULSES,

DIO

POWER

FAULT

AMR

COMPARATOR

MOD

SERIAL PORTS

OSC/ PLL

CONVERTER

LCD DRIVER

DIO , PULSE

COMPUTE

ENGINE

FLASH

RAM

32 kHz

REGULATOR

CT / COIL

POWER SUPPLY

TERIDIAN

71M6533

71M6534

TEMP

SENSOR

VREF

BATTERY

PWR MODE

CONTROL

WAKE-up

NEUTRAL

C or µWire

EEPROM

9/24/2008

V2*

* 71M6534 only

Teridian is a trademark and Single Converter Technology is a registered

trademark of Maxim Integrated Products, Inc.

MICROWIRE is a registered trademark of National Semiconductor Corp.

19-5373; Rev 2; 2/12

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

2 Rev 2

Table of Contents

1 Hardware Description .................................................................................................................... 9

1.1 Hardware Overview ............................................................................................................... 9

1.2 Analog Front End (AFE) ........................................................................................................ 9

1.2.1 Signal Input Pins ......................................................................................................... 9

1.2.2 Input Multiplexer ........................................................................................................ 10

1.2.3 A/D Converter (ADC) ................................................................................................. 11

1.2.4 FIR Filter ................................................................................................................... 11

1.2.5 Voltage References ................................................................................................... 12

1.2.6 Temperature Sensor.................................................................................................. 13

1.2.7 Battery Monitor .......................................................................................................... 13

1.2.8 AFE Functional Description ....................................................................................... 13

1.3 Digital Computation Engine (CE) ....................................................................................... 14

1.3.1 Meter Equations ........................................................................................................ 15

1.3.2 Real-Time Monitor ..................................................................................................... 16

1.3.3 Pulse Generators ...................................................................................................... 16

1.3.4 Data RAM (XRAM) .................................................................................................... 16

1.3.5 CE Functional Overview ............................................................................................ 17

1.3.6 Delay Compensation ................................................................................................. 18

1.4 80515 MPU Core .................................................................................................................. 19

1.4.1 Memory Organization and Addressing ....................................................................... 19

1.4.2 Special Function Registers (SFRs) ............................................................................ 21

1.4.3 Generic 80515 Special Function Registers ................................................................ 22

1.4.4 71M6533/71M6534-Specific Special Function Registers ............................................ 25

1.4.5 Instruction Set ........................................................................................................... 26

1.4.6 UARTs ...................................................................................................................... 26

1.4.7 Timers and Counters ................................................................................................. 29

1.4.8 WD Timer (Software Watchdog Timer) ...................................................................... 30

1.4.9 Interrupts ................................................................................................................... 30

1.5 On-Chip Resources ............................................................................................................. 37

1.5.1 Oscillator ................................................................................................................... 37

1.5.2 PLL and Internal Clocks............................................................................................. 37

1.5.3 Real-Time Clock (RTC) ............................................................................................. 38

1.5.4 Temperature Sensor.................................................................................................. 39

1.5.5 Physical Memory ....................................................................................................... 39

1.5.6 Optical Interface ........................................................................................................ 42

1.5.7 Digital I/O .................................................................................................................. 42

1.5.8 LCD Drivers .............................................................................................................. 46

1.5.9 Battery Monitor .......................................................................................................... 47

1.5.10 EEPROM Interface .................................................................................................... 47

1.5.11 SPI Slave Port ........................................................................................................... 50

1.5.12 Hardware Watchdog Timer ........................................................................................ 53

1.5.13 Test Ports (TMUXOUT Pin) ....................................................................................... 54

1.5.14 V2 Comparator (71M6534/6534H Only) ..................................................................... 54

2 Functional Description ................................................................................................................ 55

2.1 Theory of Operation ............................................................................................................ 55

2.2 System Timing Summary.................................................................................................... 56

2.3 Battery Modes ..................................................................................................................... 57

2.3.1 BROWNOUT Mode ................................................................................................... 59

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 3

2.3.2 LCD Mode ................................................................................................................. 59

2.3.3 SLEEP Mode............................................................................................................. 59

2.4 Fault and Reset Behavior ................................................................................................... 65

2.4.1 Reset Mode ............................................................................................................... 65

2.4.2 Power Fault Circuit .................................................................................................... 65

2.5 Wake Up Behavior............................................................................................................... 65

2.5.1 Wake on PB .............................................................................................................. 65

2.5.2 Wake on Timer .......................................................................................................... 66

2.6 Data Flow ............................................................................................................................. 66

2.7 CE/MPU Communication .................................................................................................... 67

3 Application Information ............................................................................................................... 68

3.1 Connection of Sensors (CT, Resistive Shunt) ................................................................... 68

3.2 Distinction between 71M6533/71M6534 and 71M6533G/H/71M6534H Parts ..................... 68

3.3 Connecting 5 V Devices ...................................................................................................... 69

3.4 Temperature Measurement ................................................................................................. 69

3.5 Temperature Compensation ............................................................................................... 69

3.5.1 Temperature Coefficients .......................................................................................... 69

3.5.2 Temperature Compensation for VREF ....................................................................... 71

3.5.3 System Temperature Compensation .......................................................................... 72

3.5.4 Temperature Compensation for the RTC ................................................................... 72

3.6 Connecting LCDs ................................................................................................................ 72

3.7 Connecting I2C EEPROMs .................................................................................................. 73

3.8 Connecting Three-Wire EEPROMs ..................................................................................... 73

3.9 UART0 (TX/RX) .................................................................................................................... 74

3.10 Optical Interface (UART1) ................................................................................................... 74

3.11 Connecting the V1 Pin ........................................................................................................ 75

3.12 Connecting the Reset Pin ................................................................................................... 75

3.13 Connecting the Emulator Port Pins.................................................................................... 76

3.14 Connecting a Battery .......................................................................................................... 76

3.15 Flash Programming ............................................................................................................ 77

3.16 MPU Firmware Library ........................................................................................................ 77

3.17 Crystal Oscillator ................................................................................................................ 77

3.18 Meter Calibration ................................................................................................................. 78

4 Firmware Interface ....................................................................................................................... 79

4.1 I/O RAM and SFR Map –Functional Order .......................................................................... 79

4.2 I/O RAM Description – Alphabetical Order......................................................................... 83

4.3 CE Interface Description ..................................................................................................... 95

4.3.1 CE Program .............................................................................................................. 95

4.3.2 CE Data Format ........................................................................................................ 95

4.3.3 Constants .................................................................................................................. 95

4.3.4 Environment .............................................................................................................. 96

4.3.5 CE Calculations ......................................................................................................... 97

4.3.6 CE Front End Data (Raw Data).................................................................................. 97

4.3.7 CE Status and Control ............................................................................................... 98

4.3.8 CE Transfer Variables ............................................................................................. 100

4.3.9 Temperature Measurement and Temperature Compensation .................................. 102

4.3.10 Pulse Generation..................................................................................................... 102

4.3.11 Noise Suppression and Version Parameters ............................................................ 104

4.3.12 CE Calibration Parameters ...................................................................................... 104

4.3.13 CE Flow Diagrams .................................................................................................. 105

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

4 Rev 2

5 Electrical Specifications ............................................................................................................ 107

5.1 Absolute Maximum Ratings.............................................................................................. 107

5.2 Recommended External Components ............................................................................. 108

5.3 Recommended Operating Conditions .............................................................................. 108

5.4 Performance Specifications ............................................................................................. 109

5.4.1 Input Logic Levels ................................................................................................... 109

5.4.2 Output Logic Levels ................................................................................................. 109

5.4.3 Power-Fault Comparator ......................................................................................... 109

5.4.4 V2 Comparator (71M6534 only) ............................................................................... 109

5.4.5 Battery Monitor ........................................................................................................ 110

5.4.6 Supply Current ........................................................................................................ 110

5.4.7 V3P3D Switch ......................................................................................................... 110

5.4.8 2.5 V Voltage Regulator........................................................................................... 111

5.4.9 Low-Power Voltage Regulator ................................................................................. 111

5.4.10 Crystal Oscillator ..................................................................................................... 111

5.4.11 Optical Interface ...................................................................................................... 111

5.4.12 LCD DAC ................................................................................................................ 112

5.4.13 LCD Drivers ............................................................................................................ 112

5.4.14 Temperature Sensor................................................................................................ 113

5.4.15 VREF and VBIAS .................................................................................................... 114

5.4.16 ADC Converter, V3P3A Referenced ........................................................................ 115

5.5 Timing Specifications ....................................................................................................... 116

5.5.1 Flash Memory ......................................................................................................... 116

5.5.2 EEPROM Interface .................................................................................................. 116

5.5.3 RESET .................................................................................................................... 116

5.5.4 RTC ........................................................................................................................ 116

5.5.5 SPI Slave Port (MISSION Mode) ............................................................................. 117

5.6 Typical Performance Data ................................................................................................ 118

5.6.1 Accuracy over Current ............................................................................................. 118

5.6.2 Accuracy over Temperature..................................................................................... 119

5.7 Package Outline Drawings ............................................................................................... 119

5.7.1 71M6533 (100-Pin LQFP) ........................................................................................ 119

5.7.2 71M6534/6534H (120-Pin LQFP) ............................................................................ 120

5.8 Pinout ................................................................................................................................ 121

5.8.1 71M6533/71M6533G/71M6533H Pinout (100-Pin LQFP) ......................................... 121

5.8.2 71M6534/71M6534H Pinout (120-Pin LQFP) ........................................................... 122

5.9 Pin Descriptions ................................................................................................................ 123

5.9.1 Power and Ground Pins........................................................................................... 123

5.9.2 Analog Pins ............................................................................................................. 123

5.9.3 Digital Pins .............................................................................................................. 124

5.9.4 I/O Equivalent Circuits ............................................................................................. 126

6 Ordering Information ................................................................................................................. 127

7 Related Information ................................................................................................................... 127

8 Contact Information ................................................................................................................... 127

Appendix A: Acronyms ..................................................................................................................... 128

Appendix B: Revision History ........................................................................................................... 129

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 5

Figures

Figure 2: General Topology of a Chopped Amplifier ............................................................................... 12

Figure 4: AFE Block Diagram ................................................................................................................. 14

Figure 5: Samples from Multiplexer Cycle .............................................................................................. 17

Figure 7: Interrupt Structure ................................................................................................................... 36

Figure 8: Optical Interface ...................................................................................................................... 42

Figure 9: Connecting an External Load to DIO Pins ............................................................................... 46

Figure 11: 3-wire Interface. Write Command, HiZ=1 .............................................................................. 49

Figure 12: 3-wire Interface. Read Command. ........................................................................................ 49

Figure 13: 3-Wire Interface. Write Command when CNT=0 ................................................................... 49

Figure 15: SPI Slave Port: Read Operation with Gap ............................................................................. 51

Figure 16: SPI Slave Port: Typical Read and Write Operations .............................................................. 53

Figure 17: Functions Defined by V1 ....................................................................................................... 53

Figure 18: Voltage, Current, Momentary and Accumulated Energy ......................................................... 55

Figure 19: Timing Relationship between ADC MUX and Compute Engine .............................................. 56

Figure 20: RTM Output Format .............................................................................................................. 56

Figure 21: Operation Modes State Diagram ........................................................................................... 57

Figure 23: Power-Up Timing with V3P3SYS and VBAT Tied Together ................................................... 60

Figure 24: Power-Up Timing with VBAT Only ......................................................................................... 61

Figure 25: Functional Blocks in BROWNOUT Mode ............................................................................... 62

Figure 26: Functional Blocks in LCD Mode............................................................................................. 63

Figure 28: Wake Up Timing ................................................................................................................... 66

Figure 29: MPU/CE Data Flow ............................................................................................................... 66

Figure 30: MPU/CE Communication ...................................................................................................... 67

Figure 31: Resistive Voltage Divider ...................................................................................................... 68

Figure 32: CT with Single Ended (Left) and Differential Input (Right) Connection.................................... 68

Figure 33: Resistive Shunt (Left), Rogowski Sensor (Right) ................................................................... 68

Figure 34: Error Band for VREF over Temperature (Regular-Accuracy Parts) ........................................ 71

Figure 35: Error Band for VREF over Temperature (High-Accuracy Parts) ............................................. 71

Figure 36: Connecting LCDs .................................................................................................................. 73

Figure 37: I2C EEPROM Connection ...................................................................................................... 73

Figure 38: Three-Wire EEPROM Connection ......................................................................................... 74

Figure 39: Connections for UART0 ........................................................................................................ 74

Figure 40: Connection for Optical Components ...................................................................................... 75

Figure 41: Voltage Divider for V1 ........................................................................................................... 75

Figure 42: External Components for the RESET Pin: Push-Button (Left), Production Circuit (Right) ....... 76

Figure 43: External Components for the Emulator Interface ................................................................... 76

Figure 45: CE Data Flow: Multiplexer and ADC .................................................................................... 105

Figure 47: CE Data Flow: Squaring and Summation Stages ................................................................. 106

Figure 48: SPI Slave Port (MISSION Mode) Timing ............................................................................. 117

Figure 49: Wh Accuracy (0.1 A - 200 A, 240 V, Room Temperature) at Various Frequencies (Differential

Mode, CTs) .................................................................................................................................. 118

Figure 50: Typical Wh Accuracy (0.02 A - 200 A, 240 V, Room Temperature), Various Load Angles

(Differential Mode, CTs) ................................................................................................................ 118

Figure 51: 71M6533/71M6533G/71M6533H 100-Pin LQFP Package Outline ....................................... 119

Figure 52: 71M6534/6534H 120-Pin LQFP Package Outline ................................................................ 120

Figure 53: Pinout for 71M6533/71M6533G/71M6533H LQFP-100 Package ......................................... 121

Figure 54: Pinout for 71M6534/71M6534H LQFP-120 Package ........................................................... 122

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

6 Rev 2

Tables

Table 1: Signals Selected for the ADC with SLOTn_SEL and SLOTn_ALTSEL (MUX_DIV[3:0] = 7) ........... 11

Table 2: ADC Resolution ....................................................................................................................... 11

Table 3: ADC RAM Locations ................................................................................................................ 12

Table 4: XRAM Locations for ADC Results ............................................................................................ 15

Table 5: Inputs Selected in Regular and Alternate Multiplexer Cycles..................................................... 15

Table 6: CKMPU Clock Frequencies ...................................................................................................... 19

Table 7: Memory Map ............................................................................................................................ 20

Table 9: Special Function Register Map ................................................................................................. 21

Table 10: Generic 80515 SFRs - Location and Reset Values ................................................................. 22

Table 11: PSW Bit Functions (SFR 0xD0) ............................................................................................... 23

Table 12: Port Registers ........................................................................................................................ 24

Table 13: Stretch Memory Cycle Width .................................................................................................. 25

Table 14: 71M6533/71M6534 Specific SFRs ......................................................................................... 25

Table 16: UART Modes ......................................................................................................................... 27

Table 18: The S1CON (UART1) Register (SFR 0x9B) ............................................................................. 28

Table 19: PCON Register Bit Description (SFR 0x87) ............................................................................. 28

Table 20: Timers/Counters Mode Description ........................................................................................ 29

Table 21: Allowed Timer/Counter Mode Combinations ........................................................................... 29

Table 22: TMOD Register Bit Description (SFR 0x89) ............................................................................ 29

Table 23: The TCON Register Bit Functions (SFR 0x88) ........................................................................ 30

Table 24: The IEN0 Bit Functions (SFR 0xA8) ........................................................................................ 31

Table 25: The IEN1 Bit Functions (SFR 0xB8) ....................................................................................... 31

Table 26: The IEN2 Bit Functions (SFR 0x9A) ........................................................................................ 31

Table 27: TCON Bit Functions (SFR 0x88) ............................................................................................. 32

Table 28: The T2CON Bit Functions (SFR 0xC8) ................................................................................... 32

Table 29: The IRCON Bit Functions (SFR 0xC0) .................................................................................... 32

Table 30: External MPU Interrupts ......................................................................................................... 33

Table 31: Interrupt Enable and Flag Bits ................................................................................................ 33

Table 32: Interrupt Priority Level Groups ................................................................................................ 34

Table 33: Interrupt Priority Levels .......................................................................................................... 34

Table 35: Interrupt Polling Sequence ..................................................................................................... 35

Table 36: Interrupt Vectors .................................................................................................................... 35

Table 37: Clock System Summary ......................................................................................................... 37

Table 38: Bank Switching with FL_BANK[2:0] ........................................................................................ 41

Table 39: Data/Direction Registers and Internal Resources for DIO 1-15................................................ 43

Table 40: Data/Direction Registers and Internal Resources for DIO 16-30 .............................................. 43

Table 41: Data/Direction Registers and Internal Resources for DIO 36-47 .............................................. 44

Table 45: EECTRL Bits for the 3-wire Interface ....................................................................................... 48

Table 46: SPI Registers ......................................................................................................................... 50

Table 47: SPI Command Description ..................................................................................................... 51

Table 49: TMUX[4:0] Selections ............................................................................................................ 54

Table 50: Available Circuit Functions ..................................................................................................... 58

Table 51: VREF Definition for the Regular Accuracy Parts ..................................................................... 70

Table 52: VREF Definition for the High-Accuracy Parts .......................................................................... 70

Table 53: I/O RAM Map – Functional Order ........................................................................................... 79

Table 54: I/O RAM Description – Alphabetical (by Bit Name) ................................................................. 83

Table 55: CE EQU[2:0] Equations and Element Input Mapping .............................................................. 97

Table 56: CE Raw Data Access Locations ............................................................................................. 97

Table 57: CESTATUS (CE RAM 0x80) Bit Definitions .............................................................................. 98

Table 59: Sag Threshold and Gain Adjust Control ................................................................................ 100

Table 60: CE Transfer Variables .......................................................................................................... 100

Table 61: CE Energy Measurement Variables ...................................................................................... 101

Table 62: Other Transfer Variables ...................................................................................................... 102

Table 63: CE Temperature Registers ................................................................................................... 102

Table 65: CE Parameters for Noise Suppression and Code Version..................................................... 104

Table 66: CE Calibration Parameters ................................................................................................... 104

Table 67: Absolute Maximum Ratings .................................................................................................. 107

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 7

Table 68: Recommended External Components .................................................................................. 108

Table 69: Recommended Operating Conditions ................................................................................... 108

Table 70: Input Logic Levels ................................................................................................................ 109

Table 71: Output Logic Levels ............................................................................................................. 109

Table 72: Power-fault Comparator Performance Specifications ............................................................ 109

Table 73: V2 Comparator Performance Specifications ......................................................................... 109

Table 74: Battery Monitor Performance Specifications (BME = 1) ......................................................... 110

Table 75: Supply Current Performance Specifications .......................................................................... 110

Table 76: V3P3D Switch Performance Specifications ........................................................................... 110

Table 77: 2.5 V Voltage Regulator Performance Specifications ............................................................ 111

Table 78: Low-Power Voltage Regulator Performance Specifications ................................................... 111

Table 79: Crystal Oscillator Performance Specifications ....................................................................... 111

Table 80: Optical Interface Performance Specifications ........................................................................ 111

Table 81: LCD DAC Performance Specifications .................................................................................. 112

Table 82: LCD Driver Performance Specifications ................................................................................ 112

Table 83: Temperature Sensor Performance Specifications ................................................................. 113

Table 84: VREF Performance Specifications ........................................................................................ 114

Table 85: ADC Converter Performance Specifications ......................................................................... 115

Table 86: Flash Memory Timing Specifications .................................................................................... 116

Table 87: EEPROM Interface Timing ................................................................................................... 116

Table 88: RESET Timing ..................................................................................................................... 116

Table 89: RTC Range for Date ............................................................................................................ 116

Table 90: SPI Slave Port (MISSION Mode) Timing............................................................................... 117

Table 91: Power and Ground Pins ....................................................................................................... 123

Table 92: Analog Pins.......................................................................................................................... 123

Table 93: Digital Pins ........................................................................................................................... 124

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

8 Rev 2

Figure 1: IC Functional Block Diagram

∆Σ ADC

CONVERTER

VREF

MUX

XIN

XOUT

VREF

DIO1/OPT_RX

RESET

UART2/OPTICAL

UART1

COM3..0

LCD DISPLAY

DRIVER

DIGITAL I/O

RTCLK (32KHz)

POWER FAULT

GNDD V3P3A

V3P3D

VBAT

VOLT

REG

2.5V to logic

V2P5

TMUXOUT

FAULTZ

TMUX[4:0]

GNDA

VBIAS

OSC

(32 kHz)

MCK

PLL

VREF

TEST

MODE

DIO_DIR

DIO_R

DIO

E_RXTX

RTC

RST_SUBSEC

QREG,PREG

RTC_DAY

RTC_HR

RTC_MIN

RTC_SEC

VBIAS

ICE_E

PLS_INV

PLS_INTERVAL

PLS_MAXWIDTH

CE_LCTN

EQU

PRE_SAMPS

SUM_CYCLES

RTM_0...3

RTM_E

CE_E

OPT_RXDIS

OPT_RXINV

OPT_TXE

OPT_TXINV

OPT_TXMOD

OPT_FDC

LCD_ONLY

SLEEP

V3P3SYS

TEST

MUX

CE_PROG

CK_CE

CK_MPU

VADC

MULTI-

PURPOSE

I/O

RTM

RPULSE

WPULSE

COM0..3

Segments

DIO_1..24

to TMUX

SPI SLAVE

PCMD

EEPROM I/F

FLASH

128 KB/

256 KB

XRAM

4 KB

CE_DATA

PCSZ

PCLK

PSDI

PSDO

SDATA

SCLK

EEDATA

EECTRL

OPT_TX

OPT_RX

PB PB

IRAM

256B

MPU

EMULATOR

E_TCLK

E_RSTZ

DIO2/OPT_TX

DIO3

SEG7/MUX_SYNC

SEG8

SEG9/E_RXTX

SEG10/E_TCLK

SEG11/E_RST

SEG12 ...SEG18

SEG19/CKTEST

DIO29/SEG49...DIO30/SEG50

DIO4/SEG24/SDCK

DIO5/SEG25/SDATA

DIO6/SEG26/WPULSE

DIO7/SEG27/RPULSE

DIO10/SEG30...DIO11/SEG31

DIO41/SEG61

RPULSE

WPULSE

XRAM BUS

IRAM BUS

16 32

CKTEST

DIO_PV

DIO_PW

CKOUT_E

SPE

DIO_EEX

OPT_TXE

ICE_E

SEG0...SEG2

SEG3/PCLK

SEG4/PSDO

SEG5/PCSZ

SEG6/PSDI

FIR

DIO23/SEG43...DIO27/SEG47

DIO13/SEG33...DIO21/SEG41

XPULSE

YPULSE

XPULSE

YPULSE

DIO_PX

DIO_PY

DIO8/SEG28/XPULSE

DIO9/SEG29/YPULSE

SEG20...SEG23

DIO56...DIO58

ICE_E

GP0-GP7

NV RAM

2.5V_NV

RTCA_ADJ

RTC_DATE

RTC_MO

RTC_YR

LCD_DAC

LCD_MODE

LCD_CLK

LCD_E

LCD_BLKMAP

LCD_SEG

LCD_Y

MPU_DIV

CKOUT_E

IBP

ICP

IAP

IAN

IBN

ICN

IDP

IDN

DIO43/SEG63...DIO45/SEG65

DIO47/SEG67...DIO51/SEG71

5/24/2010

V2_OK*

V3_OK*

VBIAS*

V3*

V2*

* 71M6534 only

DIO12/SEG32*

DIO22/SEG42*

DIO28/SEG48*

DIO36/SEG56*...DIO39/SEG59*

DIO42/SEG62*

DIO46/SEG66*

DIO52/SEG72*...DIO55/SEG75*

TEMP

VBAT

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 9

1 Hardware Description

1.1 Hardware Overview

The Teridian 71M6533 and 71M6534 single-chip energy meter integrate all primary functional blocks

required to implement a solid-state electricity meter. Included on the chip are:

• An analog front end (AFE)

• An Independent digital computation engine (CE)

• An 8051-compatible microprocessor (MPU) which executes one instruction per clock cycle (80515)

• A voltage reference

• A temperature sensor

• LCD drivers

• RAM and Flash memory

• A real time clock (RTC)

• A variety of I/O pins

Various current sensor technologies are supported including Current Transformers (CT), Resistive Shunts

and Rogowski coils.

In a typical application, the 32-bit compute engine (CE) of the 71M6533/71M6534 sequentially processes

the samples from the voltage inputs on analog input pins and performs calculations to measure active

energy (Wh) and reactive energy (VARh), as well as A2h, and V2h for four-quadrant metering. These

measurements are then accessed by the MPU, processed further and output using the peripheral devices

available to the MPU.

In addition to advanced measurement functions, the real time clock function allows the 71M6533/71M6534

to record time of use (TOU) metering information for multi-rate applications and to time-stamp tamper

events. Measurements can be displayed on 3.3 V LCDs commonly used in low-temperature environments.

Flexible mapping of LCD display segments facilitate integration of existing custom LCDs. Design trade-offs

between the number of LCD segments and DIO pins can be implemented in software to accommodate

various requirements.

In addition to the temperature-trimmed ultra-precision voltage reference, the on-chip digital temperature

compensation mechanism includes a temperature sensor and associated controls for correction of unwanted

temperature effects on measurement and RTC accuracy, e.g. to meet the requirements of ANSI and IEC

standards. Temperature dependent external components such as a crystal oscillator, current transformers

(CTs) and their corresponding signal conditioning circuits can be characterized and their correction factors

can be programmed to produce electricity meters with exceptional accuracy over the industrial temperature

range.

One of the two internal UARTs is adapted to support an Infrared LED with internal drive and sense

configuration and can also function as a standard UART. The optical output can be modulated at 38 kHz.

This flexibility makes it possible to implement AMR meters with an IR interface. A block diagram of the IC

is shown in Figure 1.

1.2 Analog Front End (AFE)

The AFE of the 71M6533/71M6534 consists of an input multiplexer, a delta-sigma A/D converter and a

voltage reference.

1.2.1 Signal Input Pins

All analog signal input pins are sensitive to voltage. The VA, VB, and VC pins are single-ended. Pins

IAP/IAN, IBP/IBN, ICP/ICN, and IDP/IDN can be programmed individually to be differential or single-ended.

The differential signal is applied between the InP and InN input pins. Single-ended signals are applied to

the InP input while the common signal, return, is the V3P3A pin. When using the differential mode, inputs

can be chopped, i.e., a connection from V3P3A to InP or InN alternates in each multiplexer cycle.

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

10 Rev 2

1.2.2 Input Multiplexer

The input multiplexer applies the input signals from the pins IAP/IAN, VA, IBP/IBN, VB, ICP/ICN, VC, and

IDP/IDN to the input of the ADC. Additionally, using the alternate multiplexer selection, it has the ability to

select temperature and the battery voltage. One input is applied per time slot.

The multiplexer can implement from one to 10 time slots (states) per frame as controlled by the I/O RAM

field MUX_DIV[3:0]. The multiplexer always starts at state 1 and proceeds until as many states as defined

by MUX_DIV[3:0] have been converted.

The multiplexer can be operated in two modes:

• During a normal multiplexer cycle (MUX_ALT = 0), the signals selected in the I/O RAM SLOTn_SEL[3:0]

fields are processed. These are typically the signals from the IA, IB, IC, ID and VA, VB, and VC pins.

• During the alternate multiplexer cycle (MUX_ALT = 1), the signals selected in the SLOTn_SEL[3:0] fields

are processed. These signals typically comprise the temperature signal (TEMP), the battery monitor

(VBAT) and some of the voltage signals such as VA, VB, and VC. To prevent unnecessary drainage on

the battery, the battery monitor is enabled only with the BME bit (IO RAM 0x2020[6]).

The alternate multiplexer cycles are usually performed infrequently (every second or so) by the MPU. In

order to prevent disruption of the voltage tracking mechanism and voltage allpass networks of the CE,

VA, VB, and VC are not replaced in the alternate cycles.

The current inputs can be configured to be used in differential mode, using the pin pairs IAP/IAN,

IBP/IBN, ICP/ICN, and IDP/IDN. The fourth current input is available to support measurement of a fourth

or neutral phase.

In a typical application, IAP/IAN, IBP/IBN, ICP/ICN, and IDP/IDN are connected to current transformers

that sense the current on each phase of the line voltage. VA, VB, and VC are typically connected to the

phase voltages via resistor dividers.

Multiplexer advance, FIR initiation and VREF chopping are controlled by the internal MUX_CTRL signal.

Additionally, MUX_CTRL launches each pass through the CE program. Conceptually, MUX_CTRL is

clocked by CK32, the 32768Hz clock from the PLL block. The behavior of MUX_CTRL is governed by

MUX_ALT, EQU[2:0], CHOP_E[1:0], and MUX_DIV[3:0].

The MUX_ALT bit requests an alternative multiplexer frame. The bit may be asserted on any MPU cycle

and may be subsequently deasserted on any cycle including the next one. A rising edge on MUX_ALT will

cause MUX_CTRL to wait until the next multiplexer frame and implement a single alternate multiplexer frame.

The inputs converted during normal and alternate frames are selectable using the pointers to signals.

SLOTn_SEL[3:0] selects the input signal for the nth state in a standard multiplexer frame, while

SLOTn_ALTSEL[3:0] selects the input for the nth state in an alternate multiplexer frame. For example, if

SLOT0_SEL[3:0] contains 0 and SLOT1_SEL[3:0] contains 1, signal selection 0, equivalent to IA (see Table 1),

will be applied for the first time slot, while signal 1, equivalent to VA, will be applied for the second time

slot. See Table 1 for a typical assignment of values for the SLOTn_SEL[3:0] and SLOTn_ALTSEL[3:0]

registers assuming seven time slots (MUX_DIV[3:0] = 7) for the processing of three voltage and current

phases plus an additional neutral current.

The correlation between signal numbers, CE memory addresses, and analog signals is given in Table 3.

For the processing of three voltage and current phases in a typical polyphase meter without neutral

measurement, MUX_DIV[3:0] is set to 6, and SLOT6_SEL[3:0] as well as SLOT6_ALTSEL[3:0] would be

empty.

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 11

Table 1: Signals Selected for the ADC with SLOTn_SEL and SLOTn_ALTSEL (MUX_DIV[3:0] = 7)

Time

Slot

Regular Slot

Alternate Slot

Typical Selections

Signal

Number

Signal for

ADC

Signal

Number

Signal for

ADC

SLOT0_SEL[3:0]

SLOT0_ALTSEL[3:0]

TEMP

SLOT1_SEL[3:0]

SLOT1_ALTSEL[3:0]

SLOT2_SEL[3:0]

SLOT2_ALTSEL[3:0]

VBAT

SLOT3_SEL[3:0]

SLOT3_ALTSEL[3:0]

SLOT4_SEL[3:0]

SLOT4_ALTSEL[3:0]

SLOT5_SEL[3:0]

SLOT5_ALTSEL[3:0]

SLOT6_SEL[3:0]

SLOT6_ALTSEL[3:0]

SLOT7_SEL[3:0]

–

SLOT7_ALTSEL[3:0]

SLOT8_SEL[3:0]

–

SLOT8_ALTSEL[3:0]

SLOT9_SEL[3:0]

–

SLOT9_ALTSEL[3:0]

The duration of each multiplexer state depends on the number of ADC samples processed by the FIR,

which is set by FIR_LEN[1:0]. Each multiplexer state will start on the rising edge of CK32. FIR conversions

require 1, 2, or 3 CK32 cycles. The number of CK32 cycles is determined by FIR_LEN[1:0].

1.2.3 A/D Converter (ADC)

A single delta-sigma A/D converter digitizes the voltage and current inputs to the 71M6533/71M6534. The

resolution of the ADC is programmable using the I/O RAM bits M40MHZ and M26MHZ (see Table 2). The

CE code must be tailored for use with the selected ADC resolution.

Table 2: ADC Resolution

Setting for [M40MHZ,

M26MHZ] FIR_LEN[1:0] FIR CE

Cycles Resolution

[00], [10] or [11]

138

288

384

18 bits

21 bits

22 bits

[01]

186

384

588

19 bits

22 bits

24 bits

Initiation of each ADC conversion is controlled by MUX_CTRL as described in Section 1.1.1. At the end of

each ADC conversion, the FIR filter output data is stored into the CE RAM location determined by the MUX

selection.

1.2.4 FIR Filter

The finite impulse response filter is an integral part of the ADC and it is optimized for use with the multiplexer.

The purpose of the FIR filter is to decimate the ADC output to the desired resolution. At the end of each

ADC conversion, the output data is stored into the fixed CE RAM location determined by the multiplexer

selection as shown in Table 3. FIR data is stored LSB justified, but shifted left by eight bits.

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

12 Rev 2

Table 3: ADC RAM Locations

Signal Number

Address

(HEX) Name Signal Number

Address

(HEX) Name

0x00

0x05

0x01

0x06

0x02

0x0A

TEMP

0x03

0x0B

VBAT

0x04

1.2.5 Voltage References

The device includes an on-chip precision bandgap voltage reference that incorporates auto-zero techniques.

The reference is trimmed in production to minimize errors caused by component mismatch and drift. The

result is a voltage output with a predictable temperature coefficient.

The amplifier within the reference is chopper stabilized, i.e. the polarity can be switched by the MPU using

CHOP_E[1:0] (I/O RAM 0x2002[5:4]). The CHOP_E[1:0] field enables the MPU to operate the chopper

circuit in regular or inverted operation, or in toggling mode. When the chopper circuit is toggled in between

multiplexer cycles, DC offsets on the measured signals will automatically be averaged out.

The general topology of a chopped amplifier is shown in Figure 2.

Figure 2: General Topology of a Chopped Amplifier

It is assumed that an offset voltage Voff appears at the positive amplifier input. With all switches, as

controlled by CROSS, in the A position, the output voltage is:

Voutp – Voutn = G (Vinp + Voff – Vinn) = G (Vinp – Vinn) + G Voff

With all switches set to the B position by applying the inverted CROSS signal, the output voltage is:

Voutn – Voutp = G (Vinn – Vinp + Voff) = G (Vinn – Vinp) + G Voff, or

Voutp – Voutn = G (Vinp – Vinn) - G Voff

Thus, when CROSS is toggled, e.g. after each multiplexer cycle, the offset will alternately appear on the

output as positive and negative, which results in the offset effectively being eliminated, regardless of its

polarity or magnitude.

When CROSS is high, the connection of the amplifier input devices is reversed. This preserves the overall

polarity of that amplifier gain; it inverts its input offset. By alternately reversing the connection, the

amplifier’s offset is averaged to zero. This removes the most significant long-term drift mechanism in the

voltage reference. The CHOP_E[1:0] field controls the behavior of CROSS. The CROSS signal will reverse

the amplifier connection in the voltage reference in order to negate the effects of its offset. On the first

CK32 rising edge after the last multiplexer state of its sequence, the multiplexer will wait one additional

CK32 cycle before beginning a new frame. At the beginning of this cycle, the value of CROSS will be

updated according to the CHOP_E[1:0] field. The extra CK32 cycle allows time for the chopped VREF to

settle. During this cycle, MUXSYNC is held high. The leading edge of MUXSYNC initiates a pass through

the CE program sequence. The beginning of the sequence is the serial readout of the four RTM words.

inp

outp

outn

inn

CROSS

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 13

CHOP_E[1:0] has four states: positive, reverse, and two toggle states. In the positive state, CHOP_E[1:0]

= 01, CROSS and CHOP_CLK are held low. In the reverse state, CHOP_E[1:0] = 10, CROSS and

CHOP_CLK are held high. In the first toggle state, CHOP_E [1:0] = 00, CROSS is automatically toggled

near the end of each multiplexer frame and an ALT frame is forced during the last multiplexer frame in each

SUM cycle. It is desirable that CROSS take on alternate values during each ALT frame. For this reason,

if CHOP_E[1:0] = 00, CROSS will not toggle at the end of the multiplexer frame immediately preceding the

ALT frame in each accumulation interval.

Figure 3: CROSS Signal with CHOP_E[1:0] = 00

Figure 3 shows CROSS over two accumulation intervals when CHOP_E[1:0] = 00. At the end of the

first interval, CROSS is low, at the end of the second interval, CROSS is high. The offset error for

the two temperature measurements taken during the ALT multiplexer frames will be averaged to zero.

Note that the number of multiplexer frames in an accumulation interval is always even. Operation

with CHOP_E[1:0] = 00 does not require control of the chopping mechanism by the MPU while eliminating

the offset for temperature measurement.

In the second toggle state, CHOP_E[1:0] = 11, no ALT frame is forced during the last multiplexer cycle in

an accumulation interval, and CROSS always toggles near the end of each multiplexer frame.

The internal bias voltage, VBIAS (typically 1.6 V), is used by the ADC as a reference when measuring the

temperature and battery monitor signals.

1.2.6 Temperature Sensor

The 71M6533 and 71M6534 include an on-chip temperature sensor implemented as a bandgap reference.

It is used to determine the die temperature. The MPU may request an alternate multiplexer cycle containing

the temperature sensor output by asserting MUX_ALT.

The primary use of the temperature data is to determine the magnitude of compensation required to offset

the thermal drift in the system (see Section 3.5 Temperature Compensation).

1.2.7 Battery Monitor

The battery voltage is measured by the ADC during alternative multiplexer frames if the BME (Battery

Measure Enable) bit in the I/O RAM is set. While BME is set, an on-chip 45 kΩ load resistor is applied to

the battery and a scaled fraction of the battery voltage is applied to the ADC input. After each alternative

MUX frame, the result of the ADC conversion is available at XRAM address 0x0B. BME is ignored and

assumed zero when system power is not available (V1 < VBIAS). See Section 6.4.5 for details regarding

the ADC LSB size and the conversion accuracy.

1.2.8 AFE Functional Description

The AFE functions as a data acquisition system, controlled by the MPU. The main signals (IA, VA, IB,

VB, etc.) are sampled and the ADC counts obtained are stored in XRAM where they can be accessed by

the CE and, if necessary, by the MPU. Alternate multiplexer cycles are initiated less frequently by the

MPU to gather access to the slow temperature and battery signals.

Figure 4 shows the block diagram of the AFE.

Multiplexer frames

Accumulation interval n Accumulation interval n+1

2 43 251925201 2 43 251925201

Alternative MUX cycle

Multiplexer frames

Alternative MUX cycle

CROSS CROSS

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

14 Rev 2

∆Σ ADC

CONVERTER

VREF

VB_REF

ADC_E

MUX

VREF

VBIAS

TEMP

VREF

VBIAS

VREF_CAL

VREF_DIS

VBAT

VADC

EQU

MUX_ALT

MUX_DIV

FIR

FIR_LEN

IBP

ICP

IAP

IAN

IBN

ICN

IDN

IDP

Figure 4: AFE Block Diagram

1.3 Digital Computation Engine (CE)

The CE, a dedicated 32-bit signal processor, performs the precision computations necessary to accurately

measure energy. The CE calculations and processes include:

• Multiplication of each current sample with its associated voltage sample to obtain the energy per

sample (when multiplied with the constant sample time).

• Frequency-insensitive delay cancellation on all six channels (to compensate for the delay between

samples caused by the multiplexing scheme).

• 90° phase shifter (for VAR calculations).

• Pulse generation.

• Monitoring of the input signal frequency (for frequency and phase information).

• Monitoring of the input signal amplitude (for sag detection).

• Scaling of the processed samples based on calibration coefficients. Scaling of all samples based on

temperature compensation information.

The CE program resides in flash memory. Common access to flash memory by the CE and MPU is controlled

by a memory share circuit. Each CE instruction word is two bytes long. Allocated flash space for the CE

program cannot exceed 4096 16-bit words (8 KB). The CE program counter begins a pass through the

CE code each time multiplexer state 0 begins. The code pass ends when a HALT instruction is executed.

For proper operation, the code pass must be completed before the multiplexer cycle ends (see Section

2.2 System Timing Summary).

The CE program must begin on a 1-KB boundary of the flash address. The I/O RAM register CE_LCTN[7:0]

defines which 1-KB boundary contains the CE code. Thus, the first CE instruction is located at

1024*CE_LCTN[7:0].

The CE can access up to 4 KB of data RAM (XRAM), or 1024 32-bit data words, starting at RAM address

0x0000.

The XRAM can be accessed by the FIR filter block, the RTM circuit, the CE, and the MPU. Assigned time

slots are reserved for FIR and MPU, respectively, to prevent bus contention for XRAM data access.

The MPU can read and write the XRAM shared between the CE and MPU as the primary means of data

communication between the two processors.

Table 4 shows the CE addresses in XRAM allocated to analog inputs from the AFE.

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 15

Table 4: XRAM Locations for ADC Results

Address (HEX)

Name

Description

0x00

Phase A current

0x01

Phase A voltage

0x02

Phase B current

0x03

Phase B voltage

0x04

Phase C current

0x05

Phase C voltage

0x06

Neutral current

0x07 – 0x09

–

Not used

0x0A

TEMP

Temperature

0x0B

VBAT

Battery Voltage

The CE is aided by support hardware to facilitate implementation of equations, pulse counters, and

accumulators. This hardware is controlled through I/O RAM locations EQU[2:0] (equation assist), the

DIO_PV and DIO_PW (pulse count assist) bits, and PRE_SAMPS[1:0] and SUM_CYCLES[5:0] (accumulation

assist).

PRE_SAMPS[1:0] and SUM_CYCLES[5:0] support a dual-level accumulation scheme where the first

accumulator accumulates results from PRE_SAMPS[1:0] samples and the second accumulator accumulates

up to SUM_CYCLES[5:0] of the first accumulator results. The integration time for each energy output is

PRE_SAMPS[1:0] * SUM_CYCLES[5:0] / 2520.6 (with MUX_DIV[3:0] = 6). CE hardware issues the

XFER_BUSY interrupt when the accumulation is complete.

1.3.1 Meter Equations

The 71M6533 and 71M6534 provide hardware assistance to the CE in order to support various meter

equations. This assistance is controlled through the I/O RAM field EQU[2:0] (equation assist). The

Compute Engine (CE) firmware for industrial configurations can implement the equations listed in Table 5.

EQU[2:0] specifies the equation to be used based on the meter configuration and on the number of phases

used for metering.

Table 5: Inputs Selected in Regular and Alternate Multiplexer Cycles

EQU[2:0]

Description

Wh and VARh formula

Mux

Sequence

ALT Mux

Sequence

Element

1 element, 2 W,

1φ with neutral

current sense

VA ∙ IA VA ∙ IB N/A

Sequence is

programmable

with

SLOTn_SEL[3:0]

Sequence is

programmable with

SLOTn_ALTSEL[3:0]

1 element, 3 W, 1φ

VA(IA-IB)/2

N/A

2 element, 3 W,

3φ Delta

VA ∙ IA VB ∙ IB N/A

2 element, 4 W,

3φ Delta

VA(IA-IB)/2 N/A VC ∙IC

2 element, 4 W,

3φ Wye

VA(IA-IB)/2 VB(IC-IB)/2

N/A

3 element, 4 W,

3φ Wye

VA ∙ IA VB ∙ IB VC ∙ IC

Not all CE codes support all equations.

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

16 Rev 2

1.3.2 Real-Time Monitor

The CE contains a Real-Time Monitor (RTM), which can be programmed to monitor four selectable XRAM

locations at full sample rate. The four monitored locations are serially output to the TMUXOUT pin via the

digital output multiplexer at the beginning of each CE code pass. The RTM can be enabled and disabled

with the RTM_E bit. The RTM output is clocked by CKTEST (pin SEG19/CKTEST), with the clock output

enabled by setting CKOUT_E = 1. Each RTM word is clocked out in 35 cycles and contains a leading flag

bit. See Figure 20 for the RTM output format. RTM is low when not in use.

1.3.3 Pulse Generators

The 71M6533 and 71M6534 provide four pulse generators, RPULSE, WPULSE, XPULSE and YPULSE,

as well as hardware support for the RPULSE and WPULSE pulse generators. The pulse generators can

be used to output CE status indicators, SAG for example, to DIO pins.

The polarity of the pulses may be inverted with PLS_INV bit. When this bit is set, the pulses are active

high, rather than the more usual active low. PLS_INV inverts all the pulse outputs.

XPULSE and YPULSE

Pulses generated by the CE may be exported to the XPULSE and YPULSE pulse outputs. Pins DIO8

and DIO9 are used for these pulses. Generally, the XPULSE and YPULSE outputs are updated once on

each pass of the CE code, resulting in a pulse frequency up to a maximum of 1260Hz (assuming a MUX

frame is 13 CK32 cycles).

Standard CE code permits the selection of either an energy indication or signaling of a sag event for the

YPULSE output. This method is faster than checking the sag bits by the MPU at every CE_BUSY interrupt.

See Section 5.3 CE Interface Description for details.

RPULSE and WPULSE

During each CE code pass, the hardware stores exported WPULSE and RPULSE sign bits in an 8-bit

FIFO and outputs them at a specified interval. This permits the CE code to calculate the RPULSE and

WPULSE outputs at the beginning of its code pass and to rely on hardware to spread them over the MUX

frame. The FIFO is reset at the beginning of each MUX frame. The PLS_INTERVAL register controls the

delay to the first pulse update and the interval between subsequent updates. The LSB of this register is

equivalent to 4 CK_FIR cycles. If zero, the FIFO is deactivated and the pulse outputs are updated

immediately. Thus, NINTERVAL is 4 * PLS_INTERVAL.

Since the FIFO resets at the beginning of each MUX frame, the user must specify PLS_INTERVAL so that

all of the pulse updates are output before the MUX frame completes. For instance, if the CE code outputs

6 updates per MUX interval, and if the MUX interval is 1950 cycles long, the ideal value for the interval is

1950/6/4 = 81.25. If PLS_INTERVAL = 82, the fifth output will occur too late and be lost. In this case, the

proper value for PLS_INTERVAL is 81.

Hardware also provides a maximum pulse width feature. The PLS_MAXWIDTH register selects a maximum

negative pulse width to be Nmax updates according to the formula: Nmax = (2 * PLS_MAXWIDTH + 1). If

PLS_MAXWIDTH = 255, no width checking is performed.

The WPULSE and RPULSE pulse generator outputs are available on DIO6 and DIO7, respectively. They

can also be output on OPT_TX (see OPT_TXE[1:0] for details).

1.3.4 Data RAM (XRAM)

The CE and MPU use a single general-purpose Data RAM (also referred to as XRAM). The Data RAM is

1024 32-bit words, shared between the CE and the MPU using a time-multiplex method. This reduces

MPU wait states when accessing CE data. When the MPU and CE are clocking at maximum frequency

(10 MHz), the DRAM will make up to four accesses during each 100 ns interval. These consist of two

MPU accesses, one CE access and one SPI access.

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 17

The Data RAM is 32 bits wide and uses an external multiplexer so as to appear byte-wide to the MPU.

The Data RAM hardware will convert an MPU byte write operation into a read-modify-write operation that

requires two Data RAM accesses. The second access is guaranteed to be available because the MPU

cannot access the XRAM on two consecutive instructions unless it is using the same address.

In addition to the reduction of wait states, this arrangement permits the MPU to easily use unneeded CE

data memory. Likewise, the amount of memory the CE uses is not limited by the size of a dedicated CE

data RAM.

1.3.5 CE Functional Overview

The ADC processes one sample per channel per multiplexer cycle. Figure 5 shows the timing of the

samples taken during one multiplexer cycle (phases A, B, and C being processed). During an ALT

multiplexer sequence, missing samples are filled in by the CE.

The number of samples processed during one accumulation cycle is controlled by PRE_SAMPS[1:0] (I/O

RAM 0x2001[7:6]) and SUM_CYCLES[5:0] (I/O RAM 0x2001[5:0]). The integration time for each energy

output is:

PRE_SAMPS[1:0] * SUM_CYCLES[5:0] / 2520.6, where 2520.6 is the sample rate in Hz

For example, PRE_SAMPS[1:0] = 42 and SUM_CYCLES[5:0] = 50 will establish 2100 samples per accumulation

cycle. PRE_SAMPS[1:0] = 100 and SUM_CYCLES[5:0] = 21 will result in the exact same accumulation

cycle of 2100 samples or 833 ms. After an accumulation cycle is completed, the XFER_BUSY interrupt

signals to the MPU that accumulated data are available.

Figure 5: Samples from Multiplexer Cycle

The end of each multiplexer cycle is signaled to the MPU by the CE_BUSY interrupt. At the end of each

multiplexer cycle, status information, such as sag data and the digitized input signal, is available to the MPU.

1/2520.6Hz = 397µs

2/32768Hz =

61.04µs

13/32768Hz = 397µs

per mux cycle

1/2520.6Hz = 397µs

2/32768Hz =

61.04µs

13/32768Hz = 397µs

per mux cycle

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

18 Rev 2

Figure 6: Accumulation Interval

Figure 6 shows the accumulation interval resulting from PRE_SAMPS[1:0] = 42 and SUM_CYCLES[5:0] = 50,

consisting of 2100 samples of 397µs each, followed by the XFER_BUSY interrupt. The sampling in this

example is applied to a 50 Hz signal.

There is no correlation between the line signal frequency and the choice of PRE_SAMPS[1:0] or

SUM_CYCLES[5:0] (even though when SUM_CYCLES[5:0] = 42, one set of SUM_CYCLES happens to

sample a period of 16.6 ms). Furthermore, sampling does not have to start when the line voltage crosses

the zero line, and the length of the accumulation interval need not be an integer multiple of the signal cycles.

1.3.6 Delay Compensation

When measuring the energy of a phase (i.e., Wh and VARh) in a service, the voltage and current for that

phase must be sampled at the same instant. Otherwise, the phase difference, Ф, introduces errors.

delay

t360360 ⋅⋅=⋅=

Where f is the frequency of the input signal and tdelay is the sampling delay between voltage and current.

In traditional meter ICs, sampling is accomplished by using two A/D converters per phase (one for voltage

and the other one for current) controlled to sample simultaneously. Our Single Converter Technology,

however, exploits the 32-bit signal processing capability of its CE to implement “constant delay” all-pass

filters. These all-pass filters correct for the conversion time difference between the voltage and the

corresponding current samples that are obtained with a single multiplexed A/D converter.

The “constant delay” all-pass filters provide a broad-band delay β that is precisely matched to the differ-

ence in sample time between the voltage and the current of a given phase. This digital filter does not

affect the amplitude of the signal, but provides a precisely controlled phase response. The delay

compensation implemented in the CE aligns the voltage samples with their corresponding current

samples by routing the voltage samples through the all-pass filter, thus delaying the voltage samples by

β, resulting in the residual phase error β – Ф. The residual phase error is negligible, and is typically less

than ±1.5 millidegrees at 100Hz, thus it does not contribute to errors in the energy measurements.

XFER_BUSY

Interrupt to MPU

20ms

833ms

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 19

1.4 80515 MPU Core

The 71M6533 and 71M6534 include an 80515 MPU (8-bit, 8051-compatible) that processes most instructions

in one clock cycle. Using a 10 MHz clock results in a processing throughput of 10 MIPS. The 80515

architecture eliminates redundant bus states and implements parallel execution of fetch and execution

phases. Normally, a machine cycle is aligned with a memory fetch, therefore, most of the 1-byte instructions

are performed in a single machine cycle (MPU clock cycle). This leads to an 8x average performance

improvement (in terms of MIPS) over the Intel 8051 device running at the same clock frequency.

Table 6 shows the CKMPU frequency as a function of the allowed combinations of the MPU clock divider

MPU_DIV[2:0] and the MCK divider bits M40MHZ and M26MHZ. Actual processor clocking speed can be

adjusted to the total processing demand of the application (metering calculations, AMR management, memory

management, LCD driver management and I/O management) using the I/O RAM field MPU_DIV[2:0] and

the MCK divider bits M40MHZ and M26MHZ, as shown in Table 6.

Table 6: CKMPU Clock Frequencies

MPU_DIV [2:0] [M40MHZ, M26MHZ] Values

[1,0]

[0,1]

[0,0]

000

9.8304 MHz

6.5536 MHz

4.9152 MHz

001

4.9152 MHz

3.2768 MHz

2.4576 MHz

010

2.4576MHz

1.6384 MHz

1.2288 MHz

011

1.2288 MHz

819.2 kHz

614.4 kHz

100

614.4 kHz

409.6 kHz

307.2 kHz

101

307.2 kHz

204.8 kHz

153.6 kHz

110

153.6 kHz

102.4 kHz

76.8 kHz

111

153.6 kHz

102.4 kHz

76.8 kHz

Typical measurement and metering functions based on the results provided by the internal 32-bit compute

engine (CE) are available for the MPU as part of Maxim’s Teridian standard library, which provides

demonstration source code to help reduce the design cycle.

1.4.1 Memory Organization and Addressing

The 80515 MPU core incorporates the Harvard architecture with separate code and data spaces. Memory

organization in the 80515 is similar to that of the industry standard 8051. There are four memory areas:

Program memory (Flash, shared by MPU and CE), external RAM (Data RAM, shared by the CE and MPU,

Configuration or I/O RAM) and internal data memory (Internal RAM). Table 7 shows the memory map.

Program Memory

The 80515 can address up to 64 KB of program memory space from 0x0000 to 0xFFFF. Program memory

is read when the MPU fetches instructions or performs a MOVC operation. Access to program memory

above 0x7FFF is controlled by the FL_BANK[2:0] SFR register (SFR 0xB6).

After reset, the MPU starts program execution from program memory location 0x0000. The lower part of

the program memory includes reset and interrupt vectors. The interrupt vectors are spaced at 8-byte

intervals, starting from 0x0003.

MPU External Data Memory (XRAM)

Both internal and external memory is physically located on the 71M6533/71M6534 device. The external

memory referred to in this documentation is only external to the 80515 MPU core.

4 KB of RAM starting at address 0x0000 is shared by the CE and MPU. The CE normally uses the first

1 KB, leaving 3 KB for the MPU. Different versions of the CE code use varying amounts. Consult the

documentation for the specific code version being used for the exact limit.

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

20 Rev 2

If the MPU overwrites the CE’s working RAM, the CE’s output may be corrupted. If the CE is

disabled, the first 0x40 bytes of RAM are still unusable while MUX_DIV[3:0] ≠ 0 because the

71M6533/71M6534 ADC writes to these locations. Setting MUX_DIV[3:0] = 0 disables the ADC

output, preventing the CE from writing the first 0x40 bytes of RAM.

The 80515 writes into external data memory when the MPU executes a MOVX @Ri,A or MOVX

@DPTR,A instruction. The MPU reads external data memory by executing a MOVX A,@Ri or MOVX

A,@DPTR instruction (SFR PDATA provides the upper 8 bytes for the MOVX A,@Ri instruction).

Internal and External Memory Map

Table 7 shows the address, type, use and size of the various memory components.

Only the memory ranges shown in Table 7 contain physical memory.

Table 7: Memory Map

Address

(hex)

Memory

Technology

Memory

Type Name Typical Usage Memory Size

(bytes)

00000-1FFFF Flash Memory

Non-

volatile

Program memory

MPU Program and

non-volatile data

128 KB

00000-3FFFF† Flash Memory

Non-

volatile

Program memory

MPU Program and

non-volatile data

256 KB†

on 1K

boundary

Flash Memory

Non-

volatile

Program memory CE program 8 KB max.

0000-0FFF Static RAM Volatile

External RAM

(XRAM)

Shared by CE and

MPU

4 KB

2000-20BF,

20C8-20FF

Static RAM Volatile

Configuration RAM

(I/O RAM)

Hardware control 256

20C0-20C7 Static RAM

Non-

volatile

(battery)

Configuration RAM

(I/O RAM)

Battery-buffered

memory 8

0000-00FF

Static RAM

Volatile

Internal RAM

Part of 80515 Core

256

† For the 71M6534 only.

MOVX Addressing

There are two types of instructions differing in whether they provide an 8-bit or 16-bit indirect address to

the external data RAM.

In the first type, MOVX A,@Ri, the contents of R0 or R1 in the current register bank provide the eight

lower-ordered bits of address. The eight high-ordered bits of the address are specified with the PDATA

SFR. This method allows the user paged access (256 pages of 256 bytes each) to all ranges of the

external data RAM.

In the second type of MOVX instruction, MOVX A,@DPTR, the data pointer generates a 16-bit address.

This form is faster and more efficient when accessing very large data arrays (up to 64 KB), since no

additional instructions are needed to set up the eight high ordered bits of the address.

It is possible to mix the two MOVX types. This provides the user with four separate data pointers, two

with direct access and two with paged access, to the entire 64 KB of external memory range.

Dual Data Pointer

The Dual Data Pointer accelerates the block moves of data. The standard DPTR is a 16-bit register that

is used to address external memory or peripherals. In the 80515 core, the standard data pointer is called

DPTR, the second data pointer is called DPTR1. The data pointer select bit, located in the LSB of the DPS

when DPS[0] = 1.

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 21

The user switches between pointers by toggling the LSB of the DPS register. The values in the data pointers

are not affected by the LSB of the DPS register. All DPTR related instructions use the currently selected

DPTR for any activity.

The second data pointer may not be supported by certain compilers.

DPTR1 is useful for copy routines, where it can make the inner loop of the routine two instructions

faster compared to the reloading of DPTR from registers. Any interrupt routine using DPTR1 must save

and restore DPS, DPTR and DPTR1, which increases stack usage and slows down interrupt latency.

By selecting the Evatronics R80515 core in the Keil compiler project settings and by using the compiler

directive “MODC2”, dual data pointers are enabled in certain library routines.

An alternative data pointer is available in the form of the PDATA register (SFR 0xBF, sometimes referred

to as USR2). It defines the high byte of a 16-bit address when reading or writing XDATA with the instruction

MOVX A,@Ri or MOVX @Ri,A.

Internal Data Memory Map and Access

The Internal data memory provides 256 bytes (0x00 to 0xFF) of data memory. The internal data memory

address is always 1 byte wide. Table 8 shows the internal data memory map.

The Special Function Registers (SFR) occupy the upper 128 bytes. The SFR area of internal data memory

is available only by direct addressing. Indirect addressing of this area accesses the upper 128 bytes of

Internal RAM. The lower 128 bytes contain working registers and bit addressable memory. The lower 32

bytes form four banks of eight registers (R0-R7). Two bits on the program memory status word (PSW) select

which bank is in use. The next 16 bytes form a block of bit addressable memory space at addresses

0x00-0x7F. All of the bytes in the lower 128 bytes are accessible through direct or indirect addressing.

Table 8: Internal Data Memory Map

Address Range Direct Addressing Indirect Addressing

0x80

0xFF

Special Function Registers (SFRs)

RAM

0x30

0x7F

Byte addressable area

0x20

0x2F

Bit addressable area

0x00

0x1F

1.4.2 Special Function Registers (SFRs)

A map of the Special Function Registers is shown in Table 9.

Only a few addresses in the SFR memory space are occupied, the others are not implemented. A read

access to unimplemented addresses will return undefined data, while a write access will have no effect.

SFRs specific to the 71M6533/71M6534 are shown in bold print on a gray field. The registers at 0x80,

0x88, 0x90, etc., are bit addressable, all others are byte addressable. See the restrictions for the INTBITS

Table 9: Special Function Register Map

Hex/

Bin

Bit

Addressable

Byte Addressable Bin/

Hex

X000

X001

X010

X011

X100

X101

X110

X111

INTBITS

IFLAGS

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

22 Rev 2

Hex/

Bin

Bit

Addressable

Byte Addressable Bin/

Hex

X000

X001

X010

X011

X100

X101

X110

X111

WDCON

PSW

T2CON

IRCON

IEN1

IP1

S0RELH

S1RELH

PDATA

FLSHCTL

FL_BANK

PGADR

IEN0

IP0

S0RELL

DIR2

DIR0

S0CON

S0BUF

IEN2

S1CON

S1BUF

S1RELL

EEDATA

EECTRL

DIR1

DPS

ERASE

TCON

TMOD

TL0

TL1

TH0

TH1

CKCON

DPL

DPH

DPL1

DPH1

PCON

1.4.3 Generic 80515 Special Function Registers

Table 10 shows the location, description and reset or power-up value of the generic 80515 SFRs. Additional

descriptions of the registers can be found at the page numbers listed in the table.

Table 10: Generic 80515 SFRs - Location and Reset Values

Name Address

(Hex)

Reset value

(Hex)

Description Page

0x80

0xFF

Port 0

0x81

0x07

Stack Pointer

DPL

0x82

0x00

Data Pointer Low 0

DPH

0x83

0x00

Data Pointer High 0

DPL1

0x84

0x00

Data Pointer Low 1

DPH1

0x85

0x00

Data Pointer High 1

PCON

0x87

0x00

UART Speed Control, Idle and Stop mode Control

TCON

0x88

0x00

Timer/Counter Control

TMOD

0x89

0x00

Timer Mode Control

TL0

0x8A

0x00

Timer 0, low byte

TL1

0x8B

0x00

Timer 1, high byte

TH0

0x8C

0x00

Timer 0, low byte

TH1

0x8D

0x00

Timer 1, high byte

CKCON

0x8E

0x01

Clock Control (Stretch=1)

0x90

0xFF

Port 1

DPS

0x92

0x00

Data Pointer select Register

S0CON

0x98

0x00

Serial Port 0, Control Register

S0BUF

0x99

0x00

Serial Port 0, Data Buffer

IEN2

0x9A

0x00

Interrupt Enable Register 2

S1CON

0x9B

0x00

Serial Port 1, Control Register

S1BUF

0x9C

0x00

Serial Port 1, Data Buffer

S1RELL

0x9D

0x00

Serial Port 1, Reload Register, low byte

0xA0

0xFF

Port 2

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 23

Name Address

(Hex)

Reset value

(Hex)

Description Page

IEN0

0xA8

0x00

Interrupt Enable Register 0

IP0

0xA9

0x00

Interrupt Priority Register 0

S0RELL

0xAA

0xD9

Serial Port 0, Reload Register, low byte

0xB0

0xFF

Port 3

IEN1

0xB8

0x00

Interrupt Enable Register 1

IP1

0xB9

0x00

Interrupt Priority Register 1

S0RELH

0xBA

0x03

Serial Port 0, Reload Register, high byte

S1RELH

0xBB

0x03

Serial Port 1, Reload Register, high byte

PDATA

0xBF

0x00

High address byte for MOVX@Ri - also called USR2

IRCON

0xC0

0x00

Interrupt Request Control Register

T2CON

0xC8

0x00

Polarity for INT2 and INT3

PSW

0xD0

0x00

Program Status Word

WDCON

0xD8

0x00

Baud Rate Control Register (only WDCON[7] bit used)

0xE0

0x00

Accumulator

0xF0

0x00

B Register

Accumulator (ACC, A, SFR 0xE0):

ACC is the accumulator register. Most instructions use the accumulator to hold the operand. The

mnemonics for accumulator-specific instructions refer to accumulator as A, not ACC.

B Register (SFR 0xF0):

The B register is used during multiply and divide instructions. It can also be used as a scratch-pad register

to hold temporary data.

Program Status Word (PSW, SFR 0xD0)):

This register contains various flags and control bits for the selection of the register banks (see Table 11).

Table 11: PSW Bit Functions (SFR 0xD0)

PSW Bit

Symbol

Function

Carry flag.

Auxiliary Carry flag for BCD operations.

5 F0

General purpose Flag 0 available for user.

F0 is not to be confused with the F0 flag in the CESTATUS register.

4 RS1

working register bank:

RS1/RS0

Bank selected

Location

Bank 0

0x00 – 0x07

Bank 1

0x08 – 0x0F

Bank 2

0x10 – 0x17

Bank 3

0x18 – 0x1F

3 RS0

Overflow flag.

–

User defined flag.

0 P

Parity flag, affected by hardware to indicate odd or even number of one bits in

the Accumulator, i.e. even parity.

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

24 Rev 2

Stack Pointer (SP, SFR 0x81):

The stack pointer is a 1-byte register initialized to 0x07 after reset. This register is incremented before

PUSH and CALL instructions, causing the stack to begin at location 0x08.

Data Pointer:

The data pointers (DPTR and DPRT1) are 2 bytes wide. The lower part is DPL(SFR 0x82) and DPL1 (SFR

0x84) and the highest is DPH (SFR 0x83) and DPH1 (SFR 0x85). The data pointers can be loaded as two

registers (e.g. MOV DPL,#data8). They are generally used to access external code or data space (e.g.

MOVC A,@A+DPTR or MOVX A,@DPTR respectively).

Program Counter:

The program counter (PC) is 2 bytes wide and initialized to 0x0000 after reset. The PC is incremented

when fetching operation code or when operating on data from program memory.

Port Registers:

The I/O ports are controlled by Special Function Registers P0, P1 and P2, as shown in Table 12. The contents

of the SFR can be observed on corresponding pins on the chip. Writing a 1 to any of the ports causes the

corresponding pin to be at high level (V3P3). Writing a 0 causes the corresponding pin to be held at a low

level (GND). The data direction registers DIR0, DIR1, and DIR2 define individual pins as input or output

pins (see Section 1.5.7 Digital I/O for details).

Table 12: Port Registers

Address

R/W Description

0x80

R/W

DIR0

0xA2

R/W

Data direction register for port 0. Setting a bit to 1 means that the

corresponding pin is an output.

0x90

R/W

DIR1

0x91

R/W

Data direction register for port 1.

0xA0

R/W

DIR2

0xA1

R/W

Data direction register for port 2.

All DIO ports on the chip are bi-directional. Each of them consists of a Latch (SFR P0 to P2), an output

driver and an input buffer, therefore the MPU can output or read data through any of these ports. Even if

a DIO pin is configured as an output, the state of the pin can still be read by the MPU, for example when

counting pulses issued via DIO pins that are under CE control.

The technique of reading the status of or generating interrupts based on DIO pins configured as

outputs can be used to implement pulse counting.

Clock Stretching (CKCON[2:0], SFR 0x8E)

The CKCON[2:0] field defines the stretch memory cycles that are used for MOVX instructions when

accessing external peripherals. The practical value of this field for the 71M6533/71M6534 is to guarantee

access to XRAM between CE, MPU, and SPI. The default setting of CKCON[2:0] (001) should not be

changed.

Table 13 shows how the signals of the External Memory Interface change when stretch values are set

from 0 to 7. The widths of the signals are counted in MPU clock cycles. The post-reset state of the

CKCON[2:0] register (001), which is shown in bold in the table, performs the MOVX instructions with a

stretch value equal to 1.

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 25

Table 13: Stretch Memory Cycle Width

CKCON[2:0] Stretch

Value

Read Signal Width

Write Signal Width

memaddr

memrd

memaddr

memwr

000

001

010

011

100

101

110

111

1.4.4 71M6533/71M6534-Specific Special Function Registers

Table 14 shows the location and description of the 71M6533/71M6534-specific SFRs.

Table 14: 71M6533/71M6534 Specific SFRs

(Alternate Name)

SFR

Address

Bit Field

Name

R/W Description

EEDATA

0x9E

R/W

I2C EEPROM interface data register.

EECTRL 0x9F

R/W

I2C EEPROM interface control register.

See Section 1.5.10 EEPROM Interface for a

description of the command and status bits

available for

EECTRL

ERASE

(FLSH_ERASE) 0x94

This register is used to initiate either the Flash

Mass Erase cycle or the Flash Page Erase cycle.

See the Flash Memory section for details.

FL_BANK[2:0]

0xB6[2:0]

R/W

Flash Bank Selection.

PGADDR

(FLSH_PGADR) 0xB7

R/W

Flash Page Erase Address register. Contains

the flash memory page address (page 0

through page 127) that will be erased

during the

Page Erase cycle (default = 0x00). Must be re-

written for each new Page Erase cycle.

FLSHCRL

0xB2[0] FLSH_PWE R/W

Program Write Enable:

MOVX commands refer to XRAM Space,

normal operation (default).

1: MOVX @DPTR,A moves A to Program

Space (Flash) @ DPTR.

0xB2[1] FLSH_MEEN W

Mass Erase Enable:

0: Mass Erase disabled (default).

1: Mass Erase enabled.

Must be re-written for each new Mass Erase cycle.

0xB2[4] WRPROT_CE*

Protects flash from address CE_LCTN *1024 to

the end of memory from flash page erase.

0xB2[5] WRPROT_BT*

Protects flash from address 0 to address

BOOT_SIZE*1024 from flash page erase.

0xB2[6]

SECURE

R/W

Enables security provisions that prevent external

reading of flash memory and CE program RAM.

This bit is reset on chip reset and may only be set.

Attempts to write zero are ignored.

0xB2[7]

PREBOOT

Indicates that the preboot sequence is active.

* The WRPROT_CE and WRPROT_BT bits can only be cleared when the SECURE bit

is not set. When SECURE = 1, WRPROT_CE and WRPROT_BT can only be set to 1.

A hardware reset is required to clear these bits if SECURE = 1.

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

26 Rev 2

(Alternate Name)

SFR

Address

Bit Field

Name

R/W Description

IFLAGS

0xE8[0] IE_XFER R/W

This flag monitors the XFER_BUSY interrupt. It

is set by hardware and must be cleared by the

interrupt handler.

0xE8[1] IE_RTC R/W

This flag monitors the RTC_1SEC interrupt. It

set by hardware and must be cleared by the

interrupt handler.

0xE8[2] FW_COL1 R/W

This flag indicates that a flash write was in

progress while the CE was busy.

0xE8[3] FW_COL0 R/W

This flag indicates that a flash write was

attempted when the CE was attempting to

begin a code pass.

0xE8[4] IE_PB R/W

This flag indicates that the wake-up pushbutton

was pressed.

0xE8[5] IE_WAKE R/W

This flag indicates that the MPU was awakened

by the autowake timer.

0xE8[6] PLL_RISE R/W

PLL_RISE Interrupt Flag:

Write 0 to clear the PLL_RISE interrupt flag.

0xE8[7] PLL_FALL R/W

PLL_FALL Interrupt Flag:

Write 0 to clear the PLL_FALL interrupt flag.

INTBITS

(INT0 … INT6)

0xF8[6:0]

INT6 … INT0 R

Interrupt inputs. The MPU may read these bits

to see the status of external interrupts INT0 up

to INT6. These bits do not have any memory

and are primarily intended for debug use.

0xF8[7]

WD_RST

The WDT is reset when a 1 is written to this bit.

Only byte operations on the entire INTBITS register should be used when

writing. The byte must have all bits set except the bits that are to be

cleared.

1.4.5 Instruction Set

All instructions of the generic 8051 microcontroller are supported. A complete list of the instruction set

and of the associated op-codes is contained in the 71M653X Software User’s Guide (SUG).

1.4.6 UARTs

The 71M6533 and 71M6534 include a UART (UART0) that can be programmed to communicate with a

variety of AMR modules and other external devices. A second UART (UART1) is connected to the optical

port, as described in the 1.5.6 Optical Interface section.

The UARTs are dedicated 2-wire serial interfaces, which can communicate with an external host processor

at up to 38,400 bits/s (with MPU clock = 1.2288 MHz). The operation of the RX and TX UART0 pins is as

follows:

• UART0 RX: Serial input data are applied at this pin. Conforming to RS-232 standard, the bytes are

input LSB first.

• UART0 TX: This pin is used to output the serial data. The bytes are output LSB first.

The 71M6533 and 71M6534 have several UART-related registers for the control and buffering of serial

data.

A single SFR register serves as both the transmit buffer and receive buffer (S0BUF, SFR 0x99 for UART0

and S1BUF, SFR 0x9C for UART1). When written by the MPU, SxBUF acts as the transmit buffer, and

when read by the MPU, it acts as the receive buffer. Writing data to the transmit buffer starts the transmission

by the associated UART. Received data are available by reading from the receive buffer. Both UARTs

can simultaneously transmit and receive data.

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 27

WDCON[7] selects whether timer 1 or the internal baud rate generator is used. All UART transfers are

programmable for parity enable, parity, 2 stop bits/1 stop bit and XON/XOFF options for variable

communication baud rates from 300 to 38400 bps. Table 15 shows how the baud rates are calculated.

Table 16 shows the selectable UART operation modes.

Table 15: Baud Rate Generation

Using Timer 1

(WDCON[7] = 0)

Using Internal Baud Rate Generator

(WDCON[7] = 1)

UART0

2smod * fCKMPU/ (384 * (256-TH1))

2smod * fCKMPU/(64 * (210-S0REL))

UART1

N/A

fCKMPU/(32 * (210-S1REL))

S0REL and S1REL are 10-bit values derived by combining bits from the respective timer reload registers

(S0RELL, S0RELH, S1RELL, S1RELH). SMOD is the SMOD bit in the SFR PCON register. TH1 is the high

byte of timer 1.

Table 16: UART Modes

UART 0

UART 1

Mode 0 N/A

Start bit, 8 data bits, parity, stop bit, variable

baud rate (internal baud rate generator)

Mode 1

Start bit, 8 data bits, stop bit, variable

baud rate (internal baud rate generator

or timer 1)

Start bit, 8 data bits, stop bit, variable baud

rate (internal baud rate generator)

Mode 2

Start bit, 8 data bits, parity, stop bit,

fixed baud rate 1/32 or 1/64 of fCKMPU

N/A

Mode 3

Start bit, 8 data bits, parity, stop bit,

variable baud rate (internal baud rate

generator or timer 1)

N/A

Parity of serial data is available through the P flag of the accumulator. 7-bit serial modes with

parity, such as those used by the FLAG protocol, can be simulated by setting and reading bit 7 of

8-bit output data. 7-bit serial modes without parity can be simulated by setting bit 7 to a constant

1. 8-bit serial modes with parity can be simulated by setting and reading the 9th bit, using the

control bits TB80 (S0CON[3]) and TB81 (S1CON[3]) in the S0CON (SFR 0x98) and S1CON (SFR 0x9B)

SFRs for transmit and RB81 (S1CON[2]) for receive operations.

The feature of receiving 9 bits (Mode 3 for UART0, Mode A for UART1) can be used as handshake signals

for inter-processor communication in multi-processor systems. In this case, the slave processors have bit

SM20 (S0CON[5]) for UART0, or SM21 (S1CON[5] for UART1, set to 1. When the master processor outputs

the slave’s address, it sets the 9th bit to 1, causing a serial port receive interrupt in all the slaves. The

slave processors compare the received byte with their address. If there is a match, the addressed slave

will clear SM20 or SM21 and receive the rest of the message. The rest of the slave’s will ignore the message.

After addressing the slave, the host outputs the rest of the message with the 9th bit set to 0, so no additional

serial port receive interrupts will be generated.

UART Control Registers:

The functions of UART0 and UART1 depend on the setting of the Serial Port Control Registers S0CON

and S1CON shown in Table 17 and Table 18, respectively, and the PCON register shown in Table 19.

Since the TI0, RI0, TI1 and RI1 bits are in an SFR bit addressable byte, common practice

would be to clear them with a bit operation, but this must be avoided. The hardware implements

bit operations as a byte wide read-modify-write hardware macro. If an interrupt occurs after

the read, but before the write, its flag will be cleared unintentionally.

The proper way to clear these flag bits is to write a byte mask consisting of all ones except for

a zero in the location of the bit to be cleared. The flag bits are configured in hardware to ignore

ones written to them.

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

28 Rev 2

Table 17: The S0CON (UART0) Register (SFR 0x98)

Bit

Symbol

Function

S0CON[7] SM0

The SM0 and SM1 bits set the UART0 mode:

Mode

Description

SM0

SM1

N/A

8-bit UART

9-bit UART

S0CON[6] SM1

S0CON[5]

SM20

Enables the inter-processor communication feature.

S0CON[4]

REN0

If set, enables serial reception. Cleared by software to disable reception.

S0CON[3] TB80

The 9th transmitted data bit in Modes 2 and 3. Set or cleared by the MPU,

depending on the function it performs (parity check, multiprocessor

communication etc.)

S0CON[2] RB80

In Modes 2 and 3 it is the 9th data bit received. In Mode 1, SM20 is 0, RB80

is the stop bit. In mode 0, this bit is not used. Must be cleared by software.

S0CON[1] TI0

Transmit interrupt flag; set by hardware after completion of a serial transfer.

Must be cleared by software.

S0CON[0] RI0

Receive interrupt flag; set by hardware after completion of a serial reception.

Must be cleared by software.

Table 18: The S1CON (UART1) Register (SFR 0x9B)

Bit Symbol Function

S1CON[7] SM

Sets the baud rate and mode for UART1.

Mode

Description

Baud Rate

9-bit UART

variable

8-bit UART

variable

S1CON[5]

SM21

Enables the inter-processor communication feature.

S1CON[4]

REN1

If set, enables serial reception. Cleared by software to disable reception.

S1CON[3] TB81

The 9

transmitted data bit in Mode A. Set or cleared by the MPU, depending

on the function it performs (parity check, multiprocessor communication

etc.)

S1CON[2] RB81

In Modes A and B, it is the 9th data bit received. In Mode B, if SM21 is 0,

RB81

is the stop bit. Must be cleared by software

S1CON[1] TI1 Transmit interrupt flag, set by hardware after completion of a serial transfer

Must be cleared by software.

S1CON[0] RI1

Receive interrupt flag, set by hardware after completion of a serial reception.

Must be cleared by software.

Table 19: PCON Register Bit Description (SFR 0x87)

Bit Symbol Function

PCON[7]

SMOD

The SMOD bit doubles the baud rate when set

PCON[6:2]

–

Not used.

PCON[1]

STOP

Stops MPU flash access and MPU peripherals including timers and UARTs

when set until an external interrupt is received.

PCON[0]

IDLE

Stops MPU flash access when set until an internal interrupt is received.

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 29

1.4.7 Timers and Counters

The 80515 has two 16-bit timer/counter registers: Timer 0 and Timer 1. These registers can be configured

for counter or timer operations.

In timer mode, the register is incremented every 12 MPU clock cycles. In counter mode, the register is

incremented when the falling edge is observed at the corresponding input signal T0 or T1 (T0 and T1 are

the timer gating inputs derived from certain DIO pins, see Section 1.5.7 Digital I/O). Since it takes 2 machine

cycles to recognize a 1-to-0 event, the maximum input count rate is 1/2 of the clock frequency (CKMPU).

There are no restrictions on the duty cycle, however to ensure proper recognition of the 0 or 1 state, an

input should be stable for at least 1 machine cycle.

Four operating modes can be selected for Timer 0 and Timer 1, as shown in Table 20 and Table 21. The

TMOD Register, shown in Table 22, is used to select the appropriate mode. The timer/counter operation

is controlled by the TCON Register, which is shown in

Table 23. Bits TR1 (TCON[6]) and TR0 (TCON[4]) in the TCON register start their associated timers when

set.

Table 20: Timers/Counters Mode Description

Mode

Function

0 0 Mode 0

13-bit Counter/Timer mode with 5 lower bits in the TL0 or TL1 register

and the remaining 8 bits in the TH0 or TH1 register (for Timer 0 and

Timer 1, respectively). The 3 high order bits of TL0 and TL1 are held

at zero.

Mode 1

16-bit Counter/Timer mode.

1 0 Mode 2

8-bit auto-reload Counter/Timer. The reload value is kept in TH0 or

TH1, while TL0 or TL1 is incremented every machine cycle. When

TL(x) overflows, a value from TH(x) is copied to TL(x) (where x is 0

for counter/timer 0 or 1 for counter/timer 1.

1 1 Mode 3

If Timer 1 M1 and M0 bits are set to 1, Timer 1 stops.

If Timer 0 M1 and M0 bits are set to 1, Timer 0 acts as two independent

8-bit Timer/Counters.

In Mode 3, TL0 is affected by TR0 and gate control bits, and sets the TF0 flag on overflow, while

TH0 is affected by the TR1 bit, and the TF1 flag is set on overflow.

Table 21 specifies the combinations of operation modes allowed for Timer 0 and Timer 1.

Table 21: Allowed Timer/Counter Mode Combinations

Timer 1

Mode 0

Mode 1

Mode 2

Timer 0 - mode 0

Yes

Timer 0 - mode 1

Yes

Timer 0 - mode 2

Not allowed

Yes

Table 22: TMOD Register Bit Description (SFR 0x89)

Bit

Symbol

Function

Timer/Counter 1:

TMOD[7] Gate

If TMOD[7] is set, external input signal control is enabled for Counter 0.

external gate control. The TR1 bit in the TCON register (SFR 0x88) must

also be set in order for Counter 1 to increment.

With these settings Counter 1 is incremented on every falling edge of the

logic signal applied to one or more of the interrupt sources controlled by

the DI_RBP, DIO_R1, … DIO_RXX registers.

TMOD[6] C/T

Selects timer or counter operation. When set to 1, a counter operation is

performed. When cleared to 0, the corresponding register will function as a

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

30 Rev 2

timer.

TMOD[5:4]

M1:M0

Selects the mode for Timer/Counter 1 as shown in Table 20.

Timer/Counter 0

TMOD[3] Gate

If TMOD[3] is set, external input signal control is enabled for Counter 0.

external gate control. The TR0 bit in the TCON register (SFR 0x88) must

also be set in order for Counter 0 to increment.

With these settings Counter 0 is incremented on every falling edge of the

logic signal applied to one or more of the interrupt sources controlled by

the DI_RBP, DIO_R1, … DIO_RXX registers.

TMOD[2] C/T

Selects timer or counter operation. When set to 1, a counter operation is

performed. When cleared to 0, the corresponding register will function as

a timer.

TMOD[1:0]

M1:M0

Selects the mode for Timer/Counter 0, as shown in Table 20.

Table 23: The TCON Register Bit Functions (SFR 0x88)

Bit Symbol Function

TCON[7] TF1

The Timer 1 overflow flag is set by hardware when Timer 1 overflows.

This flag can be cleared by software and is automatically cleared when

an interrupt is processed.

TCON[6]

TR1

Timer 1 run control bit. If cleared, Timer 1 stops.

TCON[5] TF0

Timer 0 overflow flag set by hardware when Timer 0 overflows. This

flag can be cleared by software and is automatically cleared when an

interrupt is processed.

TCON[4]

TR0

Timer 0 Run control bit. If cleared, Timer 0 stops.

TCON[3] IE1 Interrupt 1 edge flag is set by hardware when the falling edge on external

pin int1 is observed. Cleared when an interrupt is processed.

TCON[2] IT1 Interrupt 1 type control bit set by the MPU. Selects either the falling

edge or low level on input pin to cause an external interrupt.

TCON[1] IE0

Interrupt 0 edge flag is set by hardware when the falling edge on external

pin int0 is observed. Cleared when an interrupt is processed.

TCON[0] IT0

Interrupt 0 type control bit. Selects either the falling edge or low level

on input pin to cause interrupt.

1.4.8 WD Timer (Software Watchdog Timer)

There is no internal software watchdog timer. Use the standard watchdog timer instead (see Section

1.5.12 Hardware Watchdog Timer).

1.4.9 Interrupts

The 80515 MPU provides 11 interrupt sources with four priority levels. Each source has its own request

flag(s) located in a special function register (TCON, IRCON, and SCON). Each interrupt requested by the

corresponding flag can be individually enabled or disabled by the enable bits in SFRs IEN0 (SFR 0xA8),

IEN1 (SFR 0xB8), and IEN2 (SFR 0x9A). shows the device interrupt structure.

Referring to Figure 7, interrupt sources can originate from within the 80515 MPU core (referred to as

Internal Sources) or can originate from other parts of the 71M653x SoC (referred to as External Sources).

There are seven external interrupt sources, as seen in the leftmost part of Figure 7, and in Table 24 and

Table 25 (i.e. EX0-EX6)

Interrupt Overview

When an interrupt occurs, the MPU will vector to the predetermined address as shown in Table 36. Once

the interrupt service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 31

is terminated by a return from instruction, RETI. When an RETI is performed, the processor will return to

the instruction that would have been next when the interrupt occurred.

When the interrupt condition occurs, the processor will also indicate this by setting a flag bit. This bit is

set regardless of whether the interrupt is enabled or disabled. Each interrupt flag is sampled once per

machine cycle, then samples are polled by the hardware. If the sample indicates a pending interrupt

when the interrupt is enabled, then the interrupt request flag is set. On the next instruction cycle, the interrupt

will be acknowledged by hardware forcing an LCALL to the appropriate vector address, if the following

conditions are met:

• No interrupt of equal or higher priority is already in progress.

• An instruction is currently being executed and is not completed.

• The instruction in progress is not RETI or any write access to the registers IEN0, IEN1, IEN2, IP0 or IP1.

Special Function Registers for Interrupts

The following SFR registers control the interrupt functions:

• The interrupt enable registers: IEN0, IEN1 and IEN2 (see Table 24, Table 25 and Table 26).

• The Timer/Counter control registers, TCON and T2CON (see Table 27 and Table 28).

• The interrupt request register, IRCON (see Table 29).

• The interrupt priority registers: IP0 and IP1 (see Table 34).

Table 24: The IEN0 Bit Functions (SFR 0xA8)

Bit Symbol Function

IEN0[7]

EAL

EAL = 0 disables all interrupts.

IEN0[6]

WDT

Not used for interrupt control.

IEN0[5]

– Not Used.

IEN0[4]

ES0

ES0 = 0 disables serial channel 0 interrupt.

IEN0[3]

ET1

ET1 = 0 disables timer 1 overflow interrupt.

IEN0[2]

EX1

EX1 = 0 disables external interrupt 1.

IEN0[1]

ET0

ET0 = 0 disables timer 0 overflow interrupt.

IEN0[0]

EX0

EX0 = 0 disables external interrupt 0.

Table 25: The IEN1 Bit Functions (SFR 0xB8)

Bit

Symbol

Function

IEN1[7]

–

Not used.

IEN1[6]

–

Not used.

IEN1[5]

EX6

EX6 = 0 disables external interrupt 6: XFER_BUSY, RTC_1SEC, WD_NROVF

IEN1[4]

EX5

EX5 = 0 disables external interrupt 5: EEPROM_BUSY

IEN1[3]

EX4

EX4 = 0 disables external interrupt 4: PLL_OK (rise), PLL_OK (fall)

IEN1[2]

EX3

EX3 = 0 disables external interrupt 3: CE_BUSY

IEN1[1]

EX2

EX2 = 0 disables external interrupt 2: FWCOL0, FWCOL1, SPI

IEN1[0]

– Not Used.

Table 26: The IEN2 Bit Functions (SFR 0x9A)

Bit

Symbol

Function

IEN2[0]

ES1

ES1 = 0 disables the serial channel 1 interrupt.

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

32 Rev 2

Table 27: TCON Bit Functions (SFR 0x88)

Bit

Symbol

Function

TCON[7]

TF1

Timer 1 overflow flag.

TCON[6]

TR1

Not used for interrupt control.

TCON[5]

TF0

Timer 0 overflow flag.

TCON[4]

TR0

Not used for interrupt control.

TCON[3]

IE1

External interrupt 1 flag.

TCON[2] IT1

External interrupt 1 type control bit:

0 = interrupt on low level.

1 = interrupt on falling edge.

TCON[1]

IE0

External interrupt 0 flag

TCON[0] IT0

External interrupt 0 type control bit:

0 = interrupt on low level.

1 = interrupt on falling edge.

Table 28: The T2CON Bit Functions (SFR 0xC8)

Bit Symbol Function

T2CON[7]

–

Not used.

T2CON[6] I3FR

Polarity control for external interrupt 3: CE_BUSY

0 = falling edge.

1 = rising edge.

T2CON[5] I2FR

Polarity control for external interrupt 2: FWCOL0, FWCOL1, SPI

0 = falling edge.

1 = rising edge.

T2CON[4:0]

–

Not used.

Table 29: The IRCON Bit Functions (SFR 0xC0)

Bit

Symbol

Function

IRCON[7]

–

Not used

IRCON[6]

–

Not used

IRCON[5]

IEX6

1 = External interrupt 6 occurred and has not been cleared.

IRCON[4]

IEX5

1 = External interrupt 5 occurred and has not been cleared.

IRCON[3]

IEX4

1 = External interrupt 4 occurred and has not been cleared.

IRCON[2]

IEX3

1 = External interrupt 3 occurred and has not been cleared.

IRCON[1]

IEX2

1 = External interrupt 2 occurred and has not been cleared.

IRCON[0]

–

Not used.

TF0 and TF1 (Timer 0 and Timer 1 overflow flags) will be automatically cleared by hardware when

the service routine is called (Signals T0ACK and T1ACK – port ISR – active high when the service

routine is called).

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 33

External MPU Interrupts

The seven external interrupts are the interrupts external to the 80515 core, i.e. signals that originate in

other parts of the 71M6533/71M6534, for example the CE, DIO, RTC, EEPROM interface.

The external interrupts are connected as shown in Table 30. The polarity of interrupts 2 and 3 is

programmable in the MPU via the I3FR and I2FR bits in T2CON. Interrupts 2 and 3 should be programmed

for falling sensitivity (I3FR = I2FR = 0). The generic 8051 MPU literature states that interrupts 4 through 6

are defined as rising-edge sensitive. Thus, the hardware signals attached to interrupts 5 and 6 are inverted

to achieve the edge polarity shown in Table 30.

Table 30: External MPU Interrupts

External

Interrupt

Connection Polarity Flag Reset

Digital I/O High Priority

see Section 1.5.7

automatic

Digital I/O Low Priority

see Section 1.5.7

automatic

FWCOL0, FWCOL1, SPI

falling

automatic

CE_BUSY

falling

automatic

PLL_OK (rising), PLL_OK (falling)

rising

automatic

EEPROM busy

falling

automatic

XFER_BUSY, RTC_1SEC or WD_NROVF

falling

manual

External interrupt 0 and 1 can be mapped to pins on the device using DIO resource maps. See Section

1.5.7 Digital I/O for more information.

FWCOLx interrupts occur when the CE collides with a flash write attempt. See the flash write description

in the Flash Memory section for more detail.

SFR enable bits must be set to permit any of these interrupts to occur. Likewise, each interrupt has its own

flag bit, which is set by the interrupt hardware, and reset by the MPU interrupt handler. XFER_BUSY,

RTC_1SEC, WD_NROVF, FWCOL0, FWCOL1, SPI, PLLRISE and PLLFALL have their own enable and

flag bits in addition to the interrupt 6, 4 and enable and flag bits (see Table 31).

IE0 through IEX6 are cleared automatically when the hardware vectors to the interrupt handler. The other

flags, IE_XFER through IE_PB, are cleared by writing a zero to them.

Since these bits are in an SFR bit addressable byte, common practice would be to clear them

with a bit operation, but this must be avoided. The hardware implements bit operations as a

byte wide read-modify-write hardware macro. If an interrupt occurs after the read, but before

the write, its flag will be cleared unintentionally.

The proper way to clear the flag bits is to write a byte mask consisting of all ones except for a

zero in the location of the bit to be cleared. The flag bits are configured in hardware to ignore

ones written to them.

Table 31: Interrupt Enable and Flag Bits

Interrupt Enable Interrupt Flag Interrupt Description

Name

Location

Name

Location

EX0

SFR A8[0]

IE0

SFR 88[1]

External interrupt 0

EX1

SFR A8[2]

IE1

SFR 88[3]

External interrupt 1

EX2

SFR B8[1]

IEX2

SFR C0[1]

External interrupt 2

EX3

SFR B8[2]

IEX3

SFR C0[2]

External interrupt 3

EX4

SFR B8[3]

IEX4

SFR C0[3]

External interrupt 4

EX5

SFR B8[4]

IEX5

SFR C0[4]

External interrupt 5

EX6

SFR B8[5]

IEX6

SFR C0[5]

External interrupt 6

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

34 Rev 2

Interrupt Enable

Interrupt Flag

Interrupt Description

Name

Location

Name

Location

EX_XFER

2002[0]

IE_XFER

SFR E8[0]

XFER_BUSY interrupt (INT 6)

EX_RTC

2002[1]

IE_RTC

SFR E8[1]

RTC_1SEC interrupt (INT 6)

IEN_WD_NROVF

20B0[0]

WD_NROVF_FLAG

20B1[0]

WDT near overflow (INT 6)

IEN_SPI

20B0[4]

SPI_FLAG

20B1[4]

SPI Interface (INT2)

EX_FWCOL 2007[4]

IE_FWCOL0

SFR E8[3]

FWCOL0 interrupt (INT 2)

IE_FWCOL1

SFR E8[2]

FWCOL1 interrupt (INT 2)

EX_PLL 2007[5]

IE_PLLRISE

SFRE8[6]

PLL_OK rise interrupt (INT 4)

IE_PLLFALL

SFRE8[7]

PLL_OK fall interrupt (INT 4)

IE_WAKE

SFRE8[5]

AUTOWAKE flag†

IE_PB

SFRE8[4]

PB flag†

†The AUTOWAKE and PB flag bits are shown in Table 31 because they behave similarly to interrupt flags,

even though they are not actually related to an interrupt. These bits are set by hardware when the MPU

wakes from a push button or wake timeout. The bits are reset by writing a zero. Note that the PB flag is

set whenever the PB is pushed, even if the part is already awake.

WD_NROVF_FLAG is set approximately 1 ms before a WDT reset occurs. The flag can be cleared by

writing a zero to it and is automatically cleared by the falling edge of WAKE.

Interrupt Priority Level Structure

All interrupt sources are combined in groups, as shown in Table 32:

Table 32: Interrupt Priority Level Groups

Group Members

External interrupt 0, Serial

channel 1 interrupt

Timer 0 interrupt, External

interrupt 2

External interrupt 1, External

interrupt 3

Timer 1 interrupt, External

interrupt 4

Serial channel 0 interrupt,

External interrupt 5

External interrupt 6

Each group of interrupt sources can be programmed individually to one of four priority levels (as shown in

Table 33) by setting or clearing one bit in the SFR interrupt priority register IP0 and one in IP1 (Table 34).

If requests of the same priority level are received simultaneously, an internal polling sequence as shown

in Table 35 determines which request is serviced first.

Changing interrupt priorities while interrupts are enabled can easily cause software defects. It is best

to set the interrupt priority registers only once during initialization before interrupts are enabled.

Table 33: Interrupt Priority Levels

IP1[x]

IP0[x]

Priority Level

Level 0 (lowest)

Level 1

Level 2

Level 3 (highest)

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 35

Table 34: Interrupt Priority Registers (IP0 and IP1)

(MSB)

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

(LSB)

IP0

SFR 0xA9

–

IP0[5]

IP0[4]

IP0[3]

IP0[2]

IP0[1]

IP0[0]

IP1

SFR 0xB9

–

IP1[5]

IP1[4]

IP1[3]

IP1[2]

IP1[1]

IP1[0]

Table 35: Interrupt Polling Sequence

External interrupt 0

Polling sequence

Serial channel 1 interrupt

Timer 0 interrupt

External interrupt 2

External interrupt 1

External interrupt 3

Timer 1 interrupt

External interrupt 4

Serial channel 0 interrupt

External interrupt 5

External interrupt 6

Interrupt Sources and Vectors

Table 36 shows the interrupts with their associated flags and vector addresses.

Table 36: Interrupt Vectors

Interrupt

Request Flag Description Interrupt Vector

Address

IE0

External interrupt 0

0x0003

TF0

Timer 0 interrupt

0x000B

IE1

External interrupt 1

0x0013

TF1

Timer 1 interrupt

0x001B

RI0/TI0

Serial channel 0 interrupt

0x0023

RI1/TI1

Serial channel 1 interrupt

0x0083

IEX2

External interrupt 2

0x004B

IEX3

External interrupt 3

0x0053

IEX4

External interrupt 4

0x005B

IEX5

External interrupt 5

0x0063

IEX6

External interrupt 6

0x006B

71M6533/H and 71M6534/H Data Sheet FDS_6533_6534_004

36 Rev 2

Figure 7: Interrupt Structure

TCON.1 (IE0 )

Individual

Enable Bits

S1CON.0 (RI1 )

S1CON.1 (TI1 )

Individual Flags

Internal

Source

>=1

TCON.5 (TF0 )

TCON.3 (IE1 )

TCON.7 (TF1 )

S0CON.0 (RI0 )

S0CON.0 (TI0 )

>=1

IRCON.1

(IEX2)

I2FR

IRCON.2

(IEX3)

I3FR

IRCON.3

(IEX4)

IRCON.4

(IEX5)

IRCON.5

(IEX6)

IEN0.7

(EAL)

IP1.0/

IP0.0

IP1.1/

IP0.1

IP1.2/

IP0.2

IP1.3/

IP0.3

IP1.4/

IP0.4

IP1.5/

IP0.5

Interrupt

Flags

Priority

Assignment

Interrupt

Vector

Polling Sequence

Interrupt Enable

Logic and Polarity

Selection

DIO

Timer 0

Timer 1

CE_BUSY

UART0

EEPROM

XFER_BUSY

RTC_1S EX_RTC

PLL OK

External

Source

DIO_Rn

I2C

>=1

Flash

Write

Collision

>=1

IEN2.0

(ES1)

IEN0.1

(ET0)

IEN0.0

(EX0)

IEN1.1

(EX2)

IEN0.2

(EX1)

IEN1.2

(EX3)

IEN0.3

(ET1)

IEN1.3

(EX4)

IEN0.4

(ES0)

IEN1.4

(EX5)

IEN1.5

(EX6)

IE_XFER

IE_RTC

EX_XFER

>=1

EX_EEX

EX_SPI

IE_EEX

IE_SPI

IT0

IE_FWCOL1

SPI_FLAG

UART1

(optical)

No.

Flag=1 means

that an inter-

rupt has oc-

curred and

has not been

cleared

EX0 – EX6 are cleared

automatically when the

hardware vectors to the

interrupt handler

byte received

byte transmitted

overflow occurred

byte received

byte transmitted

accumulation

cycle completed

PLL status

changed

CE completed code run and

has new status information

DIO status

changed

DIO status

changed

every second

BUSY fell

command

received

SPI I/F

Write attempt, CE

busy

2/2/2009

IE_FWCOL0

DIO

NR_OVF

EX_FWCOL

EX_PLL

IE_PLLRISE

IE_PLLFALL

IEN_SPI

IEN_NR_

WDOVF WD_NROVF_FLAG

CE code start,

flash write busy

WDT near

overflow

>=1

MPU-external

sources

MPU-internal

sources

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 37

1.5 On-Chip Resources

1.5.1 Oscillator

The 71M6533/71M6534 oscillator drives a standard 32.768 kHz watch crystal. These crystals are accurate

and do not require a high-current oscillator circuit. The oscillator has been designed specifically to handle

these crystals and is compatible with their high impedance and limited power handling capability. The

oscillator power dissipation is very low to maximize the lifetime of any battery attached to VBAT.

Oscillator calibration can improve the accuracy of both the RTC and metering. Refer to Section 1.5.3

Real-Time Clock (RTC) for more information.

The oscillator is powered directly and only from VBAT, which therefore must be connected to a DC voltage

source. The oscillator requires approximately 100 nA, which is negligible compared to the internal leakage

of a battery.

The oscillator may appear to work when VBAT is not connected, but this mode of operation is not

recommended.

If VBAT is connected to a drained battery or disconnected, a battery test that sets BME may drain

VBAT’s supply and cause the oscillator to stop. A stopped oscillator may force the device to reset.

Therefore, an unexpected reset during a battery test should be interpreted as a battery failure.

1.5.2 PLL and Internal Clocks

Timing for the device is derived from the 32.768 kHz crystal oscillator output. On-chip timing functions

include:

• The MPU clock (CKMPU)

• The emulator clock (2 x CKMPU)

• The clock for the CE (CKCE)

• The clock driving the delta-sigma ADC along with the FIR (CKADC, CKFIR)

• A real time clock (RTC).

The two general-purpose counter/timers contained in the MPU are controlled by CKMPU (see Timers and

Counters). Table 37 provides a summary of the clock functions provided.

Table 37: Clock System Summary

Clock Derived

From

MCK Divider / [M40MHZ, M26MHZ] Brownout Mode

÷ 2 / [1,0]

÷ 3 / [0,1]

÷ 4** / [0,0]

32 kHz

CKPLL

Crystal

78.6432 MHz

Off

MCK

CKPLL

39.3216 MHz

26.2144 MHz

19.6608 MHz

112 kHz

CKCE MCK

4.9152

MHz

†

9.8304

MHz

†

6.5536 MHz 4.9152 MHz Off

CKADC / CKFIR

MCK

4.9152 MHz

6.5536 MHz

4.9152 MHz

28 kHz

CKMPU maximum

MCK

9.8304 MHz***

6.5536 MHz ***

4.9152 MHz ***

28 kHz

CK32

MCK

32.768 kHz

Default state at power-up

*** This is the maximum CKMPU frequency. CKMPU can be reduced from this rate using MPU_DIV[2:0].

†

CKCE = 9.8304 MHz when CE10MHZ is set, 4.9152 MHz otherwise.

The master clock, MCK, is generated by an on-chip PLL that multiplies the crystal oscillator output frequency

(CK32) by 2400 to provide 80 MHz (78.6432 MHz). A divider controlled by the I/O RAM registers

M40MHZ and M26MHZ permits scaling of MCK by ½, ⅓, and ¼. All other clocks are derived from this

scaled MCK output (making them multiples of 32768 Hz), and the clock skew is matched so that the rising

edges of CKADC, CKCE, CK32, and CKMPU are aligned.

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

38 Rev 2

The PLL has a 2x emulator clock which is controlled by the ECK_DIS bit. Since clock noise from this feature

may disturb the ADC, it is recommended that this option be avoided when possible.

The MPU clock frequency CKMPU is determined by another divider controlled by the I/O RAM field

MPU_DIV[2:0] and can be set to MCK/2(MPU_DIV+2) Hz where MPU_DIV[2:0] varies from 0 to 6. The circuit

also generates the 2 x CKMPU clock for use by the emulator. The emulator clock is not generated when

ECK_DIS is asserted.

During a power-on reset, [M40MHZ, M26MHZ] defaults to [0,0], and the MCK divider is set to divide by 4.

When [M40MHZ, M26MHZ] = [1,0], the CE clock frequency may be set to ~5 MHz (4.9152 MHz) or ~10

MHz (9.8304 MHz), using the I/O RAM register CE10MHZ. In this mode, the ADC and FIR clock frequencies

remain at ~5 MHz. When [M40MHZ, M26MHZ] = [0,1], the CE, ADC, FIR, and MPU clock frequencies are

shifted to ~6.6 MHz (6.5536 MHz). This increases the ADC sample rate by 33%.

CE codes are tailored to particular clock frequencies. Changing the clock frequency for a

particular CE code may render it unusable.

In SLEEP mode, the M40MHZ and M26MHZ inputs to the clock generator are forced low. In BROWNOUT

mode, the clocks are derived from the crystal oscillator, and the clock frequencies are scaled by 7/8.

1.5.3 Real-Time Clock (RTC)

The RTC is driven directly by the crystal oscillator. It is powered by the net RTC_NV (battery-backed up

supply). The RTC consists of a counter chain and output registers. The counter chain consists of registers

for seconds, minutes, hours, day of week, day of month, month, and year. The RTC is capable of

processing leap years. Each counter has its own output register. The RTC registers will not be affected

by the reset pin, watchdog timer resets, or by transitions between the battery modes and mission mode.

Whenever the MPU reads the seconds register, all other output registers are automatically updated.

Since the RTC clock is not coherent to the MPU clock, the MPU must read the seconds register until two

consecutive reads are the same (this requires either 2 or 3 reads). At this point, all RTC output registers

will have the correct time. Regardless of the MPU clock speed, RTC reads require one wait state.

RTC time is set by writing to the RTC_SEC[5:0] through RTC_YR registers. Each write operation must be

preceded by a write operation to the WE register in I/O RAM. The value written to the WE register is

unimportant.

Time adjustments are written to the RTCA_ADJ[6:0], PREG[16:0] and QREG[1:0] registers. Updates to

PREG[16:0] and QREG[1:0] must occur after the one second interrupt, and must be finished before reaching

the next one-second boundary. The new values are loaded into the counters at the next one-second

boundary.

PREG[16:0] and QREG[1:0] are separate registers in the device hardware, but the bits are 16-bit contiguous

so the MPU firmware can treat them as a single register. A single binary number can be calculated and

then loaded into them at the same time.

The 71M6533 and 71M6534 have two rate adjustment mechanisms. The first is an analog rate adjustment,

using RTCA_ADJ[6:0], which trims the crystal load capacitance. Setting RTCA_ADJ[6:0] to 00 minimizes

the load capacitance, maximizing the oscillator frequency. Setting RTCA_ADJ[6:0] to 0x7F maximizes the

load capacitance, minimizing the oscillator frequency. The adjustable capacitance is approximately:

ADJRTCA

ADJ

5.16

128

_⋅=

The typical adjustment range is approximately -15 ppm. The precise amount of adjustment will depend

on the crystal and board properties. The adjustment may occur at any time, and the resulting clock frequency

can be measured over a one-second interval.

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 39

The second rate adjustment is a digital rate adjust using PREG[16:0] and QREG[1:0], which can be used

to adjust the clock rate up to ± 988 ppm, with a resolution of 3.8 ppm. Updates must occur after a one

second interrupt, and must finish before the next one second boundary. The rate adjustment will be

implemented starting at the next one-second boundary. Since the LSB results in an adjustment every

four seconds, the frequency should be measured over an interval that is a multiple of four seconds.

To adjust the clock rate using the digital rate adjust, the appropriate values must be written to PREG[16:0]

and QREG[1:0]. The default frequency is 32,768 RTCLK cycles per second. To shift the clock frequency

by ∆ ppm, calculate PREG[16:0] and QREG[1:0] using the following equation:











+

⋅∆+

⋅

=+⋅ −5.0

101

832768

floorQREGPREG46

For example, for a shift of -988 ppm, 4⋅PREG + QREG = 262403 = 0x40103. PREG[16:0] = 0x10040, and

QREG[1:0] = 0x03. The default values of PREG[16:0] and QREG[1:0], corresponding to zero adjustment,

are 0x10000 and 0x0, respectively.

The RTC timing may be observed on the TMUXOUT pin by setting TMUX[4:0] to 0x10 or 0x11.

Default values for RTCA_ADJ[6:0], PREG[16:0] and QREG[1:0] should be nominal values, at the

center of the adjustment range. Uncalibrated extreme values (zero, for example) can cause incorrect

operation.

If the crystal temperature coefficient is known, the MPU can integrate temperature and correct the RTC

time as necessary.

Both RTCA_ADJ[6:0] and PREG[16:0]/QREG[1:0] are non-volatile registers, i.e. their values will be

preserved in BROWNOUT, SLEEP and LCD modes. However, the digital correction controlled by the

PREG[16:0]/QREG[1:0] registers is not operational in SLEEP mode.

The digital adjustment using PREG[16:0] and QREG[1:0] is preferred over the analog adjustment using

RTCA_ADJ: The digital adjustment is more repeatable and has a wider range.

The sub-second register of the RTC, SUBSEC, can be read by the MPU after the one-second interrupt and

before reaching the next one second boundary. SUBSEC contains the count remaining, in 1/256 second

nominal clock periods, until the next one-second boundary. When the RST_SUBSEC bit is written, the

SUBSEC counter is restarted. Reading and resetting the sub-second counter can be used as part of an

algorithm to accurately set the RTC.

When setting the RTC_SEC register, it is important to take into account that the associated write operation

will be performed only in the next second boundary.

1.5.4 Temperature Sensor

The device includes an on-chip temperature sensor for determining the temperature of the bandgap

reference. If automatic temperature measurement is not performed by selecting CHOP_E[1:0] = 00, the

MPU may request an alternate multiplexer frame containing the temperature sensor output by asserting

MUX_ALT. The primary use of the temperature data is to determine the magnitude of compensation

required to offset the thermal drift in the system (see Section 3.5 Temperature Compensation).

1.5.5 Physical Memory

Flash Memory

The device includes 128 KB (71M6533/H, 71M6534) or 256 KB (71M6533G, 71M6534H) of on-chip flash

memory. The flash memory primarily contains MPU and CE program code. It also contains images of

the CE and MPU data in RAM as well as of I/O RAM. On power-up, before enabling the CE, the MPU

copies these images to their respective locations.

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

40 Rev 2

The flash memory is segmented into individually erasable pages that contain 1024 bytes.

Flash space allocated for the CE program is limited to 4096 16-bit words (8 KB). The CE program must

begin on a 1 KB boundary of the flash address space. The CE_LCTN[7:0] word defines which 1 KB

boundary contains the CE code. Thus, the first CE instruction is located at 1024*CE_LCTN[7:0].

Flash Write Procedures

The MPU may write to the flash memory. This is one of the non-volatile storage options available to the

user in addition to external EEPROM.

FLSH_PWE (flash program write enable) differentiates 80515 data store instructions (MOVX@DPTR,A)

between Flash and XRAM writes. This bit must be cleared by the MPU after each byte write operation.

Write operations to this bit are inhibited when interrupts are enabled.

The MPU cannot write to flash while the CE is executing its code from flash. Two interrupts warn of collisions

between the MPU firmware and the CE timing. If a flash write operation is attempted while the CE is

busy, the flash write will not execute and the FWCOL0 interrupt will be issued. If a flash write is still in

progress when the CE would otherwise begin a code pass, the code pass is skipped, the write operation

is completed, and the FWCOL1 interrupt is issued.

The simplest flash write procedure disables the CE during the write operation and interpolates the metering

measurements. However, this results in the loss of at least one second of data, because the CE has to

resynchronize with the mains voltage.

There is a brief guaranteed interval (typically 1/32768 s) between CE executions which occurs 2520 times

per second. The start of the interval can be detected with the CE_BUSY interrupt which occurs on the

falling edge of CE_BUSY (an internal signal measurable from TMUXOUT). However, this guaranteed idle

time (30.5 µs) is too short to write a byte which takes 42 µs or to erase a page of flash memory which

takes at least 20 ms. Some CE code has substantially longer idle times, but in those cases, firmware

interrupt latencies can easily consume the available write time. If a flash write fails in this scheme, the

failure can be detected with the FWCOL0 or FWCOL1 interrupt and the write can be retried.

It is practical to pre-erase pages, disable interrupts and poll the CE_BUSY interrupt flag, IRCON[2]. This

method avoids problems with interrupt latency, but can still result in a write failure if the CE code takes

too much time. As mentioned above, polling FWCOL0 and FWCOL1 can detect write failures. However,

the speed in a polling write is only 2520 bytes per second and the firmware cannot respond to interrupts.

As an alternative to using flash, a small EEPROM can store data without compromises. EEPROM interfaces

are included in the device.

Updating Individual Bytes in Flash Memory

The original state of a flash byte is 0xFF (all ones). Once a value other than 0xFF is written to a flash

memory cell, overwriting with a different value usually requires that the cell be erased first. Since cells

cannot be erased individually, the page has to be copied to RAM, followed by a page erase. After this,

the page can be updated in RAM and then written back to the flash memory.

Flash Erase Procedures

Flash erasure is initiated by writing a specific data pattern to specific SFR registers in the proper sequence.

These special pattern/sequence requirements prevent inadvertent erasure of the flash memory.

The mass erase sequence is:

1. Write 1 to the FLSH_MEEN bit (SFR 0xB2[1]).

2. Write the pattern 0xAA to FLSH_ERASE (SFR 0x94).

The mass erase cycle can only be initiated when the ICE port is enabled.

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 41

The page erase sequence is:

1. Write the page address to FLSH_PGADR[5:0] (SFR 0xB7[7:2]).

2. Write the pattern 0x55 to FLSH_ERASE (SFR 0x94).

Note: Transitions to BROWNOUT mode must be avoided during page erase operations.

Bank-Switching

The program memory of the 71M6533/71M6534 consists of a fixed lower bank of 32 KB, addressable at

0x0000 to 0x7FFF plus an upper banked area of 32 KB, addressable at 0x8000 to 0xFFFF. The upper 32

KB space is banked using the I/O RAM FL_BANK[2:0] register as shown in Table 38.: Note that when

FL_BANK[2:0] = 0, the upper bank is the same as the lower bank.

Table 38: Bank Switching with FL_BANK[2:0]

71M6533/H

71M6534

FL_BANK[1:0]

71M6534H

71M6533G

FL_BANK[2:0]

Address Range for Lower Bank

(0x000-0x7FFF)

Address Range for Upper Bank

(0x8000-0xFFFF)

000

0x0000-0x7FFF

001

0x8000-0xFFFF

010

0x10000-0x17FFF

011

0x18000-0x1FFFF

Not applicable

in 71M6533/H

and 71M6534

100

0x20000-0x27FFF

101

0x28000-0x2FFFF

110

0x30000-0x37FFF

111

0x38000-0x3FFFF

Program Security

When enabled, the security feature limits the ICE to global flash erase operations only. All other ICE

operations are blocked. This guarantees the security of the user’s MPU and CE program code. Security

should be enabled by MPU code that is executed during the pre-boot interval (60 CKMPU cycles before

the primary boot sequence begins). Once security is enabled, the only way to disable it is to perform a

global erase of the flash, followed by a chip reset.

The first 60 cycles of the MPU boot code are called the pre-boot phase because during this phase the

ICE is inhibited. A read-only status bit, PREBOOT, identifies these cycles to the MPU. Upon completion

of pre-boot, the ICE can be enabled and is permitted to take control of the MPU.

The security enable bit, SECURE, is reset whenever the chip is reset. Hardware associated with the bit

permits only ones to be written to it. Thus, pre-boot code may set SECURE to enable the security feature

but may not reset it. Once SECURE is set, the pre-boot code is protected and no external read of program

code is possible

Specifically, when SECURE is set, the following applies:

• The ICE is limited to bulk flash erase only.

• Page zero of flash memory, the preferred location for the user’s pre-boot code, may not be

page-erased by either MPU or ICE. Page zero may only be erased with global flash erase.

• Writes to page zero, whether by MPU or ICE are inhibited.

MPU/CE RAM

The 71M6533 and 71M6534 includes 4 KB of static RAM memory on-chip (XRAM) plus 256 bytes of internal

RAM in the MPU core. The 4 KB of static RAM are used for data storage for both MPU and CE operations.

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

42 Rev 2

1.5.6 Optical Interface

The device includes an interface to implement an IR/optical port. The pin OPT_TX is designed to directly

drive an external LED for transmitting data on an optical link. The pin OPT_RX has the same threshold

as the RX pin, but can also be used to sense the input from an external photo detector used as the receiver

for the optical link. OPT_TX and OPT_RX are connected to a dedicated UART port (UART1).

The OPT_TX and OPT_RX pins can be inverted with configuration bits OPT_TXINV and OPT_RXINV,

respectively. Additionally, the OPT_TX output may be modulated at 38 kHz. Modulation is available

when system power is present (i.e. not in BROWNOUT mode). The OPT_TXMOD bit enables modulation.

The duty cycle is controlled by OPT_FDC[1:0], which can select 50%, 25%, 12.5%, and 6.25% duty cycle. A

6.25% duty cycle means OPT_TX is low for 6.25% of the period. Figure 8 illustrates the OPT_TX generator.

OPT_TXMOD = 0 OPT_TXMOD = 1,

OPT_FDC = 2 (25%)

1/38kHz

OPT_TXINV

from

OPT_TX UART MOD

EN DUTY

OPT_TX

OPT_TXMOD

OPT_FDC

OPT_TXE[1:0]

V3P3

Internal

AB0

DIO2

WPULSE

VARPULSE

Figure 8: Optical Interface

When not needed for the optical UART, the OPT_TX pin can alternatively be configured as DIO2,

WPULSE, or VARPULSE. The configuration bits are OPT_TXE[1:0]. Likewise, OPT_RX can alternately

be configured as DIO_1. Its control is OPT_RXDIS.

In the 71M6534, a multiplexer allows the selection of alternate pins DIO18/MTX and DIO22/RTX for

UART1. This function is controlled with the UMUX_E and UMUX_SEL bits in I/O RAM.

1.5.7 Digital I/O

The device includes up to 40 pins (71M6533) or 53 pins (71M6534) of general purpose digital I/O. These

pins are compatible with 5 V inputs (no current limiting resistors are needed). The Digital I/O pins can be

categorized as follows:

• Dedicated DIO pins (5 pins): DIO3, DIO56, DIO57, DIO58, PB

• DIO/LCD segment pins

o A total of 33 pins for the 71M6533:

DIO4/SEG24 - DIO11/SEG31 (8 pins)

DIO13/SEG33 - DIO21/SEG41 (9 pins)

DIO23/SEG43 – DIO27/SEG47 (5 pins)

DIO29/SEG49 - DIO30/SEG50 (2 pins)

DIO41/SEG61 (1 pin)

DIO43/SEG63 - DIO45/SEG65 (3 pins)

DIO47/SEG67 – DIO51/SEG71 (5 pins)

o A total of 46 pins for the 71M6534:

DIO4/SEG24 – DIO30/SEG50 (27 pins)

DIO36/SEG56 – DIO39/SEG59 (4 pins)

DIO41/SEG61 – DIO55/SEG75 (15 pins)

• DIO pins combined with other functions (2 pins): DIO2/OPT_TX, DIO1/OPT_RX

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 43

On reset or power-up, all DIO pins are inputs until they are configured for the desired direction under

MPU control. The pin function can be configured by the I/O RAM bits LCD_BITMAPn. Setting

LCD_BITMAPn = 1 configures the pin for LCD, setting LCD_BITMAPn = 0 configures it for DIO.

Once a pin is configured as DIO, it can be configured independently as an input or output with the

DIO_DIR bits or the LCD_SEGn registers. Input and output data are written to or read from the pins using

SFR registers P0, P1, and P2.

Table 39 through

Table 42 shows all the DIO pins with their configuration, direction control and data registers. Table

entries marked with an asterisk and grayed are applicable to the 71M6534 only.

Table 39: Data/Direction Registers and Internal Resources for DIO 1-15

DIO

12*

LCD Segment

–

32*

71M6533 Pin #

–

71M6534 Pin #

114

109

120

Configuration (DIO

or LCD segment) Always DIO

LCD_BITMAP[31:24]

LCD_BITMAP[39:32]

Data Register

DIO0 = P0 (SFR 0x80)

DIO1 = P1 (SFR 0x90)

Direction Register

0 = input, 1 = output

–

DIO_DIR0 (SFR 0xA2)

DIO_DIR1 (SFR 0x91)

Internal Resources

Configurable

Y Y Y Y Y Y Y Y Y Y Y Y – – – –

Table 40: Data/Direction Registers and Internal Resources for DIO 16-30

DIO

22*

28*

–

LCD Segment

42*

48*

–

71M6533 Pin #

–

71M6534 Pin #

115

Configuration (DIO

or LCD segment)

–

LCD_BITMAP[39:32]

LCD_BITMAP[47:40]

LCD_BITMAP[55:48]

Data Register

–

DIO2 = P2 (SFR 0xA0)

DIO3 = P3 (SFR 0xB0)

Direction Register

0 = input, 1 = output

LCD_SEG44[3]

LCD_SEG45[3]

LCD_SEG46[3]

LCD_SEG47[3]

LCD_SEG48[3]*

LCD_SEG49[3]

LCD_SEG50[3]

DIO_DIR2 (SFR 0xA1)

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

44 Rev 2

Table 41: Data/Direction Registers and Internal Resources for DIO 36-47

DIO

–

36*

37*

38*

39*

–

42*

46*

LCD Segment

–

56*

57*

58*

59*

–

62*

66*

71M6533 Pin #

–

71M6534 Pin #

–

117

118

Configuration (DIO

or LCD segment)

–

LCD_BITMAP[55:48]

LCD_BITMAP[63:56]

LCD_BITMAP[71:64]

Data Register – – – –

LCD_SEG56[0]*

LCD_SEG57[0]*

LCD_SEG58[0]*

LCD_SEG59[0]*

–

LCD_SEG61[0]

LCD_SEG62[0]*

LCD_SEG63[0]

LCD_SEG64[0]

LCD_SEG65[0]

LCD_SEG66[0]*

LCD_SEG67[0]

Direction Register

0 = input, 1 = output – – – –

LCD_SEG56[3]*

LCD_SEG57[3]*

LCD_SEG58[3]*

LCD_SEG59[3]*

LCD_SEG61[3]

LCD_SEG62[3]*

LCD_SEG63[3]

LCD_SEG64[3]

LCD_SEG65[3]

LCD_SEG66[3]*

LCD_SEG67[3]

Table 42: Data/Direction and Internal Resources for DIO 48-58

DIO

52*

53*

54*

55*

LCD Segment

72*

73*

74*

75*

–

71M6533 Pin #

–

71M6534 Pin #

Configuration (DIO

or LCD segment)

Always DIO

LCD_BITMAP[71:64]

LCD_BITMAP[80:72]

Data Register

LCD_SEG68[0]

LCD_SEG69[0]

LCD_SEG70[0]

LCD_SEG71[0]

LCD_SEG72[0]*

LCD_SEG73[0]*

LCD_SEG74[0]*

LCD_SEG75[0]*

DIO_56[4]

DIO_57[4]

DIO_58[4]

Direction Register

0 = input, 1 = output

LCD_SEG68[3]

LCD_SEG69[3]

LCD_SEG70[3]

LCD_SEG71[3]

LCD_SEG72[3]*

LCD_SEG73[3]*

LCD_SEG74[3]*

LCD_SEG75[3]*

DIO_DIR56[7]

DIO_DIR57[7]

DIO_DIR58[7]

See the tables in the I/O RAM Description (Section 5.2) for exact bit locations. For example,

DIO43 is controlled by LCD_SEG63[0] which resolves to I/O RAM location 0x2045[4].

DIO24 and higher do not have SFR registers for direction control. DIO36 and higher do not have SFR

registers for data access. The direction control of these pins is achieved with the LCD_SEGn[3] registers

and data access is controlled with the LCD_SEGn[0] registers in I/O RAM. DIO56 through DIO58 are

dedicated DIO pins. They are controlled with DIO_DIR56[7] through DIO_DIR58[7] (direction) and with

DIO_56[4] through DIO_58[4] (data) in I/O RAM.

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 45

Since the control for DIO_24 through DIO_55 is shared with the control for LCD segments, the firmware

must take care not to disturb the DIO pins when accessing the LCD segments and vice versa. Usually,

this requires reading the I/O RAM register, applying a mask and writing back the modified byte.

DIO4 and DIO5 can be configured to implement the EEPROM Interface.

Additionally, if DIO6 and DIO7 are configured as DIO and defined as outputs, they can be used as dedicated

pulse outputs (WPULSE = DIO6, VARPULSE = DIO7) using the DIO_PW and DIO_PV bits. In this case,

DIO6 and DIO7 are under CE control. Similarly, DIO8 and DIO9 can be declared pulse outputs (XPULSE =

DIO8, YPULSE = DIO9).

The PB pin is a dedicated digital input. In addition, if the optical UART is not used, OPT_TX and OPT_RX can

be configured as dedicated DIO pins, DIO1and DIO2, respectively (see Section 1.5.6 Optical Interface).

Tracking DIO pins configured as outputs is useful for pulse counting without external hardware.

Either the interrupts or the counter/timer clocks can be used to count the pulse outputs, or

interrupt on the CE’s power failure output.

A 3-bit configuration word, I/O RAM register DIO_Rn (0x2009[2:0] through 0x200E[6:4]) can be used for

certain pins (when configured as DIO) to individually assign an internal resource such as an interrupt or a

timer control (DIO_RRX configures the RX pin). This way, DIO pins can be tracked even if they are

configured as outputs. See Table 39 for DIO pins available for this option.

Table 43 lists the internal resources which can be assigned using DIO_R0 (also called DIO_RPB) through

DIO_R7. If more than one input is connected to the same resource, the resources are combined using a

logical OR.

Table 43: Selectable Resources using the DIO_Rn Bits

DIO_Rn

Resource Selected for DIO Pin

None

Reserved

T0 (counter0 clock)

T1 (counter1 clock)

High priority I/O interrupt (INT0 rising)

Low priority I/O interrupt (INT1 rising)

High priority I/O interrupt (INT0 falling)

Low priority I/O interrupt (INT1 falling)

When driving LEDs, relay coils etc., the DIO pins should sink the current into GNDD (as shown in

Figure 9, right), not source it from V3P3D (as shown in Figure 9, left). This is due to the resistance

of the internal switch that connects V3P3D to either V3P3SYS or VBAT.

Sourcing current into or out of DIO pins other than the PB pin, for example with pull-up or pull-

down resistors, should be avoided. Violating this rule will lead to increased quiescent current in

SLEEP and LCD modes.

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

46 Rev 2

Figure 9: Connecting an External Load to DIO Pins

1.5.8 LCD Drivers

The device contains a total of 57 (71M6533) or 75 (71M6534) dedicated and multiplexed LCD drivers,

which are grouped as follows:

• 15 dedicated LCD segment drivers (SEG0 to SEG2, SEG8, SEG12 to SEG18, SEG20 to SEG23)

• 4 drivers multiplexed with the SPI port (SEG3 to SEG6)

• 2 drivers multiplexed with MUX_SYNC and CKTEST (SEG7 and SEG19)

• 3 or 8 drivers multiplexed with the ICE interface

o 71M6533 – 3 drivers (SEG9 to SEG11)

o 71M6534 – 8 drivers (SEG9 to SEG11 and SEG51 to SEG55)

• 33 or 46 multi-use LCD/DIO pins described in Section 1.5.7 Digital I/O

o 71M6533 – 33 pins

o 71M6534 – 46 pins

With a minimum of 15 driver pins always available and a total of 57 (71M6533) or 75 (71M6534) driver

pins in the maximum configuration, the device is capable of driving between 60 to 228 pixels (71M6533)

or 60 to 300 pixels (71M6534) of an LCD display with 25% duty cycle. At eight pixels per digit, this

corresponds to 7.5 to 28 digits for the 71M6533 or 7.5 to 37 digits for the 71M6534. The LCD interface is

flexible and can drive 7-segment digits, 14- segments digits or enunciator symbols.

For each multi-use pin, the corresponding LCD_BITMAP[] bit (see Section 1.5.7 Digital I/O) is used to select

the pin for DIO or LCD operation. The mapping of the LCD_BITMAP[] bits is specified in Section 5.1 I/O

RAM and SFR Map –Functional Order. The LCD drivers are supported by the four common pins (COM0

– COM3).

LCD segment data is written to the LCD_SEGn[3:0] I/O RAM registers as described in Section 5.2 I/O

RAM Description – Alphabetical Order. Note that even though the register names call out bit numbers 3

to 0 some registers use physical bits 4 to 7.

The segment driver SEG18 can be configured to blink at either 0.5 Hz or 1 Hz. The blink rate is controlled

by LCD_Y. There can be up to four pixels/segments connected to this driver pin. The I/O RAM field

LCD_BLKMAP18[3:0] identifies which pixels, if any, are to blink.

The LCD bias may be compensated for temperature using the LCD_DAC[2:0] bits in I/O RAM. The bias

may be adjusted from 1.4 V below the 3.3 V supply (V3P3SYS in mission mode and BROWNOUT

V3P3SYS

VBAT

V3P3D

DIO

GNDD

MISSION

BROWNOUT

LCD/SLEEP

LOW

HIGH

HIGH-Z

V3P3SYS

VBAT

V3P3D

DIO

GNDD

MISSION

BROWNOUT

LCD/SLEEP

LOW

HIGH

HIGH-Z

RecommendedNot recommended

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 47

modes, VBAT in LCD mode). When the LCD_DAC[2:0] bits are set to 000, the DAC is bypassed and

powered down. This can be used to reduce current in LCD mode.

1.5.9 Battery Monitor

The battery voltage is measured by the ADC during alternative MUX frames if the BME (Battery Measure

Enable) bit is set. While BME is set, an on-chip 45 kΩ load resistor is applied to the battery and a scaled

fraction of the battery voltage is applied to the ADC input. After each alternative MUX frame, the result of

the ADC conversion is available at XRAM address 0x07. BME is ignored and assumed zero when system

power is not available.

If VBAT is connected to a drained battery or disconnected, a battery test that sets BME may drain

VBAT’s supply and cause the oscillator to stop. A stopped oscillator may force the device to reset.

Therefore, an unexpected reset during a battery test should be interpreted as a battery failure.

Battery measurement is not very linear but is very reproducible. The best way to perform the calibration

is to set the battery input to the desired failure voltage and then have the MPU firmware record that

measurement. After this, the MPU firmware’s battery measurement logic may use the recorded value as

the battery failure limit. The same value can also be a calibration offset for any battery voltage display.

See Section 6.4.5 for details regarding the ADC LSB size and the conversion accuracy.

1.5.10 EEPROM Interface

The 71M6533 and 71M6534 provides hardware support for either a two-pin or a three-wire (µ-wire) type

of EEPROM interface. The interfaces use the EECTRL and EEDATA registers for communication.

Two-pin EEPROM Interface

The dedicated 2-pin serial interface communicates with external EEPROM devices. The interface is

multiplexed onto the DIO4 (SCK) and DIO5 (SDA) pins and is selected by setting DIO_EEX[1:0] = 01.

The MPU communicates with the interface through the SFR registers EEDATA and EECTRL. If the MPU

wishes to write a byte of data to the EEPROM, it places the data in EEDATA and then writes the Transmit

code to EECTRL. This initiates the transmit operation which is finished when the BUSY bit falls. INT5 is also

asserted when BUSY falls. The MPU can then check the RX_ACK bit to see if the EEPROM acknowledged

the transmission.

A byte is read by writing the Receive command to EECTRL and waiting for the BUSY bit to fall. Upon

completion, the received data is in EEDATA. The serial transmit and receive clock is 78 kHz during each

transmission, and then holds in a high state until the next transmission. The EECTRL bits when the two-pin

interface is selected are shown in Table 44.

Table 44: EECTRL Bits for 2-pin Interface

Status

Bit Name

Read/

Write

Reset

State Polarity Description

ERROR

Positive

1 when an illegal command is received.

BUSY

Positive

1 when serial data bus is busy.

RX_ACK

Negative

0 indicates that the EEPROM sent an ACK bit.

4 TX_ACK R 1 Negative

0 indicates when an ACK bit has been sent to the

EEPROM.

3:0 CMD[3:0] W 0000 Positive

CMD[3:0]

Operation

0000

No-op command. Stops the I2C clock

(SCK, DIO4). If not issued, SCK

keeps toggling.

0010

Receive a byte from the EEPROM

and send ACK.

0011

Transmit a byte to the EEPROM.

0101

Issue a STOP sequence.

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

48 Rev 2

Status

Bit Name Read/

Write

Reset

State Polarity Description

0110

Receive the last byte from the

EEPROM and do not send ACK.

1001

Issue a START sequence.

Others

No operation, set the ERROR bit.

The EEPROM interface can also be operated by controlling the DIO4 and DIO5 pins directly. In

this case, a resistor has to be used in series with SDA to avoid data collisions due to limits in the

speed at which the SDA pin can be switched from output to input. However, controlling DIO4 and

DIO5 directly is discouraged, because it may tie up the MPU to the point where it may become too

busy to process interrupts.

Three-wire (µ-Wire) EEPROM Interface

A 500 kHz three-wire interface, using SDATA, SCK, and a DIO pin for CS is available. The interface is

selected by setting DIO_EEX[1:0] = 2. The EECTRL bits when the three-wire interface is selected are

shown in Table 45. When EECTRL is written, up to 8 bits from EEDATA are either written to the EEPROM

or read from the EEPROM, depending on the values of the EECTRL bits.

The µ-Wire EEPROM interface is only functional when MPU_DIV[2:0] = 000.

Table 45: EECTRL Bits for the 3-wire Interface

Control

Bit

Name Read/

Write

Description

7 WFR W

Wait for Ready. If this bit is set, the trailing edge of BUSY will be delayed

until a rising edge is seen on the data line. This bit can be used during

the last byte of a Write command to cause the INT5 interrupt to occur

when the EEPROM has finished its internal write sequence. This bit is

ignored if HiZ=0.

BUSY

Asserted while the serial data bus is busy. When the BUSY bit falls, an

INT5 interrupt occurs.

HiZ

Indicates that the SD signal is to be floated to high impedance immediately

after the last SCK rising edge.

Indicates that EEDATA is to be filled with data from EEPROM.

3:0 CNT[3:0] W

Specifies the number of clocks to be issued. Allowed values are 0

through 8. If RD=1, CNT bits of data will be read MSB first, and right

justified into the low order bits of EEDATA. If RD=0, CNT bits will be

sent MSB first to the EEPROM, shifted out of the MSB of EEDATA. If

CNT[3:0] is zero, SDATA will simply obey the HiZ bit.

The timing diagrams in Figure 10 through Figure 14 describe the 3-wire EEPROM interface behavior. All

commands begin when the EECTRL register is written. Transactions start by first raising the DIO pin that

is connected to CS. Multiple 8-bit or less commands such as those shown in Figure 10 through Figure 14

are then sent via EECTRL and EEDATA.

When the transaction is finished, CS must be lowered. At the end of a Read transaction, the EEPROM

will be driving SDATA, but will transition to HiZ (high impedance) when CS falls. The firmware should

then immediately issue a write command with CNT=0 and HiZ=0 to take control of SDATA and force it to

a low-Z state.

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 49

Figure 10: 3-wire Interface. Write Command, HiZ=0.

Figure 11: 3-wire Interface. Write Command, HiZ=1

Figure 12: 3-wire Interface. Read Command.

Figure 13: 3-Wire Interface. Write Command when CNT=0

Figure 14: 3-wire Interface. Write Command when HiZ=1 and WFR=1

SCLK (output)

BUSY (bit)

CNT Cycles (6 shown)

SDATA (output)

Write -- No HiZ

D2D3D4D5D6D7

EECTRL Byte Written INT5

SDATA output Z

(LoZ)

CNT Cycles (6 shown)

Write -- With HiZ

INT5

EECTRL Byte Written

SCLK (output)

BUSY (bit)

SDATA (output) D2D3D4D5D6D7

(HiZ)(LoZ)

SDATA output Z

CNT Cycles (8 shown)

READ

D0D1D2D3D4D5

INT5

D6D7

EECTRL Byte Written

SCLK (output)

BUSY (bit)

SDATA (input)

SDATA output Z

(HiZ)

CNT Cycles (0 shown)

Write -- No HiZ

INT5 not issued

CNT Cycles (0 shown)

Write -- HiZ

INT5 not issued

EECTRL Byte Written EECTRL Byte Written

SCLK (output)

BUSY (bit)

SDATA (output)

SCLK (output)

BUSY (bit)

SDATA (output)

(HiZ)

SDATA output ZSDATA output Z

(LoZ)

CNT Cycles (6 shown)

Write -- With HiZ and WFR

EECTRL Byte Written

SCLK (output)

BUSY (bit)

SDATA (out/in)

D2D3D4D5D6D7 BUSY READY

(From EEPROM)

INT5

(From 6520)

SDATA output Z

(HiZ)(LoZ)

From 653X

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

50 Rev 2

1.5.11 SPI Slave Port

The slave SPI port communicates directly with the MPU data bus and is able to read and write Data RAM

locations. It is also able to send commands to the MPU. The interface to the slave port consists of the

PCSZ, PCLK, PSDI and PSDO pins. These pins are multiplexed with the LCD segment driver pins SEG3

to SEG6. The port pins default to LCD driver pins. The port is enabled by setting the SPE bit.

Possible applications for the SPI interface are:

1) An external host reads data from CE locations to obtain metering information. This can be used in

applications where the 71M6533 or 71M6534 function as a smart front-end with preprocessing

capability. Since the addresses are in 16-bit format, any type of XRAM data can be accessed: CE,

MPU, I/O RAM, but not SFRs or the 80515-internal register bank.

2) A communication link can be established via the SPI interface: By writing into MPU memory

locations, the external host can initiate and control processes in the 71M6533/71M6534 MPU.

Writing to a CE or MPU location normally generates an interrupt, a function that can be used to signal

to the MPU that the byte that had just been written by the external host must be read and processed.

Data can also be inserted by the external host without generating an interrupt.

3) An external DSP can access front-end data generated by the ADC. This mode of operation uses the

71M6533 or 71M6534 as an analog front-end (AFE).

A typical SPI transaction is as follows: While PCSZ is high, the port is held in an initialized/reset state.

During this state, PSDO is held in HiZ state and all transitions on PCLK and PSDI are ignored. When

PCSZ falls, the port will begin the transaction on the first rising edge of PCLK. The transaction ends

when PCSZ is raised. At this point, the SPI interrupt is generated. Some transactions may consist of a

command only. The read transaction consists of the following parts:

1. 8-bit command word generated by the host

2. 16-bit address generated by the host

3. 8-bit datum provided by the slave (71M653x)

4. Optionally, more 8-bit data bytes (71M653x)

The write transaction consists of the following parts:

1. 8-bit command word generated by the host

2. 16-bit address generated by the host

3. 8-bit datum provided by the host

4. Optionally, more 8-bit data bytes provided by the host

The optional data bytes are part of an auto-increment mode, where the read or write address is

incremented by 1 after every read or write operation and does not have to be generated by the host. This

operation mode is useful for quickly accessing fields of adjacent data in one long SPI command

sequence.

Table 46 lists I/O RAM registers (bit fields) that are involved in SPI transactions.

Table 46: SPI Registers

Description

SP_ADDR[15:8]

SP_ADDR[7:0]

SPI Address. 16-bit address from the bus master. This register does not auto-incre-

ment and reading this register will not reflect the next available address after an auto-

increment command.

SP_CMD

SPI command. 8-bit command from the bus master.

SPE

SPI port enable. Enables the SPI interface.

SPI_FLAG

SPI interrupt flag. The flag is set by the hardware and is cleared by the firmware writ-

ing a 0. Firmware using this interrupt should clear the spurious interrupt indication

during initialization.

In order to allow access from the external host, the SPE bit has to be set. The SP_CMD and

SP_ADDR[15:0] bit fields contain a copy of the command word and address sent by the SPI master.

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 51

The SPI_FLAG flag bit will be set upon every SPI transaction regardless of whether the command is 11xx

xxxx or 10xx xxxx. The SP_ADDR[15:0] bit field is for writing purposes by the host only. Data read from

SP_ADDR[15:0] will not contain the next available SPI address after an auto-increment operation.

The last issued SPI command and address (if part of the command) are available to the MPU in registers

SP_CMD and SP_ADDR.

The SPI port supports data transfers at 1 Mb/s in mission mode, and 16 kb/s in BROWNOUT mode. The

SPI port may operate at higher speeds under certain conditions. For SPI speeds higher than 1 Mbit/s, the

following conditions apply:

• Write operations can be issued by the host at up to 2 Mbits/s.

• Read operations can be issued at up to 2 Mbit/s, if a minimum gap of 1 µs is inserted by the host

between the last PSCK clock of the SPI address and the first clock of the data read. This gap will

give the hardware of the 71M653x sufficient time to fetch and provide the read data.

A read transaction performed at 2 Mbit/s is shown in Figure 15.

Figure 15: SPI Slave Port: Read Operation with Gap

Figure 16 illustrates the SPI Interface read and write timing.

Table 47: SPI Command Description

Command

Description

11xx xxxx ADDR Byte0 ... ByteN Read data starting at ADDR. The address value provided in ADDR will

be automatically incremented until PCSZ is raised. Upon completion:

SP__CMD=11xx xxxx

An MPU interrupt is generated.

10xx xxxx ADDR Byte0 ... ByteN

Write data starting at ADDR. The address value provided in ADDR will

be automatically incremented until PCSZ is raised. Upon completion:

SP_CMD=10xx xxxx

An MPU interrupt is generated.

0xxx xxxx ADDR Byte0 ... ByteN

Commands other than 1xxx xxxx are ignored, but an SPI interrupt is still

generated when PCSZ goes high.

Certain I/O RAM registers can be written and read using the SPI port (see Table 48). However, the MPU

takes priority over the I/O RAM bus, and SPI operation may fail without notice. To avoid this situation, the

SPI host should send a command other than 11xxxxxx or 10xxxxxx (read or write) before the actual read

or write command. The SPI slave interface will load the command register and generate an INT2 interrupt

upon receiving the command. The MPU should service the interrupt and halt any external data memory

operations to effectively grant the bus to the SPI. When the SPI host finishes, it should send another

PCLK

PSDI

PSDO

Command Address

1 µs min.

0.5 µs

Data

PCSZ

7 6 5 4 3 1 0 15 6 5 4 3 1 014……………...….2 7 6 5 4 3 1 02

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

52 Rev 2

command so the MPU can access the bus. There are no issues with Data RAM access; SPI and the

MPU will share the bus with no conflicts for Data RAM access.

Table 48: I/O RAM Registers Accessible via SPI

Name Address (hex) Bit Range Read/Write

CE0

2000

7:3

CE1

2001

7:0

CE2

2002

5:3, 1:0

CONFIG0

2004

7:6, 1:0

CONFIG1

2005

5:2, 0

VERSION

2006

7:0

CONFIG2

2007

7:0

DIO0

2008

7, 4:0

DIO1 to DIO6

2009 to 200E

6:4, 2:0

−

200F

7:6, 3:2

RTM0H

2060

1:0

RTM0L

2061

7:0

RTM1H

2062

1:0

RTM1L

2063

7:0

RTM2H

2064

1:0

RTM2L

2065

7:0

RTM3H

2066

1:0

RTM3L

2067

7:0

PLS_W

2080

7:0

PLS_I

2081

7:0

SLOT0 to SLOT9

2090 to 209A

7:0

CE3

209D

3:0

CE4

20A7

7:0

CE5

20A8

7:0

WAKE

20A9

7:5, 3:0

CONFIG3

20AC

7:0

CONFIG4

20AD

7:0

−

20AF

2:0

SPI0

20B0

4, 0

SPI1

20B1

4, 0

VERSION

20C8

7:0

CHIP_ID

20C9

7:0

TRIMSEL

20FD

4:0

TRIMX

20FE

TRIM

20FF

7:0

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 53

V3P3

V3P3 -

400mV

V3P3 - 10mV

VBIAS

Battery

modes

Normal

operation,

WDT

enabled

WDT dis-

abled

A15 A14 A1 A0C0

0 31

D7 D6 D1 D0 D7 D6 D1 D0

C5C6C7

PCSZ

PSCK

PSDI

PSDO

8 bit CMD 16 bit Address DATA[ADDR] DATA[ADDR+1]

7 8 23 24 32 39

Extended Read . . .

SERIAL READ

A15 A14 A1 A0C0

0 31

C5C6C7x

PCSZ

PSCK

PSDI

PSDO

8 bit CMD 16 bit Address DATA[ADDR] DATA[ADDR+1]

7 8 23 24 32 39

Extended Write . . .

SERIAL WRITE

D7 D6 D1 D0 D7 D6 D1 D0 x

HI Z

(From Host)

(From 653X)

(From Host)

(From 653X)

Figure 16: SPI Slave Port: Typical Read and Write Operations

SFR locations, i.e. the control registers internal to the 71M653x MPU, are not accessible via the SPI port.

In cases where these registers have to be accessed, for example to control DIO pins, a protocol that uses

the MPU has to be used for read and write operations involving the SFRs.

1.5.12 Hardware Watchdog Timer

An independent, robust, fixed-duration, watchdog timer (WDT) is included in the 71M6533/71M6534. It

uses the RTC crystal oscillator as its time base and must be refreshed by the MPU firmware at least every

1.5 seconds. When not refreshed on time, the WDT overflows and the

part is reset as if the RESET pin were pulled high, except that the I/O

RAM bits will be in the same state as after a wake-up from SLEEP or LCD

modes (see the I/O RAM description in Section 5.2 for a list of I/O RAM bit

states after RESET and wake-up). 4100 oscillator cycles (or 125 ms) after

the WDT overflow, the MPU will be launched from program address

0x0000.

A status bit, WD_OVF, is set when the WDT overflow occurs. This bit is

preserved in LCD mode (not in SLEEP mode) and can be read by the

MPU when WAKE rises to determine if the part is initializing after a WDT

overflow event or after a power-up. After it is read, the MPU firmware

must clear WD_OVF. The WD_OVF bit is also cleared by the RESET pin.

There is no internal digital state that deactivates the WDT. The WDT can

be disabled by tying the V1 pin to V3P3 (see Figure 17). Of course, this

also deactivates V1 power fault detection. Since there is no method in

firmware to disable the crystal oscillator or the WDT, it is guaranteed that

whatever state the part might find itself in, upon watchdog overflow, the

part will be reset to a known state.

Figure 17: Functions Defined by V1

Asserting ICE_E will also deactivate the WDT. This is the only method that will work in BROWNOUT mode.

In normal operation, the WDT is reset by periodically writing a one to the WDT_RST bit. The watchdog timer

is also reset when the internal signal WAKE=0 (see Section 2.5 Wake Up Behavior).

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

54 Rev 2

If enabled with the IEN_WD_NROVF bit in I/O RAM, an interrupt occurs roughly 1 ms before the WDT resets

the chip. This can be used to determine the cause of a WDT reset since it allows the code to log its state

(e.g. the current PC value, loop counters, flags, etc.) before a WDT reset occurs.

1.5.13 Test Ports (TMUXOUT Pin)

One of the digital or analog signals listed in Table 49 can be selected to be output on the TMUXOUT pin.

The function of the multiplexer is controlled with TMUX[4:0] (I/O RAM 0x20AA[4:0]), as shown in Table 49.

The TMUXOUT pin may be used for diagnosis purposes or in production test. The RTC 1-second output

may be used to calibrate the crystal oscillator. The RTC 4-second output provides even higher precision.

Table 49: TMUX[4:0] Selections

TMUX[4:0]

Mode

Function

Analog

GNDD

Analog

Reserved

Analog

GNDD

Analog

Reserved

Analog

PLL_2P5

Analog

Output of the 2.5 V low-power regulator

Analog

Internal VBIAS voltage (nominally 1.6V)

Analog

Not used

8 - 0x0F

–

Reserved

0x10

Digital

RTC 1-second output

0x11

Digital

RTC 4-second output

0x12

–

Not used

0x13

Digital

V1 comparator output, synchronized to RTCLK

0x14

Digital

Real-time output from the CE

0x15

Digital

WDTR_EN (comparator 1 output AND V1LT3)

0x16

Digital

V2 comparator output (71M6534 only)

0x17

Digital

V1 comparator output, unsynchronized

0x18

Digital

RXD (from Optical interface, w/ optional inversion)

0x19

Digital

MUX_SYNC

0x1A

–

Not used

0x1B

Digital

CKMPU (MPU clock)

0x1C

Digital

Pulse output

0X1D

Digital

RTCLK (output of the oscillator circuit, nominally 32,786Hz)

0X1E

Digital

CE_BUSY (busy interrupt generated by CE, 396µs)

0X1F Digital

XFER_BUSY (transfer busy interrupt generated by the CE,

nominally every 999.7ms)

1.5.14 V2 Comparator (71M6534/6534H Only)

The 71M6534/6534H offers a pin that is connected to an internal comparator. The voltage applied to this

pin is compared to the internal reference voltage (VBIAS). If the voltage at the V2 pin is above VBIAS,

the comparator output will be high (1). The comparator output is reflected at the TMUXOUT pin, when

0x16 is selected for TMUX[4:0].

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 55

2 Functional Description

2.1 Theory of Operation

The energy delivered by a power source into a load can be expressed as:

∫

dttItVE

)()(

Assuming phase angles are constant, the following formulae apply:

 P = Real Energy [Wh] = V * A * cos φ* t

 Q = Reactive Energy [VARh] = V * A * sin φ * t

 S = Apparent Energy [VAh] =

22 QP +

For a practical meter, not only voltage and current amplitudes, but also phase angles and harmonic content

may change constantly. Thus, simple RMS measurements are inherently inaccurate. A modern solid-state

electricity meter IC such as the Teridian 71M6533 and 71M6534 functions by emulating the integral operation

above, i.e. it processes current and voltage samples through an ADC at a constant frequency. As long as

the ADC resolution is high enough and the sample frequency is beyond the harmonic range of interest, the

current and voltage samples, multiplied with the time period of sampling will yield an accurate quantity for

the momentary energy. Summing up the momentary energy quantities over time will result in accumulated

energy.

Figure 18: Voltage, Current, Momentary and Accumulated Energy

Figure 18 shows the shapes of V(t), I(t), the momentary power and the accumulated power, resulting from

50 samples of the voltage and current signals over a period of 20 ms. The application of 240 VAC and 100 A

results in an accumulation of 480 Ws (= 0.133 Wh) over the 20 ms period, as indicated by the accumulated

power curve. The described sampling method works reliably, even in the presence of dynamic phase

shift and harmonic distortion.

-500

-400

-300

-200

-100

100

200

300

400

500

0 5 10 15 20

Current [A]

Voltage [V]

Energy per Interval [Ws]

Accumulated Energy [Ws]

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

56 Rev 2

2.2 System Timing Summary

Figure 19 summarizes the timing relationships between the input MUX states, the CE_BUSY signal and

the two serial output streams. In this example, MUX_DIV[3:0] = 6 and FIR_LEN[1:0] = 1. The duration of

each MUX frame is (M40MHZ/M26MHZ = 00, 10, or 11 assumed):

• 1 + MUX_DIV[3:0] * 1, if FIR_LEN[1:0] = 0 (138 CE cycles), complete MUX frame = 7 CK32 cycles

• 1 + MUX_DIV[3:0] * 2, if FIR_LEN[1:0] = 1 (288 CE cycles) , complete MUX frame = 13 CK32 cycles

• 1 + MUX_DIV[3:0] * 3, if FIR_LEN[1:0] = 2 (384 CE cycles) , complete MUX frame = 19 CK32 cycles

An ADC conversion will always consume an integer number of CK32 clocks. Following this is a single

CK32 cycle where the bandgap voltage is allowed to recover from the change in CROSS.

Figure 19: Timing Relationship between ADC MUX and Compute Engine

Each CE program pass begins when the ADC0 conversion (slot 0, as defined by SLOT0_SEL) begins.

Depending on the length of the CE program, it may continue running until the end of the last conversion.

CE opcodes are constructed to ensure that all CE code passes consume exactly the same number of

cycles. The result of each ADC conversion is inserted into the XRAM when the conversion is complete.

The CE code is written to tolerate sudden changes in ADC data. The exact clock count when each ADC

value is loaded into RAM is shown in Figure 19.

Figure 20 shows that the serial data stream, RTM, begins transmitting at the beginning of state S. RTM,

consisting of 140 CK cycles, will always finish before the next code pass starts.

FLAG

RTM DATA 0 (32 bits)

0 1 0 1 0 1 0 1

FLAG FLAG FLAG

CK32

MUX_SYNC

CKTEST

TMUXOUT/RTM

LSB

SIGN

LSB

SIGN

30 31 30 31 30 31 30 31

LSB

SIGN

RTM DATA 1 (32 bits)

RTM DATA 2 (32 bits)

RTM DATA 3 (32 bits)

Figure 20: RTM Output Format

CK32

MUX_DIV Conversions (MUX_DIV=6 is shown) Settle

ADC MUX Frame

ADC EXECUTION

MUX_SYNC

CE_EXECUTION

RTM

140

MAX CK COUNT

0 300

150

600 900 1200 1500 1800

ADC0 ADC1 ADC2 ADC3 ADC4 ADC5

CK COUNT = CE_CYCLES + floor((CE_CYCLES + 2) / 4)

NOTES:

1. ALL DIMENSIONS ARE 4.9152 MHz CK COUNTS.

2. XFER_BUSY OCCURS ONCE EVERY (PRESAMPS * SUM_CYCLES) CODE PASSES.

CE_BUSY

XFER_BUSY

INITIATED BY A CE OPCODE AT END OF SUM INTERVAL

ADC TIMING

CE TIMING

RTM TIMING

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 57

2.3 Battery Modes

Shortly after system power (V3P3SYS) is applied, the part will be in MISSION mode. MISSION mode

means that the part is operating with system power and that the internal PLL is stable. This mode is the

normal operation mode where the part is capable of measuring energy.

When system power is not available (i.e. when V1<VBIAS), the 71M6533 and 71M6534 will be in one of

three battery modes: BROWNOUT, LCD, or SLEEP mode. Figure 21 shows a state diagram of the various

operation modes, with the possible transitions between modes. For information on the timing of mode

transitions refer to Figure 22 through Figure 24.

Figure 21: Operation Modes State Diagram

When V1 falls below VBIAS or the part wakes up under battery power, the part will automatically enter

BROWNOUT mode (see Section 2.5 Wake Up Behavior). From BROWNOUT mode, the part may enter

either LCD mode or SLEEP mode, as controlled by the MPU via the I/O RAM bits LCD_ONLY and SLEEP.

The transition from MISSION mode to BROWNOUT mode is signaled by the IE_PLLFALL interrupt flag

(SFR 0xE8[7]). The transition in the other direction is signaled by the IE_PLLRISE interrupt flag (SFR

0xE8[6]), when the PLL becomes stable.

Meters that do not require functionality in the battery modes, e.g. meters that only use the SLEEP

mode to maintain the RTC, still need to contain code that brings the chip from BROWNOUT

mode to SLEEP mode. Otherwise, the chip remains in BROWNOUT mode once the system

power is missing and consumes more current than intended.

Similarly, meters equipped with batteries need to contain code that transitions the chip to SLEEP

mode as soon as the battery is attached in production. Otherwise, remaining in BROWNOUT

mode would unnecessarily drain the battery.

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

58 Rev 2

To facilitate transition to SLEEP mode, which is useful when an unprogrammed IC is mounted on a PCB

with a battery installed, the Teridian production test programs the following six-byte sequence into the

flash location starting at address 0x00000: 0x74 - 0x40 - 0x90 - 0x20 - 0xA9 - 0xF0. This sequence

decodes to the following assembler code:

0000: 7440 MOV A,#40 ; set bit 6 in accumulator

0002: 9020A9 MOV DPTR,#20A9 ; point to I/O RAM address 0x20A9

0005: F0 MOVX @DPTR,A ; set bit 6 (sleep) in 0x20A9

Transitions from both LCD and SLEEP mode are initiated by wake-up timer timeout conditions or

pushbutton events. When the PB pin is pulled high (pushbutton is pressed), the IE_PB interrupt flag (SFR

0xE8[4]) is set, and when the wake-up timer times out, the IE_WAKE interrupt flag (SFR 0xE8[5]) is set.

In the absence of system power, if the voltage margin for the LDO regulator providing 2.5 V to the internal

circuitry becomes too low to be safe, the part automatically enters SLEEP mode (BAT_OK false). The

battery voltage must stay above 3 V to ensure that BAT_OK remains true. Under this condition, the

71M6533 and 71M6534 stays in SLEEP mode, even if the voltage margin for the LDO improves (BAT_OK

true). Table 50 shows the circuit functions available in each operating mode.

Table 50: Available Circuit Functions

Circuit Function

System Power

Battery Power (Nonvolatile Supply)

MISSION

BROWNOUT

LCD

SLEEP

Yes

–

CE/MPU Data RAM

Yes

–

FIR

Yes

–

Analog circuits:

Yes

–

MPU clock rate

From PLL, as

defined by

MPU_DIV[2:0]

28.672 kHz

(7/8 of 32768 Hz) – –

MPU_DIV

Yes

–

ICE

Yes

–

DIO Pins

Yes

–

Watchdog Timer

Yes

–

LCD

Yes

–

EEPROM Interface (2-wire)

Yes

Yes (8 kb/s)

–

EEPROM Interface (3-wire)

Yes

Yes (16 kb/s)

–

UART

Yes

300 bd

–

Optical TX modulation

Yes

–

Flash Read

Yes

–

Flash Page Erase

Yes

–

Flash Write

Yes

–

XRAM Read and Write

Yes

–

Wakeup Timer

Yes

Oscillator and RTC

Yes

XRAM data preservation

Yes

–

V3P3D voltage output pin

Yes

–

GPO – GP7 registers

Yes

– indicates not active

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 59

2.3.1 BROWNOUT Mode

In BROWNOUT mode, most non-metering digital functions are active (as shown in Table 50) including

ICE, UART, EEPROM, LCD and RTC. In BROWNOUT mode, a low-bias current regulator will provide

2.5 Volts to V2P5 and V2P5NV. The regulator has an output called BAT_OK to indicate that it has sufficient

overhead. When BAT_OK = 0, the part will enter SLEEP mode. From BROWNOUT mode, the processor

can voluntarily enter LCD or SLEEP modes. When system power is restored, the part will automatically

transition from any of the battery modes to MISSION mode, once the PLL has settled.

The MPU will run at 7/8 of the crystal clock rate in BROWNOUT mode. This permits the UARTs to be

operated at 300 bd. In this mode, the MPU clock has substantial short-term jitter.

The value of MPU_DIV[2:0] will be remembered (not changed) as the part enters and exits BROWNOUT.

MPU_DIV[2:0] will be ignored during BROWNOUT.

While PLL_OK = 0, the I/O RAM bits ADC_E and CE_E are held in the zero state disabling both the ADC and

the CE. When PLL_OK falls, the CE program counter is cleared immediately and all FIR processing halts.

Figure 25 shows the functional blocks active in BROWNOUT mode.

2.3.2 LCD Mode

In LCD mode, the data contained in the LCD_SEGn[3:0] fields is displayed. Up to four LCD segments

connected to the pin SEG18 can be made to blink without the involvement of the MPU, which is disabled

in LCD mode. To minimize power, only segments that might be used should be enabled.

LCD mode can be exited only by system power up, a timeout of the wake-up timer, or a push button.

When the IC exits LCD mode, the MPU can discover the event that caused the exit by reading the interrupt

flags and interpret them as follows:

• IE_WAKE = 1 indicates that the wake timer has expired.

• IE_PB =1 indicates that the pushbutton input (PB) was activated.

• COMPSTAT = 0 indicates that a reset occurred but that main power is not yet available.

• If none of the above conditions applies, system power (V3P3SYS) must have been restored

After the transition from LCD mode to MISSION or BROWNOUT mode, the PC will be at 0x0000, the

XRAM is in an undefined state, and the I/O RAM is only partially preserved (see the description of I/O

RAM states in Section 5.2). GP0[7:0] through GP7[7:0] are preserved unless a hardware reset occurs

(RESET pin is pulled high or power to the part is cycled without a battery being present). Figure 26

shows the functional blocks active in LCD mode.

2.3.3 SLEEP Mode

In SLEEP mode, the battery current is minimized and only the Oscillator and RTC functions are active.

This mode can be exited only by system power-up, a timeout of the wake-up timer, or a push button event.

When the IC exits SLEEP mode, the MPU can discover the event that caused the exit by reading the

interrupt flags and interpret them as follows:

• IE_WAKE = 1 indicates that the wake timer has expired.

• IE_PB =1 indicates that the pushbutton input (PB) was activated.

• COMPSTAT = 0 indicates that a reset occurred but that main power is not yet available.

• If none of the above conditions applies, system power (V3P3SYS) must have been restored

After the transition from SLEEP mode to MISSION or BROWNOUT mode the PC will be at 0x0000, the

XRAM is in an undefined state, and the I/O RAM is only partially preserved (see the description of I/O

RAM states in Section 5.2). GP0[7:0] through GP7[7:0] are preserved unless the a hardware reset occurs

(RESET pin is pulled high or power to the part is cycled without a battery being present). Figure 27

shows the functional blocks active in SLEEP mode.

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

60 Rev 2

Figure 22: Transition from BROWNOUT to MISSION Mode when System Power Returns

Figure 23: Power-Up Timing with V3P3SYS and VBAT Tied Together

time

V3P3SYS

and VBAT

MPU Mode

Battery

Current

MPU Clock

Source

Xtal

PLL

(4.2 MHz)

PLL_OK

MISSION

300 nA

WAKE

Internal

RESETZ

BROWN-

OUT

1024 CK32

cycles

14.5 CK32

cycles

4096 CK32

cycles

V1_OK

Power

System

(V3P3SYS)

MPU Mode

Battery

Current

Transition

MPU Clock

Source

Xtal

PLL

(4.2 MHz/MUX_DIV)

PLL_OK

MISSION

2048...4096

CK32 cycles

300 nA

13..14 CK

cycles

WAKE

BROWNOUT

V1_OK

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 61

Figure 24: Power-Up Timing with VBAT Only

time

VBAT

MPU Mode

Battery

Current

MPU Clock

Source

Xtal

PLL_OK

WAKE

Internal

RESETZ

1024 CK32

cycles

BROWNOUT

14.5 CK32

cycles

VBAT_OK

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

62 Rev 2

Figure 25: Functional Blocks in BROWNOUT Mode

(Inactive blocks in the figure are grayed out.)

∆Σ ADC

CONVERTER

VREF

MUX

XIN

XOUT

VREF

DIO1/OPT_RX

RESET

UART2/OPTICAL

UART1

COM3..0

LCD DISPLAY

DRIVER

DIGITAL I/O

RTCLK (32KHz)

POWER FAULT

GNDD V3P3A

V3P3D

VBAT

VOLT

REG

2.5V to logic

V2P5

TMUXOUT

FAULTZ

TMUX[4:0]

GNDA

VBIAS

OSC

(32 kHz)

MCK

PLL

VREF

TEST

MODE

DIO_DIR

DIO_R

DIO

E_RXTX

RTC

RST_SUBSEC

QREG,PREG

RTC_DAY

RTC_HR

RTC_MIN

RTC_SEC

VBIAS

ICE_E

PLS_INV

PLS_INTERVAL

PLS_MAXWIDTH

CE_LCTN

EQU

PRE_SAMPS

SUM_CYCLES

RTM_0...3

RTM_E

CE_E

OPT_RXDIS

OPT_RXINV

OPT_TXE

OPT_TXINV

OPT_TXMOD

OPT_FDC

LCD_ONLY

SLEEP

V3P3SYS

TEST

MUX

CE_PROG

CK_CE

CK_MPU

VADC

MULTI-

PURPOSE

I/O

RTM

RPULSE

WPULSE

COM0..3

Segments

DIO_1..24

to TMUX

SPI SLAVE

PCMD

EEPROM I/F

FLASH

128 KB/

256 KB

XRAM

4 KB

CE_DATA

PCSZ

PCLK

PSDI

PSDO

SDATA

SCLK

EEDATA

EECTRL

OPT_TX

OPT_RX

PB PB

IRAM

256B

MPU

EMULATOR

E_TCLK

E_RSTZ

DIO2/OPT_TX

DIO3

SEG7/MUX_SYNC

SEG8

SEG9/E_RXTX

SEG10/E_TCLK

SEG11/E_RST

SEG12 ...SEG18

SEG19/CKTEST

DIO29/SEG49...DIO30/SEG50

DIO4/SEG24/SDCK

DIO5/SEG25/SDATA

DIO6/SEG26/WPULSE

DIO7/SEG27/RPULSE

DIO10/SEG30...DIO11/SEG31

DIO41/SEG61

RPULSE

WPULSE

XRAM BUS

IRAM BUS

16 32

CKTEST

DIO_PV

DIO_PW

CKOUT_E

SPE

DIO_EEX

OPT_TXE

ICE_E

SEG0...SEG2

SEG3/PCLK

SEG4/PSDO

SEG5/PCSZ

SEG6/PSDI

FIR

DIO23/SEG43...DIO27/SEG47

DIO13/SEG33...DIO21/SEG41

XPULSE

YPULSE

XPULSE

YPULSE

DIO_PX

DIO_PY

DIO8/SEG28/XPULSE

DIO9/SEG29/YPULSE

SEG20...SEG23

DIO56...DIO58

ICE_E

GP0-GP7

NV RAM

2.5V_NV

RTCA_ADJ

RTC_DATE

RTC_MO

RTC_YR

LCD_DAC

LCD_MODE

LCD_CLK

LCD_E

LCD_BLKMAP

LCD_SEG

LCD_Y

MPU_DIV

CKOUT_E

IBP

ICP

IAP

IAN

IBN

ICN

IDP

IDN

DIO43/SEG63...DIO45/SEG65

DIO47/SEG67...DIO51/SEG71

5/24/2010

V2_OK*

V3_OK*

VBIAS*

V3*

V2*

* 71M6534 only

DIO12/SEG32*

DIO22/SEG42*

DIO28/SEG48*

DIO36/SEG56*...DIO39/SEG59*

DIO42/SEG62*

DIO46/SEG66*

DIO52/SEG72*...DIO55/SEG75*

TEMP

VBAT

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 63

Figure 26: Functional Blocks in LCD Mode

(Inactive blocks in the figure are grayed out.)

∆Σ ADC

CONVERTER

VREF

MUX

XIN

XOUT

VREF

DIO1/OPT_RX

RESET

UART2/OPTICAL

UART1

COM3..0

LCD DISPLAY

DRIVER

DIGITAL I/O

RTCLK (32KHz)

POWER FAULT

GNDD V3P3A

V3P3D

VBAT

VOLT

REG

2.5V to logic

V2P5

TMUXOUT

FAULTZ

TMUX[4:0]

GNDA

VBIAS

OSC

(32 kHz)

MCK

PLL

VREF

TEST

MODE

DIO_DIR

DIO_R

DIO

E_RXTX

RTC

RST_SUBSEC

QREG,PREG

RTC_DAY

RTC_HR

RTC_MIN

RTC_SEC

VBIAS

ICE_E

PLS_INV

PLS_INTERVAL

PLS_MAXWIDTH

CE_LCTN

EQU

PRE_SAMPS

SUM_CYCLES

RTM_0...3

RTM_E

CE_E

OPT_RXDIS

OPT_RXINV

OPT_TXE

OPT_TXINV

OPT_TXMOD

OPT_FDC

LCD_ONLY

SLEEP

V3P3SYS

TEST

MUX

CE_PROG

CK_CE

CK_MPU

VADC

MULTI-

PURPOSE

I/O

RTM

RPULSE

WPULSE

COM0..3

Segments

DIO_1..24

to TMUX

SPI SLAVE

PCMD

EEPROM I/F

FLASH

128 KB/

256 KB

XRAM

4 KB

CE_DATA

PCSZ

PCLK

PSDI

PSDO

SDATA

SCLK

EEDATA

EECTRL

OPT_TX

OPT_RX

PB PB

IRAM

256B

MPU

EMULATOR

E_TCLK

E_RSTZ

DIO2/OPT_TX

DIO3

SEG7/MUX_SYNC

SEG8

SEG9/E_RXTX

SEG10/E_TCLK

SEG11/E_RST

SEG12 ...SEG18

SEG19/CKTEST

DIO29/SEG49...DIO30/SEG50

DIO4/SEG24/SDCK

DIO5/SEG25/SDATA

DIO6/SEG26/WPULSE

DIO7/SEG27/RPULSE

DIO10/SEG30...DIO11/SEG31

DIO41/SEG61

RPULSE

WPULSE

XRAM BUS

IRAM BUS

16 32

CKTEST

DIO_PV

DIO_PW

CKOUT_E

SPE

DIO_EEX

OPT_TXE

ICE_E

SEG0...SEG2

SEG3/PCLK

SEG4/PSDO

SEG5/PCSZ

SEG6/PSDI

FIR

DIO23/SEG43...DIO27/SEG47

DIO13/SEG33...DIO21/SEG41

XPULSE

YPULSE

XPULSE

YPULSE

DIO_PX

DIO_PY

DIO8/SEG28/XPULSE

DIO9/SEG29/YPULSE

SEG20...SEG23

DIO56...DIO58

ICE_E

GP0-GP7

NV RAM

2.5V_NV

RTCA_ADJ

RTC_DATE

RTC_MO

RTC_YR

LCD_DAC

LCD_MODE

LCD_CLK

LCD_E

LCD_BLKMAP

LCD_SEG

LCD_Y

MPU_DIV

CKOUT_E

IBP

ICP

IAP

IAN

IBN

ICN

IDP

IDN

DIO43/SEG63...DIO45/SEG65

DIO47/SEG67...DIO51/SEG71

5/24/2010

V2_OK*

V3_OK*

VBIAS*

V3*

V2*

* 71M6534 only

DIO12/SEG32*

DIO22/SEG42*

DIO28/SEG48*

DIO36/SEG56*...DIO39/SEG59*

DIO42/SEG62*

DIO46/SEG66*

DIO52/SEG72*...DIO55/SEG75*

TEMP

VBAT

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

64 Rev 2

Figure 27: Functional Blocks in SLEEP Mode

(Inactive blocks in the figure are grayed out.)

∆Σ

ADC

CONVERTER

VREF

MUX

XIN

XOUT

VREF

DIO

OPT

RESET

UART

OPTICAL

UART

COM

LCD DISPLAY

DRIVER

DIGITAL I

RTCLK

(

KHz

)

POWER FAULT

GNDD

VBAT

VOLT

REG

V to logic

TMUXOUT

FAULTZ

TMUX

[

]

GNDA

VBIAS

OSC

(

kHz

)

MCK

PLL

VREF

TEST

MODE

DIO

DIR

DIO

RXTX

RTC

RST

SUBSEC

QREG

PREG

RTC

DAY

RTC

MIN

RTC

SEC

VBIAS

ICE

PLS

INV

PLS

INTERVAL

PLS

MAX WI DTH

LCTN

EQU

PRE

SAMPS

SUM

CYCLES

RTM

...

RTM

OPT

RXDIS

OPT

RXINV

OPT

TXE

OPT

TXI NV

OPT

TXMOD

OPT

FDC

LCD

ONLY

SLEEP

SYS

TEST

MUX

PROG

MPU

VADC

MULTI

PURPOSE

RTM

RPULSE

WPULSE

COM

Segments

DIO

to TMUX

SPI SLAVE

PCMD

EEPROM I

FLASH

128

256

XRAM

DATA

PCSZ

PCLK

PSDI

PSDO

SDATA

SCLK

EEDATA

EECTRL

OPT

IRAM

256

MPU

EMULATOR

TCLK

RSTZ

DIO

OPT

DIO

SEG

MUX

SYNC

SEG

RXTX

SEG

TCLK

SEG

RST

SEG

...

SEG

CKTEST

DIO

SEG

...

DIO

SEG

DIO

SEG

SDCK

DIO

SEG

SDATA

DIO

SEG

WPULSE

DIO

SEG

RPULSE

DIO

SEG

...

DIO

SEG

DIO

SEG

XRAM BUS

IRAM BUS

CKTEST

DIO

CKOUT

SPE

DIO

EEX

OPT

TXE

ICE

SEG

...

SEG

PCLK

SEG

PSDO

SEG

PCSZ

SEG

PSDI

FIR

DIO

SEG

...

DIO

SEG

DIO

SEG

...

DIO

SEG

XPULSE

YPULSE

DIO

SEG

XPULSE

DIO

SEG

YPULSE

SEG

...

SEG

DIO

...

DIO

ICE

NV RAM

RTCA

ADJ

RTC

DATE

RTC

LCD

DAC

LCD

MODE

LCD

CLK

LCD

BLKMAP

LCD

SEG

LCD

MPU

DIV

CKOUT

IBP

ICP

IAP

IAN

IBN

ICN

IDP

IDN

DIO

SEG

...

DIO

SEG

DIO

SEG

...

DIO

SEG

2010

VBIAS

6534

only

DIO

SEG

DIO

SEG

DIO

SEG

DIO

SEG

*...

DIO

SEG

DIO

SEG

DIO

SEG

DIO

SEG

*...

DIO

SEG

TEMP

VBAT

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 65

2.4 Fault and Reset Behavior

2.4.1 Reset Mode

When the RESET pin is pulled high, all digital activity stops. The oscillator and RTC module continue to

run. Additionally, all I/O RAM bits are set to their default states. As long as V1, the input voltage at the

power fault block, is greater than VBIAS, the internal 2.5 V regulator will continue to provide power to the

digital section.

Once initiated, the reset mode will persist until the reset timer times out, signified by WAKE rising. This

will occur in 4100 cycles of the real time clock after RESET goes low, at which time the MPU will begin

executing its pre-boot and boot sequences from address 00. See the description of Program Security

in Section 1.5.5 for additional descriptions of pre-boot and boot.

If system power is not present, the reset timer duration will be 2 cycles of the crystal clock at which time

the MPU will begin executing in BROWNOUT mode, starting at address 00.

2.4.2 Power Fault Circuit

The 71M6533 and 71M6534 include a comparator to monitor system power fault conditions. When the

output of the comparator falls (V1<VBIAS), the I/O RAM PLL_OK bit is zeroed and the part switches to

BROWNOUT mode, if a battery is present (and the MPU keeps executing code). If a battery is not

present, as indicated by BAT_OK=0, WAKE will fall and the part will enter SLEEP mode. Once system

power returns the MPU remains in reset and does not transition to MISSION mode until 2048 to 4096

CK32 clock cycles later, when PLL_OK rises. .

There are several conditions the device could be in as system power returns. If the part is in BROWNOUT

mode, it will automatically switch to MISSION mode when PLL_OK rises. It will receive an interrupt indicating

this. No configuration bits will be reset or reconfigured during this transition.

If the part is in LCD or SLEEP mode when system power returns, it will also switch to MISSION mode

when PLL_OK rises. In this case, all configuration bits will be in the reset state due to WAKE having

been zero. The RTC clock will not be disturbed, but the MPU RAM must be re-initialized. The hardware

watchdog timer will become active when the part enters MISSION mode.

If there is no battery when system power returns, the part will switch to MISSION mode when PLL_OK

rises. All configuration bits will be in reset state, and RTC and MPU RAM data will be unknown and must

be initialized by the MPU.

2.5 Wake Up Behavior

As described above, the part will always wake up in MISSION mode when system power is restored.

Additionally, the part will wake up in BROWNOUT mode when PB rises (push button is pressed) or when

a timeout of the wake-up timer occurs.

2.5.1 Wake on PB

If the part is in SLEEP or LCD mode, it can be awakened by a rising edge on the PB pin. This pin is normally

pulled to GND and can be pulled high by a push button depression. Before the PB signal rises, the MPU

is in reset due to WAKE being low. When PB rises, WAKE rises and within three crystal cycles, the MPU

begins to execute. The MPU can determine whether the PB signal woke it up by checking the IE_PB flag.

Figure 28 shows the Wake Up timing.

For debouncing, the PB pin is monitored by a state machine operating from a 32 Hz clock. This circuit will

reject between 31 ms and 62 ms of noise. Detection hardware will ignore all transitions after the initial

rising edge. This will continue until the MPU clears the IE_PB bit.

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

66 Rev 2

Figure 28: Wake Up Timing

2.5.2 Wake on Timer

If the part is in SLEEP or LCD mode, it can be awakened by the wake-up timer. Until this timer times out,

the MPU is in reset due to WAKE being low. When the wake-up timer times out, the WAKE signal rises

and within three CK32 cycles, the MPU begins to execute. The MPU can determine whether the timer

woke it by checking the AUTOWAKE interrupt flag (IE_WAKE).

The wake-up timer begins timing when the part enters LCD or SLEEP mode. Its duration is controlled by

WAKE_PRD[2:0] and WAKE_RES. WAKE_RES selects a timer LSB of either 1 minute (WAKE_RES = 1) or

2.5 seconds (WAKE_RES = 0). WAKE_PRD[2:0] selects a duration of from 1 to 7 LSBs.

The timer is armed by WAKE_ARM = 1. It must be armed at least three RTC cycles before SLEEP or

LCD_ONLY is initiated. Setting WAKE_ARM presets the timer with the values in WAKE_RES and WAKE_PRD

and readies the timer to start when the processor writes to the SLEEP or LCD_ONLY bits. The timer is

reset and disarmed whenever the processor is awake. Thus, if it is desired to wake the MPU periodically

(every 5 seconds, for example) the timer must be rearmed every time the MPU is awakened.

2.6 Data Flow

The data flow between the Compute Engine (CE) and the MPU is shown in Figure 29. In a typical application,

the 32-bit CE sequentially processes the samples from the voltage inputs on pins IA, VA, IB, and VB,

performing calculations to measure active power (Wh), reactive power (VARh), A2h, and V2h for four-quadrant

metering. These measurements are then accessed by the MPU, processed further and output using the

peripheral devices available to the MPU. Figure 29 illustrates the CE/MPU data flow.

Figure 29: MPU/CE Data Flow

time

System

Power

(V3P3SYS)

MPU Mode

PLL_OK

15 CK32

cycles

WAKE

LCD

PB or wake-

up timer

BROWNOUT

MPU

Pre

Processor

Post

Processor

IRQ

Processed

Metering

Data

Pulses

I/O RAM (Configuration RAM)

Samples

Data

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 67

2.7 CE/MPU Communication

Figure 30 shows the functional relationships between the CE and the MPU. The CE is controlled by the

MPU via shared registers in the I/O RAM and in RAM.

The CE outputs two interrupt signals to the MPU: CE_BUSY and XFER_BUSY, which are connected to

the MPU interrupt service inputs as external interrupts. CE_BUSY indicates that the CE is actively

processing data. This signal will occur once every multiplexer cycle. XFER_BUSY indicates that the CE

is updating data to the output region of the RAM. This will occur whenever the CE has finished generating a

sum by completing an accumulation interval determined by SUM_CYCLES[5:0] * PRE_SAMPS[1:0] samples.

Interrupts to the MPU occur on the falling edges of the XFER_BUSY and CE_BUSY signals.

Refer to Section 5.3 CE Interface Description for additional information on setting up the device using the

MPU firmware.

VARSUM

WSUM

APULSEW

APULSER

EXT PULSE

SAG CONTROL

DATA

DIO

XFER BUSY

SAMPLES

MPU

INTERRUPTS

I/O RAM (Configuration RAM)

Mux Control

ADC

DISPLAY (Memory

mapped LCD

segments)

SERIAL

(UART0/1)

EEPROM

VAR

(DIO7)

PULSES

W (DIO6)

CE BUSY

Figure 30: MPU/CE Communication

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

68 Rev 2

3 Application Information

3.1 Connection of Sensors (CT, Resistive Shunt)

Figure 31 through Figure 33 show how resistive dividers, current transformers, Rogowski coils and resistive

shunts are connected to the voltage and current inputs of the 71M6533/71M6534.

The analog input pins of the 71M65XX are designed for sensors with low source impedance. RC

filters with components differing from the components used in the Teridian Demo Boards should be

avoided. See Application Note AN5292 for details on filter implementation.

Figure 31: Resistive Voltage Divider

Figure 32: CT with Single Ended (Left) and Differential Input (Right) Connection

Figure 33: Resistive Shunt (Left), Rogowski Sensor (Right)

Note: Ferrites or other inductive components must not be connected directly to the sensor input pins (InP,

InN Vn).

3.2 Distinction between 71M6533/71M6534 and 71M6533G/H/71M6534H Parts

The 71M6533G, 71M6533H, and 71M6534H (high-accuracy) parts go through an additional process of

characterization during production which makes them suitable to high-accuracy performance over

temperature.

The first process, applied to all parts is the trimming of the reference voltage to the target value of 1.195

The second process, which is applied only to the high-accuracy parts, is the characterization of the re-

ference voltage over temperature. The coefficients for the reference voltage are stored in trim fuses (I/O

RAM registers TRIMBGA, TRIMBGB, TRIMM[2:0]. The MPU can read these trim fuses and calculate the

VA = Vin * R

out

/(R

out

+ R

)

out

Vout

1/N

Iin Iout

Filter

V3P3

InP

InN

V3P3A

OUT

1/N

DIFF

out

V3P3

Vout = dIin /dt

Vout

1/N

Iin

V3P3

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 69

correction coefficients PPM1 and PPMC2 per the formulae given in Section 6.4.15 VREF. See Section 3.5

Temperature Compensation for additional details.

The fuse TRIMBGB is non-zero for the high-accuracy parts and zero for the regular parts. Only partial trim

fuse information is available for the regular parts. The values for PPMC and PPMC2 that are used by the

CE to implement temperature compensation are calculated as follows:

• PPMC = TC1 * 22.46 = (52.46 - TRIMT) * 3.18 * 22.46 = (52.46 - TRIMT) * 71.423

• PPMC2 = TC2 * 1150.1 = –0.444 * 1150.1 = -510.6

The factor TRIMT used to calculate PPMC is derived from the trim fuse TRIMT[7:0].

3.3 Connecting 5 V Devices

All digital input pins of the 71M6533/71M6534 are compatible with external 5 V devices. I/O pins configured

as inputs do not require current-limiting resistors when they are connected to external 5 V devices.

3.4 Temperature Measurement

Measurement of absolute temperature uses the on-chip temperature sensor and applying the following

formula:

NTN

T+

−

=))((

In the above formula T is the temperature in °C, N(T) is the ADC count at temperature T, Nn is the ADC

count at 25°C, Sn is the sensitivity in LSB/°C as stated in the Electrical Specifications, and Tn is +25 °C.

It is recommended that temperature measurements be based on TEMP_RAW_X which is the sum of two

consecutive temperature readings, thus being higher by a factor of two than the raw sensor readings.

Example: At 25°C a temperature sensor value of 483,203,000 (Nn) is read by the ADC. At an unknown

temperature T the value 449.648.000 is read at (N(T)). We determine the absolute temperature by dividing

the difference of Nn and N(T) by 512 times the slope factor (-1180). After this, we add the 25 °C from the

reference measurement:

CCT 5.8025

)1180( 512

0483,203,00-0449.648.00 =+

−⋅

The divisor 512 accounts for the 8-bit shift of the ADC value and for the factor of 2 introduced into the

measurement by the CE which adds two consecutive temperature readings.

3.5 Temperature Compensation

In a typical application, the CE compensates for the temperature dependency of the reference voltage

(see Section 4.1.1). System-wide temperature correction over the entire meter is possible by involving

the MPU. The thermal coefficients processed by the MPU may include the current sensors, the voltage

sensors, and other influences.

3.5.1 Temperature Coefficients

For the 71M6533 and 71M6534 (regular accuracy parts), the temperature coefficient TC2 is given as a

constant that represent typical component behavior (in µV/°C2). TC1 can be calculated for the individual

chip from the contents of the TRIMT[7:0] I/O RAM register. TC1 and TC2 allow compensation for variations

of the reference voltage to within ±40 PPM/°C.

For the high-accuracy parts, individualized coefficients TC1 and TC2 can be retrieved from the on-chip

fuses via TRIMBGA, TRIMBGB, TRIMM[2:0] (see Section 3.2 Distinction between 71M6533/71M6534 and

71M6533G/H/71M6534H Parts). For this part, TC1 and TC2 allow compensation for variations of the

reference voltage to within ±15 PPM/°C

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

70 Rev 2

Since TC1 and TC2 are given in µV/°C and µV/°C2, respectively, the value of the VREF voltage

(1.195V) has to be taken into account when transitioning to PPM/°C and PPM/°C2. This means

that PPMC = 26.84*TC1/1.195 and PPMC2 = 1374*TC2/1.195).

Close examination of the electrical specification (see Table 51) for the parts with regular accuracy reveals

that the achievable deviation is not strictly ±40 PPM/°C over the whole temperature range: Only for

temperatures for which T-22 > 40 (i.e. T > 62°C) or for which T-22 < -40 (i.e. T < -18°C), the data sheet

states ±40 PPM/°C. For temperatures between -18°C and +62°C, the error should be considered

constant at ±1,600 PPM, or ±0.16%.

Similar considerations apply to the high-accuracy parts (see Table 52), where the error around the

calibration temperature should be considered constant at ±600 PPM, or ±0.06%.

Parameter

Condition

Min

Typ

VREF(T) deviation from VNOM(T)

)40,22max(

)(

)()(

−

TTVNOM

TVNOMTVREF

-40 +40 PPM/ºC

Table 51: VREF Definition for the Regular Accuracy Parts

Parameter

Condition

Min

Typ

4 VREF(T) deviation from

VNOM(T)

)40,22max(

)(

)()(

−

TTVNOM

TVNOMTVREF

-15 +15 PPM/ºC

Table 52: VREF Definition for the High-Accuracy Parts

Figure 34 and Figure 35 show this concept graphically. The “box” from -18°C to +62°C reflects the fact

that it is impractical to measure the temperature coefficient of high-quality references at small temperature

excursions. For example, at +25°C, the expected error would be ±3°C * 40 PPM/°C, or just 0.012% for the

regular-accuracy parts..

The maximum deviation of ±2520 PPM (or 0.252%) for the regular-accuracy parts is reached at the

temperature extremes. If the reference voltage is used to measure both voltage and current, the identical

errors of ±0.252% add up to a maximum Wh registration error of ±0.504%.

The maximum deviation of ±945 PPM (or 0.0945%) for the high-accuracy parts is reached at the

temperature extremes. If the reference voltage is used to measure both voltage and current, the identical

errors of ±0.0945% add up to a maximum Wh registration error of ±0.189%.

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 71

Figure 34: Error Band for VREF over Temperature (Regular-Accuracy Parts)

Figure 35: Error Band for VREF over Temperature (High-Accuracy Parts)

4.1.1 Temperature Compensation for VREF

The bandgap temperature is used to digitally compensate the power outputs for the temperature dependence

of VREF, using the CE register GAIN_ADJ (internal temperature compensation). Since the band gap amplifier

is chopper-stabilized via the CHOP_E[1:0] field, the most significant long-term drift mechanism in the voltage

reference is removed.

In internal temperature compensation mode, the CE applies the following formula to determine the GAIN_ADJ

value. In this formula TEMP_X is the deviation from nominal or calibration temperature expressed in multiples

of 0.1 °C:

14 2

16385_ PPMCXTEMPPPMCXTEMP

ADJGAIN ⋅

⋅

-2800

-2400

-2000

-1600

-1200

-800

-400

400

800

1200

1600

2000

2400

2800

-40 -20 020 40 60 80

Error Band (PPM) over Temperature (°C)

±40 PPM/°C

-1200

-800

-400

400

800

1200

-40 -20 020 40 60 80

Error Band (PPM) over Temperature (°C)

±15 PPM/°C

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

72 Rev 2

4.1.2 System Temperature Compensation

In a production electricity meter, the 71M6533 and 71M6534 is not the only component contributing to

temperature dependency. A whole range of components (e.g. current transformers, resistor dividers,

power sources, filter capacitors) will contribute temperature effects.

Since the output of the on-chip temperature sensor is accessible to the MPU, temperature compensation

mechanisms with great flexibility are possible. MPU access to GAIN_ADJ permits a system-wide temperature

correction over the entire meter rather than local to the chip.

4.1.3 Temperature Compensation for the RTC

In order to obtain accurate readings from the RTC, the following calibration procedures are recommended:

1. At the time of meter calibration, the crystal oscillator may be calibrated using the RTCA_ADJ register in

I/O RAM to be as close to 32768 Hz as possible. The recommended procedure is to connect a high-

precision frequency counter to the TMUXOUT pin and select 0x11 for TMUX[4:0]. This will generate a

4-second pulse at TMUXOUT that can be used to trim RTCA_ADJ to the best value.

A wider trim range is achieved with the I/O RAM registers PREG[16:0] and QREG[1:0].

2. When the meter is in service, the MPU takes frequent temperature readings. If the temperature

characteristics of the crystal are known, the temperature readings can be used to modify the settings

for the I/O RAM registers PREG[16:0] and QREG[1:0] in order to keep the crystal frequency close to

32768 Hz.

3. After periods of operation under battery power, the temperature for the time the meter was not powered

can be estimated by averaging the temperatures before and after battery operation. Based on this,

the overall correction for the RTC time can be calculated and applied to the RTC after main power returns

to the meter.

4.2 Connecting LCDs

The 71M6533 and 71M6534 have an on-chip LCD controller capable of controlling static or multiplexed

LCDs. Figure 36 shows the basic connection for an LCD.

The following dedicated and multi-use pins can be assigned as LCD segments:

• 15 dedicated LCD segment pins: SEG0 to SEG2, SEG8, SEG12 to SEG18, SEG20 to SEG23.

• 9 dual-function pins: MUX_SYNC/SEG7, CKTEST/SEG19, E_RXTX/SEG9, E_TCLK/SEG10,

E_RST/SEG11, SEG3/PCLK, SEG4/PSDO, SEG5/PCSZ, SEG6/PSDI.

• 5 additional dual-function pins in the 71M6534: SEG51/E_TBUS0, SEG52/E_TBUS1,

SEG53/E_TBUS2, SEG54/E_TBUS3, SEG55/E_ISYNC

• 33 (71M6533) or 46 (71M6534) combined DIO and segment pins

o 71M6533: SEG24/DIO4 to SEG31/DIO11, SEG33/DIO13 to SEG41/DIO21, SEG43/DIO23 to

SEG47/DIO27, SEG49/DIO29, SEG50/DIO30, SEG61/DIO41, SEG63/DIO43 to

SEG65/DIO45, and SEG67/DIO47 to SEG71/DIO51.

o 71M6534: SEG24/DIO4 to SEG50/DIO30, SEG56/DIO36 to SEG59/DIO39, SEG61/DIO41 to

SEG75/DIO55.

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 73

Figure 36: Connecting LCDs

4.3 Connecting I2C EEPROMs

I2C EEPROMs or other I2C compatible devices should be connected to the DIO pins DIO4 and DIO5, as

shown in Figure 37.

Pull-up resistors of roughly 10 kΩ to V3P3D (to ensure operation in BROWNOUT mode) should be used

for both SCL and SDA signals. The DIO_EEX[1:0] register in I/O RAM must be set to 1 in order to convert

the DIO pins DIO4 and DIO5 to I2C pins SCL and SDA.

Figure 37: I2C EEPROM Connection

4.4 Connecting Three-Wire EEPROMs

µWire EEPROMs and other compatible devices should be connected to the DIO pins DIO4 and DIO5, as

shown in Figure 38 and described below:

• DIO5 connects to both the DI and DO pins of the three-wire device.

• The CS pin must be connected to a vacant DIO pin of the 71M6533/71M6534.

• In order to prevent bus contention, a 10 kΩ to resistor is used to separate the DI and DO signals.

• The CS and CLK pins should be pulled down with a resistor to prevent operation of the three-wire

device on power-up, before the 71M6533/71M6534 can establish a stable signal for CS and CLK.

• The DIO_EEX[1:0] field in I/O RAM must be set to 2 in order to convert the DIO pins DIO4 and DIO5

to µWire pins.

The µ-Wire EEPROM interface is only functional when MPU_DIV[2:0] = 000.

DIO4

DIO5

EEPROM

SCL

SDA

V3P3D

10 k

segments

LCD

commons

71M6533/71M6534

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

74 Rev 2

Figure 38: Three-Wire EEPROM Connection

4.5 UART0 (TX/RX)

The UART0 RX pin should be pulled down by a 10 kΩ resistor and additionally protected by a 100 pF ceramic

capacitor, as shown in Figure 39.

Figure 39: Connections for UART0

4.6 Optical Interface (UART1)

The OPT_TX and OPT_RX pins can be used for a regular serial interface (by connecting a RS_232

transceiver for example), or they can be used to directly operate optical components (for example, an

infrared diode and phototransistor implementing a FLAG interface). Figure 40 shows the basic connections

for UART1. The OPT_TX pin becomes active when the OPT_TXE[1:0] I/O RAM field is set to 00.

The polarity of the OPT_TX and OPT_RX pins can be inverted with the configuration bits, OPT_TXINV

and OPT_RXINV, respectively.

The OPT_TX output may be modulated at 38 kHz when system power is present. Modulation is not

available in BROWNOUT mode. The OPT_TXMOD bit enables modulation. The duty cycle is controlled

by OPT_FDC[1:0], which can select 50%, 25%, 12.5%, and 6.25% duty cycle. A 6.25% duty cycle means

OPT_TX is low for 6.25% of the period. The OPT_RX pin uses digital signal thresholds and may need an

analog filter when receiving modulated optical signals.

With modulation, an optical emitter can be operated at higher current than nominal, enabling it to

increase the distance along the optical path.

If operation in BROWNOUT mode is desired, the external components should be connected to V3P3D.

71M6533/71M6534

10 k

100 pF

EEPROM

100 kΩ

DIO4

DIO5

CLK

V3P3D

100 kΩ

DIOn

10 k

Ω

VCC

71M6533/71M6534

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 75

Figure 40: Connection for Optical Components

4.7 Connecting the V1 Pin

A voltage divider should be used to establish that V1 is in a safe range when the meter is in MISSION

mode (see Figure 41). V1 must be lower than 2.9 V in all cases in order to keep the hardware watchdog

timer enabled. The resistor divider ratio must be chosen so that V1 crosses the VBIAS threshold when

V3P3 is near the minimum supply voltage (3.0 VDC). A series resistor (R3) provides additional hysteresis,

and a capacitor to ground (C1) is added for enhanced EMC immunity.

The amount of hysteresis depends on the choice of R1 and R3: If V1 < VBIAS, approximately 1 µA will

flow into the on-chip V1 comparator causing a voltage drop. If V1 ≥ VBIAS, almost no current will flow

into the comparator. The voltage drop will require V3P3 to be slightly higher for V1 to cross the VBIAS

threshold when V3P3 is rising as compared to when V3P3 is falling. Maintaining sufficient hysteresis

helps to eliminate rapid mode changes which may occur in cases where the power supply is unstable with

V1 close to the VBIAS threshold point.

Figure 41: Voltage Divider for V1

4.8 Connecting the Reset Pin

Even though a functional meter will not necessarily need a reset switch, it is useful to have a reset push-

button for prototyping as shown in Figure 42, left side. The RESET signal may be sourced from V3P3SYS

(functional in MISSION mode only), V3P3D (MISSION and BROWNOUT modes), or VBAT (all modes, if

a battery is present), or from a combination of these sources, depending on the application.

For a production meter, the RESET pin should be protected by the by the external components shown in

Figure 42, right side. R1 should be in the range of 100 Ω and mounted as closely as possible to the IC.

Since the 71M6533 and 71M6534 generates its own power-on reset, a reset button or circuitry, as

shown in Figure 42, is only required for test units and prototypes.

V3P3

R1R3

100pF

GND

16.9kΩ

20kΩ

OPT_TX

OPT_RX

71M6533/71M6534

V3P3SYS

Phototransistor

LED

10 kΩ

100 pF

V3P3SYS

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

76 Rev 2

Figure 42: External Components for the RESET Pin: Push-Button (Left), Production Circuit (Right)

4.9 Connecting the Emulator Port Pins

Even when the emulator is not used, small shunt capacitors to ground (22 pF) should be used for protection

from EMI as illustrated in Figure 43. Production boards should have the ICE_E pin connected to ground

via a resistor of around 200 Ω.

The 71M6534 is capable of supporting a trace emulator. To connect this non-standard emulator, the pins

E_TBUS0 (SEG51) – E_TBUS3 (SEG54) and E_ISYNC (SEG55) have to be brought out to the emulator

interface.

Figure 43: External Components for the Emulator Interface

4.10 Connecting a Battery

It is important that a valid voltage is connected to the VBAT pin at all times. For meters without a battery,

VBAT should be connected directly to V3P3SYS. Designs for meters with batteries need to ensure that

the meter functions even when the battery voltage decreases below the specified voltage for VBAT. This

can be achieved by connecting a diode from V3P3SYS to VBAT. However, the battery test will yield

inaccurate results if that technique is used, since the voltage at V3P3SYS will feed current to the VBAT pin.

A better solution is shown in Figure 44. During the battery test, a DIO pin is activated as an output and

applies a low voltage to the anode of the diode. This prevents the voltage at the power supply to influence

the voltage at the VBAT pin.

E_RST

71M6533/71M6534

E_TCLK

62 Ω

22 pF

LCD Segments

ICE_E

V3P3D

E_RXT

(optional)

RESET

71M6533/

71M6534

GNDD

V3P3D

VBAT/

V3P3D

Reset

Switch

0.1µF

10k

71M6533/

71M6534

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 77

Figure 44: Connecting a Battery

Meters equipped with batteries need to contain code that transitions the chip to SLEEP mode as

soon as the battery is attached in production. Otherwise, remaining in BROWNOUT mode would

add unnecessary drain to the battery.

4.11 Flash Programming

Operational or test code can be programmed into the flash memory using either an in-circuit emulator or

the Flash Programmer Module (TFP-2). The flash programming procedure uses the E_RST, E_RXTX,

and E_TCLK pins. The FL_BANK[2:0] field must be set to the value corresponding to the bank that is

being programmed.

4.12 MPU Firmware Library

All application-specific MPU functions mentioned in Section 3 Application Information are featured in the

Teridian demonstration source code. The code is available as part of the Demonstration Kit for the

71M6533/71M6534. The Demonstration Kits come with the 71M6533/71M6534 preprogrammed with demo

firmware and mounted on a functional sample meter Demo Board. The Demo Boards allow for quick and

efficient evaluation of the IC without having to write firmware or having to supply an in-circuit emulator

(ICE).

4.13 Crystal Oscillator

The oscillator drives a standard 32.768 kHz watch crystal. The oscillator has been designed specifically

to handle these crystals and is compatible with their high impedance and limited power handling capability.

The oscillator power dissipation is very low to maximize the lifetime of any battery backup device attached

to VBAT.

Board layouts with minimum capacitance from XIN to XOUT will require less battery current. Good

layouts will have XIN and XOUT shielded from each other.

For best rejection of electromagnetic interference, connect the crystal body and the ground

terminals of the two crystal capacitors to GNDD through a ferrite bead. No external resistor

should be connected across the crystal, since the oscillator is self-biasing.

71M6533/6534

V3P3A

DIO

Power

Supply

V3P3SYS

VBAT

Battery or

Super

Cap

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

78 Rev 2

4.14 Meter Calibration

Once the Teridian 71M6533 and 71M6534 energy meter device has been installed in a meter system, it

must be calibrated. A complete calibration includes the following:

• Calibration of the metrology section, i.e. calibration for tolerances of the current sensors, voltage dividers

and signal conditioning components as well as of the internal reference voltage (VREF).

• Establishment of the reference temperature (Section 3.2) for temperature measurement and temperature

compensation (Section 3.5).

• Calibration of the battery voltage measurement (Section 1.5.9).

• Calibration of the oscillator frequency (Section 1.5.3) and temperature compensation for the RTC

(Section 4.1.3).

The metrology section can be calibrated using the gain and phase adjustment factors accessible to the

CE. The gain adjustment is used to compensate for tolerances of components used for signal conditioning,

especially the resistive components. Phase adjustment is provided to compensate for phase shifts

introduced by the current sensors or by the effects of reactive power supplies.

Due to the flexibility of the MPU firmware, any calibration method, such as calibration based on energy, or

current and voltage can be implemented. It is also possible to implement segment-wise calibration (depending

on current range).

The 71M6533 and 71M6534 supports common industry standard calibration techniques, such as single-

point (energy-only), multi-point (energy, Vrms, Irms), and auto-calibration.

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 79

5 Firmware Interface

5.1 I/O RAM and SFR Map –Functional Order

In Table 53, unimplemented (U) and reserved (R) bits are shaded in light gray. Unimplemented bits have no memory storage, writing them has no

effect, and reading them always returns zero. Reserved bits may be in use and should not be changed from the values given in parentheses.

Writing values other than those shown in parenthesis to reserved bits may have undesirable side effects and must be avoided.

Non-volatile bits are shaded in dark gray. Non-volatile bits are backed-up during power failures if the system includes a battery connected to the

VBAT pin.

This table lists only the SFR registers that are not generic 8051 SFR registers. Bits marked with † (e.g. UMUX_E†) apply to the 71M6534 only.

Table 53: I/O RAM Map – Functional Order

Name

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Configuration:

CE0

2000

EQU[2:0]

CE_E

CE10MHZ

CE1

2001

PRE_SAMPS[1:0]

SUM_CYCLES[5:0]

CE2

2002

CHOP_E[1:0]

RTM_E

WD_OVF

EX_RTC

EX_XFR

COMP0

2003

PLL_OK

COMPSTAT

CONFIG0

2004

VREF_CAL

PLS_INV

CKOUT_E

VREF_DIS

MPU_DIV[2:0]

CONFIG1

2005

R (0)

R(0)

ECK_DIS

M26MHZ

ADC_E

MUX_ALT

M40MHZ

VERSION

2006

VERSION[7:0]

CONFIG2

2007

OPT_TXE[1:0]

EX_PLL

EX_FWCOL

FIR_LEN[1:0]

OPT_FDC[1:0]

CE3

209D

MUX_DIV[3:0]

CE4

20A7

BOOT_SIZE[7:0]

CE5

20A8

CE_LCTN[7:0]

WAKE

20A9

WAKE_ARM

SLEEP

LCD_ONLY

WAKE_RES

WAKE_PRD[2:0]

TMUX

20AA

TMUX[4:0]

ANACTRL

20AB

R (0000)

LCD_DAC[2:0]

CHOP_I_EN

CONFIG3

20AC

SEL_IBN

CHOP_IB

SEL_IAN

CHOP_IA

CONFIG4

20AD

SEL_IDN

CHOP_ID

SEL_ICN

CHOP_IC

Interrupts and WD Timer:

INTBITS

SFR F8

WD_RST

INT6

INT5

INT4

INT3

INT2

INT1

INT0

IFLAGS

SFR E8

IE_PLLFALL

IE_PLLRISE

IE_WAKE

IE_PB

IE_FWCOL1

IE_FWCOL0

IE_RTC

IE_XFER

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

80 Rev 2

Name

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Digital I/O:

20AF

DIO_RRX[2:0]

DIO0

2008

DIO_EEX[1:0]

OPT_RXDIS

OPT_RXINV

DIO_PW

DIO_PV

OPT_TXMOD

OPT_TXINV

DIO1

2009

DIO_R1[2:0]

DI_RPB[2:0]

DIO2

200A

DIO_R3[2:0]

DIO_R2[2:0]

DIO3

200B

DIO_R5[2:0]

DIO_R4[2:0]

DIO4

200C

DIO_R7[2:0]

DIO_R6[2:0]

DIO5

200D

DIO_R9[2:0]

DIO_R8[2:0]

DIO6

200E

DIO_R11[2:0]

DIO_R10[2:0]

200F

R (00)

U U DIO_PX DIO_PY U U

UMUX_E†

UMUX_SEL†

DIO7/ P0

SFR 80

DIO_0[7:0](Port 0)

DIO8

SFR A2

DIO_DIR0[7:1]

DIO9 / P1

(Port 1) SFR 90 DIO_1[7:5]

DIO_1[3:0]

DIO_1[4]†

DIO10 SFR 91 DIO_DIR1[7:5]

DIO_DIR1[3:0]

DIO_DIR[4]†

DIO11/ P2

(Port 2) SFR A0 DIO_2[7]

DIO_2[5:0]

DIO_2[6]†

DIO12 SFR A1 DIO_DIR2[7]

DIO_DIR2[5:0]

DIO_DIR2[6]†

P3 SFR B0 U DIO3[6] DIO3[5]

DIO3[3] DIO3[2] DIO3[1] DIO3[0]

DIO3[4]†

Flash:

ERASE

SFR 94

FLSH_ERASE[7:0]

FLSHCTL

SFR B2

PREBOOT

SECURE

WRPROT_BT

WRPROT_CE

FLSH_MEEN

FLSH_PWE

FL_BANK SFR B6 U U U U U

FL_BANK[1:0]

FL_BANK[2:0]†

PGADR

SFR B7

FLSH_PGADR[5:0]

Real Time Clock:

RTCCTRL

2010

RST_SUBSEC

RTCA_ADJ

2011

RTCA_ADJ[6:0]

SUBSEC1

2014

SUBSEC[7:0]

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 81

Name

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

RTC0

2015

RTC_SEC[5:0]

RTC1

2016

RTC_MIN[5:0]

RTC2

2017

RTC_HR[4:0]

RTC3

2018

RTC_DAY[2:0]

RTC4

2019

RTC_DATE[2:0]

RTC5

201A

RTC_MO[3:0]

RTC6

201B

RTC_YR[7:0]

RTCADJ_H

201C

PREG[16:14]

RTCADJ_M

201D

PREG[13:6]

RTCADJ_L

201E

PREG[5:0]

QREG[1:0]

201F

RTC write protect register (write data is discarded)

LCD Display Interface:

LCDX

2020

MUX_SYNC_E

BME

R (0)

LCDY

2021

LCD_Y

LCD_E

LCD_MODE[2:0]

LCD_CLK[1:0]

LCD_MAP0

2023

See the detailed description for LCD_BITMAP[ ] in Table 54: I/O RAM Description – Alphabetical

…

LCD_MAP5

2028

LCD_MAP6†

2029

LCD0

2030

See the detailed description for LCD_SEG[ ] in Table 54: I/O RAM Description – Alphabetical

…

LCD41

2059

LCD_BLNK

205A

LCD_BLKMAP19[3:0]

LCD_BLKMAP18[3:0]

Area Reserved for Factory Test:

RTM0H

2060

RTM0[9:8]

RTM0L

2061

RTM0[7:0]

RTM1H

2062

RTM1[9:8]

RTM1L

2063

RTM1[7:0]

RTM2H

2064

RTM2[9:8]

RTM2L

2065

RTM2[7:0]

RTM3H

2066

RTM3[9:8]

RTM3L

2067

RTM3[7:0]

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

82 Rev 2

Name

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SPI Interface:

SPI…

2070

SPE

SP_CMD

2071

SP_CMD[7:0]

SP_ADH

2072

SP_ADDR[15:8]

SP_ADL

2073

SP_ADDR[7:0]

Pulse Generator:

PLS_W

2080

PLS_MAXWIDTH[7:0]

PLS_I

2081

PLS_INTERVAL[7:0]

ADC Mux:

SLOT0

2090

SLOT1_SEL[3:0]

SLOT0_SEL[3:0]

SLOT1

2091

SLOT3_SEL[3:0]

SLOT2_SEL[3:0]

SLOT2

2092

SLOT5_SEL[3:0]

SLOT4_SEL[3:0]

SLOT3

2093

SLOT7_SEL[3:0]

SLOT6_SEL[3:0]

SLOT4

2094

SLOT9_SEL[3:0]

SLOT8_SEL[3:0]

SLOT5

2096

SLOT1_ALTSEL[3:0]

SLOT0_ALTSEL[3:0]

SLOT6

2097

SLOT3_ALTSEL[3:0]

SLOT2_ALTSEL[3:0]

SLOT7

2098

SLOT5_ALTSEL[3:0]

SLOT4_ALTSEL[3:0]

SLOT8

2099

SLOT7_ALTSEL[3:0]

SLOT6_ALTSEL[3:0]

SLOT9

209A

SLOT9_ALTSEL[3:0]

SLOT8_ALTSEL[3:0]

SPI Interrupt:

SPI0 20B0 U U U IEN_SPI U U U

IEN_WD_

NROVF

SPI1 20B1 U U U SPI_FLAG U U U

WD_NROVF_

FLAG

General-Purpose and Non Volatile Registers:

GP0

20C0

GP0[7:0]

…

GP7

20C7

GP7[7:0]

VERSION

20C8

VERSION[7:0]

Serial EEPROM:

EEDATA

SFR 9E

EEDATA[7:0]

EECTRL

SFR 9F

EECTRL[7:0]

† 71M6534 only

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 83

5.2 I/O RAM Description – Alphabetical Order

The following conventions apply to the descriptions in this table:

• Bits with a W (write) direction are written by the MPU into configuration RAM. Typically, they are initially stored in flash memory and copied to

the configuration RAM by the MPU. Some of the more frequently programmed bits are mapped to the MPU SFR memory space. The remaining

bits are mapped to 2xxx.

• Bits with an R (read) direction can be read by the MPU.

• Columns labeled Reset and Wake describe the bit values upon reset and wake, respectively. “NV” in the Wake column means the bit is powered

by the nonvolatile supply and is not initialized. LCD-related registers labeled “L” retain data upon transition from LCD mode to BROWNOUT

mode and vice versa, but do not retain data in SLEEP mode. “–“ means that the value is undefined.

• Write-only bits will return zero when they are read.

• Bits marked with an asterisk (e.g. DIO_DIR1[4]†) are applicable to the 71M6534 only.

Table 54: I/O RAM Description – Alphabetical (by Bit Name)

Name

Location

Reset

Wake

Dir

Description

ADC_E

2005[3]

R/W

Enables ADC and VREF. When disabled, removes bias current.

BME 2020[6] 0 – R/W

Battery Measure Enable. When set, a load current is immediately applied to the battery

and it is connected to the ADC to be measured on Alternative Mux Cycles. See the

MUX_ALT bit.

BOOT_SIZE[7:0] 20A7[7:0] 01 01 R/W

End of space reserved for boot program. The ending address of the boot region is

1024*BOOT_SIZE.

CE10MHZ

2000[3]

R/W

CE clock select. When set, the CE is clocked at 10 MHz. Otherwise, the CE clock

frequency is 5 MHz.

CE_E

2000[4]

R/W

CE enable.

CE_LCTN[7:0]

20A8[7:0]

0x31

R/W

CE program location. The starting address for the CE program is 1024*CE_LCTN.

CHOP_E[1:0] 2002[5:4] 00 00 R/W

Chop enable for the reference bandgap circuit. The value of CHOP will change on the

rising edge of MUXSYNC according to the value in CHOP_E:

00 = toggle, except at the mux sync edge at the end of SUMCYCLE, an alternative

MUX frame is automatically inserted at the end of each accumulation interval.

01 = positive.

10 = reversed.

11 = toggle, no alternative MUX frame is inserted

CHOP_I_EN 20AB[0] 0 0 R/W

When CHOP_I_EN is set, chop mode for the analog current inputs can be enabled

with the CHOP_IA, CHOP_IB, CHOP_IC, and CHOP_ID bits.

CHOP_IA

CHOP_IB

CHOP_IC

CHOP_ID

20AC[0]

20AC[4]

20AD[0]

20AD[4]

R/W When CHOP_I_EN is set, these bits enable chop mode for the respective channel.

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

84 Rev 2

CKOUT_E 2004[4] 0 0 R/W

Control bit for the SEG19/CKOUT pin:

0: The pin is the SEG19 LCD driver

1: The pin is the CK_FIR output (5 MHz in mission mode, 32 kHz in BROWNOUT

mode)

COMPSTAT

2003[0]

Status bit for the V1 comparator (same as V1_OK, see TMUXOUT).

DI_RPB[2:0]

DIO_R1[2:0]

DIO_R2[2:0]

DIO_R3[6:4]

DIO_R4[2:0]

DIO_R5[2:0]

DIO_R6[2:0]

DIO_R7[2:0]

DIO_R8[2:0]

DIO_R9[2:0]

DIO_R10[2:0]

DIO_R11[2:0]

DIO_RRX[2:0]*

2009[2:0]

2009[6:4]

200A[2:0]

200A[6:4]

200B[2:0]

200B[6:4]

200C[2:0]

200C[6:4]

200D[2:0]

200D[6:4]

200E[2:0]

200E[6:4]

20AF[2:0]

R/W

Connects dedicated I/O pins DIO1 through DIO11 as well as input pins PB to internal

resources. If more than one input is connected to the same resource, the Multiple

column in the table below specifies how they are combined.

DIO_Rx[2:0]

Resource

Multiple

000

NONE

001

Reserved

010

T0 (Counter /Timer 0 clock or gate)

011

T1 (Counter /Timer 1 clock or gate)

100

High priority IO interrupt (int0 rising)

101

Low priority IO interrupt (int1 rising)

110

High priority IO interrupt (int0 falling)

111

Low priority IO interrupt (int1 falling)

*DIO_RRX applies to the RX pin.

DIO_DIR0[7:1] SFR A2[7:1] 0 – R/W

Programs the direction of pins DIO7 through DIO1. Writing a 1 indicates an output. A bit

is ignored if the corresponding pin is not configured as DIO. See DIO_PV and DIO_PW

for special options for DIO6 and DIO7. See DIO_EEX[1:0] for special options for DIO4

and DIO5.

DIO_DIR1[7:5,

3:0],

DIO_DIR1[4]†

SFR 91 0 – R/W

Programs the direction of pins DIO15 through DIO8. Writing a 1 indicates an output.

A bit is ignored if the corresponding pin is not configured as DIO. See DIO_PX and

DIO_PY for special options for the DIO8 and DIO9 outputs.

†DIO_DIR1[4]

controlling DIO12 is only applicable to the 71M6534.

DIO_DIR2[7,5:0]

DIO_DIR2[6]† SFR A1 0 – R/W

Programs the direction of pins DIO23 through DIO16. Writing a 1 indicates an output.

A bit is ignored if the corresponding pin is not configured as a DIO.

†

DIO_DIR2[6] controlling DIO22 is only applicable to the 71M6534.

DIO_56

DIO_57

DIO_58

2052[4]

2053[4]

2054[4]

–

– R/W The value on DIO pins 56 through 58. The MPU writes data to these registers to change

the data on these pins.

DIO_DIR56

DIO_DIR57

DIO_DIR58

2052[7]

2053[7]

2054[7]

–

R/W Programs the direction of DIO pins 56 through 58. Writing a 1 indicates an output.

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 85

DIO_0[7:0]

DIO_1[7:0]

DIO_2[7:0]

DIO_3[6:0]

SFR 80

SFR 90

SFR A0

SFR B0

–

R/W

The value on the DIO pins. Pins configured as LCD will read zero. When written, changes

data on pins configured as outputs. Pins configured as LCD or input will ignore writes.

DIO_0[7:0] corresponds to DIO7 through DIO1 and PB (PB is read on DIO_0[0]).

DIO_1[7:0] corresponds to DIO15 through DIO8. (DIO_1[4] corresponding to

DIO12 is only applicable to the 71M6534)

DIO_2[7:0] corresponds to DIO23 through DIO16. (DIO_2[4] corresponding to

DIO22 is only applicable to the 71M6534)

DIO_3[6:0] corresponds to DIO30 through DIO24. (DIO_3[4] corresponding to

DIO28 is only applicable to the 71M6534)

DIO_EEX[1:0] 2008[7:6] 0 0 R/W

When set, converts DIO4 and DIO5 to interface with external EEPROM. DIO4 becomes

SDCK and DIO5 becomes bi-directional SDATA.

DIO_EEX[1:0]

Function

Disable EEPROM interface

2-Wire EEPROM interface

3-Wire EEPROM interface

--not used--

DIO_PV

2008[2]

R/W

Causes VARPULSE to be output on DIO7.

DIO_PW

2008[3]

R/W

Causes WPULSE to be output on DIO6.

DIO_PX

200F[3]

R/W

Causes XPULSE to be output on DIO8.

DIO_PY

200F[2]

R/W

Causes YPULSE to be output on DIO9.

EEDATA[7:0]

SFR 9E

R/W

Serial EEPROM interface data.

EECTRL[7:0]

SFR 9F

R/W

Serial EEPROM interface control.

ECK_DIS 2005[5] 0 0 R/W

Emulator clock disable. When ECK_DIS = 1, the emulator clock is disabled.

If ECK_DIS is set, the emulator and programming devices will be unable to

erase or program the device.

EQU[2:0]

2000[7:5]

R/W

Specifies the power equation to be used by the CE.

EX_XFR

EX_RTC

EX_FWCOL

EX_PLL

2002[0]

2002[1]

2007[4]

2007[5]

R/W

Interrupt enable bits. These bits enable the XFER_BUSY, the RTC_1SEC, the

FirmWareCollision (FWCOL), and PLL interrupts. Note that if one of these interrupts is

to be enabled, its corresponding MPU EX enable must also be set. See Section 1.4.9

Interrupts for details.

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

86 Rev 2

FIR_LEN[1:0] 2007[3:2] 1 1 R/W

FIR_LEN[1:0] controls the length of the ADC decimation FIR filter.

[M40MHZ, M26MHZ] FIR_LEN[1:0]

Resulting FIR

Filter Cycles

Resulting

ADC Gain

[00], [10], or [11]

138

0.110017

288

1.000

384

2.37037

[01]

186

0.113644

384

1.000

588

3.590363

FL_BANK[1:0]

FL_BANK[2:0]†

SFR B6[1:0]

SFR B6[2:0] 1 1 R/W

Flash bank selection. Flash memory above 32 k is mapped to the MPU address space

from 0x8000 to 0xFFFF in 32 KB banks. When MPU address[15] = 1, the address in

flash is mapped to FL_BANK[1:0] or FL_BANK[2:0] (71M6534 only), MPU Address[14:0].

FL_BANK[] is reset by the erase cycle.

FLSH_ERASE

[7:0] SFR 94[7:0] 0 0 W

Flash Erase Initiate. (Default = 0x00). FLSH_ERASE is used to initiate either the Flash

Mass Erase cycle or the Flash Page Erase cycle. Specific patterns are expected for

FLSH_ERASE in order to initiate the appropriate Erase cycle.

0x55 = Initiate Flash Page Erase cycle. Must be proceeded by a write to

FLSH_PGADR @ SFR 0xB7.

0xAA = Initiate Flash Mass Erase cycle. Must be proceeded by a write to

FLSH_MEEN @ SFR 0xB2 and the debug (CC) port must be enabled.

Any other pattern written to FLSH_ERASE will have no effect. The erase cycle is not

completed until 0x00 is written to FLSH_ERASE.

FLSH_MEEN SFR B2[1] 0 0 W

Mass Erase Enable.

0 = Mass Erase disabled (default).

1 = Mass Erase enabled.

Must be re-written for each new Mass Erase cycle.

FLSH_PGADR

[5:0] SFR B7 [7:2] 0 0 W

Flash Page Erase Address. (Default = 0x00)

FLSH_PGADR[5:0] with FL_BANK[2:0], sets the Flash Page Address (page 0 through

127) that will be erased during the Page Erase cycle.

Must be re-written for each new Page Erase cycle.

FLSH_PWE SFR B2[0] 0 0 R/W

Program Write Enable. This bit must be cleared by the MPU after each byte write

operation. Writes to this bit are inhibited when interrupts are enabled.

0 = MOVX commands refer to XRAM Space, normal operation (default).

1 = MOVX @DPTR,A moves A to Program Space (Flash) @ DPTR.

FOVRIDE 20FD[4] 0 0 R/W

Permits the values written by the MPU to temporarily override the values in the fuse

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 87

GP0

…

GP7

20C0

…

20C7

…

R/W

Non-volatile general-purpose registers powered by the RTC supply. These registers

maintain their value in all power modes, but will be cleared on reset. The values of

GP0…GP7

will be undefined if VBAT drops below the minimum value.

IE_FWCOL0

IE_FWCOL1

SFR E8[2]

SFR E8[3]

R/W

Interrupt flags for the Firmware Collision Interrupt. See the Flash Memory section for

details.

IE_PB SFR E8[4] 0 – R/W

PB flag. Indicates that a rising edge occurred on PB. Firmware must write a zero to

this bit to clear it. The bit is also cleared when the MPU requests SLEEP or LCD

mode. On bootup, the MPU can read this bit to determine if the part was woken with

the PB DIO0[0].

IE_PLLRISE SFR E8[6] 0 0 R/W

Indicates that the MPU was woken or interrupted (INT4) by system power becoming

available, or more precisely, by PLL_OK rising. The firmware must write a zero to this

bit to clear it.

IE_PLLFALL SFR E8[7] 0 0 R/W

Indicates that the MPU has entered BROWNOUT mode because system power has

become unavailable (INT4), or more precisely, because PLL_OK fell. This bit will not

be set if the part wakes into BROWNOUT mode because of PB or the WAKE timer.

The firmware must write a zero to this bit to clear it.

IEN_SPI

20B0[4]

R/W

SPI interrupt enable.

IEN_WD_NROVF

20B0[0]

R/W

Active high watchdog near overflow interrupt enable.

IE_XFER

IE_RTC

SFR E8[0]

SFR E8[1]

R/W

Interrupt flags. These flags monitor the XFER_BUSY interrupt and the RTC_1SEC

interrupt. The flags are set by hardware.

IE_WAKE SFR E8[5] 0 – R/W

Indicates that the MPU was awakened by the autowake timer. This bit is typically read

by the MPU on bootup. The firmware must write a zero to this bit to clear it.

INTBITS SFR F8[6:0] – – R/W

Interrupt inputs. The MPU may read these bits to see the status of external interrupts

INT0, INT1 up to INT6. These bits do not have any memory and are primarily intended

for debug use.

LCD_BITMAP

[31:24] 2023[7:0] 0 L R/W

Configuration for DIO11/SEG31 through DIO4/SEG24. Unused bits should be set to zero.

1 = LCD pin, 0 = DIO pin.

LCD_BITMAP

[39:32] 2024[7:0] 0 L R/W

Configuration for DIO19/SEG39 through DIO12/SEG32. LCD_BITMAP[32] ,

corresponding to DIO12/SEG32, is only applicable to the 71M6534. Unused bits

should be set to zero.

1 = LCD pin, 0 = DIO pin.

LCD_BITMAP

[47:40]

2025[7:0] 0 L R/W

Configuration for DIO27/SEG47 through DIO20/SEG40. LCD_BITMAP[42],

corresponding to DIO22/SEG42, is only applicable to the 71M6534. Unused bits should

be set to zero.

1 = LCD pin, 0 = DIO pin.

LCD_BITMAP

[50:48] 2026[2:0] 0 L R/W

Configuration for DIO30/SEG50 through DIO28/SEG48. LCD_BITMAP[48],

corresponding to DIO28/SEG48, is only applicable to the 71M6534. Unused bits should

be set to zero.

1 = LCD pin, 0 = DIO pin.

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

88 Rev 2

LCD_BITMAP

[63:61],

[59:56]†

2027[7:5,3:0] 0 L R/W

Configuration for DIO43/SEG63 through DIO41/SEG61 and DIO39/SEG59 through

DIO36/SEG56. LCD_BITMAP[62], corresponding to DIO42/SEG62, and

LCD_BITMAP[59:56] ,corresponding to DIO39/SEG59 through DIO36/SEG56, are only

applicable to the 71M6534. Unused bits should be set to zero.

1 = LCD pin, 0 = DIO pin.

LCD_BITMAP

[71:64] 2028[7:0] 0 L R/W

Configuration for DIO51/SEG71 through DIO44/SEG64. LCD_BITMAP[66],

corresponding to DIO46/SEG66, is only applicable to the 71M6534. Unused bits should

be set to zero.

1 = LCD pin, 0 = DIO pin.

LCD_BLKMAP18

[3:0]

205A[3:0] 0 L R/W

Identifies which segments connected to SEG18 should blink. 1 means blink. The

most significant bit corresponds to COM3, the least significant bit to COM0.

LCD_CLK[1:0] 2021[1:0] 0 L R/W

Sets the LCD clock frequency for the COM/SEG pins (not the frame rate) according to

the following (fw = 32768 Hz):

00 = fw/512,

01 = fw/256, 10 = fw/128, 11 = fw/64

LCD_DAC[2:0] 20AB[3:1] 0 L R/W

LCD contrast control DAC. Adjusts the LCD voltage in steps of 0.2 V from V3P3SYS

(mission mode) or VBAT (BROWNOUT/LCD modes).

LCD_DAC[2:0]

Resulting LCD Voltage

000

V3P3 or VBAT

001

V3P3 or VBAT – 0.2 V

010

V3P3 or VBAT – 0.4 V

011

V3P3 or VBAT – 0.6 V

100

V3P3 or VBAT – 0.8 V

101

V3P3 or VBAT – 1.0 V

110

V3P3 or VBAT – 1.2 V

111

V3P3 or VBAT – 1.4 V

LCD_E 2021[5] 0 L R/W

Enables the LCD display. When disabled, VLC2, VLC1 and VLC0 are ground as are

the COM and SEG outputs.

LCD_MODE[2:0] 2021[4:2] 0 L R/W

The LCD bias mode. Use the LCD DAC to reduce saturation. The number of states is

the number of commons which are driven to multiplex the LCD.

LCD_MODE[2:0]

Function

Notes

000

4 states, ⅓ bias

⅓ bias modes can drive 3.3 V LCDs.

001

3 states, ⅓ bias

010

2 states, ½ bias

½ bias and static modes can drive

both 3.3 V and 5 V LCDs.

011

3 states, ½ bias

100

static display

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 89

LCD_ONLY 20A9[5] 0 0 W

Puts the 71M6533/71M6534 to sleep, but with the LCD display still active. LCD_ONLY

is ignored if system power is present. While in SLEEP mode, the device will wake up

on reset, when the autowake timer times out, when the push button is pushed, or when

system power returns.

LCD_SEG0[3:0]

…

LCD_SEG18[3:0]

2030[3:0]

…

2042[3:0]

…

R/W

LCD Segment Data. Each word contains information for 1 to 4 time divisions of each

segment.

In each word, bit 0 corresponds to COM0, bit 1 to COM1, bit 2 to COM2 and bit 3 to

COM3 of the first segment. Bits 4 through 7 correspond to COM0 to COM3, respectively,

of the second segment.

Care should be taken when writing to LCD_SEG locations since some of them control

DIO pins.

LCD_SEG32, LCD_SEG42, LCD_SEG48, LCD_SEG51 through LCD_SEG59, LCD_SEG62,

LCD_SEG66, and LCD_SEG72 through LCD_SEG75 are only applicable to the 71M6534.

LCD_SEG19[3:0]

…

LCD_SEG31[3:0]

2043[3:0]

…

204F[3:0]

…

R/W

LCD_SEG32[3:0]†

2050[3:0]

R/W

LCD_SEG33[3:0]

…

LCD_SEG41[3:0]

2051[3:0]

…

2059[3:0]

…

R/W

LCD_SEG42[3:0]†

2030[7:4]

R/W

LCD_SEG43[3:0]

…

LCD_SEG47[3:0]

2031[7:4]

…

2035[7:4]

…

R/W

LCD_SEG48[3:0]†

2036[7:4]

R/W

LCD_SEG49[3:0]

LCD_SEG50[3:0]

2037[7:4]

2038[7:4]

R/W

LCD_SEG51[3:0]†

…

LCD_SEG59[3:0]

†

2039[7:4]

…

2041[7:4]

…

R/W

LCD_SEG61[3:0]

2043[7:4]

R/W

LCD_SEG62[3:0]†

2044[7:4]

R/W

LCD_SEG63[3:0]

…

LCD_SEG65[3:0]

2045[7:4]

…

2047[7:4]

…

R/W

LCD_SEG66[3:0]†

2048[7:4]

R/W

LCD_SEG67[3:0]

…

LCD_SEG71[3:0]

2049[7:4]

…

204D[7:4]

…

R/W

LCD_SEG72[3:0]†

…

LCD_SEG75[3:0]

†

204E[7:4]

…

2051[7:4]

…

R/W

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

90 Rev 2

LCD_Y 2021[6] 0 L R/W

LCD Blink Frequency (ignored if blink is disabled or if the segment is off).

0 = 1 Hz (500 ms ON, 500 ms OFF)

1 = 0.5 Hz (1 s ON, 1 s OFF)

M26MHZ

M40MHZ

2005[4]

2005[0]

R/W

M26MHZ and M40MHZ set the master clock (MCK) frequency. These bits are reset on

chip reset and may only be set. Attempts to write zeroes to M40MHZ and M26MHZ are

ignored.

M40MHZ

M26MHZ

MCK Frequency

20 MHz

26.7 MHz

40 MHz

MPU_DIV[2:0] 2004[2:0] 0 0 R/W

The MPU clock divider (from MCK). These bits may be programmed by MPU without

risk of losing control.

MPU_DIV[2:0]

Resulting Clock Frequency

000

MCK/4

001

MCK/8

010

MCK/16

011

MCK/32

100

MCK/64

101

MCK/128

110

MCK/265

111

MCK/265

MUX_ALT 2005[2] 0 0 R/W

The MPU asserts this bit when it wishes the MUX to perform ADC conversions on an

alternate set of inputs.

If CHOP_E is 00, MUX_ALT is automatically asserted once per sum cycle, when

XFER_BUSY falls.

MUX_DIV[3:0]

209D[3:0]

R/W

The number of states in the input multiplexer.

MUX_SYNC_E

2020[7]

R/W

When set, SEG7 outputs MUX_SYNC. Otherwise, SEG7 is an LCD pin.

OPT_FDC[1:0] 2007[1:0] 0 0 R/W

Selects the modulation duty cycle for OPT_TX.

OPT_FDC[1:0]

Function

50% Low

25% Low

12.5% Low

6.25% Low

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 91

OPT_RXDIS 2008[5] 0 0 R/W

Configures OPT_RX to an analog input to the optical UART comparator or as a digital

input/output, DIO1.

0 = OPT_RX, 1 = DIO1.

OPT_RXINV 2008[4] 0 0 R/W

Inverts the result from the OPT_RX comparator when 1. Affects only the UART input.

Has no effect when OPT_RX is used as a DIO input.

OPT_TXE[1:0] 2007[7:6] 00 00 R/W

Configures the OPT_TX output pin.

OPT_TXE[1:0]

Function

OPT_TX

DIO2

WPULSE

RPULSE

OPT_TXINV

2008[0]

R/W

Inverts OPT_TX when 1. This inversion occurs before modulation.

OPT_TXMOD 2008[1] 0 0 R/W

Enables modulation of OPT_TX. When OPT_TXMOD is set, OPT_TX is modulated

when it would otherwise have been zero. The modulation is applied after any inversion

caused by OPT_TXINV.

PLL_OK

2003[6]

Indicates that system power is present and the clock generation PLL is settled.

PLS_MAXWIDTH

[7:0] 2080[7:0] FF FF R/W

Determines the maximum width of the pulse (low going pulse).

The maximum pulse width is (2*PLS_MAXWIDTH + 1)*TI. Where TI is PLS_INTERVAL

If PLS_INTERVAL = 0, TI is the sample time (397 µs). If set to 255, pulse width control

is disabled and pulses are output with a 50% duty cycle.

PLS_INTERVAL

[7:0] 2081[7:0] 0 0 R/W

For PULSE_W and PULSE_V only, if the FIFO is used, PLS_INTERVAL must be set to

81. If PLS_INTERVAL = 0, the FIFO is not used and pulses are output as soon as the

CE issues them.

PLS_INV 2004[6] 0 0 R/W

Inverts the polarity of the pulse outputs Normally, these pulses are active low. When

inverted, they become active high.

PREBOOT

SFRB2[7]

–

Indicates that the preboot sequence is active.

PREG[16:0]

201C[2:0]

201D[7:0]

201E[7:2]

R/W

RTC adjust. See Section 1.5.3 Real-Time Clock (RTC) for additional details.

0x0FFBF ≤ PREG ≤ 0x10040

PREG[16:0] and QREG[1:0] are separate in hardware but can be programmed with a

single number calculated by the MPU. . PREG[16:0] and QREG[1:0] are non-volatile,

but have no correcting function in SLEEP mode.

PRE_SAMPS[1:0] 2001[7:6] 0 0 R/W

The duration of the pre-summer, in samples.

PRE_SAMPS[1:0]

Pre-Summer Duration

100

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

92 Rev 2

QREG[1:0]

201E[1:0]

R/W

RTC adjust. See Section 1.5.3 Real-Time Clock (RTC) for additional details.

RST_SUBSEC

2010[0]

R/W

The sub-second counter is restarted when a 1 is written to this bit.

RTCA_ADJ[6:0]

2011[6:0]

–

R/W

Analog RTC adjust. See Section 1.5.3 Real-Time Clock (RTC) for additional details.

RTC_SEC[5:0

RTC_MIN[5:0]

RTC_HR[4:0]

RTC_DAY[2:0]

RTC_DATE[4:0]

RTC_MO[3:0]

RTC_YR[7:0]

2015

2016

2017

2018

2019

201A

201B

R/W

These are the year, month, day, hour, minute and second parameters of the RTC.

Writing to these registers sets the time. Each write to one of these registers must be

preceded by a write to 0x201F (WE). Valid values for each parameter are:

SEC: 00 to 59, MIN: 00 to 59, HR: 00 to 23 (00 = Midnight)

DAY: 01 to 07 (01 = Sunday), DATE: 01 to 31, MO: 01 to 12

YR: 00 to 99 (00 and all others divisible by 4 are leap years)

Values in the RTC registers are undefined when the IC powers up without a battery but

are maintained through mission and battery modes when a sufficient voltage is maintained

at the VBAT pin. Write operations to these registers are delayed by one second.

There is no change of value at reset if the voltage at VBAT is within specification.

RTM_E

2002[3]

R/W

Real Time Monitor enable (RTM). When 0, the RTM output is low.

RTM0[7:0]

RTM1[7:0]

RTM2[7:0]

RTM3[7:0]

2060[9:8]

2061[7:0]

2062[9:8]

2063[7:0]

2064[9:8]

2064[7:0]

2065[9:8]

2066[7:0]

R/W The four RTM probes. Before each CE code pass, the values of these registers are

serially output on the RTM pin. The RTM registers are ignored when RTM_E = 0.

SECURE SFRB2[6] 0 – R/W

When set, enables security provisions that prevent external reading of flash memory

and CE program RAM (zeros will be returned if the memory is read). It should be set

while PREBOOT is set. SECURE is cleared when the flash is mass-erased and on chip

reset. The bit may only be set, attempts to write zero are ignored.

SLEEP 20A9[6] 0 0 W

Puts the 71M6533/71M6534 into SLEEP mode. This bit is ignored if system power is

present. The 71M6533 and 71M6534 will wake when the autowake timer times out,

when the push button is pushed, when system power returns or when RESET goes high.

SEL_IAN

SEL_IBN

SEL_ICN

SEL_IDN

20AC[1]

20AC[5]

20AD[1]

20AD[5]

R/W When set to 1, selects differential mode for the corresponding current input (IA, IB, IC,

or ID). When 0, the input remains single-ended.

SLOT0_SEL[3:0]

SLOT1_SEL[3:0]

…

SLOT8_SEL[3:0]

SLOT9_SEL[3:0]

2090[3:0]

2090[7:4]

2094[3:0]

2094[7:4]

…

R/W

Primary multiplexer frame analog input selection. These bits map the selected input,

0-9 to the multiplexer state. The ADC output is always written to the memory location

corresponding to the input, regardless of which multiplexer state an input is mapped to

(see Section 1.1 Error! Not a valid result for table.).

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 93

SLOT0_ALTSEL

[3:0]

SLOT1_ALTSEL

[3:0]

SLOT2_ALTSEL

[3:0]

…

SLOT8_ALTSEL

[3:0]

SLOT9_ALTSEL

[3:0]

2096[3:0]

2096[7:4]

2097[3:0]

…

209A[3:0]

209A[7:4]

…

R/W

Alternate multiplexer frame analog input selection. Maps the selected input, 0-11, to

the multiplexer state.

The additional inputs, 10 and 11 in the alternate frame are:

10 = TEMP

11 = VBAT

SP_ADDR[15:8]

SP_ADDR[7:0]

2072[7:0]

2073[7:0]

–

SPI Address. 16-bit address from the bus master.

SP_CMD

2071

–

SPI command. 8-bit command from the bus master.

SPE

2070[7]

R/W

SPI port enable. Enables the SPI interface on pins SEG3 through SEG6.

SPI_FLAG 20B1[4] R/W

SPI interrupt flag. The flag is set by the hardware and is cleared by the firmware

writing a 0. Firmware using this interrupt should clear the spurious interrupt indication

during initialization.

SUBSEC[7:0] 2014[7:0] – – R

The remaining count, in terms of 1/256 RTC cycles, to the next one second boundary.

SUBSEC may be read by the MPU after the one second interrupt and before reaching

the next one second boundary. Setting RST_SUBSEC will clear SUBSEC.

SUM_CYCLES[5:0]

2001[5:0]

R/W

The number of pre-summer outputs summed in the final summer.

TMUX[4:0] 20AA[4:0] 2 – R/W

Selects one of 32 signals for TMUXOUT. For details, see Section 1.5.13 Test Ports

(TMUXOUT Pin).

TRIM[7:0] 20FF 0 0 R/W

Contains TRIMT[7:0], TRIMBGA,TRIMBGB or TRIMM[2:0] depending on the value

written to TRIMSEL[3:0]. If TRIMBGB = 0, the device is a 71M6533/71M6534, else it is

a 71M6533H/71M6534H.

TRIMSEL[3:0] 20FD[3:0] 0 0 R/W

Selects the temperature trim fuse to be read with the TRIM register:

TRIMSEL[3:0]

Trim Fuse

Purpose

TRIMT[7:0]

Trim for the magnitude of VREF

TRIMM[2:0]

Trim values related to temperature

compensation

TRIMBGA

TRIMBGB

UMUX_E† 200F[7] 0 0 R/W

Enables the optical UART multiplexer, selects the alternate function (MTX, MRX) for

DIO18, DIO22.

UMUX_SEL† S00F[6] 0 0 R/W

When UMUX_E = 1, selects between OPT_TX, OPT_RX and MTX, MRX as the optical

UART I/O pins. 0 = OPT_TX, OPT_RX, 1 = MTX, MRX

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

94 Rev 2

VERSION[7:0] 2006

20C8

–

The device version index. This word may be read by the firmware to determine the

silicon version.

VERSION[7:0]

Silicon Version

0000 0101

A05

VREF_CAL

2004[7]

R/W

Brings VREF to the VREF pad. This feature is disabled when VREF_DIS =1.

VREF_DIS

2004[3]

R/W

Disables the internal voltage reference.

WAKE_ARM 20A9[7] 0 – W

Writing a 1 to this bit arms the autowake timer and presets it with the values presently

in WAKE_PRD and WAKE_RES. The autowake timer is reset and disarmed whenever

the processor is in MISSION mode or BROWNOUT mode. The timer must be armed

at least three RTC cycles before the SLEEP or LCD-ONLY mode is commanded.

WAKE_PRD 20A9[2:0] 001 – R/W

Sleep time. Time = WAKE_PRD[2:0]*WAKE_RES. The default = 001. The maximum

value is 7.

WAKE_RES

20A9[3]

–

R/W

Resolution of WAKE timer: 1 = 1 minute, 0 = 2.5 seconds.

WD_NROVF_

FLAG

20B1[0] – 0 R/W

This flag is set approximately 1 ms before the watchdog timer overflows. It is cleared

by writing a 0 or on the falling edge of WAKE.

WD_RST SFR F8[7] 0 0 W

WD timer bit. This bit must be accessed with byte operations. Operations possible for

this bit are:

Write 0: Clears the flag.

Write 1: Resets the WDT.

WD_OVF 2002[2] 0 NV* R/W

The WDT overflow status bit, set when the WDT overflows. It is preserved in LCD

mode and will indicate at bootup if the part is recovering from a WDT overflow or a

power fault. This bit should be cleared by the MPU on bootup. It is also automatically

cleared when RESET is high.

*Not preserved in SLEEP mode

201F[7:0]

An 8-bit value has to be written to this address prior to accessing the RTC registers.

WRPROT_BT

SFR B2[5]

When set, this bit protects flash addresses from 0 to BOOT_SIZE*1024 from flash page erase.

WRPROT_CE SFR B2[4] 0 0

When set, this bit protects flash addresses from CE_LCTN*1024 to the end of memory

from flash page erase.

† Applicable to the 71M6534 only.

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 95

5.3 CE Interface Description

5.3.1 CE Program

The CE performs the precision computations necessary to accurately measure power. These computations

include offset cancellation, phase compensation, product smoothing, product summation, frequency

detection, VAR calculation, sag detection and voltage phase measurement. All data computed by the CE

is dependent on the selected meter equation as given by EQU[2:0] (in I/O RAM). As a function of

EQU[2:0], the element components V0 through I2 take on different meanings.

The Teridian CE program is supplied as a data image that can be merged with the MPU operational code

for meter applications. Typically, the CE program covers most applications and does not need to be

modified. Other variations of the CE code may be available. The description in this section applies to CE

code revision CE34A02D, which functions for both the 71M6533 and the 71M6534. This version of the

CE code does not process the ID current channel. Also available are CE codes capable of calculating

and measuring the ID channel.

5.3.2 CE Data Format

All CE words are 4 bytes. Unless specified otherwise, they are in 32-bit two’s complement format

(-1 = 0xFFFFFFFF). Calibration parameters are defined in flash memory (or external EEPROM) and

must be copied to CE data memory by the MPU before enabling the CE. Internal variables are used in

internal CE calculations. Input variables allow the MPU to control the behavior of the CE code. Output

variables are outputs of the CE calculations. The corresponding MPU address for the most significant

byte is given by 0x0000 + 4 x CE_address and by 0x0003 + 4 x CE_address for the least significant byte.

5.3.3 Constants

Constants used in the CE Data Memory tables are:

• Sampling Frequency: FS = 32768 Hz/13 = 2520.62 Hz.

• F0 is the fundamental frequency of the mains phases.

• IMAX is the external rms current corresponding to 250 mV pk at the inputs IA, IB and IC.

• VMAX is the external rms voltage corresponding to 250 mV pk at the VA, VB and VC inputs.

• NACC, the accumulation count for energy measurements is PRE_SAMPS[1:0]*SUM_CYCLES[5:0]. This

value also resides in SUM_PRE (CE address 0x23) where it is used for phase angle measurement.

• The duration of the accumulation interval for energy measurements is

PRE_SAMPS[1:0]*SUM_CYCLES[5:0]/FS.

• ln_8 is a gain constant of the current channel, n. Its value is 8 or 1 and is controlled by In_SHUNT.

• X is a gain constant of the pulse generators. Its value is determined by PULSE_FAST and PULSE_SLOW.

• Voltage LSB for sag detection = VMAX * 7.879810-9 V.

The system constants IMAX and VMAX are used by the MPU to convert internal digital quantities (as

used by the CE) to external, i.e. metering quantities. Their values are determined by the scaling of the

voltage and current sensors used in an actual meter. The LSB values used in this document relate digital

quantities at the CE or MPU interface to external meter input quantities. For example, if a SAG threshold

of 80 V peak is desired at the meter input, the digital value that should be programmed into SAG_THR

would be 80 V/SAG_THRLSB, where SAG_THRLSB is the LSB value in the description of SAG_THR.

The parameters EQU[2:0], CE_E, PRE_SAMPS[1:0], and SUM_CYCLES[5:0], essential to the function of

the CE, are stored in I/O RAM (see Section 5.2 I/O RAM Description – Alphabetical Order).

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

96 Rev 2

5.3.4 Environment

Before starting the CE using the CE_E bit, the MPU has to establish the proper environment for the CE by

implementing the following steps:

• Load the CE data into RAM.

• Establish the equation to be applied in EQU[2:0].

• Establish the accumulation period and number of samples in PRE_SAMPS[1:0] and SUM_CYCLES[5:0].

• Establish the number of cycles per ADC multiplexer frame (MUX_DIV[3:0]).

• Apply proper values to SLOTn_SEL[3:0] and SLOTn_ALTSEL[3:0].

• Set PLS_INTERVAL[7:0] to 81.

• Select the proper values for FIR_LEN[1:0] (1) and MUX_DIV[3:0] (6).

• Set CHOP_E[1:0] = 00.

• Initialize any MPU interrupts, such as CE_BUSY, XFER_BUSY, or a power failure detection interrupt.

When different CE codes are used, a different set of environment parameters needs to be established.

The exact values for these parameters are stated in the Application Notes and other documentation

accompanying the CE codes.

Operating CE codes with environment parameters deviating from the values specified will lead to

unpredictable results.

Typically, there are thirteen 32768 Hz cycles per ADC multiplexer frame (see Figure 19 in the System

Timing Summary section). This means that the product of the number of cycles per frame and the number

of conversions per frame must be 12 (allowing for one settling cycle). The default configuration is FIR_LEN

= 1 (two cycles per conversion) and MUX_DIV[3:0] = 6 (6 conversions per mux cycle).

During operation, CHOP_E[1:0] = 00 enables the automatic chopping mode and forces an alternate

multiplexer sequence at regular intervals. This enables accurate temperature measurement.

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 97

5.3.5 CE Calculations

Table 55: CE EQU[2:0] Equations and Element Input Mapping

EQU[

2:0]

Watt & VAR

Formula

(WSUM/VARS

UM)

Element Input Mapping

W0SUM/ VAR0SUM W1SUM/

VAR1SUM

W2SUM/

VAR2SUM

I0SQ

SUM

I1SQ

SUM

I2SQ

SUM

VA IA

(1 element, 2W

)

VA*IA – – IA – –

VA*(IA-IB)/2

(1 element, 3W

)

VA*(IA-IB)/2 – – IA-IB IB –

VA*IA + VB*IB

(2 element, 3W

Delta)

VA*IA VB*IB – IA IB –

VA*(IA-IB)/2 +

VC*IC

(2 element, 4W

Delta)

VA*(IA-IB)/2 – VC*IC IA-IB IB IC

VA*(IA-IB)/2 +

VB*(IC-IB)/2

(2 element, 4W

Wye)

VA*(IA-IB)/2 VB*(IC-IB)/2 – IA-IB IC-IB IC

VA*IA + VB*IB

+ VC*IC

(3 element, 4W

Wye)

VA*IA VB*IB VC*IC IA IB IC

* Only EQU = 5 is supported by CE code version CE34A02D.

5.3.6 CE Front End Data (Raw Data)

Access to the raw data provided by the AFE is possible by reading addresses 0 through B as shown in

Table 56.

Table 56: CE Raw Data Access Locations

Name

Address

Description

MPU

Type

IA FIR data

0x00

Input

ADC Input data, valid at the end of the MUX

frame. The address mapping of analog

inputs to memory is hard-wired in the ADC

converter circuit.

VA FIR data 0x01 0x04 Input

IB FIR data

0x02

0x08

Input

VB FIR data

0x03

0x0C

Input

IC FIR data

0x04

0x10

Input

VC FIR data

0x05

0x14

Input

ID FIR data

0x06

0x18

Input

TEMP FIR data

0x0A

0x28

Input

VBAT FIR data

0x0B

0x2C

Input

…

Internal

…

Chip ID, Version bytes 0x0F 003C Read

Only

Upper 16 bits are zero. Lower 16 bits are

CHIP_ID[15:8], VERSION[7:0]. This word is

read only.

…

Internal

…

Last Address

0x3FF

0xFFC

Internal

Last Memory Location

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

98 Rev 2

5.3.7 CE Status and Control

CESTATUS provides information about the status of voltage and input AC signal frequency, which are useful

for generating early power fail warnings, e.g. to initiate necessary data storage. It contains sag warning

flags for phase A, B, and C, as well as F0, the derived clock operating at the fundamental input frequency.

CESTATUS represents the status flags for the preceding CE code pass (CE_BUSY interrupt). Sag alarms

are not remembered from one code pass to the next. The CE Status word is refreshed at every

CE_BUSY interrupt. The significance of the bits in CESTATUS is shown in Table 57.

CE Address

Name

Description

0x80

CESTATUS

See description of CESTATUS bits in Table 57.

Since the CE_BUSY interrupt typically occurs at 2520.6 Hz, it is desirable to minimize the computation

required in the interrupt handler of the MPU. Rather than reading the CE status word at every CE_BUSY

interrupt and interpret the sag bits, it is recommended that the MPU activate the YPULSE output to generate

interrupts when a sag occurs (see the description of the CECONFIG register)

Table 57: CESTATUS (CE RAM 0x80) Bit Definitions

CESTATUS [bit]

Name

Description

31:29

Not Used

These unused bits will always be zero.

28 F0

F0 is a square wave at the exact fundamental frequency for the phase

selected with the FREQSELn bits in CECONFIG.

27 SAG_C

Normally zero. Becomes one when |VC| remains below SAG_THR for

SAG_CNT samples. Will not return to zero until |VC| rises above SAG_THR.

26 SAG_B

Normally zero. Becomes one when VB remains below SAG_THR for

SAG_CNT

samples. Will not return to zero until VB rises above

SAG_THR

25 SAG_A

Normally zero. Becomes one when VA remains below SAG_THR for

SAG_CNT samples. Will not return to zero until VA rises above SAG_THR.

24:0

Not Used

These unused bits will always be zero.

The CE is initialized by the MPU using CECONFIG. This register contains in packed form SAG_CNT,

FREQSEL0, FREQSEL1, EXT_PULSE, I0_SHUNT, I1_SHUNT, PULSE_SLOW, and PULSE_FAST. The

CECONFIG bit definitions are given in Table 58.

Address

Name Data Description

0x20 CECONFIG 0x5020 See description of the CECONFIG bits in Table 58.

The SAG_MASKn bits enable sag detection for the respective phase when set to 1. When SAG_INT is set

to 1, a sag event will generate a transition on the YPULSE output.

IA_SHUNT, IB_SHUNT and IC_SHUNT can configure their respective current inputs to accept shunt resistor

sensors. In this case the CE provides an additional gain of 8 to the selected current input. WRATE may

need to be adjusted based on the values Ix_SHUNT.

The CE pulse generator can be controlled by either the MPU (external) or CE (internal) variables. Control is by

the MPU if EXT_PULSE = 1. In this case, the MPU controls the pulse rate by placing values into APULSEW

and APULSER. By setting EXT_PULSE = 0, the CE controls the pulse rate based on WSUM_X and VARSUM_X.

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 99

The EXT_TEMP bit enables temperature compensation mode:

• When EXT_TEMP = 0 (internal compensation), the CE will control the gain using GAIN_ADJ (see

Table 59) based on PPMC, PPMC2 and TEMP_X, the difference between die temperature and the

reference / calibration temperature TEMP_NOM. Since PPMC and PPMC2 reflect the typical behavior

of the reference voltage over temperature, the internal temperature compensation eliminates the effects

of temperature-related errors of VREF only.

• When EXT_TEMP = 1 (external compensation), the MPU is allowed to control the CE gain using

GAIN_ADJ, based on any algorithm implemented in MPU code.

The 71M6533 Demo Code creep function halts both internal and external pulse generation.

The FREQSEL1 and FREQSEL0 bits select the phase used to control the CE-internal PLL. CE accuracy

depends on the channel selected by the FREQSEL1 and FREQSEL0 bits receiving a clean voltage signal.

Table 58: CECONFIG Bit Definitions

CECONFIG

[bit]

Name Default Description

[20]

[19]

[18]

SAG_MASK2

SAG_MASK1

SAG_MASK0

When 1, enables sag interrupt based on phase C.

When 1, enables sag interrupt based on phase B.

When 1, enables sag interrupt based on phase A.

If more than one sag mask is set, a sag interrupt will only be

generated when all phases enabled for the interrupt sag.

[17] SAG_INT 0 When 1, enables the sag interrupt to be output on the

YPULSE/DIO9 pin (see Section 1.5.7).

[16] EXT_TEMP 0 When set, enables the control of GAIN_ADJ by the MPU.

When 0, enables the control of GAIN_ADJ by the CE.

[15:8] SAG_CNT 80

(0x50)

The number of consecutive voltage samples below SAG_THR

before a sag alarm is declared. The maximum value is 255.

SAG_THR

is at address 0x24.

[7] FREQSEL1 0

The combination of FREQSEL1 and FEQSEL0 selects the phase

to be used for the frequency monitor, the phase-to-phase lag

calculation,the zero crossing counter (MAINEDGE_X), and the

F0 bit (CESTATUS[28]).

FREQ

SEL1

FREQ

SEL0

Phase

Selected

Phases Used for Voltage

Phase Lag Calculation

PH_A to B_X

PH_A to C_X

A-B

A-C

B-C

B-A

C-A

C-B

Not allowed

[6] FREQSEL0 0

[5] EXT_PULSE 1

When zero, causes the pulse generators to respond to internal

data (WPULSE = WSUM_X, RPULSE = VARSUM_X).

Otherwise, the generators respond to values the MPU places

in APULSEW and APULSER.

[4] IC_SHUNT 0

When 1, the current gain of channel C is increased by 8. The

gain factor controlled by In_SHUNT is referred to as In_8

throughout this document.

[3]

IB_SHUNT

When 1, the current gain of channel B is increased by 8.

[2]

IA_SHUNT

When 1, the current gain of channel A is increased by 8.

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

100 Rev 2

[1] PULSE_FAST 0

When PULSE_FAST = 1, the pulse generator input is increased

16x. When PULSE_SLOW = 1, the pulse generator input is

reduced by a factor of 64. These two bits control the pulse

gain factor X (see table below). Default is 0 for both (X = 6).

PULSE_SLOW

PULSE_FAST

1.5 * 22 = 6

1.5 * 26 = 96

1.5 * 2-4 = 0.09375

Do not use

[0] PULSE_SLOW 0

Table 59: Sag Threshold and Gain Adjust Control

Address

Name Default Description

0x24 SAG_THR 2.39*107

The voltage threshold for sag warnings. The default value is

equivalent to 80 V RMS if VMAX = 600 V. The LSB value is

VMAX * 7.8798*10-9 V. For example, if a sag threshold of 80

V RMS is required:

91039.2

108798.7

280

_⋅=

⋅⋅

⋅

=−

VMAX

THRSAG

0x40 GAIN_ADJ 16384 This register scales all voltage and current channels. The

default value is equivalent to unity gain (1.000).

5.3.8 CE Transfer Variables

When the MPU receives the XFER_BUSY interrupt, it knows that fresh data is available in the transfer

variables. CE transfer variables are modified during the CE code pass that ends with an XFER_BUSY

interrupt. They remain constant throughout each accumulation interval. In this data sheet, the names of

CE transfer variables always end with _X. The transfer variables can be categorized as:

1. Fundamental energy measurement variables

2. Instantaneous (RMS) values

3. Other measurement parameters

Fundamental Energy Measurement Variables

Table 60 describes each transfer variable for fundamental energy measurement. All variables are signed

32-bit integers. Accumulated variables such as WSUM are internally scaled so they have at least 2x

margin before overflow when the integration time is one second. Additionally, the hardware will not

permit output values to fold back upon overflow.

Table 60: CE Transfer Variables

Address

Name Description

0x85

WSUM_X

The signed sum: W0SUM_X+W1SUM_X+W2SUM_X.

0x86

W0SUM_X

The sum of Wh samples from each wattmeter element. In_8 is the

gain 1 or 8 as configured by In_SHUNT.

LSB = 9.4045*10-13 VMAX IMAX / In_8 Wh.

0x87

W1SUM_X

0x88

W2SUM_X

0x8A

VARSUM_X

The signed sum: VAR0SUM_X+VAR1SUM_X+VAR2SUM_X.

0x8B

VAR0SUM_X

The sum of VARh samples from each wattmeter element. In_8 is the

gain 1 or 8 as configured by In_SHUNT.

LSB = 9.4045*10-13 VMAX IMAX / In_8 VARh.

0x8C

VAR1SUM_X

0x8D

VAR2SUM_X

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 101

WSUM_X and VARSUM_X are the signed sum of Phase-A, Phase-B and Phase-C Wh or VARh values

according to the metering equation specified in the I/O RAM register EQU[2:0]. WxSUM_X is the Wh value

accumulated for phase x in the last accumulation interval and can be computed based on the specified

LSB value.

For example, with VMAX = 600 V and IMAX = 208 A, the LSB for WxSUM_X is 0.1173 µWh.

Instantaneous Energy Measurement Variables

Table 61 contains various measurement variables. IxSQSUM_X and VxSQSUM are the squared current and

voltage samples acquired during the last accumulation interval. They can be used to calculate RMS voltages

and currents. INSQSUM_X can be used for computing the neutral current.

Table 61: CE Energy Measurement Variables

Address

Name Description

0x8F

I0SQSUM_X

The sum of squared current samples from each element.

LSBI = 9.4045*10-13 IMAX2 / In_82 A2h

0x90

I1SQSUM_X

0x91

I2SQSUM_X

0x92 INSQSUM_X

The sum of squared current samples from the calculated neutral:

∑

++ 2

210 )( III

LSB=9.4045*10

-13

IMAX

/ In_8

0x99

I0SQRES_X

Residual current measurements with double-precision accuracy. The

exact current is:

ISQn = InSQSUM_X + InSQRES_X

0x9A

I1SQRES_X

0x9B

I2SQRES_X

0x9C

INSQRES_X

0x93

V0SQSUM_X

The sum of squared voltage samples from each element.

LSBV= 9.4045*10-13 VMAX2 V2h

0x94

V1SQSUM_X

0x95

V2SQSUM_X

The RMS values can be computed by the MPU from the squared current and voltage samples as follows:

Other Transfer variables include those available for frequency and phase measurement, and those reflecting

the count of the zero-crossings of the mains voltage and the battery voltage. These transfer variables are

listed in Table 62.

MAINEDGE_X reflects the number of half-cycles accounted for in the last accumulated interval for the AC

signal of the phase specified in the FREQSEL1 and FREQSEL0 registers. MAINEDGE_X is useful for

implementing a real-time clock based on the input AC signal.

ACC

RMS N

FLSBIxSQSUM

Ix ⋅⋅⋅

=3600

ACC

RMS

FLSBVxSQSUM

Vx ⋅⋅⋅

=3600

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

102 Rev 2

Table 62: Other Transfer Variables

Address

Name Description

0x82 FREQ_X Fundamental frequency: LSB

10587.0

−

⋅≈≡

0x97 PH_AtoB_X

Voltage phase lag. The selection of the reference phase is based

on FREQSEL1 and FREQSEL0 in the CECONFIG register:

If FREQSEL1/FREQSEL0 select phase A: Phase lag from A to B.

If FREQSEL1/FREQSEL0 select phase B: Phase lag from B to C.

If FREQSEL1/FREQSEL0 select phase C: Phase lag from C to A.

The angle in degrees is (0 to 360): PH_AtoB_X * 360/N

ACC

+ 2.4

0x98 PH_AtoC_X

If FREQSEL1/FREQSEL0 select phase A: Phase lag from A to C.

If FREQSEL1/FREQSEL0 select phase B: Phase lag from B to A.

If FREQSEL1/FREQSEL0 select phase C: Phase lag from C to B.

Angle in degrees is (0 to 360): PH_AtoC_X * 360/NACC + 4.8

0x83 MAINEDGE_X

The number of edge crossings of the selected voltage in the

previous accumulation interval. Edge crossings are either

direction and are debounced.

0x84 VBAT_SUM_X

The output of the battery measurement. This value is

equivalent to twice the measured ADC value.

5.3.9 Temperature Measurement and Temperature Compensation

Table 63 describes the CE registers supporting temperature measurement and temperature compensation.

Table 63: CE Temperature Registers

Address

Name Default Description

0x81

TEMP_RAW

N/A

The filtered, unscaled reading from the temperature sensor.

0x9D TEMP_X N/A

This register contains the difference between the die temperature

and the reference/calibration temperature as established in the

TEMP_NOM

0x39 DEGSCALE 21755 Scale factor for the temperature calculation. It is not necessary

to use values other than the default value.

0x1F TEMP_NOM 0

This register holds the reference or calibration temperature

vale. At calibration time, the value read in TEMP_RAW must be

written to

TEMP_NOM.

0x3A

PPMC

Linear temperature correction factor.

0x3B

PPMC2

Quadratic temperature correction factor.

5.3.10 Pulse Generation

Table 64 describes the CE pulse generation parameters.

The combination of the PULSE_SLOW and PULSE_FAST parameters (see Table 58) controls the speed of

the pulse rate. The default values of 0 and 0 will maintain the original pulse rate given by the Kh equation.

WRATE controls the number of pulses that are generated per measured Wh and VARh quantities. The

lower WRATE is, the slower the pulse rate for measured energy quantity. The metering constant Kh is

derived from WRATE as the amount of energy measured for each pulse. That is, if Kh = 1Wh/pulse, a

power applied to the meter of 120 V and 30 A results in one pulse per second. If the load is 240 V at

150 A, ten pulses per second will be generated.

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 103

The maximum pulse rate is 3*FS = 7.5 kHz.

Control is transferred to the MPU for pulse generation if EXT_PULSE = 1. In this case, the pulse rate is

determined by APULSEW and APULSER. The MPU loads the source for pulse generation in APULSEW

and APULSER to generate pulses. Irrespective of the EXT_PULSE status, the output pulse rate controlled

by APULSEW and APULSER is implemented by the CE only. By setting EXT_PULSE = 1, the MPU is providing

the source for pulse generation. If EXT_PULSE is 1, W0SUM_X and VAR0SUM_X are the default pulse

generation sources. In this case, creep cannot be controlled since it is an MPU function.

PULSE_WIDTH allows adjustment of the pulse width for compatibility with calibration and other external

equipment. The minimum pulse width possible is 66.16µs.

The maximum time jitter is1/6 of the MUX cycle period (nominally 67 µs) and is independent of the number

of pulses measured. Thus, if the pulse generator is monitored for one second, the peak jitter is 67 ppm.

After 10 seconds, the peak jitter is 6.7 ppm. The average jitter is always zero. If it is attempted to drive

either pulse generator faster than its maximum rate, it will simply output at its maximum rate without

exhibiting any rollover characteristics. The actual pulse rate, using WSUM as an example, is:

XFWSUMWRATE

RATE S

⋅⋅⋅

where FS = sampling frequency (2520.6 Hz), X = Pulse speed factor (as defined in the CECONFIG register

with the PULSE_FAST and PULSE_SLOW bits).

Table 64: CE Pulse Generation Parameters

Address

Name Default Description

0x21

WRATE

171

Kh = VMAX*IMAX*66.1782 / (In_8*WRATE*NACC*X) Wh/pulse.

0x22

KVAR

6448

Scale factor for VAR measurement.

0x23

SUM_PRE

2520

PRE_SAMPS * SUM_CYCLES (NACC)

0x41 APULSEW 0

Wh pulse (WPULSE) generator input to be updated by the MPU

when using external pulse generation. The output pulse rate is:

APULSEW * FS * 2-32 * WRATE * X * 2-14.

This input is buffered and can be updated by the MPU during a

conversion interval. The change will take effect at the beginning

of the next interval.

0x38 PULSEWIDTH 12

maximum pulse width is (2*PULSEWIDTH+1)*(1/FS). The default

value will generate pulses of 10 ms width at FS = 2520.62 Hz.

0x42

APULSER

VARh (RPULSE) pulse generator input.

0x43

APULSEX

Pulse generator input for XPULSE output.

0x44

APULSEY

Pulse generator input for YPULSE output.

0x45

WSUM_ACCUM

Roll-over accumulator for WPULSE. A pulse is generated when

this register reaches 2

0x46

VSUM_ACCUM

Roll-over accumulator for RPULSE. A pulse is generated when

this register reaches 2

0x47

SUM2_ACCUM

Roll-over accumulator for the XPULSE pulse output.

0x48

SUM3_ACCUM

Roll-over accumulator for the YPULSE pulse output.

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

104 Rev 2

5.3.11 Noise Suppression and Version Parameters

Table 65 shows the CE parameters used for suppression of noise due to scaling and truncation effects.

Table 65: CE Parameters for Noise Suppression and Code Version

Address

Name Default Description

0x26

QUANTA

These parameters are added in channel A to the Watt calculation

to compensate for input noise and truncation.

LSB = (VMAX*IMAX / In_8) *1.04173*10-9 W

0x27

QUANTB

0x28

QUANTC

0x2A

QUANT_VARA

These parameters are added to the VAR calculation for element

A and B to compensate for input noise and truncation.

LSB = (VMAX*IMAX / In_8) * 1.04173*10-9 W

0x2B

QUANT_VARB

0x2C

QUANT_VARC

0x2E QUANT_IA 0

These parameters are added to compensate for input noise and

truncation in their respective channels in the squaring calculations

for I2 and V2.

LSB=VMAX2*5.08656*10-13 V2 and

LSB= (IMAX2/In_82)* 5.08656*10-13 A2

0x2F QUANT_IB 0

0x30 QUANT_IC 0

0x35 0x63653333

Text strings holding the CE version information as supplied by

the CE data associated with the CE code. For example, the

words 0x63653333 and 0x61303463 form the text string

“ce33a04c”.

These locations are overwritten in operation.

0x36 0x61303463

0x37 0x00000000

5.3.12 CE Calibration Parameters

Table 66 lists the parameters that are typically entered to effect calibration of meter accuracy.

Table 66: CE Calibration Parameters

Address

Name Default Description

0x10

CAL_IA

16384

These constants control the gain of their respective channels. The

nominal value for each parameter is 214 = 16384. The gain of each

channel is directly proportional to its CAL parameter. Thus, if the

gain of a channel is 1% slow, CAL should be increased by 1%.

CAL_ID is used to calibrate the neutral current input.

0x11

CAL_VA

16384

0x12

CAL_IB

16384

0x13

CAL_VB

16384

0x14

CAL_IC

16384

0x15

CAL_VC

16384

0x16

CAL_ID

16384

0x18 PHADJ_A 0

These constants control the CT phase compensation. No com-

pensation occurs when PHADJ_X = 0. As PHADJ_X is increased,

more compensation (lag) is introduced. The range is ± 215 – 1. If it

is desired to delay the current by the angle Φ, the equations are:

Φ⋅−

Φ⋅

=TAN

TAN

XPHADJ 0131.01487.0

02229.0

at 60Hz

Φ⋅−

Φ⋅

=TAN

TAN

XPHADJ 009695.01241.0

0155.0

2_ 20

at 50Hz

0x19 PHADJ_B 0

0x1A PHADJ_C 0

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 105

5.3.13 CE Flow Diagrams

Figure 45 through Figure 47 show the data flow through the CE in simplified form. Functions not shown

include delay compensation, sample interpolation, scaling and the processing of meter equations.

Figure 45: CE Data Flow: Multiplexer and ADC

Figure 46: CE Data Flow: Scaling, Gain Control, Intermediate Variables

FCLK= 4.9152MHz

VREFmultiplexer

FS= 2184 Hz

Per channel

ΔΣ

mod FIR

de-multiplexer

FS= 2184 Hz

Per channel

IA_RAW

IB_RAW

VA_RAW

VB_RAW

IC_RAW

VC_RAW

ID ID_RAW

IA_RAW

VA_RAW

OFFSET

NULL PHASE

COMP

GAIN_ADJ

CAL_IA

x x x

LPF

PHADJ_A

OFFSET

NULL

x x

LPF

CAL_VA

90°

VAR0

Generator

...other phases

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

106 Rev 2

Figure 47: CE Data Flow: Squaring and Summation Stages

SQUARE

VARA

VARB

IASQ

VASQ

IBSQ

SUM IASQSUM_X

VASQSUM_X

ICSQSUM_X

SUM WASUM_X

WBSUM_X

VARASUM_X

VARBSUM_X

SUM_CYCLES=60 &

PRE_SAMPS = 42

MPU

PRE_SAMPS

VARC

WCSUM_X

VARCSUM_X

ICSQ

VBSQ

VCSQ

IBSQSUM_X

VBSQSUM_X

VCSQSUM_X

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 107

6 Electrical Specifications

6.1 Absolute Maximum Ratings

Table 67 shows the absolute maximum ranges for the device. Stresses beyond Absolute Maximum Ratings

may cause permanent damage to the device. These are stress ratings only and functional operation at these

or any other conditions beyond those indicated under recommended operating conditions (Section 6.3) is

not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device

reliability. All voltages are with respect to GNDA.

Table 67: Absolute Maximum Ratings

Voltage and Current

Supplies and Ground Pins

V3P3SYS, V3P3A

−

0.5 V to 4.6 V

VBAT

-0.5 V to 4.6 V

GNDD

-0.5 V to +0.5 V

Analog Output Pins

V3P3D

-10 mA to 10 mA,

-0.5 V to 4.6 V

VREF

-10 mA to +10 mA,

-0.5 V to V3P3A+0.5 V

V2P5 -10 mA to +10 mA,

-0.5 V to 3.0 V

Analog Input Pins

IA, VA, IB, VB, IC, VC, V1

-10 mA to +10 mA

-0.5 V to V3P3A+0.5 V

XIN, XOUT

-10 mA to +10 mA

-0.5 V to 3.0 V

All Other Pins

Configured as SEG or COM drivers -1 mA to +1 mA,

-0.5 to V3P3D+0.5

Configured as Digital Inputs -10 mA to +10 mA,

-0.5 to 6 V

Configured as Digital Outputs

-15 mA to +15 mA,

-0.5 V to V3P3D+0.5 V

All other pins −

0.5 V to V3P3D+0.5 V

Temperature and ESD Stress

Operating junction temperature (peak, 100ms)

140 °C

Operating junction temperature (continuous)

125 °C

Storage temperature

−45 °C to +165 °C

Solder temperature – 10 second duration

250 °C

ESD stress on all pins

4 kV

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

108 Rev 2

6.2 Recommended External Components

Table 68: Recommended External Components

Name

From

Function

Value

Unit

V3P3A

AGND

Bypass capacitor for 3.3 V supply

≥

0.1

20% †

V3P3D

GNDD

Bypass capacitor for 3.3 V output

0.1

20% †

CSYS

V3P3SYS

GNDD

Bypass capacitor for V3P3SYS

≥

1.0

30%

C2P5

V2P5

GNDD

Bypass capacitor for V2P5

0.1

20%

XTAL XIN XOUT

32.768 kHz crystal – electrically similar to

ECS .327-12.5-17X or Vishay XT26T,

load capacitance 12.5 pF

32.768 kHz

CXS XIN AGND

Load capacitor for crystal (depends on

crystal specs and board parasitics).

33 ±10% pF

CXL XOUT AGND

Load capacitor for crystal (depends on

crystal specs and board parasitics).

7 ±10% †† pF

Notes:

1. AGND and GNDD should be connected together.

2. V3P3SYS and V3P3A should be connected together.

† For accuracy and EMI rejection, C1 + C2 should be 470 µF or higher.

†† 10, 12, or 15 pF may be used if 7 pF is not available, with limited range for RTCA_ADJ.

6.3 Recommended Operating Conditions

Table 69: Recommended Operating Conditions

Parameter

Condition

Min

Typ

Max

Unit

V3P3SYS, V3P3A: 3.3 V Supply Voltage

V3P3A and V3P3SYS must be at the

same voltage

Normal Operation

3.0

3.3

3.6

Battery Backup

3.6

VBAT

No Battery

Externally Connect to V3P3SYS

Battery Backup:

BRN and LCD modes

SLEEP mode

3.0

2.0

3.8

Operating Temperature

-40

+85

ºC

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 109

6.4 Performance Specifications

6.4.1 Input Logic Levels

Table 70: Input Logic Levels

Parameter

Condition

Min

Typ

Max

Unit

Digital high-level input voltage †, VIH

Digital low-level input voltage †, VIL

0.8

Input pull-up current, I

E_RXTX, E_ISYNC

E_RST, CKTEST

Other digital inputs

VIN=0 V, ICE_E=1

-1

100

µA

Input pull down current, I

ICE_E

RESET

Other digital inputs

VIN = V3P3D

-1

100

µA

† In battery powered modes, digital inputs should be below 0.3 V or above 2.5 V to minimize battery current.

6.4.2 Output Logic Levels

Table 71: Output Logic Levels

Parameter

Condition

Min

Typ

Max

Unit

Digital high-level output voltage VOH

ILOAD = 1 mA

V3P3D–0.4

ILOAD = 15 mA

V3P3D-0.6

Digital low-level output voltage VOL

ILOAD = 1 mA

0.4

ILOAD = 15 mA

0.8

OPT_TX VOH (V3P3D-OPT_TX)

ISOURCE=1 mA

0.4

OPT_TX VOL

ISINK=20 mA

0.7

6.4.3 Power-Fault Comparator

Table 72: Power-fault Comparator Performance Specifications

Parameter

Condition

Min

Typ

Max

Unit

Offset Voltage: V1-VBIAS

-20

+15

Hysteresis Current: V1

Vin = VBIAS – 100 mV

0.8

1.2

μA

Response Time: V1

+100 mV overdrive

100

μs

WDT Disable Threshold: V1-V3P3A

-400

-10

6.4.4 V2 Comparator (71M6534 only)

Table 73: V2 Comparator Performance Specifications

Parameter

Condition

Min

Typ

Max

Unit

Offset Voltage: V2-VBIAS

-20

+15

Hysteresis Current

Vin = VBIAS – 100 mV

0.8

1.2

μA

Response Time

+100 mV overdrive

μs

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

110 Rev 2

6.4.5 Battery Monitor

The LSB values do not include the 8-bit left shift at CE input.

Table 74: Battery Monitor Performance Specifications (BME = 1)

Parameter

Condition

Min

Typ

Max

Unit

Load Resistor

kΩ

LSB Value

[M40MHZ, M26MHZ]

= [00], [10], or [11]

FIR_LEN=0 (L=138)

FIR_LEN=1 (L=288)

FIR_LEN=2 (L=384)

(-10%)

-48.7

-5.35

-2.26

(+10%)

μV

[M40MHZ, M26MHZ]

= [01]

FIR_LEN=0 (L=186)

FIR_LEN=1 (L=384)

FIR_LEN=2 (L=588)

(-10%)

-19.8

-2.26

-0.63

(+10%)

μV

Offset Error

-200

+100

6.4.6 Supply Current

Table 75: Supply Current Performance Specifications

Parameter

Condition

Min

Typ

Max

Unit

V3P3SYS current (CE off)

Normal Operation,

V3P3A = V3P3SYS = 3.3 V

CKMPU = 614 kHz

No Flash Memory write

RTM_E=0, ECK_DIS=1,

ADC_E=1, ICE_E=0

4.2

5.3

V3P3SYS current (CE on)

8.4

9.6

V3P3A current

3.5

3.8

VBAT current

-400

+400

V3P3SYS current,

Write Flash

Normal Operation as above,

except write Flash at maximum

rate,

CE_E

= 0,

ADC_ E

= 0

10 12 mA

VBAT current

VBAT=3.6V

BROWNOUT mode

71M6533/6533H

71M6534H

LCD Mode

LCD DAC off

LCD DAC on

SLEEP Mode

112

0.7

250

1.5

µA

6.4.7 V3P3D Switch

Table 76: V3P3D Switch Performance Specifications

Parameter

Condition

Min

Typ

Max

Unit

On resistance – V3P3SYS to V3P3D

| IV3P3D | ≤ 1 mA

On resistance – VBAT to V3P3D

| IV3P3D | ≤ 1 mA

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 111

6.4.8 2.5 V Voltage Regulator

Unless otherwise specified, the load = 5 mA.

Table 77: 2.5 V Voltage Regulator Performance Specifications

Parameter

Condition

Min

Typ

Max

Unit

V2P5

Iload = 0

2.3

2.5

2.7

V2P5 load regulation

Iload = 0 mA to 5 mA

Voltage overhead V3P3SYS-V2P5

Iload = 5 mA, reduce V3P3

until V2P5 drops 200 mV

460 mV

PSSR ∆V2P5/∆V3P3

RESET=0, iload=0

-2

mV/V

6.4.9 Low-Power Voltage Regulator

Unless otherwise specified, V3P3SYS = V3P3A = 0, PB=GND (BROWNOUT).

Table 78: Low-Power Voltage Regulator Performance Specifications

Parameter

Condition

Min

Typ

Max

Unit

V2P5

LOAD

2.3

2.5

2.7

V2P5 load regulation

ILOAD = 0 mA to 1 mA

VBAT voltage requirement ILOAD = 1 mA, reduce VBAT

until REG_LP_OK = 0

3.0 V

PSRR ΔV2P5/ΔVBAT

LOAD

= 0

-50

mV/V

6.4.10 Crystal Oscillator

Table 79: Crystal Oscillator Performance Specifications

Parameter

Condition

Min

Typ

Max

Unit

Maximum Output Power to Crystal 1

Crystal connected

μW

XIN to XOUT Capacitance 2

Capacitance to GNDD 2

XIN

XOUT

RTCA_ADJ = 0

1 This specification defines a nominal relationship rather than a measured parameter. Correct circuit

operation will be verified with other specs that use this nominal relationship as a reference.

2 This specification will be guaranteed and verified in production samples, but will not be measured in

production.

6.4.11 Optical Interface

Table 80: Optical Interface Performance Specifications

Parameter Condition Min Typ Max Unit

OPT_TX VOH (V3P3D-OPT_TX)

ISOURCE =1 mA

0.4

OPT_TX V

SINK

= 20 mA

0.7

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

112 Rev 2

6.4.12 LCD DAC

Table 81: LCD DAC Performance Specifications

Parameter Condition Min Typ Max Unit

VLCD Voltage

VDACLCDPVVLCD 019.0)_059.01(33 −⋅−⋅=

1 ≤ LCD_DAC ≤ 7 -10 +10 %

6.4.13 LCD Drivers

The information in Table 82 applies to all COM and SEG pins with LCD_DAC[2:0] = 000.

Table 82: LCD Driver Performance Specifications

Parameter

Condition

Min

Typ

Max

Unit

VLC2 Voltage

With respect to VLCD †

-0.1

+0.1

VLC1 Voltage††,

⅓ bias

½ bias

½ bias, minimum output level

With respect to 2*VLC2/3

With respect to VLC2/2

-3

1.0

% VLC2

VLC0 Voltage††,

⅓ bias

With respect to VLC2/3

-4

VLC1 Impedance

∆ILOAD = 100 µA (Isink)

kΩ

∆I

LOAD

-100

(Isource)

VLC0 Impedance

∆ILOAD = 100 µA (Isink)

kΩ

∆I

LOAD

-100

(Isource)

† VLCD is V3P3SYS in MISSION mode and VBAT in BROWNOUT and LCD modes.

†† Specified as percentage of VLC2, the maximum LCD voltage.

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 113

6.4.14 Temperature Sensor

Table 83 shows the performance for the temperature sensor. The LSB values do not include the 8-bit left

shift at CE input.

Table 83: Temperature Sensor Performance Specifications

Parameter

Condition

Min

Typ

Max

Unit

Nominal relationship: N(T) = Sn*(T-Tn) + Nn, Tn = 25ºC

Nominal

Sensitivity (Sn)2

00109.0 











⋅−= L

[M40MHZ, M26MH] =

[00], [10], or [11]

FIR_LEN=0 (L=138)

FIR_LEN=1 (L=288)

FIR_LEN=2 (L=384)

-106

-964

-2286

LSB/ºC

[M40MHZ, M26MHZ] =

[01]

FIR_LEN=0 (L=186)

FIR_LEN=1 (L=384)

FIR_LEN=2 (L=588)

-260

-2286

-8207

Nominal Offset

(Nn) 2

508.0 











⋅= L

[M40MHZ, M26MHZ] =

[00], [10], or [11]

FIR_LEN=0 (L=138)

FIR_LEN=1 (L=288)

FIR_LEN=2 (L=384)

49447

449446

1065353

LSB

[M40MHZ, M26MHZ] =

[01]

FIR_LEN=0 (L=186)

FIR_LEN=1 (L=384)

FIR_LEN=2 (L=588)

121071

1065353

3825004

Temperature Error †











−

−=

NTN

TERR ))((

Tn = 25°C,

T = -40ºC to +85ºC -101 +101 ºC

† Temperature error is calculated with the value Nn, which is measured at Tn during meter calibration and

stored in MPU or CE for use in temperature calculations.

1 Guaranteed by design; not production tested.

2 This specification defines a nominal relationship rather than a measured parameter. Correct circuit

operation will be verified with other specs that use this nominal relationship as a reference.

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

114 Rev 2

6.4.15 VREF and VBIAS

Table 84 shows the performance specifications for VREF and VBIAS. Unless otherwise specified,

VREF_DIS = 0.

Table 84: VREF Performance Specifications

Parameter

Condition

Min

Typ

Max

Unit

VREF output voltage, VREF(22)

Ta = 22ºC

1.193

1.195

1.197

VREF chop step

VREF power supply sensitivity

ΔVREF / ΔV3P3A

V3P3A = 3.0 to 3.6 V -1.5 1.5 mV/V

VREF input impedance

VREF_DIS = 1,

VREF = 1.3 to 1.7 V

100 kΩ

VREF output impedance CAL =1,

ILOAD = 10 µA, -10 µA

2.5 kΩ

VNOM definition 3

626

102)22(101)22()22()(

−−

⋅−+⋅−+= TCTTCTVREFTVNOM

If TRIMBGA and TRIMBGB are available (71M6533G/H, 71M6534H)

Definitions

γ = 0.1·TRIMBGB - 0.143·(TRIMM+0.5),

900

370000500

−⋅−

=TRIMBGATEMP

η = (56.2 – TRIMT)·0.55

VNOM temperature coefficients

TC1

TC2

η+ 19γ - 0.065γξ +0.34ξ + 8.0

0.015γ - 0.0013ξ – 0.35

µV/ºC

µV/ºC 2

VREF(T) deviation from

VNOM(T)

)40,22max(

)(

)()(

−

TTVNOM

TVNOMTVREF

-15 1 +15 1 PPM/ºC

If TRIMBGA and TRIMBGB are not available (71M6533, 71M6534)

VNOM temperature coefficients:

TC1

TC2

3.18·(52.46-TRIMT)

-0.444

µV/ºC

µV/°C

VREF(T) deviation from VNOM(T)

)40,22max(

)(

)()(

−

TTVNOM

TVNOMTVREF

-40 1 +40 1 PPM/ºC

VREF aging

±25

PPM/

year

VBIAS Voltage

Ta = 25 °C

Ta = -40 °C to 85 °C

(-1%)

(-4%)

1.6

(+1%)

(+4%)

1 Guaranteed by design; not production tested.

2 This specification will be guaranteed and verified in production samples, but will be measured in

production only at DC.

3 This relationship describes the nominal behavior of VREF at different temperatures.

4 TEMP22 is the value read from the temperature sensor at 22°C.

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 115

6.4.16 ADC Converter, V3P3A Referenced

Table 85 shows the performance specifications for the ADC converter, V3P3A referenced. For this data,

FIR_LEN=2, [M40MHZ, M26MHZ]=[00], unless stated otherwise, VREF_DIS=0. LSB values do not include

the 8-bit left shift at the CE input.

Table 85: ADC Converter Performance Specifications

Parameter Condition Min Typ Max Unit

Recommended Input Range

(Vin-V3P3A)

-250

250

peak

Voltage to Current Crosstalk

)cos(

*10

VcrosstalkVin

Vin

Vcrosstalk ∠−∠

Vin = 200 mV peak,

65 Hz, on VA.

Vcrosstalk = largest

measurement on IA or IB

-10 1 10 1 μV/V

THD (First 10 harmonics): 1

250 mV-pk

20 mV-pk

Vin=65 Hz,

64 kpts FFT, Blackman-

Harris window

-75

-90

Input Impedance

At 65 Hz

kΩ

Temperature coefficient of Input

Impedance

At 65 Hz 1.7 Ω/°C

LSB size

75.4

25.1 











⋅⋅= L

VV REFLSB

L = FIR length

[M40MHZ,

M26MHZ] =

[00], [10], or [11]

FIR_LEN=0

FIR_LEN=1

FIR_LEN=2

3231

355

150

nV/LSB

[M40MHZ,

M26MHZ] =

[01]

FIR_LEN=0

FIR_LEN=1

FIR_LEN=2

1319

150

nV/LSB

Digital Full Scale

3









L

L = FIR length

[M40MHZ,

M26MHZ] =

[00], [10], or [11]

FIR_LEN=0

FIR_LEN=1

FIR_LEN=2

± 97336

± 884736

± 2097152

LSB

[M40MHZ,

M26MHZ] =

[01]

FIR_LEN=0

FIR_LEN=1

FIR_LEN

± 238328

± 2097152

± 7529536

LSB

DC Gain Error vs

%Power Supply Variation

3.3/33100

/35710

APV

VnVNout

INPK

∆

Vin=200 mV pk, 65 Hz

V3P3A=3.0 V, 3.6 V 50 PPM /

Input Offset (Vin-V3P3A)

-10

1 Guaranteed by design; not production tested.

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

116 Rev 2

6.5 Timing Specifications

6.5.1 Flash Memory

Table 86: Flash Memory Timing Specifications

Parameter Condition Min Typ Max Unit

Flash Read Pulse Width

V3P3A = V3P3SYS = 0

(BROWNOUT Mode)

100

Flash write cycles

-40°C to +85°C

20,000

Cycles

Flash data retention

25°C

100

Years

Flash data retention

85°C

Years

Flash byte writes between page or

mass erase operations

2 Cycles

Write Time per Byte

µs

Page Erase (1024 bytes)

Mass Erase

200

6.5.2 EEPROM Interface

Table 87: EEPROM Interface Timing

Parameter

Condition

Min

Typ

Max

Unit

Write Clock frequency (I2C)

CKMPU = 4.9 MHz,

Using interrupts

78 kHz

CKMPU = 4.9 MHz,

bit-banging DIO4/5

150 kHz

Write Clock frequency (3-wire)

CKMPU=4.9 MHz

500

kHz

6.5.3 RESET

Table 88: RESET Timing

Parameter Condition Min Typ Max Unit

Reset pulse width

µs

Reset pulse fall time

1 1

µs

1 Guaranteed by design; not production tested.

6.5.4 RTC

Table 89: RTC Range for Date

Parameter

Condition

Min

Typ

Max

Unit

Range for date

2000

2255

year

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 117

6.5.5 SPI Slave Port (MISSION Mode)

Table 90: SPI Slave Port (MISSION Mode) Timing

Parameter

Condition

Min

Typ

Max

Unit

tSPIcyc PCLK cycle time

µs

tSPILead Enable lead time

tSPILag Enable lag time

tSPIW PCLK pulse width:

High

Low

tSPISCK PCSZ to first PCLK fall

Ignore if PCLK is low

when PCSZ falls.

2 ns

tSPIDIS Disable time

tSPIEV PCLK to Data Out

tSPISU Data input setup time

tSPIH Data input hold time

MSB OUT LSB OUT

MSB IN LSB IN

SPIcyc

SPILead

SPILag

SPISCK

SPIH

SPIW

SPIEV

SPIW

SPIDIS

PCSZ

PCLK

PSDI

PSDO

Figure 48: SPI Slave Port (MISSION Mode) Timing

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

118 Rev 2

6.6 Typical Performance Data

6.6.1 Accuracy over Current

Figure 49 shows meter accuracy over current for various line frequencies. Figure 50 shows meter accuracy

over current at various load angles.

Figure 49: Wh Accuracy (0.1 A - 200 A, 240 V, Room Temperature) at Various Frequencies

(Differential Mode, CTs)

Figure 50: Typical Wh Accuracy (0.02 A - 200 A, 240 V, Room Temperature), Various Load Angles

(Differential Mode, CTs)

-0.5

-0.4

-0.3

-0.2

-0.1

0.1

0.2

0.3

0.4

0.5

0.1 110 100 1000

% Error

Current (A rms)

6533/34 Wh Performance, Equation 5, 45 Hz, 55 Hz, 65 Hz -240 V - 0° Phase

Angle

45 Hz

55 Hz

65 Hz

-1

-0.8

-0.6

-0.4

-0.2

0.2

0.4

0.6

0.8

0.01 0.1 110 100

Error (%)

I [A]

71M6533/6534 Wh Accuracy at Various Phase Angles

Equation 5, 240 V

0°

60°

300°

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 119

6.6.2 Accuracy over Temperature

With digital temperature compensation enabled, the temperature characteristics of the reference voltage

(VREF) are compensated to within ±40 PPM/°C for the 71M6533/71M6534 and within ±15 PPM/°C for the

71M6533H/71M6534H.

6.7 Package Outline Drawings

6.7.1 71M6533 (100-Pin LQFP)

Controlling dimensions are in mm.

Figure 51: 71M6533/71M6533G/71M6533H 100-Pin LQFP Package Outline

15.7(0.618)

16.3(0.641)

15.7(0.618)

16.3(0.641)

Top View

MAX. 1.600

0.50 TYP.

14.000 +/- 0.200

0.225 +/- 0.045

0.60 TYP>

1.50 +/- 0.10

0.10 +/- 0.10

Side View

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

120 Rev 2

6.7.2 71M6534/6534H (120-Pin LQFP)

Controlling dimensions are in mm.

MAX. 1.600

0.400

13.950 +/- 0.100

0.180 +/- 0.050

0.600 +/- 0.150

1.400 +/- 0.050

0.100 +/- 0.050

16.000 +/- 0.200

120

16.000 +/- 0.200

7.000

14.000 +/- 0.100

8.000

8.000 7.000

Figure 52: 71M6534/6534H 120-Pin LQFP Package Outline

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 121

6.8 Pinout

6.8.1 71M6533/71M6533G/71M6533H Pinout (100-Pin LQFP)

Figure 53: Pinout for 71M6533/71M6533G/71M6533H LQFP-100 Package

TERIDIAN

71M6533

71M6533G

71M6533H

10026

SEG38/DIO18/MTX

SEG9/E_RXTX

GNDD

TMUXOUT

SEG37/DIO17

SEG3/PCLK

V3P3D

SEG19/CKTEST

SEG4/PSDO

SEG5/PCSZ

DIO2/OPT_TX

V3P3SYS

DIO3

COM1

COM2

COM3

COM0

DIO57

DIO58

DIO56

GNDD

SEG14

SEG13

SEG12

SEG7/MUX_SYNC

SEG8

SEG50/DIO30

SEG6/PSDI

SEG36/DIO16

SEG49/DIO29

SEG2/TEST2

SEG1/TEST1

SEG15

SEG0/TEST0

SEG65/DIO45

SEG44/DIO24

SEG45/DIO25

SEG47/DIO27

SEG46/DIO26

SEG33/DIO13

SEG63/DIO43

SEG64/DIO44

SEG16

SEG27/DIO7/RPULSE

SEG39/DIO19

SEG26/DIO6/WPULSE

SEG25/DIO5/SDATA

SEG29/DIO9/YPULSE

SEG31/DIO11

GNDD

RESET

V2P5

VBAT

SEG24/DIO4/SDCK

SEG23

SEG22

SEG28/DIO8/XPULSE

SEG41/DIO21

SEG40/DIO20

ICE_E

SEG18

SEG17

SEG30/DIO10

SEG20

SEG21

SEG43/DIO23

V3P3A

GNDA

XOUT

TEST

XIN

DIO1/OPT_RX

ICN

VREF

IAP

IBN

ICP

GNDD

SEG11/E_RST

SEG10/E_TCLK

SEG61/DIO41

IAN

IBP

IDP

SEG35/DIO15

SEG34/DIO14

SEG67/DIO47

SEG68/DIO48

SEG69/DIO49

SEG70/DIO50

SEG71/DIO51

IDN

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

122 Rev 2

6.8.2 71M6534/71M6534H Pinout (120-Pin LQFP)

Figure 54: Pinout for 71M6534/71M6534H LQFP-120 Package

Teridian

71M6534/

71M6534H

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

SEG38/DIO18/MTX

SEG16

SEG27/DIO7/RPULSE

SEG39/DIO19

SEG26/DIO6/WPULSE

SEG25/DIO5/SDATA

SEG29/DIO9/YPULSE

SEG31/DIO11

GNDD

RESET

V2P5

VBAT

SEG24/DIO4/SDCK

SEG23

SEG22

SEG28/DIO8/XPULSE

SEG41/DIO21

SEG40/DIO20

ICE_E

SEG43/DIO23

SEG18

SEG17

SEG30/DIO10

SEG20

SEG21

GNDD

SEG14

SEG13

SEG12

SEG11/E_RST

SEG10/E_TCLK

SEG9/E_RXTX

SEG7/MUX_SYNC

SEG8

SEG50/DIO30

SEG6/PSDI

SEG36/DIO16

SEG49/DIO29

SEG35/DIO15

SEG34/DIO14

SEG48/DIO28

SEG2/TEST2

SEG1/TEST1

SEG15

SEG0/TEST0

SEG56/DIO36

SEG57/DIO37

SEG58/DIO38

SEG59/DIO39

SEG71/DIO51

SEG72/DIO52

SEG73/DIO53

SEG74/DIO54

SEG75/DIO55

GNDD

TMUXOUT

SEG37/DIO17

SEG3/PCLK

V3P3D

SEG19/CKTEST

SEG4/PSDO

SEG5/PCSZ

SEG65/DIO45

DIO2/OPT_TX

V3P3SYS

DIO3

COM1

COM2

COM3

COM0

DIO57

DIO58

SEG66/DIO46

SEG67/DIO47

SEG68/DIO48

SEG69/DIO49

SEG70/DIO50

SEG32/DIO12

XOUT

TEST

XIN

GNDD

DIO1/OPT_RX

VREF

IAP

IBP

ICP

ICN

VBIAS

V3P3A

GNDA

SEG62/DIO42

SEG61/DIO41

SEG42/DIO22/MRX

SEG54/E_TBUS3

SEG53/E_TBUS2

SEG52/E_TBUS1

SEG51/E_TBUS0

SEG44/DIO24

SEG45/DIO25

SEG47/DIO27

SEG46/DIO26

DIO56

SEG55/E_ISYNC

SEG33/DIO13

SEG63/DIO43

SEG64/DIO44

IDP

IDN

IBN

IAN

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 123

6.9 Pin Descriptions

Pins marked with an asterisk (e.g. V2*) are only available on the 71M6534.

6.9.1 Power and Ground Pins

Table 91: Power and Ground Pins

Name

Type

Circuit

Description

GNDA

–

Analog ground: This pin should be connected directly to the ground plane.

GNDD

–

Digital ground: This pin should be connected directly to the ground plane.

V3P3A P –

Analog power supply: A 3.3 V power supply should be connected to this

pin, must be the same voltage as V3P3SYS.

V3P3SYS

–

System 3.3 V supply. This pin should be connected to a 3.3 V power supply.

V3P3D O 13

Auxiliary voltage output of the chip. In mission mode, this pin is con-

nected to V3P3SYS by the internal selection switch. In BROWNOUT

mode, it is internally connected to VBAT. V3P3D is floating in LCD and

SLEEP mode. A bypass capacitor to ground should not exceed 0.1 µF.

VBAT P 12

Battery backup and oscillator power supply. A battery or super-capacitor

is to be connected between VBAT and GNDD. If no battery is used,

connect VBAT to V3P3SYS.

V2P5 O 10

Output of the internal 2.5 V regulator. A 0.1 µF capacitor to GNDA

should be connected to this pin.

6.9.2 Analog Pins

Table 92: Analog Pins

Name

Type

Circuit

Description

IAP/IAN,

IBP/IBN,

ICP/ICN

IDP/IDN

I 6

Differential or single-ended Line Current Sense Inputs: These pins are voltage

inputs to the internal A/D converter. Typically, they are connected to the

outputs of current sensors. Unused pins must be tied to V3P3A.

VA, VB,

VC I 6

Line Voltage Sense Inputs: These pins are voltage inputs to the internal

A/D converter. Typically, they are connected to the outputs of resistor

dividers. Unused pins must be tied to V3P3A.

V1 I 7

Comparator Input: This pin is a voltage input to the internal comparator.

The voltage applied to the pin is compared to the internal BIAS voltage

(1.6 V). If the input voltage is above VBIAS, the comparator output will be

high (1). If the comparator output is low, a voltage fault will occur. A series

5 kΩ resistor should be connected from V1 to the resistor divider.

V2* I 7

Comparator Input (71M6534 only): This pin is a voltage input to an internal

comparator. The voltage applied to this pin is compared to an internal

reference voltage (VBIAS). If the input voltage is above VBIAS, the

comparator output will be high (1).

VBIAS*

Low-impedance output for use in biasing current sensors and voltage dividers.

VREF O 9

Voltage Reference for the ADC. This pin should be left unconnected

(floating).

XIN

XOUT I 8

Crystal Inputs: A 32 kHz crystal should be connected across these pins.

Typically, a 33 pF capacitor is also connected from XIN to GNDA and a

7 pF capacitor (alternatively, 10 pF to 15 pF) is connected from XOUT

to GNDA. It is important to minimize the capacitance between these pins.

See the crystal manufacturer datasheet for details.

If an external clock is used, a 150 mV (p-p) clock signal should be applied

to XIN, and XOUT should be left unconnected.

Pin types: P = Power, O = Output, I = Input, I/O = Input/Output

The circuit number denotes the equivalent circuit, as specified under Section 6.9.4 I/O Equivalent Circuits.

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

124 Rev 2

6.9.3 Digital Pins

Table 93: Digital Pins

Name

Type

Circuit

Description

COM3,COM2,

COM1,COM0

O 5

LCD Common Outputs: These 4 pins provide the select signals for

the LCD display.

SEG0…SEG2,

SEG8,

SEG12…SEG18,

SEG20…SEG23

O 5 Dedicated LCD Segment Output pins.

SEG24/DIO4

…

SEG31/DIO11,

SEG32/DIO12*

SEG33/DIO13

…

SEG41/DIO21,

SEG42/DIO22*

SEG43/DIO23

…

SEG47/DIO27,

SEG48/DIO28*

SEG49/DIO29,

SEG50/DIO30,

SEG56/DIO36*

…

SEG59/DIO39*

SEG61/DIO41,

SEG62/DIO42*

SEG63/DIO43

…

SEG65/DIO45,

SEG66/DIO45*

SEG67/DIO47

…

SEG71/DIO51

SEG72/DIO52*

…

SEG75/DIO55*

I/O 3, 4, 5

Multi-use pins, configurable as either LCD SEG driver or DIO.

(DIO4 = SCK, DIO5 = SDA when configured as EEPROM interface;

WPULSE = DIO6, VARPULSE = DIO7, DIO8 = XPULSE,

DIO9 = YPULSE when configured as pulse outputs).

Unused pins must be configured as outputs or terminated to

V3P3/GNDD.

SEG32/DIO12, SEG42/DIO22, SEG48/DIO28, SEG56/DIO36

through SEG59/DIO39, SEG62/DIO42, SEG66/DIO45,

SEG72/DIO52 through SEG75/DIO55 are only available in the

71M6534.

SEG38/DIO18 and SEG42/DIO22 can be assigned to the multiplexed

UART outputs/inputs MTX and MRX (71M6534 only). This function

is controlled by the I/O RAM bits UMUX_E and UMUX_SEL.

SEG51/E_TBUS0*

SEG52/E_TBUS1*

SEG53/E_TBUS2*

SEG54/E_TBUS3*

SEG55/E_ISYNC_

BRKRQ*

I/O 5 Multiuse pins, configurable as either LCD SEG driver or emulator

trace bus or handshake (71M6534 only).

SEG3/PCLK

SEG4/PSDO

SEG5/PCSZ

SEG6/PSDI

I/O 3, 4, 5 Multi-use pins, configurable as either LCD SEG driver or SPI

PORT.

DIO3, DIO56,

DIO57, DIO58

I/O 3 Dedicated DIO Pins.

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 125

E_RXTX/SEG9

I/O

1, 4, 5

Multi-use pins, configurable as either emulator port pins (when

ICE_E pulled high) or LCD SEG drivers (when ICE_E tied to GND).

E_RST/SEG11

I/O

1, 4, 5

E_TCLK/SEG10

4, 5

ICE_E I 2

ICE enable. When zero, E_RST, E_TCLK, and E_RXTX become

SEG9, SEG10, and SEG11 respectively. For production units, this

pin should be pulled to GND to disable the emulator port.

CKTEST/SEG19,

MUXSYNC/SEG7 O 4, 5

Multi-use pins, configurable as either multiplexer/clock output or

LCD segment driver using the I/O RAM bits CKOUT_E or

MUX_SYNC_E.

TMUXOUT O 4

Pin connected to the output test multiplexer. Controlled by

TMUX[3:0].

OPT_RX/DIO1 I/O 3, 4

Multi-use pin, configurable as Optical Receive Input or general DIO.

When configured as OPT_RX, this pin is a regular UART RX pin.

If this pin is unused it must be configured as an output or

terminated to V3P3D or GNDD.

OPT_TX/DIO2 I/O 3, 4

Multi-use pin, configurable as either Optical LED Transmit Output

or general DIO. When configured as OPT_TX, this pin is capable

of directly driving an LED for transmitting data in an IR serial interface.

RESET I 2

Chip reset: This input pin is used to reset the chip into a known

state. For normal operation, this pin is pulled low. To reset the

chip, this pin should be pulled high. This pin has an internal 30 μA

(nominal) current source pull-down. No external reset circuitry is

necessary.

RX I 3

UART input. If this pin is unused it must be terminated to

V3P3D or GNDD.

UART output.

TEST I 7

Enables Production Test.

This pin must be grounded in normal operation.

PB I 3

Push button input. This pin must be at GNDD when not active or

unused. A rising edge sets the IE_PB flag. It also causes the part to

wake up if it is in SLEEP or LCD mode. PB does not have an internal

pull-up or pull-down resistor.

Pin types: P = Power, O = Output, I = Input, I/O = Input/Output.

The circuit number denotes the equivalent circuit, as specified in Section 6.9.4.

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

126 Rev 2

6.9.4 I/O Equivalent Circuits

Oscillator Equivalent Circuit

Type 8:

Oscillator I/O

Digital Input Equivalent Circuit

Type 1:

Standard Digital Input or

pin configured as DIO Input

with Internal Pull-Up

GNDD

110K

V3P3D

CMOS

Input

V3P3D

Digital

Input

Digital Input

Type 2:

Pin configured as DIO Input

with Internal Pull-Down

GNDD

110K

GNDD

CMOS

Input

V3P3D

Digital

Input

Digital Input Type 3:

Standard Digital Input or

pin configured as DIO Input

GNDD

CMOS

Input

V3P3D

Digital

Input

CMOS

Output

GNDD

V3P3D

GNDD

V3P3D

Digital Output Equivalent Circuit

Type 4:

Standard Digital Output or

pin configured as DIO Output

Digital

Output

LCD Output Equivalent Circuit

Type 5:

LCD SEG or

pin configured as LCD SEG

LCD

Driver

GNDD

LCD SEG

Output

MUX

GNDA

V3P3A

Analog Input Equivalent Circuit

Type 6:

ADC Input

Analog

Input

Comparator Input Equivalent

Circuit Type 7:

Comparator Input

GNDA

V3P3A

Comparator

Input

Oscillator

GNDD

Oscillator

VREF Equivalent Circuit

Type 9:

VREF

from

internal

reference

GNDA

V3P3A

VREF

V2P5 Equivalent Circuit

Type 10:

V2P5

from

internal

reference

GNDD

V3P3D

V2P5

VLCD Equivalent Circuit

Type 11:

VLCD Power

GNDD

LCD

Drivers

VLCD

VBAT Equivalent Circuit

Type 12:

VBAT Power

GNDD

Power

Down

Circuits

VBAT

V3P3D Equivalent Circuit

Type 13:

V3P3D

from

V3P3SYS

V3P3D

from

VBAT

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 127

7 Ordering Information

PART PIN-

PACKAGE

VREF TRIM

DEVIATION**

FLASH

SIZE

(KB)

PACKAGE ORDERING

NUMBER

PACKAGE

MARKING

71M6533

100 LQFP

(Lead(Pb)-

free)

±40

128

Bulk

71M6533-IGT/F

71M6533-IGT

71M6533H

±15

128

71M6533H-IGT/F

71M6533H-IGT

71M6533G*

±40

256

71M6533G-IGT/F

71M6533G-IGT

71M6533

±40

128

Tape and

reel

71M6533-IGTR/F

71M6533-IGT

71M6533H

±15

128

71M6533H-IGTR/F

71M6533H-IGT

71M6533G*

±40

256

71M6533G-IGTR/F

71M6533G-IGT

71M6534

120 LQFP

(Lead(Pb)-

free)

±40

128

Bulk

71M6534-IGT/F

71M6534-IGT

71M6534H

±15

256

71M6534H-IGT/F

71M6534H-IGT

71M6534

±40

128

Tape and

reel

71M6534-IGTR/F

71M6534-IGT

71M6534H

±15

256

71M6534H-IGTR/F

71M6534H-IGT

*Future product—contact factory for availability.

**VREF trim deviation is the difference between the physical reference voltage and the nominal

reference voltage (VNOM, as calculated from the trim fuses) in ppm/°C. See Section 3.5.1 for details.

8 Related Information

Users must also refer to the following documents related to the 71M6533 and 71M6534:

• 71M6533/G/H and 71M6534/H Data Sheet (this document)

• 71M653X Software User’s Guide (SUG)

9 Contact Information

For more information about Maxim products or to check the availability of the 71M6533/G/H and

71M6534/H, contact technical support at www.maxim-ic.com/support.

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

128 Rev 2

Appendix A: Acronyms

AFE Analog Front End

AMR Automatic Meter Reading

ANSI American National Standards Institute

CE Compute Engine

DIO Digital I /O

DSP Digital Signal Processor

FIR Finite Impulse Response

I2C Inter-IC Bus

ICE In-Circuit Emulator

IEC International Electrotechnical Commission

MPU Microprocessor Unit (CPU)

PLL Phase-locked loop

RMS Root Mean Square

SFR Special Function Register

SOC System on Chip

SPI Serial Peripheral Interface

TOU Time of Use

UART Universal Asynchronous Receiver/Transmitter

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Rev 2 129

Appendix B: Revision History

REVISION

NUMBER

REVISION

DATE

DESCRIPTION

2 2/12 1) Added Guaranteed By Design notes to the Electrical Specifications.

2) Added explanation on NV properties of RTCA_ADJ[ ] and

PREG/QREG[ ] and corrected entries in Table 54.

3) Added note that transitions to BROWNOUT mode must be avoided

during page erase operations.

4) Added note in Application Section (3.1) stating that filter com-

ponents other that those shown on the Demo Boards should not be

connected to the sensor input pins. Added reference to AN5292.

5) Consolidated spelling of low-power modes (SLEEP, LCD,

BROWNOUT) and of COMPSTAT register.

6) Corrected value for C2 capacitor in Table 68.

7) Extended explanation of WD_OVF (not preserved in SLEEP mode)

and corrected entries in Table 54.

8) Added explanation of WD_NROVF_FLAG.

9) Added explanation on MPU activity on transition to BROWNOUT

mode in section 2.4.2.

1.2

August 3, 2010

1) Throughout document: Added bit ranges to all register fields where

missing (e.g. MPU_DIV[2:0]).

2) Figure 1: Corrected name for PSDI and PSDO signals.

3) Section 1.2.3 (page 11): Added note concerning tailoring CE code

for ADC resolution.

4) Section 1.1.1, Table 5 (page 15): Corrected equations for EQU=3.

Added note – not all CE codes support all equations.

5) Clarified Section 1.3.2 (page 16).

6) Section 1.4 80515 MPU Core:

 (page 19) Table 6: Change approximate frequencies to exact

frequencies.

 (page 19): Changed providing Library to providing demonstration

source code.

 (page 20) Added note about MUX_DIV=0 disables ADC output.

 (page 21) See restrictions on INTBITS register.

 (page 22) Added P1-P3 to Table 10.

 (page 24) Updated Data Pointer description.

 (page 25) Table 14: Added note about clearing the WRPROT_CE

and WRPROT_BT bits. Updated description for FWCOL0,

FWCOL1.

 (page 26) Section 1.4.6: Clarified SOBUF, S1BUF as Tx and Rx

buffers.

 (page 27): Added caution on proper way to clear flag bits.

 (page 31) Table 25: Added Interrupt sources for Ext. Interrupts 2-6.

7) Section 1.5.2 PLL and Internal Clocks

 (page 37) Table 37: Changed frequencies to exact frequencies.

 (page 38): Added caution concerning frequency relationship to

specific CE code.

8) (page 39) Section 1.5.3 Real-Time Clock (RTC): Added description

for observing RTC timing on TMUXOUT pin.

9) (page 46) Section 1.5.7 Digital I/O: Added caution about not sourcing

current in or out of DIO pins. Updated Figure 9.

10) Section 1.5.11 SPI Slave Port, (page 52): Clarified description of

I/O RAM access via the SPI interface. Added Table 48.

11) Section 2.3 Battery Modes (page 57): Added details on software

71M6533/G/H and 71M6534/H Data Sheet FDS_6533_6534_004

130 Rev 2

REVISION

NUMBER

REVISION

DATE

DESCRIPTION

precautions for switching between modes and factory programming

of the first 6 flash addresses..

12) Figure 25, Figure 26 and Figure 27: Corrected name for PSDI and

PSDO signals.

13) Section 2.5.2 Wake on Timer (page 66): Updated description.

14) Section 3.1 Connection of Sensors (CT, Resistive Shunt) (page

68): Added note concerning analog input pins requiring sensors

with low source impedance.

15) Section 4.12 MPU Firmware Library (page 77): Modified to indicate

demonstration source code provided.

16) Section 4.13 Crystal Oscillator (page 77): Updated caution about

rejecting electromagnetic interference.

17) Table 53 I/O RAM Map – Functional Order (page 79): Updated format

for Unused and NVRAM locations.

18) Section 5.3.4 Environment (page 96): Added comment concerning

importance of parameter dependence on CE code environment.

19) Section 5.3.7 CE Status and Control: (page 99) Updated description

of EXT_TEMP. Updated Table 58.

20) Section 5.3.8 CE Transfer Variables:

 (page 100) Updated Table 60.

 (page 102) Added VBAT_SUM_X to Table 62.

21) Section 5.3.12: Added CAL_ID location.

22) Section 1.1.1: Updated flow diagrams.

23) Added 71M6533G (256 KB).

24) Updated value for capacitor at XOUT (7 pF).

25) Added description of delay compensation in CE (1.3.6).

26) Added description of error bands for VREF in 3.5.1.

27) Replaced Accuracy with Trim Deviation in Ordering Information.

28) Added explanation on pulse generation to description of registers

WSUM_ACCUM and VSUM_ACCUM.

29) Corrected comment in I/O RAM Table for entry DIO_DIR1[7:5, 3:0] to

state “see DIO_PX and DIO_PY for special options for the DIO8 and

DIO9 outputs”.

30) Added comment in electrical specifications for Battery Monitor

stating that the LSB values do not include the 8-bit left shift at CE

input”.

31) In Section on Real-Time Clock (RTC), corrected maximum value for

RTCA_ADJ to 0x7F and corrected adjustment rage to ±15 ppm.

Added note: “The digital adjustment using PREG[16:0] and

QREG[1:0] is preferred over the analog adjustment using

RTCA_ADJ: The digital adjustment is more repeatable and has a

wider range”

32) Corrected entry for SPE in I/O RAM Table to state “Enables the SPI

Interface on pins SEG3 through SEG6”

33) In I/O RAM Table for entry TRIM[7:0]: Added TRIMT[7:0] to list of

fuses accessible with TRIM[7:0].

34) Corrected entry in I/O RAM Table on IE_XFER and IE_RTC:

Removed text stating that flags are cleared automatically.

35) Added entry in I/O RAM Table for WE: Write data is discarded.

36) Corrected formula for sag threshold in CE section.

37) Completely reworked the description of the SPI port.

FDS_6533_6534_004 71M6533/G/H and 71M6534/H Data Sheet

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit

patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

 2012 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products.

REVISION

NUMBER

REVISION

DATE

DESCRIPTION

1.1

November 9,

2009

Changes and corrections:

1) Stated < 0.1% for accuracy for both H and non-H parts over

2000:1 range on title page.

2) Added STOP and IDLE bits in description of PCOM SFR.

3) Consolidated spelling of RTCA_ADJ.

4) Added explanation for Figure 18.

5) Completely revised section 2.5.2 (Wake on Timer).

6) Improved description of hysteresis in Application Section (3.11).

7) Corrected bit range for CE_LCTN to CE_LCTN[7:0].

8) Corrected bit assignment for control of DIO56 – DIO58 (DIO_56[4]

and DIO_DIR56[7].

9) Added LCD_SEG19[ ] to Table 47.

10) Added text in Table 47 stating that registers RTC_SEC to

RTC_YR do not change at reset.

11) Specified Voltage LSB in CE Interface Description (for sag

detection).

12) Corrected formulae for RMS calculation below Table 56.

13) Updated package outline drawing.

14) Added text describing connection of a trace emulator to the

71M6534 in Section 3.13.

15) Clarified write delay that applies to the RTC_SEC and other RTC

registers in Section 1.4.3 and Table 47.

16) Added note describing firmware measures to be applied when

using UART1 in full-duplex mode.

1.0

March 6, 2009

First publication with changes with respect to the preliminary data

sheet (PDS) as follows:

1) Corrected reversed labels for Timer/Counter 1 and 2 in Table 22.

2) Updated Figure 7 (Interrupt structure).

3) Updated range for RTC_A from 1.9 PPM to 3.8 PPM.

4) Changed SLEEP mode current at 25°C to 0.7 µV and deleted

entry for typical SLEEP mode current over temperature.

5) Corrected bit enumeration for FLSH_PGADR[7:2].

6) Corrected various typographical errors (TRIMMT etc.).

7) Corrected entries under “Wk.” Column for GP0-GP7 in alphabetical

I/O RAM table.

8) Added explanation for hysteresis at the V1 pin in Applications

section.

9) Replaced graph showing system performance specification over

temperature with specification on accuracy of VREF

compensation.

10) Changed accuracy of VREF compensation over temperature to

±15 PPM/°C

11) Changed LSB values provided for temperature sensor.

12) Added minimum output level for VLC1 LCD voltage.

13) Removed access to I/O RAM from SPI Port description.

14) Updated numerous parameters in Electrical Specification

(temperature sensor, supply current for mission and battery

modes).

15) Corrected number of pre-boot cycles in Flash Memory Section.

16) Updated entries in I/O RAM table under “Wake” column.

17) Updated CE register tables.

71M6533/G/H and 71M6534/H Data Sheet

132 Rev 2