ICE2PCS01GXUMA1 - INFINEON TECHNOLOGIES AG

Version 2.3, 09 November 2019

CCM-PFC

ICE2PCS01

ICE2PCS01G

Standalone Power Factor

Correction (PFC) Controller in

Continuous Conduction Mode

(CCM)

P o w e r M a n a g e m e n t & S u p p l y

N e v e r s t o p t h i n k i n g .

CCM-PFC

Revision History:

2019-11-09

Datasheet

Previous Version: V 2.2

Page

Subjects (major changes since last revision)

Typo error, Vcc maximum voltage should be 25V instead of 26V

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CoolMOST™, CoolSET™ are trademarks of Infineon Technologies AG.

Edition 2019-11-09

Published by

Infineon Technologies AG

81726 München, Germany

Legal Disclaimer

The information given in this document shall in no event be regarded as a guarantee of conditions or

characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any

information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties

and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights

of any third party.

Information

For further information on technology, delivery terms and conditions and prices please contact your nearest

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test

ICE2PCS01

PG-DIP-8

ICE2PCS01G

PG-DSO-8

Typical Application

VOUT

Auxiliary Supply

VCC

EMI-Filter

85 ... 265 VAC

SWITCH

ICE2PCS01/

PFC-Controller

ICE2PCS01G

Protection Unit

VSENSE

PWM Logic

Voltage Loop

Driver

Compensation

GATE

FREQ

Variable

Ramp

Oscillator

Generator

VCOMP

ICOMP

Current Loop

Nonlinear

Compensation

Gain

ISENSE

GND

CCM-PFC

ICE2PCS01

ICE2PCS01G

Standalone Power Factor Correction

(PFC) Controller in Continuous

Conduction Mode (CCM)

Product Highlights

•

Leadfree DIP and DSO Package

•

Wide Input Range

•

Optimized for applications which require fast Startup

•

Output Power Controllable by External Sense Resistor

•

Programmable Operating Frequency

•

Output Over-Voltage Protection

•

Fast Output Dynamic Response during Load Jumps

Features

Description

•

Ease of Use with Few External Components

The ICE2PCS01/G is a 8-pin wide input range controller

•

Supports Wide Range

IC for active power factor correction converters. It is de-

•

Average Current Control

signed for converters in boost topology, and requires few

•

External Current and Voltage Loop Compensation external components. Its power supply is recommended

for Greater User Flexibility

to be provided by an external auxiliary supply which will

•

Programmable Operating/Switching Frequency

switch on and off the IC.

(50kHz - 250kHz)

The IC operates in the CCM with average current control,

•

Max Duty Cycle of 95% (at 25°C) at 125kHz

and in DCM only under light load condition. The switching

•

Trimmed Internal Reference Voltage (3V+2% at

frequency is programmable by the resistor at pin 4. Both

25°C)

compensations for the current and voltage loop are exter-

•

VCC Under-Voltage Lockout

nal to allow full user control.

•

Cycle by Cycle Peak Current Limiting

There are various protection features incorporated to en-

•

Output Over-Voltage Protection

sure safe system operation conditions. The internal refer-

•

Open Loop Detection

ence is trimmed (3V+2%) to ensure precise protection and

•

Enhanced Dynamic Response

control level. The device has a fast startup time with con-

•

Short Startup(SoftStart) duration

trolled peak start up current.

•

Fulfills Class D Requirements of IEC 1000-3-2

•

Soft Overcurrent Protection

•

Type

Package

ICE2PCS01

PG-DIP-8

ICE2PCS01G

PG-DSO-8

Version 2.3

09 November 2019

CCM-PFC

ICE2PCS01/G

Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1

Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.2

Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Representative Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.1

General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.2

Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.3

Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

3.4

System Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.4.1

Soft Over Current Control (SOC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.4.2

Peak Current Limit (PCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.4.3

Open Loop Protection / Input Under Voltage Protect (OLP) . . . . . . . . . . . 9

3.4.4

Over-Voltage Protection (OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.5

Frequency Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

3.6

Average Current Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.6.1

Complete Current Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.6.2

Current Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.6.3

Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.6.4

Nonlinear Gain Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3.7

PWM Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.8

Voltage Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.8.1

Voltage Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.8.2

Enhanced Dynamic Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

3.9

Output Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.1

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.2

Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

4.3

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.3.1

Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.3.2

Variable Frequency Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.3.3

PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.3.4

System Protection Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

4.3.5

Current Loop Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.3.6

Voltage Loop Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

4.3.7

Driver Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Version 2.3

09 November 2019

Package PG-DIP-8 / PG-DSO-8

GND

GATE

ICOMP

VCC

ISENSE

VSENSE

FREQ

VCOMP

CCM-PFC

ICE2PCS01/G

Pin Configuration and Functionality

1.1

Pin Configuration

ICOMP (Current Loop Compensation)

Low pass filter and compensation of the current control

loop. The capacitor which is connected at this pin

Function

integrates the output current of OTA2 and averages the

current sense signal.

IC Ground

Current Loop Compensation

ISENSE (Current Sense Input)

Current Sense Input

The ISENSE Pin senses the voltage drop at the

external sense resistor (R1). This is the input signal for

Switching Frequency Setting

the average current regulation in the current loop. It is

Voltage Loop Compensation

also fed to the peak current limitation block.

During power up time, high inrush currents cause high

VOUT Sense (Feedback) Input

negative voltage drop at R1, driving currents out of pin

IC Supply Voltage

3 which could be beyond the absolute maximum

ratings. Therefore a series resistor (R2) of around

Gate Drive Output

220Ω is recommended in order to limit this current into

the IC.

FREQ (Frequency Setting)

This pin allows the setting of the operating switching

frequency by connecting a resistor to ground. The

frequency range is from 50kHz to 250kHz.

VSENSE (Voltage Sense/Feedback)

The output bus voltage is sensed at this pin via a

resistive divider. The reference voltage for this pin is

3V.

VCOMP (Voltage Loop Compensation)

This pin provides the compensation of the output

voltage loop with a compensation network to ground

(see Figure 2). This also gives the soft start function

which controls an increasing AC input current during

start-up.

VCC (Power Supply)

The VCC pin is the positive supply of the IC and should

be connected to an external auxiliary supply. The

Figure 1

Pin Configuration (top view)

operating range is between 11V and 25V. The turn-on

threshold is at 11.8V and under voltage occurs at 11V.

There is no internal clamp for a limitation of the power

supply.

GATE

1.2

Pin Functionality

The GATE pin is the output of the internal driver stage,

GND (Ground)

which has a capability of 1.5A instantaneous source

The ground potential of the IC.

and 2.0A instantaneous sink current.

Its gate drive voltage is clamped at 15V (typically).

Version 2.3

09 November 2019

Symbol

GND

ICOMP

ISENSE

FREQ

VCOMP

VSENSE

VCC

GATE

ICE2PCS01/G

85 ... 265 VAC

Vout

auxiliary supply

300ns

1.5V

-1.43x

OTA3

1.7V

ISENSE

GATE

VSENSE

VCC

FREQ

VCOMP

OTA2

ICOMP

4.2V

PowerDown

UVLO VCC

0.6V

GND

PWM

Comparator

Ramp Generator

Variable Oscillator

Toff min

Over-current

Comparator

Deglitcher

PWM Logic Gate Driver

undervoltage lockout

open-loop protect

Voltage Loop

Current Loop

Compensation

Protection Block

3.25V

OverVoltage protect

Peak Current Limit

Current Loop

Nonlinear

Gain

OTA1

+/-30µA, 39µS

1.0mS

+/-50µA linear range

Vin

Fault

2.85V 3.18V

0.75 V

-ve

Window Detect

+ve

-ve

Soft Over

Current Control

Fault

OP1

Current Sense

Opamp

OSC CLK

2.5%T

Protection

Logic

RFI Filter D2 ... D5

CCM-PFC

ICE2PCS01/G

Representative Block diagram

Figure 2

Representative Block diagram

Version 2.3

09 November 2019

(VVSENSE > 0.6 V) (VVSENSE < 0.6 V)

VCC

11.8 V

11.0 V

IC's

Normal

Open loop/

OFF Start Operation

OFF

Operation

Standby

State

VSENSE

x VOUT )

(

R3 + R4

OTA1

VCO M P

protect

S 1

ICE2PCS01/G

(VVSENSE > 0.6 V)

CCM-PFC

ICE2PCS01/G

Functional Description

If VCC drops below 11V, the IC is off. The IC will then

3.1

General

be consuming typically 300∝A, whereas consuming

The ICE2PCS01/G is a 8 pin control IC for power factor

13mA during normal operation.

correction converters. It comes in both DIP and DSO

The IC can be turned off and forced into standby mode

packages and is suitable for wide range line input

by pulling down the voltage at pin 6 (VSENSE) to lower

applications from 85 to 265 VAC. The IC supports

than 0.6V. The current consumption is reduced to

converters in boost topology and it operates in

300µA in this mode.

continuous conduction mode (CCM) with average

current control.

3.3

Start-up

The IC operates with a cascaded control; the inner

current loop and the outer voltage loop. The inner

Figure 4 shows the operation of voltage loop’s OTA1

current loop of the IC controls the sinusoidal profile for

during startup. The VCOMP pin is pull internally to

the average input current. It uses the dependency of

ground via switch S1 during UVLO and other fault

the PWM duty cycle on the line input voltage to

conditions (see later section on “System Protection”).

determine the corresponding input current. This means

During power up when VOUT is less than 83% of the

the average input current follows the input voltage as

rated level, OTA1 sources an output current, maximum

long as the device operates in CCM. Under light load

30∝A, into the compensation network at pin 5

condition, depending on the choke inductance, the

(VCOMP) causing the voltage at this pin to rise linearly.

system may enter into discontinuous conduction mode

This results in a controlled linear increase of the input

(DCM). In DCM, the average current waveform will be

current from 0A thus reducing the stress on the

distorted but the resultant harmonics are still low

external component.

enough to meet the Class D requirement of IEC 1000-

3-2.

The outer voltage loop controls the output bus voltage.

Depending on the load condition, OTA1 establishes an

appropriate voltage at VCOMP pin which controls the

amplitude of the average input current.

The IC is equipped with various protection features to

ensure safe operating condition for both the system

and device. Important protection features are namely

Open-Loop protection, Current Limitation and Output

Over-voltage Protection.

3.2

Power Supply

An internal under voltage lockout (UVLO) block

monitors the VCC power supply. As soon as it exceeds

11.8V and the voltage at pin 6 (VSENSE) is >0.6V, the

Figure 4

Startup Circuit

IC begins operating its gate drive and performs its

Startup as shown in Figure 3.

As VOUT has not reached within 5% from the rated

value, VCOMP voltage is level-shifted by the window

detect block as shown in Figure 5, to ensure there is

fast boost up of the output voltage.

When VOUT approaches its rated value, OTA1’s

sourcing current drops and the level shift of the window

detect block is removed. The normal voltage loop then

takes control.

Figure 3

State of Operation respect to VCC

Version 2.3

09 November 2019

VCC > VCCUVLO VCC<VCCUVLO

VIN (VAC)

IC’s

State

PCL / SOC

OLP

VOUT

108%

VOUT,Rated

100%

20%

OVP

CCM-PFC

ICE2PCS01/G

Functional Description

3.4

System Protection

The IC provides several protection features in order to

ensure the PFC system in safe operating range.

Depending on the input line voltage (VIN) and output

Max Vcomp current

bus voltage (VOUT), Figure 7 and 8 show the conditions

VOUT =rated

when these protections are active.

VOUT

95%rated

83%rated

Level-shifted VCOMP

av(IIN)

VCOMP

Figure 6

VIN Related Protection Features

Figure 5

Startup with controlled maximum current

Figure 7

VOUT Related Protection Features

The following sections describe the functionality of

these protection features.

3.4.1

Soft Over Current Control (SOC)

The IC is designed not to support any output power

that corresponds to a voltage lower than -0.75V at the

ISENSE pin. A further increase in the inductor current,

which results in a lower ISENSE voltage, will activate

the Soft Over Current Control (SOC). This is a soft

control as it does not directly switch off the gate drive.

It acts on the nonlinear gain block to result in a reduced

PWM duty cycle.

Version 2.3

09 November 2019

Window Detect

Normal Control

Normal

Operation

IC OFF

igure 10 Frequency Versus RFREQ

---

POUT(rated)

POUT(max)

IC’s

Normal

State

Operation

SOC

VISENSE

-0.61V -0.75V

PCL

-1.04V

CCM-PFC

ICE2PCS01/G

Functional Description

connected) or an insufficient input voltage VIN for

normal operation. In this case, most of the blocks within

the IC will be shutdown. It is implemented using

comparator C3 with a threshold of 0.6V as shown in the

IC block diagram in Figure 2.

3.4.4

Over-Voltage Protection (OVP)

Whenever VOUT exceeds the rated value by 5%, the

over-voltage protection OVP is active as shown in

Figure 6. This is implemented by sensing the voltage at

pin VSENSE with respect to a reference voltage of

3.15V. A VSENSE voltage higher than 3.15V will

immediately reduce the output duty cycle, bypassing

the normal voltage loop control. This results in a lower

Figure 8

SOC and PCL Protection as function of

input power to reduce the output voltage VOUT. A

VISENSE

VSENSE voltage higher than 3.25V will immediately

turn off the gate, thereby preventing damage to bus

The rated output power with a minimum VIN (VINMIN) is

capacitor.

0.61

---

POUT(rated) = VINMIN ⋅

----

R1 ⋅ 2

3.5

Frequency Setting

Due to the internal parameter tolerance, the maximum

The switching frequency of the PFC converter can be

power with VINMIN is

set with an external resistor R5 at FREQ pin as shown

Figure 10. The pin voltage VFREQ is typically 1.7V. The

0.75

---

POUT(max) = VINMIN ⋅

----

corresponding capacitor for the oscillator is integrated

R1 ⋅ 2

in the device and the R5/frequency relationship is given

at the “Electrical Characteristic” section. The

recommended operating frequency range is from

3.4.2

Peak Current Limit (PCL)

50kHz to 250kHz. As an example, a R5 of 33kΩ at pin

The IC provides a cycle by cycle peak current limitation

FREQ will set a switching frequency FSW of 136kHz

(PCL). It is active when the voltage at pin 3 (ISENSE)

typically.

reaches -1.04V. This voltage is amplified by OP1 by a

factor of -1.43 and connected to comparator C2 with a

reference voltage of 1.5V as shown in Figure 9. A

deglitcher with 300ns after the comparator improves

noise immunity to the activation of this protection.

Current Limit

Full-wave

Deglitcher

Rectifier

300ns

1.5V

Turn Off

ISENSE

Driver

1.43x

IINDUCTOR

OP1

ICE2PCS01/G

Figure 9

Peak Current Limit (PCL)

3.4.3

Open Loop Protection / Input Under

Voltage Protect (OLP)

Whenever VSENSE voltage falls below 0.6V, or

equivalently VOUT falls below 20% of its rated value, it

indicates an open loop condition (i.e. VSENSE pin not

Version 2.3

09 November 2019

Vout

From

Full-wave

Retifier

GATE

ISENSE

Current Loop

voltage

proportional to

Gate

averaged

Inductor current

Driver

Current Loop

PWM

ICOMP

Compensation

Comparator

OTA2

1.0mS

PWM Logic

+/-50uA (linear range)

Input From

Nonlinear

4.2V

Voltage Loop

Gain

Fault

ICE2PCS01/G

CCM-PFC

ICE2PCS01/G

Functional Description

From the above equation, DOFF is proportional to VIN.

3.6

Average Current Control

The objective of the current loop is to regulate the

average inductor current such that it is proportional to

3.6.1

Complete Current Loop

the off duty cycle DOFF, and thus to the input voltage

The complete system current loop is shown in Figure

VIN. Figure 12 shows the scheme to achieve the

11.

objective.

ave(I

) at ICOMP

ramp profile

GATE

drive

Figure 12

Average Current Control in CCM

The PWM is performed by the intersection of a ramp

signal with the averaged inductor current at pin 5

(ICOMP). The PWM cycle starts with the Gate turn off

for a duration of TOFFMIN (250ns typ.) and the ramp is

Figure 11

Complete System Current Loop

kept discharged. The ramp is then allowed to rise after

It consists of the current loop block which averages the

TOFFMIN expires. The off time of the boost transistor

voltage at pin ISENSE, resulted from the inductor

ends at the intersection of the ramp signal and the

current flowing across R1. The averaged waveform is

averaged current waveform. This results in the

compared with an internal ramp in the ramp generator

proportional relationship between the average current

and PWM block. Once the ramp crosses the average

and the off duty cycle DOFF.

waveform, the comparator C1 turns on the driver stage

Figure 13 shows the timing diagrams of TOFFMIN and the

through the PWM logic block. The Nonlinear Gain block

PWM waveforms.

defines the amplitude of the inductor current. The

following sections describe the functionality of each

TOFFMIN

individual blocks.

2.5% of T

3.6.2

Current Loop Compensation

PWM cycle

The compensation of the current loop is done at the

ICOMP pin. This is the OTA2 output and a capacitor C3

VCREF(1)

has to be installed at this node to ground (see Figure

11). Under normal mode of operation, this pin gives a

voltage which is proportional to the averaged inductor

VRAMP

ramp

current. This pin is internally shorted to 4.2V in the

released

event of IC shuts down when OLP and UVLO occur.

PWM

3.6.3

Pulse Width Modulation (PWM)

The IC employs an average current control scheme in

(1) VCREF is a function of VICOMP

continuous conduction mode (CCM) to achieve the

power factor correction.

Figure 13

Ramp and PWM waveforms

Assuming the voltage loop is working and output

voltage is kept constant, the off duty cycle DOFF for a

3.6.4

Nonlinear Gain Block

CCM PFC system is given as

The nonlinear gain block controls the amplitude of the

VIN

regulated inductor current. The input of this block is the

DOFF

------

VOUT

Version 2.3

09 November 2019

Current

Limit Latch

Peak Current

HIGH =

Limit

turn GATE on

PWM on

Latch

Current Loop

PWM on signal

Toffmin

2.5% of T

CCM-PFC

ICE2PCS01/G

Functional Description

voltage at pin VCOMP. This block has been designed

to support the wide input voltage range (85-265VAC).

Vout

From

3.7

PWM Logic

Full-wave

Retifier

The PWM logic block prioritizes the control input

signals and generates the final logic signal to turn on

the driver stage. The speed of the logic gates in this

block, together with the width of the reset pulse TOFFMIN,

Gate Driver

are designed to meet a maximum duty cycle DMAX of

Current Loop

95% at the GATE output under 136kHz of operation.

PWM Generation

In case of high input currents which result in Peak

VIN

GATE

Current Limitation, the GATE will be turned off

immediately and maintained in off state for the current

PWM cycle. The signal Toffmin resets (highest priority,

Nonlinear

OTA1

Av(IIN)

Gain

overriding other input signals) both the current limit

VSENSE

latch and the PWM on latch as illustrated in Figure 14.

VCOMP

ICE2PCS01/G

Figure 15

Voltage Loop

3.8.2

Enhanced Dynamic Response

Due to the low frequency bandwidth of the voltage loop,

the dynamic response is slow and in the range of about

Figure 14

PWM Logic

several 10ms. This may cause additional stress to the

bus capacitor and the switching transistor of the PFC in

the event of heavy load changes.

3.8

Voltage Loop

The IC provides therefore a “window detector” for the

The voltage loop is the outer loop of the cascaded

feedback voltage VVSENSE at pin 6 (VSENSE).

Whenever VVSENSE exceeds the reference value (3V)

control scheme which controls the PFC output bus

by +5%, it will act on the nonlinear gain block which in

voltage VOUT. This loop is closed by the feedback

turn affect the gate drive duty cycle directly. This

sensing voltage at VSENSE which is a resistive divider

change in duty cycle is bypassing the slow changing

tapping from VOUT. The pin VSENSE is the input of

VCOMP voltage, thus results in a fast dynamic

OTA1 which has an internal reference of 3V. Figure 15

response of VOUT.

shows the important blocks of this voltage loop.

3.8.1

Voltage Loop Compensation

3.9

Output Gate Driver

The compensation of the voltage loop is installed at the

VCOMP pin (see Figure 15). This is the output of OTA1

The output gate driver is a fast totem pole gate drive. It

and the compensation must be connected at this pin to

has an in-built cross conduction currents protection and

ground. The compensation is also responsible for the

a Zener diode Z1 (see Figure 16) to protect the external

soft start function which controls an increasing AC input

transistor switch against undesirable over voltages.

current during start-up.

The maximum voltage at pin 8 (GATE) is typically

clamped at 15V.

The output is active HIGH and at VCC voltages below

the under voltage lockout threshold VCCUVLO, the gate

drive is internally pull low to maintain the off state.

Version 2.3

09 November 2019

VCC

Gate Driver

PWM Logic

HIGH to

turn on

External

MOS

GATE

* LV: Level Shift

ICE2PCS01/G

CCM-PFC

ICE2PCS01/G

Functional Description

Figure 16

Gate Driver

Version 2.3

09 November 2019

CCM-PFC

ICE2PCS01/G

Electrical Characteristics

4.1

Absolute Maximum Ratings

Note:

Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction

of the integrated circuit.

Parameter

Remarks

VCC Supply Voltage

FREQ Voltage

ICOMP Voltage

ISENSE Voltage

ISENSE Current

Recommended R2=220Ω

VSENSE Voltage

VSENSE Current

R3>400kΩ

VCOMP Voltage

GATE Voltage

Clamped at 15V if driven

internally.

Junction Temperature

Storage Temperature

Thermal Resistance

PG-DSO-8-13

Junction-Ambient for DSO-8-13

Thermal Resistance

PG-DIP-8-4

Junction-Ambient for DIP-8-4

ESD Protection

Human Body Model1)

According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5kΩ series resistor)

2) Absolute ISENSE current should not be exceeded

4.2

Operating Range

Note:

Within the operating range the IC operates as described in the functional description.

Parameter

Remarks

VCC Supply Voltage

Junction Temperature

Version 2.3

09 November 2019

Symbol

Limit Values

Unit

min.

max.

VCC

-0.3

VFREQ

-0.3

VICOMP

-0.3

VISENSE

-20

IISENSE

-1

VVSENSE

-0.3

IVSENSE

-1

VVCOMP

-0.3

VGATE

-0.3

-40

150

°C

-55

150

°C

RthJA (DSO)

185

K/W

RthJA(DIP)

K/W

VESD

Symbol

Limit Values

Unit

min.

max.

VCC

VCCUVLO

TJCon

-40

125

°C

CCM-PFC

ICE2PCS01/G

Electrical Characteristics

4.3

Characteristics

Note:

The electrical characteristics involve the spread of values within the specified supply voltage and junction

temperature range TJ from – 40 °C to 125°C.Typical values represent the median values, which are

related to 25°C. If not otherwise stated, a supply voltage of VCC =18V is assumed for test condition.

4.3.1

Supply Section

Parameter

Test Condition

VCC Turn-On Threshold

VCC Turn-Off Threshold/

Under Voltage Lock Out

VCC Turn-On/Off Hysteresis

Start Up Current

VVCC=VVCCon -0.1V

Before VCCon

Operating Current with active GATE

R5 = 33kΩ

CL= 4.7nF

Operating Current during Standby

VVSENSE= 0.5V

VICOMP= 4V

4.3.2

Variable Frequency Section

Parameter

Test Condition

Switching Frequency (Typical)

R5 = 33kΩ

Switching Frequency (Min.)

R5 = 82kΩ

Switching Frequency (Max.)

R5 = 15kΩ

Voltage at FREQ pin

Version 2.3

09 November 2019

Symbol

Limit Values

Unit

min.

typ.

max.

VCCon

11.4

11.8

12.7

VCCUVLO

10.4

11.0

11.7

VCChy

0.65

0.8

1.4

ICCstart

450

1100

∝A

ICCHG

ICCStdby

700

1300

∝A

Symbol

Limit Values

Unit

min.

typ.

max.

FSWnom

124

136

147

kHz

FSWmin

kHz

FSWmax

250

285

315

kHz

VFREQ

1.65

1.70

1.76

CCM-PFC

ICE2PCS01/G

Electrical Characteristics

4.3.3

PWM Section

Parameter

Test Condition

Max. Duty Cycle

FSW = FSWnom

(R5 = 33kΩ)

Min. Duty Cycle

VVCOMP= 0V, VVSENSE= 3V

VICOMP= 4.3V

Min. Off Time

VVSENSE= 3V

VISENSE= 0.1V (R5 = 33kΩ)

The parameter is not subject to production test - verified by design/characterization

4.3.4

System Protection Section

Parameter

Test Condition

Open Loop Protection (OLP)

VSENSE Threshold

Peak Current Limitation (PCL)

ISENSE Threshold

Soft Over Current Control (SOC)

ISENSE Threshold

Output Over-Voltage Protection (OVP)

Version 2.3

09 November 2019

Symbol

Limit Values

Unit

min.

typ.

max.

DMAX

98.5

DMIN

TOFFMIN

100

250

580

Symbol

Limit Values

Unit

min.

typ.

max.

VOLP

0.55

0.6

0.65

VPCL

-1.16

-1.04

-0.95

VSOC

-0.75

-0.68

-0.61

VOVP

3.1

3.25

3.4

CCM-PFC

ICE2PCS01/G

Electrical Characteristics

4.3.5

Current Loop Section

Parameter

Test Condition

OTA2 Transconductance Gain

At Temp = 25°C

OTA2 Output Linear Range1)

ICOMP Voltage during OLP

VVSENSE= 0.5V

4.3.6

Voltage Loop Section

Parameter

Test Condition

OTA1 Reference Voltage

measured at VSENSE

OTA1 Transconductance Gain

OTA1 Max. Source Current

VVSENSE= 2V

Under Normal Operation

VVCOMP= 3V

OTA1 Max. Sink Current

VVSENSE= 4V

Under Normal Operation

VVCOMP= 3V

Enhanced Dynamic Response

VSENSE High Threshold

VSENSE Low Threshold

VSENSE Input Bias Current at 3V

VVSENSE= 3V

VSENSE Input Bias Current at 1V

VVSENSE= 1V

VCOMP Voltage during OLP

VVSENSE= 0.5V

IVCOMP= 0.5mA

Version 2.3

09 November 2019

Symbol

Limit Values

Unit

min.

typ.

max.

GmOTA2

0.8

1.0

1.3

IOTA2

± 50

∝A

VICOMPF

3.9

4.2

Symbol

Limit Values

Unit

min.

typ.

max.

VOTA1

2.92

3.00

3.08

GmOTA1

∝S

IOTA1SO

∝A

IOTA1SK

∝A

VHi

VLo

3.09

2.76

3.18

2.85

3.26

2.94

IVSEN3V

1.5

∝A

IVSEN1V

∝A

VVCOMPF

0.2

0.4

CCM-PFC

ICE2PCS01/G

Electrical Characteristics

4.3.7

Driver Section

Parameter

Test Condition

GATE Low Voltage

VCC =10V

IGATE = 5 mA

VCC =10V

IGATE =20 mA

IGATE = 0 A

IGATE = 20 mA

IGATE = -20 mA

GATE High Voltage

VCC = 25V

CL = 4.7nF

VCC = 19V

CL = 4.7nF

VCC = VVCCoff + 0.2V

CL = 4.7nF

GATE Rise Time

VGate = 2V ...12V

CL = 4.7nF

GATE Fall Time

VGate = 12V ...2V

CL = 4.7nF

GATE Current, Peak,

CL = 4.7nF1)

Rising Edge

GATE Current, Peak,

CL = 4.7nF1)

Falling Edge

Design characteristics (not meant for production testing)

Version 2.3

09 November 2019

Symbol

Limit Values

Unit

min.

typ.

max.

VGATEL

1.2

1.5

0.4

1.0

-0.2

VGATEH

14.8

7.8

9.2

IGATE

-1.5

IGATE

2.0

CCM-PFC

ICE2PCS01/G

Outline Dimension

Figure 17

PG-DSO-8 and PG-DIP-8 Outline Dimension

Version 2.3

09 November 2019

h t t p : / / w w w . i n f i n e o n . c o m

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