ADT7476ARQZ-REEL - Analog Devices

dBCool™ Remote Thermal

Controller and Voltage Monitor

ADT7476

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

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FEATURES

Monitors up to 5 voltages

Controls and monitors up to 4 fans

High and low frequency fan drive signal

1 on-chip and 2 remote temperature sensors

Extended temperature measurement range up to 191°C

Automatic fan speed control mode controls system cooling

based on measured temperature

Enhanced acoustic mode dramatically reduces user

perception of changing fan speeds

Thermal protection feature via THERM output

Monitors performance impact of Intel® Pentium™ 4

processor

Thermal control circuit via THERM input

3-wire and 4-wire fan speed measurement

Limit comparison of all monitored values

Meets SMBus 2.0 electrical specifications

GENERAL DESCRIPTION

The ADT7476 dBCool controller is a thermal monitor

and multiple PWM fan controller for noise-sensitive or power-

sensitive applications requiring active system cooling. The

ADT7476 can drive a fan using either a low or high frequency

drive signal, monitor the temperature of up to two remote

sensor diodes plus its own internal temperature, and measure

and control the speed of up to four fans, so they operate at

the lowest possible speed for minimum acoustic noise.

The automatic fan speed control loop optimizes fan speed

for a given temperature. The effectiveness of the system’s

thermal solution can be monitored using the THERM input.

The ADT7476 also provides critical thermal protection to

the system using the bidirectional THERM pin as an output

to prevent system or component overheating.

FUNCTIONAL BLOCK DIAGRAM

05382-001

ACOUSTIC

ENHANCEMENT

CONTROL

BAND GAP

REFERENCE

10-BIT

ADC

INTERRUPT

MASKING

PWM

CONFIGURATION

REGISTERS

ADDRESS

POINTER

VALUE AND

LIMIT

REGISTERS

LIMIT

COMPARATORS

INTERRUPT

STATUS

REGISTERS

INPUT

SIGNAL

CONDITIONING

AND

ANALOG

MULTIPLEXER

VCC TO ADT7476

VCC

D1+

D1–

D2+

D2–

+5VIN

+12VIN

+2.5VIN

VCCP

VID/GPIO

VID5

ID4/GPIO4

ID3/GPIO3

ID2/GPIO2

ID1/GPIO1

ID0/GPIO0

GPIO6

SERIAL BUS

INTERFACE

SCL SDA SMBALERT

SMBus

ADDRESS

SELECTION

ADDR

SELECT

ADDREN

GND

PWM1

PWM2

PWM3

PWM

REGISTERS

AND

CONTROLLERS

(HF AND LF)

AUTOMATIC

FAN SPEED

CONTROL

TACH1

TACH2

TACH3

TACH4

FAN

SPEED

COUNTER

THERMAL

PROTECTION

PERFORMANCE

MONITORING

THERM

BAND GAP

TEMP. SENSOR

ADT7476

Figure 1.

ADT7476

Rev. A | Page 2 of 72

TABLE OF CONTENTS

Features .............................................................................................. 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Table of Contents .............................................................................. 2

Revision History ............................................................................... 3

Specifications..................................................................................... 4

Timing Diagram ........................................................................... 5

Absolute Maximum Ratings............................................................ 6

Thermal Resistance ...................................................................... 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics ............................................. 9

Product Description....................................................................... 11

Feature Comparisons Between ADT7476 and ADT7468..... 11

Recommended Implementation............................................... 12

Serial Bus Interface..................................................................... 13

Write Operations........................................................................ 15

Read Operations......................................................................... 16

SMBus Timeout .......................................................................... 16

Virus Protection.......................................................................... 16

Voltage Measurement Input...................................................... 17

Analog-to-Digital Converter .................................................... 17

Input Circuitry............................................................................ 17

Voltage Measurement Registers................................................ 17

Voltage Limit Registers .............................................................. 17

Extended Resolution Registers ................................................. 17

Additional ADC Functions for Voltage Measurements ........ 17

VID Code Monitoring............................................................... 20

VID Code Input Threshold Voltage......................................... 20

VID Code Change Detect Function ........................................ 20

Programming the GPIOs........................................................... 20

Temperature Measurement Method ........................................ 20

Factors Affecting Diode Accuracy........................................... 22

Additional ADC Functions for Temperature

Measurement .............................................................................. 23

Limits, Status Registers, and Interrupts....................................... 25

Limit Values ................................................................................ 25

Status Registers ........................................................................... 26

THERM Timer ........................................................................... 28

Fan Drive Using PWM Control ............................................... 31

Laying Out 3-Wire Fans ............................................................ 33

Programming TRANGE.................................................................. 36

Programming the Automatic Fan Speed Control Loop ............ 37

Manual Fan Control Overview................................................. 37

THERM Operation in Manual Mode...................................... 37

Automatic Fan Control Overview............................................ 37

Step 1: Hardware Configuration .............................................. 38

Step 2: Configuring the Mux .................................................... 41

Step 3: TMIN Settings for Thermal Calibration Channels ...... 43

Step 4: PWMMIN for Each PWM (Fan) Output ...................... 44

Step 5: PWMMAX for PWM (Fan) Outputs.............................. 45

Step 6: TRANGE for Temperature Channels................................ 46

Step 7: TTHERM for Temperature Channels ............................... 48

Step 8: THYST for Temperature Channels.................................. 50

Fan Presence Detect................................................................... 51

Fan Sync....................................................................................... 52

Standby Mode ............................................................................. 52

XNOR Tree Test Mode .............................................................. 52

Power-On Default ...................................................................... 52

Outline Dimensions ....................................................................... 72

Ordering Guide .......................................................................... 72

ADT7476

Rev. 0 | Page 3 of 72

REVISION HISTORY

3/06—Rev. 0 to Rev. A

Changes to Features Section ............................................................1

Changes to Table 1 ............................................................................4

Inserted Table 3..................................................................................6

Changes to Feature Comparisons Between ADT7476 and

ADT7468 Section............................................................................11

Changes to Figure 23 ......................................................................16

Changes to Fan Speed Measurement Registers Section.............34

Changes to Register Tables Section...............................................53

Changes to Ordering Guide...........................................................72

4/05—Revision 0: Initial Version

ADT7476

Rev. A | Page 4 of 72

SPECIFICATIONS

TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.1

Table 1.

Parameter Min Typ Max Unit Test Conditions/Comments

POWER SUPPLY

Supply Voltage 3.0 3.3 3.6 V

Supply Current, ICC 1.5 3 mA Interface inactive, ADC active

TEMPERATURE-TO-DIGITAL CONVERTER

Local Sensor Accuracy ±0.5 ±1.5 °C 0°C ≤ TA ≤ 85°C

±2.5 °C –40°C ≤ TA ≤ 125°C

Resolution 0.25 °C

Remote Diode Sensor Accuracy ±0.5 ±1.5 °C 0°C ≤ TA ≤ 85°C

±2.5 °C –40°C ≤ TA ≤ 125°C

Resolution 0.25 °C

Remote Sensor Source Current 180 μA High level

11 μΑ Low level

ANALOG-TO-DIGITAL CONVERTER

(INCLUDING MUX AND ATTENUATORS)

Total Unadjusted Error (TUE) ±2 % For 12 V channel

±1.5 % For all other channels

Differential Nonlinearity (DNL) ±1 LSB 8 bits

Power Supply Sensitivity ±0.1 %/V

Conversion Time (Voltage Input) 11 ms Averaging enabled

Conversion Time (Local Temperature) 12 ms Averaging enabled

Conversion Time (Remote Temperature) 38 ms Averaging enabled

Total Monitoring Cycle Time 145 ms Averaging enabled

Total Monitoring Cycle Time 19 ms Averaging disabled

Input Resistance 70 120 kΩ For VCCP channel

70 114 kΩ For all other channels

FAN RPM-TO-DIGITAL CONVERTER

Accuracy ±6 % 0°C ≤ TA ≤ 70°C

±10 % −40°C ≤ TA ≤ +120°C

Full-Scale Count 65,535

Nominal Input RPM 109 RPM Fan count = 0xBFFF

329 RPM Fan count = 0x3FFF

5000 RPM Fan count = 0x0438

10,000 RPM Fan count = 0x021C

OPEN-DRAIN DIGITAL OUTPUTS, PWM1 TO PWM3,

XTO

Current Sink, IOL 8.0 mA

Output Low Voltage, VOL 0.4 V IOUT = −8.0 mA

High Level Output Current, IOH 0.1 20 μA VOUT = VCC

OPEN-DRAIN SERIAL DATA BUS OUTPUT (SDA)

Output Low Voltage, VOL 0.4 V IOUT = −4.0 mA

High Level Output Current, IOH 0.1 1.0 μA VOUT = VCC

ADT7476

Rev. A | Page 5 of 72

Parameter Min Typ Max Unit Test Conditions/Comments

SMBUS DIGITAL INPUTS (SCL, SDA)

Input High Voltage, VIH 2.0 V

Input Low Voltage, VIL 0.4 V

Hysteresis 500 mV

DIGITAL INPUT LOGIC LEVELS (TACH INPUTS)

Input High Voltage, VIH 2.0 V

3.6 V Maximum input voltage

Input Low Voltage, VIL 0.8 V

−0.3 V Minimum input voltage

Hysteresis 0.5 V p-p

DIGITAL INPUT LOGIC LEVELS (THERM) ADTL+

Input High Voltage, VIH 0.75 × VCC V

Input Low Voltage, VIL 0.4 V

DIGITAL INPUT CURRENT

Input High Current, IIH ±1 μA VIN = VCC

Input Low Current, IIL ±1 μA VIN = 0

Input Capacitance, CIN 5 pF

SERIAL BUS TIMING2 See Figure 2

Clock Frequency, fSCLK 10 400 kHz

Glitch Immunity, tSW 50 ns

Bus Free Time, tBUF 4.7 μs

SCL Low Time, tLOW 4.7 μs

SCL High Time, tHIGH 4.0 50 μs

SCL, SDA Rise Time, tr 1000 ns

SCL, SDA Fall Time, tf 300 μs

Data Setup Time, tSU;DAT 250 ns

Detect Clock Low Timeout, tTIMEOUT 15 35 ms Can be disabled

1 All voltages are measured with respect to GND, unless otherwise specified. Typical voltages are TA = 25°C and represent a most likely parametric norm. Logic inputs

accept input high voltages up to VMAX, even when the device is operating down to VMIN. Timing specifications are tested at logic levels of VIL = 0.8 V for a falling edge,

and VIH = 2.0 V for a rising edge.

2 SMBus timing specifications are guaranteed by design and are not production tested.

TIMING DIAGRAM

SCL

BUF

HD; STA

HD; DAT

SU; DAT

LOW

SU; STA

HIGH

HD; STA

SU; STO

05382-002

Figure 2. Serial Bus Timing Diagram

ADT7476

Rev. A | Page 6 of 72

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Positive Supply Voltage (VCC) 3.6 V

Maximum Voltage on +12VIN Pin 16 V

Maximum Voltage on +5VIN Pin 6.25V

Maximum Voltage on All Open-Drain Outputs 3.6 V

Voltage on Any Input or Output Pin −0.3 V to +4.2 V

Input Current at Any Pin ±5 mA

Package Input Current ±20 mA

Maximum Junction Temperature (TJ MAX) 150°C

Storage Temperature Range −65°C to

+150°C

Lead Temperature, Soldering

IR Reflow Peak Temperature 220°C

Pb-Free Peak Temperature 260°C

Lead Temperature (Soldering, 10 sec) 300°C

ESD rating 1500 V

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

Table 3. Thermal Resistance

Package Type θJA θJC Unit

24-Lead QSOP 122 31.25 °C/W

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on

the human body and test equipment and can discharge without detection. Although this product features

proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy

electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance

degradation or loss of functionality.

ADT7476

Rev. A | Page 7 of 72

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

05382-003

+5V

VID4/GPIO4

D1+

D1–

PWM1/XTO

CCP

+2.5V

/THERM

+12V

/VID5

D2+

D2–

PWM3/ADDREN

TACH4/THERM/SMBALERT/GPIO6/ADDR SELECT

VID0/GPIO0

VID1/GPIO1

VID2/GPIO2

VID3/GPIO3

TACH1

TACH2

TACH3

PWM2/SMBALERT

SDA

SCL

GND

ADT7476

TOP VIEW

(Not to Scale)

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 SDA Digital I/O (Open Drain). SMBus bidirectional serial data. Requires SMBus pull-up.

2 SCL Digital Input (Open Drain). SMBus serial clock input. Requires SMBus pull-up.

3 GND Ground Pin.

4 VCC Power Supply. Powered by 3.3 V standby, if monitoring in low power states is required. VCC is also monitored

through this pin.

5 VID0 Digital Input. Voltage supply readouts from CPU. This value is read into the VID register (0x43).

GPIO0 General-Purpose Open-Drain Digital I/O.

6 VID1 Digital Input. Voltage supply readouts from CPU. This value is read into the VID register (0x43).

GPIO1 General-Purpose Open-Drain Digital I/O.

7 VID2 Digital Input. Voltage supply readouts from CPU. This value is read into the VID register (0x43).

GPIO2 General-Purpose Open-Drain Digital I/O.

8 VID3 Digital Input. Voltage supply readouts from CPU. This value is read into the VID register (0x43).

GPIO3 General-Purpose Open-Drain Digital I/O.

9 TACH3 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 3.

10 PWM2 Digital Output (Open Drain). Requires 10 kΩ typical pull-up. Pulse-width modulated output to control Fan 2

speed. Can be configured as a high or low frequency drive.

SMBALERT Digital Output (Open Drain). This pin can be reconfigured as an SMBALERT interrupt output to signal out-of-

limit conditions.

11 TACH1 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 1.

12 TACH2 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 2.

13 PWM3 Digital I/O (Open Drain). Pulse-width modulated output to control Fan 3 and Fan 4 speed. Requires 10 kΩ typical

pull-up. Can be configured as a high or low frequency drive.

ADDREN If pulled low on power-up, the ADT7476 enters address select mode, and the state of Pin 14 (ADDR SELECT)

determines the ADT7476 slave address.

14 TACH4 Digital Input (Open Drain). Fan tachometer input to measure speed of Fan 4.

THERM Alternatively, the pin can be reconfigured as a bidirectional THERM pin. Use to time and monitor assertions on

the THERM input. For example, can be connected to the PROCHOT output of an Intel Pentium 4 processor or to

the output of a trip point temperature sensor. Can be used as an output to signal overtemperature conditions.

SMBALERT Digital Output (Open Drain). This pin can be reconfigured as an SMBALERT interrupt output to signal out-of-

limit conditions.

GPIO6 General-Purpose Open-Drain Digital I/O.

ADDR SELECT If in address select mode, the logic state of this pin defines the SMBus device address.

15 D2– Cathode Connection to Second Thermal Diode.

ADT7476

Rev. A | Page 8 of 72

Pin No. Mnemonic Description

16 D2+ Anode Connection to Second Thermal Diode.

17 D1– Cathode Connection to First Thermal Diode.

18 D1+ Anode Connection to First Thermal Diode.

19 VID4 Digital Input. Voltage supply readouts from CPU. This value is read into the VID register (0x43).

GPIO4 General-Purpose Open-Drain Digital I/O.

20 +5VIN Analog Input. Monitors +5 V power supply.

21 +12VIN Analog Input. Monitors +12 V power supply.

VID5 Digital Input. Voltage supply readouts from CPU. This value is read into the VID register (0x43).

22 +2.5VIN Analog Input. Monitors +2.5 V supply, typically a chipset voltage.

THERM Alternatively, this pin can be reconfigured as a bidirectional/omnidirectional THERM pin. Can be used to time

and monitor assertions on the THERM input. For example, can be connected to the PROCHOT output of an Intel

Pentium 4 processor or to the output of a trip point temperature sensor. Can be used as an output to signal

overtemperature conditions.

23 VCCP Analog Input. Monitors processor core voltage (0 V to 3 V).

24 PWM1 Digital Output (Open Drain). Pulse-width modulated output to control Fan 1 speed. Requires 10 kΩ typical

pull-up.

XTO Also functions as the output from the XOR tree in XOR test mode.

ADT7476

Rev. A | Page 9 of 72

TYPICAL PERFORMANCE CHARACTERISTICS

–10

–20

–30

–40

–50

–60

024681012

CAPACITANCE (nF)

TEMPERATURE ERROR (°C)

14 16 18 20 22

05382-004

Figure 4. Temperature Error vs. Capacitance Between D+ and D−

–10

–20

–30

0204060

LEAKAGE RESISTANCE (MΩ)

TEMPERATURE ERROR (°C)

80 100

–40

05382-006

D+ TO V

D+ TO GND

Figure 5. Remote Temperature Error vs. PCB Resistance

–5

0 100M 200M 300M 400M 500M 600M

NOISE FREQUENCY (Hz)

TEMPERATURE ERROR (°C)

100mV

60mV

40mV

05382-007

Figure 6. Remote Temperature Error vs. Common-Mode Noise Frequency

0 100M 200M 300M 400M 500M 600M

NOISE FREQUENCY (Hz)

TEMPERATURE ERROR (°C)

40mV

05382-008

–10

60mV

100mV

Figure 7. Remote Temperature Error vs. Differential Mode Noise Frequency

1.20

1.18

1.16

1.14

1.12

1.10

1.08

1.06

3.0 3.1 3.2 3.3 3.4

(V)

(mA)

1.04

1.02

3.5 3.6

1.00

0.98

05382-009

Figure 8. Normal IDD vs. Power Supply

100mV

250mV

–5

–10

–15

0 100M 200M 300M 400M 500M 600M

FREQUENCY (Hz)

TEMPERATURE ERROR (°C)

05382-010

Figure 9. Internal Temperature Error vs. Power Supply

ADT7476

Rev. A | Page 10 of 72

05382-011

–2

–4

–6

0 100M 200M 300M

FREQUENCY (Hz)

TEMPERATURE ERROR (°C)

400M 500M 600M

–8

–10

–12

100mV

250mV

Figure 10. Remote Temperature Error vs. Power Supply Noise Frequency

3.0

2.5

2.0

1.5

1.0

0.5

–0.5

–40 –20 0 20 40 60 85

OIL BATH TEMPERATURE (°C)

TEMPERATURE ERROR (°C)

–1.0

–1.5

105 125

05382-012

Figure 11. Internal Temperature Error vs. Temperature

3.0

2.5

2.0

1.5

1.0

0.5

–0.5

–40 –20 0 20 40 60 85

OIL BATH TEMPERATURE (°C)

TEMPERATURE ERROR (°C)

–1.0

–1.5

105 125

05382-013

–2.0

Figure 12. Remote Temperature Error vs. Temperature

ADT7476

Rev. A | Page 11 of 72

PRODUCT DESCRIPTION

The ADT7476 is a complete thermal monitor and multiple fan

controller for any system requiring thermal monitoring and

cooling. The device communicates with the system via a serial

system management bus. The serial bus controller has a serial

data line for reading and writing addresses and data (Pin 1),

and an input line for the serial clock (Pin 2). All control and

programming functions for the ADT7476 are performed over

the serial bus. In addition, a pin can be reconfigured as an

SMBALERT output to signal out-of-limit conditions.

FEATURE COMPARISONS BETWEEN ADT7476

AND ADT7468

• Dynamic TMIN , dynamic operating point, and associated

registers are no longer available on the ADT7476. The

following related registers are not available in the

ADT7476:

• Calibration Control 1 and Calibration Control 2

(Register 0x36 and Register 0x37)

• Operating Point (Register 0x33, Register 0x34, and

• Previously, TRANGE defined the slope of the automatic fan

control algorithm. For the ADT7476, TRANGE now defines a

true temperature range.

• For the ADT7476, acoustic filtering is now assigned to

temperature zones and not to fans. Smoothing times have

been increased for better acoustic performance.

• For the ADT7476, temperature measurements are made

with two switching currents instead of three. SRC is not

available in the ADT7476.

• For the ADT7476, high frequency PWM can now be

enabled/disabled on each PWM output individually.

• For the ADT7476, THERM can now be enabled/disabled

on each temperature channel individually.

• The ADT7476 does not support full shutdown mode.

• The ADT7476 defaults to twos complement temperature

measurement mode.

• Some pins have swapped/added functions.

• The power-up routine for the ADT7476 is simplified.

Other minor changes in the ADT7476 include the following:

• Vcore_low_enable has been reallocated to Bit 7 of

Configuration Register 1 (0x40).

• Dev ID register reads 0x76.

ADT7476

Rev. A | Page 12 of 72

RECOMMENDED IMPLEMENTATION

Configuring the ADT7476, as shown in Figure 13, allows the

system designer to use the following features:

• Two PWM outputs for fan control of up to three fans. (The

front and rear chassis fans are connected in parallel.)

• Three TACH fan speed measurement inputs.

• VCC measured internally through Pin 4.

• CPU temperature measured using Remote 1 temperature

channel.

• Remote temperature zone measured through Remote 2

temperature channel.

• Local temperature zone measured through the internal

temperature channel.

• Bidirectional THERM pin. This feature allows Intel

Pentium 4 PROCHOT monitoring and can function as an

overtemperature THERM output. It can alternatively be

programmed as an SMBALERT system interrupt output.

05382-014

TACH2

PWM3

TACH3

D1+

D1–

+5V

+12V

/VID5

GND

ADT7476

SCL

SDA

D2+

D2–

TACH1

VID[0:4]/VID[0:5]

PWM1

AMBIENT

TEMPERATURE

SMBALERT

THERM

5(VRM9)/6(VRM10)

PROCHOT

FRONT

CHASSIS

FAN

REAR

CHASSIS

FAN

Figure 13. ADT7476 Configuration

ADT7476

Rev. A | Page 13 of 72

SERIAL BUS INTERFACE

Control of the ADT7476 is carried out using the serial system

management bus (SMBus). The ADT7476 is connected to this

bus as a slave device, under the control of a master controller.

The ADT7476 has a 7-bit serial bus address. When the device

is powered up with Pin 13 (PWM3/ADDREN) high, the

ADT7476 has a default SMBus address of 0101110 or 0x2E.

The read/write bit must be added to get the 8-bit address.

If more than one ADT7476 is used in a system, each ADT7476

is placed in ADDR SELECT mode by strapping Pin 13 low on

power-up. The logic state of Pin 14 then determines the device’s

SMBus address. The logic of these pins is sampled on power-up.

The device address is sampled on power-up and latched on

the first valid SMBus transaction, more precisely on the low-to-

high transition at the beginning of the 8th SCL pulse, when the

serial bus address byte matches the selected slave address.

The selected slave address is chosen using the ADDREN pin/

ADDR SELECT pin. Any attempted changes in the address

have no effect after this.

Table 5. Hardwiring the ADT7476 SMBus Device Address

Pin 13 State Pin 14 Address

0 Low (10 kΩ to GND) 0101100 (0x2C)

0 High (10 kΩ Pull-Up) 0101101 (0x2D)

1 Don’t Care 0101110 (0x2E)

05382-015

ADT7476

ADDRESS = 0x2E

VCC

ADDR SELECT

PWM3/ADDREN

10kΩ

Figure 14. Default SMBus Address = 0x2E

5382-016

ADT7476

ADDRESS = 0x2C

10kΩ

ADDR SELECT

PWM3/ADDREN

Figure 15. SMBus Address = 0x2C (Pin 14 = 0)

05382-017

ADT7476

ADDRESS = 0x2D

10kΩ

ADDR SELECT

PWM3/ADDREN

Figure 16. SMBus Address = 0x2D (Pin 14 = 1)

05382-018

DO NOT LEAVE ADDREN

UNCONNECTED! CAN

CAUSE UNPREDICTABLE

ADDRESSES.

ADT7476

13 NC

10kΩ

ARE SHOULD BE TAKEN TO ENSURE THAT PIN 13

(PWM3/ADDREN) IS EITHER TIED HIGH OR LOW. LEAVING PIN 1

FLOATING COULD CAUSE THE ADT7476 TO POWER UP WITH AN

UNEXPECTED ADDRESS.

NOTE THAT IF THE ADT7476 IS PLACED INTO ADDR SELECT

MODE, PINS 13 AND 14 CANNOT BE USED AS THE ALTERNATIVE

FUNCTIONS (PWM3, TACH4/THERM) UNLESS THE CORRECT

IRCUIT IS MUXED IN AT THE CORRECT TIME OR DESIGNED TO

HANDLE THESE DUAL FUNCTIONS.

ADDR SELECT

PWM3/ADDREN

Figure 17. Unpredictable SMBus Address if Pin 13 Is Unconnected

The ability to make hardwired changes to the SMBus slave

address allows the user to avoid conflicts with other devices

sharing the same serial bus, for example, if more than one

ADT7476 is used in a system.

The serial bus protocol operates as follows:

1. The master initiates data transfer by establishing a start

condition, defined as a high-to-low transition on the serial

data line SDA while the serial clock line SCL remains high.

This indicates an address/data stream follows. All slave

peripherals connected to the serial bus respond to the start

condition and shift in the next eight bits, consisting of a

7-bit address (MSB first), plus a R/W bit that determines

the direction of the data transfer, that is, whether data is

written to or read from the slave device.

2. The peripheral whose address corresponds to the transmit-

ted address responds by pulling the data line low during

the low period before the ninth clock pulse, known as the

acknowledge bit. All other devices on the bus now remain

idle while the selected device waits for data to be read from

or written to it. If the R/W bit is a 0, the master writes to

the slave device. If the R/W bit is a 1, the master reads from

the slave device.

3. Data is sent over the serial bus in sequences of nine clock

pulses, eight bits of data followed by an acknowledge bit

from the slave device. Transitions on the data line must

occur during the low period of the clock signal and

remain stable during the high period. A low-to-high

transition, when the clock is high, can be interpreted

as a stop signal. The number of data bytes transmitted

over the serial bus in a single read or write operation is

limited only by what the master and slave devices

can handle.

ADT7476

Rev. A | Page 14 of 72

4. When all data bytes have been read or written, stop

conditions are established. In write mode, the master pulls

the data line high during the 10th clock pulse to assert a

stop condition.

In read mode, the master device overrides the acknowledge

bit by pulling the data line high during the low period before

the ninth clock pulse. This is known as No Acknowledge.

The master then takes the data line low during the low

period before the 10th clock pulse, and then high during

the 10th clock pulse to assert a stop condition. Any number

of bytes of data can be transferred over the serial bus in one

operation. It is not possible to mix read and write in one

operation because the type of operation is determined at

the beginning and cannot subsequently be changed with-

out starting a new operation. For the ADT7476, write

operations contain either one or two bytes, and

read operations contain one byte and perform the

following functions.

To write data to one of the device data registers or read

data from it, the address pointer register must be set, so

the correct data register is addressed, then data can be

written into that register or read from it. The first byte

of a write operation always contains an address stored in

the address pointer register. If data is to be written to the

device, the write operation contains a second data byte

that is written to the register selected by the address

pointer register (see Figure 18).

The device address is sent over the bus followed by the

R/W bit being set to 0. This is followed by two data bytes.

The first data byte is the address of the internal data

pointer register. The second data byte is the data to be

written to the internal data register.

On PCs and servers, control of the ADT7476 is carried out using

the SMBus. The ADT7476 is connected to this bus as a slave

device, under the control of a master controller, which is usually

(but not necessarily) the ICH.

The ADT7476 has three 7-bit serial bus addresses. The R/W bit

must be added to get the 8-bit address (that is, 01011100 or

0x5C). Data is sent over the serial bus in sequences of nine clock

pulses: eight bits of data followed by an acknowledge bit from the

slave device. Transitions on the data line must occur during the

low period of the clock signal and remain stable during the high

period, because a low-to-high transition when the clock is high

might be interpreted as a stop signal. The number of data bytes

transmitted over the serial bus in a single read or write opera-

tion is limited only by what the master and slave devices

can handle.

When reading data from a register, there are two possibilities:

• If the ADT7476 address pointer register value is unknown,

or not the desired value, it must first be set to the correct

value before data can be read from the desired data

ADT7476 as before, but only the data byte containing the

A read operation is then performed consisting of the serial

bus address, R/W bit set to 1, followed by the data byte

read from the data register (see Figure 20.)

• If the address pointer register is already at the desired

address, data can be read from the corresponding data

(see Figure 20).

R/W

SCL

SDA 10

11A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

ACK. BY

ADT7476

START BY

MASTER

ACK. BY

ADT7476

D7 D6 D5 D4 D3 D2 D1 D0

ACK. BY

ADT7476

STOP BY

MASTER

SCL (CONTINUED)

SDA (CONTINUED)

FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

ADDRESS POINTER REGISTER BYTE

FRAME 3

DATA BYTE

05382-019

Figure 18. Writing a Register Address to the Address Pointer Register, then Writing Data to the Selected Register

ADT7476

Rev. A | Page 15 of 72

R/W

SCL

11A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

ACK. BY

ADT7476

STOP BY

MASTER

START BY

MASTER FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

ADDRESS POINTER REGISTER BYTE

119

ACK. BY

ADT7476

05382-020

Figure 19. Writing to the Address Pointer Register Only

R/W

SCL

SDA 10 11A1 A0 D7 D6 D5 D4 D3 D2 D1 D0

NO ACK. BY

MASTER

STOP BY

MASTER

START BY

MASTER FRAME 1

SERIAL BUS ADDRESS BYTE

FRAME 2

DATA BYTE FROM ADT7476

119

ACK. BY

ADT7476

05382-021

Figure 20. Reading Data from a Previously Selected Register

It is possible to read a data byte from a data register without

first writing to the address pointer register, if the address

pointer register is already at the correct value. However, it is

not possible to write data to a register without writing to the

address pointer register, because the first data byte of a write

is always written to the address pointer register.

In addition to supporting the send byte and receive byte

protocols, the ADT7476 also supports the read byte protocol.

(See System Management Bus Specifications Rev. 2 for

more information; this document is available from Intel.)

If several read or write operations must be performed in

succession, the master can send a repeat start condition

instead of a stop condition to begin a new operation.

WRITE OPERATIONS

The SMBus specification defines several protocols for different

types of read and write operations. The ones used in the

ADT7476 are discussed below. The following abbreviations

are used in the diagrams:

S – START

P – STOP

R – READ

W – WRITE

A – ACKNOWLEDGE

A – NO ACKNOWLEDGE

The ADT7476 uses the following SMBus write protocols.

Send Byte

In this operation, the master device sends a single command

byte to a slave device, as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by

the write bit (active low).

3. The addressed slave device asserts ACK on SDA.

4. The master sends a command code.

5. The slave asserts ACK on SDA.

6. The master asserts a stop condition on SDA, and the

transaction ends.

For the ADT7476, the send byte protocol is used to write a

from the same address. This operation is illustrated in Figure 21.

05382-022

SLAVE

ADDRESS WASA

ADDRESS

23154

Figure 21. Setting a Register Address for Subsequent Read

If the master is required to read data from the register imme-

diately after setting up the address, it can assert a repeat start

condition immediately after the final ACK and carry out a

single-byte read without asserting an intermediate stop

condition.

ADT7476

Rev. A | Page 16 of 72

Write Byte

In this operation, the master device sends a command byte

and one data byte to the slave device, as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by

the write bit (active low).

3. The addressed slave device asserts ACK on SDA.

4. The master sends a command code.

5. The slave asserts ACK on SDA.

6. The master sends a data byte.

7. The slave asserts ACK on SDA.

8. The master asserts a stop condition on SDA,

and the transaction ends.

This operation is illustrated in Figure 22.

05382-023

SLAVE

ADDRESS W A DATASA

ADDRESS

23154

678

Figure 22. Single-Byte Write to a Register

READ OPERATIONS

The ADT7476 uses the following SMBus read protocols.

Receive Byte

This operation is useful when repeatedly reading a single

operation, the master device receives a single byte from a

slave device, as follows:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the

read bit (high).

3. The addressed slave device asserts ACK on SDA.

4. The master receives a data byte.

5. The master asserts NO ACK on SDA.

6. The master asserts a stop condition on SDA, and the

transaction ends.

In the ADT7476, the receive byte protocol is used to read a

single byte of data from a register whose address has previously

been set by a send byte or write byte operation. This operation

is illustrated in Figure 23.

05382-024

SLAVE

ADDRESS DATAARSA

24315

Figure 23. Single-Byte Read from a Register

Alert Response Address

Alert response address (ARA) is a feature of SMBus devices that

allows an interrupting device to identify itself to the host when

multiple devices exist on the same bus.

The SMBALERT output can be used as either an interrupt

output or an SMBALERT. One or more outputs can be con-

nected to a common SMBALERT line connected to the master.

If a device’s SMBALERT line goes low, the following procedure

occurs:

1. SMBALERT is pulled low.

2. The master initiates a read operation and sends the alert

response address (ARA = 0001 100). This is a general call

address that must not be used as a specific device address.

3. The device whose SMBALERT output is low responds to

the alert response address, and the master reads its device

address. The address of this device is now known and can

be interrogated in the usual way.

4. If more than one device’s SMBALERT output is low, the

one with the lowest device address has priority in accor-

dance with normal SMBus arbitration.

5. Once the ADT7476 has responded to the alert response

address, the master must read the status registers, and

the SMBALERT is cleared only if the error condition

is gone.

SMBus TIMEOUT

The ADT7476 includes an SMBus timeout feature. If there is

no SMBus activity for 35 ms, the ADT7476 assumes the bus

is locked and releases the bus. This prevents the device from

locking or holding the SMBus expecting data. Some SMBus

controllers cannot handle the SMBus timeout feature, so it

can be disabled.

Configuration Register 1 (0x40)

Bit 6 TODIS = 0, SMBus timeout enabled (default)

Bit 6 TODIS = 1, SMBus timeout disabled

VIRUS PROTECTION

To prevent rogue programs or viruses from accessing critical

ADT7476 register settings, the lock bit can be set. Setting Bit 1

of Configuration Register 1 (0x40) sets the lock bit and locks

critical registers. In this mode, certain registers can no longer be

written to until the ADT7476 is powered down and powered up

again. For more information on which registers are locked, see

the Register Tables section.

ADT7476

Rev. A | Page 17 of 72

VOLTAGE MEASUREMENT INPUT

The ADT7476 has four external voltage measurement channels.

It can also measure its own supply voltage, VCC. Pin 20 to Pin 23

can measure 5 V, 12 V, and 2.5 V supplies, and the processor

core voltage VCCP (0 V to 3 V input). The VCC supply voltage

measurement is carried out through the VCC pin (Pin 4). The

2.5 V input can be used to monitor a chipset supply voltage in

computer systems.

ANALOG-TO-DIGITAL CONVERTER

All analog inputs are multiplexed into the on-chip, successive-

approximation, analog-to-digital converter. This has a

resolution of 10 bits. The basic input range is 0 V to 2.25 V, but

the inputs have built-in attenuators to allow measurement of

2.5 V, 3.3 V, 5 V, 12 V, and the processor core voltage VCCP

without any external components. To allow the tolerance of

these supply voltages, the ADC produces an output of 3/4 full

scale (768 dec or 300 hex) for the nominal input voltage, and so

has adequate headroom to deal with overvoltages.

INPUT CIRCUITRY

The internal structure for the analog inputs is shown in

Figure 24. The input circuit consists of an input protection

diode, an attenuator, plus a capacitor to form a first-order low-

pass filter that gives input immunity to high frequency noise.

CCP

17.5kΩ

52.5kΩ35pF

45kΩ

94kΩ30pF

68kΩ

71kΩ30pF

93kΩ

47kΩ30pF

12V

120k

Ω

20kΩ30pF

5382-025

MUX

Figure 24. Structure of Analog Inputs

VOLTAGE MEASUREMENT REGISTERS

VOLTAGE LIMIT REGISTERS

Associated with each voltage measurement channel is a high

and low limit register. Exceeding the programmed high or low

limit causes the appropriate status bit to be set. Exceeding either

limit can also generate SMBALERT interrupts.

Table 9 shows the input ranges of the analog inputs and output

codes of the 10-bit ADC.

When the ADC is running, it samples and converts a voltage

input in 0.7 ms and averages 16 conversions to reduce noise;

a measurement takes nominally 11 ms.

EXTENDED RESOLUTION REGISTERS

Voltage measurements can be made with higher accuracy

using the extended resolution registers (0x76 and 0x77).

Whenever the extended resolution registers are read, the

corresponding data in the voltage measurement registers

(0x20 to 0x24) is locked until their data is read. That is,

if extended resolution is required, the extended resolution

the appropriate voltage measurement register.

ADDITIONAL ADC FUNCTIONS FOR VOLTAGE

MEASUREMENTS

A number of other functions are available on the ADT7476

to offer the system designer increased flexibility.

Turn-Off Averaging

For each voltage/temperature measurement read from a value

the results averaged, before being placed into the value reg-

ister. When faster conversions are needed, setting Bit 4 of

Configuration Register 2 (0x73) turns averaging off.

This effectively gives a reading 16 times faster, but the reading

can be noisier. The default round-robin cycle time takes 146.5 ms.

ADT7476

Rev. A | Page 18 of 72

Table 6. Conversion Time with Averaging Disabled

Channel Measurement Time (ms)

Voltage Channels 0.7

Remote Temperature 1 7

Remote Temperature 2 7

Local Temperature 1.3

When Bit 7 of Configuration Register 6 (0x10) is set, the default

round-robin cycle time increases to 240 ms.

Bypass All Voltage Input Attenuators

Setting Bit 5 of Configuration Register 2 (0x73) removes the

attenuation circuitry from the 2.5 V, VCCP, VCC, 5 V, and 12 V

inputs. This allows the user to directly connect external sensors

or rescale the analog voltage measurement inputs for other

applications. The input range of the ADC without the

attenuators is 0 V to 2.25 V.

Bypass Individual Voltage Input Attenuators

Bits [7:4] of Configuration Register 4 (0x7D) can be used

to bypass individual voltage channel attenuators.

Table 7. Bypassing Individual Voltage Input Attenuators

Using Configuration Register 4 (0x7D)

Bit Channel Attenuated

4 Bypass 2.5 V attenuator

5 Bypass VCCP attenuator

6 Bypass 5 V attenuator

7 Bypass 12 V attenuator

Configuration Register 2 (0x73)

Bit 4 = 1, averaging off.

Bit 5 = 1, bypass input attenuators.

Bit 6 = 1, single-channel convert mode.

TACH1 Minimum High Byte Register (0x55)

Bits [7:5] select ADC channel for single-channel convert mode.

Single-Channel ADC Conversion

While single-channel mode is intended as a test mode that

can be used to increase sampling times for a specific channel,

therefore helping to analyze that channel’s performance in

greater detail, it can also have other applications.

Setting Bit 6 of Configuration Register 2 (0x73) places the

ADT7476 into single-channel ADC conversion mode. In this

mode, the ADT7476 can read a single voltage channel only.

The selected voltage input is read every 0.7 ms. The appropriate

ADC channel is selected by writing to Bits [7:5] of the TACH1

minimum high byte register (0x55).

Table 8. Programming Single-Channel ADC Mode

000 2.5 V

001 VCCP

010 VCC

011 5 V

100 12 V

101 Remote 1 temperature

110 Local temperature

111 Remote 2 temperature

1 In the process of configuring single-channel ADC conversion mode, the TACH1 minimum high byte is also changed, possibly trading off TACH1 minimum high byte

functionality with single-channel mode functionality.

ADT7476

Rev. A | Page 19 of 72

Table 9. 10-Bit A/D Output Code vs. VIN

Input Voltage A/D Output

12 VIN 5 VIN VCC (3.3 VIN) 2.5 VIN VCCP Decimal Binary (10 Bits)

<0.0156 <0.0065 <0.0042 <0.0032 <0.00293 0 00000000 00

0.0156 to 0.0312 0.0065 to 0.0130 0.0042 to 0.0085 0.0032 to 0.0065 0.0293 to 0.0058 1 00000000 01

0.0312 to 0.0469 0.0130 to 0.0195 0.0085 to 0.0128 0.0065 to 0.0097 0.0058 to 0.0087 2 00000000 10

0.0469 to 0.0625 0.0195 to 0.0260 0.0128 to 0.0171 0.0097 to 0.0130 0.0087 to 0.0117 3 00000000 11

0.0625 to 0.0781 0.0260 to 0.0325 0.0171 to 0.0214 0.0130 to 0.0162 0.0117 to 0.0146 4 00000001 00

0.0781 to 0.0937 0.0325 to 0.0390 0.0214 to 0.0257 0.0162 to 0.0195 0.0146 to 0.0175 5 00000001 01

0.0937 to 0.1093 0.0390 to 0.0455 0.0257 to 0.0300 0.0195 to 0.0227 0.0175 to 0.0205 6 00000001 10

0.1093 to 0.1250 0.0455 to 0.0521 0.0300 to 0.0343 0.0227 to 0.0260 0.0205 to 0.0234 7 00000001 11

0.1250 to 0.14060 0.0521 to 0.0586 0.0343 to 0.0386 0.0260 to 0.0292 0.0234 to 0.0263 8 00000010 00

•

4.0000 to 4.0156 1.6675 to 1.6740 1.1000 to 1.1042 0.8325 to 0.8357 0.7500 to 0.7529 256 (¼ scale) 01000000 00

•

8.0000 to 8.0156 3.3300 to 3.3415 2.2000 to 2.2042 1.6650 to 1.6682 1.5000 to 1.5029 512 (½ scale) 10000000 00

•

12.0000 to 12.0156 5.0025 to 5.0090 3.3000 to 3.3042 2.4975 to 2.5007 2.2500 to 2.2529 768 (¾ scale) 11000000 00

•

15.8281 to 15.8437 6.5983 to 6.6048 4.3527 to 4.3570 3.2942 to 3.2974 2.9677 to 2.9707 1013 11111101 01

15.8437 to 15.8593 6.6048 to 6.6113 4.3570 to 4.3613 3.2974 to 3.3007 2.9707 to 2.9736 1014 11111101 10

15.8593 to 15.8750 6.6113 to 6.6178 4.3613 to 4.3656 3.3007 to 3.3039 2.9736 to 2.9765 1015 11111101 11

15.8750 to 15.8906 6.6178 to 6.6244 4.3656 to 4.3699 3.3039 to 3.3072 2.9765 to 2.9794 1016 11111110 00

15.8906 to 15.9062 6.6244 to 6.6309 4.3699 to 4.3742 3.3072 to 3.3104 2.9794 to 2.9824 1017 11111110 01

15.9062 to 15.9218 6.6309 to 6.6374 4.3742 to 4.3785 3.3104 to 3.3137 2.9824 to 2.9853 1018 11111110 10

15.9218 to 15.9375 6.6374 to 6.4390 4.3785 to 4.3828 3.3137 to 3.3169 2.9853 to 2.9882 1019 11111110 11

15.9375 to 15.9531 6.6439 to 6.6504 4.3828 to 4.3871 3.3169 to 3.3202 2.9882 to 2.9912 1020 11111111 00

15.9531 to 15.9687 6.6504 to 6.6569 4.3871 to 4.3914 3.3202 to 3.3234 2.9912 to 2.9941 1021 11111111 01

15.9687 to 15.9843 6.6569 to 6.6634 4.3914 to 4.3957 3.3234 to 3.3267 2.9941 to 2.9970 1022 11111111 10

>15.9843 >6.6634 >4.3957 >3.3267 >2.9970 1023 11111111 11

ADT7476

Rev. A | Page 20 of 72

VID CODE MONITORING

The ADT7476 has five dedicated voltage ID (VID code) inputs.

These are digital inputs that can be read back through the VID

being used in the system. Five VID code inputs support VRM9.x

solutions. In addition, Pin 21 (12 V input) can be reconfigured as

a sixth VID input to satisfy future VRM requirements.

VID Code Register (0x43)

Bit 0 = VID0, reflects logic state of Pin 5.

Bit 1 = VID1, reflects logic state of Pin 6.

Bit 2 = VID2, reflects logic state of Pin 7.

Bit 3 = VID3, reflects logic state of Pin 8.

Bit 4 = VID4, reflects logic state of Pin 19.

Bit 5 = VID5, reconfigurable 12 V input. This bit reads 0 when

Pin 21 is configured as the 12 V input. This bit reflects the logic

state of Pin 21 when the pin is configured as VID5.

VID CODE INPUT THRESHOLD VOLTAGE

The switching threshold for the VID code inputs is approxi-

mately 1 V. To enable future compatibility, it is possible to

reduce the VID code input threshold to 0.6 V. Bit 6 (THLD) of

the VID register (0x43) controls the VID input threshold

voltage.

VID Code Register (0x43)

Bit 6 THLD = 0, VID switching threshold = 1 V,

VOL < 0.8 V, VIH > 1.7 V, VMAX = 3.3 V.

Bit 6 THLD = 1, VID switching threshold = 0.6 V,

VOL < 0.4 V, VIH > 0.8 V, VMAX = 3.3 V.

Bit 7 VIDSEL = 0, Pin 21 functions as a 12 V measurement

input. Software can read this bit to determine there are five

VID inputs being monitored. Bit 5 of Register 0x43 (VID5)

always reads back 0. Bit 0 of Status Register 2 (0x42) reflects

12 V out-of-limit measurements.

Bit 7 VIDSEL = 1, Pin 21 functions as the sixth VID code input

(VID5). Software can read this bit to determine there are six

VID inputs being monitored. Bit 5 of Register 0x43 reflects the

logic state of Pin 21. Bit 0 of Status Register 2 (0x42) reflects

VID code changes.

Reconfiguring Pin 21 as VID5 Input

Pin 21 can be reconfigured as a sixth VID code input (VID5)

for VRM10 compatible systems. Because the pin is configured

as VID5, it is not possible to monitor a 12 V supply.

Bit 7 of the VID configuration register (0x43) determines the

function of Pin 21. System or BIOS software can read the state

of Bit 7 to determine whether the system is designed to monitor

12 V or is monitoring a sixth VID input.

VID CODE CHANGE DETECT FUNCTION

The ADT7476 has a VID code change detect function. When

Pin 21 is configured as the VID5 input, VID code changes are

detected and reported back by the ADT7476. Bit 0 of Status

when set. The VID code change bit is set when the logic states

on the VID inputs are different than they were 11 µs previously.

The change of VID code is used to generate an SMBALERT

interrupt. If an SMBALERT interrupt is not required, Bit 0 of

Interrupt Mask Register 2 (0x75), when set, prevents

SMBALERTs from occurring on VID code changes.

Interrupt Status Register 2 (0x42)

Bit 0 12V/VC = 0, if Pin 21 is configured as VID5, Logic 0

denotes no change in VID code within the last 11 µs.

Bit 0 12V/VC = 1, if Pin 21 is configured as VID5, Logic 1

means that a change has occurred on the VID code inputs

within the last 11 µs. An SMBALERT is generated if this func-

tion is enabled.

PROGRAMMING THE GPIOS

The ADT7476 follows an upgrade path from the ADM1027 to

ADT7476. In order to maintain consistency between versions,

it is necessary to omit references to GPIO5. As a result, there

are six GPIOs as follows: GPIO0, GPIO1, GPIO2, GPIO3,

GPIO4, and GPIO6.

Setting Bit 4 of Configuration Register 5 (0x7C) to 1 enables

GPIO functionality. This turns all pins configured as VID

inputs into general-purpose outputs. Writing to the corre-

sponding VID bit in the VID register (0x43) sets the polarity

for the corresponding GPIO. GPIO6 can be programmed

independently as an input/output/etc., using Bits [3:2] of

Configuration Register 5 (0x7C).

TEMPERATURE MEASUREMENT METHOD

Local Temperature Measurement

The ADT7476 contains an on-chip band gap temperature

sensor whose output is digitized by the on-chip, 10-bit ADC.

The 8-bit MSB temperature data is stored in the temperature

registers (Register 0x25, Register 0x26, and Register 0x27).

Because both positive and negative temperatures can be

measured, the temperature data is stored in Offset 64 format or

twos complement format, as shown in Table 1 0 and Table 11.

ADT7476

Rev. A | Page 21 of 72

Theoretically, the temperature sensor and ADC can measure

temperatures from −63°C to +127°C (or −61°C to +191°C in the

extended temperature range) with a resolution of 0.25°C.

However, this exceeds the operating temperature range of the

device, so local temperature measurements outside the

ADT7476 operating temperature range are not possible.

Remote Temperature Measurement

The ADT7476 can measure the temperature of two remote

diode sensors or diode-connected transistors connected to

Pin 17 and Pin 18, or Pin 15 and Pin 16.

The forward voltage of a diode or diode-connected transistor

operated at a constant current exhibits a negative temperature

coefficient of about −2 mV/°C. Unfortunately, the absolute

value of VBE varies from device to device and individual

calibration is required to null this out, so the technique is

unsuitable for mass production. The technique used in the

ADT7476 is to measure the change in VBE when the device

is operated at two different currents.

This is given by

VBE = KT/q × 1n(N)

where:

K is Boltzmann’s constant.

q is the charge on the carrier.

T is the absolute temperature in Kelvin.

N is the ratio of the two currents.

Figure 25 shows the input signal conditioning used to measure

the output of a remote temperature sensor. This figure shows

the external sensor as a substrate transistor, provided for

temperature monitoring on some microprocessors. It could

also be a discrete transistor such as a 2N3904/2N3906.

05382-026

D+

BIAS

DIODE

TO ADC

OUT+

OUT–

REMOTE

SENSING

TRANSISTOR D–

THERMDA

THERMDC

IN × I I

BIAS

LOW-PASS FILTER

= 65kHz

CPU

Figure 25. Signal Conditioning for Remote Diode Temperature Sensors

If a discrete transistor is used, the collector is not grounded

and should be linked to the base. If a PNP transistor is used,

the base is connected to the D– input and the emitter to the

D+ input. If an NPN transistor is used, the emitter is con-

nected to the D– input and the base to the D+ input. Figure 26

and Figure 27 show how to connect the ADT7476 to an NPN

or PNP transistor for temperature measurement. To prevent

ground noise from interfering with the measurement, the more

negative terminal of the sensor is not referenced to ground, but

is biased above ground by an internal diode at the D– input.

To measure VBE, the sensor is switched between operating

currents of I and N × I. The resulting waveform is passed

through a 65 kHz low-pass filter to remove noise and to a

chopper-stabilized amplifier that performs the functions of

amplification and rectification of the waveform to produce a

dc voltage proportional to VBE. This voltage is measured by

the ADC to give a temperature output in 10-bit, twos comple-

ment format. To further reduce the effects of noise, digital

filtering is performed by averaging the results of 16

measurement cycles.

A remote temperature measurement takes nominally 38 ms.

The results of remote temperature measurements are stored in

10-bit, twos complement format, as illustrated in Table 10. The

extra resolution for the temperature measurements is held in

the Extended Resolution Register 2 (0x77). This gives

temperature readings with a resolution of 0.25°C.

Noise Filtering

For temperature sensors operating in noisy environments,

previous practice was to place a capacitor across the D+ pin and

the D− pin to help combat the effects of noise. However, large

capacitances affect the accuracy of the temperature measurement,

leading to a recommended maximum capacitor value of 1000 pF.

This capacitor reduces the noise, but does not eliminate it, which

makes it difficult to use of the sensor in a very noisy environment.

In most cases, a capacitor is not required as differential inputs

by their very nature have a high immunity to noise.

N3904

NPN

ADT7476

D+

D–

05382-027

Figure 26. Measuring Temperature Using an NPN Transistor

N3906

PNP

ADT7476

D+

D–

05382-028

Figure 27. Measuring Temperature Using a PNP Transistor

ADT7476

Rev. A | Page 22 of 72

FACTORS AFFECTING DIODE ACCURACY

Remote Sensing Diode

The ADT7476 is designed to work with either substrate

transistors built into processors or with discrete transistors.

Substrate transistors are generally PNP types with the collector

connected to the substrate. Discrete types can be either PNP

or NPN transistors connected as a diode (base-shorted to the

collector). If an NPN transistor is used, the collector and base

are connected to D+ and the emitter to D−. If a PNP transistor

is used, the collector and base are connected to D− and the

emitter is connected to D+.

To reduce the error due to variations in both substrate and

discrete transistors, a number of factors should be taken

into consideration:

• The ideality factor, nf, of the transistor is a measure of the

deviation of the thermal diode from ideal behavior. The

ADT7476 is trimmed for an nf value of 1.008. Use the

following equation to calculate the error introduced at a

temperature T (°C), when using a transistor whose nf

does not equal 1.008. See the processor data sheet for

the nf values.

ΔT = (nf − 1.008) × (273.15 K + T)

To factor this in, the user can write the ∆T value to the

offset register. The ADT7476 then automatically adds it

to or subtracts it from the temperature measurement.

• Some CPU manufacturers specify the high and low current

levels of the substrate transistors. The high current level of

the ADT7476, IHIGH, is 180 µA and the low level current,

ILOW, is 11 µA. If the ADT7476 current levels do not match

the current levels specified by the CPU manufacturer, it

might be necessary to remove an offset. The CPU’s data

sheet advises whether this offset needs to be removed and

how to calculate it. This offset can be programmed to the

offset register. It is important to note that, if more than one

offset must be considered, the algebraic sum of these

offsets must be programmed to the offset register.

If a discrete transistor is used with the ADT7476, the best

accuracy is obtained by choosing devices according to the

following criteria:

• Base-emitter voltage greater than 0.25 V at 11 µA, at

the highest operating temperature.

• Base-emitter voltage less than 0.95 V at 180 µA, at the lowest

operating temperature.

• Base resistance less than 100 Ω.

• Small variation in hFE (approximately 50 to 150) that indicates

tight control of VBE characteristics.

Transistors, such as 2N3904, 2N3906, or equivalents in SOT-23

packages, are suitable devices to use.

Table 10. Twos Complement Temperature Data Format

Temperature Digital Output (10-Bit)1

–128°C 1000 0000 00 (diode fault)

–50°C 1100 1110 00

–25°C 1110 0111 00

–10°C 1111 0110 00

0°C 0000 0000 00

10.25°C 0000 1010 01

25.5°C 0001 1001 10

50.75°C 0011 0010 11

75°C 0100 1011 00

100°C 0110 0100 00

125°C 0111 1101 00

127°C 0111 1111 00

1 Bold numbers denote 2 LSBs of measurement in Extended Resolution

Table 11. Extended Range, Temperature Data Format

Temperature Digital Output (10-Bit)1

–64°C 0000 0000 00 (diode fault)

–1°C 0011 1111 00

0°C 0100 0000 00

1°C 0100 0001 00

10°C 0100 1010 00

25°C 0101 1001 00

50°C 0111 0010 00

75°C 1000 1001 00

100°C 1010 0100 00

125°C 1011 1101 00

191°C 1111 1111 00

1 Bold numbers denote 2 LSBs of measurement in Extended Resolution

Nulling Out Temperature Errors

As CPUs run faster, it is more difficult to avoid high frequency

clocks when routing the D+/D– traces around a system board.

Even when recommended layout guidelines are followed, some

temperature errors can still be attributed to noise coupled onto

the D+/D– lines. Constant high frequency noise usually

attenuates, or increases, temperature measurements by a linear,

constant value.

The ADT7476 has temperature offset registers at Register 0x70

and Register 0x72 for the Remote 1 and Remote 2 temperature

channels. By doing a one-time calibration of the system, the

user can determine the offset caused by system board noise

and null it out using the offset registers. The offset registers

automatically add a twos complement 8-bit reading to every

temperature measurement.

ADT7476

Rev. A | Page 23 of 72

Changing Bit 1 of Configuration Register 5 (0x7C) changes the

resolution and therefore the range of the temperature offset as

either having a range of –63°C to +127°C with a resolution of

1°C or having a range of −63°C to +64°C with a resolution of

0.5°C. This temperature offset can be used to compensate for

linear temperature errors introduced by noise.

Temperature Offset Registers

ADT7463/ADT7476 Backwards Compatible Mode

By setting Bit 0 of Configuration Register 5 (0x7C), all tempera-

ture measurements are stored in the zone temperature value

registers (Register 0x25, Register 0x26, and Register 0x27) in

twos complement in the range −63°C to +127°C. The

temperature limits must be reprogrammed in twos

complement.

If a twos complement temperature below −63°C is entered, the

temperature is clamped to −63°C. In this mode, the diode fault

condition remains −128°C = 1000 0000, while in the extended

temperature range (−63°C to +191°C), the fault condition is

represented by −64°C = 0000 0000.

Temperature Measurement Registers

Bits [7:6] TDM2, Remote 2 temperature LSBs

Bits [5:4] LTMP, Local temperature LSBs

Bits [3:2] TDM1, Remote 1 temperature LSBs

Temperature Measurement Limit Registers

Associated with each temperature measurement channel are high

and low limit registers. Exceeding the programmed high or low

limit causes the appropriate status bit to be set. Exceeding either

limit can also generate SMBALERT interrupts (depending on

the way the interrupt mask register is programmed and assuming

that SMBALERT is set as an output on the appropriate pin).

Reading Temperature from the ADT7476

It is important to note that temperature can be read from the

ADT7476 as an 8-bit value (with 1°C resolution) or as a 10-bit

value (with 0.25°C resolution). If only 1°C resolution is re-

quired, the temperature readings can be read back at any time

and in no particular order.

If the 10-bit measurement is required, this involves a 2-register

read for each measurement. The extended resolution register

(0x77) should be read first. This causes all temperature reading

registers to be frozen until all temperature reading registers

have been read from. This prevents an MSB reading from being

updated while its two LSBs are being read and vice versa.

ADDITIONAL ADC FUNCTIONS FOR

TEMPERATURE MEASUREMENT

A number of other functions are available on the ADT7476 to

offer the system designer increased flexibility.

Turn-Off Averaging

For each temperature measurement read from a value register,

16 readings have actually been made internally, and the results

averaged, before being placed into the value register. Sometimes

it is necessary to take a very fast measurement. Setting Bit 4 of

Configuration Register 2 (0x73) turns averaging off. The default

round-robin cycle time takes 146.5 ms.

Table 12. Conversion Time with Averaging Disabled

Channel Measurement Time (ms)

Voltage Channels 0.7

Remote Temperature 1 7

Remote Temperature 2 7

Local Temperature 1.3

When Bit 7 of Configuration Register 6 (0x10) is set, the default

round-robin cycle time increases to 240 ms.

Table 13. Conversion Time with Averaging Enabled

Channel Measurement Time (ms)

Voltage Channels 11

Remote Temperature 39

Local Temperature 12

ADT7476

Rev. A | Page 24 of 72

Single-Channel ADC Conversions

Setting Bit 6 of Configuration Register 2 (0x73) places the

ADT7476 into single-channel ADC conversion mode. In this

mode, the ADT7476 can be made to read a single temperature

channel only. The appropriate ADC channel is selected by

writing to Bits [7:5] of the TACH1 minimum high byte

Table 14. Programming Single-Channel ADC Mode for

Temperatures

101 Remote 1 temperature

110 Local temperature

111 Remote 2 temperature

Configuration Register 2 (0x73)

Bit 4 = 1, averaging off.

Bit 6 = 1, single-channel convert mode.

TACH1 Minimum High Byte (0x55)

Bits [7:5] selects ADC channel for single-channel convert mode.

Overtemperature Events

Overtemperature events on any of the temperature channels can

be detected and dealt with automatically in automatic fan speed

control mode. Register 0x6A to Register 0x6C are the THERM

temperature limits. When a temperature exceeds its THERM

temperature limit, all PWM outputs run at the maximum

PWM duty cycle (Register 0x38, Register 0x39, and Register

0x3A). This effectively runs the fans at the fastest allowed speed.

The fans run at this speed until the temperature drops below

THERM minus hysteresis. This can be disabled by setting the

boost bit in Configuration Register 3, Bit 2 (Register 0x78). The

hysteresis value for the THERM temperature limit is the value

programmed into the hysteresis registers (Register 0x6D and

FANS

TEMPERATURE

100%

HYSTERESIS (°C)

THERM LIMIT

05382-029

Figure 28. THERM Temperature Limit Operation

THERM can be disabled on specific temperature channels using

Bits [7:5] of Configuration Register 5 (0x7C). THERM can also

be disabled by:

• In Offset 64 mode, writing −64°C to the appropriate

THERM temperature limit.

• In twos complement mode, writing −128°C to the

appropriate THERM temperature limit.

ADT7476

Rev. A | Page 25 of 72

LIMITS, STATUS REGISTERS, AND INTERRUPTS

LIMIT VALUES

Associated with each measurement channel on the ADT7476

are high and low limits. These can form the basis of system

status monitoring. A status bit can be set for any out-of-limit

condition and is detected by polling the device. Alternatively,

SMBALERT interrupts can be generated to flag out-of-limit

conditions to a processor or microcontroller.

8-Bit Limits

The following is a list of 8-bit limits on the ADT7476.

Volt age L imit Re gi s ters

Temperature Limit Registers

THERM Limit Register

16-Bit Limits

The fan TACH measurements are 16-bit results. The fan TACH

limits are also 16 bits, consisting of a high byte and low byte.

Because fans running under speed or stalled are normally the

only conditions of interest, only high limits exist for fan TACHs.

Because the fan TACH period is actually being measured,

exceeding the limit indicates a slow or stalled fan.

Fan Limit Registers

Out-of-Limit Comparisons

Once all limits have been programmed, the ADT7476 can be

enabled for monitoring. The ADT7476 measures all voltage and

temperature measurements in round-robin format and sets the

appropriate status bit for out-of-limit conditions. TACH meas-

urements are not part of this round-robin cycle. Comparisons

are done differently depending on whether the measured value

is being compared to a high or low limit.

High Limit > Comparison Performed

Low Limit ≤ Comparison Performed

Voltage and temperature channels use a window comparator

for error detecting and, therefore, have high and low limits.

Fan speed measurements use only a low limit. This fan limit is

needed only in manual fan control mode.

Analog Monitoring Cycle Time

The analog monitoring cycle begins when a 1 is written to the

start bit (Bit 0) of Configuration Register 1 (0x40). The ADC

measures each analog input in turn, and, as each measurement

is completed, the result is automatically stored in the

appropriate value register. This round-robin monitoring

cycle continues unless disabled by writing a 0 to Bit 0 of

Configuration Register 1.

As the ADC is normally left to free-run in this manner, the

time taken to monitor all the analog inputs is normally not of

interest, because the most recently measured value of any input

can be read out at any time.

ADT7476

Rev. A | Page 26 of 72

For applications where the monitoring cycle time is important,

it can be calculated easily.

The total number of channels measured is

• Four dedicated supply voltage inputs

• Supply voltage (VCC pin)

• Local temperature

• Two remote temperatures

As mentioned previously, the ADC performs round-robin

conversions and takes 11 ms for each voltage measurement,

12 ms for a local temperature reading, and 39 ms for each

remote temperature reading. The total monitoring cycle time

for averaged voltage and temperature monitoring is, therefore,

nominally

(5 × 11) + 12 + (2 × 39) = 145 ms

Fan TACH measurements are made in parallel and are not

synchronized with the analog measurements in any way.

STATUS REGISTERS

The results of limit comparisons are stored in Status Register 1

and Status Register 2. The status register bit for each channel

reflects the status of the last measurement and limit comparison

on that channel. If a measurement is within limits, the corre-

sponding status register bit is cleared to 0. If the measurement

is out-of-limits, the corresponding status register bit is set to 1.

The state of the various measurement channels can be polled by

reading the status registers over the serial bus. In Bit 7 (OOL) of

Status Register 1 (0x41), 1 means an out-of-limit event has been

flagged in Status Register 2. This means the user also needs to

read Status Register 2. Alternatively, Pin 10 or Pin 14 can be

configured as an SMBALERT output. This hard interrupt

automatically notifies the system supervisor of an out-of-limit

condition. Reading the status registers clears the appropriate

status bit as long as the error condition that caused the interrupt

has cleared. Status register bits are sticky. Whenever a status bit

is set, indicating an out-of-limit condition, it remains set even

if the event that caused it has gone away (until read).

The only way to clear the status bit is to read the status register

after the event has gone. Interrupt status mask registers

(Register 0x74 and Register 0x75) allow individual interrupt

sources to be masked from causing an SMBALERT. However, if

one of these masked interrupt sources goes out-of-limit, its

associated status bit is set in the interrupt status registers.

Interrupt Status Register 1 (0x41)

Bit 7 (OOL) = 1, denotes a bit in Status Register 2 is set and

Status Register 2 should be read.

Bit 6 (R2T) = 1, Remote 2 temperature high or low limit has

been exceeded.

Bit 5 (LT) = 1, Local temperature high or low limit has been

exceeded.

Bit 4 (R1T) = 1, Remote 1 temperature high or low limit has

been exceeded.

Bit 3 (5 V) = 1, 5 V high or low limit has been exceeded.

Bit 2 (VCC) = 1, VCC high or low limit has been exceeded.

Bit 1 (VCCP) = 1, VCCP high or low limit has been exceeded.

Bit 0 (2.5 V) = 1, 2.5 V high or low limit has been exceeded. If

the 2.5 V input is configured as THERM, this bit represents the

status of THERM.

Interrupt Status Register 2 (0x42)

Bit 7 (D2 FAULT) = 1, indicates an open or short on D2+/D2–

inputs.

Bit 6 (D1 FAULT) = 1, indicates an open or short on D1+/D1–

inputs.

Bit 5 (F4P) = 1, indicates Fan 4 has dropped below minimum

speed. Alternatively, indicates that the THERM limit has been

exceeded, if the THERM function is used. Alternatively,

indicates the status of GPIO6.

Bit 4 (FAN3) = 1, indicates Fan 3 has dropped below

minimum speed.

Bit 3 (FAN2) = 1, indicates Fan 2 has dropped below

minimum speed.

Bit 2 (FAN1) = 1, indicates Fan 1 has dropped below

minimum speed.

Bit 1 (OVT) = 1, indicates a THERM overtemperature limit has

been exceeded.

Bit 0 (12V/VC) = 1, indicates a 12 V high or low limit has been

exceeded. If the VID code change function is used, this bit indi-

cates a change in VID code on the VID0 to VID5 inputs.

SMBALERT Interrupt Behavior

The ADT7476 can be polled for status, or an SMBALERT

interrupt can be generated for out-of-limit conditions. It is

important to note how the SMBALERT output and status

bits behave when writing interrupt handler software.

ADT7476

Rev. A | Page 27 of 72

STICKY

STATUS BIT

HIGH LIMIT

TEMPERATURE

CLEARED ON READ

(TEMP BELOW LIMIT)

TEMP BACK IN LIMIT

(STATUS BIT STAYS SET)

SMBALERT

5382-030

Figure 29. SMBALERT and Status Bit Behavior

Figure 29 shows how the SMBALERT output and sticky status

bits behave. Once a limit is exceeded, the corresponding status

bit is set to 1. The status bit remains set until the error condi-

tion subsides and the status register is read. The status bits

are referred to as sticky, because they remain set until read

by software. This ensures that an out-of-limit event cannot

be missed, if software is polling the device periodically.

Note: The SMBALERT output remains low for the entire

duration that a reading is out-of-limit and until the status

ware handles the interrupt.

Handling SMBALERT Interrupts

To prevent the system from being tied up servicing interrupts,

it is recommend to handle the SMBALERT interrupt as follows:

1. Detect the SMBALERT assertion.

2. Enter the interrupt handler.

3. Read the status registers to identify the interrupt source.

4. Mask the interrupt source by setting the appropriate mask

bit in the interrupt mask registers (0x74 and 0x75).

5. Take the appropriate action for a given interrupt source.

6. Exit the interrupt handler.

7. Periodically poll the status registers. If the interrupt status

bit has cleared, reset the corresponding interrupt mask bit

to 0. This causes the SMBALERT output and status bits to

behave as shown in Figure 30.

Masking Interrupt Sources

Interrupt Mask Register 1 and Interrupt Mask Register 2 are

located at Register 0x74 and Register 0x75. These allow

individual interrupt sources to be masked out to prevent

SMBALERT interrupts. Note: Masking an interrupt source

prevents only the SMBALERT output from being asserted; the

appropriate status bit is set normally.

STICKY

STATUS BIT

HIGH LIMIT

TEMPERATURE

CLEARED ON READ

(TEMP BELOW LIMIT)

TEMP BACK IN LIMIT

(STATUS BIT STAYS SET)

INTERRUPT

MASK BIT SET

SMBALERT

05382-031

INTERRUPT MASK BIT

CLEARED

(SMBALERT REARMED)

Figure 30. How Masking the Interrupt Source Affects SMBALERT Output

Interrupt Mask Register 1 (0x74)

Bit 7 (OOL) = 1, masks SMBALERT for any alert condition

flagged in Status Register 2.

Bit 6 (R2T) = 1, masks SMBALERT for Remote 2 temperature.

Bit 5 (LT) = 1, masks SMBALERT for local temperature.

Bit 4 (R1T) = 1, masks SMBALERT for Remote 1 temperature.

Bit 3 (5 V) = 1, masks SMBALERT for 5 V channel.

Bit 2 (VCC) = 1, masks SMBALERT for VCC channel.

Bit 1 (VCCP) = 1, masks SMBALERT for VCCP channel.

Bit 0 (2.5 V) = 1, masks SMBALERT for 2.5V/ THERM.

Interrupt Mask Register 2 (0x75)

Bit 7 (D2) = 1, masks SMBALERT for Diode 2 errors.

Bit 6 (D1) = 1, masks SMBALERT for Diode 1 errors.

Bit 5 (F4P) = 1, masks SMBALERT for Fan 4 failure.

If the TACH4 pin is being used as the THERM input, this bit

masks SMBALERT for a THERM event. If the TACH4 pin is

being used as GPIO6, setting this bit masks interrupts related

to GPIO6.

Bit 4 (FAN3) = 1, masks SMBALERT for Fan 3.

Bit 3 (FAN2) = 1, masks SMBALERT for Fan 2.

Bit 2 (FAN1) = 1, masks SMBALERT for Fan 1.

Bit 1 (OVT) = 1, masks SMBALERT for overtemperature

(exceeding THERM temperature limits).

Bit 0 (12V/VC) = 1, masks SMBALERT for 12 V channel or

for a VID code change, depending on the function used.

ADT7476

Rev. A | Page 28 of 72

Enabling the SMBALERT Interrupt Output

The SMBALERT interrupt function is disabled by default.

Pin 10 or Pin 14 can be reconfigured as an SMBALERT out-

put to signal out-of-limit conditions.

Table 15. Configuring Pin 10 as SMBALERT Output

Configuration Register 3 (0x78) [1] Pin 10 = SMBALERT

[0] Pin 10 = PWM2

Assigning THERM Functionality to a Pin

Pin 14 on the ADT7476 has four possible functions:

SMBALERT, THERM, GPIO6, and TACH4. The user

chooses the required functionality by setting Bit 0 and Bit 1

of Configuration Register 4 (0x7D).

If THERM is enabled, Configuration Register 3 (0x78), Bit 1,

the following occurs:

• Pin 22 becomes THERM.

• If Pin 14 is configured as THERM (Bit 0 and Bit 1 of

Configuration Register 4 at Address 0x7D), THERM is

enabled on this pin.

If THERM is not enabled, the following occurs:

• Pin 22 becomes a 2.5 V measurement input.

• If Pin 14 is configured as THERM, then THERM is

disabled on this pin.

Table 16. Configuring Pin 14

Bit 0 Bit 1 Function

0 0 TACH4

0 1 THERM

1 0 SMBALERT

1 1 GPIO6

THERM as an Input

When THERM is configured as an input, the user can time

assertions on the THERM pin. This can be useful for connect-

ing to the PROCHOT output of a CPU to gauge system

performance.

The user can also set up the ADT7476 so that, when the

THERM pin is driven low externally, the fans run at 100%. The

fans run at 100% for the duration of the time that the THERM

pin is pulled low. This is done by setting the BOOST bit (Bit 2)

in Configuration Register 3 (0x78) to 1. This works only if the

fan is already running, for example, in manual mode when the

current duty cycle is above Register 0x00, or in automatic mode

when the temperature is above TMIN.

If the temperature is below TMIN or if the duty cycle in manual

mode is set to Register 0x00, pulling the THERM low externally

has no effect. See Figure 31 for more information.

05382-032

THERM

MIN

THERM ASSERTED TO LOW AS AN INPUT:

FANS DO NOT GO TO 100%, BECAUSE

TEMPERATURE IS BELOW T

MIN

THERM ASSERTED TO LOW AS AN INPUT:

FANS DO NOT GO TO 100%, BECAUSE

TEMPERATURE IS ABOVE T

MIN

AND FANS

ARE ALREADY RUNNING.

Figure 31. Asserting THERM Low as an Input

in Automatic Fan Speed Control Mode

THERM TIMER

The ADT7476 has an internal timer to measure THERM

assertion time. For example, the THERM input can be

connected to the PROCHOT output of a Pentium 4 CPU

to measure system performance. The THERM input can also

be connected to the output of a trip point temperature sensor.

The timer is started on the assertion of the ADT7476 THERM

input and stopped when THERM is de-asserted. The timer

counts THERM times cumulatively, that is, the timer resumes

counting on the next THERM assertion. The THERM timer

continues to accumulate THERM assertion times until the

timer is read (it is cleared on read), or until it reaches full scale.

If the counter reaches full scale, it stops at that reading until

cleared.

The 8-bit THERM timer register (0x79) is designed so Bit 0 is

set to 1 on the first THERM assertion. Once the cumulative

THERM assertion time has exceeded 45.52 ms, Bit 1 of the

THERM timer is set and Bit 0 now becomes the LSB of the

timer with a resolution of 22.76 ms (see Figure 32).

ADT7476

Rev. A | Page 29 of 72

THERM

TIMER

(REG. 0x79) THERM ASSERTED

≤ 22.76ms

765 32104

000 00010

THERM

TIMER

(REG. 0x79) THERM ASSERTED

≥ 45.52ms

765 32104

000 00100

THERM

TIMER

(REG. 0x79) THERM ASSERTED ≥ 113.8ms

(91.04ms + 22.76ms)

765 32104

000 01010

THERM

ACCUMULATE THERM LOW

ASSERTION TIMES

THERM

ACCUMULATE THERM LOW

ASSERTION TIMES

05382-033

Figure 32. Understanding the THERM Timer

When using the THERM timer, be aware of the following.

After a THERM timer read (Register 0x79):

1. The contents of the timer are cleared on read.

2. The F4P bit (Bit 5) of Status Register 2 needs to be

cleared (assuming that the THERM timer limit has

been exceeded).

If the THERM timer is read during a THERM assertion, the

following happens:

1. The contents of the timer are cleared.

2. Bit 0 of the THERM timer is set to 1, because a THERM

assertion is occurring.

The THERM timer increments from zero.

3. If the THERM timer limit (Reg. 0x7A) = 0x00, the F4P bit

is set.

Generating SMBALERT Interrupts from THERM Timer

Events

The ADT7476 can generate SMBALERTs when a programma-

ble THERM timer limit has been exceeded. This allows the

system designer to ignore brief, infrequent THERM assertions,

while capturing longer THERM timer events. Register 0x7A is

the THERM timer limit register. This 8-bit register allows a

limit from 0 seconds (first THERM assertion) to 5.825 seconds

to be set before an SMBALERT is generated. The THERM timer

value is compared with the contents of the THERM timer limit

limit value, then the F4P bit (Bit 5) of Status Register 2 is set and

an SMBALERT is generated.

Note: Depending on which pins are configured as a THERM

timer, setting the F4P bit (Bit 5) of Interrupt Mask Register 2

(0x75) or Bit 0 of Interrupt Mask Register 1 (0x74), masks out

SMBALERT; although the F4P bit of Interrupt Status Register 2 is

still set if the THERM timer limit is exceeded.

Figure 33 is a functional block diagram of the THERM timer,

limit, and associated circuitry. Writing a value of 0x00 to the

THERM timer limit register (Reg. 0x7A) causes an SMBALERT

to be generated on the first THERM assertion. A THERM timer

limit value of 0x01 generates an SMBALERT, once cumulative

THERM assertions exceed 45.52 ms.

22.76ms

45.52ms

91.04ms

182.08ms

364.16ms

728.32ms

1.457s

2.914s

IN OUT

RESET

LATCH

CLEARED

ON READ

F4P BIT (BIT 5)

MASK REGISTER 2

(REGISTER 0x75)

1 = MASK

F4P BIT (BIT 5)

STATUS REGISTER 2

COMPARATOR

22.76ms

45.52ms

91.04ms

182.08ms

364.16ms

728.32ms

1.457s

2.914s

543

10 76543210

THERM LIMIT

(REGISTER 0x7A)

THERM TIMER

(REGISTER 0x79)

THERM TIMER CLEARED ON READ

SMBALERT

THERM

05382-034

Figure 33. Functional Block Diagram of THERM Monitoring Circuitry

ADT7476

Rev. A | Page 30 of 72

Configuring the Relevant THERM Behavior

1. Configure the desired pin as the THERM timer input.

Setting Bit 1 (THERM timer enable) of Configuration

functionality. This is disabled on Pin 14 and Pin 22 by

default.

Setting Bit 0 and Bit 1 (PIN14FUNC) of Configuration

functionality on Pin 22 (Bit 1 of Configuration Register 3,

THERM, must also be set). Pin 14 can also be used as

TACH4.

2. Select the desired fan behavior for THERM timer events.

Assuming the fans are running, setting Bit 2 (BOOST bit)

of Configuration Register 3 (0x78) causes all fans to run at

100% duty cycle whenever THERM is asserted. This allows

fail-safe system cooling. If this bit is 0, the fans run at their

current settings and are not affected by THERM events. If

the fans are not already running when THERM is asserted,

the fans do not run to full speed.

3. Select whether THERM timer events should generate

SMBALERT interrupts.

When set, Bit 5 (F4P) of Interrupt Mask Register 2 (0x75)

or Bit 0 of Interrupt Mask Register 1 (0x74), depending on

which pins are configured as a THERM timer, masks out

the SMBALERT when the THERM timer limit value is

exceeded. This bit should be cleared if the SMBALERT

based on THERM events are required.

4. Select a suitable THERM limit value.

This value determines whether an SMBALERT is gener-

ated on the first THERM assertion, or only if a cumulative

THERM assertion time limit is exceeded. A value of 0x00

causes an SMBALERT to be generated on the first THERM

assertion.

5. Select a THERM monitoring time.

This value specifies how often OS- or BIOS-level software

checks the THERM timer. For example, BIOS can read the

THERM timer once an hour to determine the cumulative

THERM assertion time. If, for example, the total THERM

assertion time is <22.76 ms in Hour 1, >182.08 ms in Hour

2, and >5.825 sec in Hour 3, this indicates that system per-

formance is degrading significantly, because THERM is

asserting more frequently on an hourly basis.

Alternatively, OS- or BIOS-level software can timestamp

when the system is powered on. If an SMBALERT is gen-

erated due to the THERM timer limit being exceeded,

another timestamp can be taken. The difference in time

can be calculated for a fixed THERM timer limit time.

For example, if it takes one week for a THERM timer limit

of 2.914 seconds to be exceeded, and the next time it takes

only 1 hour, this is an indication of a serious degradation in

system performance.

Configuring the THERM Pin as an Output

In addition to monitoring THERM as an input, the ADT7476 can

optionally drive THERM low as an output. When PROCHOT is

bidirectional, THERM can be used to throttle the processor by

asserting PROCHOT. The user can preprogram system-critical

thermal limits. If the temperature exceeds a thermal limit by

0.25°C, THERM asserts low. If the temperature is still above the

thermal limit on the next monitoring cycle, THERM stays low.

THERM remains asserted low until the temperature is equal to

or below the thermal limit. Because the temperature for that

channel is measured only once for every monitoring cycle, after

THERM asserts it is guaranteed to remain low for at least one

monitoring cycle.

The THERM pin can be configured to assert low, if the

Remote 1, local, or Remote 2 THERM temperature limits are

exceeded by 0.25°C. The THERM temperature limit registers

are at Register 0x6A, Register 0x6B, and Register 0x6C,

respectively. Setting Bits [7:5] of Configuration Register 5 (0x7C)

enables the THERM output feature for the Remote 1, local, and

Remote 2 temperature channels, respectively. Figure 34 shows

how the THERM pin asserts low as an output in the event of a

critical overtemperature.

MONITORING

CYCLE

TEMP

THERM LIMIT

0.25°C

THERM LIMIT

HERM

05382-035

Figure 34. Asserting THERM as an Output, Based on Tripping THERM Limits

An alternative method of disabling THERM is to program the

THERM temperature limit to –63°C or less in Offset 64 mode,

or −128°C or less in twos complement mode; that is, for

THERM temperature limit values less than −63°C or −128°C,

respectively, THERM is disabled.

ADT7476

Rev. A | Page 31 of 72

Enabling and Disabling THERM on individual Channels

THERM can be enabled/disabled for individual or combina-

tions of temperature channels using Bits [7:5] of Configuration

THERM Hysteresis

Setting Bit 0 of Configuration Register 7 (0x11) disables

THERM hysteresis.

If THERM hysteresis is enabled and THERM is disabled (Bit 2

of Configuration Register 4, 0x7D), the THERM pin does not

assert low when a THERM event occurs. If THERM hysteresis

is disabled and THERM is disabled (Bit 2 of Configuration

ured as THERM), the THERM pin asserts low when a THERM

event occurs.

If THERM and THERM hysteresis are both enabled, the

THERM output asserts as expected.

THERM Operation in Manual Mode

In manual mode, THERM events do not cause fans to go to full

speed, unless Bit 3 of Configuration Register 6 (0x10) is set to 1.

Additionally, Bit 3 of Configuration Register 4 (0x7D) can be

used to select PWM speed on THERM event (100% or

maximum PWM).

Bit 2 in Configuration Register 4 (0x7D) can be set to disable

THERM events from affecting the fans.

FAN DRIVE USING PWM CONTROL

The ADT7476 uses pulse-width modulation (PWM) to control

fan speed. This relies on varying the duty cycle (or on/off ratio)

of a square wave applied to the fan to vary the fan speed. The

external circuitry required to drive a fan using PWM control is

extremely simple. For 4-wire fans, the PWM drive might need

only a pull-up resistor. In many cases, the 4-wire fan PWM

input has a built-in, pull-up resistor.

The ADT7476 PWM frequency can be set to a selection of

low frequencies or a single high PWM frequency. The low

frequency options are used for 3-wire fans, while the high

frequency option is usually used with 4-wire fans.

For 3-wire fans, a single N-channel MOSFET is the only drive

device required. The specifications of the MOSFET depend on

the maximum current required by the fan being driven and

the input capacitance of the FET. Because a 10 kΩ (or greater)

resistor must be used as a PWM pull-up, an FET with large

input capacitance can cause the PWM output to become

distorted and adversely affect the fan control range. This is a

requirement only when using high frequency PWM mode.

Typical notebook fans draw a nominal 170 mA, so SOT devices

can be used where board space is a concern. In desktops, fans

typically draw 250 mA to 300 mA each. If you drive several fans

in parallel from a single PWM output or drive larger server

fans, the MOSFET must handle the higher current require-

ments. The only other stipulation is that the MOSFET should

have a gate voltage drive, VGS < 3.3 V, for direct interfacing to

the PWM output pin. The MOSFET should also have a low on

resistance to ensure that there is not a significant voltage drop

across the FET, which would reduce the voltage applied across

the fan and, therefore, the maximum operating speed of the fan.

Figure 35 shows how to drive a 3-wire fan using PWM control.

05382-036

ADT7476

TACH

PWM

12V

FAN

NDT3055L

TACH

3.3V

10kΩ

4.7kΩ

10kΩ

1N4148

Figure 35. Driving a 3-Wire Fan Using an N-Channel MOSFET

Figure 35 uses a 10 kΩ pull-up resistor for the TACH signal.

This assumes that the TACH signal is an open-collector from

the fan. In all cases, the TACH signal from the fan must be kept

below 3.6 V maximum to prevent damaging the ADT7476.

Figure 36 shows a fan drive circuit using an NPN transistor

such as a general-purpose MMBT2222. While these devices

are inexpensive, they tend to have much lower current han-

dling capabilities and higher on resistance than MOSFETs.

When choosing a transistor, care should be taken to ensure

that it meets the fan’s current requirements. Ensure that the

base resistor is chosen, so the transistor is saturated when the

fan is powered on.

Because in 4-wire fans the fan drive circuitry is not switched on

or off, as with previous PWM driven/powered fans, the internal

drive circuit is always on and uses the PWM input as a signal

instead of a power supply. This enables the internal fan drive

circuit to perform better than 3-wire fans, especially for high

frequency applications.

05382-037

ADT7476

TACH

PWM

12V

FAN

MMBT2222

3.3V

470Ω

4.7kΩ

10kΩ

1N4148

Figure 36. Driving a 3-Wire Fan Using an NPN Transistor

ADT7476

Rev. A | Page 32 of 72

Figure 37 shows a typical drive circuit for 4-wire fans.

05382-038

ADT7476

TACH

PWM

12V, 4-WIRE FAN

3.3V

2kΩ

4.7kΩ

10kΩ

TACH

TACH PWM

3.3V

Figure 37. Driving a 4-Wire Fan

Driving Two Fans from PWM3

The ADT7476 has four TACH inputs available for fan speed

measurement, but only three PWM drive outputs. If a fourth

fan is being used in the system, it should be driven from the

PWM3 output in parallel with the third fan.

Figure 38 shows how to drive two fans in parallel using low

cost NPN transistors. Figure 39 shows the equivalent circuit

using a MOSFET.

Because the MOSFET can handle up to 3.5 A, it is simply a

matter of connecting another fan directly in parallel with the

first. Care should be taken in designing drive circuits with

transistors and FETs to ensure the PWM outputs are not

required to source current, and they sink less than the

5 mA maximum current specified on the data sheet.

Driving up to Three Fans from PWM3

TACH measurements for fans are synchronized to particular

PWM channels; for example, TACH1 is synchronized to

PWM1. TACH3 and TACH4 are both synchronized to PWM3,

so PWM3 can drive two fans. Alternatively, PWM3 can be pro-

grammed to synchronize TACH2, TACH3, and TACH4 to the

PWM3 output. This allows PWM3 to drive two or three fans.

In this case, the drive circuitry looks the same, as shown in

Figure 38 and Figure 39. The SYNC bit in Register 0x62 enables

this function.

Synchronization is not required in high frequency mode when

used with 4-wire fans.

Enhance Acoustics Register 1 (0x62)

Bit 4 SYNC = 1, synchronizes TACH2, TACH3, and TACH4

to PWM3.

05382-039

ADT7476

PWM3

3.3V 3.3V

1N4148

MMBT3904

MMBT2222

10Ω

2.2kΩ

1kΩ

TACH3 TACH4

3.3V3.3V

Figure 38. Interfacing Two Fans in Parallel to the PWM3 Output Using Low Cost NPN Transistors

05382-040

ADT7476

PWM3

TACH3

TACH4

3.3V

3.3

+V +V

TACH

NDT3055L

1N4148 5V OR

12V FAN

5V OR

12V FAN

10kΩ

TYPICAL

10kΩ

TYPICAL

10kΩ

TYPICAL

3.3V

Figure 39. Interfacing Two Fans in Parallel to the PWM3 Output Using a Single N-Channel MOSFET

ADT7476

Rev. A | Page 33 of 72

LAYING OUT 3-WIRE FANS

Figure 40 shows how to lay out a common circuit arrangement

for 3-wire fans.

05382-041

MMBT2222

PWM

1N4148

3.3V OR 5V

12V OR 5V

TACH

Figure 40. Planning for 3-Wire Fans on a PCB

TACH Inputs

Pin 9, Pin 11, Pin 12, and Pin 14 (when configured as TACH

inputs) are high impedance inputs intended for fan speed

measurement.

Signal conditioning in the ADT7476 accommodates the slow

rise and fall times typical of fan tachometer outputs. The maxi-

mum input signal range is 0 V to 3.6 V, even though VCC is

3.3 V. In the event that these inputs are supplied from fan

outputs that exceed 0 V to 3.6 V, either resistive attenuation

of the fan signal or diode clamping must be included to keep

inputs within an acceptable range.

Figure 41 to Figure 44 show circuits for most common fan

TACH outputs.

If the fan TACH output has a resistive pull-up to VCC, it can be

connected directly to the fan input, as shown in Figure 41.

05382-042

12V

PULL-UP

4.7kΩ

TYP

TACH

OUTPUT

FAN SPEED

COUNTER

TACH

ADT7476

Figure 41. Fan with TACH Pull-Up to VCC

If the fan output has a resistive pull-up to 12 V, or other voltage

greater than 3.6 V, the fan output can be clamped with a Zener

diode, as shown in Figure 42. The Zener diode voltage should

be chosen so that it is greater than VIH of the TACH input but

less than 3.6 V, allowing for the voltage tolerance of the Zener. A

value of between 3 V and 3.6 V is suitable.

05382-043

12V

PULL-UP

4.7kΩ

TYPICAL

TACH

OUTPUT FAN SPEED

COUNTER

TACH

ADT7476

ZD1*

*CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8 × V

Figure 42. Fan with TACH Pull-Up to Voltage > 3.6 V (for Example, 12 V),

Clamped with Zener Diode

If the fan has a strong pull-up (less than 1 kΩ) to 12 V or a

totem-pole output, a series resistor can be added to limit the

Zener current, as shown in Figure 43.

5382-044

5V OR 12V

PULL-UP TYP

<1kΩ OR

TOTEM POLE

TACH

OUTPUT

FAN SPEED

COUNTER

TACH

ADT7476

ZD1

ZENER*

FAN

*CHOOSE ZD1 VOLTAGE APPROXIMATELY 0.8 × V

10kΩ

Figure 43. Fan with Strong TACH Pull-Up to > VCC or Totem-Pole Output,

Clamped with Zener Diode and Resistor

Alternatively, a resistive attenuator can be used, as shown

in Figure 44. R1 and R2 should be chosen such that

2 V < VPULL-UP × R2/(RPULL-UP + R1 + R2) < 3.6 V

The fan inputs have an input resistance of nominally 160 kΩ to

ground, which should be taken into account when calculating

resistor values.

With a pull-up voltage of 12 V and pull-up resistor less than

1 kΩ, suitable values for R1 and R2 are 100 kΩ and 40 kΩ,

respectively. This gives a high input voltage of 3.42 V.

05382-045

12V

<1kΩ

TACH

OUTPUT

FAN SPEED

COUNTER

TACH

ADT7476

R2*

*SEE TEXT

R1*

Figure 44. Fan with Strong TACH Pull-Up to > VCC or Totem-Pole Output,

Attenuated with R1/R2

ADT7476

Rev. A | Page 34 of 72

The fan counter does not count the fan TACH output pulses

directly, because the fan speed could be less than 1000 RPM and

it takes several seconds to accumulate a reasonably large and

accurate count. Instead, the period of the fan revolution is

measured by gating an on-chip 90 kHz oscillator into the input

of a 16-bit counter for N periods of the fan TACH output

(Figure 45), so the accumulated count is actually proportional

to the fan tachometer period and inversely proportional to the

fan speed.

N, the number of pulses counted, is determined by the settings

of TACH pulses per revolution register (0x7B). This register

contains two bits for each fan, allowing one, two (default), three,

or four TACH pulses to be counted.

05382-046

CLOCK

PWM

TACH

Figure 45. Fan Speed Measurement

Fan Speed Measurement Registers

The fan tachometer readings are 16-bit values consisting of a

2-byte read from the ADT7476.

Reading Fan Speed from the ADT7476

The measurement of fan speeds involves a 2-register read

for each measurement. The low byte should be read first.

This causes the high byte to be frozen until both high and

low byte registers have been read, preventing erroneous

TACH readings. The fan tachometer reading registers report

back the number of 11.11 µs period clocks (90 kHz oscillator)

gated to the fan speed counter, from the rising edge of the first

fan TACH pulse to the rising edge of the third fan TACH pulse

(assuming two pulses per revolution are being counted).

Because the device is essentially measuring the fan TACH

period, the higher the count value, the slower the fan is actu-

ally running. A 16-bit fan tachometer reading of 0xFFFF

indicates that either the fan has stalled or is running very

slowly (<100 RPM).

High Limit > Comparison Performed

Because the actual fan TACH period is being measured, falling

below a fan TACH limit by 1 sets the appropriate status bit and

can be used to generate an SMBALERT.

Measuring fan TACH has the following caveat: When the

ADT7476 starts up, TACH measurements are locked. In effect,

an internal read of the low byte has been made for each TACH

input. The net result of this is that all TACH readings are

locked until the high byte is read from the corresponding

TACH registers. All TACH-related interrupts are also ignored

until the appropriate high byte is read.

Once the corresponding high byte has been read, TACH

measurements are unlocked and interrupts are processed as

normal.

Fan TACH Limit Registers

The fan TACH limit registers are 16-bit values consisting of

two bytes.

Fan Speed Measurement Rate

The fan TACH readings are normally updated once

every second.

The FAST bit (Bit 3) of Configuration Register 3 (0x78), when

set, updates the fan TACH readings every 250 ms.

DC Bits

If any of the fans are not being driven by a PWM channel but

are powered directly from 5 V or 12 V, their associated dc bit

in Configuration Register 3 should be set. This allows TACH

readings to be taken on a continuous basis for fans connected

directly to a dc source. For 4-wire fans, once high frequency

mode is enabled, the dc bits do not need to be set as this is

automatically done internally.

ADT7476

Rev. A | Page 35 of 72

Calculating Fan Speed

Assuming a fan with two pulses per revolution, and with the

ADT7476 programmed to measure two pulses per revolution,

fan speed is calculated by

Fan Speed (RPM) = (90,000 × 60)/Fan TACH Reading

where Fan TACH Reading is the 16-bit fan tachometer reading.

Example

TACH1 High Byte Register (0x29) = 0x17

TACH1 Low Byte Register (0x28) = 0xFF

What is Fan 1 speed in RPM?

Fan 1 TACH Reading = 0x17FF = 6143 (decimal)

RPM = (f × 60)/Fan 1 TACH Reading

RPM = (90,000 × 60)/6143

Fan Speed = 879 RPM

Fan Pulses per Revolution

Different fan models can output either one, two, three, or four

TACH pulses per revolution. Once the number of fan TACH

pulses is determined, it can be programmed into the fan pulses

per revolution register (0x7B) for each fan. Alternatively,

this register can be used to determine the number or pulses

per revolution output by a given fan. By plotting fan speed

measurements at 100% speed with different pulses per

revolution setting, the smoothest graph with the lowest

ripple determines the correct pulses per revolution value.

Fan Pulses per Revolution Register

Bits [1:0] Fan 1 default = 2 pulses per revolution.

Bits [3:2] Fan 2 default = 2 pulses per revolution.

Bits [5:4] Fan 3 default = 2 pulses per revolution.

Bits [7:6] Fan 4 default = 2 pulses per revolution.

00 = 1 pulse per revolution.

01 = 2 pulses per revolution.

10 = 3 pulses per revolution.

11 = 4 pulses per revolution.

Fan Spin-Up

The ADT7476 has a unique fan spin-up function. It spins the

fan at 100% PWM duty cycle until two TACH pulses are de-

tected on the TACH input. Once two TACH pulses have been

detected, the PWM duty cycle goes to the expected running

value, for example, 33%. The advantage is that fans have

different spin-up characteristics and take different times to

overcome inertia. The ADT7476 runs the fans just fast enough

to overcome inertia and is quieter on spin-up than fans

programmed to spin up for a given spin-up time.

Fan Startup Timeout

To prevent the generation of false interrupts as a fan spins up,

because it is below running speed, the ADT7476 includes a fan

startup timeout function. During this time, the ADT7476 looks

for two TACH pulses. If two TACH pulses are not detected,

then an interrupt is generated.

Fan startup timeout can be disabled by setting Bit 5 (FSPDIS) of

Configuration Register 1 (0x40).

PWM1, PWM2, PWM3 Configuration Registers

(0x5C, 0x5D, and 0x5E)

Bits [2:0] SPIN, startup timeout for PWM1 = 0x5C, PWM2 =

0x5D, and PWM3 = 0x5E.

000 = No startup timeout

001 = 100 ms

010 = 250 ms default

011 = 400 ms

100 = 667 ms

101 = 1 second

110 = 2 second

111 = 4 second

Disabling Fan Startup Timeout

Although fan startup makes fan spin-ups much quieter than

fixed-time spin-ups, the option exists to use fixed spin-up

times. Setting Bit 5 (FSPDIS) to 1 in Configuration Register 1

(0x40) disables the spin-up for two TACH pulses. Instead, the

fan spins up for the fixed time as selected in Register 0x5C to

PWM Logic State

The PWM outputs can be programmed high for 100% duty

cycle (noninverted) or low for 100% duty cycle (inverted).

PWM1 Configuration Register (0x5C)

Bit 4 INV.

0 = Logic high for 100% PWM duty cycle.

1 = Logic low for 100% PWM duty cycle.

PWM2 Configuration Register (0x5D)

Bit 4 INV.

0 = Logic high for 100% PWM duty cycle.

1 = Logic low for 100% PWM duty cycle.

PWM3 Configuration Register (0x5E)

Bit 4 INV.

0 = Logic high for 100% PWM duty cycle.

1 = Logic low for 100% PWM duty cycle.

ADT7476

Rev. A | Page 36 of 72

Low Frequency Mode PWM Drive Frequency Once under manual control, each PWM output can be manu-

ally updated by writing Register 0x30 to Register 0x32 (PWMx

current duty cycle registers).

The PWM drive frequency can be adjusted for the application.

for PWM1 to PWM3, respectively. Programming the PWM Current Duty Cycle Registers

PWM1, PWM 2, PWM3 Frequency Registers

(Register 0x5F to Register 0x61)

The PWM current duty cycle registers are 8-bit registers that

allow the PWM duty cycle for each output to be set anywhere

from 0% to 100% in steps of 0.39%. The value to be programmed

into the PWMMIN register is given by

Bits [2:0] FREQ

000 = 11.0 Hz

Valu e (decimal) = PWMMIN/0.39

001 = 14.7 Hz

010 = 22.1 Hz Example 1: For a PWM duty cycle of 50%

011 = 29.4 Hz Value (decimal) = 50/0.39 = 128 (decimal)

Value = 128 (decimal) or 0x80 (hex)

100 = 35.3 Hz default

101 = 44.1 Hz Example 2: For a PWM duty cycle of 33%

110 = 58.8 Hz

Value (decimal) = 33/0.39 = 85 (decimal)

Value = 85 (decimal) or 0x54 (hex)

111 = 88.2 Hz

High Frequency Mode PWM Drive

PWM Duty Cycle Registers

Setting Bit 3 of Register 0x5F, Register 0x60, and Register 0x61

enables high frequency mode for Fan 1, Fan 2, and Fan 3

respectively.

In high frequency mode, the PWM drive frequency is always

22.5 kHz. When high frequency mode is enabled, the dc bits are

automatically asserted internally and do not need to be

changed.

By reading the PWMx current duty cycle registers, the user can

keep track of the current duty cycle on each PWM output, even

when the fans are running in automatic fan speed control mode

or acoustic enhancement mode.

Fan Speed Control

The ADT7476 controls fan speed using automatic and manual

modes. PROGRAMMING TRANGE

TRANGE defines the distance between TMIN and 100% PWM.

For the ADT7467, ADT7468, and ADT7473, TRANGE is

effectively a slope. For the ADT7475 andADT7476, TRANGE is no

longer a slope but defines the temperature region where the

PWM output linearly ramps from PWMMIN to 100% PWM.

In automatic fan speed control mode, fan speed is automatically

varied with temperature and without CPU intervention, once

initial parameters are set up. The advantage is that, if the system

hangs, the user is guaranteed that the system is protected from

overheating.

05382-047

TMIN

PWM = 100%

PWMMIN

PWMMAX

PWM = 0%

TRANGE

In manual fan speed control mode, the ADT7476 allows the

duty cycle of any PWM output to be manually adjusted. This

can be useful, if the user wants to change fan speed in software

or adjust PWM duty cycle output for test purposes. Bits [7:5] of

the behavior of each PWM output.

PWM Configuration Registers (0x5C to 0x5E)

Bits [7:5] BHVR

111 = manual mode Figure 46. TRANGE

ADT7476

Rev. A | Page 37 of 72

PROGRAMMING THE AUTOMATIC FAN SPEED CONTROL LOOP

To understand the automatic fan speed control loop, use the

ADT7476 evaluation board and software while reading this

section.

This section provides the system designer with an understanding

of the automatic fan control loop, and provides step-by-step

guidance on effectively evaluating and selecting critical system

parameters. To optimize the system characteristics, the designer

needs to give some thought to system configuration, including

the number of fans, where they are located, and what tempera-

tures are being measured in the particular system.

The mechanical or thermal engineer who is tasked with the

system thermal characterization should also be involved at

the beginning of the system development process.

MANUAL FAN CONTROL OVERVIEW

In unusual circumstances, it can be necessary to manually

control the speed of the fans. Because the ADT7476 has an

SMBus interface, a system can read back all necessary voltage,

fan speed, and temperature information, and use this

information to control the speed of the fans by writing to the

current PWM duty cycle registers (0x30, 0x31, and 0x32) of the

appropriate fan. Bits [7:5] of the PWMx configuration registers

(0x5C, 0x5D, 0x5E) are used to set up fans for manual control.

THERM OPERATION IN MANUAL MODE

In manual mode, if the temperature increases above the pro-

grammed THERM temperature limit, the fans automatically

speed up to maximum PWM or100% PWM, whichever way

the appropriate fan channel is configured.

AUTOMATIC FAN CONTROL OVERVIEW

The ADT7476 can automatically control the speed of fans based

on the measured temperature. This is done independently of

CPU intervention once initial parameters are set up.

The ADT7476 has a local temperature sensor and two remote

temperature channels that can be connected to a CPU on-chip

thermal diode (available on Intel Pentium class CPUs and other

CPUs). These three temperature channels can be used as the

basis for automatic fan speed control to drive fans using PWM.

Automatic fan speed control reduces acoustic noise by

optimizing fan speed according to accurately measured

temperature. Reducing fan speed can also decrease system

current consumption. The automatic fan speed control mode

is very flexible owing to the number of programmable parame-

ters, including TMIN and TRANGE. The TMIN and TRANGE values for a

temperature channel and, therefore, for a given fan are critical,

because they define the thermal characteristics of the system.

The thermal validation of the system is one of the most important

steps in the design process, so these values should be selected

carefully.

Figure 47 gives a top-level overview of the automatic fan control

circuitry on the ADT7476. From a systems-level perspective,

up to three system temperatures can be monitored and used to

control three PWM outputs. The three PWM outputs can be

used to control up to four fans. The ADT7476 allows the speed

of four fans to be monitored. Each temperature channel has a

thermal calibration block, allowing the designer to individually

configure the thermal characteristics of each temperature

channel. For example, one can decide to run the CPU fan when

CPU temperature increases above 60°C and a chassis fan when

the local temperature increases above 45°C.

At this stage, the designer has not assigned these thermal

calibration settings to a particular fan drive (PWM) channel.

The right side of Figure 47 shows controls that are fan-specific.

The designer has individual control over parameters such as

minimum PWM duty cycle, fan speed failure thresholds, and

even ramp control of the PWM outputs. Automatic fan control,

then, ultimately allows graceful fan speed changes that are less

perceptible to the system user.

ADT7476

Rev. A | Page 38 of 72

05382-048

MUX

THERMAL CALIBRATION

MIN

RANGE

THERMAL CALIBRATION 100%

MIN

RANGE

THERMAL CALIBRATION 100%

MIN

RANGE

REMOTE 1

TEMP

LOCAL

TEMP

REMOTE 2

TEMP

PWM

MIN

PWM1

TACH1

TACH2

TACH3

PWM

MIN

PWM2

PWM

MIN

PWM3

100%

PWM

GENERATOR

PWM

GENERATOR

TACHOMETER 3

AND 4

MEASUREMENT

TACHOMETER 1

MEASUREMENT

TACHOMETER 2

MEASUREMENT

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

PWM

GENERATOR

PWM

CONFIG

PWM

CONFIG

PWM

CONFIG

Figure 47. Automatic Fan Control Block Diagram

STEP 1: HARDWARE CONFIGURATION

During system design, the motherboard sensing and control

capabilities should be addressed early in the design stages.

Decisions about how these capabilities are used should involve

the system thermal/mechanical engineer. Ask the following

questions:

• What ADT7476 functionality is used?

• PWM2 or SMBALERT?

• TACH4 fan speed measurement or overtemperature

THERM function?

• 2.5 V voltage monitoring or overtemperature THERM

function?

• 12 V voltage monitoring or VID5 input?

The ADT7476 offers multifunctional pins that can be

reconfigured to suit different system requirements and

physical layouts. These multifunction pins are software

programmable.

• How many fans are supported in system, three or four?

This influences the choice of whether to use the

TACH4 pin or to reconfigure it for the THERM

function.

• Is the CPU fan to be controlled using the ADT7476, or

will the CPU fan run at full speed 100% of the time?

• If run at 100%, this frees up a PWM output, but the

system is louder.

• Where will the ADT7476 be physically located in the

system?

This influences the assignment of the temperature meas-

urement channels to particular system thermal zones. For

example, locating the ADT7476 close to the VRM controller

circuitry allows the VRM temperature to be monitored using

the local temperature channel.

ADT7476

Rev. A | Page 39 of 72

REAR CHASSIS

FRONT CHASSIS

CPU FAN SINK

REMOTE 1 =

AMBIENT TEMP

LOCAL =

VRM TEMP

REMOTE 2 =

CPU TEMP

PWM1

PWM2

TACH1

TACH2

TACH3

PWM3

MUX

THERMAL CALIBRATION

MIN

RANGE

THERMAL CALIBRATION 100%

MIN

RANGE

THERMAL CALIBRATION 100%

MIN

RANGE

PWM

MIN

PWM

MIN

PWM

MIN

100%

05382-049

PWM

GENERATOR

PWM

GENERATOR

TACHOMETER 3

AND 4

MEASUREMENT

TACHOMETER 1

MEASUREMENT

TACHOMETER 2

MEASUREMENT

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

PWM

GENERATOR

PWM

CONFIG

PWM

CONFIG

PWM

CONFIG

Figure 48. Hardware Configuration Example

Recommended Implementation 1

Configuring the ADT7476 as in Figure 49 provides the system

designer with the following features:

• Six VID inputs (VID0 to VID5) for VRM10 support.

• Two PWM outputs for fan control of up to three fans.

The front and rear chassis fans are connected in parallel.

• Three TACH fan speed measurement inputs.

• VCC measured internally through Pin 4.

• CPU core voltage measurement (VCORE).

• 2.5 V measurement input used to monitor CPU current

(connected to VCOMP output of ADP316x VRM controller).

This is used to determine CPU power consumption.

• 5 V measurement input.

• VRM temperature using local temperature sensor.

• CPU temperature measured using the Remote 1

temperature channel.

• Ambient temperature measured through the Remote 2

temperature channel.

• If not using VID5, it can be reconfigured as the 12 V

monitoring input.

• Bidirectional THERM pin allows the monitoring of

PROCHOT output from an Intel Pentium 4 processor, for

example, or can be used as an overtemperature THERM

output.

• SMBALERT system interrupt output.

ADT7476

Rev. A | Page 40 of 72

05382-050

FRONT

CHASSIS

FAN TACH2

ADT7476

PWM3

REAR

HASSIS

FAN

AMBIENT

TEMPERATURE

TACH3

D1+

D1–

+5V

+12V

/VID5

GND

PWM1

TACH1

VID[0:4]/VID[0.5]

D2+

D2–

THERM

SMBALERT

SDA

SCL

PROCHOT

5(VRM9)/6(VRM10)

CPU FAN

CPU

ICH

Figure 49. Recommended Implementation 1

Recommended Implementation 2

Configuring the ADT7476 as in Figure 50 provides the system

designer with the following features:

• Six VID inputs (VID0 to VID5) for VRM10 support.

• Three PWM outputs for fan control of up to three fans.

All three fans can be individually controlled.

• Three TACH fan speed measurement inputs.

• VCC measured internally through Pin 4.

• CPU core voltage measurement (VCORE).

• 2.5 V measurement input used to monitor CPU current

(connected to VCOMP output of ADP316x VRM controller).

This is used to determine CPU power consumption.

• 5 V measurement input.

• VRM temperature using local temperature sensor.

• CPU temperature measured using the Remote 1

temperature channel.

• Ambient temperature measured through the Remote 2

temperature channel.

• If not using VID5, it can be reconfigured as the 12 V

monitoring input.

• Bidirectional THERM pin allows the monitoring of

PROCHOT output/input from an Intel Pentium 4

processor, for example, or can be used as an

overtemperature THERM output.

ADT7476

Rev. A | Page 41 of 72

05382-051

FRONT

CHASSIS

FAN TACH2

ADT7476

PWM3

PWM2

REAR

CHASSIS

FAN

AMBIENT

TEMPERATURE

TACH3

D1+

D1–

+5V

+12V

/VID5

GND

PWM1

TACH1

VID[0:4]/VID[0.5]

D2+

D2–

THERM

SDA

SCL

PROCHOT

5(VRM9)/6(VRM10)

CPU FAN

CPU

ICH

Figure 50. Recommended Implementation 2

STEP 2: CONFIGURING THE MUX

After the system hardware configuration is determined, the fans

can be assigned to particular temperature channels. Not only

can fans be assigned to individual channels, but the behavior

of the fans is also configurable. For example, fans can be run

under automatic fan control, can be run manually (under

software control), or can be run at the fastest speed calcu-

lated by multiple temperature channels. The mux is the bridge

between temperature measurement channels and the three

PWM outputs.

Bits [7:5] (BHVR) of Register 0x5C, Register 0x5D, and

behavior of the fans connected to the PWM1, PWM2, and

PWM3 outputs. The values selected for these bits determine

how the mux connects a temperature measurement channel to a

PWM output.

Automatic Fan Control Mux Options

Bits [7:5] (BHVR), Register 0x5C, Register 0x5D, and

000 = Remote 1 temperature controls PWMx

001 = local temperature controls PWMx

010 = Remote 2 temperature controls PWMx

101 = fastest speed calculated by local and Remote 2

temperature controls PWMx

110 = fastest speed calculated by all three temperature

channels controls PWMx

The fastest speed calculated options pertain to controlling

one PWM output based on multiple temperature channels.

The thermal characteristics of the three temperature zones

can be set to drive a single fan. An example would be the fan

turning on when Remote 1 temperature exceeds 60°C or if

the local temperature exceeds 45°C.

Other Mux Options

Bits [7:5] (BHVR), Register 0x5C, Register 0x5D, and

011 = PWMx runs full speed

100 = PWMx disabled (default)

111 = manual mode. In manual mode, PWMx runs under

software control. In this mode, PWM duty cycle registers

(Register 0x30 to Register 0x32) are writable and control

the PWM outputs.

ADT7476

Rev. A | Page 42 of 72

MUX

05382-052

REAR CHASSIS

FRONT CHASSIS

CPU FAN SINK

REMOTE 1 =

AMBIENT TEMP

LOCAL =

VRM TEMP

REMOTE 2 =

CPU TEMP

PWM1

PWM2

TACH1

TACH2

TACH3

PWM3

MUX

THERMAL CALIBRATION

MIN

RANGE

THERMAL CALIBRATION 100%

MIN

RANGE

THERMAL CALIBRATION 100%

MIN

RANGE

PWM

MIN

PWM

MIN

PWM

MIN

100%

PWM

GENERATOR

PWM

GENERATOR

TACHOMETER 3

AND 4

MEASUREMENT

TACHOMETER 1

MEASUREMENT

TACHOMETER 2

MEASUREMENT

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

PWM

GENERATOR

PWM

CONFIG

PWM

CONFIG

PWM

CONFIG

Figure 51. Assigning Temperature Channels to Fan Channels

Mux Configuration Example

This is an example of how to configure the mux in a system

using the ADT7476 to control three fans. The CPU fan sink

is controlled by PWM1, the front chassis fan is controlled by

PWM2, and the rear chassis fan is controlled by PWM3. The

mux is configured for the following fan control behavior:

• PWM1 (CPU fan sink) is controlled by the fastest speed

calculated by the local (VRM temperature) and Remote 2

(processor) temperature. In this case, the CPU fan sink is

also used to cool the VRM.

• PWM2 (front chassis fan) is controlled by the Remote 1

temperature (ambient).

• PWM3 (rear chassis fan) is controlled by the Remote 1

temperature (ambient).

Example Mux Settings

Bits [7:5] (BHVR), PWM1 Configuration Register 0x5C.

101 = Fastest speed calculated by local and Remote 2

temperature controls PWM1

Bits [7:5] (BHVR), PWM2 Configuration Register 0x5D.

000 = Remote 1 temperature controls PWM2

Bits [7:5] (BHVR), PWM3 Configuration Register 0x5E.

000 = Remote 1 temperature controls PWM3

These settings configure the mux, as shown in Figure 52.

ADT7476

Rev. A | Page 43 of 72

05382-053

REAR CHASSIS

FRONT CHASSIS

CPU FAN SINK

LOCAL =

VRM TEMP

PWM1

PWM2

TACH1

TACH2

TACH3

PWM3

REMOTE 1 =

AMBIENT TEMP

REMOTE 2 =

CPU TEMP

THERMAL CALIBRATION

MIN

RANGE

THERMAL CALIBRATION 100%

MIN

RANGE

THERMAL CALIBRATION 100%

MIN

RANGE

PWM

MIN

PWM

MIN

PWM

MIN

100%

MUX

PWM

GENERATOR

PWM

GENERATOR

TACHOMETER 3

AND 4

MEASUREMENT

TACHOMETER 1

MEASUREMENT

TACHOMETER 2

MEASUREMENT

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

PWM

GENERATOR

PWM

CONFIG

PWM

CONFIG

PWM

CONFIG

Figure 52. MUX Configuration Example

STEP 3: TMIN SETTINGS FOR THERMAL

CALIBRATION CHANNELS

TMIN is the temperature at which the fans start to turn on under

automatic fan control. The speed at which the fan runs at TMIN

is programmed later. The TMIN values chosen are temperature

channel specific, for example, 25°C for ambient channel, 30°C

for VRM temperature, and 40°C for processor temperature.

TMIN is an 8-bit value, either twos complement or Offset 64,

that can be programmed in 1°C increments. A TMIN register

is associated with each temperature measurement channel:

Remote 1 local, and Remote 2 temperature. Once the TMIN value

is exceeded, the fan turns on and runs at the minimum PWM

duty cycle. The fan turns off once the temperature has dropped

below TMIN − THYST.

To overcome fan inertia, the fan is spun up until two valid TACH

rising edges are counted. (See the Fan Startup Timeout section

for more details.) In some cases, primarily for psycho-acoustic

reasons, it is desirable that the fan never switch off below TMIN.

When set, Bits [7:5] of Enhanced Acoustics Register 1 (0x62),

keep the fans running at the PWM minimum duty cycle, if the

temperature should fall below TMIN.

TMIN Registers

Enhance Acoustics Register 1 (Reg. 0x62)

Bit 7 (MIN3) = 0, PWM3 is off (0% PWM duty cycle) when

temperature is below TMIN − THYST.

Bit 7 (MIN3) = 1, PWM3 runs at PWM3 minimum duty cycle

below TMIN − THYST.

Bit 6 (MIN2) = 0, PWM2 is off (0% PWM duty cycle) when

temperature is below TMIN − THYST.

Bit 6 (MIN2) = 1, PWM2 runs at PWM2 minimum duty cycle

below TMIN − THYST.

Bit 5 (MIN1) = 0, PWM1 is off (0% PWM duty cycle) when

temperature is below TMIN − THYST.

Bit 5 (MIN1) = 1, PWM1 runs at PWM1 minimum duty cycle

below TMIN − THYST.

ADT7476

Rev. A | Page 44 of 72

05382-054

100%

PWM DUTYCYCLE

MIN

REAR CHASSIS

FRONT CHASSIS

CPU FAN SINK

LOCAL =

VRM TEMP

PWM1

PWM2

TACH1

TACH2

TACH3

PWM3

REMOTE 1 =

AMBIENT TEMP

REMOTE 2 =

CPU TEMP

MUX

THERMAL CALIBRATION

MIN

RANGE

THERMAL CALIBRATION 100%

MIN

RANGE

THERMAL CALIBRATION 100%

MIN

RANGE

PWM

MIN

PWM

MIN

PWM

MIN

100%

PWM

GENERATOR

PWM

GENERATOR

TACHOMETER 3

AND 4

MEASUREMENT

TACHOMETER 1

MEASUREMENT

TACHOMETER 2

MEASUREMENT

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

PWM

GENERATOR

PWM

CONFIG

PWM

CONFIG

PWM

CONFIG

Figure 53. Understanding the TMIN Parameter

STEP 4: PWMMIN FOR EACH PWM (FAN) OUTPUT

PWMMIN is the minimum PWM duty cycle at which each fan

in the system runs. It is also the start speed for each fan under

automatic fan control once the temperature rises above TMIN.

For maximum system acoustic benefit, PWMMIN should be as

low as possible. Depending on the fan used, the PWMMIN set-

ting is usually in the 20% to 33% duty cycle range. This value

can be found through fan validation.

TEMPERATURE

MIN

100%

PWM

MIN

PWM DUTY CYCLE

05382-055

Figure 54. PWMMIN Determines Minimum PWM Duty Cycle

More than one PWM output can be controlled from a single

temperature measurement channel. For example, Remote 1

Temperature can control PWM1 and PWM2 outputs. If two

different fans are used on PWM1 and PWM2, the fan

characteristics can be set up differently. As a result, Fan 1 driven

by PWM1 can have a different PWMMIN value than that of Fan 2

connected to PWM2. Figure 55 illustrates this as PWM1MIN

(front fan) is turned on at a minimum duty cycle of 20%, while

PWM2MIN (rear fan) turns on at a minimum of 40% duty cycle.

Note: Both fans turn on at exactly the same temperature,

defined by TMIN.

TEMPERATURE

MIN

100%

PWM1

MIN

PWM DUTY CYCLE

PWM1

PWM2

MIN

05382-056

Figure 55. Operating Two Different Fans from a Single Temperature Channel

ADT7476

Rev. A | Page 45 of 72

Programming the PWMMIN Registers

The PWMMIN registers are 8-bit registers that allow the mini-

mum PWM duty cycle for each output to be configured

anywhere from 0% to 100%. This allows the minimum

PWM duty cycle to be set in steps of 0.39%.

The value to be programmed into the PWMMIN register is

given by

Value (decimal) = PWMMIN/0.39

Example 1: For a minimum PWM duty cycle of 50%

Value (decimal) = 50/0.39 = 128 (decimal)

Value = 128 (decimal) or 80 (hex)

Example 2: For a minimum PWM duty cycle of 33%

Value (decimal) = 33/0.39 = 85 (decimal)

Value = 85 (decimal) or 54 (hex)

PWMMIN Registers

Note on Fan Speed and PWM Duty Cycle

The PWM duty cycle does not directly correlate to fan speed in

RPM. Running a fan at 33% PWM duty cycle does not equate to

running the fan at 33% speed. Driving a fan at 33% PWM duty

cycle actually runs the fan at closer to 50% of its full speed. This

is because fan speed in %RPM generally relates to the square

root of PWM duty cycle. Given a PWM square wave as the

drive signal, fan speed in RPM approximates to

10% ×= CycleDutyPWMfanspeed

STEP 5: PWMMAX FOR PWM (FAN) OUTPUTS

PWMMAX is the maximum duty cycle at which each fan in the

system runs under the automatic fan speed control loop. For

maximum system acoustic benefit, PWMMAX should be as low as

possible, but should be capable of maintaining the processor

temperature limit at an acceptable level. If the THERM

temperature limit is exceeded, the fans are still boosted to

100% for fail-safe cooling.

There is a PWMMAX limit for each fan channel. The default

value of this register is 0xFF and has no effect unless it is

programmed.

TEMPERATURET

MIN

100%

PWM

MIN

PWM DUTY CYCLE

PWM

MAX

05382-057

Figure 56. PWMMAX Determines Maximum PWM Duty Cycle

Below the THERM Temperature Limit

Programming the PWMMAX Registers

The PWMMAX registers are 8-bit registers that allow the

maximum PWM duty cycle for each output to be configured

anywhere from 0% to 100%. This allows the maximum PWM

duty cycle to be set in steps of 0.39%.

The value to be programmed into the PWMMAX register is

given by

Value (decimal) = PWMMAX/0.39

Example 1: For a maximum PWM duty cycle of 50%

Value (decimal) – 50/0.39 = 128 (decimal)

Value = 128 (decimal) or 80 (hex)

Example 2: For a minimum PWM duty cycle of 75%

Value (decimal) = 75/0.39 = 85 (decimal)

Value = 192 (decimal) or C0 (hex)

PWMMAX Registers

(100% default)

ADT7476

Rev. A | Page 46 of 72

STEP 6: TRANGE FOR TEMPERATURE CHANNELS

TRANGE is the range of temperature over which automatic fan

control occurs once the programmed TMIN temperature has

been exceeded. TRANGE is the temperature range between PWMMIN

and 100% PWM where the fan speed changes linearly. Otherwise

stated, it is the line drawn between the TMIN/PWMMIN and the

(TMIN + TRANGE)/PWM100% intersection points.

TEMPERATURE

MIN

100%

PWM

MIN

PWM DUTY CYCLE

RANGE

05382-058

Figure 57. TRANGE Parameter Affects Cooling Slope

The TRANGE is determined by the following procedure:

1. Determine the maximum operating temperature for that

channel (for example, 70°C).

2. Determine experimentally the fan speed (PWM duty cycle

value) that does not exceed the temperature at the worst-

case operating points. For example, 70°C is reached when

the fans are running at 50% PWM duty cycle.

3. Determine the slope of the required control loop to meet

these requirements.

4. Using the ADT7476 evaluation software, you can

graphically program and visualize this functionality. Ask

your local Analog Devices representative for details.

As PWMMIN is changed, the automatic fan control slope

changes.

MIN

100%

33%

PWM DUTY CYCLE

50%

30°C

05382-059

Figure 58. Adjusting PWMMIN Changes the Automatic Fan Control Slope

As TRANGE is changed, the slope changes. As TRANGE gets

smaller, the fans reach 100% speed with a smaller temperature

change.

05382-060

TMIN

TMIN–HYST

100%

PWM DUTY CYCLE

30°C

40°C

10%

45°C

54°C

Figure 59. Increasing TRANGE Changes the AFC slope

05382-061

100%

MAX

PWM

PWM DUTY CYCLE

TRANGE

10%

TMIN–HYST

Figure 60. Changing PWMMAX Does Not Change the AFC Slope

Selecting TRANGE

The TRANGE value can be selected for each temperature channel:

Remote 1, local, and Remote 2 temperature. Bits [7:4] (TRANGE)

of Register 0x5F to Register 0x61 define the TRANGE value for

each temperature channel.

ADT7476

Rev. A | Page 47 of 72

Table 17. Selecting a TRANGE Value

Bits [7:4]1 TRANGE (°C)

0000 2

0001 2.5

0010 3.33

0011 4

0100 5

0101 6.67

0110 8

0111 10

1000 13.33

1001 16

1010 20

1011 26.67

1100 32 (default)

1101 40

1110 53.33

1111 80

1 Register 0x5F configures Remote 1 TRANGE; Register 0x60 configures local

TRANGE; Register 0x61 configures Remote 2 TRANGE.

Actual Changes in PWM Output (Advance Acoustics

Settings)

While the automatic fan control algorithm describes the

general response of the PWM output, it is also necessary to

note the enhance acoustics registers (0x62 and 0x63) can be

used to set/clamp the maximum rate of change of PWM

output for a given temperature zone. This means that if

TRANGE is programmed with an AFC slope that is quite steep,

a relatively small change in temperature could cause a large

change in PWM output and possibly an audible change in

fan speed, which can be noticeable/annoying to end users.

Decreasing the speed the PWM output changes, by

programming the smoothing on the appropriate temperature

channels (Register 0x62 and Register 0x63), changes how fast

the fan speed increases/decreases in the event of a temperature

spike. The PWM duty cycle increases until the PWM duty cycle

reaches the appropriate duty cycle as defined by the AFC curve.

Figure 61 shows PWM duty cycle vs. temperature for each

TRANGE setting. The lower graph shows how each TRANGE setting

affects fan speed vs. temperature. As can be seen from the

graph, the effect on fan speed is nonlinear.

TEMPERATURE ABOVE TMIN

0 20406080100120

FAN SPEED (% OF MAX)

100

TEMPERATURE ABOVE TMIN

(B)

(A)

0 20406080100120

PWM DUTY CYCLE (%)

100

05382-062

2°C

80°C

53.3°C

40°C

32°C

26.6°C

20°C

16°C

13.3°C

10°C

8°C

6.67°C

5°C

4°C

3.33°C

2.5°C

2°

80°C

53.3°C

40°C

32°C

26.6°C

20°C

16°C

13.3°C

10°C

8°C

6.67°C

5°C

4°C

3.33°C

2.5°C

Figure 61. TRANGE vs. Actual Fan Speed (Not PWM Drive) Profile

The graphs in Figure 61 assume the fan starts from 0% PWM

duty cycle. Clearly, the minimum PWM duty cycle, PWMMIN,

needs to be factored in to see how the loop actually performs

in the system. Figure 62 shows how TRANGE is affected when

the PWMMIN value is set to 20%. It can be seen that the fan

actually runs at about 45% fan speed when the temperature

exceeds TMIN.

ADT7476

Rev. A | Page 48 of 72

TEMPERATURE ABOVE T

MIN

0 20 40 60 80 100 120

PWM DUTY CYCLE (%)

100

TEMPERATURE ABOVE T

MIN

(A)

(B)

0 20406080100120

FAN SPEED (% OF MAX)

100

05382-063

2°

80°C

53.3°C

40°C

32°C

26.6°C

20°C

16°C

13.3°C

10°C

8°C

6.67°C

5°C

4°C

3.33°C

2.5°C

2°C

80°C

53.3°C

40°C

32°C

26.6°C

20°C

16°C

13.3°C

10°C

8°C

6.67°C

5°C

4°C

3.33°C

2.5°C

Figure 62. TRANGE and % Fan Speed Slopes with PWMMIN = 20%

Example: Determining TRANGE for Each Temperature

Channel

The following example shows how the different TMIN and TRANGE

settings can be applied to three different thermal zones. In this

example, the following TRANGE values apply:

TRANGE = 80°C for ambient temperature

TRANGE = 53.33°C for CPU temperature

TRANGE = 40°C for VRM temperature

This example uses the MUX configuration described in Step 2,

with the ADT7476 connected as shown in Figure 52. Both CPU

temperature and VRM temperature drive the CPU fan con-

nected to PWM1. Ambient temperature drives the front chassis

fan and rear chassis fan connected to PWM2 and PWM3. The

front chassis fan is configured to run at PWMMIN = 20%. The

rear chassis fan is configured to run at PWMMIN = 30%. The

CPU fan is configured to run at PWMMIN = 10%.

Note: The control range for 4-wire fans is much wider than that

of 3-wire fans. In many cases, 4-wire fans can start with a PWM

drive of as little as 20% or less. In extreme cases, some 3-wire

fans cannot run unless a PWM drive of 60% or more is applied.

TEMPERATURE ABOVE TMIN

0 10203040 10050 60 70 80 90

PWM DUTY CYCLE (%)

100

TEMPERATURE ABOVE TMIN

FAN SPEED (% MAX RPM)

100

0 10203040 10050 60 70 80 90

05382-064

VRM TEMPERATURE

AMBIENT TEMPERATURE

CPU TEMPERATURE

VRM TEMPERATURE

CPU TEMPERATURE

AMBIENT TEMPERATURE

Figure 63. TRANGE and % Fan Speed Slopes for VRM, Ambient, and

CPU Temperature Channels

STEP 7: TTHERM FOR TEMPERATURE CHANNELS

TTHERM is the absolute maximum temperature allowed on a

temperature channel. Above this temperature, a component

such as the CPU or VRM might be operating beyond its safe

operating limit. When the temperature measured exceeds

TTHERM, all fans are driven at 100% PWM duty cycle (full speed)

to provide critical system cooling.

The fans remain running at 100% until the temperature drops

below TTHERM minus hysteresis, where hysteresis is the number

programmed into the hysteresis registers (0x6D and 0x6E). The

default hysteresis value is 4°C.

ADT7476

Rev. A | Page 49 of 72

The TTHERM limit should be considered the maximum worst-case

operating temperature of the system. Because exceeding any

TTHERM limit runs all fans at 100%, it has very negative acoustic

effects. Ultimately, this limit should be set up as a fail-safe, and

one should ensure that it is not exceeded under normal system

operating conditions.

Note that TTHERM limits are nonmaskable and affect the fan

speed no matter how automatic fan control settings are

configured. This allows some flexibility, because a TRANGE value

can be selected based on its slope, while a hard limit (such as

70°C), can be programmed as TMAX (the temperature at which

the fan reaches full speed) by setting TTHERM to that limit (for

example, 70°C).

THERM Registers

THERM Hysteresis

THERM hysteresis on a particular channel is configured via the

hysteresis settings below (Register 0x6D and Register 0x6E). For

example, setting hysteresis on the Remote 1 channel also sets

the hysteresis on Remote 1 THERM.

Hysteresis Registers

Bits [7:4], Remote 1 Temperature hysteresis (4°C default).

Bits [3:0], Local Temperature hysteresis (4°C default).

Bits [7:4], Remote 2 Temperature hysteresis (4°C default).

Because each hysteresis setting is four bits, hysteresis values

are programmable from 1°C to 15°C. It is not recommended

that hysteresis values ever be programmed to 0°C, because this

disables hysteresis. In effect, this would cause the fans to cycle

(during a THERM event) between normal speed and 100%

speed, or, while operating close to TMIN, between normal speed

and off, creating unsettling acoustic noise.

05382-065

MIN

PWM DUTYCYCLE

100%

THERM

RANGE

REAR CHASSIS

FRONT CHASSIS

CPU FAN SINK

LOCAL =

VRM TEMP

PWM1

PWM2

TACH1

TACH2

TACH3

PWM3

REMOTE 1 =

AMBIENT TEMP

REMOTE 2 =

CPU TEMP

MUX

THERMAL CALIBRATION

MIN

RANGE

THERMAL CALIBRATION 100%

MIN

RANGE

THERMAL CALIBRATION 100%

MIN

RANGE

PWM

MIN

PWM

GENERATOR

PWM

MIN

PWM

GENERATOR

TACHOMETER 3

AND 4

MEASUREMENT

PWM

MIN

TACHOMETER 1

MEASUREMENT

TACHOMETER 2

MEASUREMENT

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

PWM

GENERATOR

100%

PWM

CONFIG

PWM

CONFIG

PWM

CONFIG

Figure 64. How TTHERM Relates to Automatic Fan Control

ADT7476

Rev. A | Page 50 of 72

STEP 8: THYST FOR TEMPERATURE CHANNELS

THYST is the amount of extra cooling a fan provides after the

temperature measured has dropped back below TMIN before the

fan turns off. The premise for temperature hysteresis (THYST) is

that, without it, the fan would merely chatter, or cycle on and

off regularly, whenever the temperature is hovering at about the

TMIN setting.

The THYST value chosen determines the amount of time needed

for the system to cool down or heat up as the fan turns on and

off. Values of hysteresis are programmable in the range 1°C to

15°C. Larger values of THYST prevent the fans from chattering on

and off. The THYST default value is set at 4°C.

The THYST setting applies not only to the temperature hysteresis

for fan on/off, but the same setting is used for the TTHERM

hysteresis value, described in Step 6. Therefore, programming

on/off and the THERM function.

In some applications, it is required that fans not turn off below

TMIN, but remain running at PWMMIN. Bits [7:5] of Enhance

Acoustics Register 1 (0x62) allow the fans to be turned off or to

be kept spinning below TMIN. If the fans are always on, the THYST

value has no effect on the fan when the temperature drops

below TMIN.

THERM Hysteresis

Any hysteresis programmed via Register 0x6D and

THERM channel.

05382-066

REAR CHASSIS

FRONT CHASSIS

CPU FAN SINK

LOCAL =

VRM TEMP

PWM1

PWM2

TACH1

TACH2

TACH3

PWM3

REMOTE 1 =

AMBIENT TEMP

REMOTE 2 =

CPU TEMP

MUX

THERMAL CALIBRATION

TMIN TRANGE

THERMAL CALIBRATION 100%

TMIN TRANGE

THERMAL CALIBRATION 100%

TMIN TRANGE

PWM

MIN

PWM

MIN

PWM

MIN

100%

TMIN

PWM DUTYCYCLE

100%

TRANGE

TTHERM

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

RAMP

CONTROL

(ACOUSTIC

ENHANCEMENT)

PWM

GENERATOR

PWM

GENERATOR

TACHOMETER 3

AND 4

MEASUREMENT

TACHOMETER 1

MEASUREMENT

TACHOMETER 2

MEASUREMENT

PWM

GENERATOR

PWM

CONFIG

PWM

CONFIG

PWM

CONFIG

Figure 65. The THYST Value Applies to Fan On/Off Hysteresis and THERM Hysteresis

ADT7476

Rev. A | Page 51 of 72

Enhance Acoustics Register 1 (Reg. 0x62)

Bit 7 MIN3 = 0, PWM3 is off (0% PWM duty cycle) when

temperature is below TMIN − THYST.

Bit 7 MIN3 = 1, PWM3 runs at PWM3 minimum duty cycle

below TMIN − THYST.

Bit 6 MIN2 = 0, PWM2 is off (0% PWM duty cycle) when

temperature is below TMIN − THYST.

Bit 6 MIN2 = 1, PWM2 runs at PWM2 minimum duty cycle

below TMIN − THYST.

Bit 5 MIN1 = 0, PWM1 is off (0% PWM duty cycle) when

temperature is below TMIN − THYST.

Bit 5 MIN1 = 1, PWM1 runs at PWM1 minimum duty cycle

below TMIN − THYST.

Configuration Register 6 (0x10)

Bit 0 SLOW, 1 slows the ramp rate for PWM changes associated

with the Remote 1 temperature channel by 4. Configuration

Bit 1 SLOW, 1 slows the ramp rate for PWM changes associated

with the local temperature channel by 4.

Configuration Register 6 (0x10)

Bit 2 SLOW, 1 slows the ramp rate for PWM changes associated

with the Remote 2 temperature channel by 4.

Configuration Register 6 (0x10)

Bit 7 ExtraSlow, 1 slows the ramp rate for all fans by a factor

of 39.2%.

The following sections list the ramp-up times when the

SLOW bit is set for each temperature monitoring channel.

Enhance Acoustics Register 1 (0x62)

Bits [2:0] ACOU, selects the ramp rate for PWM outputs

associated with the Remote Temperature 1 input.

000 = 37.5 seconds

001 = 18.8 seconds

010 = 12.5 seconds

011 = 7.5 seconds

100 = 4.7 seconds

101 = 3.1 seconds

110 = 1.6 seconds

111 = 0.8 seconds

Enhance Acoustics Register 2 (0x63)

Bits [2:0] ACOU3, selects the ramp rate for PWM outputs

associated with the local temperature channel.

000 = 37.5 sec

001 = 18.8 sec

010 = 12.5 seconds

011 = 7.5 seconds

100 = 4.7 seconds

101 = 3.1 seconds

110 = 1.6 seconds

111 = 0.8 seconds

Bits [6:4] ACOU2, selects the ramp rate for PWM outputs

associated with the Remote 2 temperature input.

000 = 37.5 seconds

001 = 18.8 seconds

010 = 12.5 seconds

011 = 7.5 seconds

100 = 4.7 seconds

101 = 3.1 seconds

110 = 1.6 seconds

111 = 0.8 seconds

When Bit 7 of Configuration Register 6 (0x10) = 1, the above

ramp rates change to the following values:

000 = 52.2 seconds

001 = 26.1 seconds

010 = 17.4 seconds

011 = 10.4 seconds

100 = 6.5 seconds

101 = 4.4 seconds

110 = 2.2 seconds

111 = 1.1 seconds

Setting the appropriate slow bit, Bits [2:0] of Configuration

FAN PRESENCE DETECT

This feature is used to determine if a 4-wire fan is directly

connected to a PWM output. This feature does not work for

3-wire fans. To detect whether a 4-wire fan is connected

directly to a PWM output, the following must be performed

in this order:

1. Drive the appropriate PWM outputs to 100% duty cycle.

2. Set Bit 0 of Configuration Register 2 (0x73).

3. Wait 5 ms.

4. Program fans to run at a different speed if necessary.

5. Read the state of Bits [3:1] of Configuration Register 2

(0x73). The state of these bits reflects whether a 4-wire fan

is connected directly to the PWM output.

As the detection time only takes 5 ms, programming the

PWM outputs to 100% and then back to its normal speed is

not noticeable, in most cases.

ADT7476

Rev. A | Page 52 of 72

How Fan Presence Detect Works

4-wire fans typically have an internal pull-up to 4.75 V ±10%,

which typically sources 5 mA. While the detection cycle is on,

an internal current sink is turned on, sinking current from the

fan’s internal pull-up. By driving some of the current from the

fan’s internal pull-up (~100 µA) the logic buffer switches to a

defined logic state. If this state is high, a fan is present; if the

state is low, no fan is present.

Note: The PWM input voltage should be clamped to 3.3 V. This

ensures the PWM output is not pulled to a voltage higher than

the maximum allowable voltage on that pin (3.6 V).

FAN SYNC

When two ADT7476s are used in a system, it is possible to

synchronize them so that one PWM channel from each device

can be effectively OR’ed together to create a PWM output that

reflects the maximum speed of the two OR’ed PWMs. This

OR’ed PWM can in turn be used to drive a chassis fan. See

the Analog Devices website, located at www.analog.com, for

information on the Fan SYNC function.

STANDBY MODE

The ADT7476 has been specifically designed to respond to the

STBY supply. In computers that support S3 and S5 states, the

core voltage of the processor is lowered in these states. When

monitoring THERM, the THERM timer should be disabled

during these states.

When the VCCP voltage drops below the VCCP low limit, the

following occurs:

1. Status Bit 1 (VCCP) in Status Register 1 is set.

2. SMBALERT is generated, if enabled.

3. THERM monitoring is disabled. The THERM timer

should hold its value prior to the S3 or S5 state.

Once the core voltage, VCCP, goes above the VCCP low limit,

everything is re-enabled and the system resumes normal

operation.

XNOR TREE TEST MODE

The ADT7476 includes an XNOR tree test mode. This mode

is useful for in-circuit test equipment at board-level testing. By

applying stimulus to the pins included in the XNOR tree, it is

possible to detect opens, or shorts, on the system board.

The XNOR tree test is invoked by setting Bit 0 (XEN) of the

XNOR tree test enable register (0x6F).

Figure 66 shows the signals that are exercised in the XNOR tree

test mode.

PWM1/XTO

PWM3

PWM2

TACH4

TACH3

TACH2

TACH1

VID4

VID3

VID2

VID1

VID0

05382-067

Figure 66. XNOR Tree Test

POWER-ON DEFAULT

When the ADT7476 is powered up, monitoring is off by default

and the PWM outputs go to 100%. All necessary registers then

need to be configured via the SMBus for the appropriate

functions to operate.

ADT7476

Rev. A | Page 53 of 72

Table 18. ADT7476 Registers

Address R/W Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Lockable

0x10 R/W

Configuration

ExtraSlow VCCP

Low

MasterEn SlaveEn

THERM in

Manual

SLOW

Remote 2

SLOW

Local

SLOW Remote

0x00 Yes

0x11 R

Configuration

RES RES RES RES RES RES RES DisTHERMHys 0x00 Yes

0x20 R

2.5 V

Measurement

9 8 7 6 5 4 3 2 0x00

0x21 R

VCCP

Measurement

9 8 7 6 5 4 3 2 0x00

0x22 R

VCC

Measurement

9 8 7 6 5 4 3 2 0x00

0x23 R

5 V

Measurement

9 8 7 6 5 4 3 2 0x00

0x24 R

12 V

Measurement

9 8 7 6 5 4 3 2 0x00

0x25 R

Remote 1

Temperature

9 8 7 6 5 4 3 2 0x80

0x26 R

Local

Temperature

9 8 7 6 5 4 3 2 0x80

0x27 R

Remote 2

Temperature

9 8 7 6 5 4 3 2 0x80

0x28 R

TACH1 Low

Byte

7 6 5 4 3 2 1 0 0x00

0x29 R

TACH1 High

Byte

15 14 13 12 11 10 9 8 0x00

0x2A R

TACH2 Low

Byte

7 6 5 4 3 2 1 0 0x00

0x2B R

TACH2 High

Byte

15 14 13 12 11 10 9 8 0x00

0x2C R

TACH3 Low

Byte

7 6 5 4 3 2 1 0 0x00

0x2D R

TACH3 High

Byte

15 14 13 12 11 10 9 8 0x00

0x2E R

TACH4 Low

Byte

7 6 5 4 3 2 1 0 0x00

0x2F R

TACH4 High

Byte

15 14 13 12 11 10 9 8 0x00

0x30 R/W

PWM1 Current

Duty Cycle

7 6 5 4 3 2 1 0 0xFF

0x31 R/W

PWM2 Current

Duty Cycle

7 6 5 4 3 2 1 0 0xFF

0x32 R/W

PWM3 Current

Duty Cycle

7 6 5 4 3 2 1 0 0xFF

0x38 R/W

PWM1 Max

Duty Cycle

7 6 5 4 3 2 1 0 0xFF Yes

0x39 R/W

PWM2 Max

Duty Cycle

7 6 5 4 3 2 1 0 0xFF Yes

0x3A R/W

PWM3 Max

Duty Cycle

7 6 5 4 3 2 1 0 0xFF Yes

0x3D R

Device ID

7 6 5 4 3 2 1 0 0x76

0x3E R

Company ID

Number

7 6 5 4 3 2 1 0 0x41

0x40 R/W

Configuration

RES TODIS FSPDIS Vx1 FSPD RDY LOCK STRT 0x04 Yes

0x41 R

Interrupt

Status

OOL R2T LT R1T 5 V VCC VCCP 2.5 V/THERM 0x00

ADT7476

Rev. A | Page 54 of 72

Address R/W Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Lockable

0x42 R

Interrupt

Status

D2 FAULT D1

FAULT

F4P/GPIO4 FAN3 FAN2 FAN1 OVT 12 V/VC 0x00

0x43 R/W VID Code VIDSEL THLD VID5 VID4 VID3 VID2 VID1 VID0 0x1F

0x44 R/W

2.5 V Low

Limit

7 6 5 4 3 2 1 0 0x00

0x45 R/W

2.5 V High

Limit

7 6 5 4 3 2 1 0 0xFF

0x46 R/W VCCP Low Limit 7 6 5 4 3 2 1 0 0x00

0x47 R/W VCCP High Limit 7 6 5 4 3 2 1 0 0xFF

0x48 R/W VCC Low Limit 7 6 5 4 3 2 1 0 0x00

0x49 R/W VCC High Limit 7 6 5 4 3 2 1 0 0xFF

0x4A R/W 5 V Low Limit 7 6 5 4 3 2 1 0 0x00

0x4B R/W 5 V High Limit 7 6 5 4 3 2 1 0 0xFF

0x4C R/W 12 V Low Limit 7 6 5 4 3 2 1 0 0x00

0x4D R/W

12 V High

Limit

7 6 5 4 3 2 1 0 0xFF

0x4E R/W

Remote 1

Temp Low

Limit

7 6 5 4 3 2 1 0 0x81

0x4F R/W

Remote 1

Temp High

Limit

7 6 5 4 3 2 1 0 0x7F

0x50 R/W

Local Temp

Low Limit

7 6 5 4 3 2 1 0 0x81

0x51 R/W Local Temp

High Limit

7 6 5 4 3 2 1 0 0x7F

0x52 R/W

Remote 2

Temp Low

Limit

7 6 5 4 3 2 1 0 0x81

0x53 R/W

Remote 2

Temp High

Limit

7 6 5 4 3 2 1 0 0x7F

0x54 R/W

TACH1

Minimum Low

Byte

7 6 5 4 3 2 1 0 0xFF

0x55 R/W

TACH1

Minimum

High Byte

15 14 13 12 11 10 9 8 0xFF

0x56 R/W

TACH2

Minimum Low

Byte

7 6 5 4 3 2 1 0 0xFF

0x57 R/W

TACH2

Minimum

High Byte

15 14 13 12 11 10 9 8 0xFF

0x58 R/W

TACH3

Minimum Low

Byte

7 6 5 4 3 2 1 0 0xFF

0x59 R/W

TACH3

Minimum

High Byte

15 14 13 12 11 10 9 8 0xFF

0x5A R/W

TACH4

Minimum Low

Byte

7 6 5 4 3 2 1 0 0xFF

0x5B R/W

TACH4

Minimum

High Byte

15 14 13 12 11 10 9 8 0xFF

0x5C R/W

PWM1

Configuration

BHVR BHVR BHVR INV RES SPIN SPIN SPIN 0x62 Yes

0x5D R/W

PWM2

Configuration

BHVR BHVR BHVR INV RES SPIN SPIN SPIN 0x62 Yes

ADT7476

Rev. A | Page 55 of 72

Address R/W Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Lockable

0x5E R/W

PWM3

Configuration

BHVR BHVR BHVR INV RES SPIN SPIN SPIN 0x62 Yes

0x5F R/W

Remote 1

TRANGE/PWM1

Frequency

RANGE RANGE RANGE RANGE HF/LF FREQ FREQ FREQ 0XC4 Yes

0x60 R/W

Local

TRANGE/PWM2

Frequency

RANGE RANGE RANGE RANGE HF/LF FREQ FREQ FREQ 0XC4 Yes

0x61 R/W

Remote 2

TRANGE/PWM3

Frequency

RANGE RANGE RANGE RANGE HF/LF FREQ FREQ FREQ 0XC4 Yes

0x62 R/W

Enhance

Acoustics Reg.

MIN3 MIN2 MIN1 SYNC EN1 ACOU ACOU ACOU 0X00 Yes

0x63 R/W

Enhance

Acoustics Reg.

EN2 ACOU2 ACOU2 ACOU2 EN3 ACOU3 ACOU3 ACOU3 0X00 Yes

0x64 R/W

PWM1 Min

Duty Cycle

7 6 5 4 3 2 1 0 0X80 Yes

0x65 R/W

PWM2 Min

Duty Cycle

7 6 5 4 3 2 1 0 0X80 Yes

0x66 R/W

PWM3 Min

Duty Cycle

7 6 5 4 3 2 1 0 0X80 Yes

0x67 R/W

Remote 1

Temp TMIN

7 6 5 4 3 2 1 0 0X5A Yes

0x68 R/W

Local Temp

TMIN

7 6 5 4 3 2 1 0 0X5A Yes

0x69 R/W

Remote 2

Temp TMIN

7 6 5 4 3 2 1 0 0X5A Yes

0x6A R/W

Remote 1

THERM Temp

Limit

7 6 5 4 3 2 1 0 0X64 Yes

0x6B R/W

Local THERM

Temp Limit

7 6 5 4 3 2 1 0 0X64 Yes

0x6C R/W

Remote 2

THERM Temp

Limit

7 6 5 4 3 2 1 0 0X64 Yes

0x6D R/W

Remote 1 and

Local

Temp/TMIN

Hysteresis

HYSR1 HYSR1 HYSR1 HYSR1 HYSL HYSL HYSL HYSL 0X44 Yes

0x6E R/W

Remote 2

Temp/TMIN

Hysteresis

HYSR2 HYSR2 HYSR2 HYRS RES RES RES RES 0X40 Yes

0x6F R/W

XNOR Tree

Test Enable

RES RES RES RES RES RES RES XEN 0X00 Yes

0x70 R/W

Remote 1

Temperature

Offset

7 6 5 4 3 2 1 0 0X00 Yes

0x71 R/W

Local

Temperature

Offset

7 6 5 4 3 2 1 0 0X00 Yes

0x72 R/W

Remote 2

Temperature

Offset

7 6 5 4 3 2 1 0 0X00 Yes

0x73 R/W

Configuration

RES CONV ATTN AVG Fan3Detect Fan2Detect Fan1Detect FanPresenceDT 0X00 Yes

0x74 R/W

Interrupt Mask

OOL R2T LT R1T 5 V VCC VCCP 2.5 V/ THERM 0X00

0x75 R/W

Interrupt Mask

D2 D1 F4P FAN3 FAN2 FAN1 OVT 12 V/VC 0X00

0x76 R/W

Extended

Resolution 1

5 V 5 V VCC VCC VCCP VCCP 2.5 V 2.5 V 0X00

0x77 R/W

Extended

Resolution 2

TDM2 TDM2 LTMP LTMP TDM1 TDM1 12 V 12 V 0X00

ADT7476

Rev. A | Page 56 of 72

Address R/W Description Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Lockable

0x78 R/W

Configuration

DC4 DC3 DC2 DC1 FAST BOOST THERM/

2.5V

ALERT Enable 0x00 Yes

0x79 R

THERM Timer

Status

TMR TMR TMR TMR TMR TMR TMR ASRT/TMRO 0x00

0x7A R/W

THERM Timer

Limit

LIMT LIMT LIMT LIMT LIMT LIMT LIMT LIMT 0x00

0x7B R/W

TACH Pulses

per Revolution

FAN4 FAN4 FAN3 FAN3 FAN2 FAN2 FAN1 FAN1 0x55

0x7C R/W

Configurations

THERM

O/P Only

Local

THERM

O/P

Only

R1 THERM

O/P Only

VID/

GPIO

GPIO6P GPIO6D Temp

Offset

TWOS COMPL 0x01 Yes

0x7D R/W

Configuration

BpAtt

12 V

BpAtt

5 V

BpAtt VCCP BpAtt

2.5 V

Max/Full

on THERM

THERM

Disable

Pin14Func Pin14Func 0x00 Yes

0x7E R Test 1 Do not write to these registers 0x00 Yes

0x7F R Test 2 Do not write to these registers 0x00 Yes

Table 19. Register 0x10—Configuration Register 6 (Power-On Default = 0x00)1, 2

Bit Name R/W Description

[0] SlowFan

Remote 1

R/W When this bit is set, Fan 1 smoothing times are multiplied ×4 for Remote 1 temperature channel

(as defined in Register 0x62).

[1] SlowFan

Local

R/W When this bit is set, Fan 2 smoothing times are multiplied ×4 for local temperature channel (as defined

in Register 0x63).

[2] SlowFan

Remote 2

R/W When this bit is set, Fan 3 smoothing times are multiplied ×4 for Remote 2 temperature channel

(as defined in Register 0x63).

[3] THERM in

Manual

R/W When this bit is set, THERM is enabled in manual mode.1

[4] SlaveEn R/W Setting this bit configures the ADT7476 as a slave for use in fan sync mode.

[5] MasterEn R/W Setting this bit configures the ADT7476 as a master for use in fan sync mode.

[6] VccpLow R/W VCCPLO = 1. When the power is supplied from 3.3 V STANDBY and the core voltage (VCCP) drops below

its VCCP low limit value (Register 0x46), the following occurs:

• Status Bit 1 in Status Register 1 is set.

• SMBALERT is generated, if enabled.

• PROCHOT monitoring is disabled.

• Everything is re-enabled once VCCP increases above the VCCP low limit.

When VCCP increases above the low limit:

• PROCHOT monitoring is enabled.

• Fans return to their programmed state after a spin-up cycle.

[7] ExtraSlow R/W When this bit is set, all fan smoothing times are increased by a further 39.2%

1 A THERM event always overrides any fan setting (even when fans are disabled).

2 This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.

Table 20. Register 0x11—Configuration Register 7 (Power-On Default = 0x00)1

Bit Name R/W Description

[0] DisTHERMHys R/W Setting this bit to 1 disables THERM hysteresis.

[7:1] Reserved N/A Reserved. Do not write to these bits.

1 This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.

ADT7476

Rev. A | Page 57 of 72

Table 21. Voltage Reading Registers (Power-On Default = 0x00)1

0x20 Read-only Reflects the voltage measurement at the 2.5 V input on Pin 22 (8 MSBs of reading).

0x21 Read-only Reflects the voltage measurement at the VCCP input on Pin 23 (8 MSBs of reading).2

0x22 Read-only Reflects the voltage measurement at the VCC input on Pin 4 (8 MSBs of reading).3

0x23 Read-only Reflects the voltage measurement at the 5 V input on Pin 20 (8 MSBs of reading).

0x24 Read-only Reflects the voltage measurement at the 12 V input on Pin 21 (8 MSBs of reading).

1 If the extended resolution bits of these readings are also being read, the extended resolution registers (0x76, 0x77) must be read first. Once the extended resolution

registers have been read, the associated MSB reading registers are frozen until read. Both the extended resolution registers and the MSB registers are frozen.

2 If VCCPLow (Bit 7 of Register 0x40) is set, VCCP can control the sleep state of the ADT7476.

3 VCC (Pin 4) is the supply voltage for the ADT7476.

Table 22. Temperature Reading Registers (Power-On Default = 0x80)1, 2, 3

0x25 Read-only Remote 1 temperature reading (8 MSBs of reading). 3, 4

0x26 Read-only Local temperature reading (8 MSBs of reading).

0x27 Read-only Remote 2 temperature reading (8 MSBs of reading). 3, 4

1 If the extended resolution bits of these readings are also being read, the extended resolution registers (Reg. 0x76, 0x77) must be read first. Once the extended

resolution registers have been read, all associated MSB reading registers are frozen until read. Both the extended resolution registers and the MSB registers are frozen.

2 These temperature readings can be in twos complement or Offset 64 format; this interpretation is determined by Bit 0 of Configuration Register 5 (0x7C).

3 In twos complement mode, a temperature reading of −128°C (0x80) indicates a diode fault (open or short) on that channel.

4 In Offset 64 mode, a temperature reading of −64°C (0x00) indicates a diode fault (open or short) on that channel.

Table 23. Fan Tachometer Reading Registers (Power-On Default = 0x00)1

0x28 Read-only TACH1 low byte.

0x29 Read-only TACH1 high byte.

0x2A Read-only TACH2 low byte.

0x2B Read-only TACH2 high byte.

0x2C Read-only TACH3 low byte.

0x2D Read-only TACH3 high byte.

0x2E Read-only TACH4 low byte.

0x2F Read-only TACH4 high byte.

1 These registers count the number of 11.11 μs periods (based on an internal 90 kHz clock) that occur between a number of consecutive fan TACH pulses (default = 2).

The number of TACH pulses used to count can be changed using the fan pulses per revolution register (0x7B). This allows the fan speed to be accurately measured.

Because a valid fan tachometer reading requires that two bytes are read, the low byte must be read first. Both the low and high bytes are then frozen until read. At

power-on, these registers contain 0x0000 until such time as the first valid fan TACH measurement is read into these registers. This prevents false interrupts from

occurring while the fans are spinning up. A count of 0xFFFF indicates that a fan is one of the following:

• Stalled or blocked (object jamming the fan).

• Failed (internal circuitry destroyed).

• Not populated. (The ADT7476 expects to see a fan connected to each TACH. If a fan is not connected to that TACH, its TACH minimum high and low bytes should

be set to 0xFFFF.)

• Alternate function, for example, TACH4 reconfigured as THERM pin.

Table 24. Current PWM Duty Cycle Registers (Power-On Default = 0xFF)1

0x30 R/W PWM1 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF).

0x31 R/W PWM2 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF).

0x32 R/W PWM3 current duty cycle (0% to 100% duty cycle = 0x00 to 0xFF).

1 These registers reflect the PWM duty cycle driving each fan at any given time. When in automatic fan speed control mode, the ADT7476 reports the PWM duty cycles

back through these registers. The PWM duty cycle values vary according to temperature in automatic fan speed control mode. During fan startup, these registers

report back 0x00. In manual mode, the PWM duty cycle outputs can be set to any duty cycle value by writing to these registers.

ADT7476

Rev. A | Page 58 of 72

Table 25. Maximum PWM Duty Cycle (Power-On Default = 0xFF)1, 2

0x38 R/W Maximum duty cycle for PWM1 output, default = 100% (0xFF.)

0x39 R/W Maximum duty cycle for PWM2 output, default = 100% (0xFF).

0x3A R/W Maximum duty cycle for PWM3 output, default = 100% (0xFF).

1 These registers set the maximum PWM duty cycle of the PWM output.

2 This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.

Table 26. Register 0x40—Configuration Register 1 (Power-On Default = 0x04)

Bit Name R/W Description

[0] STRTT

1, 2R/W Logic 1 enables monitoring and PWM control outputs based on the limit settings programmed.

Logic 0 disables monitoring and PWM control based on the default power-up limit settings.

Note that the limit values programmed are preserved even if a Logic 0 is written to this bit and the

default settings are enabled. This bit does not become locked once Bit 1 (LOCK bit) has been set.

[1] LOCK Write once Logic 1 locks all limit values to their current settings. Once this bit is set, all lockable registers become

read-only and cannot be modified until the ADT7476 is powered down and powered up again. This

prevents rogue programs such as viruses from modifying critical system limit settings. (This bit is

lockable.)

[2] RDY Read-only This bit is set to 1 by the ADT7476 to indicate only that the device is fully powered up and ready to begin

system monitoring.

[3] FSPD R/W When set to 1, this bit runs all fans at maximum speed as programmed in the maximum PWM duty cycle

registers (0x30 to 0x32). Power-on default = 0. This bit is not locked at any time.

[4] Vx1 R/W BIOS should set this bit to a 1 when the ADT7476 is configured to measure current from an ADI ADOPT™

VRM controller and to measure the CPU’s core voltage. This bit allows monitoring software to display

CPU watts usage. (This bit is lockable.)

[5] FSPDIS R/W Logic 1 disables fan spin-up for two TACH pulses. Instead, the PWM outputs go high for the entire fan

spin-up timeout selected.

[6] TODIS R/W When this bit is set to 1, the SMBus timeout feature is enabled.

In this state, if at any point during an SMBus transaction involving the ADT7476 activity ceases for more

than 35 ms, the ADT7476 assumes the bus is locked and releases the bus. This allows the ADT7476 to be

used with SMBus controllers that cannot handle SMBus timeouts. (This bit is lockable.)

1 Bit 0 (STRT) of Configuration Register 1 (0x40) remains writable after lock bit is set.

2 When monitoring (STRT) is disabled, PWM outputs always go to 100% for thermal protection.

Table 27. Register 0x41—Interrupt Status Register 1 (Power-On Default = 0x00)

Bit Name R/W Description

[0] 2.5 V/

THERM

timer

Read-only 2.5 V = 1 indicates that the 2.5 V high or low limit has been exceeded. This bit is cleared on a read of the

status register only if the error condition has subsided. If Pin 22 is configured as THERM, this bit is

asserted when the timer limit has been exceeded.

[1] VCCP Read-only VCCP = 1 indicates that the VCCP high or low limit has been exceeded. This bit is cleared on a read of the

status register only if the error condition has subsided.

[2] VCC Read-only VCC = 1 indicates that the VCC high or low limit has been exceeded. This bit is cleared on a read of the

status register only if the error condition has subsided.

[3] 5 V Read-only A 1 indicates the 5 V high or low limit has been exceeded. This bit is cleared on a read of the status

[4] R1T Read-only R1T = 1 indicates that the Remote 1 low or high temperature has been exceeded. This bit is cleared on a

read of the status register only if the error condition has subsided.

[5] LT Read-only LT = 1 indicates that the local low or high temperature has been exceeded. This bit is cleared on a read of

the status register only if the error condition has subsided.

ADT7476

Rev. A | Page 59 of 72

Bit Name R/W Description

[6] R2T Read-only R2T = 1 indicates that the Remote 2 low or high temperature has been exceeded. This bit is cleared on a

read of the status register only if the error condition has subsided.

[7] OOL Read-only OOL = 1 indicates that an out-of-limit event has been latched in Interrupt Status Register 2. This bit is a

logical OR of all status bits in Interrupt Status Register 2. Software can test this bit in isolation to

determine whether any of the voltage, temperature, or fan speed readings represented by Interrupt

Status Register 2 are out-of-limit, which saves the need to read Interrupt Status Register 2 during every

interrupt or polling cycle.

OOL = 0, then when one or more alerts are generated in Interrupt Status Register 2, assuming all the

mask bits in the Interrupt Mask Register 2 (0x75) =1, SMBALERT is still asserted.

OOL = 1, then when one or more alerts are generated in Interrupt Status Register 2, assuming all the

mask bits in the Interrupt Mask Register 2 (0x75) =1, SMBALERT is not asserted.

Table 28. Register 0x42—Interrupt Status Register 2 (Power-On Default = 0x00)

Bit Name R/W Description

[0] 12V/VC Read-only A 1 indicates that the 12 V high or low limit has been exceeded. This bit is cleared on a read of the status

This bit is set when the levels on VID0 to VID5 are different than they were 11 μs previously. This pin can be

used to generate an SMBALERT whenever the VID code changes.

[1] OVT Read-only OVT = 1 indicates that one of the THERM overtemperature limits has been exceeded. This bit is cleared on a

read of the status register when the temperature drops below THERM − THYST.

[2] FAN1 Read-only

FAN1 = 1 indicates that Fan 1 has dropped below minimum speed or has stalled. This bit is not set when

the PWM 1 output is off.

[3] FAN2 Read-only FAN2 = 1 indicates that Fan 2 has dropped below minimum speed or has stalled. This bit is not set when

the PWM 2 output is off.

[4] FAN3 Read-only FAN3 = 1 indicates that Fan 3 has dropped below minimum speed or has stalled. This bit is not set when

the PWM 3 output is off.

[5] F4P Read-only When Pin 14 is programmed as a TACH4 input, F4P = 1 indicates that Fan 4 has dropped below minimum

speed or has stalled. This bit is not set when the PWM3 output is off.

R/W When Pin 14 is programmed as the GPIO6 output, writing to this bit determines the logic output of GPIO6.

When GPIO6 is programmed as an input, this bit reflects the value read by GPIO6.

Read-only

If Pin 14 is configured as the THERM timer input for THERM monitoring, then this bit is set when the THERM

assertion time exceeds the limit programmed in the THERM limit register (Reg. 0x7A).

[6] D1 Read-only D1 = 1 indicates either an open or short circuit on the Thermal Diode 1 inputs.

[7] D2 Read-only D2 = 1 indicates either an open or short circuit on the Thermal Diode 2 inputs.

Table 29. Register 43H—VID Register (Power-On Default = 0x1F )

Bit Name R/W Description

[4:0] VID/GPIO Read-

only

The VID inputs from the CPU indicate the expected processor core voltage. On power-up, these bits

reflect the state of the VID pins, even if monitoring is not enabled.

When enabled as a GPO, these bits are writable.

[5] VID5/GPIO

Read-

only

Reads VID5 from the CPU when Bit 7 = 1. If Bit 7 = 0, the VID5 bit always reads back 0 (power-on default).

When enabled as a GPO, this bit is writable.

[6] THLD R/W Selects the input switching threshold for the VID inputs.

THLD = 0 selects a threshold of 1 V (VOL < 0.8 V, VIH > 1.7 V).

THLD = 1 lowers the switching threshold to 0.6 V (VOL < 0.4 V, VIH > 0.8 V).

[7] VIDSEL R/W VIDSEL = 0 configures Pin 21 as the 12 V measurement input (default).

ADT7476

Rev. A | Page 60 of 72

Table 30. Voltage Limit Registers1

0x44 R/W 2.5 V low limit 0x00

0x45 R/W 2.5 V high limit 0xFF

0x46 R/W VCCP low limit 0x00

0x47 R/W VCCP high limit 0xFF

0x48 R/W VCC low limit 0x00

0x49 R/W VCC high limit 0xFF

0x4A R/W 5 V low limit 0x00

0x4B R/W 5 V high limit 0xFF

0x4C R/W 12 V low limit 0x00

0x4D R/W 12 V high limit 0xFF

1 Setting the Configuration Register 1 lock bit has no effect on these registers.

2 High limits: An interrupt is generated when a value exceeds its high limit (>comparison). Low limits: An interrupt is generated when a value is equal to or below its low

limit (≤comparison).

Table 31. Temperature Limit Registers1

0x4E R/W Remote 1 temperature low limit 0x81

0x4F R/W Remote 1 temperature high limit 0x7F

0x50 R/W Local temperature low limit 0x81

0x51 R/W Local temperature high limit 0x7F

0x52 R/W Remote 2 temperature low limit 0x81

0x53 R/W Remote 2 temperature high limit 0x7F

1 Exceeding any of these temperature limits by 1°C causes the appropriate status bit to be set in the interrupt status register. Setting the Configuration Register 1 lock

bit has no effect on these registers.

2 High limits: An interrupt is generated when a value exceeds its high limit (>comparison). Low limits: An interrupt is generated when a value is equal to or below its low

limit (≤comparison).

Table 32. Fan Tachometer Limit Registers1

0x54 R/W TACH1 minimum low byte 0xFF

0x55 R/W TACH1 minimum high byte/single-channel ADC

channel select

0xFF

0x56 R/W TACH2 minimum low byte 0xFF

0x57 R/W TACH2 minimum high byte 0xFF

0x58 R/W TACH3 minimum low byte 0xFF

0x59 R/W TACH3 minimum high byte 0xFF

0x5A R/W TACH4 minimum low byte 0xFF

0x5B R/W TACH4 minimum high byte 0xFF

1 Exceeding any of the TACH limit registers by 1 indicates that the fan is running too slowly or has stalled. The appropriate status bit is set in Interrupt Status Register 2

to indicate the fan failure. Setting the Configuration Register 1 lock bit has no effect on these registers.

Table 33. Register 0x55—TACH 1 Minimum High Byte (Power-On Default = 0xFF)

Bits Name R/W Description

[4:0] Reserved Read-only

These bits are reserved when Bit 6 of Configuration Register 2 (0x73) is set (single-channel ADC mode).

Otherwise, these bits represent Bits [4:0] of the TACH1 minimum high byte.

[7:5] SCADC R/W When Bit 6 of Configuration Register 2 (0x73) is set (single-channel ADC mode), these bits are used to

select the only channel from which the ADC takes measurements. Otherwise, these bits represent Bits

[7:5] of the TACH1 minimum high byte.

ADT7476

Rev. A | Page 61 of 72

Table 34. PWM Configuration Registers

0x5C R/W PWM1 configuration 0x62

0x5D R/W PWM2 configuration 0x62

0x5E R/W PWM3 configuration 0x62

1 These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to these registers fail.

Table 35. Register 0x5C, Register 0x5D, and Register 0x5E—PWM Configuration Registers (Power-On Default = 0x62)

Bit Name R/W Description

[2:0] SPIN R/W These bits control the startup timeout for PWMx. The PWM output stays high until two valid

TACH rising edges are seen from the fan. If there is not a valid TACH signal during the fan TACH

measurement directly after the fan startup timeout period, then the TACH measurement reads

0xFFFF and Interrupt Status Register 2 reflects the fan fault. If the TACH minimum high and

low bytes contain 0xFFFF or 0x0000, then the Status Register 2 bit is not set, even if the fan has

not started.

000 = No startup timeout

001 = 100 ms

010 = 250 ms (default)

011 = 400 ms

100 = 667 ms

101 = 1 sec

110 = 2 sec

111 = 4 sec

[4] INV R/W This bit inverts the PWM output. The default is 0, which corresponds to a logic high output for

100% duty cycle. Setting this bit to 1 inverts the PWM output, so 100% duty cycle corresponds

to a logic low output.

[7:5] BHVR R/W These bits assign each fan to a particular temperature sensor for localized cooling.

000 = Remote 1 temperature controls PWMx (automatic fan control mode).

001 = Local temperature controls PWMx (automatic fan control mode).

010 = Remote 2 temperature controls PWMx (automatic fan control mode).

011 = PWMx runs full speed (default).

100 = PWMx disabled.

101 = Fastest speed calculated by local and Remote 2 temperature controls PWMx.

110 = Fastest speed calculated by all three temperature channel controls PWMx.

111 = Manual mode. PWM duty cycle registers (Register 0x30 to Register 0x32) become

writable.

ADT7476

Rev. A | Page 62 of 72

Table 36. TEMP TRANGE/PWM Frequency Registers

0x5F R/W Remote 1 TRANGE/PWM1 frequency 0xC4

0x60 R/W Local temperature TRANGE/PWM2 frequency 0xC4

0x61 R/W Remote 2 TRANGE/PWM3 frequency 0xC4

1 These registers become read-only when the Configuration Register 1 lock bit is set. Any subsequent attempts to write to these registers fail.

Table 37. Register 0x5F, Register 0x60, and Register 0x61—TEMP TRANGE/PWM Frequency Registers (Power-On Default = 0xC4)

Bit Name R/W Description

[2:0] FREQ R/W These bits control the PWMx frequency (only apply when PWM channel is in low frequency mode).

000 = 11.0 Hz

001 = 14.7 Hz

010 = 22.1 Hz

011 = 29.4 Hz

100 = 35.3 Hz (default)

101 = 44.1 Hz

110 = 58.8 Hz

111 = 88.2 Hz

[3] HF/LF R/W HF/LF = 1, High frequency PWM mode is enabled for PWMx.

HF/LF = 0, Low frequency PWM mode is enabled for PWMx.

[7:4] RANGE R/W These bits determine the PWM duty cycle vs. the temperature range for automatic fan control.

0000 = 2°C

0001 = 2.5°C

0010 = 3.33°C

0011 = 4°C

0100 = 5°C

0101 = 6.67°C

0110 = 8°C

0111 = 10°C

1000 = 13.33°C

1001 = 16°C

1010 = 20°C

1011 = 26.67°C

1100 = 32°C (Default)

1101 = 40°C

1110 = 53.33°C

1111 = 80°C

ADT7476

Rev. A | Page 63 of 72

Table 38. Register 0x62—Enhanced Acoustics Register 1 (Power-On Default = 0x00)

Bit Name R/W1 Description

[2:0] ACOU2 R/W Assuming that PWMx is associated with the Remote 1 temperature channel, these bits define the maximum

rate of change of the PWMx output for Remote 1 temperature-related changes. Instead of the fan speed

jumping instantaneously to its newly determined speed, it ramps gradually at the rate determined by these

bits. This feature ultimately enhances the acoustics of the fan.

When Bit 7 of Configuration Register 6 (0x10) is 0

Time Slot Increase Time for 0% to 100%

000 = 1 37.5 sec

001 = 2 18.8 sec

010 = 3 12.5 sec

011 = 4 7.5 sec

100 = 8 4.7 sec

101 = 12 3.1 sec

110 = 24 1.6 sec

111 = 48 0.8 sec

When Bit 7 of Configuration Register 6 (0x10) is 1

Time Slot Increase Time for 0% to 100%

000 = 1 52.2 sec

001 = 2 26.1 sec

010 = 3 17.4 sec

011 = 4 10.4 sec

100 = 8 6.5 sec

101 = 12 4.4 sec

110 = 24 2.2 sec

111 = 48 1.1 sec

[3] EN1 R/W When this bit is 1, smoothing is enabled on Remote 1 temperature channel.

[4] SYNC R/W SYNC = 1 synchronizes fan speed measurements on TACH2, TACH3, and TACH4 to PWM3. This allows up to

three fans to be driven from PWM3 output and their speeds to be measured.

SYNC = 0 synchronizes only TACH3 and TACH4 to PWM3 output.

[5] MIN1 R/W When the ADT7476 is in automatic fan control mode, this bit defines whether PWM1 is off (0% duty cycle)

or at PWM1 minimum duty cycle when the controlling temperature is below its TMIN – hysteresis value.

0 = 0% duty cycle below TMIN – hysteresis.

1 = PWM1 minimum duty cycle below TMIN – hysteresis.

[6] MIN2 R/W When the ADT7476 is in automatic fan speed control mode, this bit defines whether PWM2 is off (0% duty

cycle) or at PWM2 minimum duty cycle when the controlling temperature is below its TMIN – hysteresis

value.

0 = 0% duty cycle below TMIN – hysteresis.

1 = PWM2 minimum duty cycle below TMIN – hysteresis.

[7] MIN3 R/W When the ADT7476 is in automatic fan speed control mode, this bit defines whether PWM3 is off (0% duty

cycle) or at PWM3 minimum duty cycle when the controlling temperature is below its TMIN – hysteresis

value.

0 = 0% duty cycle below TMIN – hysteresis.

1 = PWM3 minimum duty cycle below TMIN – hysteresis.

1 This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.

2 Setting the relevant bit of Configuration Register 6 (0x10, Bits [2:0]), further decreases these ramp rates by a factor of 4.

ADT7476

Rev. A | Page 64 of 72

Table 39. Register 0x63—Enhanced Acoustics Register 2 (Power-On Default = 0x00)

Bit Name R/W1 Description

[2:0] ACOU3 R/W Assuming that PWMx is associated with the Local temperature channel, these bits define the maximum

rate of change of the PWMx output for local temperature-related changes. Instead of the fan speed

jumping instantaneously to its newly determined speed, it ramps gradually at the rate determined by

these bits. This feature ultimately enhances the acoustics of the fan.

When Bit 7 of Configuration Register 6 (0x10) is 0

Time Slot Increase Time for 0% to 100%

000 = 1 37.5 sec

001 = 2 18.8 sec

010 = 3 12.5 sec

011 = 4 7.5 sec

100 = 8 4.7 sec

101 = 12 3.1 sec

110 = 24 1.6 sec

111 = 48 0.8 sec

When Bit 7 of Configuration Register 6 (0x10) is 1

Time Slot Increase Time for 0% to 100%

000 = 1 52.2 sec

001 = 2 26.1 sec

010 = 3 17.4 sec

011 = 4 10.4 sec

100 = 8 6.5 sec

101 = 12 4.4 sec

110 = 24 2.2 sec

111 = 48 1.1 sec

[3] EN3 R/W When this bit is 1, smoothing is enabled on the local temperature channel.

[6:4] ACOU2 R/W Assuming that PWMx is associated with the Remote 2 temperature channel, these bits define the

maximum rate of change of the PWMx output for Remote 2 temperature related changes. Instead of

the fan speed jumping instantaneously to its newly determined speed, it ramps gradually at the rate

determined by these bits. This feature ultimately enhances the acoustics of the fan.

When Bit 7 of Configuration Register 6 (0x10) is 0

Time Slot Increase Time for 0% to 100%

000 = 1 37.5 sec

001 = 2 18.8 sec

010 = 3 12.5 sec

011 = 4 7.5 sec

100 = 8 4.7 sec

101 = 12 3.1 sec

110 = 24 1.6 sec

111 = 48 0.8 sec

When Bit 7 of Configuration Register 6 (0x10) is 1

Time Slot Increase Time for 0% to 100%

000 = 1 52.2 sec

001 = 2 26.1 sec

010 = 3 17.4 sec

011 = 4 10.4 sec

100 = 8 6.5 sec

101 = 12 4.4 sec

110 = 24 2.2 sec

111 = 48 1.1 sec

[7] EN2 Read/write When this bit is 1, smoothing is enabled on the Remote 2 temperature channel.

1 This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.

ADT7476

Rev. A | Page 65 of 72

Table 40. PWM Minimum Duty Cycle Registers

0x64 R/W PWM1 minimum duty cycle 0x80 (50% duty cycle)

0x65 R/W PWM2 minimum duty cycle 0x80 (50% duty cycle)

0x66 R/W PWM3 minimum duty cycle 0x80 (50% duty cycle)

1 These registers become read-only when the ADT7476 is in automatic fan control mode.

Table 41. Register 0x64, Register 0x65, Register 0x66—PWM Minimum Duty Cycle Registers (Power-On Default = 0x80;

50% duty cycle)

Bit Name R/W1Description

[7:0] PWM duty cycle R/W These bits define the PWMMIN duty cycle for PWMx.

0x00 = 0% duty cycle (fan off).

0x40 = 25% duty cycle.

0x80 = 50% duty cycle.

0xFF = 100% duty cycle (fan full speed).

1 These registers become read-only when the ADT7476 is in automatic fan control mode.

Table 42. TMIN Registers1

0x67 R/W Remote 1 temperature TMIN 0x5A (90°C)

0x68 R/W Local temperatue TMIN 0x5A (90°C)

0x69 R/W Remote 2 temperature TMIN 0x5A (90°C)

1 These are the TMIN registers for each temperature channel. When the temperature measured exceeds TMIN, the appropriate fan runs at minimum speed and increases

with temperature according to TRANGE.

2 These registers become read-only when the Configuration Register 1 lock bit is set. Any subsequent attempts to write to these registers fail.

Table 43. THERM Limit Registers1

0x6A R/W Remote 1 THERM limit 0x64 (100°C)

0x6B R/W Local THERM limit 0x64 (100°C)

0x6C R/W Remote 2 THERM limit 0x64 (100°C)

1 If any temperature measured exceeds its THERM limit, all PWM outputs drive their fans at 100% duty cycle. This is a fail-safe mechanism incorporated to cool the

system in the event of a critical overtemperature. It also ensures some level of cooling in the event that software or hardware locks up. If set to 0x80, this feature is

disabled. The PWM output remains at 100% until the temperature drops below THERM limit – hysteresis. If the THERM pin is programmed as an output, exceeding

these limits by 0.25°C can cause the THERM pin to assert low as an output.

2 These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to these registers fail.

Table 44. Temperature/TMIN Hysteresis Registers1

0x6D R/W Remote 1 and Local Temperature hysteresis. 0x44

HYSL [3:0]

Local Temperature hysteresis. 0°C to 15°C of

hysteresis can be applied to the Local

temperature AFC control loops.

HYSR1 [7:4]

Remote 1 Temperature hysteresis. 0°C to

15°C of hysteresis can be applied to the

Remote 1 Temperature AFC control loops.

0x6E R/W Remote 2 temperature hysteresis. 0x40

HYSR2 [7:4]

Local Temperature hysteresis. 0°C to 15°C of

hysteresis can be applied to the Local

Temperature AFC control loops.

1 Each 4-bit value controls the amount of temperature hysteresis applied to a particular temperature channel. Once the temperature for that channel falls below its

TMIN value, the fan remains running at PWMMIN duty cycle until the temperature = TMIN – hysteresis. Up to 15°C of hysteresis can be assigned to any temperature

channel. The hysteresis value chosen also applies to that temperature channel, if its THERM limit is exceeded. The PWM output being controlled goes to 100%, if the

THERM limit is exceeded and remains at 100% until the temperature drops below THERM – hysteresis. For acoustic reasons, it is recommended the hysteresis value not

be programmed less than 4°C. Setting the hysteresis value lower than 4°C causes the fan to switch on and off regularly when the temperature is close to TMIN.

2 These registers become read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to these registers fail.

ADT7476

Rev. A | Page 66 of 72

Table 45. XNOR Tree Test Enable

0x6F R/W XNOR tree test enable register. 0x00

XEN [0]

If the XEN bit is set to 1, the device enters

the XNOR tree test mode. Clearing the bit

removes the device from the XNOR tree test

mode.

Reserved [7:1] Unused. Do not write to these bits.

1 This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.

Table 46. Remote 1 Temperature Offset

0x70 [7:0] R/W Remote 1 temperature offset. 0x00

Allows a temperature offset to be applied

automatically to the Remote 1 temperature

channel measurement. Bit 1 of

Configuration Register 5 (0x7C) determines

the range and resolution of this register.

1 This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.

Table 47. Local Temperature Offset

0x71 [7:0] R/W Local temperature offset. 0x00

Allows a temperature offset to be applied

automatically to the local temperature

measurement. Bit 1 of Configuration

resolution of this register.

1 This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.

Table 48. Remote 2 Temperature Offset

0x72 [7:0] R/W Remote 2 temperature offset. 0x00

Allows a temperature offset to be applied

automatically to the Remote 2 temperature

channel measurement. Bit 1 of

Configuration Register 5 (0x7C) determines

the range and resolution of this register.

1 This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.

ADT7476

Rev. A | Page 67 of 72

Table 49. Register 0x73—Configuration Register 2 (Power-On Default = 0x00)

Bit Name R/W1Description

[0] FanPresenceDT R/W When FanPresenceDT = 1, the state of Bits [3:1] of 0x73 reflects the presence of a 4-wire fan on

the appropriate TACH channel.

[1] Fan1Detect Read Fan1Detect = 1 indicates that a 4-wire fan is connected to the TACH 1 input.

[2] Fan2Detect Read Fan2Detect = 1 indicates that a 4-wire fan is connected to the TACH 2 input.

[3] Fan3Detect Read Fan3Detect = 1 indicates that a 4-wire fan is connected to the TACH 3 input.

[4] AVG R/W AVG = 1, averaging on the temperature and voltage measurements is turned off. This allows

measurements on each channel to be made much faster (x16).

[5] ATTN R/W ATTN = 1, the ADT7476 removes the attenuators from the 2.5 V, VCCP, 5 V, and 12 V inputs. These

inputs can be used for other functions such as connecting up external sensors. It is also possible

to remove attenuators from individual channels using Bits [7:4] of Configuration Register 4

(0x7D).

[6] CONV R/W CONV = 1, the ADT7476 is put into a single-channel ADC conversion mode. In this mode, the

ADT7476 can be made to read continuously from one input only, for example, Remote 1

temperature. The appropriate ADC channel is selected by writing to Bits [7:5] of TACH 1

minimum high byte register (0x55).

000 2.5 V

001 VCCP

010 VCC (3.3 V)

011 5 V

100 12 V

101 Remote 1 temperature

110 Local temperature

111 Remote 2 temperature

[7] Res This bit is reserved and should not be changed.

1 This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.

Table 50. Register 0x74—Interrupt Mask Register 1 (Power-On Default <7:0> = 0x00)

Bit Name R/W Description

[0] 2.5V/

THERM R/W 2.5V/ THERM = 1, masks SMBALERT for out-of-limit conditions on the 2.5 V/ THERM timer channel.

[1] VCCP R/W VCCP = 1, masks SMBALERT for out-of-limit conditions on the VCCP channel.

[2] VCC R/W VCC = 1, masks SMBALERT for out-of-limit conditions on the VCC channel.

[3] 5V R/W 5 V = 1, masks SMBALERT for out-of-limit conditions on the 5 V channel.

[4] RIT R/W RIT = 1, masks SMBALERT for out-of-limit conditions on the Remote 1 temperature channel.

[5] LT R/W LT = 1, masks SMBALERT for out-of-limit conditions on the local temperature channel.

[6] R2T R/W R2T = 1, masks SMBALERT for out-of-limit conditions on the Remote 2 temperature channel.

[7] OOL R/W OOL = 1, masks SMBALERT for any out-of-limit condition in Interrupt Status Register 2.

ADT7476

Rev. A | Page 68 of 72

Table 51. Register 0x75—Interrupt Mask Register 2 (Power-On Default <7:0> = 0x00)

Bit Name R/W Description

[0] 12V/VC R/W When Pin 21 is configured as a 12 V input, 12V/VC = 1 masks SMBALERT for out-of-limit conditions

on the 12 V channel. When Pin 21 is programmed as VID5, this bit masks an SMBALERT, if the VID5

VID code bit changes.

[1] OVT Read only OVT = 1, masks SMBALERT for overtemperature THERM conditions.

[2] FAN1 R/W FAN1 = 1, masks SMBALERT for a Fan 1 fault.

[3] FAN2 R/W FAN2 = 1, masks SMBALERT for a Fan 2 fault.

[4] FAN3 R/W FAN3 = 1, masks SMBALERT for a Fan 3 fault.

[5] F4P R/W If Pin 14 is configured as TACH 4, F4P = 1 masks SMBALERT for a Fan 4 fault.

If Pin 14 is configured as THERM, F4P = 1 masks SMBALERT for an exceeded THERM timer limit.

If Pin 14 is configured as GPIO, F4P = 1 masks SMBALERT when GPIO is an input and GPIO is

asserted.

[6] D1 R/W D1 = 1 masks SMBALERT for a diode open or short on a Remote 1 channel.

[7] D2 R/W D2 = 1 masks SMBALERT for a diode open or short on a Remote 2 channel.

Table 52. Register 0x76—Extended Resolution Register 11 (Power-On Default <7:0> = 0x00)

Bit Name R/W Description

[1:0] 2.5 V Read-only 2.5 V LSBs. Holds the 2 LSBs of the 10-bit 2.5 V measurement.

[3:2] VCCP Read-only VCCP LSBs. Holds the 2 LSBs of the 10-bit VCCP measurement.

[5:4] VCC Read-only VCC LSBs. Holds the 2 LSBs of the 10-bit VCC measurement.

[7:6] 5 V Read-only 5 V LSBs. Holds the 2 LSBs of the 10-bit 5 V measurement.

1 If this register is read, this register and the registers holding the MSB of each reading are frozen until read.

Table 53. Register 0x77—Extended Resolution Register 21 (Power-On Default <7:0> = 0x00)

Bit Name R/W Description

[1:0] 12 V Read-only 12 V LSBs. Holds the 2 LSBs of the 10-bit 12 V measurement.

[3:2] TDM1 Read-only Remote 1 Temperature LSBs. Holds the 2 LSBs of the 10-bit Remote 1 temperature measurement.

[5:4] LTMP Read-only Local Temperature LSBs. Holds the 2 LSBs of the 10-bit local temperature measurement.

[7:6] TDM2 Read-only Remote 2 Temperature LSBs. Holds the 2 LSBs of the 10-bit Remote 2 temperature measurement.

1 If this register is read, this register and the registers holding the MSB of each reading are frozen until read.

ADT7476

Rev. A | Page 69 of 72

Table 54. Register 0x78—Configuration Register 3 (Power-On Default = 0x00)

Bit Name R/W1Description

[0] ALERT R/W ALERT = 1, Pin 10 (PWM2/SMBALERT) is configured as an SMBALERT interrupt output to indicate

out-of-limit error conditions.

ALERT = 0, Pin 10 (PWM2/SMBALERT) is configured as the PWM2 output.

[1] THERM/

2.5 V

R/W THERM = 1 enables THERM functionality on Pin 22 and Pin 14, if Pin 14 is configured as THERM,

determined by Bits 0 and 1 (PIN14FUNC) of Configuration Register 4. When THERM is asserted, if

the fans are running and the boost bit is set, the fans run at full speed. Alternatively, THERM can be

programmed so that a timer is triggered to time how long THERM has been asserted.

THERM = 0 enables 2.5V measurement on Pin 22 and disables THERM. If Bits [7:5] of Configuration

Pin14FUNC THERM/2.5 V Pin 22 Pin 14

00 0 2.5 V TACH4

01 0 2.5 V THERM

10 0 2.5 V SMBALERT

11 0 2.5 V GPIO

00 1 THERM TACH4

01 1 2.5 V THERM

10 1 THERM SMBALERT

11 1 THERM GPIO

[2] BOOST R/W When THERM is an input and BOOST = 1, assertion of THERM causes all fans to run at the maximum

programmed duty cycle for fail-safe cooling.

[3] FAST R/W FAST = 1, enables fast TACH measurements on all channels. This increases the TACH measurement

rate from once per second to once every 250 ms (4 ×).

[4] DC1 R/W DC1 = 1, enables TACH measurements to be continuously made on TACH1. Fans must be driven by

dc. Setting this bit prevents pulse stretching because it is not required for dc-driven motors.

[5] DC2 R/W DC2 = 1, enables TACH measurements to be continuously made on TACH2. Fans must be driven by

dc. Setting this bit prevents pulse stretching because it is not required for dc-driven motors.

[6] DC3 R/W DC3 = 1, enables TACH measurements to be continuously made on TACH3. Setting this bit prevents

pulse stretching because it is not required for dc-driven motors.

[7] DC4 R/W DC4 = 1, enables TACH measurements to be continuously made on TACH4. Setting this bit prevents

pulse stretching because it is not required for dc-driven motors.

1 This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.

Table 55. Register 0x79—THERM Timer Status Register (Power-On Default = 0x00)

Bit Name R/W Description

[7:1] TMR Read-only Times how long THERM input is asserted. These seven bits read zero until the THERM assertion time

exceeds 45.52 ms.

[0] ASRT/

TMR0

Read-only This bit is set high on the assertion of the THERM input and is cleared on read. If the THERM

assertion time exceeds 45.52 ms, this bit is set and becomes the LSB of the 8-bit TMR reading. This

allows THERM assertion times from 45.52 ms to 5.82 sec to be reported back with a resolution of

22.76 ms.

Table 56. Register 0x7A—THERM Timer Limit Register (Power-On Default = 0x00)

Bit Name R/W Description

[7:0] LIMT R/W Sets maximum THERM assertion length allowed before an interrupt is generated. This is an 8-bit limit

with a resolution of 22.76 ms allowing THERM assertion limits of 45.52 ms to 5.82 sec to be

programmed. If the THERM assertion time exceeds this limit, Bit 5 (F4P) of Interrupt Status Register 2

(Reg. 0x42) is set. If the limit value is 0x00, an interrupt is generated immediately on the assertion of

the THERM input.

ADT7476

Rev. A | Page 70 of 72

Table 57. Register 0x7B—TACH Pulses per Revolution Register (Power-On Default = 0x55)

Bit Name R/W Description

[1:0] FAN1 R/W Sets number of pulses to be counted when measuring Fan 1 speed. Can be used to determine fan

pulses per revolution for unknown fan type.

Pulses Counted

00 = 1

01 = 2 (default)

10 = 3

11 = 4

[3:2] FAN2 R/W Sets number of pulses to be counted when measuring Fan 2 speed. Can be used to determine fan

pulses per revolution for unknown fan type.

Pulses Counted

00 = 1

01 = 2 (default)

10 = 3

11 = 4

[5:4] FAN3 R/W Sets number of pulses to be counted when measuring Fan 3 speed. Can be used to determine fan

pulses per revolution for unknown fan type.

Pulses Counted

00 = 1

01 = 2 (default)

10 = 3

11 = 4

[7:6] FAN4 R/W Sets number of pulses to be counted when measuring Fan 4 speed. Can be used to determine fan

pulses per revolution for unknown fan type.

Pulses Counted

00 = 1

01 = 2 (default)

10 = 3

11 = 4

Table 58. Register 0x7C—Configuration Register 5 (Power-On Default = 0x01)

Bit Name R/W1Description

[0] TWOS

COMPL

R/W TWOS COMPL = 1, sets the temperature range to the twos complement temperature range.

TWOS COMPL = 0, changes the temperature range to the Offset 64 temperature range. When this bit

is changed, the ADT7476 interprets all relevant temperature register values as defined by this bit.

[1] TempOffset R/W TempOffset = 0, sets offset range to −63°C to +64°C with 0.5°C resolution.

TempOffset = 1, sets offset range to −63°C to +127°C with 1°C resolution.

These settings apply to registers 0x70, 0x71 and 0x72 (Remote 1, internal, and Remote 2 temperature

offset registers.

[2] GPIO6D R/W GPIO 6 direction. When GPIO 6 function is enabled, this determines whether GPIO 6 is an input (0) or

an output (1).

[3] GPIO6P R/W GPIO 6 polarity. When the GPIO 6 function is enabled and is programmed as an output, this bit

determines whether the GPIO 6 is active low (0) or high (1).

[4] VID/GPIO R/W VID/GPIO = 0, VID functionality is enabled on Pin 5, Pin 6, Pin 7, Pin 8, and Pin 19.

VID/GPIO = 1, GPIO functionality is enabled on Pin 5, Pin 6, Pin 7, Pin 8, and Pin 19.

[5] R1 THERM R/W R1 THERM = 1 , THERM temperature limit functionality enabled for Remote 1 temperature channel,

that is THERM is bidirectional. R1 THERM = 0, THERM is a timer input only.

THERM can also be disabled on any channel by:

In Offset 64 mode, writing −64°C to the appropriate THERM temperature limit

In twos complement mode, writing −128°C to the appropriate THERM temperature limit

ADT7476

Rev. A | Page 71 of 72

Bit Name R/W1Description

[6] Local

THERM

R/W Local THERM = 1 , THERM temperature limit functionality enabled for local temperature channel, that

is THERM is bidirectional. Local THERM = 0, THERM is a timer input only.

THERM can also be disabled on any channel by:

In Offset 64 mode, writing −64°C to the appropriate THERM temperature limit

In twos complement mode, writing −128°C to the appropriate THERM temperature limit

[7] R2 THERM R/W R2 THERM = 1 , THERM temperature limit functionality enabled for Remote 2 temperature channel,

that is. THERM is bidirectional. R2 THERM = 0, THERM is a timer input only.

THERM can also be disabled on any channel by:

In Offset 64 mode, writing −64°C to the appropriate THERM temperature limit

In twos complement mode, writing −128°C to the appropriate THERM temperature limit

1 This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.

Table 59. Register 0x7D—Configuration Register 4 (Power-On Default = 0x00)

Bit Name R/W1Description

[1:0] PIN14FUNC R/W These bits set the functionality of Pin 14:

00 = TACH4 (default)

01 = THERM

10 = SMBALERT

11 = GPIO

[2] THERM

Disable

R/W THERM Disable=0, THERM overtemperature output is enabled assuming THERM is correctly

configured (Registers 0x78, 0x7C, 0x7D).

THERM Disable=1, THERM overtemperature output is disabled on all channels.

THERM can also be disabled on any channel by:

In Offset 64 mode, writing −64°C to the appropriate THERM temperature limit.

In twos complement mode, writing −128°C to the appropriate THERM temperature limit.

[3] MaxSpeed

on THERM

R/W MaxSpeed on THERM = 0, fans go to full speed when THERM temperature limit is exceeded.

MaxSpeed on THERM = 1, fans go to maximum speed (Registers 0x38, 0x39, and 0x3A) when THERM

temperature limit is exceeded.

[4] BpAtt2.5V R/W Bypass 2.5 V attenuator. When set, the measurement scale for this channel changes from 0 V (0x00) to

2.25 V (0xFF).

[5] BpAttVCCP R/W Bypass VCCP attenuator. When set, the measurement scale for this channel changes from 0 V (0x00) to

2.25 V (0xFF).

[6] BpAtt5V R/W Bypass 5 V attenuator. When set, the measurement scale for this channel changes from 0 V (0x00) to

2.25 V (0xFF).

[7] BpAtt12V R/W Bypass 12 V attenuator. When set, the measurement scale for this channel changes from 0 V (0x00) to

2.25 V (0xFF).

1 This register becomes read-only when the Configuration Register 1 lock bit is set to 1. Any subsequent attempts to write to this register fail.

Table 60. Register 0x7E—Manufacturer’s Test Register 1 (Power-On Default = 0x00)

Bit Name R/W Description

[7:0] Reserved Read-only Manufacturer’s test register. These bits are reserved for manufacturer’s test purposes and should not

be written to under normal operation.

Table 61. Register 0x7F—Manufacturer’s Test Register 2 (Power-On Default = 0x00)

Bit Name R/W Description

[7:0] Reserved Read-only Manufacturer’s test register. These bits are reserved for manufacturer’s test purposes and should not

be written to under normal operation.

ADT7476

Rev. A | Page 72 of 72

OUTLINE DIMENSIONS

COMPLIANT TO JEDEC STANDARDS MO-137AE

24 13

PIN 1

SEATING

PLANE

0.010

0.004 0.012

0.008

0.025

BSC

0.069

0.053

0.010

0.006

0.050

0.016

8°

0°

0.065

0.049

COPLANARITY

0.004

0.345

0.341

0.337

0.158

0.154

0.150 0.244

0.236

0.228

Figure 67. 24-Lead Shrink Small Outline Package [QSOP]

(RQ-24)

Dimensions shown in inches

ORDERING GUIDE

Model Termperature Range Package Description Package Option

ADT7476ARQZ1 –40°C to +125°C 24-Lead QSOP RQ-24

ADT7476ARQZ-REEL1 –40°C to +125°C 24-Lead QSOP RQ-24

ADT7476ARQZ-REEL7 –40°C to +125°C 24-Lead QSOP RQ-24

EVAL-ADT7476EB Evaluation Board

1 Z = Pb-free part.

registered trademarks are the property of their respective owners.

D05382-0-3/06(A)

TTT