ESDALC5-1BM2 - STMicroelectronics

This is information on a product in full production.

June 2012 Doc ID 16936 Rev 2 1/14

ESDALC5-1BM2, ESDALC5-1BT2

Single-line low capacitance Transil™,

transient surge voltage suppressor (TVS) for ESD protection

Datasheet − production data

Features

■Single-line low capacitance Transil diode

■Bidirectional ESD protection

■Breakdown voltage VBR = 5.8 V min.

■Low diode capacitance (26 pF typ at 0 V)

■Low leakage current < 60 nA @ 5 V

■Very small PCB area: 0.6 mm²

Benefits

■High ESD protection level

■High integration

■Suitable for high density boards

■Lead-free packages

■ECOPACK®2 compliant components

Complies with the following standards:

■IEC 61000-4-2 level 4

– 15 kV (air discharge)

– 8 kV (contact discharge)

■MIL STD 883G - Method 3015-7: class 3

– Human body model

Applications

Where transient overvoltage protection in ESD

sensitive equipment is required, such as:

■Computers

■Printers

■Communication systems

■Cellular phone handsets and accessories

■Video equipment

Figure 1. Functional diagram

Description

The ESDALC5-1BM2 and ESDALC5-1BT2 are

bidirectional single-line TVS diodes designed to

protect data lines or other I/O ports against ESD

transients.

These devices are ideal for applications where

both reduced line capacitance and board space

saving are required.

TM: Transil is a trademark of STMicroelectronics

SOD882

ESDALC5-1BM2 SOD882T

ESDALC5-1BT2

I/O1

I/O2

www.st.com

Characteristics ESDALC5-1BM2, ESDALC5-1BT2

2/14 Doc ID 16936 Rev 2

1 Characteristics

Figure 2. Electrical characteristics (definitions)

Table 1. Absolute maximum ratings (Tamb = 25 °C)

Symbol Parameter Value Unit

VPP Peak pulse voltage IEC 61000-4-2 contact discharge ±30 kV

PPP(1)

1. For a surge greater than the maximum values, the diode will fail in short-circuit.

Peak pulse power dissipation (8/20 µs) Tj initial = Tamb 150 W

IPP Peak pulse current (8/20 µs) 9 A

TjJunction temperature -55 to +150 °C

Tstg Storage temperature range -65 to +150 °C

TLMaximum lead temperature for soldering during 10 s 260 °C

Table 2. Electrical characteristics (values, Tamb = 25 °C)

Symbol Test condition Min. Typ. Max. Unit

VBR

From pin1 to pin2, IR = 1 mA (direct) 11 13 V

From pin2 to pin1, IR = 1 mA (reverse) 5.8 8

IRM VRM = 5 V 60 nA

RdSquare pulse, IPP = 1 A, tp = 2.5 µs 650 mΩ

Cline F = 1 MHz, VR = 0 V 26 30 pF

Symbol Parameter

V = Breakdown voltage

I = Leakage current @ V

V = Stand-off voltage

I = Peak pulse current

I = Breakdown current

RM RM

V = Clamping voltage

I = Forward current

R = Series resistanc between input and output

C = Input capacitance per line

I/O

line

ESDALC5-1BM2, ESDALC5-1BT2 Characteristics

Doc ID 16936 Rev 2 3/14

Figure 3. Relative variation of peak pulse

power versus initial junction

temperature

Figure 4. Relative variation of leakage

current versus junction

temperature (typical values)

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

025 50 75 100 125 150

P [T initial]/P [T initial = 25°C]

PP j PP j

T (°C)

100

1000

25 50 75 100 125

I [T ]/I [T = 25 °C]

RjRj

T (°C)

Figure 5. Peak pulse power versus

exponential pulse duration (direct)

Figure 6. Peak pulse power versus

exponential pulse duration

(reverse)

100

1000

10000

110 100 1000

P (W)

T (µs)

100

1000

10000

1 10 100 1000

T (µs)

P (W)

Figure 7. Clamping voltage versus peak

pulse current (typical values,

exponential waveform, direct)

Figure 8. Clamping voltage versus peak

pulse current (typical values,

exponential waveform, reverse)

0.1

1.0

10.0

100.0

8 10121416182022

I (A)

V (V)

0.1

1.0

10.0

100.0

6 8 10 12 14 16

I (A)

V (V)

Characteristics ESDALC5-1BM2, ESDALC5-1BT2

4/14 Doc ID 16936 Rev 2

Figure 9. Junction capacitance versus

reverse applied voltage

(typical values, direct)

Figure 10. Junction capacitance versus

reverse applied voltage

(typical values, reverse)

012345

C(pF)

V (V)

LINE

012345

C(pF)

V (V)

LINE

Figure 11. ESD response to IEC 61000-4-2

(+15 kV air discharge)

Figure 12. ESD response to IEC 61000-4-2

(-15 kV air discharge)

5 V/Div

100 ns/Div

5 V/Div

100 ns/Div

Figure 13. S21 attenuation measurement

result

Figure 14. Static characteristic

100k 1M 10M 100M 1G

- 40

- 35

- 30

- 25

- 20

- 15

- 10

- 5

F(Hz)

Direct

Reverse

ESDALC5-1BM2, ESDALC5-1BT2 Ordering information scheme

Doc ID 16936 Rev 2 5/14

2 Ordering information scheme

Figure 15. Ordering information scheme

ESDA LC 5 - 1 B x2

ESD array

Low capacitance

Package

M2 = SOD882

T2 = Thin SOD882

Breakdown voltage

Number of lines

Directional

5 = 5 Volts min

B = Bi-directional

Package information ESDALC5-1BM2, ESDALC5-1BT2

6/14 Doc ID 16936 Rev 2

3 Package information

●Epoxy meets UL94, V0

●Lead-free packages

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK® is an ST trademark.

Figure 16. SOD882 dimension definitions

Table 3. SOD882 dimension values

Ref.

Dimensions

Millimeters Inches

Min. Typ. Max. Min. Typ. Max.

A 0.40 0.47 0.50 0.016 0.019 0.020

A1 0.00 0.05 0.000 0.002

b1 0.45 0.50 0.55 0.018 0.020 0.022

b2 0.45 0.50 0.55 0.018 0.020 0.022

D 0.55 0.60 0.65 0.022 0.024 0.026

E 0.95 1.00 1.05 0.037 0.039 0.041

e 0.60 0.65 0.70 0.024 0.026 0.028

L1 0.20 0.25 0.30 0.008 0.010 0.012

L2 0.20 0.25 0.30 0.008 0.010 0.012

PIN # 1 ID

b2b1

ESDALC5-1BM2, ESDALC5-1BT2 Package information

Doc ID 16936 Rev 2 7/14

Note: Product marking may be rotated by multiples of 90° for assembly plant differentiation. In no

case should this product marking be used to orient the component for its placement on a

PCB. Only pin 1 mark is to be used for this purpose.

Figure 19. SOD882 tape and reel specifications

Figure 17. SOD882 footprint in mm

(inches)

Figure 18. SOD882 marking

0.55

(0.022)

0.40

(0.016)

0.50

0.020

0.55

(0.022)

Pin1 Pin 2

User direction of unreeling

All dimensions in mm

4.0 ± 0.1

2.0 ± 0.05

8.0 + 0.3 /-0.1

2.0 ± 0.10

1.75 ± 0.1

3.5 ±- 0.05

Ø 1.50 ± 0.10

0.68 ± 0.05

0.20 ± 0.05

1.10 ± 0.05

0.66 ± 0.05

Bar indicates Pin 1

Package information ESDALC5-1BM2, ESDALC5-1BT2

8/14 Doc ID 16936 Rev 2

Figure 20. SOD882T dimension definitions

Note: Product marking may be rotated by multiples of 90° for assembly plant differentiation. In no

case should this product marking be used to orient the component for its placement on a

PCB. Only pin 1 mark is to be used for this purpose.

Table 4. SOD882T dimension values

Ref.

Dimensions

Millimeters Inches

Min. Typ. Max. Min. Typ. Max.

A 0.30 0.40 0.012 0.016

A1 0.00 0.05 0.000 0.002

b1 0.45 0.50 0.55 0.018 0.020 0.022

b2 0.45 0.50 0.55 0.018 0.020 0.022

D 0.55 0.60 0.65 0.022 0.024 0.026

E 0.95 1.00 1.05 0.037 0.039 0.041

e 0.60 0.65 0.70 0.024 0.026 0.028

L1 0.20 0.25 0.30 0.008 0.010 0.012

L2 0.20 0.25 0.30 0.008 0.010 0.012

Figure 21. SOD882T footprint in mm

(inches)

Figure 22. SOD882T marking

PIN # 1 ID

b2b1

0.55

(0.022)

0.40

(0.016)

0.50

0.020

0.55

(0.022)

Pin1 Pin 2

ESDALC5-1BM2, ESDALC5-1BT2 Package information

Doc ID 16936 Rev 2 9/14

Figure 23. SOD882T tape and reel specifications

User direction of unreeling

All dimensions in mm

4.0 ± 0.1

2.0 ± 0.05

8.0 0.1±

2.0 ± 0.10

1.75 ± 0.1

3.5 ±- 0.05

Ø 1.50 ± 0.10

0.70 ± 0.05

0.20 ± 0.05

1.15 ± 0.05

0.47 ± 0.05

Bar indicates Pin 1

Recommendation on PCB assembly ESDALC5-1BM2, ESDALC5-1BT2

10/14 Doc ID 16936 Rev 2

4 Recommendation on PCB assembly

4.1 Stencil opening design

1. General recommendation on stencil opening design

a) Stencil opening dimensions: L (Length), W (Width), T (Thickness).

Figure 24. Stencil opening dimensions

b) General design rule

Stencil thickness (T) = 75 ~ 125 µm

2. Reference design

a) Stencil opening thickness: 100 µm

b) Stencil opening for central exposed pad: Opening to footprint ratio is 50%.

c) Stencil opening for leads: Opening to footprint ratio is 90%.

Figure 25. Recommended stencil window position

Aspect Ratio W

----- 1.5≥=

Aspect Area LW×

2T L W+()

----------------------------0.66≥=

Lead footprint on PCB

Stencil window

position

Lead footprint on PCB

Package footprint

0.45 mm

0.39 mm

0.05 mm 0.05 mm

Stencil window

position

ESDALC5-1BM2, ESDALC5-1BT2 Recommendation on PCB assembly

Doc ID 16936 Rev 2 11/14

4.2 Solder paste

1. Halide-free flux qualification ROL0 according to ANSI/J-STD-004.

2. “No clean” solder paste is recommended.

3. Offers a high tack force to resist component movement during high speed.

4. Solder paste with fine particles: powder particle size is 20-45 µm.

4.3 Placement

1. Manual positioning is not recommended.

2. It is recommended to use the lead recognition capabilities of the placement system, not

the outline centering.

3. Standard tolerance of ± 0.05 mm is recommended.

4. 3.5 N placement force is recommended. Too much placement force can lead to

squeezed out solder paste and cause solder joints to short. Too low placement force

can lead to insufficient contact between package and solder paste that could cause

open solder joints or badly centered packages.

5. To improve the package placement accuracy, a bottom side optical control should be

performed with a high resolution tool.

6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is

recommended during solder paste printing, pick and place and reflow soldering by

using optimized tools.

4.4 PCB design preference

1. To control the solder paste amount, the closed via is recommended instead of open

vias.

2. The position of tracks and open vias in the solder area should be well balanced. The

symmetrical layout is recommended, in case any tilt phenomena caused by

asymmetrical solder paste amount due to the solder flow away.

Recommendation on PCB assembly ESDALC5-1BM2, ESDALC5-1BT2

12/14 Doc ID 16936 Rev 2

4.5 Reflow profile

Figure 26. ST ECOPACK® recommended soldering reflow profile for PCB mounting

Note: Minimize air convection currents in the reflow oven to avoid component movement.

60 sec

(90 max)

250

100

150

200

240210180150120906030 300

270

-2 °C/s to

-3 °C/s

-6 °C/s max

240-245 °C

2 - 3 °C/s

0.9 °C/s

Temperature (°C)

Time (s)

ESDALC5-1BM2, ESDALC5-1BT2 Ordering information

Doc ID 16936 Rev 2 13/14

5 Ordering information

6 Revision history

Table 5. Ordering information

Order code Marking(1)

1. The marking can be rotated by multiples of 90° to differentiate assembly location

Package Weight Base qty Delivery mode

ESDALC5-1BM2 G SOD882 0.92 mg 12000 Tape and reel

ESDALC5-1BT2 H SOD882T 0.76 mg 12000 Tape and reel

Table 6. Document revision history

Date Revision Changes

02-Feb-2010 1Initial release.

06-Jun-2012 2Updated Figure 11, Figure 12, Figure 16, Figure 20, Table 3, and

Table 4. Updated note in page 7, 8 and 13. Updated IRM in Table 2.

ESDALC5-1BM2, ESDALC5-1BT2

14/14 Doc ID 16936 Rev 2

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