Si501/2/3 3 2 K H Z -100 MH Z CMEMS O SC ILLA TOR Features Wide frequency range: 32 kHz to 100 MHz Contact Silicon Labs for frequencies above 100 MHz Si501 single frequency w/ OE Si502 dual frequency w/ OE/FS Si503 quad frequency w/ FS 20/30/50 ppm frequency stability including 10-year aging LVCMOS output Low period jitter Low power Continuous supply voltage range: +1.71 V to +3.63 V User selectable tRise/tFall options Glitchless start and stop Excellent short-term stability, longterm aging Industry standard footprints: 2x2.5, 2.5x3.2, 3.2x5 mm RoHS compliant, Pb-free Short lead times: <2 weeks -20 to +70 C: Extnd commercial -40 to +85 C: Industrial The Si50x family also includes the Si504 for in-circuit programmability (See the Si504 Data Sheet) Applications Storage (SATA/SAS/PCIe) General purpose processors Industrial controllers Embedded controllers Motor control Flow control Office/Home automation IP cameras/surveillance Display and control panels Outdoor electronics Multi-function printers Office equipment Description The Si501/2/3 CMEMS oscillator family provides monolithic, MEMS-based IC replacements for traditional crystal oscillators. Silicon Laboratories' CMEMS technology combines standard CMOS + MEMS in a single, monolithic IC to provide integrated, high-quality and high-reliability oscillators. Each device is factory tested and configured for guaranteed performance to data sheet specifications across voltage, process, temperature, shock, vibration, and aging. Additional information on the Si50x CMEMS oscillator architecture and CMEMS technology is available in white papers on the Silicon Labs website at www.siliconlabs.com/cmems. Functional Block Diagram Ordering Information: See Section 5. Pin Assignments FS/OE 1 GND 2 4 VDD 3 CLK Patents pending VDD LDO Resonator & Oscillator Digital Frequency-Locked Loop (FLL) FS/OE Temperature Sensor Temp Comp / Digital Control VCO CLK / NVM M RAM M ROM GND Rev. 1.0 6/14 Copyright (c) 2014 by Silicon Laboratories Si501/2/3 Si501/2/3 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2. Si501/2/3 Typical Applications Circuits, AC Waveforms, and Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.1. Si501/2 Applications Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 2.2. Si501/2 AC Waveforms and Functional Descriptions . . . . . . . . . . . . . . . . . . . . . . . . .9 2.3. Si503 Applications Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.4. Si503 AC Waveform and Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1. OE Enable and Disable States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.2. Output Rise and Fall settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1. Si501 Ordering Guide and Part Number Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 5.2. Si502 Ordering Guide and Part Number Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 5.3. Si503 Ordering Guide and Part Number Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 6. Package Dimensions and Land Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1. Package Outline: 3.2 x 5 mm 4-pin DFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.2. Package Outline: 2.5 x 3.2 mm 4-pin DFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.3. Package Outline: 2 x 2.5 mm 4-pin DFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7. Top Markings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 7.1. 3.2 x 5 mm Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.2. 3.2 x 5 mm Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.3. 2.5 x 3.2 mm Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.4. 2.5 x 3.2 mm Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 7.5. 2 x 2.5 mm Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.6. 2 x 2.5 mm Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 2 Rev. 1.0 Si501/2/3 1. Electrical Specifications Table 1. Recommended Operating Conditions VDD=1.71 to 3.63 V, TA= -40 to 85 C, unless otherwise specified Parameter Supply Voltage 1 Supply Current Static Supply Current Symbol Test Condition Min Typ Max Unit 1.71 -- 3.63 V CL=4 pF, 3.3 VDD, FCLK=1.0 MHz, low power option -- 1.7 2.5 mA CL=4 pF, 3.3 VDD, FCLK=100 MHz, low power option -- 5.3 6.5 mA CL=4 pF, 3.3 VDD, FCLK=1.0 MHz, low jitter option -- 3.9 4.9 mA CL=4 pF, 3.3 VDD, FCLK=100 MHz, low jitter option -- 7.6 8.9 mA Mode=Stop2, low power option FCLK=1 MHz -- 1.7 2.5 mA Mode=Stop2, low jitter option FCLK=1 MHz -- 3.9 4.9 mA Mode=Doze2 -- 670 890 A Mode=Sleep2 -- 0.3 1 A VDD IDD1 IDD2 Input High Voltage VIH FS/OE pin 0.70 x VDD -- -- V Input Low Voltage VIL FS/OE pin -- -- 0.30 x VDD V OE Internal Pull Resistor RI Ordering option 40 50 60 k Operating Temperature TA Extended commercial grade -20 -- 70 C Industrial grade -40 -- 85 C Notes: 1. The supply voltage range is continuous from 1.71 to 3.63 V. 2. Si501 and Si502 only. Si503 has FS only and does not support Stop, Doze, or Sleep. See Section 3. Functional Description for more information on operational modes. Rev. 1.0 3 Si501/2/3 Table 2. Output Clock Characteristics VDD=1.71 to 3.63 V, TA= -40 to 85 C, unless otherwise specified. Parameter Symbol Frequency Range FCLK Clock Period TCLK Total Stability1 FSTAB Initial Accuracy Startup Time2 Resume Time3,4 Output Disable Time3,4 Frequency Update Time4,6 Test Condition 1/FCLK Min Typ Max Unit 0.032 -- 100 MHz 31,250 -- 10 ns -20 -- +20 ppm -30 -- +30 ppm -50 -- +50 ppm FI Measured at 25 C at the time of shipping -- 2 -- ppm TSU From VDD crossing 1.71 V to first clock output -- 2.5 4 ms From Sleep mode -- 2.5 5 ms From Doze mode -- 1.7 2.55 ms 5 From Stop mode -- -- 1.5 x TCLK + 35 ns To Sleep/Doze mode, from output running -- -- 225 s To Stop, from output running -- -- 1.5 x TCLK + 35 ns -- -- 5 ms TRUN TD TNEW_FREQ Notes: 1. Orderable option. Stability budget consists of initial tolerance, operating temperature range, rated power supply voltage change, load change, 10-year aging, shock, and vibration. 2. Hold FS/OE high (strong or weak) during powerup for fastest time to clock. 3. Si501 and Si502 only. Si503 has FS only and does not support Stop, Doze, or Sleep. 4. Asserted FS/OE actions must be held stable for the maximum duration of the invoked FS/OE event (e.g., TRUN, TNEW_FREQ, TD, etc). 5. If the Si502 frequency is switched while the device is in Stop mode, the frequency prior to Stop will be output briefly until the glitchless switch to the other frequency. Doze mode and Sleep mode do not have this behavior. 6. Si502 and Si503 only. Si501 is a single frequency device with OE only. 4 Rev. 1.0 Si501/2/3 Table 3. Output Clock Levels and Symmetry VDD = 1.71 to 3.63 V, TA = -40 to 85 C unless otherwise indicated. Parameter Symbol Output High Voltage VOH Output Low Voltage Rise/Fall Time1 Duty Cycle Min Typ Max Unit 1st ordering option code: A and H IOH=-4 mA 0.90 x VDD -- -- V VOL 1st ordering option code: A and H IOH=+4 mA -- -- 0.10 x VDD V tRise /tFall 1st ordering option code2: A and H Z0=25 @ 3.3 V 0.4 0.72 1.2 ns 1st ordering option code: B and J Z0= 50 @ 3.3 V 1 1.3 1.6 ns 1st ordering option code: C and K Z0= 50 @ 2.5 V 1 1.3 1.6 ns 1st ordering option code: D and L Z0 = 50 @ 1.8 V 1 1.3 1.6 ns 1st ordering option code: E and M Z0= 110 @ 3.3 V 2 3 4 ns 1st ordering option code: F and N Z0=220 @ 3.3 V3 4 5 7 ns 1st ordering option code: G and P Z0=440 @ 3.3 V3 7 8 11 ns Drive strength selected such that tRise/tFall (20% to 80%)<10% of period 45 50 55 % DC Test Condition Notes: 1. CL=15 pF, tRise/tFall (20% to 80%), 3.3 V, unless otherwise stated. 2. Recommended series termination resistor (RS) = 24.9 for Z0=50 3. Ordering options F, N, G, and P are not recommended for FCLK > 5 MH2. Rev. 1.0 5 Si501/2/3 Table 4. Output Clock Jitter and Phase Noise VDD = 1.71 to 3.63 V, TA = -40 to 85 C unless otherwise indicated. Parameter Cycle-to-Cycle Jitter Period Jitter Period Jitter Pk-Pk Phase Jitter1 Symbol JCCPP JPRMS JPPKPK Test Condition Min Typ Max Unit 100 MHz, Low Jitter Option 1st ordering option code: H -- 14 25 ps pk-pk 100 MHz, Low Power Option 1st ordering option code: A -- 16 26 ps pk-pk 100 MHz, Low Jitter Option 1st ordering option code: H -- 1 1.6 ps rms 100 MHz, Low Power Option 1st ordering option code: A -- 1.3 1.9 ps rms Low Jitter Option 10k samples 1st ordering option code: H -- 9 13 ps pk-pk Low Power Option 10k samples 1st ordering option code: A -- 10 16 ps pk-pk 75 MHz FOFFSET=900 kHz to 7.5 MHz Low Jitter Option 1st ordering option code: H -- 1 1.3 ps rms 75 MHz FOFFSET=900 kHz to 7.5 MHz Low Power Option 1st ordering option code: A -- 2.5 3.2 ps rms Notes: 1. Integrated phase jitter exceeds the requirements of some high-performance data communications systems. See AN783 for additional information. 6 Rev. 1.0 Si501/2/3 Table 5. Environmental Compliance and Package Information Parameter Test Condition Mechanical Shock MIL-STD-883, Method 2002, Cond B. (1,500 g) Mechanical Shock High g MIL-STD-883, Method 2002, Cond E. (10,000 g) Mechanical Vibration MIL-STD-883, Method 2007 Solderability MIL-STD-883, Method 2003 Temperature Cycle JESD22, Method A104 Resistance to Solder Heat MIL-STD-883, Method 2036 Contact Pads Gold over Nickel/Palladium Table 6. Thermal Conditions Parameter Thermal Impedance Symbol Test Condition Value JA 3.2x5 mm, still air 187 2.5x3.2 mm, still air 239 2x2.5 mm, still air 241 Unit C/W Table 7. Absolute Maximum Limits1 Parameter Symbol Rating Unit TMAX 85 C TS -55 to +125 C Supply Voltage VDD -0.5 to +3.8 V Input Voltage VIN -0.5 to VDD +0.3V V HBM 2000 V CDM 500 V TPEAK 260 C Soldering Time at TPEAK (PB-free profile)2 TP 20-40 s Junction Temperature TJ 125 C Maximum Operating Temperature Storage Temperature ESD Sensitivity (JESD22-A114) ESD Sensitivity (CDM) Soldering Temperature (Pb-free profile)2 Notes: 1. Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device reliability. 2. The device is compliant with JEDEC J-STD-020. Rev. 1.0 7 Si501/2/3 2. Si501/2/3 Typical Applications Circuits, AC Waveforms, and Functional Descriptions The Si501/2/3 family has various applications circuits and ac waveforms depending on the selected device and ordering configuration options. Pay careful attention when reading the following section to be sure you refer to the correct diagrams. 2.1. Si501/2 Applications Circuits VDD VDD RUP FS/OE 1 4 VDD 0.1 F Si501/2 Z0 = 50 GND 2 3 CLK CLK RS Figure 1. Si501/2 Applications Circuit with Optional Output Series Resistor Note: The dotted line box in Figure 1 is an optional component depending on tRise/tFall configuration option. This diagram applies to all Si50x product drive strength configuration options. See Table 3 for RS recommendations. See Section 5. "Ordering Guide" for configuration options. MCU VDD RUP OUTPUT DRIVER VDD VDD VDD ~50K RUP FS/OE 4 VDD 1 0.1F Si501/2 Z0 = 50 GND 2 3 CLK CLK RS Note: The dotted line boxes in Figure 2 show resistor options depending on MCU pull-up resistors configuration and the Si501/2 internal resistor configuration options. See Section 5. "Ordering Guide" for configuration options. Users should design only one of the pin 1 dotted-line options. The series resistor (RS) on pin 3 is also optional. See Table 3 for RS recommendations. Figure 2. Si501/2 Applications Circuit with MCU Configuration Options 8 Rev. 1.0 Si501/2/3 Table 8. Si502 FS/OE States and Resistor Values FS/OE Pin State RUP Clock Output Strong High 0 RUP 1 k Frequency 1 Weak High 20 kRUP 200 k Frequency 2 Low -- Hi-Z Notes: 1. If the Si502 internal pull-up resistor configuration option is not selected, an MCU internal pull-up resistor or an external pull-up resistor should be used. 2. The parallel combination of all pull-up resistors on the FS/OE pin, including the optional internal device pull-up resistor must be > 20 kto select the Weak High state. 3. If the Si502 internal pull-up resistor is enabled with no other external FS/OE connections, the FS/OE state will be detected as Weak High' which selects the Frequency 2 output by default. 2.2. Si501/2 AC Waveforms and Functional Descriptions Supply Voltage (VDD) VDD=1.71V CLK TSU Figure 3. Si501/2 Power On Time (refer to Table 2) RUP <1k: RUP <1k: TD FS/OE CLK TRUN RUP >20k: TNEW_ FREQ Hi-Z Hi-Z Figure 4. Si501/2 AC Waveform (refer to Table 2) Rev. 1.0 9 Si501/2/3 2.3. Si503 Applications Circuits VDD VDD VDD ~50K RUP FS/OE 4 VDD 1 RDOWN 0.1 F Si503 Z0 = 50 GND 2 3 CLK CLK RS Note: The dotted line boxes show optional components depending on tRise/tFall and internal pull up resistor configuration options. See Section 5. "Ordering Guide" for configuration options. See Table 3 for RS recommendations. Figure 5. Si503 Applications Circuit with Configuration Options Table 9. Si503 Frequency Select with External Resistor Options FS/OE Pin State RUP RDOWN Clock Output Strong High 0 RUP 1 k Do not populate Frequency 1 Weak High 20 kRUP 200 k Do not populate Frequency 2 Weak Low Do not populate 20 kRDOWN 200 k Frequency 3 Strong Low Do not populate 0 RDOWN 1 k Frequency 4 Note: If the Si503 internal pull-up resistor is enabled with no other external FS/OE connections, the FS/OE state will be detected as Weak High' which selects the Frequency 2 output by default. 10 Rev. 1.0 Si501/2/3 MCU VDD VDD VDD RUP VDD ~50K FS/OE OUTPUT DRIVER 4 VDD 1 0.1 F VDD Si503 RUP 6K OUTPUT DRIVER Z0 = 50 GND 3 2 CLK CLK RS Note: The dotted line boxes in Figure 6 show resistor options depending on MCU pull-up resistors configuration and the Si503 internal resistor configuration options. See Section 5. "Ordering Guide" for configuration options. Users should design only one of the pin 1 dotted-line options. The series resistor (RS) on pin 3 is also optional. See Table 3 for RS recommendations. Figure 6. Si503 Applications Circuit with MCU and Configuration Options Table 10. Si503 Frequency Select FS/OE Pin State MCU Output 1 MCU Output 2 Clock Output Strong High High Hi-Z Frequency 1 Weak High Hi-Z Hi-Z Frequency 2 Weak Low Hi-Z Low Frequency 3 Strong Low Low Hi-Z Frequency 4 Note: If the Si50x internal pull-up resistor is enabled with no other external OE connections, the OE state will be detected as Weak High' which selects the Frequency 2 output by default. 2.4. Si503 AC Waveform and Functional Description VDD 1.71V TSU Figure 7. Si503 Power On Time (refer to Table 2) Rev. 1.0 11 Si501/2/3 RUP < 1k: FS RUP > 20k: RDOWN > 20k: TNEW_ FREQ TNEW_ FREQ CLK Hi-Z Hi-Z Figure 8. Si503 AC Waveform (refer to Table 2) 3. Functional Description The Si50x series oscillator family includes four base devices. All devices are configurable according to the Section 5. "Ordering Guide". The four devices each support a single clock output frequency at any one time and are segmented according to the number of clock frequencies they store in on-chip memory. The Si501 supports a single stored frequency, enabled with the OE functionality. The Si502 stores two frequencies that can be selected with FS and enabled/disabled with OE functionality. The Si503 stores four frequencies, selected with FS functionality. The Si503 does not support OE functionality. The Si501/2/3 are covered in this data sheet. The Si504 is a programmable oscillator, controlled through a single pin interface (C1D). It is covered in its own Si504 data sheet available at www.siliconlabs.com/cmems. All devices in the Si50x CMEMS series employ a cost-optimized, power-efficient, digital FLL architecture to produce a highly accurate and stable output clock from a passively compensated MEMS resonator reference frequency. The architecture uses the MEMS resonator as its reference frequency along with a divided signal from an on-chip, digitally-controlled VCO to drive a frequency comparator for the FLL's digital loop filter. The digital loop filter accumulates and further processes the frequency error values to produce the target output frequency. The architecture also uses a high-resolution, low-noise temperature sensor and temperature compensation algorithm to offset any temperature drift of the passively compensated MEMS resonator. Each device is calibrated for temperature and MEMS-resonator frequency pairs and derives a device-specific compensation polynomial. As the temperature changes, this compensation circuitry offsets any frequency drift. This tightly coupled system is extremely accurate and fast because the MEMS resonator and CMOS compensation circuitry are in a single, monolithic chip, and, therefore, separated by a few microns. The complete system process occurs many thousands of times per second, providing excellent frequency accuracy and stability across temperature changes, including any fast temperature transients. The oscillator also supports a low-power version that reduces the sampling cycle to a longer period, reducing power consumption for applications that can tolerate relaxed jitter specifications of approximately 1 ps RMS to reduce power by approximately 2-3 mA. See Table 1 for exact specifications. 3.1. OE Enable and Disable States The Si50x CMEMS series supports four operational output states via the FS/OE configuration pin. If enabled, the Si50x is in Run mode, the clock is output and power is as specified in Table 1. The disable modes are Stop, Sleep, and Doze. Each of these states has a different power consumption profile as specified in Table 1. 3.1.1. Stop Mode The Si50x output in Stop mode is high-impedance, also known as High-Z (Hi-Z) or Tri-State. Stop mode disables the output driver, but the digital core and MEMS resonator remain enabled for fast transition to Run mode. The output is stopped and held at High-Z after completing the last cycle glitch-free. No other power saving measure is taken in Stop mode. 12 Rev. 1.0 Si501/2/3 3.1.2. Doze Mode The Si50x output in Doze mode is high-impedance, also known as High-Z (Hi-Z) or Tri-State. Doze mode disables the output driver, the VCO, and the MEMS resonator, but the digital core remains enabled. The output is stopped and is held at High-Z after completing the last cycle glitch-free. 3.1.3. Sleep Mode The Si50x output in Sleep mode is high-impedance, also known as High-Z (Hi-Z) or Tri-State. Sleep mode disables power to all circuitry except for low-leakage circuitry that retains the last device configuration. The output is stopped and is held at High-Z after completing the last cycle glitch-free. 3.2. Output Rise and Fall Settings The Si50x clock output is programmable. This enables reduction of electromagnetic interference (EMI) radiation from the clock output. The amount of EMI reduction is dependent on the output frequency, the harmonic of interest, and the board layout. Lab results using a 50 MHz FOUT and changing the clock tRise/tFall time from 0.7 ns to 8 ns show up to 14 dB of EMI reduction. The tRise/tFall feature also allows the Si50x to match competing devices' rise and fall times. Crystal oscillator tRise/tFall behavior is largely dependent on the supply voltage. In crystal-based oscillators, a higher supply voltage will generally drive a more rapid tRise/tFall time. The Si50x configuration options allow the user to match the tRise/tFall to the supply voltage. The Si50x also provides a specified tRise/tFall with a given supply voltage and a 50 trace impedance. See Table 3 for Si50x tRise/tFall specifications. 4. Pin Descriptions FS/OE 1 GND 2 4 VDD 3 CLK Figure 9. Si501/2/3 Table 11. Pin Description Pin Name Function 1 FS/OE FS=Frequency Select. Si502 and Si503 only. OE=Output Enable. Si501 and Si502 only. 2 GND Ground. 3 CLK Output clock. 4 VDD Power supply. Bypass with a 0.1F capacitor placed as close to the VDD pin as possible. Rev. 1.0 13 Si501/2/3 5. Ordering Guide The Si50x family of CMEMS oscillators are highly configurable. Each orderable part number must be specified according to the guidelines below. Each customized part's performance is guaranteed to operate within the data sheet specifications. An on-line configuration and ordering tool is available at www.siliconlabs.com/cmems. 5.1. Si501 Ordering Guide and Part Number Syntax Jittervs Power VDD A B C D E F G H J K L M N P 1.73.6 3.3V 2.5V 1.8V 1.73.6 1.73.6 1.73.6 1.73.6 3.3V 2.5V 1.8V 1.73.6 1.73.6 1.73.6 Low Power Low Jitter TYP TR/TF 0.7ns1 1.3ns2 1.3ns2 1.3ns2 3ns3 5ns3 8ns3 0.7ns1 1.3ns2 1.3ns2 1.3ns2 3ns3 5ns3 8ns3 501 A B C D E F G H J K L M J C A OE High Enable Enable Enable Stop Doze Sleep Enable Enable Enable Stop Doze Sleep OE Internal Low PullResistor Stop PullUp Doze PullUp Sleep PullUp Enable PullDown Enable PullDown Enable PullDown Stop None Doze None Sleep None Enable None Enable None Enable None B C D Package Dimension 3.2x5mm4 2.5x3.2mm 2x2.5mm Temp Range F 20to70C G 40to85C Reel R Reel CutTape D A G R Revision OPN Prefix 501 502 503 504 Ppm Description Singlefrequency Dual frequency Quad frequency Anyfrequency A B C 50 30 20 Frequency Code Mxxxxxx xMxxxxx xxMxxxx 100M000 xxxxxx Description fOUT <1MHz 1MHzfOUT <10MHz 10MHzfOUT <100MHz fOUT =100MHz 6digitcodefor>6decimalresolution Note: 1. Series termination resistor (RS) is recommended for this configuration. See Table 3 and Section 2. 2. Series termination resistor is not needed for this configuration. Output impedance is 50 for the indicated supply condition. 3. Series termination resistor is not needed for this configuration. Reduced EMI setting. 4. Silicon Labs 3.2 x 5 mm package is delivered as 3.2 x 4 mm and accommodates the industry-standard 3.2 x 5 mm footprint. Figure 10. Si501 Part Number Syntax 14 Rev. 1.0 Si501/2/3 5.2. Si502 Ordering Guide and Part Number Syntax Jittervs Power VDD A B C D E F G H J K L M N P 1.73.6 3.3V 2.5V 1.8V 1.73.6 1.73.6 1.73.6 1.73.6 3.3V 2.5V 1.8V 1.73.6 1.73.6 1.73.6 Low Power Low Jitter TYP TR/TF 0.7ns1 1.3ns2 1.3ns2 1.3ns2 3ns3 5ns3 8ns3 0.7ns1 1.3ns2 1.3ns2 1.3ns2 3ns3 5ns3 8ns3 502 A B C D E F OE Low5 Stop Doze Sleep Stop Doze Sleep Internal PullResistor PullUp PullUp PullUp None None None B C D Package Dimension 3.2x5mm4 2.5x3.2mm 2x2.5mm Temp Range F 20to70C G 40to85C Reel R J C A Reel CutTape D A G R Revision OPN Prefix 501 502 503 504 Ppm Description Singlefrequency Dual frequency Quad frequency Anyfrequency A B C 50 30 20 Frequency Code xxxxxx Description 6digitcodefromSilicon Labs Note: 1. Series termination resistor (RS) is recommended for this configuration. See Table 3 and Section 2. 2. Series termination resistor is not needed for this configuration. Output impedance is 50 for the indicated supply condition. 3. Series termination resistor is not needed for this configuration. Reduced EMI setting. 4. Silicon Labs 3.2 x 5 mm package is delivered as 3.2 x 4 mm and accommodates the industry-standard 3.2 x 5 mm footprint. 5. The Si502 OE pin has three (3) states: OE High = Freq 1; OE Weak High = Freq 2; OE Low is configurable. Figure 11. Si502 Part Number Syntax Rev. 1.0 15 Si501/2/3 5.3. Si503 Ordering Guide and Part Number Syntax Jittervs Power VDD A B C D E F G H J K L M N P 1.73.6 3.3V 2.5V 1.8V 1.73.6 1.73.6 1.73.6 1.73.6 3.3V 2.5V 1.8V 1.73.6 1.73.6 1.73.6 Low Power Low Jitter TYP TR/TF 0.7ns1 1.3ns2 1.3ns2 1.3ns2 3ns3 5ns3 8ns3 0.7ns1 1.3ns2 1.3ns2 1.3ns2 3ns3 5ns3 8ns3 503 Internal PullResistor PullUp None A B B C D Package Dimension 3.2x5mm4 2.5x3.2mm 2x2.5mm Temp Range F 20to70C G 40to85C Reel R J C A Reel CutTape D A G R Revision OPN Prefix 501 502 503 504 Ppm Description Singlefrequency Dual frequency Quad frequency Anyfrequency A B C 50 30 20 Frequency Code xxxxxx Description 6digitcodefromSiliconLabs Note: 1. Series termination resistor (RS) is recommended for this configuration. See Table 3 and Section 2. 2. Series termination resistor is not needed for this configuration. Output impedance is 50 for the indicated supply condition. 3. Series termination resistor is not needed for this configuration. Reduced EMI setting. 4. Silicon Labs 3.2 x 5 mm package is delivered as 3.2 x 4 mm and accommodates the industry-standard 3.2 x 5 mm footprint. Figure 12. Si503 Part Number Syntax 16 Rev. 1.0 Si501/2/3 6. Package Dimensions and Land Patterns 6.1. Package Outline: 3.2 x 5 mm 4-pin DFN 2.54 4.000.15 #4 #3 VDD CLK 3.200.15 1.20 Top View GND FS/OE #1 1.34 2.20 0.94 1.60 #2 1.20 1.50 0.90 Max Note: Layout and pin-compatible with industry-standard 3.2 x 5 mm footprint. Figure 13. 3.2 x 5 mm 4-pin DFN 6.2. Package Outline: 2.5 x 3.2 mm 4-pin DFN 2.20 3.200.15 #4 2.500.15 #3 0.90 Top View 1.90 0.70 1.20 #1 #2 1.20 0.90 1.40 0.90 Max Figure 14. 2.5 x 3.2 mm 4-pin DFN 6.3. Package Outline: 2 x 2.5 mm 4-pin DFN 2.500.15 1.90 #4 2.000.15 #3 0.70 Top View 1.50 0.55 1.00 #1 #2 1.00 0.65 0.90 Max 1.10 Figure 15. 2 x 2.5 mm 4-pin DFN Rev. 1.0 17 Si501/2/3 7. Top Markings 7.1. 3.2 x 5 mm Top Marking 7.2. 3.2 x 5 mm Top Marking Explanation Mark Method: Laser Font Size: 0.60 mm Right-Justified Line 1 Marking: TTTTTT=Trace Code Line 2 Marking 18 Manufacturing Code from the Assembly Purchase Order form. Circle=0.5 mm Diameter Left-Justified Pin 1 Indicator YY=Year WW=Work Week Assigned by the Assembly House. Corresponds to the year and work week of the build date. Rev. 1.0 Si501/2/3 7.3. 2.5 x 3.2 mm Top Marking 7.4. 2.5 x 3.2 mm Top Marking Explanation Mark Method: Laser Font Size: 0.50 mm Right-Justified Line 1 Marking: TTTTT=Trace Code Manufacturing Code from the Assembly Purchase Order form. Line 2 Marking: Circle=0.3 mm Diameter Left-Justified Pin 1 Indicator Y=Year WW=Work Week Assigned by the Assembly House. Corresponds to the year and work week of the build date. Rev. 1.0 19 Si501/2/3 7.5. 2 x 2.5 mm Top Marking 7.6. 2 x 2.5 mm Top Marking Explanation Mark Method: Laser Font Size: 0.50 mm Right-Justified Line 1 Marking: TTTT=Trace Code Manufacturing Code from the Assembly Purchase Order form. Line 2 Marking: Circle=0.3 mm Diameter Left-Justified Pin 1 Indicator Y=Year WW=Work Week 20 Assigned by the Assembly House. Corresponds to the year and work week of the build date. Rev. 1.0 Si501/2/3 DOCUMENT CHANGE LIST Revision 0.2 to Revision 0.3 Revision 0.72 to Revision 1.0 Combined Si501/2/3 data sheets. Modified title page. Modified Table 2. Modified Table 4. Modified Section 2. Modified Section 3. Modified Section 4. Modified Section 5. Updated Table 3. Updated Section 6. Revision 0.3 to Revision 0.4 Modified title page. Modified Table 1. Modified Table 2. Modified Table 3. Modified Table 4. Modified Table 5. Modified Table 6. Modified Table 7. Modified Section 2. Modified Section 4. Modified Section 5. Modified Section 6. Revision 0.4 to Revision 0.41 Modified Table 4. Revision 0.41 to Revision 0.7 Revised supported frequency range. Added MIN/MAX figures to all relevant tables. Revision 0.7 to Revision 0.71 Revised Table 3. Revised Section 5. Revision 0.71 to Revision 0.72 Revised Table 1. Revised Table 2. Revised Table 3. Revised Table 5. Modified Section 2. Added Section 3. Modified Section 4. Rev. 1.0 21 ClockBuilder Pro One-click access to Timing tools, documentation, software, source code libraries & more. Available for Windows and iOS (CBGo only). www.silabs.com/CBPro Timing Portfolio www.silabs.com/timing SW/HW Quality Support and Community www.silabs.com/CBPro www.silabs.com/quality community.silabs.com Disclaimer Silicon Laboratories intends to provide customers with the latest, accurate, and in-depth documentation of all peripherals and modules available for system and software implementers using or intending to use the Silicon Laboratories products. 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