DECEMBER 2005
DSC-5282/08
1
©2004 Integrated Device Technology, Inc.
128K x 36, 256K x 18,
3.3V Synchronous ZBT™ SRAMs
3.3V I/O, Burst Counter,
Flow-Through Outputs
Pin Description Summary
it read or write.
The IDT71V3557/59 contain address, data-in and control signal
registers. The outputs are flow-through (no output data register). Output
enable is the only asynchronous signal and can be used to disable the
outputs at any given time.
A Clock Enable (CEN) pin allows operation of the IDT71V3557/59
to be suspended as long as necessary. All synchronous inputs are
ignored when (CEN) is high and the internal device registers will hold
their previous values.
There are three chip enable pins (CE1, CE2, CE2) that allow the user
to deselect the device when desired. If any one of these three is not asserted
when ADV/LD is low, no new memory operation can be
initiated. However, any pending data transfers (reads or writes) will
be completed. The data bus will tri-state one cycle after chip is de-
selected or a write is initiated.
The IDT71V3557/59 have an on-chip burst counter. In the burst
mode, the IDT71V3557/59 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the LBO input pin. The LBO pin selects between linear and
interleaved burst sequence. The ADV/LD signal is used to load a new
external address (ADV/LD = LOW) or increment the internal burst counter
(ADV/LD = HIGH).
The IDT71V3557/59 SRAMs utilize IDT's latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and a 165 fine pitch ball grid array (fBGA).
Features
◆◆
◆◆
◆128K x 36, 256K x 18 memory configurations
◆◆
◆◆
◆Supports high performance system speed - 100 MHz
(7.5 ns Clock-to-Data Access)
◆◆
◆◆
◆ZBTTM Feature - No dead cycles between write and read
cycles
◆◆
◆◆
◆Internally synchronized output buffer enable eliminates
the need to control OEOE
OEOE
OE
◆◆
◆◆
◆Single R/WW
WW
W
(READ/WRITE) control pin
◆◆
◆◆
◆4-word burst capability (Interleaved or linear)
◆◆
◆◆
◆Individual byte write (BWBW
BWBW
BW1 - BWBW
BWBW
BW4) control (May tie active)
◆◆
◆◆
◆Three chip enables for simple depth expansion
◆◆
◆◆
◆3.3V power supply (±5%), 3.3V (±5%) I/O Supply (VDDQ)
◆◆
◆◆
◆Optional Boundary Scan JTAG Interface (IEEE 1149.1
complaint)
◆◆
◆◆
◆Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine
pitch ball grid array (fBGA)
Description
The IDT71V3557/59 are 3.3V high-speed 4,718,592-bit (4.5 Mega-
bit) synchronous SRAMs organized as 128K x 36/256K x 18. They are
designed to eliminate dead bus cycles when turning the bus around
between reads and writes, or writes and reads. Thus they have been
given the name ZBTTM, or Zero Bus Turnaround.
Address and control signals are applied to the SRAM during one clock
cycle, and on the next clock cycle the associated data cycle occurs, be
A
0
-A
17
Addre ss Inputs
Input
Synchronous
CE
1
, CE
2
,
CE
2
Chi p Ena b le s
Input
Synchronous
OE
Outp ut E nab le
Input
Asynchronous
R/
W
Read /Write Sig nal
Input
Synchronous
CEN
Clock Enable
Input
Synchronous
BW
1
,
BW
2
,
BW
3
,
BW
4
Individual Byte Write Selects
Input
Synchronous
CLK
Clock
Input
N/A
ADV/
LD
Advance burst address / Load new address
Input
Synchronous
LBO
Linear / Inte rleaved Burst Order
Input
Static
TMS
Test Mode Select
Input
Synchronous
TDI
Tes t Da ta In pu t
Input
Synchronous
TCK
Test Clock
Input
N/A
TDO
Test D at a O u t pu t
Output
Synchronous
TRST
JTAG Reset (Optional)
Input
Asynchronous
ZZ
Sleep Mode
Input
Synchronous
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
Data Inp ut / Outp ut
I/O
Synchronous
V
DD
, V
DDQ
Core Po wer, I/O Powe r
Supply
Static
V
SS
Ground
Supply
Static
5282 tbl 01
IDT71V3557S
IDT71V3559S
IDT71V3557SA
IDT71V3559SA
6.422
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Pin Definitions (1)
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
Symbol
Pi n Function
I/O
Active
Description
A0-A17 Address Inputs I N/A Synchronous Address inputs. The address register is triggere d by a combination of the rising edge of CLK,
ADV/LD lo w, CEN low, and true chip enables.
ADV/LD Ad vance / Load I N/A ADV/ LD is a s ynchro nous input that is used to lo ad the inte rnal re gis ters with new ad d re s s and co ntrol when i t
is sampled low at the rising edge of clock with the chip selecte d. When ADV/ LD is l ow w ith the chi p
deselected, any burst in progress is terminated. When ADV/ LD is sampled high then the internal burst
counter is advanced for any burst that was in progress. The external addresses are ignored when ADV/ LD is
sampled high.
R/WRe ad / Wri te I N/ A R/ W signal is a synchronous input that identifies whether the current load cycle initiated is a Read or Write
acce ss to the memory array. The data bus activity for the current cycle takes place one clock cycle later.
CEN Clo ck Enable I LOW Synchrono us Clock Enab le Inp ut. When CEN is sampled high, all other synchronous inputs, including clock
are ignored and outputs remain unc hanged. The effect of CEN sampled high on the device outputs is as if
the low to high clock transition did not occur. For normal operation, CEN must be samp led low at rising edge
of clock.
BW1-BW4Ind iv id ual By te
Write En ab les I LOW S ync hro no us b yte write e nab le s . E ach 9-b it b yte has its o wn ac tiv e lo w b yte write e nab le . On lo ad write
cycle s (When R/W and ADV/ LD are sampled low) the ap prop riate byte write signal (BW1-BW4) must be valid.
The byte write signal must also be valid on each cycle of a burst write. Byte Write signals are ignored when
R/W is sampled high. The ap propriate byte(s) of data are written into the d evice one cycle later. BW1-BW4
can all b e tie d lo w if always do ing write to the entire 36-b it wo rd.
CE1, CE2Chip E nab les I LOW Synchronous ac tive low chip enable. CE1 and CE2 are use d with CE 2 to enable the IDT71V3557/59. (CE1 or
CE2 sampled high or CE2 sampled low) and ADV/LD low at the rising edge of clock, initiates a deselect
cycle. The ZBTTM has a one cycle dese lect, i.e., the data bus will tri-state one clock cycle after de select is
initiated.
CE2Chi p E nab le I HIGH S yn chro no us activ e hi g h chi p e nab le . CE 2 is us ed with CE1 and CE2 to enable the chip. CE2 has inverted
polarity but otherwise identical to CE1 and CE2.
CLK Clock I N/A This is the clock input to the IDT71V3557/59. Except for OE, all timing re fe re nce s for the d e v ic e are mad e
with respect to the rising edge of CLK.
I/O0-I/O31
I/OP1-I/OP4 Data Input/Outp ut I/O N/A Data input/outp ut (I/O) p ins. The d ata inp ut path is registered, triggered by the rising e dge of CLK. The data
output path is flow-through (no output re gister).
LBO Linear Burst Order I LOW Burst order selection input. When LBO is high the Interleaved burst sequence is selected. When LBO is low
the Linear burst sequence is selected. LBO is a static input, and it must not change during device operation..
OE Outp ut Enable I LOW As ync hronous o utp ut e nabl e. OE mus t b e l o w to re ad data fro m the 7 1V 3557/59 . Whe n OE i s HI GH the I/ O
pins are in a high-impedance state. OE d o e s no t ne ed to be activ e ly co ntro ll e d fo r read and write cyc le s. In
norm al o p e r ation , OE can be tied low.
TMS Test Mode Select I N/A Gives input command for TAP co ntroller. Sampled on rising e dge of TDK. This pin has an inte rnal pullup.
TDI Te st Data Inp ut I N/A Serial input of registe rs placed between TDI and TDO. Sampled on rising edge of TCK. This pin has an
internal pullup.
TCK Test Clock I N/A Clock input of TAP controller. Each TA P event is clocked. Test inputs are captured o n rising edge of TCK,
while test outputs are driven from the falling edge of TCK. This pin has an inte rnal pullup.
TDO Te st Data Outp ut O N/ A Serial outp ut of reg is ters place d between TDI and TDO. This outp ut is active de pending on the state of the
TAP controller.
TRST
JTAG Reset
(Optional) ILOW
Op ti o nal As y nchr o no us JTA G r e s e t. C an b e u s e d to re s e t the TA P contr o l le r, b ut not r e q ui red . J TA G r e s e t
oc curs automatically at p o we r up and also resets usi ng TMS and TCK p e r IEEE 1149.1. If not us ed TRST can
be left floating. This pin has an inte rnal pullup.
ZZ Sleep Mode I HIGH Synchronous sleep mode input. ZZ HIGH will gate the CLK internally and power d own the IDT71V3557/3559 to
its lowest po wer consumption level. Data retention is guarante ed in Sleep Mode. This pin has an internal
pulldown.
VDD Power Sup ply N/A N/A 3.3V c ore power sup ply.
VDDQ Power S upp l y N/ A N/ A 3.3 V I/ O Su p p l y.
VSS Ground N/A N/A Ground.
5282 tbl 02
6.42
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
3
Functional Block Diagram 128K x 36
Clk
DQ
DQ
DQ
Address A [0:16]
Control Logic
Address
Control
DI DO
Input Register
5282 drw 01
Clock
Data I/O [0:31], I/O P[1:4]
Mux Sel
Gate
OE
CE1,CE
2CE2
R/W
CEN
ADV/LD
BWx
LBO 128K x 36 BIT
MEMORY ARRAY
,
JTAG
(SA Version)
TMS
TDI
TCK TDO
TRST
(optional)
6.424
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Functional Block Diagram 256K x 18
Recommended DC Operating
Conditions
NOTES:
1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.
2. VIH (max.) = +6.0V for pulse width less than tCYC/2, once per cycle.
Clk
DQ
DQ
DQ
Address A [0:17]
Control Logic
Address
Control
DI DO
Input Register
5282 drw 01a
Clock
Data I/O [0:15], I/O P[1:2]
Mux Sel
Gate
OE
CE1,CE
2CE2
R/W
CEN
ADV/LD
BWx
LBO 256K x 18 BIT
MEMORY ARRAY
,
JTAG
(SA Version)
TMS
TDI
TCK TDO
TRST
(optional)
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
DD
Core Supply Voltage 3.135 3.3 3.465 V
V
DDQ
I/O Supply Voltage 3.135 3.3 3. 465 V
V
SS
Ground 0 0 0 V
V
IH
Input High Voltage - In puts 2.0 ____ V
DD
+ 0.3 V
V
IH
Input High Volt age - I/O 2.0 ____ V
DDQ
+ 0.3(2) V
V
IL
Input Low Vo lt age -0. 3(1) ____ 0.8 V
5282 tbl 04
6.42
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
5
Recommended Operating
Temperature and Supply Voltage
Pin Configuration 128K x 36
NOTES:
1. Pins 14, 64, and 66 do not have to be connected directly to VSS as long as the input voltage is < VIL.
2. Pin 16 does not have to be connected directly to VDD as long as the input voltage is > VIH.
3. Pins 83 and 84 are reserved for future 8M and 16M respectively.
4. Pin 64 supports ZZ (sleep mode) for the latest die revisions.
Top View
100 TQFP
100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 8189 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
CE
1
CE
2
BW
4
BW
3
BW
2
BW
1
CE
2
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/LD
NC
(3)
NC
(3)
A
8
A
9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
LBO
A
14
A
13
A
12
A
11
A
10
V
DD
V
SS
A
0
A
1
A
2
A
3
A
4
A
5
I/O
31
I/O
30
V
DDQ
V
SS
I/O
29
I/O
28
I/O
27
I/O
26
V
SS
V
DDQ
I/O
25
I/O
24
V
SS
V
DD
I/O
23
I/O
22
V
DDQ
V
SS
I/O
21
I/O
20
I/O
19
I/O
18
V
SS
V
DDQ
I/O
17
I/O
16 80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O
14
V
DDQ
V
SS
I/O
13
I/O
12
I/O
11
I/O
10
V
SS
V
DDQ
I/O
9
I/O
8
V
SS
V
DD
I/O
7
I/O
6
V
DDQ
V
SS
I/O
5
I/O
4
I/O
3
I/O
2
V
SS
V
DDQ
I/O
1
I/O
0
5282 drw 02
V
SS(1)
I/O
15
I/O
P3
V
DD(2)
I/O
P4
A
15
A
16
I/O
P1
V
SS/ZZ(1,4)
I/O
P2
V
SS(1)
,
NC
NC
NC
Grade
Temperature
(1)
V
SS
V
DD
V
DDQ
Comme rcial 0°C to +70° C 0V 3.3V± 5% 3.3V± 5%
Industrial -40° C to + 85°C 0V 3.3V±5% 3.3V± 5%
5282 tbl 05
NOTES:
1. TA is the "instant on" case temperature.
6.426
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings (1)
100 TQFP Capacitance(1)
(TA = +25°C, F = 1.0MHZ)
Pin Configuration 256K x 18
NOTES:
1. Pins 14, 64, and 66 do not have to be connected directly to VSS as long as the input voltage
is < V IL.
2. Pin 16 does not have to be connected directly to VDD as long as the input voltage
is > VIH.
3. Pins 83 and 84 are reserved for future 8M and 16M respectively.
4. Pin 64 supports ZZ (sleep mode) for the latest die revisions.
Top View
100 TQFP
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed VDDQ during power
supply ramp up.
7. TA is the "instant on" case temperature.
10099989796959493929190 8786858483828189 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
CE
1
CE
2
NC
NC
BW
2
BW
1
CE
2
V
DD
V
SS
CLK
R/W
CEN
OE
ADV/LD
NC
(3)
NC
(3)
A
8
A
9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC
LBO
A
15
A
14
A
13
A
12
A
11
V
DD
V
SS
A
0
A
1
A
2
A
3
A
4
A
5
NC
NC
VDDQ
VSS
NC
I/OP2
I/O15
I/O14
VSS
VDDQ
I/O13
I/O12
VSS
VDD
I/O11
I/O10
VDDQ
VSS
I/O9
I/O8
NC
NC
VSS
VDDQ
NC
NC 80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
VDDQ
VSS
NC
I/OP1
I/O7
I/O6
VSS
VDDQ
I/O5
I/O4
VSS
VDD
I/O3
I/O2
VDDQ
VSS
I/O1
I/O0
NC
NC
VSS
VDDQ
NC
NC
5282 drw 02a
VSS(1)
NC
NC
VDD(2)
NC
A
16
A
17
NC
VSS(1)
A10
VSS/ZZ(1,4)
,
NC
NC
NC
Symbol
Rating
Commercial &
Industrial Values
Unit
V
TERM
(2) Te rminal Voltage with
Re s p e ct to GND -0.5 to +4.6 V
V
TERM
(3,6) Terminal Voltage with
Re s p e ct to GND -0.5 to V
DD
V
V
TERM
(4,6) Terminal Voltage with
Re s p e ct to GND -0.5 to V
DD
+0.5 V
V
TERM
(5,6) Terminal Voltage with
Re s p e ct to GND -0.5 to V
DDQ
+0.5 V
T
A
(7)
Commercial
Operating Temperature -0 to +70 oC
Industrial
Operating Temperature -40 to +85 oC
T
BIAS
Temperature
Under Bias -55 to +125 oC
T
STG
Storage
Temperature -55 to +125 oC
P
T
Po wer Dis sipatio n 2. 0 W
I
OUT
DC Output Curre nt 50 mA
5282 tbl 06
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
Inp ut Cap acitanc e
V
IN
= 3d V
5
pF
C
I/O
I/O Cap acitance
V
OUT
= 3d V
7
pF
5282 tbl 07
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
Inp ut Cap ac itance
V
IN
= 3d V
7
pF
C
I/O
I/O Cap acitance
V
OUT
= 3d V
7
pF
5282 tbl 07a
119 BGA Capacitance(1)
(TA = +25°C, F = 1.0MHZ)
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
Inp ut Cap acitanc e
V
IN
= 3d V
TBD
pF
C
I/O
I/O Cap acitance
V
OUT
= 3d V
TBD
pF
5282 tbl 07b
119 BGA Capacitance(1)
(TA = +25°C, F = 1.0MHZ)
6.42
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
7
Pin Configuration 128K x 36, 119 BGA
Pin Configuration - 256K x 18, 119 BGA
Top View
Top View
NOTES:
1. R5 and J5 do not have to be directly connected to VSS as long as the input voltage is < VIL.
2. J3 does not have to be directly connected directly to VDD as long as the input voltage is ≥ VIH.
3. G4 and A4 are reserved for future 8M and 16M respectively.
4. These pins are NC for the "S" version and the JTAG signal listed for the "SA" version.
5. TRST is offered as an optional JTAG reset if requested in the application. If not needed, can be left floating and will internally be pulled to VDD.
6. Pin T7 supports ZZ (sleep mode) for the latest die revisions.
1234567
AVDDQ A6A4A8A16 VDDQ
BNC CE2A3ADV/LD A9CE2NC
CA7A2VDD A12 A15 NC
DI/O16 I/OP3 VSS NC VSS I/OP2 I/O15
EI/O17 I/O18 VSS VSS I/O13 I/O14
FVDDQ I/O19 VSS OE VSS I/O12 VDDQ
GI/O20 I/O21 BW3BW2I/O11 I/O10
HI/O22 I/O23 VSS R/WVSS I/O9I/O8
JVDDQ VDD VDD VDD VDDQ
KI/O24 I/O26 VSS CLK VSS I/O6I/O7
LI/O25 I/O27 BW4NC BW1I/O4I/O5
MVDDQ I/O28 VSS CEN VSS I/O3VDDQ
NI/O29 I/O30 VSS A1VSS I/O2I/O1
PI/O31 I/OP4 VSS A0VSS I/O 0
I/O
P1
RNC A5LBO VDD A13
TNC NC A10 A11 A14 NC NC/ZZ(6)
UVDDQ NC/TMS(4) NC/TDI(4) NC/TCK(4) NC/TDO(4) NC/TRST(4,5) VDDQ
5282 drw 13A
VSS(1)
NC
NC(3)
CE1
NC(3)
VDD(2) VSS(1)
,
NC
1234567
AVDDQ A6A4NC(3) A8A16 VDDQ
BNC CE2 A3ADV/LD A9CE2NC
CA7A2VDD A13 A17 NC
DI/O8NC VSS NC VSS I/OP1 NC
ENC I/O9VSS VSS NC I/O7
FVDDQ NC VSS OE VSS I/O6VDDQ
GNC I/O10 BW2NC I/O5
HI/O11 NC VSS R/WVSS I/O4NC
JVDDQ VDD VDD VDD VDDQ
KNC I/O12 VSS CLK VSS NC I/O3
LI/O13 NC NC BW1I/O2NC
MVDDQ I/O14 VSS CEN VSS NC VDDQ
NI/O15 NC VSS A1VSS I/O1NC
PNC I/OP2 VSS A0VSS NC I/O0
RNC A5LBO VDD A12
TNC A10 A15 NC A14 A11 NC/ZZ(6)
UVDDQ NC/TMS(4) NC/TDI(4) NC/TCK(4) NC/TDO(4) NC/TRST(4,5) VDDQ
5282 drw 13B
NC
SS(1)
V
VSS
VSS
CE1
NC(3)
VDD(2) VSS(1)
,
NC
6.428
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Pin Configuration 128K x 36, 165 fBGA
Pin Configuration - 256K x 18, 165 fBGA
NOTES:
1. H1 and N7 do not have to be directly connected to VSS as long as the input voltage is < VIL.
2. H2 does not have to be directly connected directly to VDD as long as the input voltage is ≥ VIH.
3. A9, B9, B11, A1, R2, and P2 are reserved for future 9M, 18M, 36M, 72M, 144M, and 288M respectively.
4. These pins are NC for the "S" version and the JTAG signal listed for the "SA" version.
5. TRST is offered as an optional JTAG reset if requested in the application. If not needed, can be left floating and will internally be pulled to VDD.
6. Pin H11 supports ZZ (sleep mode) for the latest die revisions.
1234567891011
ANC
(3) A7CE1BW3BW2CE2CEN ADV/LD NC(3) A8NC
BNC A
6CE2BW4BW1CLK R/WOE NC(3) A9NC(3)
CI/O
P3 NC VDDQ VSS VSS VSS VSS VSS VDDQ NC I/OP2
DI/O
17 I/O16 VDDQ VDD VSS VSS VSS VDD VDDQ I/O15 I/O14
EI/O
19 I/O18 VDDQ VDD VSS VSS VSS VDD VDDQ I/O13 I/O12
FI/O
21 I/O20 VDDQ VDD VSS VSS VSS VDD VDDQ I/O11 I/O10
GI/O
23 I/O22 VDDQ VDD VSS VSS VSS VDD VDDQ I/O9I/O8
HV
SS(1) VDD(2) NC VDD VSS VSS VSS VDD NC NC NC/ZZ(6)
JI/O
25 I/O24 VDDQ VDD VSS VSS VSS VDD VDDQ I/O7I/O6
KI/O
27 I/O26 VDDQ VDD VSS VSS VSS VDD VDDQ I/O5I/O4
LI/O
29 I/O28 VDDQ VDD VSS VSS VSS VDD VDDQ I/O3I/O2
MI/O
31 I/O30 VDDQ VDD VSS VSS VSS VDD VDDQ I/O1I/O0
NI/O
P4 NC VDDQ VSS NC/TRST
(4,5) NC VSS(1) VSS VDDQ NC I/OP1
PNCNC
(3) A5A2NC/TDI(4) A1NC/TDO(4) A10 A13 A14 NC
RLBO NC(3) A4A3NC/TMS(4) A0NC/TCK(4) A11 A12 A15 A16
5282 tb l 25
1234567891011
ANC
(3) A7CE1BW2NC CE2CEN ADV/LD NC(3) A8A10
BNC A
6CE2NC BW1CLK R/WOE NC(3) A9NC(3)
CNC NCV
DDQ VSS VSS VSS VSS VSS VDDQ NC I/OP1
DNC I/O
8VDDQ VDD VSS VSS VSS VDD VDDQ NC I/O7
ENC I/O
9VDDQ VDD VSS VSS VSS VDD VDDQ NC I/O6
FNCI/O
10 VDDQ VDD VSS VSS VSS VDD VDDQ NC I/O5
GNC I/O
11 VDDQ VDD VSS VSS VSS VDD VDDQ NC I/O4
HVss
(1) VDD(2) NC VDD VSS VSS VSS VDD NC NC NC/ZZ(6)
JI/O
12 NC VDDQ VDD VSS VSS VSS VDD VDDQ I/O3NC
KI/O
13 NC VDDQ VDD VSS VSS VSS VDD VDDQ I/O2NC
LI/O
14 NC VDDQ VDD VSS VSS VSS VDD VDDQ I/O1NC
MI/O
15 NC VDDQ VDD VSS VSS VSS VDD VDDQ I/O0NC
NI/O
P2 NC VDDQ VSS NC/TRST
(4,5) NC VSS(1) VSS VDDQ NC NC
PNC NC
(3) A5A2NC/TDI(4) A1NC/TDO(4) A11 A14 A15 NC
RLBO NC(3) A4A3NC/TMS(4) A0NC/TCK(4) A12 A13 A16 A17
5282 tb l 25a
6.42
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
9
Interleaved Burst Sequence Table (LBO=VDD)
Partial Truth Table for Writes (1)
Synchronous Truth Table (1)
NOTES:
1 . L = VIL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of
the burst cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will
tri-state one cycle after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all th e internal registers and the I/
Os remains unchanged.
5. To select the chip requires CE1 = L, CE2 = L and CE2 = H on these chip enable pins. The chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z during device power-up.
7. Q - data read from the device, D - data written to the device.
NOTES:
1 . L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
3. N/A for x18 configuration.
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
CEN
R/
WCE
1
,
CE
2
(5)
ADV/
LD BW
x
ADDRESS
USED
PREVIOUS CYCLE
CURRE NT CYCLE
I/O
(One cycle l ater)
L L L L Valid Exte rnal X LOAD WRITE D(7)
L H L L X Ex te rnal X LOAD READ Q(7)
L X X H Vali d Inte rnal LOA D WRITE /
BURS T WRITE BURS T WRITE
(Advance burst counter)(2) D(7)
L X X H X Inte rnal LOA D RE AD /
BURST READ BURST READ
(Advance burst counter)(2) Q(7)
L X H L X X X DESELECT or STOP(3) HIZ
L X X H X X DESELECT / NOOP NOOP HIZ
H X X X X X X SUSPEND(4) Previous Value
5282 tbl 08
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address 0 0 0 1 1 0 1 1
Second Address 0 1 0 0 1 1 1 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address(1) 11100100
5282 tbl 10
OPERATION
R/
WBW
1
BW
2
BW
3
(3)
BW
4
(3)
READ HXXXX
WRITE ALL BYTES LLLLL
WRITE BYTE 1 (I/O[0:7], I/O
P1
)(2) LLHHH
WRITE BYTE 2 (I/O[8:15], I/O
P2
)(2) LHLHH
WRITE BYTE 3 (I/O[16:23], I/O
P3
)(2,3) LHHLH
WRITE BYTE 4 (I/O[24:31], I/O
P4
)(2,3) LHHHL
NO WRITE LHHHH
5282 tbl 09
6.4210
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Functional Timing Diagram (1)
Linear Burst Sequence Table (LBO=VSS)
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
NOTES:
1. This assumes CEN, CE1, CE2 and CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
delay from the rising edge of clock.
n+29
A29
C29
D/Q28
ADDRESS
(A0-A
16)
CONTROL
(R/W,ADV/LD,BWx)
DATA
I/O [0:31], I/O P[1:4]
CYCLE
CLOCK
n+30
A30
C30
D/Q29
n+31
A31
C31
D/Q30
n+32
A32
C32
D/Q31
n+33
A33
C33
D/Q32
n+34
A34
C34
D/Q33
n+35
A35
C35
D/Q34
n+36
A36
C36
D/Q35
n+37
A37
C37
D/Q36
5282 drw 03
(2)
(2)
(2) ,
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
A1
A0
A1
A0
A1
A0
First Address 0 0 0 1 1 0 1 1
Second Address 0 1 1 0 1 1 0 0
Third Address 1 0 1 1 0 0 0 1
Fourth Address(1) 11000110
5282 tbl 11
6.42
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
11
NOTES:
1. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
2. H = High; L = Low; X = Don't Care; Z = High Impedence.
Device Operation - Showing Mixed Load, Burst,
Deselect and NOOP Cycles (2)
Cycle
Address
R/
W
ADV/
LD CE
1
(1)
CEN BW
x
OE
I/O
Comments
nA
0
HL LLXXD
1
Lo ad re ad
n+1 X X H X L X L Q
0
Burst re ad
n+2 A
1
HL LLXLQ
0+1
Lo ad re ad
n+3 X X L H L X L Q
1
Deselect or STOP
n+4 X X H X L X X Z NOOP
n+5 A
2
H L L L X X Z Load read
n+6 X X H X L X L Q
2
Burst re ad
n+7 X X L H L X L Q
2+1
Deselect or STOP
n+8 A
3
L L LLLXZLoad write
n+9 X X H X L L X D
3
Burst write
n+10 A
4
L L LLLXD
3+1
Lo ad write
n+11 X X L H L X X D
4
Deselect or STOP
n+12 X X H X L X X Z NOOP
n+13 A
5
L L LLLXZLoad write
n+14 A
6
HL LLXXD
5
Lo ad re ad
n+15 A
7
L L LLLLQ
6
Lo ad write
n+16 X X H X L L X D
7
Burst write
n+17 A
8
HL LLXXD
7+1
Lo ad re ad
n+18 X X H X L X L Q
8
Burst re ad
n+19 A
9
L L LLLLQ
8+1
Lo ad write
5282 tbl 12
6.4212
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Read Operation (1)
Burst Write Operation (1)
Burst Read Operation (1)
Write Operation (1)
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Cycle
Address
R/
W
ADV/
LD CE
1
(2)
CEN BW
x
OE
I/O
Comments
nA
0
H L L L X X X Address and Control meet setup
n+1 X X X X X X L Q
0
Contents of Address A
0
Re ad Out
5282 tbl 13
Cycle
Address
R/
W
ADV/
LD CE
1
(2)
CEN BW
x
OE
I/O
Comments
nA
0
H L L L X X X Address and Control meet setup
n+1 X X H X L X L Q
0
Address A
0
Read Out, Inc. Count
n+2 X X H X L X L Q
0+1
Address A
0+1
Read Out, Inc. Count
n+3 X X H X L X L Q
0+2
Address A
0+2
Read Out, Inc. Count
n+4 X X H X L X L Q
0+3
Address A
0+3
Read Out, Load A
1
n+5 A
1
HL LLXLQ
0
Address A
0
Read Out, Inc. Count
n+6 X X H X L X L Q
1
Address A
1
Read Out, Inc. Count
n+7 A
2
HL LLXLQ
1+1
Address A
1+1
Read Out, Load A
2
5282 tbl 14
Cycle
Address
R/
W
ADV/
LD CE
1
(2)
CEN BW
x
OE
I/O
Comments
nA
0
L L L L L X X Address and Control meet setup
n+1 X X X X L X X D
0
Write to Address A
0
5282 tbl 15
Cycle
Address
R/
W
ADV/
LD CE
1
(2)
CEN BW
x
OE
I/O
Comments
nA
0
L L L L L X X Address and Control meet setup
n+1 X X H X L L X D
0
Address A
0
Write, Inc. Count
n+2 X X H X L L X D
0+1
Address A
0+1
Write, Inc. Count
n+3 X X H X L L X D
0+2
Address A
0+2
Write, Inc. Count
n+4 X X H X L L X D
0+3
Address A
0+3
Write , Lo ad A
1
n+5 A
1
L L LLLXD
0
Address A
0
Write, Inc. Count
n+6 X X H X L L X D
1
Address A
1
Write, Inc. Count
n+7 A
2
L L LLLXD
1+1
Address A
1+1
Write , Lo ad A
2
5282 tbl 16
6.42
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
13
Read Operation with Clock Enable Used (1)
Write Operation with Clock Enable Used (1)
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
Cycle
Address
R/
W
ADV/
LD CE
1
(2)
CEN BW
x
OE
I/O
Comments
nA
0
H L L L X X X AddressA
0
and Control meet setup
n+1 X X X X H X X X Clo ck n+1 Igno red
n+2 A
1
HL LLXLQ
0
Address A
0
Read out, Lo ad A
1
n+3 X X X XHXLQ
0
Clock Ignored. Data Q
0
is on the bus.
n+4 X X X XHXLQ
0
Clock Ignored. Data Q
0
is on the bus.
n+5 A
2
HL LLXLQ
1
Address A
1
Re ad o ut, Lo ad A
2
n+6 A
3
HL LLXLQ
2
Address A
2
Re ad o ut, Lo ad A
3
n+7 A
4
HL LLXLQ
3
Address A
3
Re ad o ut, Lo ad A
4
5282 tbl 17
Cycle
Address
R/
W
ADV/
LD CE
1
(2)
CEN BW
x
OE
I/O
Comments
nA
0
L L L L L X X Address A
0
and Control meet setup.
n+1 X X X X H X X X Clo ck n+1 Ig nore d .
n+2 A
1
L L LLLXD
0
Write data D
0
, Load A
1
.
n+3 X X X X H X X X Clock Ignored.
n+4 X X X X H X X X Clock Ignored.
n+5 A
2
L L LLLXD
1
Write Data D
1
, Load A
2
n+6 A
3
L L LLLXD
2
Write Data D
2
, Load A
3
n+7 A
4
L L LLLXD
3
Write Data D
3
, Load A
4
5282 tbl 18
6.4214
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Read Operation with Chip Enable Used (1)
Write Operation with Chip Enable Used (1)
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don't Know; Z = High Impedance.
2. CE2 timing transition is identical to CE1 signal. CE2 timing transition is identical but inverted to the CE1 and CE2 signals.
3. Device outputs are ensured to be in High-Z during device power-up.
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don't Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Cycle
Address
R/
W
ADV/
LD CE
1
(2)
CEN BW
x
OE
I/O
(3)
Comments
n X X L H L X X ? Deselected.
n+1 X X L H L X X Z Deselected.
n+2 A
0
H L L L X X Z Address A
0
and Control meet setup.
n+3 X X L H L X L Q
0
Address A
0
read out, Deselected.
n+4 A
1
H L L L X X Z Address A
1
and Control meet setup.
n+5 X X L H L X L Q
1
Address A
1
read out, Deselected.
n+6 X X L H L X X Z Deselected.
n+7 A
2
H L L L X X Z Address A
2
and Control meet setup.
n+8 X X L H L X L Q
2
Address A
2
read out, Deselected.
n+9 X X L H L X X Z Deselected.
5282 tbl 19
Cycle
Address
R/
W
ADV/
LD CE
(2)
CEN BW
x
OE
I/O
Comments
n
X
X
L
H
L
X
X
?
Deselected.
n+1
X
X
L
H
L
X
X
Z
Deselected.
n+2
A
0
L
L
L
L
L
X
Z
Address A
0
and Control m eet s etup
n+3
X
X
L
H
L
X
X
D
0
Dat a D
0
Write I n, Deselected.
n+4
A
1
L
L
L
L
L
X
Z
Address A
1
and Control m eet s etup
n+5
X
X
L
H
L
X
X
D
1
Dat a D
1
Write I n, Deselected.
n+6
X
X
L
H
L
X
X
Z
Deselected.
n+7
A
2
L
L
L
L
L
X
Z
Address A
2
and Control m eet s etup
n+8
X
X
L
H
L
X
X
D
2
Dat a D
2
Write I n, Deselected.
n+9
X
X
L
H
L
X
X
Z
Deselected.
5282 tbl 20
6.42
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
15
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V +/-5%)
Figure 2. Lumped Capacitive Load, Typical Derating
Figure 1. AC Test Load
AC Test Loads AC Test Conditions (VDDQ = 3.3V)
DC Electrical Characterics Over the Operating
Temperature and Supply Voltage Range (1) (VDD = 3.3V +/-5%)
NOTE:
1. The LBO, JTAG and ZZ pins will be internally pulled to VDD and ZZ will be internally pulled to VSS if it is not actively driven in the application.
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = VDD - 0.2V, VLD = 0.2V.
VDDQ/2
50Ω
I/O Z0=50Ω
5282 drw 04 ,
1
2
3
4
20 30 50 100 200
∆tCD
(Typical, ns)
Capacitance (pF)
80
5
6
5282 drw 05 ,
Symbol
Parameter
Test Condi tions
Min.
Max.
Unit
|I
L
I
| Input Leak age Curre nt V
DD
= Max., V
IN
= 0V to V
DD
___ 5µA
|I
LI
|LBO, JTAG and ZZ Input Leakage Current(1) V
DD
= Max., V
IN
= 0V to V
DD
___ 30 µA
|I
LO
| Outp ut Le akag e Current V
OUT
= 0V to V
CC
___ 5µA
V
OL
Outp ut Lo w Voltage I
OL
= +8mA, V
DD
= Min. ___ 0.4 V
V
OH
Outp ut Hig h Vo ltag e I
OH
= -8mA, V
DD
= Min. 2.4 ___ V
5282 tbl 21
Symbol
Parameter
Test Conditions
7.5ns
8ns
8.5ns
Unit
Com'l Only
Com'l
Ind
Com'l
Ind
I
DD
Operating Power
Supply Current Device Selected, Outputs Open,
ADV/LD = X, V
DD
= Max.,
V
IN
> V
IH
or < V
IL
, f = f
MAX
(2)
275 250 260 225 235 mA
I
SB1
CMOS Standby Power
Supply Current Device Deselected, Outputs Open,
V
DD
= Max., V
IN
> V
HD
or < V
LD
,
f = 0(2,3)
40 40 45 40 45 mA
I
SB2
Clo ck Running Po wer
Supply Current Device Deselected, Outputs Open,
V
DD
= Max., V
IN
> V
HD
or < V
LD
,
f = f
MAX
(2,3)
105 10011095105mA
I
SB3
Id le Po wer
Supply Current Device Selected, Outputs Open,
CEN > V
IH
, V
DD
= Max.,
V
IN
> V
HD
or < V
LD
, f = f
MAX
(2,3)
40 40 45 40 45 mA
5282 tb l 22
Inp ut P ul se Le v e ls
Inp ut Ri s e /F all Tim e s
Inp ut Tim ing Refe re nc e Le v e ls
Outp ut Re fe re nc e Le v e l s
Output Load
0 to 3V
2ns
1.5V
1.5V
Fig ure 1
5282 tbl 23
6.4216
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V +/-5%, Commercial and Industrial Temperature Ranges)
NOTES:
1. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ.
2. Transition is measured ±200mV from steady-state.
3. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
4. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and
voltage. The specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions
(0 deg. C, 3.465V) than tCHZ, which is a Max. parameter (worse case at 70 deg. C, 3.135V).
5. Commercial temperature range only.
7.5ns(5) 8ns 8.5ns
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
CYC
Clock Cycle Time 10 ____ 10.5 ____ 11 ____ ns
t
CH
(1) Clock High Pulse Width 2.5 ____ 2.7 ____ 3.0 ____ ns
t
CL
(1) Clock Low Pulse Width 2.5 ____ 2.7 ____ 3.0 ____ ns
Output Param eters
t
CD
Clo c k Hi g h to Val id Data ____ 7.5 ____ 8____ 8.5 ns
t
CDC
Clock High to Data Change 2 ____ 2____ 2____ ns
t
CLZ
(2,3,4) Cl o ck Hig h to Outp ut Ac tiv e 3 ____ 3____ 3____ ns
t
CHZ
(2,3,4) Cl o ck Hig h to Data Hig h-Z ____ 5____ 5____ 5ns
t
OE
Output Enable Access Time ____ 5____ 5____ 5ns
t
OLZ
(2,3) Ou tp ut Enab le Lo w to Data Ac tive 0 ____ 0____ 0____ ns
t
OHZ
(2,3) Ou tp ut Enab le Hig h to Data Hi g h-Z ____ 5____ 5____ 5ns
Set Up Times
t
SE
Clock Enab le Se tup Time 2.0 ____ 2.0 ____ 2.0 ____ ns
t
SA
Address Setup Time 2.0 ____ 2.0 ____ 2.0 ____ ns
t
SD
Data In S e tup Time 2. 0 ____ 2.0 ____ 2.0 ____ ns
t
SW
Re ad / Write (R/ W) Se tup Time 2. 0 ____ 2.0 ____ 2.0 ____ ns
t
SADV
Ad vance /Load (ADV/ LD) Se tup Ti me 2. 0 ____ 2.0 ____ 2.0 ____ ns
t
SC
Chip Enable/Select Setup Time 2.0 ____ 2.0 ____ 2.0 ____ ns
t
SB
Byte Write Enab le (BWx) Setup Time 2.0 ____ 2.0 ____ 2.0 ____ ns
Hol d T im es
t
HE
Clo ck Enab le Ho ld Time 0.5 ____ 0.5 ____ 0.5 ____ ns
t
HA
Address Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns
t
HD
Data In Ho l d Tim e 0. 5 ____ 0.5 ____ 0.5 ____ ns
t
HW
Re ad / Write (R/ W) Ho ld Time 0. 5 ____ 0.5 ____ 0.5 ____ ns
t
HADV
Ad vance /Load (ADV/ LD) Hold Time 0. 5 ____ 0.5 ____ 0.5 ____ ns
t
HC
Chip Enable/Select Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns
t
HB
Byte Write Enab le (BWx) Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns
5282 tbl 24
6.42
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
17
Timing Waveform of Read Cycle (1,2,3,4)
NOTES:
1. Q (A1) represents the first output from the external address A 1. Q (A2) represents the first output from the external address A2; Q (A2+1) represents the next output data in the burst sequence
of the base address A2, etc. where address bits A0 and A 1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/ W signal when new address and control are
loaded into the SRAM.
(CENhigh, eliminates
current L-H clock edge)
Q(A
2+1
)
t
CD
Read
t
CLZ
t
CHZ
t
CD
t
CDC
Q(A
2+2
)
Q(A
1
)Q(A
2
)Q(A
2+3
)Q(A
2+3
)Q(A
2
)
Burst Read
Read
DATA
OUT
(Burst Wraps around
to initial state)
t
CDC
t
HADV
5282 drw 06
R/W
CLK
ADV/LD
ADDRESS
CE
1
,CE
2(2)
BW
1
-BW
4
OE
t
HE
t
SE
A
1
A
2
t
CH
t
CL
t
CYC
t
SADV
t
HW
t
SW
t
HA
t
SA
t
HC
t
SC
CEN
.
,
6.4218
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycles (1,2,3,4,5)
NOTES:
1. D (A1) represents the first input to the external address A1. D (A2) represents the first input to the external address A2; D (A2+1) represents the next input data in the burst sequence of the base
address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/ LD LOW.
4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/ W signal when new address and control are
loaded into the SRAM.
5. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in one cycle before
the actual data is presented to the SRAM.
t
HE
t
SE
R/W
A
1
A
2
CLK
CEN
ADV/LD
ADDRESS
CE
1
,CE
2(2)
BW
1
-BW
4
OE
DATA
IN
D(A
1
)D(A
2
)
t
HD
t
SD
(CENhigh, eliminates
current L-H clock edge)
D(A
2+1
)D(A
2+2
)D(A
2+3
)D(A
2
)
Burst Write
Write Write
(Burst Wraps around
to initial state)
t
HD
t
SD
t
CH
t
CL
t
CYC
t
HADV
t
SADV
t
HW
t
SW
t
HA
t
SA
t
HC
t
SC
t
HB
t
SB
5282 drw 07
B(A
1
)B(A
2
)B(A
2+1
)B(A
2+2
)B(A
2+3
)B(A
2
)
.
,
6.42
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
19
Timing Waveform of Combined Read and Write Cycles (1,2,3)
NOTES:
1. Q (A1) represents the first output from the external address A 1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in one cycle before
the actual data is presented to the SRAM.
t
HE
t
SE
R/W
A
1
A
2
CLK
CEN
ADV/LD
ADDRESS
CE
1
,C
E
2(2)
BW
1
-BW
4
DATA
OUT
Q(A
3
)
Q(A
1
)Q(A
6
)Q(A
7
)
t
CD
Read Read
Read Read
t
CHZ
5282 drw 08
Write t
CLZ
D(A
2
)D(A
4
)
t
CDC
D(A
5
)
Write
t
CH
t
CL
t
CYC
t
HW
t
SW
t
HA
t
SA
A
4
A
3
t
HC
t
SC
t
SD
t
HD
t
HADV
t
SADV
A
6
A
7
A
8
A
5
A
9
DATA
IN
t
HB
t
SB
Write
D(A
8
)
Write
B(A2) B(A
4
)B(A
5
)B(A
8
)
OE
.
,
6.4220
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
Timing Waveform of CEN Operation (1,2,3,4)
NOTES:
1. Q (A1) represents the first output from the external address A 1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition did not occur. All
internal registers in the SRAM will retain their previous state.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in one cycle before
the actual data is presented to the SRAM.
t
HE
t
SE
R/W
A
1
A
2
CLK
CEN
ADV/LD
ADDRESS
CE
1
,CE
2(2)
BW
1
-BW
4
OE
DATA
OUT
Q(A
1
)
t
CDC
Q(A
3
)
t
CD
t
CLZ
Q(A
1
)Q(A
4
)
t
CD
t
CDC
t
CHZ
D(A
2
)
t
SD
t
HD
t
CH
t
CL
t
CYC
t
HC
t
SC
A
4
A
5
t
HADV
t
SADV
t
HW
t
SW
t
HA
t
SA
A
3
t
HB
t
SB
DATA
IN
5282 drw 09
B(A
2
)
.
,
6.42
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
21
Timing Waveform of CS Operation (1,2,3,4)
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A3) represents the input data to the SRAM corresponding to address A3 etc.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. When either one of the Chip enables (CE1, CE2, CE2) is sampled inactive at the rising clock edge, a deselect cycle is initiated. The data-bus tri-states one cycle after the initiation of the deselect
cycle. This allows for any pending data transfers (reads or writes) to be completed.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in one cycle before
the actual data is presented to the SRAM.
R/W
A1
CLK
ADV/LD
ADDRESS
CE
1
,CE
2(2)
OE
DATA
OUT
Q(A
1
)Q(A
2
)Q(A
4
)
t
CLZ
Q(A
5
)
t
CD
t
CHZ
t
CDC
D(A
3
)
t
SD
t
HD
t
CH
t
CL
t
CYC
t
HC
t
SC
A
5
A
3
t
SB
DATA
IN
t
HE
t
SE
A
2
t
HA
t
SA
A
4
t
HW
t
SW
t
HB
CEN
t
HADV
t
SADV
5282drw 10
BW
1
-BW
4
B(A
3
)
.
,
6.4222
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
JTAG Interface Specification (SA Version only)
TCK
Device Inputs
(1)
/
TDI/TMS
Device Outputs
(2)
/
TDO
TRST
(
3
)
t
JCD
t
JDC
t
JRST
t
JS
t
JH
t
JCYC
t
JRSR
t
JF
t
JCL
t
JR
t
JCH
M5282 drw 01
x
Symbol
Parameter
Min.
Max.
Units
t
JCYC
JTAG Clock Input Period 100 ____ ns
t
JCH
JTAG Clock HIGH 40 ____ ns
t
JCL
JTAG Clock Low 40 ____ ns
t
JR
JTAG Clock Rise Time ____ 5(1) ns
t
JF
JTAG Clock Fall Time ____ 5(1) ns
t
JRST
JTAG Reset 50 ____ ns
t
JRSR
JTAG Reset Recovery 50 ____ ns
t
JCD
JTAG Data Output ____ 20 ns
t
JDC
J TAG Data Outp ut Ho ld 0 ____ ns
t
JS
JTAG Setup 25 ____ ns
t
JH
JTAG Hold 25 ____ ns
I5282 tbl 01
Register Name
Bit Si ze
Instruc ti on (IR) 4
Byp ass (BYR) 1
J TA G Id e ntifi c atio n (J IDR) 32
Bo undary Scan (BSR) Note (1)
I5282 tbl 03
NOTES:
1. Device inputs = All device inputs except TDI, TMS and TRST.
2. Device outputs = All device outputs except TDO.
3. During power up, TRST could be driven low or not be used since the JTAG circuit resets automatically. TRST is an optional JTAG reset.
NOTE:
1. The Boundary Scan Descriptive Language (BSDL) file for this device is available
by contacting your local IDT sales representative.
JTAG AC Electrical
Characteristics(1,2,3,4)
Scan Register Sizes
NOTES:
1. Guaranteed by design.
2. AC Test Load (Fig. 1) on external output signals.
3. Refer to AC Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at any speed specified in this datasheet.
6.42
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
23
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
Instruction Field
Value
Description
Revision Number (31:28) 0x2 Reserved for version number.
IDT Dev ice ID (27:12) 0x209, 0x20B Defines IDT p art numb er 71V3557SA and 71V3559SA, res pec tive ly.
IDT JEDEC ID (11:1) 0x33 Allows unique identification of device vendor as IDT.
ID Register Indicator Bit (Bit 0) 1 Indicates the presenc e of an ID register.
I5282 tbl 02
JTAG Identification Register Definitions (SA Version only)
Instruction
Description
OPCODE
EXTEST
Forces contents of the bound ary scan cells onto the device
o
utputs
(1)
.
Places the boundary scan register (BSR) between TDI and TDO.
0000
SAMPLE/PRELOAD
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs
(2)
and o utp uts
(1)
to be cap tured
in the b oundary s can ce lls and shifted se rially thro ugh TDO. PRE LOAD
allows data to be input serially into the bo undary scan cells via the TDI.
0001
DEVICE_ID
Lo ad s the J TA G ID re g is te r (J IDR) wi th th e v e ndo r ID c o d e and p lac e s
the register between TDI
and TDO.
0010
HIGHZ
Places the bypass register (BYR) be tween TDI and TDO. Forces all
device outp ut driv e rs to a High-Z state .
0011
RESERVED
S ev eral co mb i natio ns are re se rv e d. Do n o t us e c od e s o the r than thos e
id e ntifie d for E XTES T, SA MP LE/ PRELOA D, DE VICE_ID, HIGHZ, CLA MP,
VALIDATE and BYPASS instructio ns.
0100
RESERVED
0101
RESERVED
0110
RESERVED
0111
CLAMP
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the byp ass registe r (BYR) between TDI and TDO.
1000
RESERVED
Same as ab ove .
1001
RESERVED
1010
RESERVED
1011
RESERVED
1100
VALIDATE
Automatically loaded into the instruction reg iste r wheneve r the TAP
contro ller p asses throug h the CAPTURE-IR state. The lo wer two b its '01'
are mandated b y the IEE E s td . 1149.1 sp e c ific atio n.
1101
RESERVED
Same as ab ove .
1110
BYPASS
The BYPASS instruction is used to truncate the boundary scan register
as a sing le bit in le ngth.
1111
I5282 tbl 04
Available JTAG Instructions
6.4224
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
100-Pin Thin Quad Plastic Flatpack (TQFP) Package Diagram Outline
6.42
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
25
119 Ball Grid Array (BGA) Package Diagram Outline
6.4226
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
165 Fine Pitch Ball Grid Array (fBGA) Package Diagram Outline
6.42
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
27
Timing Waveform of OE Operation (1)
NOTE:
1. A read operation is assumed to be in progress.
Ordering Information
OE
DATA Out
tOHZ tOLZ
tOE
Q
5282 drw 11
Q
,
100-Pin Plastic Thin Quad Flatpack (TQFP)
119 Ball Grid Array (BGA)
165 Fine Pitch Ball Grid Array (fBGA)
Power
XX
Speed
XX
Package
PF**
BG
BQ
IDT XXXX
75*
80
85 Access time (t
CD
) in tenths of nanoseconds
5282 drw 12
Device
Type
IDT71V3557
IDT71V3559 128Kx36 Flow-Through ZBT SRAM with 3.3V I/O
256Kx18 Flow-Through ZBT SRAM with 3.3V I/O
,
X
Process/
Temperature
Range
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Blank
I
*Commercial temperature ran
g
eonly.
** JTAG (SA version) is not available with 100-pin TQFP packa
g
e
XX
S
SA Standard Power
Standard Power with JTAG Interface
X
Restricted Hazardous Substance Device
G
6.4228
IDT71V3557, IDT71V3559, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Flow-Through Outputs Commercial and Industrial Temperature Ranges
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Rd 800-345-7015 or 408-284-8200 sramhelp@idt.com
San Jose, CA 95138 fax: 408-284-2775 800-345-7015 or
www.idt.com 408/284-4555
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
6/30/99 Updated to new format
8/23/99 Pg. 5, 6 Added Pin 64 to Note 1 and changed Pins 38, 42, and 43 to DNU
Pg. 7 Changed U2–U6 to DNU
Pg. 15 Improved tCH, tCL; revised tCLZ
Pg. 21 Added BGA package diagrams
Pg. 23 Added Datasheet Document History
12/31/99 Pg. 5, 14, 15, 22 Added Industrial Temperature range offerings
05/02/00 Pg. 5,6 Insert clarification note to Recommended OperatingTemperature and Absolute Max ratings
tables
Pg. 5,6,7 Clarify note on TQFP and BGA pin configurations; corrected typo in pinout
Pg. 6 Add BGA capacitance table
Pg. 21 Add TQFP Package Diagram Outline
05/26/00 Add new package offering 13 x 15mm 165 fBGA
Pg. 23 Correct 119 BGA Package Diagram Outline
07/26/00 Pg. 5-8 Add ZZ sleep mode reference note to TQFP, BG119 and BQ165
Pg. 8 Update BQ165 pinout
Pg. 23 Update BG119 pinout package diagram dimensions
10/25/00 Remove preliminary status
Pg. 8 Add reference note to pin N5 on BQ165 pinout, reserved for JTAG TRST
05/20/02 Pg. 1-8,15,22,23,27 Added JTAG "SA" version functionality and updated ZZ pin descriptions and notes.
10/15/04 Pg. 7 Updated pin configuration for the 119 BGA - reordered I/O signals on P6, P7 (128K x 36)
and P7, N6, L6, K7, H6, G7, F6, E7, D6 (256K x 18).
12/07/05 Pg. 27 Added "Restricted hazardous substance device" to ordering information.
ZBT and ZeroBus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola Inc.
