Description
Providing improved output current limiting, the UDK,
UDN, and UDQ2559B, EB, and LB quad power drivers
combine AND logic gates and high-current bipolar outputs
with complete output protection. Each of the four outputs
sink 700 mA in the on state. The outputs have a minimum
breakdown voltage (load dump) of 60 V and a sustaining
voltage of 40 V. The inputs are compatible with TTL and
5 V CMOS logic systems.
Overcurrent protection for each channel has been designed
into these devices and is activated at approximately 1 A. It
protects each output from short circuits with supply voltages
up to 25 V. When an output current trip point is reached, that
output stage is driven linearly resulting in a reduced output
current level. If an over-current or short-circuit condition
continues, the thermal-limiting circuits will first sense the rise
in junction temperature and then the rise in chip temperature,
further decreasing the output current. Under worst-case
conditions, these devices will tolerate short circuits on all
outputs, simultaneously.
These devices can be used to drive various loads including
incandescent lamps (without warming or limiting resistors)
or inductive loads such as relays, solenoids, or dc stepping
motors.
The packages offer fused leads for enhanced thermal dissipation.
Package B is a 16-pin power DIP with exposed tabs, EB is a
28-lead power PLCC, and LB is a 16-lead power wide-body
SOIC for surface-mount applications. The lead (Pb) free
versions have 100% matte tin leadframe plating.
29317.14K
Features and Benefits
▪ 700 mA output current per channel
▪ Independent overcurrent protection for each driver
▪ Thermal protection for device and each driver
▪ Low output-saturation voltage
▪ Integral output flyback diodes
▪ TTL and 5 V CMOS-compatible inputs
Protected Quad Power Driver
Packages:
Functional Block Diagram
(1 of 4 Channels)
Not to scale
2559
16-pin DIP
with exposed thermal tabs
(B package)
28-pin PLCC
(Package EB)
16-pin SOICW
with internally fused pins
(LB package)
Thermal
Limit
ENABLE
<< 1Ω
OUTN
VCC
INN
K
Protected Quad Power Driver
2559
2
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Selection Guide
Part Number Pb-free Package Packing Ambient Temperature
(°C)
UDN2559B-T Yes 16-pin DIP, exposed tabs 25 per tube
–20 to 85UDN2559EBTR-T Yes 28-lead PLCC 800 per reel
UDN2559LBTR-T* Yes 16-lead SOIC 1000 per reel
UDQ2559B-T* Yes 16-pin DIP, exposed tabs 25 per tube –40 to 85
UDQ2559LBTR-T Yes 16-lead SOIC 1000 per reel
UDK2559B-T Yes 16-pin DIP, exposed tabs 25 per tube
–40 to 125
UDK2559EBTR* – 28-lead PLCC 800 per reel
UDK2559EBTR-T Yes 28-lead PLCC 800 per reel
UDK2559LBTR* – 16-lead SOIC 1000 per reel
UDK2559LBTR-T Yes 16-lead SOIC 1000 per reel
*Variant is in production but has been determined to be LAST TIME BUY. This classification indicates that the variant is obsolete and notice
has been given. Sale of the variant is currently restricted to existing customer applications. The variant should not be purchased for new
design applications because of obsolescence in the near future. Samples are no longer available. Status date change November 2, 2009.
Deadline for receipt of LAST TIME BUY orders is April 30, 2010.
Absolute Maximum Ratings
Characteristic Symbol Notes Rating Units
Supply Voltage VCC 7V
Input Voltage Range VIN, VEN 7V
Output Voltage VOUT 60 V
Overcurrent-Protected Output Voltage VOUT(P) 25 V
Output Current IOUT
Outputs are peak current limited at approxi-
mately 1.0 A per driver. See Circuit Description
and Application section for further information.
1.0 A
Operating Ambient Temperature TA
Range K –40 to 125 ºC
Range N –20 to 85 ºC
Range Q –40 to 85 ºC
Maximum Junction Temperature TJ(max) 150 ºC
Storage Temperature Tstg –55 to 150 ºC
Protected Quad Power Driver
2559
3
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Package EB
1
2
3
4
12
13
14
15
16
17
18 26
27
28
GROUND
GROUND GROUND
GROUND
Dwg. PP-019-1
K
NO
CONNECTION
ENABLE
SUPPLY
NC
NC
CC
V
OUT
1
OUT
2
OUT
3
OUT
4
IN
4
IN
3
IN
2
IN
1
NO
CONNECTION
K
19
20
21
22
23
24
25
5
6
7
8
9
10
11
Package B
1
2
314
4
5
6
7
89
10
11
12
13
15
16
ENABLE
GROUND
GROUND
OUT
2
K
GROUND
GROUND
OUT
3
OUT
4
K
OUT
1
V
CC
IN
1
Dwg. PP-017-1
IN
4
IN
3
IN
2
Package LB
1
2
314
4
5
6
7
89
10
11
12
13
15
16
ENABLE
GROUND
GROUND
OUT 2
K
GROUND
GROUND
OUT 3
OUT 4
K
OUT 1
VCC
IN 1
Dwg. PP-017-6
IN 4
IN3
IN 2
Pin-out Diagrams
Protected Quad Power Driver
2559
4
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
PD = (VOUT1 x IOUT1 x dc) + … + (VOUTn x IOUTn x dc)
+ (VCC x ICC) = (TJ - TA)/RJA
Copyright © 1995, 2002 Allegro MicroSystems, Inc.
Thermal Characteristics
Characteristic Symbol Test Conditions* Value Units
Package Thermal Resistance RθJA
Package B, 2-layer PCB with 0.5 in.2 exposed copper each side 43 ºC/W
Package EB, 1-layer PCB with copper limited to solder pads 36 ºC/W
Package LB, 1-layer PCB with copper limited to solder pads 90 ºC/W
*Additional thermal information available on the Allegro website
Protected Quad Power Driver
2559
5
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
ELECTRICAL CHARACTERISTICS at TA = +25°C (prefi x ‘UDN’) or over operating
temperature range (prefi x ‘UDK’ or ‘UDQ’), VCC = 4.75 V to 5.25 V
Limits
Characteristic Symbol Test Conditions Min. Typ. Max. Units
Output Leakage Current ICEX V
OUT = 50 V, VIN = 0.8 V, VEN = 2.0 V — <1.0 100 μA
V
OUT = 50 V, VIN = 2.0 V, VEN = 0.8 V — <1.0 100 μA
Output Sustaining Voltage VOUT(SUS) I
OUT = 100 mA, VIN = VEN = 0.8 V 40 — — V
Output Saturation Voltage VOUT(SAT) All Devices, IOUT = 100 mA — — 300 mV
All Devices, IOUT = 400 mA — — 500 mV
B or EB package only, IOUT = 600 mA — — 700 mV
Over-Current Trip ITRIP — 1.0 — A
Input Voltage Logic 1 VIN(1) or VEN(1) 2.0 — — V
Logic 0 VIN(0) or VEN(0) — — 0.8 V
Input Current Logic 1 VIN(1) or VEN(1) = 2.0 V — — 40 μA
Logic 0 VIN(0) or VEN(0) = 0.8 V — — -10 μA
Total Supply Current* ICC All Outputs ON, VIN = VEN = 2.0 V — — 80 mA
All Outputs OFF — — 5.0 mA
Clamp Diode Forward Voltage VF I
F = 1.0 A — — 1.7 V
I
F = 1.5 A — — 2.1 V
Clamp Diode Leakage Current IR V
R = 50 V, D1 + D2 or D3 + D4 — — 50 μA
Turn-On Delay tPHL I
OUT = 500 mA — — 20 μs
t
PLH I
OUT = 500 mA — — 20 μs
Thermal Limit TJ — 165 — °C
Typical Data is for design information only.
Negative current is defi ned as coming out of (sourcing) the specifi ed terminal.
As used here, -100 is defi ned as greater than +10 (absolute magnitude convention) and the minimum is implicitly zero.
* All inputs simultaneously, all other tests are performed with each input tested separately.
Protected Quad Power Driver
2559
6
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
TYPICAL OUTPUT
CHARACTERISTIC CIRCUIT DESCRIPTION AND APPLICATION
INCANDESCENT LAMP DRIVER
High incandescent lamp turn-ON/in-rush currents can contribute to poor
lamp reliability and destroy semiconductor lamp drivers. Warming or current-
limiting resistors protect both driver and lamp but use signifi cant power either
when the lamp is OFF or when the lamp is ON, respectively. Lamps with
steady-state current ratings up to 700 mA can be driven by these devices with-
out the need for warming (parallel) or current-limiting (series) resistors.
When an incandescent lamp is initially turned ON, the cold fi lament is
at minimum resistance and would normally allow a 10x to 12x in-rush cur-
rent. With these drivers, during turn-ON, the high in-rush current is sensed by
the internal low-value sense resistor. Drive current to the output stage is then
diverted by the shunting transistor, and the load current is momentarily limited
to approximately 1.0 A. During this short transition period, the output cur-
rent is reduced to a value dependent on supply voltage and fi lament resistance.
During lamp warmup, the fi lament resistance increases to its maximum value,
the output stage goes into saturation and applies maximum rated voltage to the
lamp.
INDUCTIVE LOAD DRIVER
Bifi lar (unipolar) stepper motors, relays, or solenoids can be driven di-
rectly. The internal fl yback diodes prevent damage to the output transistors by
suppressing the high-voltage spikes that occur when turning OFF an inductive
load.
For rapid current decay (fast turn-OFF speeds), the use of Zener diodes
will raise the fl yback voltage and inprove performance. However, the peak
voltage must not exceed the specifi ed minimum sustaining voltage (VSUPPLY +
VZ + VF VOUT(SUS)).
FAULT CONDITIONS
In the event of a shorted load, the load current will attempt to increase. As
described above, the drive current to the affected output stage is reduced, caus-
ing the output stage to go linear, limiting the peak output current to approxi-
mately 1 A. As the power dissipation of that output stage increases, a thermal
gradient sensing circuit will become operational, further decreasing the drive
current to the affected output stage and reducing the output current to a value
dependent on supply voltage and load resistance.
Continuous or multiple overload conditions causing the chip temperature
to reach approximately 165°C will result in an additional reduction in output
current to maintain a safe level.
If the fault condition is corrected, the output stage will return to its normal
saturated condition.
TYPICAL OUTPUT BEHAVIOR
Protected Quad Power Driver
2559
7
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
EB Package, 28-pin PLCC
with internally fused pins 5 through 11 and 19 through 25
2128
A
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
ATerminal #1 mark area
For Reference Only
(reference JEDEC MS-018 AB)
Dimensions in millimeters
12.45±0.13
12.45±0.13
0.51 MIN
C
SEATING
PLANE
C0.10
28X
11.51±0.08
5.21±0.36
5.21±0.36
0.74±0.08
5.21±0.36
0.43±0.10
5.21±0.36
11.51±0.08
0.51
1.27
4.37 +0.20
–0.18
2
19.05±0.25
5.33 MAX
0.46 ±0.12
1.27 MIN
1
16
A
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
ATerminal #1 mark area
6.35 +0.76
–0.25
3.30 +0.51
–0.38
10.92 +0.38
–0.25
1.52 +0.25
–0.38
0.38 +0.10
–0.05
7.62
2.54
For Reference Only
(reference JEDEC MS-001 BB)
Dimensions in inches, metric dimensions (mm) in brackets, for reference only
B Package, 16-pin DIP
with internally fused pins 4, 5, 12, and 13
and external thermal tabs
Protected Quad Power Driver
2559
8
Allegro MicroSystems, Inc.
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
LB Package, 16-pin SOICW
with internally fused pins 4 and 5, and 12 and 13
9.50
0.65
2.25
1.27
C
SEATING
PLANE
1.27
0.25
0.20 ±0.10
0.41 ±0.10 2.65 MAX
10.30±0.33
7.50±0.10
4° ±4
0.27 +0.07
–0.06
0.84 +0.44
–0.43
10.30±0.20
C0.10
16X
21
16
GAUGE PLANE
SEATING PLANE
For Reference Only
Pins 4 and 5, and 12 and 13 internally fused
Dimensions in millimeters
(reference JEDEC MS-013 AA)
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
ATerminal #1 mark area
A
B
Reference pad layout (reference IPC SOIC127P1030X265-16M)
All pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary
to meet application process requirements and PCB layout tolerances
B
PCB Layout Reference View
21
16
Copyright ©1995-2009, Allegro MicroSystems, Inc.
The products described here are manufactured under one or more U.S. patents or U.S. patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifi cations as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
