LTC4284 High Power Negative Voltage Hot Swap Controller with Energy Monitor DESCRIPTION FEATURES Drives Two Gates for High Power Applications n Configurable Parallel, Staged Start or Single Modes n Protects MOSFET with SOA Timer n Programmable 15mV to 30mV Current Limit Sense Voltage with 2% Accuracy and Adjustable Foldback n 8-Bit to 16-Bit Gear-Shift ADC with 0.5% Accuracy n Monitors Voltages, Currents, Power and Energy n Nonvolatile Configuration and Fault Recording n Floating Topology for Rugged High Voltage Operation n Selectable Inrush Control: dV/dt or Current Limit n I2C/SMBus or Single-Wire Broadcast Interfaces n Min/Max ADC Measurement Logging with Alerts n Reboots on I2C Command with Programmable Delay n Adjustable Input UV/OV Thresholds and Hysteresis n 44-Pin 5mm x 8mm QFN Package The LTC(R)4284 negative voltage hot swap controller drives external N-channel MOSFETs to allow a board to be safely inserted and removed from a live backplane. The dualgate, multi-mode drivers optimize the MOSFET safe operating area (SOA) for a variety of power levels. The SOA timer limits MOSFET temperature rise for reliable protection against overstresses. n An I2C interface and onboard gear-shift ADC allow monitoring of board current, voltage, power, energy, and fault status. An available single-wire broadcast mode simplifies the interface by eliminating two isolators. The included EEPROM provides black-box capturing and nonvolatile configuration of fault behavior. Additional features respond to input UV/OV, interrupt the host when a fault has occurred, notify when output power is good, detect insertion of a board, turn off the MOSFETs if an external supply monitor fails to indicate power good within a timeout period, and auto-reboot after a programmable delay following a host commanded turn-off. APPLICATIONS Telecom Infrastructure -48V Distributed Power Systems n Servers and Data Centers n Power Monitors n n All registered trademarks and trademarks are the property of their respective owners. Protected by U.S. patents, including 8230151, 7382167, 9634480, 9634481, 10263414. TYPICAL APPLICATION -52V/2500W Hot Swap Controller with Telemetry RTN 1F RTN (SHORT PIN) 4 x 1k IN SERIES 0.25W EACH 0.1F VEE + VEE 10.2k 402k UVH UVL 7.68k INTVCC MODE OV TMR RAMP 10k 470nF VZ VIN RTNS SCL SDAI SDAO LTC4284 ADIN ADIO EN VEE SENSE2- SENSE1- SENSE1+ SENSE2+ GATE1 PGIO DRNS GATE2 DRAIN 2.2nF 100k VEE -52V INPUT UV = 43.5V UV RELEASE AT 48.5V OV = 59V OV RELEASE AT 58V Startup Behavior 316k VEE GATE1 10V/DIV VLOAD 2000F 4 4 -52V VOUT 50V/DIV 4 10.2k VEE IINRUSH 1A/DIV - 316k 5m GATE2 10V/DIV VOUT PSMN7R6-100BSE 100ms/DIV 4284 TA01b 0.33m 4284 TA01a 2 x IPT020N10N3 Rev. A Document Feedback For more information www.analog.com 1 LTC4284 TABLE OF CONTENTS Features...................................................... 1 Applications................................................. 1 Typical Application ......................................... 1 Description.................................................. 1 Absolute Maximum Ratings............................... 3 Order Information........................................... 3 Pin Configuration........................................... 3 Electrical Characteristics.................................. 4 I2C Timing Diagram........................................ 9 Typical Performance Characteristics.................... 9 Pin Functions............................................... 12 Block Diagram.............................................. 16 Operation................................................... 17 Applications Information................................. 18 Input Power Supply................................................. 18 Turn-On Sequence...................................................20 Inrush Control..........................................................22 Power Good Monitors and PGI Fault........................23 Turn-Off Sequence................................................... 24 Overcurrent Protection............................................ 24 SOA Timer............................................................... 24 Overcurrent Fault and Auto-Retry............................ 27 Current Limit Adjustment......................................... 27 Current Limit Foldback............................................. 27 FET Bad Fault and Auto-Retry.................................. 28 Input Step and Optimum Output Ramp....................29 Dual-Gate Operation Modes.....................................30 Parallel Mode (Mode 2)...........................................30 High Stress Staged Start Mode (Mode 3)................ 32 Low Stress Staged Start (Mode 4)..........................34 Single Driver Mode (Mode 1)...................................35 Overvoltage Fault and Auto-Retry............................36 Undervoltage Fault and Auto-Retry.......................... 37 FET Short Fault........................................................38 Power Failed Fault....................................................38 External Fault and Auto-Retry..................................38 Cooling Delay...........................................................38 2 Resetting Faults.......................................................39 Alarms.....................................................................39 EN# Pin....................................................................39 ON Bit...................................................................... 39 Turning the LTC4284 On and Off.............................40 Configuring PGIO and ADIO Pins............................. 41 Design Examples..................................................... 41 Example 1: Design Procedure of Parallel Mode with SOA Timer and Current Limit Startup...................... 41 Example 2: Design Procedure of Low Stress Staged Start Mode with Single Capacitor on TMR Pin and dV/dt Startup...........................................................45 Layout Considerations............................................. 49 Reboot on I2C Command......................................... 49 Data Converters....................................................... 49 EEPROM..................................................................53 Fault Log..................................................................54 Digital Interface.......................................................55 Bus Compatibility.....................................................55 START, REPEATED START and STOP Conditions....56 ACK/NACK...............................................................56 I2C Device Addressing.............................................56 Transfer Protocol Types...........................................56 Command Codes and Register Addressing..............58 Write Protocols........................................................58 Read Protocols........................................................58 Read Page and Write Page Protocols......................58 Byte Ordering..........................................................58 ALERT# and Alert Response Protocol......................58 Stuck Bus Reset...................................................... 59 Data Synchronization and Arbitration...................... 59 Single-Wire Broadcast.............................................60 Register Tables........................................................62 Package Description...................................... 80 Revision History........................................... 81 Typical Application........................................ 82 Related Parts............................................... 82 Rev. A For more information www.analog.com LTC4284 ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION (Notes 1 and 2) SCL ADR0 ADR1 MODE WP INTVCC VIN VZ TOP VIEW 44 43 42 41 40 39 38 37 EN# 1 36 SDAI UVL 2 35 SDAO UVH 3 34 ALERT# OV 4 33 VEE VREF 5 32 PGIO4 VOUTTH 6 ADIN1 7 ADIN2 8 ADIN3 9 28 ADIO4 ADIN4 10 27 ADIO3 VEE 11 26 ADIO2 31 PGIO3 30 PGIO2 45 VEE 29 PGIO1 SENSE2- 12 25 ADIO1 ADC- 13 24 TMR SENSE1- 14 23 RAMP RTNS DRNS DRAIN GATE2 GATE1 SENSE2+ ADC+ 15 16 17 18 19 20 21 22 SENSE1+ Supply Voltage: VIN....................................................... -0.3V to 12.5V INTVCC................................................... -0.3V to 5.5V Input Voltages V Z (Note 3)............................................. -0.3V to 16V DRAIN (Note 4)...................................... -0.3V to 3.2V EN# (Note 5)............................................. -0.3V to 6V MODE........................................... -0.3V to VIN + 0.3V UVL, UVH............................................... -0.3V to 16V ADC+ , ADC -, ADIN1-4, ADR0, ADR1, DRNS, OV, RTNS, SCL, SDAI, SENSE1+, SENSE1- , SENSE2+, SENSE2-, VOUTTH, WP..........................-0.3V to INTVCC + 0.3V Output Voltages GATE1, GATE2, PGIO1-4............... -0.3V to VIN + 0.3V VREF...................................................... -0.3V to 4.5V ADIO1-4, RAMP, TMR.............-0.3V to INTVCC + 0.3V ALERT#, SDAO....................................... -0.3V to 5.5V Input Currents: V Z.......................................................................50mA DRAIN................................................................1.5mA EN#.......................................................................5mA Operating Ambient Temperature Range LTC4284C................................................. 0C to 70C LTC4284I..............................................-40C to 85C LTC4284H........................................... -40C to 125C Storage Temperature Range................... -65C to 150C UHG PACKAGE 44-LEAD (5mm x 8mm) PLASTIC QFN TJMAX = 150C, JA = 36C/W EXPOSED PAD (PIN 45) IS VEE, CONNECTION OPTIONAL ORDER INFORMATION TUBE TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC4284CUHG#PBF LTC4284CUHG#TRPBF 4284 44-Lead (5mm x 8mm) Plastic QFN 0C to 70C LTC4284IUHG#PBF LTC4284IUHG#TRPBF 4284 44-Lead (5mm x 8mm) Plastic QFN -40C to 85C LTC4284HUHG#PBF LTC4284HUHG#TRPBF 4284 44-Lead (5mm x 8mm) Plastic QFN -40C to 125C Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix. Rev. A For more information www.analog.com 3 LTC4284 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C, IIN + IVZ = 4mA with VIN Connected to VZ. (Note 2) SYMBOL PARAMETER CONDITIONS VIN Shunt Regulated Voltage at VIN IIN + IVZ = 4mA l VIN Load Regulation at VIN IIN + IVZ = 4mA to 35mA l IIN VIN Supply Current VIN = 10.5V l VIN Rising l l MIN TYP MAX UNITS 10.8 11.5 12 250 500 mV 2.5 4 mA 7.5 8.1 8.6 V 0.4 0.5 0.6 V 20 A Power Supply VIN(UVLO) VIN Undervoltage Lockout Threshold VIN(UVLO) VIN Undervoltage Lockout Hysteresis IVZ VZ Input Current VIN = 10.5V, VZ = 15V l V INTVCC Internal 5V LDO Voltage ILOAD = 1mA to 30mA, IIN + IVZ = 35mA l 4.75 5.05 5.35 V VCC(UVLO) INTVCC Undervoltage Lockout Threshold INTVCC Rising l 3.65 4 4.3 V VCC(UVLO) INTVCC Undervoltage Lockout Hysteresis l 0.12 0.2 0.3 V VGATE Gate Drive Voltage for GATE1,2 l VIN - 0.3 VIN VIN + 0.3 V VGATE(TH) Gate High Threshold for Asserting Power Good l VIN - 2.1 VIN - 1.8 VIN - 1.5 V Gate Drive GATE1,2 Rising VGATE(HYST) Gate High Hysteresis l 0.3 0.7 1.1 V IGATE(UP) GATE1,2 Pull-Up Current VGATE = 4V l -40 -50 -75 A IGATE(DN) GATE1,2 Fast Pull-Down Current VSENSE1,2 = VILIM(FAST) + 10mV, VGATE = 7V l 0.5 1.2 2 A GATE1,2 Current Limit Pull-Down Current VSENSE1,2 = VILIM + 5mV, VGATE = 7V l 12.5 25 50 mA GATE1,2 Turn Off Pull-Down Current TMR, OV, EN# = High, UVL = Low, VGATE = 7V l 4 9 20 mA tPHL(SENSE) VSENSE1,2 High to GATE1,2 Low Propagation Delay ILIM = 0000b, VSENSE1,2 Steps from 0mV to 100mV, VGATE < 3V, GATE1,2 Open l 60 150 ns tPHL(GATE) GATE1,2 Turn Off Propagation Delay TMR, OV, EN# = High, UVL = Low, VGATE < 3V, l GATE1,2 Open 0.5 1 s tDL(DB) Debounce Delay, Auto-Retry Delay Following Undervoltage or PGI Fault l 115 128 141 ms tDL(PG) Power Good Delay l 230 256 282 ms tDL(PGIWD) Power Good Input Watchdog Timer l 461 512 563 ms tDL(RTRY) Auto-Retry Delay Following Overcurrent, FET Bad or External Fault (Table11) 10 % On/Off Timing COOLING_DL = 000b - 111b l tDL(RTCRST) Auto-Retry Counter Reset Delay OC_RETRY, FET_BAD_RETRY = 01b, 10b l 18 s tDL(FETBAD) FET Bad Fault Timer Delay (Table11) FTBD_DL = 00b - 11b l 14.8 16.4 10 % tDL(RBT) Auto-Reboot Delay (Table23) After RBT_EN Bit is Set Via I2C Interface, RBT_DL = 000b - 111b l 10 % IRAMP RAMP Output Current Startup Only, dV/dt Control Enabled l -2.25 -2.5 -2.75 A IRAMP(DN) RAMP Discharge Current VRAMP = 1.2V l 1 4 10 mA dV/dt Control 4 Rev. A For more information www.analog.com LTC4284 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C, IIN + IVZ = 4mA with VIN Connected to VZ. (Note 2) SYMBOL PARAMETER CONDITIONS DRAIN Input Threshold for Power Good DRAIN Falling MIN TYP MAX 2 2.05 2.1 UNITS Drain Monitor VD,PG(TH) l VD,PG(HYST) DRAIN Input Hysteresis for Power Good VD,FET(TH) 20 DRAIN Input Threshold for FET Bad Timer DRAIN Rising, VDTH = 00b - 11b and TMR Pull-Up Current (Table11) VD,FET(HYST) DRAIN Input Hysteresis with VD,FET(TH) DRAIN Input Current IDRAIN mV 10 l V 10 % mV VDRAIN = 200mV l 0 0.1 A VDRAIN = 2 V l 0 1 A Current Limit Voltage DAC Zero-Scale ILIM = 0000b, C-Grade (Note 6) ILIM = 0000b, I-, H-Grade l l 14.7 14.5 15 15 15.3 15.5 mV mV Current Limit Voltage DAC Full-Scale ILIM = 1111b, C-Grade (Note 6) ILIM = 1111b, I-, H-Grade l l 29.4 29 30 30 30.6 31 mV mV Current Limit VILIM Current Limit Voltage DAC INL l 0 50 V VILIM Current Limit Voltage Mismatch between Channel 1 and Channel 2 l 0 350 V aSTARTUP Current Limit Foldback Factor at Startup aNORMAL VILIM(FAST) RTNS = 1.8V, DRNS = 0, 1.8V FB = 01b l 45 50 55 % FB = 10b l 16 20 24 % FB = 11b l 7 10 13 % FB = 01b l 45 50 55 % FB = 10b l 15 20 26 % FB = 11b Current Limit Foldback Factor in Normal Operation RTNS = DRNS = 1.8V l 6 10 16 % Fast Pull-Down Sense Threshold Voltage ILIM = 0000b l 20 30 40 mV ILIM = 1111b l 47 60 70 mV ISENSE + SENSE1,2+ Input Current SENSE1,2+ = 33mV l 0 1 A ISENSE- SENSE1,2- Input Current SENSE1,2- = SENSE1,2+ = 0 l -4 -10.5 -15 A Onset DRNS = 0V, TMR = 1V l -1.5 -2 -2.5 A dV/dt Control Disabled, DRNS = 1.8V, TMR = 1V TMR Pin Function ITMR(UP) TMR Pull-Up Current in Current Limit Startup in Foldback FB = 00b l -192 -202 -212 A FB = 01b l -96 -102 -108 A FB = 10b l -39 -42 -45 A FB = 11b l -20 -22 -24 A Startup in dV/dt dV/dt Control Enabled, DRNS = 1.8V, TMR = 1V l -192 -202 -212 A Hard Short in Normal Operation DRNS = 1.8V, TMR = 1V l -192 -202 -212 A ITMR(DN) TMR Pull-Down Current DRAIN < VD,FET(TH) or Start into dV/dt Control, THERM_TMR = 0, TMR = 1V l 1.6 2 2.3 A ITMR(RST) TMR Reset Current EN# = High, TMR = 1V l 3 5 8 mA TMR Rising l 2.028 2.048 2.068 VTMRH(TH) TMR Fault Threshold VTMRH(HYST) TMR Fault Hysteresis VTMRL(TH) TMR Low Status Threshold VTMRL(HYST) TMR Low Hysteresis 20 TMR Falling l 80 100 20 V mV 120 mV mV Rev. A For more information www.analog.com 5 LTC4284 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C, IIN + IVZ = 4mA with VIN Connected to VZ. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX MODE Input Thresholds Threshold 1 UNITS l 0.4 0.7 1 V Threshold 2 l INTVCC - 0.85 INTVCC - 0.55 INTVCC - 0.25 V Threshold 3 l INTVCC + 0.5 INTVCC + 1.5 INTVCC + 2.5 V Input Pins VMODE(TH) IMODE(IN) Allowable Leakage in Open State Mode 1 l 10 A VUVH(TH) UVH Input Threshold UVH Rising l 2.028 2.048 2.068 V VUVL(TH) UVL Input Threshold UVL Falling l 1.815 1.833 1.851 V VUV(HYST) Built-In UV Hysteresis UVH and UVL Tied Together l 204 215 226 dVUV(HYST) UVH, UVL Minimum Hysteresis VUVLR(TH) UVL Reset Threshold 11 UVL Falling l 1 VUVLR(HYST) UVL Reset Hysteresis VOV(TH) OV Input Threshold VOV(HYST) OV Input Hysteresis VOUTL(TH) VOUT Low Threshold VOUTL(HYST) VOUT Low Hysteresis EN# Input Threshold VEN#(TH) VEN#(HYST) EN# Input Hysteresis VWP(TH) WP Input Threshold VWP(HYST) WP Input Hysteresis VINPUT(TH) ADIO1-4, PGIO1-4 Input Threshold 1.024 mV 1.05 21 OV Rising l RTNS - DRNS Falling, VOUTTH = 0.8V 1.392 1.406 1.42 10 24 38 l VOUTTH - 0.06 VOUTTH VOUTTH + 0.06 40 l 1.248 1.28 WP Rising l 1.2 1.65 ADIO1-4, PGIO1-4 Rising l 1.312 1.28 mV V V mV 2.1 100 1.248 V mV 18 VINPUT(HYST) ADIO1-4, PGIO1-4 Input Hysteresis V mV l EN# Falling mV V mV 1.312 18 V mV DRNS, EN#, OV, RTNS, UVL, UVH, VOUTTH, WP Input Current DRNS, EN#, OV, RTNS, UVL, UVH, VOUTTH, WP = 3V l 0 1 A VOL ADIO1-4, PGIO1-4 Output Low Voltage I = 5mA l 0.15 0.4 V ILEAK ADIO1-4, PGIO1-4 Leakage Current ADIO1-4 = INTVCC, PGIO1-4 = VIN l 0 1 A VREF VREF Output Voltage IVREF = -200A, 0, 400A l 1.01 1.024 1.038 V rREF VREF to ADC VFS Ratio IVREF = -200A, 0, 400A l 0.495 0.5 0.505 Resolution (No Missing Codes) (Note 6) RTNS, ADIN1-4, ADIO1-4, DRNS, DRAIN, (ADC+ - ADC-), Power IINPUT Output Pins ADC (SENSE1,2+ - SENSE1,2-), (ADIN2 - ADIN1), (ADIN4 - ADIN3), (ADIO2 - ADIO1), (ADIO4 - ADIO3) 6 ADC = 000b l 8 Bits ADC = 010b l 10 Bits ADC = 100b l 12 Bits ADC = 110b l 14 Bits ADC = xx1b l 14 16 Bits ADC = 000b l 7 Bits ADC = 010b l 9 Bits ADC = 100b l 11 Bits ADC = 110b l 13 Bits ADC = xx1b l 13 15 Bits Rev. A For more information www.analog.com LTC4284 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C, IIN + IVZ = 4mA with VIN Connected to VZ. (Note 2) SYMBOL PARAMETER CONDITIONS VFS Full-Scale Voltage Single-Ended Inputs 2.048 V Differential Inputs 32.768 mV ADC = 000b 8 mV ADC = 010b 2 mV ADC = 100b 0.5 mV ADC = 110b 0.125 mV ADC = xx1b 0.03125 mV ADC = 000b 128 V ADC = 010b 32 V ADC = 100b 8 V ADC = 110b 2 V ADC = xx1b 0.5 V ADC = 000b 256 V ADC = 010b 64 V ADC = 100b 16 V ADC = 110b 4 V ADC = xx1b 1 V LSB LSB Step Voltage RTNS, ADIN1-4, ADIO1-4, DRNS, DRAIN ADC+ - ADC- SENSE1,2+ - SENSE1,2-, ADIN2 - ADIN1, ADIN4 - ADIN3, ADIO2 - ADIO1, ADIO4 - ADIO3 VOS INL Offset Error (Note 7) Integral Nonlinearity (Note 7) MIN Full-Scale Error (Note 7) MAX UNITS Single-Ended Inputs l 0 0.125 % VFS Differential Inputs l 0 0.25 % VFS ADIN1-4, ADIO1-4, RTNS, DRNS, DRAIN, ADC+ - ADC- l 0.01 0.06 % VFS l 0.02 0.12 % VFS SENSE1,2+ - SENSE1,2-, ADIN2 - ADIN1, ADIN4 - ADIN3, ADIO2 - ADIO1, ADIO4 - ADIO3 FSE TYP Single-Ended Inputs, C-Grade (Note 6) Single-Ended Inputs, I-, H-Grade l l 0.5 0.7 % % Differential Inputs, C-Grade (Note 6) Differential Inputs, I-, H-Grade l l 1 1.2 % % Power, C-Grade (Note 6) Power, I-, H-Grade l l 1 1.2 % % Energy l 5 % l 5 % fCONV Refresh Rate in Continuous Mode (Table12) IADC+ ADC+ Input Current ADC+ = 33mV l 0 1 A IADC- ADC+ Input Current ADC- = ADC+ = 0 l -3 -7 A RADIN(SE) ADIN1-4, ADIO1-4 Input Impedance, Single-Ended V = 3V l IADIN(SE) ADIN1-4, ADIO1-4 Input Current, Single-Ended V = 3V l 0 1 A IADIN(DIFF) ADIN1, ADIN3, ADIO1, ADIO3 Input Current, Differential Mode ADIN1, ADIN3, ADIO1, ADIO3 = 0, ADIN2, ADIN4, ADIO2, ADIO4 = 0 l -3 -7 A ADIN2, ADIN4, ADIO2, ADIO4 Input Current, Differential Mode ADIN2, ADIN4, ADIO2, ADIO4 = 33mV l 0 1 A 3 M Rev. A For more information www.analog.com 7 LTC4284 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C, IIN + IVZ = 4mA with VIN Connected to VZ. (Note 2) SYMBOL PARAMETER CONDITIONS MIN TYP MAX INTVCC - 0.25 UNITS I2C Interface VADR(H) ADR0, ADR1 Input High Threshold l INTVCC - 0.85 INTVCC - 0.55 0.4 0.7 VADR(L) ADR0, ADR1 Input Low Threshold l IADR(IN) Allowable Leakage Current l V 1 V 10 A VALERT#(OL) ALERT# Output Low Voltage I = 5mA l 0.15 0.4 V VSDAO(OL) SDAO Output Low Voltage I = 20mA l 0.25 0.6 V ISDAO,ALERT# SDAO, ALERT# Input Current SDAO, ALERT# = INTVCC l VSDAI,SCL(TH) SDAI, SCL Input Threshold ISDAI,SCL SDAI, SCL Input Current l SDAI, SCL = INTVCC 1.5 l 0 1 A 1.75 2 V 0 1 A 0.65 1.3 s I2C Interface Timing (Note 7) fSCL(MAX) Maximum SCL Clock Frequency tLOW Minimum SCL Low Period tHIGH Minimum SCL High Period 50 600 ns tBUF(MIN) Minimum Bus Free Time Between Stop/ Start Condition 0.12 1.3 s tHD,STA(MIN) Minimum Hold Time After (Repeated) Start Condition 140 600 ns tSU,STA(MIN) Minimum Repeated Start Condition Set-Up Time 30 600 ns tSU,STO(MIN) Minimum Stop Condition Set-Up Time 30 600 ns tHD,DATI(MIN) Minimum Data Hold Time Input 400 tHD,DATO(MIN) Minimum Data Hold Time Output tSU,DAT(MIN) Minimum Data Set-Up Time Input tSP(MAX) Maximum Suppressed Spike Pulse Width tRST Stuck-Bus Reset Time SCL or SDAO Held Low CX SCL, SDA Input Capacitance SDAI Tied to SDAO kHz -100 0 ns 300 600 900 ns 30 100 ns 50 110 250 ns 26 30 34 ms 5 10 pF 10 % Single-Wire Broadcast Timing fBC Broadcast Data Rate (Table11) l EEPROM tWRITE Endurance 1 Cycle = 1 Write (Notes 8, 9) l 10,000 Cycles Data Retention (Notes 8, 9) l 20 Years l 1.2 EEPROM Write Time per Byte Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: All Currents into device pins are positive and all currents out of device pins are negative. All voltages are referenced to VEE unless otherwise specified. Note 3: When VZ is connected to VIN, an internal shunt regulator limits the voltage to a minimum of 11V. Driving the pins above 11V may damage the part. These pins can be safely biased by a higher voltage using a resistor or current source that limits the current below 50mA. Note 4: An internal clamp limits DRAIN to a minimum of 3.2V. Driving this pin to voltages above the clamp may damage the part. The pin can 8 2.2 3 ms be safely tied to higher voltages through a resistor that limits the current below 1.5mA. Note 5: An internal clamp limits EN# to a minimum of 6V. Driving this pin to voltages above the clamp may damage the part. The pin can be safely tied to higher voltages through a resistor that limits the current below 5mA. Note 6: Guaranteed by design and characterization. Not tested in production. Note 7: Tested at 12-bit resolution and guaranteed for other resolutions by design and characterization. Note 8: EEPROM endurance and retention are guaranteed by design, characterization and correlation with statistical process controls. Note 9: EEPROM endurance and retention will be degraded when TJ > 85C. Rev. A For more information www.analog.com LTC4284 I2C TIMING DIAGRAM SDA tSU,DAT tSU,STA tHD,DATO tHD,DATI tSP tHD,STA tBUF tSU,STO tSP 4284 TD SCL tHD,STA REPEATED START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION TYPICAL PERFORMANCE CHARACTERISTICS 5 11.4 11.2 3 2 0 5 10 15 20 25 30 VIN INPUT CURRENT (mA) GATE PULL-DOWN CURRENT (A) VGATE (V) 8 6 4 2 -20 -30 -40 IGATE (A) -50 5.02 5.00 0 25 50 75 TEMPERATURE (C) 100 4.96 125 -60 -70 0 5 10 15 20 LOAD CURRENT (mA) 25 GATE Turn-Off Time vs SENSE Input Voltage 1k VGATE = 7V VILIM = 15mV 1 FAST PULL-DOWN 0.1 0.01 0.001 CURRENT LIMIT 0 20 40 60 80 SENSE INPUT VOLTAGE (mV) 4284 G04 30 4284 G03 GATE Pull-Down Current vs SENSE Input Voltage 10 -10 5.04 4284 G02 12 0 -25 4284 G01 10 IIN = 35mA 4.98 0 -50 35 INTVCC Voltage vs Load Current 5.06 1 GATE Output High Voltage vs Leakage Current 0 VZ = 15V VIN = 10.5V INTVCC VOLTAGE (V) 11.6 11.0 5.08 4 VZ INPUT CURRENT (A) VIN VOLTAGE (V) 11.8 VZ Input Current vs Temperature GATE TURN-OFF TIME (s) 12.0 Shunt Regulator Voltage vs Input Current 100 4284 G05 GATE FALLING FROM 11.5V TO 3V VILIM = 15mV 100 FAST PULL-DOWN 10 CGATE = 100nF 1 GATE OPEN 0.1 0.01 0 20 40 60 80 SENSE INPUT VOLTAGE (mV) 100 4284 G06 Rev. A For more information www.analog.com 9 LTC4284 TYPICAL PERFORMANCE CHARACTERISTICS GATE Fast Pull-Down Current vs GATE Voltage 2 1.2 50 UNITS VILIM1 AND VILIM2 1 0.8 0.4 0 -1 0 2 4 6 8 GATE VOLTAGE (V) 10 -2 12 0 2 4 6 8 10 ILIM CODE 12 14 4284 G07 250 CURRENT LIMIT 200 100 0 0 0.6 1.2 1.8 VDRNS (V) 2.4 100 50 2 4 6 8 10 VSENSE1 (mV) 12 14 5 10 15 LOAD CURRENT (mA) 20 1.024 1.022 -400 1.5 1.8 4284 G09 TA = -40C TA = 25C TA = 85C TA = 125C 0.20 0 5 10 15 LOAD CURRENT (mA) 20 4284 G12 0.3 -200 0 200 400 LOAD CURRENT (A) 4284 G13 10 0.6 0.9 1.2 VRTNS - VDRNS (V) ADC Full-Scale Error vs Temperature 1.023 0 0.3 4284 G11 1.025 0.20 0 0.40 0 16 1.026 0.40 POWER GOOD LATCHED VILIM = 15mV VRTNS = 1.8V 11 0.60 VREF Output Voltage vs Load Current VREF VOLTAGE (V) PGIO OUTPUT LOW VOLTAGE (V) 0 4284 G10 0.60 0 VDRNS = 1.8V VDRNS = 1.2V VDRNS = 0.6V VDRNS = 0V 150 0 3 TA = -40C TA = 25C TA = 85C TA = 125C 0.80 5 0.80 VILIM = 15mV CURRENT LIMIT VDRAIN > VD,FET(TH) POWER GOOD LATCHED 200 PGIO Output Low Voltage vs Load Current 1.00 10 ADIO Output Low Voltage vs Load Current ADC FULL-SCALE ERROR (%) 300 10 TMR Pull-Up Current vs SENSE Input Voltage TMR PULL-UP CURRENT (A) TMR PULL-UP CURRENT (A) VSENSE1 = 100% VILIM VSENSE1 = 98% VILIM VSENSE1 = 50% VILIM VSENSE1 = 20% VILIM VSENSE1 = 10% VILIM LPFB = 1 01 4284 G08 TMR Pull-Up Current vs DRNS Voltage 400 LPFB = 0 FB = 00 15 0 16 ADIO OUTPUT LOW VOLTAGE (V) 0 Current Limit Foldback Profiles 20 CURRENT LIMIT VOLTAGE (mV) SENSE INPUT = 40mV VILIM(FAST) = 30mV VILIM ERROR (%) GATE FAST PULL-DOWN CURRENT (A) 1.6 Current Limit Voltage Error vs ILIM Code 600 4284 G14 0.2 0.1 0 -0.1 -0.2 -50 -25 0 25 50 75 TEMPERATURE (C) 100 125 4284 G15 Rev. A For more information www.analog.com LTC4284 TYPICAL PERFORMANCE CHARACTERISTICS Voltage ADC Total Unadjusted Error (TUE) vs Code 0.10 Current ADC Total Unadjusted Error (TUE) vs Code 0.10 INPUT = VRTNS RESOLUTION = 12-BIT INPUT = VADC+ - VADC- RESOLUTION = 12-BIT 0.6 0.4 INL (LSB) 0 0 -0.05 -0.05 -0.10 -0.10 INPUT = VRTNS 0.8 0.05 TUE (%) TUE (%) 0.05 12-Bit Voltage ADC INL vs Code 1.0 0.2 0.0 -0.2 -0.4 -0.6 -0.8 0 1024 2048 CODE 3072 4096 0 1024 2048 CODE 3072 4284 G16 0.4 0.2 0.2 0.2 DNL (LSB) 0.6 0.4 INL (LSB) DNL (LSB) 0.6 0.4 0.0 -0.2 -0.4 -0.6 -0.6 -0.6 -0.8 -0.8 -0.8 -1.0 -1.0 2048 CODE 3072 4096 0 1024 2048 CODE 3072 4096 4284 G19 8000 VRTNS = 1.024V 1LSB = 31.25V 4000 3000 2000 0 VADC+ - VADC- = 16.4mV 1LSB = 500nV -3 -2 -1 0 1 CODE VARIATION (LSB) 2 3 2048 CODE 3072 4000 2000 0 4096 INPUT = VRTNS -10 6000 -20 -30 -40 1000 0 1024 12-Bit ADC Input Signal Attenuation (Low Frequencies) REJECTION (dB) 5000 0 4284 G21 16-Bit Current ADC Noise Histogram NUMBER OF READINGS 6000 -1.0 4284 G20 16-Bit Voltage ADC Noise Histogram NUMBER OF READINGS 0.0 -0.4 1024 4096 -0.2 -0.4 0 3072 INPUT = VADC+ - VADC- 0.8 0.6 0.0 2048 CODE 12-Bit Current ADC DNL vs Code 1.0 INPUT = VADC+ - VADC- 0.8 -0.2 1024 4284 G18 12-Bit Current ADC INL vs Code 1.0 INPUT = VRTNS 0.8 0 4284 G17 12-Bit Voltage ADC DNL vs Code 1.0 -1.0 4096 -3 -2 -1 0 1 CODE VARIATION (LSB) 2 4284 G22 3 4284 G23 -50 0 25 50 75 100 FREQUENCY (Hz) 125 150 4284 G24 Rev. A For more information www.analog.com 11 LTC4284 TYPICAL PERFORMANCE CHARACTERISTICS 12-Bit ADC Input Signal Attenuation (Extended Frequencies) ADC FSE Shift Due to IR Reflow 100 INPUT = VRTNS 80 NUMBER OF UNITS REJECTION (dB) -20 -40 REJECTION LIMITED BY QUANTIZATION NOISE -60 -80 VILIM Shift Due to IR Reflow 100 300 UNITS 260C 3 CYCLES INPUT = VADIN1 60 40 20 0 50 100 150 FREQUENCY (kHz) 200 300 UNITS 260C 3 CYCLES 80 NUMBER OF UNITS 0 60 40 20 0 -0.3 -0.2 -0.1 0.0 0.1 0.2 FSE SHIFT (%) 0.3 0.4 4284 G25 0.5 4284 G26 0 -1.2 -0.8 -0.4 0.0 0.4 VILIM SHIFT (%) 0.8 1.2 4284 G27 PIN FUNCTIONS ADC+ (Pin 16): Positive Current Sense Kelvin Input to ADC. Connect to the tap of an external resistive divider between SENSE1+ and SENSE2+ to measure the average between those two pins. Connect to SENSE1+ when using a single sense resistor. Connect to VEE if unused. ADC- (Pin 13): Negative Current Sense Kelvin Input to ADC. Connect to the tap of an external resistive divider between SENSE1- and SENSE2- to measure the average between those two pins. Connect to SENSE1- when using a single sense resistor. Connect to VEE if unused. ADIN1-ADIN4 (Pins 7-10): ADC Inputs. A single-ended voltage between 0V and 2.048V applied to each ADIN is measured by the on-chip ADC. Two differential voltages ADIN2 - ADIN1 and ADIN4 - ADIN3, if enabled, are also measured by the ADC with a full scale of 32.768mV. Connect to VEE if unused. ADIO1-ADIO4 (Pins 25-28): General Purpose Inputs/ Outputs and ADC Inputs. Configurable to logic inputs and general purpose outputs (open-drain). See Table13 for details. The single-ended voltages at ADIOs are measured by the ADC with a full scale of 2.048V. The differential voltages ADIO2 - ADIO1 and ADIO4 - ADIO3, if 12 enabled, are also measured by the ADC with a full scale of 32.768mV. Connect to VEE if unused. ADR0, ADR1 (Pin 38, Pin 39): Serial Bus Address Inputs. Connecting to VEE, OPEN or INTVCC configures one of nine possible addresses, with one dedicated to the single-wire broadcast mode. Do not bias with an external supply. See Table2 in Applications Information for address decoding. ALERT# (Pin 34): Fault Alert Output. Open-drain logic output that pulls to VEE when a fault occurs to alert the host controller. A fault alert is enabled by the FAULT_ ALERT and ADC_ALERT registers. See Tables 15 and 16 in Applications Information for details. Connect to VEE if unused. DRAIN (Pin 20): Drain Sense Input. Connect an external 100k resistor between this pin and the drain terminal of the N-channel MOSFET. A DRAIN voltage below 2.048V is one of the conditions to assert power good outputs and turn on GATE2 in the high stress staged start (Mode 3) or low stress staged start mode (Mode 4). When DRAIN voltage is above a voltage configurable between 72mV and 203mV, the FET Bad fault timer is started and the TMR output current is enabled when not in current limit. DRAIN is internally clamped to a minimum of 3.2V. Rev. A For more information www.analog.com LTC4284 PIN FUNCTIONS DRNS (Pin 21): Attenuated Drain Sense Input. Connect to the tap of an external resistive divider between the drain terminal of the N-channel MOSFET and VEE to monitor the drain voltage. DRNS coupled with RTNS monitors the output voltage for the load, which controls dV/dt inrush current and current limit foldback. DRNS operates from 0 to 2.8V. Connect to VEE if unused. EN# (Pin 1): Device Enable Input. Pull low to enable the GATE outputs to turn-on after a startup debounce delay. When pulled high, both GATE1 and GATE2 are turned off. A high-to-low transition clears faults. Transitions are recorded. Requires external pull-up. Debouncing with an external capacitor is recommended when used to monitor board present. Connect to VEE if unused. Exposed Pad (Pin 45): Exposed Pad may be left open or connected to device ground (VEE). GATE1, GATE2 (Pin 18, Pin 19): N-Channel MOSFET Gate Drive Outputs. The GATEs can be configured into single driver, parallel, high stress staged start, and low stress staged start modes. See Table1 in Application Information for details. The GATEs are pulled high by internal current sources (>40A) when VIN and INTVCC cross the UVLO thresholds, UV and OV conditions are satisfied, no other faults are present and the debounce delay expires. The GATE1 and GATE2 voltages higher than VIN - 1.8V satisfy one of the conditions to assert power good outputs. Upon a low impedance output short, a 1.2A fast pull-down current is immediately activated. INTVCC (Pin 42): 5V Internal Supply Output. The output of the internal linear regulator sources up to 30mA with an UVLO threshold of 4V. The supply powers the data converters, logic control circuitry, I2C interface and EEPROM. Bypass with 1F capacitor to VEE. INTVCC is not current limited. When driving INTVCC with an external supply, VIN and VZ must be left open or connected to INTVCC. MODE (Pin 40): GATE Drive Mode Configuration Input. Its voltage decodes four operation modes of GATE1 and GATE2. Leaving MODE open enables the single driver mode (Mode 1): GATE1 and GATE2 drive a single channel of MOSFETs. Connecting MODE to VEE enables the parallel mode (Mode 2): GATE1 and GATE2 drive two parallel channels of MOSFETs that turn on simultaneously to share the load current and turn off simultaneously upon overload. Connecting MODE to VIN enables the high stress staged start mode (Mode 3): GATE1 drives a high SOA MOSFET that turns on first for startup and withstands the stress under overload conditions, while GATE2 drives a low RDS(ON) MOSFET as a bypass switch that turns on after GATE1 is fully enhanced and turns off whenever overload occurs. Connecting MODE to INTVCC enables the low stress staged start mode (Mode 4): the turn-on behavior of GATE1 and GATE2 is the same as Mode 3, but GATE1 drives a low SOA trickle MOSFET and the low RDS(ON) bypass MOSFET driven by GATE2 stays on under overload to share the stress. See Applications Information for more details. OV (Pin 4): Overvoltage Detection Input. Connect to an external resistive divider from VEE. When OV is above its threshold of 1.406V, the GATE outputs pull low to turn off the MOSFETs and an overvoltage fault is recorded. The overvoltage fault does not affect the status of the power good outputs. Connect to VEE if unused. PGIO1, PGIO2 (Pin 29, Pin 30): General Purpose Inputs/Outputs. Configurable to sequenced, inverted and non-inverted power good outputs, general purpose logic inputs and open-drain outputs. See Table 12 in Application Information for details. If the PGIO2_ACLB bit in CONTROL_1 register 0x0A is set, PGIO2 is configured as inverted current limit engagement indicator after startup. Connect to VEE if unused. PGIO3 (Pin 31): General Purpose Input/Output. Configurable to inverted and non-inverted power good watchdog input (PGI# and PGI), general purpose logic input and open-drain output. See Table12 in Application Information for details. Connect to VEE if unused. PGIO4 (Pin 32): General Purpose Input/Output. Configurable to inverted and non-inverted external fault input (EXT_ FAULTIN# and EXT_FAULTIN), general purpose logic input and open-drain output. See Table12 in Application Information for details. Connect to INTVCC if unused. Rev. A For more information www.analog.com 13 LTC4284 PIN FUNCTIONS RAMP (Pin 23): Ramp Control. Connect a capacitor between RAMP and VEE to set inrush current in dV/dt startup mode. During the dV/dt control, RAMP acts as an attenuated output and feeds a fixed 2.5A current through the RAMP capacitor to set the slew rate of the output voltage. The dV/dt inrush control is disabled after startup when power good signals are asserted. Leave open ifunused. RTNS (Pin 22): RTN Sense Input. Connect to the tap of an external resistive divider between RTN and VEE to monitor the board input voltage. When selected, the RTNS voltage is measured by the ADC and used to calculate the input power. Monitors the output voltage for the load when coupled with DRNS, which controls dV/dt inrush current and current limit foldback. Operates from 0V to 2.8V. Connect to INTVCC if unused. SCL (Pin 37): Serial Bus Clock Input. Data at SDAI is shifted in and data at SDAO is shifted out on rising edges of SCL. This is a high impedance input that is generally connected to the output of the incoming isolator driven by the SCL port of the master controller. An external pull-up resistor or current source is required. Pull up to INTVCC if unused. SDAI (Pin 36): Serial Bus Data Input. This is a high impedance input used for shifting in command bits, data bits, and SDAO acknowledge bits. An external pull-up resistor or current source is required. Normally connected to the output of the incoming isolator that is driven by the SDA port of the master controller. Pull up to INTVCC if unused. SDAO (Pin 35): Serial Bus Data Output. Open-drain output used for sending data back to the master controller or acknowledging a write operation. An external pull-up resistor or current source is required. Normally connected to the input of the outgoing isolator that outputs to the SDA port of the master controller. In the single-wire broadcast mode, SDAO sends out selected data that is Manchester encoded with an internal clock. The broadcast bit rate is configurable between 2Mbit/s and 32kbit/s. 14 SENSE1+, SENSE2+ (Pin 15, Pin 17): Positive Current Sense Kelvin Inputs. Connect to the high side of the current sense resistors. The active current limit amplifiers control GATE1 and GATE2 independently to limit the sense voltages SENSE1+ - SENSE1- and SENSE2+ - SENSE2- from 15mV to 30mV, configurable in 1mV steps. When enabled, SENSE1+ - SENSE1- and SENSE2+ - SENSE2- are also measured by the ADC with a full scale of 32.768mV. Connect together when using a single sense resistor. Connect SENSE2+ to VEE in the high stress staged start mode (Mode 3). Connect both to VEE if unused. SENSE1-, SENSE2- (Pin 14, Pin 12): Negative Current Sense Kelvin Inputs. Connect to the low side of the current sense resistors. TMR (Pin 24): Timer Current Output. The current sourced out of TMR is proportional to the power dissipation in the MOSFET driven by GATE1. If an RC network that represents the thermal behavior of the MOSFET is connected between TMR and VEE, the voltage at TMR represents the real-time temperature rise of the MOSFET. When the TMR voltage reaches its threshold of 2.048V that corresponds to TJ(MAX) of the MOSFET, both GATE1 and GATE2 pull low to turn off the MOSFETs and an overcurrent fault is logged. If a single capacitor is connected between TMR and VEE, TMR sets the delay for MOSFET turn-off based on the power dissipation in the MOSFET. In this mode the 2A pull-down current must be enabled to discharge the capacitor when the MOSFET power drops to near zero. When EN# is low, TMR is discharged by a 5mA current. Connect to VEE if unused. UVH (Pin 3): Undervoltage High Level Input. Connect to an external resistive divider from VEE. If UVH rises above 2.048V and UVL is above 1.833V, the GATE outputs pull high to turn on the MOSFETs. A capacitor of at least 10nF between UVH and VEE prevents transients and switching noise from affecting the UV threshold. Connect to INTVCC if unused. Rev. A For more information www.analog.com LTC4284 PIN FUNCTIONS UVL (Pin 2): Undervoltage Low Level Input. Connect to an external resistive divider from VEE. If UVL drops below 1.833V and UVH is below 2.048V, the MOSFETs are turned off. Pulling below 1.024V resets faults and allows the MOSFET to turn back on when undervoltage is cleared. Connect to INTVCC if unused. VOUTTH (Pin 6): Output Low Threshold Input. Connect to an external reference voltage for output voltage low threshold. RTNS - DRNS below VOUTTH sets the VOUT low status bit. RTNS - DRNS above VOUTTH satisfies one of the conditions to assert power good outputs. Connect to VEE if unused. VEE (Pin 11 and Pin 33): Negative Supply Voltage Input and Device Ground. Connect to the negative side of the power supply. The connection between any component and device ground must be made to a dedicated plane that connects directly to VEE, not to the main current-carrying trace of -48V on the board. VREF (Pin 5): Reference Voltage Output. Regulated at 1.024V or half of the ADC full-scale. Sources up to 200A and sinks up to 400A. It can drive a capacitive load of up to 10nF. Leave open if unused. VIN (Pin 43): Positive Supply Input to the Device. Connect to VZ directly or through an external buffer transistor driven by VZ. The voltage at VIN is internally regulated at 11.5V. An undervoltage lockout (UVLO) circuit holds the GATE1 and GATE2 outputs low until VIN is above 8.1V. Bypass with at least 0.1F capacitor to VEE. If it is desired to log fault information into EEPROM upon brown-out, bypass VIN with at least 68F capacitor to VEE (See Applications Information for details). VZ (Pin 44): Shunt Regulator Input. Operates with a bias of 20A to 30mA. Connect to the positive supply (RTN) through a dropping resistor. To supply external loads with VIN, use VZ to drive an external buffer transistor with the emitter or source connected to VIN. Bypass with a 0.1F capacitor to VEE. WP (Pin 41): EEPROM Write Protect Input. All write operations to the EEPROM except fault logging are blocked when the voltage at WP is above 1.65V. Rev. A For more information www.analog.com 15 LTC4284 BLOCK DIAGRAM VZ VIN INTVCC MODE WP 4x 1.65V 11.5V - PGIC PGIO1 + - 1.28V PGIO2 WP VCC + UVLO: VIN = 8.1V INTVCC = 4V + DECODER - PGIO3 VEE PGIO4 5V VEE INTVCC 4 VREF 1.024V 1.28V EN# 1.833V UVL UVH 2.048V OV 1.406V VOUTTH VRTNS - VDRNS VSENSE1 x VDRNS 4 TMRH + - EN + - UVL + - UVH + - OV + - VOUTL TMRL DC2 CONTROL LOGIC DC1 GC 4x 4 + - + - + - + - TMR 2.048V 0.1V 2A VEE 72mV TO 203mV DRAIN 2.048V GATE1/GATE2 3.2V VEE VIN - 1.8V ADIO1 + - ADIC 4 + - 1.28V ADIO2 ADIO3 VEE ADIN1 ADIO4 ADIN2 ADIN3 ADIN4 MUX/ PREAMP SENSE2- SENSE2+ MIN/ MAX LOG VPWR (RTNS/DRNS) SENSE1- ADC2 SENSE1+ ADC+ + - ADC- 62.5x ACC1 ACC2 - + - - ACL2 FST2 48 ALERT# 32 VEE TIME EEPROM FOLDBACK dV/dt CONTROL VIN + - - + - - 50A GATE1 SDAO ENERGY 30mV TO 60mV + - VIN REGISTERS + FST1 + + + ACL1 15mV TO 30mV SCL SDAI 16 ADC1 30mV TO 60mV I2C INTERFACE POWER OSC 15mV TO 30mV ADR1 16 16 MULTIPLIER DRNS ADR0 16 RAMP 50A GATE2 DRNS RTNS 4284 BD 16 For more information www.analog.com Rev. A LTC4284 OPERATION The LTC4284 is designed to turn a board's supply voltage on and off in a controlled manner, allowing the board to be safely inserted or removed from a live, high power system. The device features four distinct operation modes: single driver mode (Mode 1), parallel mode (Mode 2), high stress staged start mode (Mode 3), and low stress staged start mode (Mode 4). Each of these modes addresses specific application requirements for SOA (Safe Operating Area), RDS(ON), and cost. In normal operation after a startup debounce delay, the LTC4284 turns on the external N-channel MOSFETs, passing the power to the load. The inrush control during startup is configurable between two methods. One is programmable active current limiting with an adjustable foldback factor. The other is constant dV/dt ramp control of the output voltage using a capacitor connected between RAMP and VEE. The inrush current is a function of the RAMP capacitor, the load capacitor and the attenuated load voltage seen between RTNS and DRNS. An 11.5V shunt regulator on VIN powers the LTC4284 with an external dropping resistor from the system RTN node. It also provides gate drive for GATE1 and GATE2. An optional buffer transistor driven by VZ boosts sourcing capability to supply external loads. An internally generated 5V supply on INTVCC supplies the logic control circuits, communication interface, data converters and EEPROM. Prior to turning on the MOSFETs, both VIN and INTVCC voltages must exceed their undervoltage lockout thresholds. In addition, the control inputs UVH, UVL, OV, EN#, PGIO3 and PGIO4 are monitored by comparators. The MOSFETs are held off until all startup conditions are met. The DRAIN, RTNS - DRNS and GATE voltages are monitored to determine if power is available for the load. Two power good signals are sequenced on PGIO1 and PGIO2, each with a delay that is twice the startup debounce delay. Additionally, PGIO3 serves as a watchdog input to monitor the output of the DC/DC module. If the module output fails to come up, the LTC4284 turns off the MOSFETs. PGIO4 defaults as an external fault input (inverted). PGIO1-4 can also be configured into general purpose inputs or outputs. An overcurrent fault at the output may result in excessive MOSFET power dissipation during Active Current Limiting (ACL). To limit this power in each channel, the ACL amplifiers regulate the SENSE1+ - SENSE1- and SENSE2+ - SENSE2- voltages at precise, programmable values (15mV to 30mV in 1mV steps). When the output voltage is low, power dissipation is further reduced by folding back the current limit, with the foldback ratio configurable to 10%, 20%, or 50% of nominal. In the event of a catastrophic output short when the sensed current is twice of the current limit, fast response comparators immediately pull the GATE pins down with 1.2A. When active current limiting is engaged, TMR is pulled up by a current that is proportional to the power dissipation in the MOSFET (M1) driven by GATE1. With an RC network representing the thermal behavior of M1 connected between TMR and VEE, the TMR voltage is proportional to the temperature rise in M1. When TMR voltage reaches its threshold of 2.048V (representing TJ(MAX) of the MOSFET), the overcurrent fault is logged and both GATE1 and GATE2 turn off, allowing protection of the MOSFETs based on true SOA. TMR can also be configured to drive a single capacitor. Following the overcurrent fault, the LTC4284 can either latch off the MOSFETs or auto-retry after a cooling delay. Both the retry delay and the number of retries are configurable, too. The LTC4284 also logs and responds to other faults including overvoltage, undervoltage, FET bad, Power Good Input (PGI) fault, FET short and external fault. Included in the LTC4284 is a pair of analog to digital converters (ADCs). The ADCs are configurable from 8-bit at 1kHz to 16-bit at 1Hz in five settings. As shown in the Block Diagram, ADC1 continuously monitors the current sense voltage between ADC+ and ADC-. ADC2 is synchronized to ADC1 and measures the attenuated input voltage at RTNS or the attenuated MOSFET drain voltage at DRNS plus one of the sixteen auxiliary inputs. Every time the ADCs finish taking a measurement, the current sense voltage is multiplied by the measurement of the RTNS or DRNS voltage to provide a power measurement. Every time power is measured, it is added to an energy accumulator that tracks the input energy or the energy consumption of the MOSFET. The energy accumulator Rev. A For more information www.analog.com 17 LTC4284 OPERATION can generate an optional alert upon overflow, and can be preset to allow it to overflow after a given amount of energy is reached. A time accumulator tallies energy increments; dividing the results of the energy accumulator by the time accumulator gives the average system power. The minimum and maximum of each ADC measurement and power are stored, and optional alerts may be generated if a measurement is above or below user configurable 8-bit thresholds. An internal EEPROM provides nonvolatile configuration of the LTC4284 operation behaviors and parameters. It also records fault information and selected ADC data. Seven bytes of uncommitted memory are reserved for general purpose storage. An I2C/SMBus interface accesses the ADC data registers and allows the host to poll the device and determine if a fault has occurred. If the ALERT# line is used as an interrupt, the host can respond to a fault in real time. A reboot command turns off the MOSFETs and automatically restarts after a configurable delay. The SDA line is divided into SDAI (input) and SDAO (output) to facilitate opto-coupling with the system host. Two three-state pins, ADR0 and ADR1, are used to decode eight device addresses. The communication interface can also be configured through ADR0 and ADR1 for a single-wire broadcast mode, sending ADC data and faults status through SDAO to the host without clocking the SCL line. This singlewire, one-way communication simplifies system design by eliminating two opto-couplers on SCL and SDAI that are required by an I2C interface. The transmission speed is configurable from 32kHz to 2MHz with four settings. APPLICATIONS INFORMATION The LTC4284 is ideally suited for high power, high availability distributed power systems, allowing a board to be safely inserted or removed from a live negative voltage backplane. The device features two GATE drivers that can be configured into parallel mode, high stress staged start mode, low stress staged start mode and single driver mode, each to optimize SOA and RDS(ON) of MOSFETs for different application requirements. In the following sections, the parallel mode is first chosen to demonstrate the common functions and basic hot-swap applications. The unique features and applications of each operation mode are then described separately. the -48V RTN through an external shunt resistor RIN to the VIN and VZ pins (Figure1). An internal shunt regulator clamps VIN to 11.5V relative to VEE and provides power to the GATE drivers. VZ acts as the shunt path of the regulator. A bypass capacitor of at least 0.1F is recommended between VIN/VZ and VEE. If EEPROM fault log is enabled (see Fault Log), the minimum bypass capacitance at VIN for the fault log operation to complete upon an undervoltage or power loss condition is Figure1 shows a basic 1.2kW application circuit with the dual-gate drivers configured in parallel mode. Figure2 shows a more complete application circuit in a dual-feed system with board insertion detection and opto-coupling. An internal 5V linear regulator that derives from the 11.5V supply powers data converters, logic control circuits, I2C interface and EEPROM. The 5V output is available at the INTVCC pin for driving external circuits. A bypass capacitor of 1F is recommended between INTVCC and VEE. To only test data converters or program EEPROM, the main -48V supply is not needed. Instead, a 5V supply may be applied between INTVCC and VEE, with VIN and VZ connected to INTVCC. Input Power Supply The LTC4284 features a floating topology that allows a wide operating voltage range and is robust to faults. For a -48V system, supply to the LTC4284 is derived from 18 F CIN 15 * (IIN(MAX) + IEXTERNAL ) mA Rev. A For more information www.analog.com LTC4284 APPLICATIONS INFORMATION -48V RTN CVCC 1F -48V RTN (SHORT PIN) R3 487k 1% R2 14.3k 1% VEE R1 10k 1% MODE VZ VIN CE1 4.7nF TMR EN# VEE SENSE2- ADC- SENSE1- GATE1 CG1 RG1 100nF 470 GATE2 DRAIN DRNS RG1A 10 RG1B 10 RD 100k DVDT = 0 THERM_TMR = 1 ILIM = 0001 FB = 11 FB_DIS = 1 LPFB = 1 RS1 0.5m RA1- 1 RA1+ 1 RA2- 1 RA2+ 1 VLOAD CL 1000F 4 4 PGIO1-4 SENSE1+ ADC+ SENSE2+ + 4 ADIO1-4 VEE BATTERY OPERATED (SUBJECT TO -36V INPUT STEPS) VEE SCL SDAI SDAO ALERT# ADIN1-4 VEE -48V INPUT RRB 5.11k 1% RTNS LTC4284 RAMP RE2 1.13M 1% CE2 68nF INTVCC OV RE1 18.2k 1% CUV 100nF VEE UVH UVL UV = 38.6V UV RELEASE AT 43.1V OV = 71.9V OV RELEASE AT 70.7V RRT 200k 1% RIN 4 x 1k IN SERIES 0.25W EACH CIN 0.1F RDB 5.11k 1% RDT 200k 1% - VEE VOUT M1A PSMN4R8-100BSE M1B PSMN4R8-100BSE RG2 470 CG2 100nF RG2A 10 RG2B 10 VEE M2A PSMN4R8-100BSE RS2 0.5m 4284 F01 M2B PSMN4R8-100BSE Figure1. -48V/1200W Hot Swap Controller with SOA Timer and Current Limited Inrush Control in Parallel Mode: GATE1 and GATE2 Simultaneously Turn On and Turn Off to Share Load Current and SOA RIN should be chosen to accommodate the maximum supply current requirement of the LTC4284 (IIN(MAX) = 4mA) plus the supply current required by any external devices driven by VIN and INTVCC at the minimum supply voltage, VS(MIN) and the maximum VIN voltage, VIN(MAX): RIN VS(MIN) -VIN(MAX) IIN(MAX) +IEXTERNAL The maximum power dissipation in the resistor is PMAX ( VS(MAX) - VIN(MIN) ) = 2 a capacitor of at least 0.1F. In this case RZ is chosen according to RZ VS(MIN) - VIN(MAX) - VBE IIN(MAX) +IEXTERNAL +20A where VBE and are the base-emitter voltage and DC current gain of the NPN transistor, respectively and 20A represents the minimum VZ operating current. The maximum power dissipation of QIN is PQIN,MAX = (VS(MAX) - VIN(MIN)) * IIN(MAX) RIN If the power dissipation of RIN is too high for a single resistor, use multiple resistors in series, which provides additional clearance spacing for high voltage surges. Another option uses an external NPN transistor (QIN) as illustrated in Figure2b. Each of VIN and VZ should be bypassed with RIN or RZ may be split into multiple segments in order to achieve the desired standoff voltage or dissipation. Whereas 1206 size resistors are commonly rated for 200V working and 400V peak, pad spacing and circuit board design rules may limit the working rating to as little as 100V. Rev. A For more information www.analog.com 19 LTC4284 APPLICATIONS INFORMATION LTC4355 100A RTN A A 100A UV = 32.4V UV RELEASE AT 35.3V R3 OV = 74.5V 499k OV RELEASE AT 73.2V 1% RTN B R8 10k R9 10k R6 100k R7 100k Q3 2N5401 RH 750 1% Q4 2N5401 R4 100k CE1 4.7nF CE2 68nF RRB 5.11k 1% UVH TMR UVL RAMP 4 1N4148 x2 RE2 1.13M 1% RRT 200k 1% R11 5.62k 1% R12 20k 1% VEE VEE R2 20k 1% R5 100k RE1 18.2k 1% 4 RTNS VREF VOUTTH OV ADIN1-4 LTC4284 ADIO1-4 EN# MODE CUV 100nF R10 100k SENSE2- ADC- SENSE1- B RS1 0.5m VEE 100A SENSE1+ ADC+ SENSE2+ 4x 2m R1 10k 1% CEN 1F HZS5C1 VEE LTC4371 -48V A 100A -48V B RA1- 1 RA1+ 1 RA2- 1 4x 2m RA2+ 1 DVDT = 0 THERM_TMR = 1 PWRGD_RESET_CNTRL = 1 ILIM = 0001 FB = 11 FB_DIS = 1 LPFB = 1 RS2 0.5m BACKPLANE PLUG-IN CARD BATTERY OPERATED (SUBJECT TO -36V INPUT STEPS) C 4284 F02a Figure2a. -48V/1200W Dual-Feed Hot Swap Controller with LTC4284 in Parallel Mode (Part One) For applications at very high voltages (>300V), a high voltage MOSFET can be used. Figure3 shows an application circuit with a depletion mode N-channel MOSFET that can withstand up to 1000V drain-to-source voltage. In this case RZ is chosen according to RZ VS(MIN) -VIN(MAX) - VGS 20A where VGS is the gate-to-source voltage of the MOSFET (positive for an enhancement mode and negative for a depletion mode transistor) . When using an enhancement mode transistor, VZ voltage must be kept lower than its absolute maximum of 16V: VZ(MAX) = VIN(MAX) + VGS < 16V In Figures 2b and 3, the voltage drop and power dissipation in the NPN or the MOSFET may be augmented by the use of one or more resistors in series with the collector or drain. If an external 12V supply is available on 20 the application board, it may be used to drive the VIN pin directly as shown in Figure4. Turn-On Sequence The following conditions must be satisfied before the turn-on sequence is started. First the voltage at VIN must exceed the undervoltage lockout level of 8.1V. Next the internal supply INTVCC must cross its 4V undervoltage lockout level. This generates a 1.3ms power-on-reset delay. After the delay times out, the voltages at UVH, UVL and OV must satisfy UVH > 2.048V, UVL > 1.833V and OV < 1.406V to indicate that the input power is within the acceptable range, and EN# must be pulled low. All the above conditions must be satisfied throughout the duration of the startup debounce delay of 128ms. If any of the above conditions is violated during the delay, the delay is reset and restarted. After the delay expires, if the ON bit in CONTROL_1 register 0x0A is high, the LTC4284 turns on the MOSFETs. Otherwise, the MOSFET will be turned Rev. A For more information www.analog.com LTC4284 APPLICATIONS INFORMATION A RZ 100k CZ 0.1F VEE VIN+ CVCC 1F QIN BCP56 CIN 0.1F R13 5.1k VEE VEE VZ R15 5.1k R14 5.1k VIN R17 5.1k R16 5.1k R19 5.1k R18 5.1k VOUT+ VIN+ VOUT+ VOUT- VIN- VOUT- CASE ON CASE FLTR100V10 FILTER MODULE VIN- JW050A1-E POWER MODULE INTVCC 6N139 Q10 R22 5.1k VDD LTC2900 RST GND + VEE PGIO4 PGIO3 SCL SDAI LTC4284 VLOAD MOC207 Q7 PGIO2 PGIO1 SDAO RG2 470 CG1 100nF GATE2 RG1A 10 DRAIN RG1B 10 VEE B DRNS VEE RDB 5.11k 1% RDT 200k 1% VEE RD 100k Q8 HCPL2630 DUAL ALERT# GATE1 R20 0.51k HCPL-0300 Q5 M1A PSMN4R8-100BSE 6N139 R21 0.51k SCL SDA VDD MICROCONTROLLER ALERT Q6 CL 1000F 100V OV TRANSIENT RESEVOIR CAPACITOR Q9 - RST GND M1B PSMN4R8-100BSE RG2 470 CG2 100nF RG2A 10 RG2B 10 RL 343 7 x 2.4k, 0805 EACH 28.7W VEE C M2A PSMN4R8-100BSE MBRM5100 4284 F02b VOUT M2B PSMN4R8-100BSE Figure2b. -48V/1200W Dual-Feed Hot Swap Controller with LTC4284 in Parallel Mode (Part Two) on (without additional delay) when the ON bit is set to 1 through the I2C interface. When all turn-on conditions are satisfied, the FET_ON_STATUS bit in SYSTEM_STATUS register 0x00 is set to 1, indicating the MOSFETs are commanded on. RTN RZ 1M MIN IXTY08N100D2 DEPLETIONMODE CZ 0.1F CIN 0.1F VZ VIN LTC4284 VEE -48V 4284 F03 Figure3. The LTC4284 Can Operate to >300V Using a Depletion Mode N-Channel MOSFET VZ EXTERNAL 12V SUPPLY* CIN 0.1F VIN LTC4284 VEE VEE VEE -48V 4284 F04 *MUST COMPLY WITH MAXIMUM RATING OF VIN PIN The turn-on sequence continues by charging up the GATEs with 50A current sources. When the GATE voltage reaches the MOSFET threshold voltage, the MOSFET begins to turn on and the inrush current charges the load capacitor CL to ramp the MOSFET drain towards VEE in a controlled manner (see Inrush Control). When the MOSFET drain is ramped down to VEE or the output is ramped up to the supply voltage, the GATEs are pulled up to VIN and the MOSFETs are fully enhanced. The GATE1_HIGH and GATE2_HIGH bits in SYSTEM_STATUS register 0x00 are set when GATE1 and GATE2 are above VIN - 1.8V. Figure5 illustrates the startup sequence of the LTC4284 in parallel mode. Figure4. Using an External 12V Supply Rev. A For more information www.analog.com 21 LTC4284 APPLICATIONS INFORMATION -48V INPUT GATE1 UVLO AND UV CLEARED 128ms VIN - 1.8V VIN - 1.8V GATE2 MOSFET VDS CURRENT INTERNAL POWER GOOD 2.048V LOAD1 + LOAD2 LOAD1 INRUSH (LATCHED) 256ms 256ms 512ms PWRGD1# READY PGIO1 PWRGD2# READY PGIO2 FAULTY POWER GOOD INPUT PGIO3 NORMAL POWER GOOD INPUT 4284 F05 Figure5. LTC4284 Turn-On Sequence in Parallel Mode During the power-on-reset delay of 1.3ms, the fault registers are cleared and the control registers are loaded with the data held in the corresponding EEPROM registers. The power-on-reset can be detected using the PORB bit in register 0x0E, which will be cleared when INTVCC dips below 3.8V. Set this bit to 1 in normal operating conditions and keep monitoring this bit. A 0 from subsequent reading indicates a power-on-reset has occurred. -48V RTN RIN CIN VEE RDT 200k 1% RRB 5.11k 1% RDB 5.11k 1% RAMP VZ VIN CR RTNS + VEE VEE VLOAD DRNS CL LTC4284 VEE Inrush Control Inrush current control can be configured in two ways. First, if the DVDT bit in CONTROL_1 register 0x0A is set to 1, the inrush current is controlled in dV/dt mode by an external capacitor connected between RAMP and VEE (the RAMP capacitor, CR), as shown in Figure6. In dV/dt mode, the inrush current is limited by controlling a constant output voltage ramp rate (dV/dt). During startup, when the GATE voltage reaches the MOSFET threshold voltage, RAMP outputs a fixed 2.5A current to charge CR while the inrush current charges load capacitor CL. 22 RRT 200k 1% SENSE2- SENSE1- SENSE1+ SENSE2+ GATE1 GATE2 -48V INPUT RS1 RS2 - VOUT M1 M2 4284 F06 Figure6. dV/dt Inrush Control Using RAMP Capacitor During dV/dt control the LTC4284 regulates the RAMP to the attenuated load voltage between RTNS and DRNS with an offset: VRAMP = VRTNS - VDRNS + 0.18V Rev. A For more information www.analog.com LTC4284 APPLICATIONS INFORMATION and regulates the inrush current to a fixed value that is a function of the attenuation ratio, r and the ratio between load capacitance and RAMP capacitance: Limit Foldback for details. In this mode the RAMP capacitor CR at the RAMP pin no longer takes effect. If CR is omitted, RAMP must be left open. C IINRUSH = 2.5A * r * L CR In parallel mode or single driver mode, GATE1 and GATE2 are turned on simultaneously to charge the load capacitor. In staged start modes, GATE1 is turned on first to charge the load capacitor and GATE2 is turned on after the load capacitor is fully charged. See High Stress Staged Start Mode (Mode 3) and Low Stress Staged Start (Mode 4) for details. The attenuation ratio r is set by the external resistive dividers at RTNS (RRT and RRB) and DRNS (RDT and RDB) in Figure6: R +R R +R r= RT RB = DT DB R RB R DB Power Good Monitors and PGI Fault RTNS and DRNS represent the attenuated input voltage and MOSFET drain voltage, respectively. The differential voltage between RTNS and DRNS therefore represents the attenuated load voltage. The operation range of VRTNS, VDRNS and VRTNS - VDRNS is from 0V to 2.8V. The dV/dt control is only active during initial startup. After the turn-on sequence is completed and power good signals are activated, the dV/dt inrush control mode is disabled and RAMP is discharged with a 4mA current. RAMP will also be discharged under any GATE turn-off conditions. In the dV/dt mode the inrush current must be set lower than the folded back current limit level to avoid triggering the current limit (see below). The second inrush control mechanism is active current limiting. This is enabled by clearing the DVDT bit in CONTROL_1 register 0x0A. In this mode the inrush current is regulated to the folded back current limit: IINRUSH = ILIM * STARTUP where ILIM is the current limit and STARTUP is the startup foldback factor. ILIM is determined by the current limit sense voltage VILIM and the sense resistance RS. V ILIM = ILIM RS VILIM is configurable from 15mV to 30mV in 1mV steps. STARTUP is configurable to 10%, 20%, 50% and 100% (no foldback) of current limit. During startup the current limit foldback profile is flat and does not change with output voltage. See Current Limit Adjustment and Current After the MOSFETs are turned on, the following conditions must be met before the power good signals are activated. First, the DRAIN voltage must fall below 2.048V to indicate the MOSFET drain is low. Second, RTNS - DRNS must be higher than the external threshold voltage at VOUTTH to indicate the output voltage is high. Last, GATE voltages must satisfy the GATE high (>VIN - 1.8V) condition. For parallel mode, one GATE must be high and the other GATE must be either high or in current limit. When all three conditions are met, an internal power good signal is latched, the PG_STATUS bit in SYSTEM_STATUS register 0x00 is set, and a series of three delay cycles are started as illustrated in Figure5. When the first delay of 256ms expires, the first power good signal PGIO1 turns on the first load. When the second delay of 256ms expires, the second power good signal PGIO2 can be used to turn on a second load. Following the two 256ms delays, a third delay of 512ms is started for monitoring PGIO3 as a power good input (PGI) watchdog. Before this delay expires, PGIO3 must be pulled low or high (polarity configurable by register 0x10) by an external supply monitor to indicate the load is working properly. Otherwise, the MOSFETs are turned off and a PGI fault is logged in FAULT register 0x04. The MOSFETs are allowed to auto-retry after a delay of 128ms following the PGI fault if the PGI_RETRY bit in CONTROL_2 register 0x0B is set to 1. Both power good signals and the power good input can be configured into inverted or non-inverted polarity using PGIO_CONFIG_1 register 0x10 (see Table12). To disable the PGI watchdog, connect PGIO3 to VEE or INTVCC depending on the configured polarity, or configure PGIO3 as general purpose input or output using register 0x10. Rev. A For more information www.analog.com 23 LTC4284 APPLICATIONS INFORMATION Power good signals are reset in two configurable ways. If the PWRGD_RESET_CNTRL bit in CONTROL_1 register 0x0A is set to 1, power good signals are reset by an output low condition as indicated by RTNS - DRNS < VOUTTH. In Figure2a VOUTTH is biased at 0.8V, so power good signals will be reset when RTNS - DRNS drops below 0.8V, which corresponds to VOUT < 32V. If the PWRGD_RESET_CNTRL bit is cleared, power good signals are reset by any GATE turn-off conditions except overvoltage fault. When the power good signals are reset, the power good delays and the PGI delay are also reset. Turn-Off Sequence In any of the following conditions, the MOSFETs are turned off by pulling down the GATE pins with 9mA current sources and the FET_ON_STATUS bit in SYSTEM_ STATUS register 0x00 is cleared. 1.VIN is lower than 7.6V (VIN undervoltage lockout). 2.INTVCC is lower than 3.8V (INTVCC undervoltage lockout). 3. EN# is high. 4. ON bit in CONTROL_1 register 0x0A is cleared. 5. OV is higher than 1.406V (overvoltage fault). 6. UVL is lower than 1.833V and UVH is lower than 2.048V (undervoltage fault). 7. TMR reaches its 2.048V threshold (overcurrent fault). 8. DRAIN rises above 2.048V or GATE dips below VIN - 1.8V and this condition lasts longer than a preconfigured delay (FET bad fault). 9. PGIO3, when configured as PGI#/PGI input, is high/ low when the PGI check delay of 512ms expires (PGIfault). 10.PGIO4 pin, when configured as EXT_FAULT#/EXT_ FAULT, is low/high (external fault). 11.The RBT_EN bit in REBOOT register 0xA2 is set. For condition 8, if the FET_BAD_TURN_OFF bit in CONTROL_1 register 0x0A is cleared, the MOSFETs remain on following a FET bad fault. For condition 10, 24 if the EXT_FAULT_TURN_OFF bit in CONFIG_3 register 0x0F is cleared, the MOSFETs remain on following an external fault. For condition 11, the LTC4284 will automatically reboot after a programmable delay. See Reboot on I2C Command. For each independent GATE turn-off fault, the LTC4284 can be configured to latch off the MOSFETs or go into an auto-retry sequence after the fault occurs. In parallel mode or single driver modes, GATE1 and GATE2 are turned off simultaneously. In high stress or low stress staged start modes, GATE2 turn-off depends on GATE1 turn-off and other conditions. Refer to the sectors covering high stress staged start mode and low stress staged start mode for details. Overcurrent Protection The LTC4284 features two levels of protection from short-circuit and overcurrent conditions. Load current is monitored by SENSE1,2+ and SENSE1,2- pins and sense resistors. There are two distinct thresholds for the sense voltages: VILIM and VILIM(FAST). VILIM is configurable from 15mV to 30mV in 1mV steps and VILIM(FAST) is always twice VILIM. See Current Limit Adjustment for details. If the sense voltage of a channel reaches VILIM, the corresponding GATE is pulled down by 25mA current until the associated active current limit loop is engaged. In the event of a catastrophic short-circuit or a sudden input step, where the sense voltage of a channel reaches VILIM(FAST), the corresponding GATE is immediately pulled down by a 1.2A current to limit peak current through the MOSFET. When the sense voltage drops to VILIM, the active current limit loop is engaged. SOA Timer During active current limit, the power dissipation in the MOSFET is large. If this power dissipation persists, the MOSFET can reach temperatures that cause damage. MOSFET manufacturers specify the safe limits on operating voltage, current and time as a curve referred to as the Safe Operating Area (SOA). Commonly, a circuit breaker timer sets a maximum time for the MOSFET to operate in a current limit mode. When this timer expires, the MOSFET Rev. A For more information www.analog.com LTC4284 APPLICATIONS INFORMATION The LTC4284 features a circuit breaker timer that better fits the SOA of the MOSFET. When active current limit is engaged, the OC_STATUS bit in FAULT_STATUS register 0x03 is set, and the TMR pin is activated and charged up by a current proportional to the power dissipation in the MOSFET that is driven by GATE1. The enabling condition of the TMR charging current depends on the operation mode (see OC_STATUS bit column in Table1). A proper electric model (RC network) is selected to represent the thermal behavior of the MOSFET. When this RC network is connected between TMR and VEE, the TMR voltage is proportional to the rise in the MOSFET junction temperature. The LTC4284 compares the TMR voltage to a fixed threshold voltage of 2.048V, which represents the maximum allowable junction temperature rise in the MOSFET. When the TMR voltage crosses this threshold, the LTC4284 turns off the MOSFET. Therefore, to provide an appropriate protection of a MOSFET, one simply selects the MOSFET that meets the SOA requirement for allowable operating conditions such as startup and input step. The MOSFET is automatically turned off before it is subject to any condition that would exceed its SOA rating. Case 1. If active current limit is engaged in normal operation (power good signals are asserted), the TMR pull-up current of the LTC4284 is proportional to the attenuated drain voltage of the MOSFET at DRNS (top line in Figure7). This is proportional to the power dissipation since the current through the MOSFET is fixed during 350 VSENSE1 = 300 TMR PULL-UP CURRENT (A) is turned off to protect it from overheating. Traditional circuit breakers often employ a fixed current charging an external capacitor. The minimum timer timeout must be set to allow the worst-case operating condition, such as completely charging a large bypass capacitor at output during startup or riding through a large input step. Then upon fault conditions such as an output short-circuit at full supply voltage, the MOSFET must withstand the large power throughout the entire timer duration. Therefore, the MOSFET must be selected to withstand the worstcase SOA condition that occurs during any possible normal operating condition or fault condition. This not only substantially increases the cost of the MOSFET, but also complicates the design procedure and MOSFET selection. 100% VILIM 96.7% VILIM 50% VILIM 20% VILIM 10% VILIM 250 200 150 100 50 0 0 0.5 1 1.5 2 DRNS VOLTAGE (V) 2.5 3 4284 F07 Figure7. TMR Pull-Up Current vs VSENSE1 and DRNS Voltage current limit (provided that foldback is disabled in normal operation by setting the FB_DIS bit in CONFIG_1 register 0x0D). The TMR pull-up current in this condition is: A ITMR(UP) =111.1 * VDRNS +2A V where 111.1A/V is the transconductance. The TMR pullup current reaches 202A at VDRNS=1.8V, which is tested and specified. The offset of 2A is introduced to guarantee a minimum pull-up current that prevents TMR from hanging in a resistive short-circuit condition. The above equation also applies to startup in dV/dt mode (DVDT bit in CONTROL_1 register 0x0A = 1), when the current limit is triggered under a fault condition such as a short-circuit. The accelerated timeout combined with startup foldback (see Current Limit Foldback) protects the startup MOSFET from overstress. Case 2. During startup in dV/dt mode when current limit is not engaged, TMR pull-up current is disabled: ITMR(UP) = 0 In this case a 2A pull down current holds TMR low if the THERM_TMR bit in control register 0x0A is set. This avoids undesired timeout before the load capacitor is fully charged by the inrush current, which is set to such a low level that the power dissipation in the startup MOSFET is insignificant. Rev. A For more information www.analog.com 25 LTC4284 APPLICATIONS INFORMATION Case 3. If current limit is engaged during startup in current limit mode (DVDT bit in CONTROL_1 register 0x0A = 0), the TMR pull-up current is reduced by the foldback ratio: A ITMR(UP) = STARTUP *111.1 * VDRNS + 2A V where STARTUP is the startup foldback ratio that is controlled by the FB bits in CONFIG_1 register 0x0D (see Current Limit Foldback). The reduction keeps the transconductance unchanged compared to that in normal operation with foldback disabled. Case 4. If current limit is not engaged, either in normal operation or during startup in current limit mode, the TMR pull-up current is gated by the DRAIN voltage. If DRAIN is lower than its threshold, VD,FET(TH), the TMR pull-up current is disabled. VD,FET(TH) is programmable from 72mV to 203mV in geometric scale using the VDTH bits in CONFIG_2 register 0x0E. This is a typical case in normal operating conditions when MOSFETs are fully enhanced. If DRAIN is higher than VD,FET(TH), an internal multiplier charges up TMR with a current approximately proportional to power dissipation in the channel 1 MOSFET: If VSENSE1 0.1VILIM, V A ITMR(UP) = 111.1 * VDRNS * SENSE1 - 0.1 +2A VILIM V The configuration of the RC network for a particular MOSFET starts with selection of a desired number of resistive and capacitive elements and their values in thermal domain based on the thermal impedance plot provided by the MOSFET manufacturer. Three resistors and three capacitors are usually enough to fit the plot fairly well from 10s to 100ms, which covers the timing range of typical operating and fault conditions. Two resistors and two capacitors may provide an acceptable accuracy for some MOSFETs or conditions. If better fitting accuracy or wider fitting range is desired, more elements may be used. After the thermal RC network is configured, the thermal quantities are then converted to electric quantities according to R E =k * R C CE = k where RE and CE are electric resistance and capacitance, respectively and R and C are thermal resistance and capacitance, respectively. The conversion constant k is given by If VSENSE1 < 0.1VILIM, ITMR(UP) = 2A Figure7 shows the TMR pull-up currents vs VDRNS at four different VSENSE1+ - VSENSE1- levels below current limit. If using an RC network representing the MOSFET thermal model between TMR and VEE, the THERM_TMR bit in CONTROL_1 register 0x0A must be set to 1 to disable the internal 2A pull-down current. The total resistance in the RC network provides the discharge path to TMR. The RC network connected to TMR should be configured to represent the electric model of the thermal behavior associated with the MOSFET (M1) driven by GATE1. M1 should be selected so that its SOA is equal to or worse than that of the MOSFET (M2) driven by GATE2. Since GATE2 turns off when GATE1 turns off due to TMR timeout, M2 26 is automatically protected when M1 is turned off under overload conditions. k= VDS,MAX *ID,MAX VTMR(TH) * ITMR(UP),MAX TMAX where VDS,MAX and ID,MAX are the maximum drainto-source voltage and maximum drain current of the MOSFET, respectively, ITMR(UP),MAX is the TMR pull-up current corresponding to the maximum power dissipation PMAX = VDS,MAX * ID,MAX, VTMR(TH) is TMR threshold voltage (2.048V), and TMAX is the maximum allowable temperature rise of the MOSFET. For example, if VDS,MAX = 72V, ID,MAX = 32A, ITMR(UP),MAX = 202A (at VDRNS = 1.8V, in current limit) and TMAX = 65C (maximum junction temperature of MOSFET = 150C and ambient temperature = 85C), k = 3.6 * 105 [V2/C]. An RC network consisting of two resistors and capacitors that represent the electric model for the thermal behavior of PSMN4R8100BSE is show in Figure2a. Rev. A For more information www.analog.com LTC4284 APPLICATIONS INFORMATION The LTC4284 also allows a single capacitor connected between TMR and VEE (see Figure13 and Figure15). In this case, the THERM_TMR bit in the CONTROL_1 register must be cleared to enable the internal 2A pull-down current. Once enabled, the 2A pull-down current keeps TMR low in normal conditions when the pull-up current is disabled. When the pull-up current is enabled under fault conditions, the 2A pull-down is switched off. A minimum capacitance must be selected to keep the MOSFETs on during worst-case operating conditions, and the MOSFETs must be selected to withstand the worst-case SOA condition during normal operating or fault conditions. Regardless of the value of the THERM_TMR bit, when EN# is higher than its 1.28V threshold, TMR is discharged by a 5mA current. When TMR is below 0.1V, the TMR_LOW bit in SYSTEM_STATUS register 0x00 is set to 1. Overcurrent Fault and Auto-Retry Under an overcurrent condition, when the active current limit loops are engaged and TMR is being charged up, the overcurrent present bit, OC_STATUS, in FAULT_STATUS register 0x03 is set. When the TMR voltage reaches its 2.048V threshold, the overcurrent fault bit, OC_FAULT, in the FAULT register 0x04 is set and the GATE pins are pulled down to turn off the MOSFETs. After the MOSFETs are turned off, the OC_STATUS bit is cleared. The MOSFETs are allowed to turn on again after a cooling delay if the OC_RETRY bits in CONTROL_2 register 0x0B have not been cleared. The auto-retry cooling delay is configurable from 512ms to 65.5s in binary scale using the COOLING_DL bits in CONFIG_2 register 0x0E (See Table11). During the cooling delay the DELAY_STATUS bit in REBOOT register 0xA2 is set to 1 to indicate the delay timer is running. It will be cleared when the delay expires. The number of retries following an overcurrent fault can be configured to 1, 7 or infinity using the OC_RETRY bits (see Table10). If a finite retry number is selected, a retry counter reset timer of 16.4s is started upon the retry following an overcurrent fault. If the next overcurrent fault occurs before the timer times out, the retry counter increments and the timer is restarted. Otherwise the retry counter is restarted. When the programmed number of retries is reached, the MOSFETs will be latched off if the next overcurrent fault occurs before the counter reset timer times out. During startup when power good conditions are not met, the counter reset timer is disabled. The retry counter and the counter reset timer for the overcurrent fault are independent of those for the FET bad fault. If the OC_RETRY bits in the CONTROL_2 register 0x0B have been cleared, the MOSFETs will remain off until the OC_FAULT bit is reset (see Resetting Faults). When the OC_FAULT bit is reset, the MOSFETs are allowed to turn on after the auto-retry delay expires. Current Limit Adjustment The current limit voltage, VILIM, is programmable between 15mV and 30mV in 1mV steps through the I2C interface using the ILIM bits in CONFIG_1 register 0x0D. The default values are stored in EE_CONFIG_1 register 0xAD in the onboard EEPROM. The fast GATE pull-down sense voltage, VILIM(FAST), is set to twice of VILIM through the whole configuration range. The fine scales are useful in adjusting the sense voltage to achieve a given current limit using the limited selection of standard sense resistor values available around 1m. The adjustability allows the LTC4284 to reduce available current for light loads or increase it in anticipation of a surge. This feature also enables the use of board-trace as sense resistors by trimming the sense voltage to match measured copper resistance during final test. The measured copper resistance may be written to the undedicated scratch pad area of the EEPROM (0xE9-0xEF) so that it is available to scale ADC current measurements. Current Limit Foldback The LTC4284 current limit can be configured to fold back to four levels: 10%, 20%, 50% and 100% (no foldback) of full current limit using the FB bits in the CONFIG_1 register 0x0D. During the startup inrush control the foldback profile is flat (Figure8a), resulting in a constant current limit. This is to protect the MOSFETs more effectively upon a resistive output short during startup. With a traditional resistive foldback profile, if the output short resistance is the same as the slope of the foldback profile, the foldback has no effect and MOSFETs with larger SOAs must be selected to withstand the full stress, substantially increasing the MOSFET cost. Rev. A For more information www.analog.com 27 LTC4284 APPLICATIONS INFORMATION limit sense voltage decreases linearly to 50% when RTNS - DRNS reaches 1.8V (corresponding to the maximum supply voltage). This profile approximately tracks the load power when the output voltage increases with a constant powerload. FB = 00 100 VILIM (%) VRTNS = 1.8V FB = 01 50 FB = 10 20 FB = 11 10 0 0.9 VRTNS - VDRNS (V) 0 1.8 4284 F08a Figure8a. Current Limit Foldback During Startup FB = 00 100 LPFB = 0 LPFB = 1 VILIM (%) 01 10 50 11 VRTNS = 1.8V 20 10 0 0 0.9 VRTNS - VDRNS (V) 1.8 4284 F08b Figure 8b. Current Limit Foldback in Normal Operation After the internal power good signal is latched (see Power Good Monitors and PGI Fault), the LTC4284 goes into normal operation and the foldback is determined by the attenuated output voltage for the load, RTNS - DRNS (Figure8b). If the output voltage or RTNS - DRNS drops to 0V in an event such as a catastrophic output short, the current limit sense voltage is folded back to the ratio configured by the FB bits. As shown in Figure8b, the foldback ratio increases linearly with RTNS - DRNS and reaches 100% when RTNS - DRNS reaches 0.9V, which corresponds to the minimum supply voltage of an application. Above 0.9V the current limit sense voltage stays constant unless the load power foldback (LPFB) bit in the CONFIG_1 register 0x0D is set. If the LPFB bit is set, the current 28 The LTC4284 foldback profile can differentiate an output short fault from an allowed input step. Upon an output short, RTNS - DRNS drops and current limit is folded back to protect the MOSFETs from overstress. In the event of an input step, RTNS - DRNS increases while the load is charged up. The current limit either stays constant or approximates constant load power (based on the LPFB bit) to approach the optimum output ramp and minimize the temperature rise of the MOSFETs (see Input Step and Optimum Output Ramp). This is superior to a foldback profile capacitance based upon VDS or power dissipation of the MOSFET. In that case, the output short and input step conditions cannot be differentiated, often resulting in unwanted turn-off upon an input step. Foldback in normal operation can be independently disabled by setting the FB_DIS bit in the CONFIG_1 register 0x0D. With this configuration foldback is only effective during startup, and it should only be used when an RC network representing the thermal model of the MOSFET is connected to TMR. If a single capacitor is used, it is recommended to enable foldback in normal operation by clearing the FB_DIS bit for more conservative protection of the MOSFET. Note that the load power foldback controlled by the LPFB bit is not affected by the FB_DIS bit. FET Bad Fault and Auto-Retry In a hot swap application several possible faults can prevent the MOSFETs from turning on fully. A damaged MOSFET may have leakage from gate to drain or have degraded RDS(ON). Debris on the board may also produce leakage or a short from the GATE pins to VEE or the MOSFET drain. In these conditions the LTC4284 may not be able to pull the GATE pins high enough to fully enhance the MOSFETs, or the MOSFETs may not reach the intended RDS(ON) when the GATE pins are fully enhanced. This can put the MOSFETs in a condition where the power in the MOSFETs is higher than its continuous power capability, even though the current is below the current limit. The Rev. A For more information www.analog.com LTC4284 APPLICATIONS INFORMATION LTC4284 monitors the integrity of the MOSFETs in two ways, and acts on both of them in the same manner. First, the LTC4284 monitors the MOSFET drain voltage at the DRAIN pin. A comparator detects a DRAIN high condition whenever DRAIN is above a reference voltage, VD,FET(TH) that can be configured to 72mV, 102mV, 143mV or 203mV (geometric scale) using the VDTH bits in the CONFIG_2 register 0x0E. Second, the LTC4284 monitors the GATE voltages. If the MOSFETs are turned on, but the GATE1 and/or GATE2 voltages are lower than VIN - 1.8V, a GATE low condition is detected. The logic that determines a GATE low condition depends on the operation mode (see Table1). For the parallel mode, in turn-on state, a GATE low condition is detected in either of the following two conditions: (1) both GATE1 and GATE2 are low; (2) One GATE is low but not in current limit. When either a DRAIN high or a GATE low condition is present when the MOSFETs are commanded on, the FET_BAD_STATUS bit in FAULT_STATUS register 0x03 is set and an internal FET bad fault timer is started. The FTBD_DL bits in CONFIG_2 register 0x0E configures the timer duration to 256ms, 512ms, 1.02s and 2.05s. If the DRAIN voltage falls below VD,FET(TH) and the GATE low conditions are cleared before the timer times out, the FET_BAD_STATUS bit is cleared and the timer is reset. If the timer does time out, the FET_BAD_FAULT bit in FAULT register 0x04 is set and the MOSFETs are turned off if the FET_BAD_TURN_OFF bit in CONTROL_1 register 0x0A has been set. The DRAIN high condition also activates TMR pull-up current when not in current limit (see SOA Timer). Note that during startup while the load is being charged, the FET_BAD_STATUS bit is set and the FET bad fault timer is running. To avoid undesired turn-off, the timer duration must be configured long enough for the load to be fully charged. After the MOSFETs are turned off following a FET bad fault, the FET_BAD_STATUS bit is cleared. The MOSFETs are allowed to turn on again after a cooling delay if the FET_BAD_RETRY bits in CONTROL_2 register 0x0B have not been cleared. The cooling delay is the same as that for an overcurrent fault and is configurable from 512ms to 65.5s in binary scale using the COOLING_DL bits in CONFIG_2 register 0x0E (see Table11). During the cooling delay the DELAY_STATUS bit in REBOOT register 0xA2 is set. It will be cleared when the delay expires. The FET_BAD_RETRY bits configures the number of retries following a FET bad fault to 1, 7 or infinity (see Table10). If a finite retry number is selected, a retry counter reset timer of 16.4s is started upon the retry following a FET bad fault. If the next FET bad fault occurs before the timer expires, the retry counter increments and the timer is reset. Otherwise the retry counter is reset. The retry counter and the counter reset timer for the FET bad fault are independent of those for the overcurrent fault. If the FET_BAD_RETRY bits in CONTROL_2 register 0x0B have been cleared, the MOSFETs will remain off until the FET_BAD_FAULT bit is reset (see Resetting Faults) or the FET_BAD_TURN_OFF bit is cleared through I2C. In either of those two cases, the MOSFETs are allowed to turn on after the auto-retry delay expires. Input Step and Optimum Output Ramp In events such as battery hot swapping or supply surge, the input voltage may experience a sudden step. The magnitude of the input step, V, can be as large as tens of volts. As long as the input voltage does not exceed the overvoltage limit, the input step is not a fault condition and the system should stay on and operate through it. In the presence of the load capacitor, the output does not follow the input immediately, but rather ramps up from the initial supply voltage to the new supply voltage while charging the load capacitor. The VDS of the MOSFET initially jumps to V and then ramps down. Additionally, during the output ramp the MOSFET not only carries the load current, IL but also the capacitance charging current, ICL, so the total power dissipation in the MOSFET can be very large. If a large input step is possible, it is usually the worst-case operating condition for the SOA of the MOSFET, and proper MOSFETs must be selected to withstand the stress. In such a condition, the minimum temperature rise of the MOSFET is achieved when ICL matches IL, or the total current is twice the load current. In other words, the current Rev. A For more information www.analog.com 29 LTC4284 APPLICATIONS INFORMATION limit should be set to twice the load current during the output ramp: ILIM(OPT) = 2 * IL This is in contrast to the concept of foldback that is used to protect the MOSFET in a short-circuit condition. The foldback profile of the LTC4284 automatically takes care of both input step and output short-circuit conditions by relating the foldback ratio to the output voltage for the load instead of VDS of the MOSFET. See Figure8b and Current Limit Foldback for details. Additionally, if the load follows a constant power relationship, the LPFB bit in CONFIG_1 register 0x0D can be set to enable load power foldback so that the current limit approximately tracks twice the load current during the output ramp. The waveforms in Figure9 show how the LTC4284, operating in the parallel mode, responds to a -36V to -72V input step -36V INPUT -72V MOSFET VDS 36V 36V High current applications often demand several power MOSFETs in parallel to reach a target RDS(ON) under 1m that is unavailable in a single MOSFET. In such cases several parallel sense resistors are also used to get small values that are not available as a single resistor. Further, dividing the load current amongst multiple devices alleviates the PCB current crowding problem with the use of a single MOSFET. VIN MOSFET VTH VIN MOSFET VTH ILIM = LOAD + INRUSH CURRENT LOAD LOAD LOAD 4284 F09 Figure9. LTC4284 Responds to -36V to -72V Input Step with a Constant Power Load (in Parallel Mode, LPFB = 1) 30 The LTC4284 features dual-gate drivers that are configured by the MODE pin into four distinct operation modes: single driver, parallel, high stress staged start, and low stress staged start. As shown in Table 1, each mode features specific SOA or RDS(ON) benefit, GATEs on/off behavior, power good signaling and fault detection logic. Leave MODE open (or bias it between 1V and INTVCC - 0.85V) to select the single driver mode (Mode 1). Pull MODE lower than 0.4V (e.g., connect to VEE) to select the parallel mode (Mode 2). Force MODE higher than INTVCC + 2.5V (e.g., connect to VIN) to select the high stress staged start mode (Mode 3). Bias MODE between INTVCC - 0.25V and INTVCC + 0.5V (e.g., connect to INTVCC) to select the low stress staged start mode (Mode 4). Each mode has a dedicated status bit in SYSTEM_STATUS register 0x00 (Table4) and ADC_STATUS register 0x01 (Table5) to indicate the mode is selected. The parallel mode works well for systems with large input steps or supply surges. The MOSFETs must be selected to withstand this worst-case operating condition for the SOA. See Input Step and Optimum Output Ramp for details. VLOAD GATE2 Dual-Gate Operation Modes Parallel Mode (Mode 2) 72V GATE1 to achieve the optimum output ramp rate. Note that the power good signals on PGIO1 and PGIO2 are not interrupted during an input step. Parallel MOSFETs share current well when they are fully enhanced, however when the MOSFETs are limiting current the offset mismatch between gate thresholds will cause the MOSFET with the lowest threshold to carry more current than the others. As this MOSFET gets hot it carries even more current since threshold voltage has a negative temperature coefficient. Eventually all the load current may Rev. A For more information www.analog.com LTC4284 APPLICATIONS INFORMATION Table1. Configuration of the LTC4284 Dual-Gate Operation Modes MODE 1.Single Driver MODE PIN Open FEATURE GATE Pull-up and Pull-down Doubled 2.Parallel Tied to SOA Doubled, VEE RDS(ON) Halved 3.High Tied to Stress VIN Staged Start GATE1 Drives High SOA MOSFET, GATE2 Drives Low RDS(ON) MOSFET 4.Low Tied to Stress INTVCC Staged Start GATE1 Drives Low SOA MOSFET, GATE2 Drives Low RDS(ON) MOSFET POWER GOOD LATCH* TURN ON SEQUENCE GATE1 and GATE2 Turn On at the Same Time SET DRAIN < 2.048V AND VOUT High AND (Both GATE1 AND GATE2 High) RESET OC_STATUS BIT GATE1 TURN GATE2 TURN FET BAD STATUS/ OFF OFF FAULT FET_ON High AND [DRAIN > VD,FET(TH) OR (GATE1 OR GATE2 Low)] ACL1 On OR ACL2 On Start-Up: ACL1 DRAIN < On OR ACL2 VD,PG(TH) AND On; Running: VOUT High AND Both ACL1 [One GATE High AND ACL2 On AND (the Other GATE High OR Configurable: in ACL)] (1) VOUT Low ACL1 On DRAIN < (2) GATE1 Off VD,PG(TH) AND (Except OV) VOUT High AND (Both GATE1 GATE1 Turns AND GATE2 On First. High) GATE2 Turns On after Start-Up: ACL1 DRAIN < GATE1 High VD,PG(TH) AND On; Running: and DRAIN VOUT High AND Both ACL1 Low AND ACL2 On [GATE1 High AND (GATE2 High OR in ACL)] CBTMR Reaches 2.048V OR Upon Other GATE-Off Faults GATE1 Off FET_ON High AND [DRAIN > VD,FET(TH) OR (Both GATE1 AND GATE2 Low) OR (One Gate Low AND Not in ACL)] GATE1 Off OR DRAIN > VD,PG(TH) OR GATE1 Low OR ACL1 On FET_ON High AND [DRAIN > VD,FET(TH) OR (GATE1 OR GATE2 Low)] GATE1 Off FET_ON High AND [DRAIN > VD,FET(TH) OR (Both GATE1 AND GATE2 Low) OR (One Gate Low AND Not in ACL)] * VOUT High is equivalent to VRTNS - VDRNS > VOUTTH. ACL1: Active current limit circuit associated with GATE1; ACL2: Active current limit circuit associated with GATE2. be carried by a single MOSFET. For this reason, although the overall RDS(ON) can be effectively lowered when a group of MOSFETs are operated in parallel by a single gate driver, they only provide the SOA of a single MOSFET. The LTC4284 resolves this problem by offering two gate drivers, each with an independent current limit circuit and associated current sense pins. When connecting MODE to VEE, these two gate drivers operate in the parallel mode, in which GATE1 and GATE2 are turned on or off simultaneously. In this mode the LTC4284 allows a group of parallel MOSFETs to be divided into two channels. During current limiting in an overcurrent event such as output short or input step, the independent gate control of the two channels divides the current evenly between them, resulting in twice the SOA performance of the hot swap controller with a single current limit circuit. This allows the use of smaller and less expensive MOSFETs, can start up a load twice as big, or increases SOA margins. Figure1 and Figure2 show 1.2kW application examples operating in the parallel mode. Two MOSFETs in each channel are used so that the power dissipation in each MOSFET when fully enhanced is 1W or less. In the parallel mode, one GATE may be fully enhanced and the other may be in current limit. This is considered a normal operating condition because the VDS of both MOSFETs is small. Hence in this condition if VDRAIN < VD,PG(TH) and VRTNS - VDRNS > VOUTTH, the power good signals will be asserted. Furthermore, this condition does not set the FET_BAD_STATUS bit in FAULT_STATUS register 0x03. The FET_BAD_STATUS bit will be set and the FET bad fault timer will be started if both GATE1 and GATE2 are low or one GATE is low but not in current limit. See FET Bad Fault and Auto-Retry for details. During startup, either GATE1 or GATE2 in current limit activates TMR pull-up current. In normal operation (internal power good signal latched), the TMR pull-up current will not be activated unless both GATE1 and GATE2 are in current limit. If an RC network is connected to TMR, Rev. A For more information www.analog.com 31 LTC4284 APPLICATIONS INFORMATION the RC network should represent the thermal behavior of a single MOSFET, since the TMR pull-up current is only related to power dissipation in the channel 1 MOSFET. When TMR reaches 2.048V (representing the maximum allowable temperature rise in the MOSFET), both GATE1 and GATE2 are turned off and an overcurrent fault is logged in FAULT register 0x04. overstresses and GATE2 drives less expensive bypass MOSFETs (M2A and M2B) with low RDS(ON) (their SOAs are usually low, too) to carry the load, as shown inFigure10. Similar to the parallel mode, the high stress staged start mode also works well for systems where large input steps or supply surges are inevitable. M1 must be selected with large enough SOA to withstand these conditions, in which M1 not only carries the full load current, but also needs to deliver the capacitive current to charge up the load. See Input Step and Optimum Output Ramp for details. If the dV/dt inrush control is enabled by setting the DVDT bit in CONTROL_1 register 0x0A, the inrush current during startup may not be evenly distributed between the two channels due to MOSFET threshold mismatch. Therefore, a proper RAMP capacitor must be selected so that the inrush current is lower than the startup current limit of each channel, not the sum of the two channels. At power-up, GATE1 is turned on first to charge the load and GATE2 is held off. The startup inrush control can be configured into either current limit mode or dV/ dt mode using the DVDT bit in CONTROL_1 register 0x0A. If dV/dt mode is selected, the inrush current must be limited substantially lower than the startup current limit. As illustrated in Figure11, when GATE1 is fully enhanced (VGATE1>VGATE(TH)) and the load capacitor is fully charged (VDRAIN<2.048), GATE2 is turned on. High Stress Staged Start Mode (Mode 3) The two GATE drivers of the LTC4284 can also be configured to operate in high stress staged start mode by connecting MODE to VIN. In this mode GATE1 drives a high SOA MOSFET (M1) for startup and to withstand -48V RTN CVCC 1F -48V RTN (SHORT PIN) VEE R3 487k 1% R2 14.3k 1% UVH UVL UV = 38.6V UV RELEASE AT 43.1V OV = 71.9V OV RELEASE AT 70.7V VEE INTVCC R1 10k 1% -48V INPUT RE3 1.13M 1% RE2 30.1k 1% CE3 150nF VIN MODE ADIO1-4 PGIO1-4 EN# VEE VEE + VLOAD 4 CL 2000F 4 4 DRNS SENSE2- ADC- SENSE1- SENSE1+ ADC+ SENSE2+ CE1 3.3nF VEE DVDT = 1 THERM_TMR = 1 ILIM = 1010 FB = 11 FB_DIS = 1 LPFB = 1 ALERT# ADIN1-4 LTC4284 VEE BATTERY OPERATED (SUBJECT TO -36V INPUT STEPS) RRB 5.11k 1% RAMP RTNS TMR RE1 4.02k 1% CE2 15nF VZ RRT 200k 1% CR 68nF SCL SDAI SDAO OV CUV 100nF RIN 4 x 1k IN SERIES 0.25W EACH VEE CIN 0.1F RS1 0.25m 8 x 2m GATE1 RG1 CG1 2k 100nF GATE2 DRAIN RG1A 10 RDT 200k 1% RD 100k RDB 5.11k 1% VEE VOUT M1 IXTQ170N10P CG2 22nF - RG2A 10 RG2B 10 VEE M2A IPT020N10N3 M2B IPT020N10N3 4284 F10 Figure10. -48V/1800W Hot Swap Controller with SOA Timer and dV/dt Inrush Control in High Stress Staged Start Mode: GATE1 Drives High SOA MOSFET and GATE2 Drives Low RDS(ON) MOSFETs 32 Rev. A For more information www.analog.com LTC4284 APPLICATIONS INFORMATION After GATE2 is also fully enhanced (VGATE2 > VGATE(TH)), the internal power good signal is latched provided that VDRAIN < 2.048 and VRTNS - VDRNS > VOUTTH. After the power good delays expire, two sequential power good signals are asserted at PGIO1 and PGIO2 (with bits [3:0] in PGIO_CONFIG_1 register 0x10 cleared) and can be used to turn on the loads (see Figure5). The majority of the load current is delivered by M2A and M2B, which have much lower RDS(ON) than M1. In this mode the current sense resistor is connected between SENSE1+ and SENSE1- , while SENSE2+ and SENSE2- are shorted to SENSE1- to disable the current limit circuit of GATE2. When GATE1 is in current limit in overcurrent events such as an output short or an input step as shown in Figure12, the LTC4284 immediately switches off GATE2 to protect M2A and M2B from overstress, leaving the current limit of GATE1 to regulate the load current through M1. In this condition the TMR pull-up current is turned on. When the TMR voltage reaches 2.048V, GATE1 is turned off and an overcurrent fault islogged. -36V INPUT -72V MOSFET VDS INPUT UVLO AND UV CLEARED GATE1 The high stress staged start mode decouples SOA from RDS(ON). The MOSFET driven by GATE1 (M1) is selected so that its SOA is large enough to withstand stresses in all operating conditions. The RDS(ON) of M1 is not a major concern, but needs to satisfy VDRAIN < 2.048V when GATE2 is off, otherwise GATE2 will not be turned on. The MOSFETs driven by GATE2 (M2A and M2B) are selected so that when fully enhanced, the RDS(ON) is low enough to make the I2R power dissipation in M2A or M2B below or close to 1W. The SOA of M2A and M2B does not need to be large because GATE2 is switched off in any of the following fault conditions: GATE1 off, GATE1 in current limit, GATE1 low (VGATE1 < VGATE(TH)), or DRAIN high (VDRAIN > 2.048V). In this way the selection of MOSFET(s) for each channel is easier and the overall cost of MOSFETs may be lower than the parallel mode. 2.048V VIN VIN - 1.8V 128ms 36V GATE1 VIN - 1.8V GATE2 VIN VIN - 1.8V GATE2 MOSFET VDS VTH 0V ILIM = LOAD + INRUSH 2.048V M1 CURRENT CURRENT VIN - 1.8V MOSFET VTH LOAD LOAD INRUSH (LATCHED) INTERAL POWER GOOD LOAD M2A/M2B CURRENT 4284 F11 Figure11. Turn-On Sequence of High Stress Staged Start Mode LOAD 0A 4284 F12 Figure12. -36V to -72V Input Step Response in High Stress Staged Start Mode (Constant Power Load, LPFB = 1) Rev. A For more information www.analog.com 33 LTC4284 APPLICATIONS INFORMATION In the high stress staged start mode, either GATE1 low or GATE2 low sets the FET_BAD_STATUS bit in FAULT_ STATUS register 0x03 and starts the FET bad fault timer. When the timer expires the FET_BAD_FAULT bit in FAULT register 0x04 is set and both GATE1 and GATE2 are turned off if the FET_BAD_TURN_OFF bit in CONTROL_1 register 0x0A has been set. Low Stress Staged Start (Mode 4) The low stress staged start mode is well suited for applications with tightly regulated supply voltages. Since in such a system an input step is no longer a valid operating condition, the worst-case operating condition for the MOSFET SOA is charging up the load during startup. By suppressing the startup inrush current to a very low level, the SOA demand for the startup MOSFET is greatly alleviated. Additionally, the bypass path only needs inexpensive, switching regulator class MOSFETs. Therefore, this architecture minimizes the cost of MOSFETs to achieve a given load current and RDS(ON). However, with the brief timer delay for current limit, it has limited capability to ride through an input step or a sustained load surge in current limit, and due to the low startup current cannot start up a resistive load such as a heating element or incandescent lamp. Figure13 shows an application circuit for a 2.5kW system operating in the low stress staged start mode. This mode is enabled by connecting MODE to INTVCC. In this mode GATE1 drives a compact, inexpensive MOSFET (M1) with small SOA as a trickle charging device for startup. GATE2 drives parallel low RDS(ON), low SOA MOSFETs (M2A and M2B) with a high current limit configured using parallel small sense resistors to deliver the full load current. The turn-on sequence is exactly the same as in the high stress staged start mode as illustrated in Figure11: GATE1 turns on first to charge the load and GATE2 turns on after GATE1 is fully enhanced. -52V RTN -52V RTN (SHORT PIN) VEE R2 226k 1% VOUTTH UVH UVL R4 412k 1% R1 10k 1% -52V INPUT CVCC 1F RIN 4 x 1k IN SERIES 0.25W EACH CIN 0.1F RRT 316k 1% CR 470nF VEE VZ VIN RRB 10.2k 1% RAMP RTNS SCL SDAI SDAO ALERT# ADIN1-4 LTC4284 UV = 43.4V UV RELEASE AT 45.1V OV = 59.3V OV RELEASE AT 58.3V VOUT LOW = 44V 4 CL 2000F 4 4 DRNS SENSE1+ ADC+ SENSE2+ CT 2.2nF LINE OPERATED (INPUT STEPS LIMITED TO <5V) VLOAD PGIO1-4 EN# VEE SENSE2- ADC- SENSE1- + VEE ADIO1-4 TMR R3 10k 1% COV 10nF INTVCC MODE OV VEE DVDT = 1 THERM_TMR = 0 ILIM = 0011 FB = 10 FB_DIS = 0 LPFB = 0 R5 26.7k 1% VEE RH 750 1% CUV 10nF R6 10.2k 1% R CG1 G1 1k 10nF RS1 5m - GATE1 GATE2 DRAIN RG1A 10 RD 100k VEE + RA1 15 RA1 15 RA2- 1 RA2+ 1 RDB 10.2k 1% RG2 150 - VEE VOUT M1 PSMN7R6-100BSE RG2A 10 RG2B 10 CG2 220nF VEE RS2 0.33m 6 x 2m RDT 316k 1% M2A IPT020N10N3 M2B IPT020N10N3 4284 F13 Figure13. -52V/2500W Hot Swap Controller in Low Stress Staged Start Mode with dV/dt Inrush Control: GATE1 Drives Trickle Startup MOSFET and GATE2 Drives Low RDS(ON) MOSFETs, for Systems with Tightly Regulated Supply Voltages 34 Rev. A For more information www.analog.com LTC4284 APPLICATIONS INFORMATION GATE2 turns off only if GATE1 turns off, which is different from the high stress staged start mode where GATE2 turns off if GATE1 is in current limit. If an overcurrent event occurs, both GATE1 and GATE2 stay in current limit to share the stress (see Figure14). Hence the current sense pins for both current limit circuits on GATE1 and GATE2 must be connected to their corresponding senseresistors. In Figure13 M1 is configured to deliver a very low inrush current (0.34A) using a RAMP capacitor in the dV/dt startup mode. The current limit is set to 0.72A by the startup foldback ratio and a large sense resistor RS1. When the load is fully charged (VDRAIN < 2.048) and the startup MOSFET is fully enhanced (VGATE1 > VGATE(TH)), GATE2 is turned on. When M2A and M2B are fully enhanced (VGATE2 > VGATE(TH)), the power good signals are asserted. The condition to set the FET_BAD_STATUS bit in FAULT_ STATUS register 0x03 and starts the FET bad fault timer in this mode is the same as in the parallel mode (see Table1). Since the FET bad fault timer is running during the trickle startup while the load is slowly charged, the timer duration must be programmed long enough using 2.048V MOSFET VTH VIN MOSFET VTH M1 CURRENT ILIM1 ILIM2 M2A/M2B CURRENT LOAD 4284 F14 Figure14. Output-Short Protection in Low Stress Staged Start Mode The startup inrush control can also be configured to current limit by clearing the DVDT bit in CONTROL_1 register 0x0A. In this case the TMR pull-up current is enabled during startup and is adjusted according to the foldback ratio. An RC network that represents the electric model for the thermal behavior of M1 should be connected to TMR. Note that after startup when M2A and M2B are turned on, the TMR pull-up current still relates to the power dissipation in M1. M1 should be selected so that its SOA is worse than that of M2A or M2B. In this way M2A and M2B are automatically protected when M1 turns off upon TMR timeout in an overcurrent condition. The LTC4284 can also be configured into the single driver mode by floating the MODE pin. There are two possible architectures in this mode. Figure 15 shows the first architecture. GATE1 drives a single MOSFET or parallel MOSFETS so that the LTC4284 behaves the same as a single hot swap controller. GATE2 is left open and its current limit circuit is disabled by shorting the SENSE2+/ SENSE2- pins to VEE. VIN GATE2 During startup in dV/dt mode the TMR pull-up current is disabled. It will not be enabled unless M1 goes into current limit under a fault condition (e.g., start into shortcircuit). In normal operation after power good asserted, the TMR pull-up current is enabled when both M1 and M2A/M2B are in current limit. A single, small TMR capacitor as shown in Figure13 can be used to configure a brief circuit breaker delay, which should be within the worst SOA of M1 and M2A/M2B. Single Driver Mode (Mode 1) TMR GATE1 the FTBD_DL bits in CONFIG_2 register 0x0E to avoid turning off M1 too early. Figure 16 shows the second architecture, in which GATE1 and GATE2 are combined to drive a single channel of MOSFET(s). SENSE1+ and SENSE2+ are connected together to the positive side of a single current sense resistor and SENSE1- and SENSE2- are connected together to the negative side of the resistor. In this way the current limit circuits for both GATE1 and GATE2 are enabled so that the GATE pull-up and pull-down currents are doubled, achieving a faster turn-off in response to fault conditions. The single driver mode can be used in low to medium power applications where a second gate driver is not needed. Rev. A For more information www.analog.com 35 LTC4284 APPLICATIONS INFORMATION -48V RTN CVCC 1F -48V RTN (SHORT PIN) VEE R3 487k 1% UV = 38.6V R2 UV RELEASE AT 43.1V 14.3k OV = 71.9V 1% OV RELEASE AT 70.7V R1 10k 1% VEE INTVCC VZ VIN MODE RAMP + RRB 5.11k 1% RTNS VEE VLOAD SCL SDAI SDAO ALERT# ADIN1-4 LTC4284 4 4 PGIO1-4 SENSE2- ADC- SENSE1- SENSE1+ ADC+ SENSE2+ GATE1 GATE2 DRAIN DRNS CT 68nF R CG1 G1 1k 47nF RD 100k RG1A 10 VEE BATTERY OPERATED (SUBJECT TO -36V INPUT STEPS) CL 330F 4 ADIO1-4 TMR EN# VEE VEE -48V INPUT RRT 200k 1% CR 68nF VEE OV DVDT = 1 THERM_TMR = 0 ILIM = 0001 FB = 11 FB_DIS = 0 LPFB = 1 CUV 100nF UVH UVL RIN 4 x 1k IN SERIES 0.25W EACH CIN 0.1F RDB 5.11k 1% VOUT 4284 F15 M1 PSMN4R8-100BSE RS1 1m - VEE RDT 200k 1% Figure15. -48V/300W Hot Swap Controller in Single Driver Mode: GATE1 Drives MOSFET and GATE2 Is Open, with dV/dt Inrush Control -48V RTN CVCC 1F DVDT = 0 THERM_TMR = 1 ILIM = 0001 FB = 11 R3 487k FB_DIS = 0 1% LPFB = 1 -48V RTN (SHORT PIN) VEE UVH UVL UV = 38.6V R2 UV RELEASE AT 43.1V 14.3k OV = 71.9V 1% OV RELEASE AT 70.7V CUV 100nF R1 10k 1% RE1 1.13M 1% CE1 68nF RRT 200k 1% VEE INTVCC VZ VIN MODE RTNS VLOAD 4 ADIO1-4 4 PGIO1-4 GATE1 RG1 CG1 470 100nF VEE GATE2 RG1A 10 DRAIN DRNS RG1B 10 VEE RS1 0.5m CL 500F 4 ADIN1-4 CE2 4.7nF BATTERY OPERATED (SUBJECT TO -36V INPUT STEPS) VEE ALERT# LTC4284 SENSE2- ADC- SENSE1- SENSE1+ ADC+ SENSE2+ -48V INPUT + RRB 5.11k 1% SCL SDAI SDAO OV RAMP TMR EN# VEE RE2 18.2k 1% RIN 4 x 1k IN SERIES 0.25W EACH CIN 0.1F RD 100k RDB 5.11k 1% RDT 200k 1% M1A PSMN4R8-100BSE VEE 4284 F16 - VOUT M1B PSMN4R8-100BSE Figure16. -48V/600W Hot Swap Controller in Single Driver Mode: Both GATE1 and GATE2 Drive MOSFETs, with Current Limit Inrush Control and SOA Timer Overvoltage Fault and Auto-Retry The OV pin can be used to monitor a supply overvoltage condition using an external resistive divider. An overvoltage fault occurs when OV rises above its 1.406V threshold. 36 This condition turns off the MOSFETs immediately and sets the OV_STATUS bit in FAULT_STATUS register 0x03 and the OV_FAULT bit in FAULT register 0x04. Note that the power good signals are not affected by the overvoltage fault. If OV subsequently falls back below the threshold Rev. A For more information www.analog.com LTC4284 APPLICATIONS INFORMATION minus hysteresis of 24mV, the OV_STATUS bit is cleared and the MOSFETs will be allowed to turn on again (without delay) unless overvoltage auto-retry has been disabled by clearing the OV_RETRY bit in CONTROL_2 register 0x0B. -48V RTN R3 487k 1% RH 1k 1% Undervoltage Fault and Auto-Retry The LTC4284 features two undervoltage pins, UVH and UVL, for precise undervoltage monitoring and adjustable hysteresis. UVH has an accurate rising threshold: VUVL(TH) = 1.833V, UVL falling Both pins have a small built-in hysteresis, VUV (11mV typical). With either a rising or a falling input supply, the undervoltage comparator works in such a way that both UVH and the UVL have to cross their threshold for the comparator output to change state. The UVH, UVL and OV threshold ratio is designed to match the standard telecom operating range of 43V to 71V and UV hysteresis of 4.5V when UVH and UVL are connected together as in Figure1, where the UV hysteresis referred to UVL is: VUV(HYST) = VUVH(TH) - VUVL(TH) = 0.215V R3 487k 1% UVL TURN-ON = 44.9V TURN-OFF = 38.6V HYSTERESIS = 6.3V UVH RH 1k 1% R2 13.3k 1% UVH TURN-ON = 43.1V TURN-OFF = 40.2V HYSTERESIS = 2.9V UVL R2 13.3k 1% OV OV R1 10k 1% VUVH(TH) = 2.048V, UVH rising UVL has an accurate falling threshold: -48V RTN R1 10k 1% -48V INPUT -48V INPUT a) b) Figure17. Adjustment of Undervoltage Thresholds for Larger (17a) or Smaller (17b) Hysteresis In the latter case, the minimum UV hysteresis allowed is the built-in hysteresis of UVH and UVL: VUVL(HYST,MIN) = VUV = 11mV which occurs when RH reaches its maximum value: RH(MAX) = 0.11 * (R1 + R2) LTC4284 ensures that the UV comparator is immune to chattering even when RH is larger than RH(MAX). Using R1 = 10k, R2 = 14.3k and R3 = 487k as in Figure1 gives a typical operating range of 43.1V and 70.7V, with an undervoltage shutdown threshold of 38.6V and an overvoltage shutdown threshold of 71.9V. An undervoltage fault occurs when UVL falls below 1.833V and UVH falls below 2.048V - VUV. This condition turns off the MOSFETs and sets the UV_STATUS bit in FAULT_STATUS register 0x03 and the UV_FAULT bit in FAULT register 0x04. The UV hysteresis can be adjusted by separating UVH and UVL with a resistor RH as shown in Figure17. To increase the UV hysteresis, place the UVL tap above the UVH tap as in Figure17a. To reduce the UV hysteresis, place the UVL tap under the UVH tap as in Figure17b. UV hysteresis referred to UVL is given by: Following the undervoltage fault, the UV_STATUS bit is cleared when the UVH pin rises above 2.048V and UVL rises above 1.833V + VUV. After a delay of 128ms, the MOSFETs will be allowed to turn on again unless the undervoltage auto-retry has been disabled by clearing the UV_RETRY bit in CONTROL_2 register 0x0B. If VUVL VUVH, When power is applied to the device, if UVL is below the 1.833V threshold and UVH is below 2.048V - VUV after INTVCC crosses its undervoltage lockout threshold of 4V, an undervoltage fault will be logged in FAULT register 0x04 and can be cleared using the I2C interface after power-up. VUVL(HYST) = VUV(HYST) + 2.048V * RH R1+ R2 If VUVL < VUVH, VUVL(HYST) = VUV(HYST) - 2.048V * RH R1+ R2 + R H Rev. A For more information www.analog.com 37 LTC4284 APPLICATIONS INFORMATION Because of the compromises of selecting from a table of discrete resistor values (1% resistors in 2% increments, 0.1% resistors in 1% increments), best possible OV and UV accuracy is achieved using separate dividers for each pin, This increases the total number of resistors from three or four to as many as six, but maximizes accuracy, greatly simplifies calculations and facilitates running changes to accommodate multiple standards or customization without any board changes. To improve noise immunity, put the resistive divider to the UV and OV pins close to the chip and keep traces to RTN and VEE short. A 0.1F capacitor from UVH or UVL (and OV through resistor R2 as in Figure17) to VEE helps reject supply noise. FET Short Fault A FET short fault will be reported if the data converter measures a current sense voltage between ADC+ and ADC- greater than 255V while the MOSFETs are turned off. This condition sets the FET_SHORT_STATUS bit in FAULT_STATUS register 0x03 and the FET_SHORT_ FAULT bit in FAULT register 0x04. Power Failed Fault The LTC4284 continuously monitors the output voltage for the load. The differential voltage between RTNS and DRNS represents the attenuated output voltage for the load. An output low status will be reported if RTNS - DRNS is lower than the external reference voltage at VOUTTH. This condition sets the VOUT_LOW status bit in FAULT_STATUS register 0x03. If this condition occurs after the internal power good signal is latched, the POWER_FAILED fault bit in FAULT register 0x04 will also be set. This fault does not turn off the MOSFETs. After RTNS - DRNS rises above VOUTTH, the VOUT_LOW bit is cleared. External Fault and Auto-Retry PGIO4 can be configured as EXT_FAULT# or EXT_FAULT using PGIO_CONFIG_1 register 0x10 bits [7:6] to monitor an external fault condition. If the input polarity is configured as EXT_ FAULT#, an external fault occurs when PGIO4 falls below its 1.28V threshold. This condition sets the EXT_FAULT_STATUS bit in FAULT_STATUS 38 register 0x03 and the EXT_FAULT bit in FAULT register 0x04. This condition also turns off the MOSFETs if the EXTFLT_TURN_OFF bit in CONFIG_3 register 0x0F has been set. When PGIO4 subsequently rises above 1.28V, the EXT_FAULT_STATUS bit is cleared. After an auto-retry delay, the MOSFETs will be allowed to turn on again unless the external fault auto-retry has been disabled by clearing the EXT_FAULT_RETRY bit in CONTROL_2 register 0x0B. The auto-retry delay for the external fault is configurable from 512ms to 65.5s in binary scale using the COOLING_ DL bits in CONFIG_2 register 0x0E. During the delay the DELAY_STATUS bit in REBOOT register 0xA2 is set to 1. It will be cleared when the delay expires. In Figure18, PGIO4 is configured as EXT_FAULT and used to monitor MOSFET temperature. When the MOSFET temperature rises above 115C, the EXT_FAULT bit in FAULT register 0x04 is set and the MOSFET is turned off. If the EXTFLT_TURN_OFF bit in CONFIG_3 register 0x0F has been cleared, an external fault condition at PGIO4 will not turn off the MOSFETs. Regardless of the value of the EXTFLT_TURN_OFF bit, if the EXT_FAULT_ALERT bit in FAULT_ALERT register 0x15 is set, the high state of the EXT_FAULT bit in FAULT register 0x04 will generate an alert by pulling ALERT# low. PGIO1-4 and ADIO1-4, when configured as general purpose inputs, can be used to monitor external conditions without turning the MOSFETs off or generating alerts. If any of these pins is pulled above the 1.28V threshold, the associated input status bit in INPUT_STATUS register 0x02 is set. Cooling Delay The cooling delay (configurable by the COOLING_DL bits, 0x0E [3:1]) after an overcurrent fault, FET bad or external fault, will not be interrupted by any other fault. If, before expiration of the cooling delay, another overcurrent, FET bad or external fault occurs, the cooling delay will restart and extend the total cooling time. During the cooling delay the DELAY_STATUS bit 0xA2 [1] is set to indicate the delay timer is running. This bit resets when the delay expires. The cooling delay can be terminated by initiating an I2C reboot command, and is also terminated by UVLO (INTVCC < 3.8V). Rev. A For more information www.analog.com LTC4284 APPLICATIONS INFORMATION R1 13.7k 1% INTVCC PGIO4_CONFIG = 01b EXTFLT_TURN_OFF = 1 PGIO4 LTC4284 VEE C1 10nF *R TH PLACED NEAR MOSFET DRAIN RTH* TDK/EPCOS B59421A0115A062 470 at 25C 4.7k at 115C 4284 F18 Figure18. Use PGIO4/EXT_FAULT to Turn Off MOSFET when Drain Temperature Exceeds 115C Resetting Faults Faults are reset with any of the following conditions. First, writing zeros to FAULT register 0x04 will clear the associated fault bits. Second, the entire FAULT register is cleared when the ON bit in CONTROL_1 register 0x0A goes from high to low, or if INTVCC falls below its 3.8V undervoltage lockout. EN# falling from high to low also clears the entire FAULT register. Finally, when UVL is pulled below its 1.024V reset threshold, all fault bits in the FAULT register are cleared. When UVL is brought back above 1.024V but below 1.833V, the UV_FAULT bit is set if UVH is below 2.048V. This can be avoided by holding UVH above 2.048V while toggling UVL to reset faults. Fault bits with associated fault conditions that are still present (as indicated in FAULT_STATUS register 0x03) cannot be cleared. The FAULT register will not be cleared when auto-retrying. When auto-retry of a specific GATE turn-off fault is disabled using CONTROL_2 register 0x0B, the existence of the associated fault bit keeps the MOSFET off. After the fault bit is cleared and the associated retry delay expires, the MOSFETs are allowed to turn on again. If auto-retry of a fault is enabled, then a high state of the associated fault status bit in 0x03 will hold the MOSFETs off and the FAULT register is ignored. Subsequently, when the condition causing the fault is cleared (and so is the fault status bit in 0x03), the MOSFETs are allowed to turn on again. Alarms Besides the fault bits and the EN#_CHANGED bit, the LTC4284 also logs ADC alarms in ADC_ALARM_LOG registers 0x05-0x09 when ADC results are higher than the pre-configured MAX thresholds or lower than the pre-configured MIN thresholds. In addition, when the tick counter or energy meter overflows, the TICK_OVERFLOW bit or METER_OVERFLOW bit is logged into METER_ CONTROL register 0x84. Finally, when EEPROM is written through I2C, the EEPROM_WRITTEN bit is logged into ADC_ALARM_LOG register 0x05. Similar to the fault bits, these alarm bits indicate the history of corresponding conditions and do not reflect the present status of the conditions. Any alarm bit can only be reset by two methods: writing a zero to the alarm bit using I2C or bringing INTVCC below its undervoltage lockout voltage. EN# Pin EN# has a 1.28V logic threshold relative to VEE with a maximum leakage current of 1A at 3V. It must be pulled low and remain low during the 128ms debounce delay. When the delay expires, the MOSFETs are allowed to turnon. An internal clamp limits EN# to a minimum of 6V. The pin can be safely connected to higher voltages through a resistor that limits the current up to 5mA. It can be used to monitor board present as shown in Figure2. The EN# bit in SYSTEM_STATUS register 0x00 indicates the present state of EN#, and the EN#_CHANGED bit in ADC_ALARM_LOG_1 register 0x05 is set high whenever EN# changes state. The EN#_CHANGED bit can be cleared using the same methods as those for resetting faults (see Resetting Faults) except pulling EN# from high to low. Pulling EN# from high to low sets the EN#_CHANGED bit while clearing the entire FAULT register 0x04. ON Bit The ON bit in CONTROL_1 register 0x0A allows one to turn on (ON bit = 1) and turn off (ON bit = 0) the MOSFETs through the I2C interface. There is no debounce delay associated with this bit, so the MOSFETs are immediately turned on after the bit is flipped from 0 to 1 while all other turn-on conditions are met. When the ON bit is changed from 1 to 0, the MOSFETs are turned off and all bits in FAULT register 0x04 plus the EN#_CHANGED bit in ADC_ALARM_LOG_1 register 0x05 are cleared. Rev. A For more information www.analog.com 39 LTC4284 APPLICATIONS INFORMATION Turning the LTC4284 On and Off -48V RTN Many methods of on/off control are possible using the EN#, UV/OV, PGIO3 or PGIO4 pins along with the I2C port. EN# works well with logic inputs or floating switch contacts; I2C control is intended for systems where the board operates only under command of a central control processor and UV (UVH, UVL) and OV are useful with signals reference to RTN, as are PGIO3 and PGIO4 when configured as power good input and external fault, respectively. On/off control is possible with or without I2C intervention. Further, the LTC4284 may reside on either the removable board or on the backplane. Even when operating autonomously, the I2C port can still exercise control over the GATE outputs. UV, OV and other fault conditions seize control as needed to turn off the GATE outputs, regardless of the state of EN# or the I2C port. Figure19 shows three configurations of on/off control of the LTC4284. Note that the on/off control of GATE2 not only is commanded by the on/off state of GATE1, but also depends on the specific conditions in each operation mode as shown in Table1. Ejector Switch or Backplane Connection Sense with Insertion Debounce Delay. A high state of EN# turns the GATE outputs off. A low state of EN# turns the GATE outputs on with a debounce delay of 128ms. Figure19a shows an ejector switch or backplane connection driving EN# as an on/off control with extra insertion debounce delay through the RC constant. This circuit works in both backplane and board resident applications. Short Pin to RTN. Figure19b uses the UV divider string to detect board insertion. This method achieves an insertion debounce delay of 128ms and works equally well in both backplane and board resident applications. I2C Only Control. The circuit in Figure 19c locks out EN# and controls the GATE outputs with the ON bit in CONTROL_1 register 0x0A. To default on or off at powerup, program the corresponding EEPROM bit (bit[7] in EE_CONTROL_1 register 0xAA) to 1 or 0, respectively. Any of the PGIO1-PGIO4 or ADIO1-ADIO4 pins, when configured as general purpose input, can be used to 40 SHORT PIN OR SWITCH 1M INTVCC 100k LTC4284 EN# VEE 10nF -48V INPUT a) Contact Debounce Delay upon Insertion for Use with an Ejector Switch or Backplane Connection Sense -48V RTN 487k 24.3k UVL UVH LTC4284 EN# VEE -48V INPUT b) Short Pin Connection Sense to RTN 0xAA BIT[7] = 1/0 FOR DEFAULT ON/OFF EN# SDAO LTC4284 SDAI SCL VEE I2C -48V INPUT c) I2C Only Control Figure19. On/Off Control of the LTC4284 monitor a connection sense or other control signal. When the ON bit in CONTROL_1 register 0x0A changes from 0 to 1, the LTC4284 turns on the GATE outputs without a delay. The I2C port can also be used to write a fault bit in FAULT register 0x04 to turn off the GATE outputs if the corresponding fault has been configured to latch off the GATE output using CONTROL_2 register 0x0B. To turn the GATE outputs back on afterwards, clear the fault bit. The GATE outputs will be turned on after an auto-retry delay (except for OV). If a fault has been configured to auto-retry (in either finite or infinite times), setting the corresponding fault bit through I2C will not turn off the GATE outputs. Rev. A For more information www.analog.com LTC4284 APPLICATIONS INFORMATION Configuring PGIO and ADIO Pins The LTC4284 has four PGIO pins and four ADIO pins, all of which can be configured as general purpose inputs/ outputs using PGIO_CONFIG_1 register 0x10 and ADIO_ CONFIG register 0x12. Additionally, PGIO1 and PGIO2 can be configured as two sequential inverted or non-inverted power good signals, PGIO3 can be configured as inverted or non-inverted power good input signal (see Power Good Monitors and PGI Fault), and PGIO4 can be configured as inverted or non-inverted external fault (see External Fault and Auto-Retry). When configured as general purpose outputs, the output data for PGIO1-PGIO4 and ADIO1- ADIO4 are stored in bits[7:4] in PGIO_CONFIG_2 register 0x11 and bits[3:0] in ADC_CONFIG register 0x12, respectively. When selected, ADIO1-ADIO4 are also monitored by the on-board ADC (see Data Converters). If the PGIO2_ACLB bit in CONTROL_1 register 0x0A is set, PGIO2 is configured as an inverted indicator of active current limit after startup. During startup PGIO2 is held low. After the internal power good signal is latched, if the OC_STATUS bit in FAULT_STATUS register 0x03 is 0, PGIO2 goes high impedance. If the OC_STATUS bit is set to indicate that active current limit is engaged, PGIO2 is pulled low. Regardless of the configurations, PGIO1-PGIO4 and ADIO1-ADIO4 all have comparators monitoring the voltage on these pins with a threshold of 1.28V. The results are stored in INPUT_STATUS register 0x02. Design Examples The design flow starts with specifying the maximum load power and the operating voltage limits (line or battery operated). A line operated system usually has a tightly regulated supply voltage. A battery operated system usually has wide supply range and can experience large input steps when replacing a dropping-out battery with a newly charged one. An operation mode is then selected based on the following guideline. Single Driver Mode (Mode 1): <800W, line or battery operated. Parallel Mode (Mode 2): up to 1500W, line or battery operated. High Stress Staged Start Mode (Mode 3): >1500W, battery operated. Low Stress Staged Start Mode (Mode 4): >1500W, line operated. This is a rough guide and the boundaries between different modes may shift up or down depending upon the allowed budget of the MOSFETs. Example 1: Design Procedure of Parallel Mode with SOA Timer and Current Limit Startup Consider a battery operated system with maximum load power of 1200W, a supply voltage range of -36V to -72V (-36V to -72V input step is allowed), and a load capacitance of CL = 1000F as shown in Figure2. The parallel mode is chosen based on the above guideline. In the parallel mode, GATE1 and GATE2 drive two parallel channels of MOSFETs to charge the load capacitor simultaneously at startup, share the load current after startup, and turn off simultaneously upon a fault condition such as output overload or short-circuit. The maximum load current is calculated as IL(MAX) = PL(MAX) VS(MIN) = 1200W 36V = 33.3A Step 1. Configure current limit and select current sense resistors. Since a -36V to -72V input step is a valid operating condition, the current limit should be twice the maximum load current to minimize the temperature rise in the MOSFETs following a large input step: ILIM(OPT) = 2 IL(MAX) = 66.7A With a constant power load, when the load voltage ramps from 36V to 72V following the input step, the load current is halved. The LPFB (load power foldback) bit in CONFIG_1 register 0x0D is set to 1 so that the current limit will be maintained at approximately twice the load current during the output ramp. In parallel mode, the two channels share the current equally, so the maximum current each channel carries is I ICH(MAX) = LIM = 33.3A 2 Rev. A For more information www.analog.com 41 LTC4284 APPLICATIONS INFORMATION Sense resistors for each channel are selected assuming they will carry the maximum channel current, or 33.3A in this example. Selection is a matter of total cost, sense voltage (configurable from 15mV to 30mV in 1mV steps), allowable dissipation, availability of discrete resistance values, using multiple devices to reduce the sensing errors associated with high current density at the interface between the PCB and resistor, and using multiple devices to ballast current flow across a wide path, between 2 or more connectors, or between 2 or more MOSFETs. These factors are iterated until an acceptable solution is found. First, determine the number of resistors needed to handle the total sense power of each channel. Compute the total sense power starting with the minimum sense voltage or 15mV: PS(CH) = VSENSE(MIN) * ICH(MAX) = 15mV * 33.3A = 500mW Second, compute the number of resistors needed to handle this power. For example, 1206 resistors are rated for 250mW dissipation. A conservative design is half as much, or 125mW. NRS(CH) = PS(CH) 125mW = 500mW 125mW =4 Thus at least four parallel 1206 resistors are needed for each channel. Third, compute the resistance value: R S(CH) = VILIM(MIN) 15mV = =450 ICH(MAX) 33.3A Four resistors of 1.8m each would give the correct sense resistance. Fourth, use the closest next-larger available sense resistor value and adjust the sense voltage as needed to restore the current. In this case, a 2m sense resistor value is selected and the sense voltage is adjusted to 16mV. Recompute the numbers: R S(CH) = 2m ICH(MAX) = 4 = 500 16mV 500 = 32A The power dissipation of each resistor package is now 512mW/4 = 128mW. The total current limit is now 32A * 2 = 64A, close enough to the optimum value of 66.7A. The above process might be iterated for several combinations of different resistor counts, different package sizes, and even combinations of mixed resistor values. When a specific design is actually built, there can be small inaccuracies in the current sensing owing to contact and copper trace resistances. An immediate remedy without changing sense resistors is to readjust the sense voltage in 1mV steps. For instance, moving sense voltage from 16mV to 17mV gives a 6.25% increase in current. Step 2. Select resistive dividers for DRNS (drain sense), RTNS (RTN sense) and VOUTTH (output low threshold). DRNS and RTNS serve multiple purposes. First, they are the inputs to a differential amplifier that measures the attenuated load voltage for dV/dt control at startup (see Inrush Control). In the event of an output overload or short-circuit, the current limit foldback profile in normal operation depends upon the differential input between RTNS and DRNS that represents the output voltage across the load. The current limit starts to fold back when RTNS - DRNS drops below 0.9V and reaches the minimum when RTNS - DRNS drops to zero (see Current Limit Foldback). Additionally, in current limit the DRNS input monitors the MOSFET's VDS and uses this information to scale the TMR pull-up current accordingly. When not in current limit, DRNS monitors VDS and serves as one input to a multiplier which generates the TMR pull-up current. Finally, RTNS and DRNS also serve as inputs to the ADCs so that the input voltage and MOSFET drain voltage can be read remotely. RTNS and DRNS have a maximum useable input voltage of 2.8V, so resistive dividers are required. To select resistive dividers for RTNS and DRNS, compute the divider ratio r using the maximum supply voltage: r= VS(MAX) 1.8V = 72V 1.8V = 40 where 1.8V is the operating point of DRNS at which the TMR pull-up current is tested and specified. The resulting PS(CH) = 16mV * 32A = 512mW 42 Rev. A For more information www.analog.com LTC4284 APPLICATIONS INFORMATION ADC measurement full scale for input (at RTNS) and MOSFET drain (at DRNS) voltages is VFS(MEAS) = r * 2.048V = 40 * 2.048V = 81.92V which gives a LSB size of 20mV in 12-bit mode. If it was desired to measure gross overvoltage inputs, such as 100V, then a decision would have to be made to sacrifice control dynamic range in favor of ADC measurement range by using a higher divider ratio. An alternative approach is to use ADIN1-ADIN4 inputs for ADC measurements, leaving RTNS and DRNS for control purpose only. With 72V load voltage corresponding to RTNS - DRNS = 1.8V, in normal operation the current limit starts to fold back when load voltage drops below 36V (or RTNS - DRNS < 0.9V) in overload conditions. This means there is no foldback in normal operating input range between -36V and -72V, allowing the MOSFETs to pass the full load current. Standard values of 200k and 5.11k give a divider ratio of 40.1. DRNS and RTNS must use identical dividers. While the exact ratio is not important, matching between them is very important. For this reason, 1% resistor tolerance is the minimum requirement; 0.25% or 0.1% is better. VOUTTH pin sets the threshold of RTNS - DRNS that indicates the low limit of the output voltage to reset power good signals if the PWRGD_RESET_CNTRL bit in CONTROL_1 register 0x0A is set to 1. The low limit is set below the minimum input voltage, so 32V is selected in this example. With a divider ratio of 40 on DRNS and RTNS, the VOUTTH threshold is 32V/40 = 0.8V. This voltage may be realized with a resistive divider between INTVCC (5V) and VEE, or for a better tolerance, between VREF (1.024V) and VEE. For the latter case, a divider of 5.62k and 20k as shown in Figure2a results in 0.8V at VOUTTH. The source current of VREF is 40A, well within its specified limit of 200A. Step 3. Design the overcurrent timer behavior. The TMR pin can be configured into a SOA timer or a single capacitor circuit breaker timer. The SOA timer requires an RC network representing the MOSFET thermal model to be connected to TMR (see SOA Timer). At least two resistors and two capacitors are needed for minimum accuracy of the thermal behavior. More RC elements are desired for better accuracy. Thus the cost and board area are larger than the single-capacitor timer. The benefit of the SOA timer is that the TMR voltage represents the temperature rise of the MOSFET and its trip threshold represents the maximum allowable peak temperature of the MOSFET. With the SOA timer, selection of MOSFETs is much simpler: they just need to meet the worst-case operation requirements. In fault conditions such as output short, the SOA timer automatically protects the MOSFETs by turning them off once the maximum allowable peak temperature is reached (TMR tripped). With the single capacitor timer, the minimum capacitor must first be selected to keep the MOSFETs on during worst-case operating conditions, then the MOSFETs must be selected to withstand the worst-case SOA conditions during normal operating and fault conditions. The cost of MOSFETs selected based on the single capacitor timer for parallel mode or high stress staged start mode may be substantially higher than that using the SOA timer. It is recommended to use the SOA timer for high power applications using parallel mode or high stress staged start mode, especially for those with large input steps. Therefore, in this example the TMR pin is configured as an SOA timer by setting the THERM_TMR bit in CONTROL_1 register 0x0A to 1, which disables the internal TMR pull-down current. With the SOA timer protecting the MOSFETs, current limit foldback may be disabled after startup. This can be done by setting the FB_DIS bit in CONTROL_1 register 0x0A to 1. The foldback during startup is not affected by the FB_DIS bit. Step 4. Select the MOSFETs. With the SOA timer, two operating requirements must be met: (1) the RDS(ON) must be low enough to carry maximum load current; (2) the SOA must be sufficient to stand the worst-case operating condition. The selection for the RDS(ON) requirement is a combination of total MOSFET cost and maximum desired dissipation per package. For the maximum channel current of 32A, two 5m devices result in 1.28W per device. With air flow 1.28W dissipation is acceptable and a third device is unnecessary. The chosen MOSFETs are two PSMN4R8-100BSE devices (each RDS(ON) < 4.8m) for each channel. The components selected so far are shown in Figure1 and Figure2a. Rev. A For more information www.analog.com 43 LTC4284 APPLICATIONS INFORMATION The worst-case MOSFET drain voltage with full load is VD(ON),MAX = ICH(MAX) * R DS(ON),MAX 32A * 4.8m 2 2 = =76.8mV The DRAIN threshold VD,FET(TH) must be set higher than this number with sufficient margin to account for component inaccuracies and temperature coefficient. When the MOSFET drain voltage is higher than this threshold, two things will happen. First, the FET_BAD_STATUS bit in FAULT_STATUS register 0x03 will be set and the FET bad timer will be started. When the timer expires the FET_ BAD_FAULT bit in FAULT register 0x04 will be set and the MOSFETs will be turned off if the FET_BAD_TURN_OFF bit in CONTROL_1 register 0x0A has been set. Second, the TMR pull-up current will be enabled even if current limit is not engaged. This current is produced by an internal multiplier monitoring the power dissipation in channel 1. VD,FET(TH) has four discrete settings: 72mV, 102mV, 143mV and 203mV. In this example 143mV is selected by setting the VDTH bits in CONFIG_2 register 0x0E to 10b. A large input step is usually the worst-case operating condition for SOA. To verify the temperature rise of the MOSFET, it is necessary to run simulations in this condition. With the above selected components and configurations, the temperature rise of the MOSFET when riding through a -36V to -72V input step with full load (1200W and 1000F) is 46C (simulated with the LTspice SOAtherm model). At worst-case operating temperature of 85C, this translates to 131C in the MOSFET, which has substantial margin from the manufacturer specified maximum temperature of 175C. With a load capacitance of 2000F, the temperature rise during the -36V to -72V input step increases to 64C, still an acceptable figure. Step 5. Design the startup current and FET bad timer. First the startup mode is selected. As pointed out in Inrush Control, the startup current (or inrush current) can be controlled either by a RAMP capacitor in dV/dt mode or by startup foldback in current limit mode. The current limit mode is selected in this example based on two considerations. First, in the parallel mode, both channels charge the load capacitance during startup. Current limit 44 will equalize the charging currents between the two channels. In the dV/dt mode, the charging current may concentrate on one channel due to MOSFET threshold mismatch. Second, the current limit mode is a better choice to work with the SOA timer that has been selected in Step 3. This is because if the dV/dt mode was selected, the TMR pullup current would be disabled in normal startup conditions and the SOA timer would not be able to track the temperature rise of the MOSFET during startup. Choice of the charging current is a trade-off between maximum charging time, maximum inrush current drawn from the backplane, and more importantly, peak power dissipated in the MOSFETs. When charging a capacitor from a voltage source, the charging process dissipates an energy in the pass MOSFET equal to the energy stored in the capacitor. The maximum input voltage results in the maximum energy: E MAX = CL * VS(MAX)2 2 = 1000F * (72V)2 2 = 2.59J This indirectly sets a limit on how quickly the load capacitor can be charged, since the average power dissipation in the MOSFETs is energy/time. In general, the faster the charge rate, the higher the peak temperature. For this reason, it is a good idea to lower the inrush current to no more than necessary to achieve the required startup time. Therefore, the smallest foldback ratio, 10%, is selected by setting the FB bits in CONFIG_1 register 0x0D to 11b, and the startup inrush current is IINRUSH = ILIM * FB = 64A * 10% = 6.4A The maximum startup charging time of the load capacitor is then computed: t STARTUP(MAX) = 1000F * 72V 6.4A CL * VS(MAX) IINRUSH = = 11.25ms This charging time is short enough for most applications. Simulation shows the temperature rise of the MOSFET in this worst-case startup condition is 40C, lower than that for the -36V to -72V input step calculated in Step 4. Rev. A For more information www.analog.com LTC4284 APPLICATIONS INFORMATION During startup the FET_BAD_STATUS bit is high and the FET bad timer is running and serves as a watchdog over the controlled startup. The load capacitor must be fully charged before this timer expires, or the GATE outputs will be turned off if the FET_BAD_TURN_OFF bit in CONTROL_1 register 0x0A has been set. There is no concern with this example since the maximum charging time of 11.25ms is much shorter than the minimum FET bad timer delay (256ms). Step 6. Select the RC network for the SOA timer following the procedure as shown in the SOA Timer section. It was found that two thermal capacitors and two thermal resistors provide fairly good curve fitting for the thermal impedance plot of the chosen MOSFET, PSMN4R8100BSE in the range between 100s and 100ms (wide enough for typical operating conditions of this application): C1 = 0.002J/C, R1 = 0.05C/W, C2 = 0.03J/C, R2 = 0.35C/W. The conversion constant is given by k= VDS,MAX *ID,MAX VTMR(TH) * = ITMR(UP),MAX TMAX 2 72V * 32A 2.048V 5V * = 3.6 *10 65C 202A C where TMAX is the maximum allowable temperature rise and chosen to be 65C, which corresponds to a maximum MOSFET temperature of 150C at an operating temperature of 85C, with 25C margin from the manufacturer specified maximum temperature of 175C. The thermal R and C values are then converted to electric R and C values as shown in SOA Timer. After the electrical R and C values are computed, choose the closest next-larger available resistor value and the closest next-smaller available capacitor value. Then the resistance corresponding to the thermal resistance of the board is added to the termination resistance (the largest one). If the computed resistance for the board thermal resistance is over 1M, choose 1M. Assuming a 5C/W board thermal resistance in this application, it is converted to 5 * 3.6 * 105=1.8M. So 1M is selected. This avoids accuracy degradation due to board leakage currents. The resulting electrical capacitors and resistors are CE1 = 4.7nF, RE1 = 18.2k, CE2 = 68nF, RE2 = 1.13M, as shown in Figure1 and Figure2a. After the SOA timer is configured, rerun simulations to ensure TMR does not reach its 2.048V trip point in all operating conditions including startup and input step. When it trips in fault conditions such as output overload or short-circuit, verify the peak temperature of the MOSFET matches the proposed maximum temperature. Iterations of the above procedure may be needed before the RC network is finalized. Step 7. Select resistive dividers for UV/OV inputs and ADC averaging resistors Select resistive dividers so that UV rising threshold is set just below the minimum input voltage and OV falling threshold is set just above the maximum input voltage. A single, 4-resistor divider as shown in Figure2a gives UV shutdown at 32.4V, UV release at 35.3V, OV shutdown at 74.5V and OV release at 73.2V. This configured range is just wide enough to cover the full input voltage range between 36V to 72V. A 100nF bypass capacitor is selected to filter out noises at UVL/UVH and OV. Four 1 averaging resistors are chosen for the ADC+ and ADC- inputs to measure the average current between the two channels. The current ADC has a full scale of 32.768mV. The total sense resistance is 0.25m, giving a full-scale current of 131.1A, with a 32mA LSB size in 12-bit mode. Example 2: Design Procedure of Low Stress Staged Start Mode with Single Capacitor on TMR Pin and dV/ dt Startup The second example is a line operated -52V system with supply tolerance of 10% (-46.8V to -57.2V) and maximum load power of 2500W as shown in Figure13. The load capacitance is specified as CL = 2000F. The low stress staged start mode is chosen for this example since the power exceeds 1500W and the supply is line regulated, without the concern about a large input step. The low pass staged start mode features a small startup MOSFET, driven by GATE1 (channel 1) and designed to carry a low startup inrush current to charge the load capacitor. After successful startup, low resistance bypass MOSFETs are driven by GATE2 (channel 2) to supply the load current. The current in channel 1 is usually only a small fraction of Rev. A For more information www.analog.com 45 LTC4284 APPLICATIONS INFORMATION the maximum load current, such as 10% or less. For this reason, its current contribution during normal operation can be ignored for the first phase of the design. Later channel 1 can be accounted for or sized to make up for any shortfall in the high current (channel 2) path, so that full power (2500W) can be supplied at minimum input voltage (46.8V). The maximum load current is calculated as IL(MAX) = PL(MAX) VS(MIN) = 2500W 46.8V = 53.4A With full load the worst-case drain voltage of the MOSFET is 53.4A * 1m = 53.4mV. Select 102mV as the DRAIN threshold for starting FET bad timer and enabling TMR pull-up current, with sufficient margin to account for inaccuracies. Set the VDTH bits in CONFIG_2 register 0x0E to 01b for this configuration. See detailed design considerations in Example 1, Step 4. Step 2. Configure current limit and select current sense resistors. Since the input voltage is well regulated, there is no need to set the current limit to twice the load current to minimize temperature rise upon a large input step as in Example 1. The current limit in this example just needs to cover the maximum load current, with enough margin to account for device tolerances. Select sense resistors for channel 2 (bypass channel) first assuming it carries the maximum load current, then add a small current carried by the startup channel for the margin. Compute the sense power of channel 2 starting with the minimum sense voltage or 15mV: PS2 = VILIM(MIN) * IL(MAX) = 15mV * 53.4A = 801mW NRS2 = PS2 125mW = 801mW 125mW = 6.4 Thus at least 6 parallel 1206 resistors are needed for channel 2. The resistance of channel 2 is Step 1. Select sufficient bypass MOSFETs to carry the maximum load current. The decision is a combination of total MOSFET cost and maximum desired dissipation per package. For the maximum channel current of 53.4A, two IPT020N10N3 (RDS(ON) < 2m) devices result in 1.415W per package, an acceptable dissipation with air flow. As an option, the IPT015N10N5 (RDS(ON) < 1.5m could be used, dissipating just 1.06W per package, at a slightly higher cost. 46 With 250mW rated 1206 resistors, use 125mW for conservative design and the minimum number of sense resistors to handle the power is R S2 = VILIM(MIN) IL(MAX) = 15mV 53.4A = 281 Six resistors of 1.69m each would give the correct sense resistance. The closest next-larger available sense resistor value is 2m: R S2 = 2m 6 =333 Adjust the sense voltage to 18mV to restore the current: V 18mV ILIM2 = ILIM = = 54A 333 R S2 and recompute the sense power: PS2 =18mV * 54A = 972mW The power dissipation of each resistor package is now 972mW/6 = 162mW, still an acceptable value for 1206 resistors. As a last step, a 5m sense resistor is chosen for a channel 1 current of V 18mV ILIM1 = ILIM = = 3.6A 5m R S1 so that the total current limit is ILIM = ILIM1 + ILIM2 = 54A + 3.6A = 57.6A Taking all tolerances into account, this provides sufficient margin for the maximum load current of 53.4A. Sense voltage may need to be readjusted to account for current sensing inaccuracies such as contact and copper trace resistances, as explained in Example 1, Step 1. Step 3. Select resistive dividers for DRNS (drain sense), RTNS (RTN sense) and VOUTTH (output low reference). Rev. A For more information www.analog.com LTC4284 APPLICATIONS INFORMATION See Example 1, Step 2 for detailed design considerations. First compute the divider ratio r for RTNS and DRNS: r= VS(MAX) 1.8V = 57.2V 1.8V = 31.78 which is rounded to 32. Standard values of 316k and 10.2k give a divider ratio of 31.98. The ADC measurement full-scale for input (at RTNS) and MOSFET drain (at DRNS) voltages is VFS(MEAS) = r * 2.048V = 32 * 2.048V = 65.5V which gives a LSB size of 16mV in 12-bit mode. With VLOAD = 32 * 1.8V = 57.6V corresponding to RTNS-DRNS=1.8V, the current limit starts to fold back when VLOAD drops below 28.8V in overload conditions. There is no foldback at normal input between -46.8V and -57.2V, allowing the MOSFETs to pass the full load current. If 44V is chosen as the output voltage threshold to reset power good signals, with a divider ratio of 32 on DRNS and RTNS, the VOUTTH threshold is 44V/32 = 1.375V. This voltage can be obtained with a resistive divider between INTVCC (5V) and VEE. The divider ratio is 5V/1.375V = 3.64. A divider of 26.7k and 10.2k as shown Figure13 gives a close enough ratio of 3.62. Step 4. Design the TMR behavior. See Example 1, Step 3 for general design considerations. Since the inrush current in the low stress staged start mode is at such a low level that the temperature rise of the startup MOSFET is insignificant, there is no need to use an SOA timer for MOSFET protection during startup. After startup there is no concern about a large input step, thus a very short timer delay is needed for MOSFET turn-off upon a fault such as output short-circuit. Therefore, in the low stress staged start mode the TMR function is essentially a filtered circuit breaker and a single timer capacitor on TMR works just fine for this purpose. Channel 2 dictates the timer capacitor selection since it carries most of the load current. All of the channel 2 current could be concentrated into a single MOSFET. The current limit of channel 2 is 54A in this example, and the MOSFET chosen in Step 1 (IPT020N10N3) can handle 60V and 60A for 100s. It has been found that 20s of circuit breaker filtering is sufficient to reject noise encountered in most systems, so the chosen MOSFET is up to the task. The TMR pull-up current is 202A at maximum overload, with a voltage threshold of 2.048V. Compute the timer capacitance, Ct, for 20s filter delay: Ct= ITMR(UP),MAX * t FILTER VTMR(TH) = 202A * 20s 2.048V =2nF Select the closest next-larger available capacitance: Ct = 2.2nF. With single capacitor on TMR, the THERM_ TMR bit in CONTROL_1 register 0x0A must be cleared to enable the internal 2A pull down current. Additionally, the FB_DIS bit in CONTROL_1 register 0x0A should be cleared to keep foldback enabled after startup to protect MOSFETs from damage upon a low impedance short-circuit. Step 5. Design the startup channel (channel 1) and FET bad timer. At startup in low stress staged start mode, channel 1 charges the load capacitance with a small trickle current. This is a good case to use the dV/dt startup mode (see discussions in Example 1, Step 5). The design procedure involves selecting a RAMP capacitor to set the dV/ dt rate for desired charging current, selecting a proper startup current limit and checking the temperature rise of the startup MOSFET under a resistive short condition. Choice of the charging current is a trade-off between maximum charging time and peak temperature of the startup MOSFET. As discussed in Example 1, Step 5, the charging current should be set to a low level that is just necessary to achieve the required charging time. Suppose an upper limit of 500ms charging time is desired for a 2000F load capacitor at the maximum input of 57.2V. The necessary charging current is IINRUSH(MIN) = CL * VS(MAX) t STARTUP(MAX) = 2000F * 57.2V 500ms = 229mA The RAMP capacitor is selected according to CR = IRAMP * r * CL IINRUSH = 2.5A * 32 * 2000F 229mA = 699nF Rev. A For more information www.analog.com 47 LTC4284 APPLICATIONS INFORMATION An acceptable value is 470nF, resulting in a nominal inrush of C 2000F IINRUSH =IRAMP * r * L =2.5A * 32 * =340mA CR 470nF and a maximum startup time of t STARTUP(MAX) = CL * VS(MAX) IINRUSH = 2000F * 57.2V 340mA = 336ms which is well below the upper limit of 500ms. The FET bad timer must be set longer than the startup time for the load capacitor to be fully charged, so it is configured to 512ms by setting the FTBD_DL bits in CONFIG_2 register 0x0E to 01b. The startup current limit should also be configured to a low level to minimize the temperature rise of the startup MOSFET under a resistive short condition, but must be higher than the dV/dt inrush current to avoid current limit being triggered in normal startup conditions. With a foldback ratio of 20%, the startup current limit of channel 1 is ILIM1(STARTUP) = 3.6A * 20% = 720mA which is more than twice of the inrush current of 340mA, with substantial margin to account for all inaccuracies. Select the 20% foldback ratio by setting the FB bits in CONFIG_1 register 0x0D to 10b. A 10% foldback ratio would result in 360mA current limit, too close to the inrush current. Since the inrush current is very low, RDS(ON) and SOA of the startup MOSFET are not critical, and a small, low cost device may be used. PSMN7R6-100BSE, with RDS(ON) < 7.6m, is selected as the startup MOSFET. After startup with 3.6A current limit, the worst-case power dissipation in this channel is (3.6A)2 * 7.6m = 98.5mW, a very low figure that has no concern. Step 6. Run simulations to verify temperature rises in both the channel 1 and channel 2 MOSFETs under all operating and fault conditions are within the acceptable range. This is a necessary step when using a single capacitor circuit breaker timer as selected in Step 4. 48 First, check temperature rise in channel 1 MOSFET (M1) during startup. The conditions include normal dV/dt startup to fully charge the 2000F load capacitor and a fault condition in which M1 charges both the load capacitor and a parallel fault resistor, both at the maximum input voltage. If temperature rise is too high in normal startup condition, the inrush current may be reduced by selecting a larger RAMP capacitor. If the inrush current must be reduced less than the value required to achieve the desired maximum charging time, a larger MOSFET has to be selected for channel 1. For the fault condition, the worst-case is found iteratively by changing the fault resistor value while monitoring the temperature rise. As a starting point, use a resistor of VS(MAX)/(4 * ILIM1(STARTUP)) or 57.2/(4 * 0.72) = 20 for this example. If the temperature rise is too high, startup current limit may be reduced by selecting a steeper foldback ratio or a larger sense resistor RS1. If the startup current limit must be reduced to less than or close to the dV/dt inrush required for the maximum charging time, a larger MOSFET must be selected. Using the conditions of this example, it is found the worstcase temperature rise in M1 either in normal startup condition or with different fault resistors is lower than 10C, an insignificant figure. This verifies the selected channel 1 MOSFET, PSMN7R6-100BSE, has more than enough SOA to handle the worst-case dissipation during startup. Second, check temperature rises in both channel 1 and channel 2 MOSFETs after startup when TMR times out under different overload conditions. The worst-case could be shorting the output to half of the available output voltage so there is no foldback while the VDS of the MOSFETs is still high. If the worst-case temperature rise in any channel is too high, larger MOSFET(s) must be selected for that channel. In this example, the worst-case temperature rise in channel 2 is an acceptable value of about 56C and that in channel 1 is insignificant (<10C). Step 7. Select resistive dividers for UV/OV inputs and ADC averaging resistors Although it is possible to use a single, four-resistor (or three-resistor if UVH and UVL connected together) divider as shown in Example 1, Step 7, two independent dividers Rev. A For more information www.analog.com LTC4284 APPLICATIONS INFORMATION with 2 (OV) or 2 to 3 (UV) resistors in each divider make it easier to make non-interactive changes at a later time. The two dividers as shown in Figure13 gives UV shutdown at 43.4V, UV release at 45.1V, OV shutdown at 59.3V and OV release at 58.3V, which covers the full input voltage range of this example. 10nF capacitors filter out noises on UVL and OV. TO SENSE1+ OR SENSE2+ PIN LTC4284 VEE PIN ALL CAPACITORS ALL RESISTIVE DIVIDERS ALL OPTO-ISOLATORS I2C COMMON MOSFET G D For ADC+ and ADC- inputs, 1 is chosen for the averag- ing resistor on the RS2 side (RA2). The averaging resistor on the RS1 side is determined by the ratio between RS1 and RS2: TO SENSE1- OR SENSE2- PIN VEE PLANE RS S 4248 F20 -48V INPUT PLANE TIE VEE TO -48V INPUT HERE Figure20. Layout Example of VEE Plane, -48V Input Plane and Sense Resistor Connection R 5m R A1 = R A2 * S1 = 1 * = 15 0.33m R S2 The current ADC has a full scale of 32.768mV. The total sense resistance is 5m in parallel with six 2m, or 0.312m. With a full scale of 32.768mV on the ADC+ - ADC- input, this gives a full-scale current of 104.9A and a LSB size of 25.6mA in 12-bit mode. Layout Considerations To achieve accurate current sensing, Kelvin connections are required. The minimum trace width for 1oz copper foil is 0.02" per amp to make sure the trace stays at a reasonable temperature. Using 0.03" per amp or wider is recommended. Note that 1oz copper exhibits a sheet resistance of about 530/square. Use 2oz or heavier copper for high current applications. The VEE pin of the LTC4284 should be connected to a separate plane from the main -48V input plane. To improve noise immunity, as shown in Figure20, the VEE connections of all capacitors, resistive dividers, opto-isolators and I2C common must be made directly to the local VEE plane, not the -48V input plane. The mechanical stress of soldering a part to a board and the heat of an IR reflow or convection soldering oven can cause the ADC full-scale error (FSE) and the current limit voltage (VILIM) to shift. Refer to Typical Performance Characteristics for ADC FSE and VILIM shifts of 300 units of LTC4284 after three cycles of the lead-free IR reflow process. Reboot on I2C Command The LTC4284 features a reboot command bit, RBT_EN in REBOOT register 0xA2. Setting this bit will cause the LTC4284 to shut down and reboot after a delay. The reboot delay is programmable from 512ms to 65.5s using the three RBT_DL bits in the REBOOT register. A reboot delay allows load capacitance to fully discharge. During the reboot delay the DELAY_STATUS bit in the REBOOT register is set to 1. It will be cleared when the delay expires. The reboot will also copy the contents of the EEPROM to volatile registers in the same way as after initial power-up. On systems where the hot swap controller supplies power to the I2C master, this allows the master to issue a command that power cycles the entire board, including itself. Once set, the RBT_EN bit remains 1 after reboot is completed. Clear it before issuing the next reboot command. Data Converters The LTC4284 incorporates a pair of Sigma-Delta A/D converters (ADCs) that are configurable from 8-bit at 1kHz conversion rate to 16-bit at 1Hz conversion rate in five settings using the ADC bits in PGIO_CONFIG_2 register 0x11 (see Table12). In the default continuous mode, the first ADC (ADC1) continuously monitors the input current through a sense resistor between ADC+ and ADC-. The second ADC (ADC2) is synchronized to ADC1 and Rev. A For more information www.analog.com 49 LTC4284 APPLICATIONS INFORMATION After each conversion of the two synchronized ADCs, the measured current sense voltage (ADC+ - ADC-) is multiplied by the measured VPWR(RTNS or DRNS) voltage to calculate input power or MOSFET power, configurable using the VPWR_SELECT bit in CONFIG_3 register 0x0F. All measured results and calculated power are stored to corresponding data registers (see Table3). They are also compared to the minimum and maximum values that are stored in the minimum and maximum data registers. If the measurement is a new minimum or maximum value, then the corresponding minimum or maximum data registers are updated. Note that all ADC data registers from 0x41 to 0x79 have a length of two bytes or 16 bits, and the data for all resolutions are left justified. monitors VPWR for power multiplication plus one of the sixteen auxiliary inputs. These inputs include 10 singleended signals and 6 differential signals and are selectable using ADC_SELECT registers 0x13-0x14 (see Table14). If multiple auxiliary inputs are selected, ADC2 will rotate between them in the continuous mode as illustrated in Figure21. The AUX_ADC_CH bits in ADC_STATUS register 0x01 are refreshed at the end of each conversion to indicate the auxiliary input that completed the latest measurement (see Table5). If all bits in ADC_SELECT registers 0x13-0x14 are cleared while the ADCs are running in continuous mode, ADC1 and ADC2 continue to measure ADC+ - ADC- and VPWR(RTNS/DRNS), respectively. The auxiliary measurements of ADC2 are disabled and the data in 0x41-0x79 from the previous measurement are preserved except 0x4A (ADIN1), which is overwritten by a small number. The ADC measurements are compared to the 8-bit minimum and maximum alarm thresholds that are configured using registers 0x1B through 0x40 and will set the corresponding ADC alarm bits in ADC_ALARM_LOG registers 0x05 to 0x09. If the associated ADC alert bit in ADC_ALERT registers 0x16 to 0x1A is set, an ADC alarm bit will generate an alert by pulling ALERT# low and set the ALERT_ GENERATED bit in METER_CONTROL register 0x84. The full-scale voltage of any single-ended input is 2.048V. For each differential input, one terminal must be at the same potential of VEE. Normally the negative terminal is at VEE and the full-scale is 32.768mV. If the positive terminal is at VEE, the full scale becomes 33.301mV. When using ADIN1-ADIN4 and ADIO1-ADIO4 as differential inputs, ADIN1, ADIN3, ADIO1 and ADIO3 must be the negative terminals, and ADIN2, ADIN4, ADIO2, ADIO4 must be positive terminals, respectively. Note that for each resolution setting, the resolution of differential auxiliary inputs of ADC2 is one bit less than that of the ADC+ - ADC- input of ADC1 or the single-ended inputs. ADC1 ADC1 ADC+ - ADC- ADC+ - ADC- * * * ADC2 * * * AUX1 AUX2 ADC1 ADC1 ADC+ - ADC- ADC+ - ADC- * * * ADC2 VPWR At the end of each ADC measurement, calculated power is added to an accumulator that meters energy. The 6-byte energy meter 0x7A to 0x7F is capable of accumulating 12 days of power at full scale in 12-bit ADC mode, which is several months at a nominal power level. When the meter overflows the METER_OVERFLOW bit in METER_ CONTROL register 0x84 is set to 1 and an optional alert is generated if the METER_OVERFLOW_ALERT bit in ADC2 * * * VPWR AUXN ADC2 VPWR AUX1 ROTATION SEQUENCE OF AUXILIARY INPUTS SELECTED BY ADC_SELECT REGISTERS 0x13-0x14 ADIN1-4 ADIO1-4 DRNS DRAIN SENSE1+ - SENSE1- SENSE2+ - SENSE2- * * * ADIN2 - ADIN1 ADIN4 - ADIN3 * * * VPWR TIME ADIO2 - ADIO1 ADIO4 - ADIO3 Figure21. LTC4284 ADC Measurement Pattern in Continuous Mode 50 Rev. A For more information www.analog.com LTC4284 APPLICATIONS INFORMATION CONFIG_3 register 0x0F is preset to 1. To measure coulombs, the energy meter may be configured to accumulate current rather than power by setting the INTEGRATE_I bit in CONFIG_3 register 0x0F. The tick counter 0x80 to 0x83 keeps track of how many times power has been added into the energy meter. Dividing the energy by the tick count will yield the average power over the accumulation interval. The 4-byte tick counter will keep count for 9 years in the 12-bit mode before overflowing. When it overflows the TICK_OVERFLOW bit in METER_CONTROL register 0x84 is set to 1 and an optional alert is generated if the TICK_OVERFLOW_ALERT bit in CONFIG_3 register 0x0F is preset to 1. Multiplying the value in the counter by the ADC conversion time yields the time that the energy meter has been accumulating. Both the energy accumulator and the tick counter are writable, allowing them to be preloaded with a given energy and/or time before overflow so that the LTC4284 will generate an overflow alert after either a specified amount of energy has been delivered or time has passed. where tCONV is the ADC conversion time depending upon the configured resolution (see Table12). To calculate coulombs: Q= CODE(48 Bits) * 32.768mV * t CONV 2 16 * R SENSE To calculate average power over the energy accumulation period: PAVG = E t CONV * CODE(COUNTER) To calculate average current: I AVG = Q t CONV * CODE(COUNTER) To calculate voltage alarm thresholds: VALARM = CODE(byte) * 2.048V 256 The following formulas are used to convert the values in the ADC data registers into physical units. Since the data are left justified, the same equations apply to all resolutions. To calculate current Alarm threshold in amperes: To calculate single-ended voltages measured by ADC2: To calculate power Alarm threshold in watts: V= CODE(word) * 2.048V 2 16 To calculate currents in amperes measured by ADC1 and differential mode ADC2: I= CODE(word) * 32.768mV 2 16 * R SENSE To calculate power in watts: P= CODE(word) * 32.768mV * 2.048V 2 16 * R SENSE To calculate energy in joules: E= CODE(48 Bits) * 32.768mV * 2.048V * t CONV 2 24 * R SENSE I ALARM = PALARM = CODE(byte) * 32.768mV 256 * R SENSE CODE(byte) * 32.768mV * 2.048V 256 * R SENSE To synchronize multiple bytes of data from the tick counter and energy meter, use the Read Page protocol (see Data Synchronization and Arbitration). An I2C read latches the tick counter and energy meter data in buffers while the tick counter and energy meter still increment. Alternatively one can set the METER_HALT bit in METER_CONTROL register 0x84 before reading the data. This will halt the ticker counter and energy meter. Clear the METER_HALT bit afterwards to reactivate incrementing. The LTC4284 ADCs also feature a snapshot mode that allows a one time measurement of a single data packet: ADC+ - ADC-, VPWR(RTNS or DRNS), and an auxiliary input selected by the SNAPSHOT_SEL bits in ADC_ SNAPSHOT register 0x85. To enable the snapshot mode, Rev. A For more information www.analog.com 51 LTC4284 APPLICATIONS INFORMATION set the ADC_HALT bit in the ADC_SNAPSHOT register to 1 and write the SNAPSHOT_SEL bits for the desired auxiliary input in one I2C command. At the falling edge of SCL after bit 0 is received, the ADCs start a single conversion of the selected data packet and the ADC_IDLE bit in ADC_STATUS register 0x01 is cleared to indicate the data is not ready. After completing the conversion, the ADCs are halted, the ADC_IDLE bit is set to indicate the data is ready, and the AUX_ADC_CH bits in the ADC_STATUS register are set to indicate the auxiliary input that is just measured. To make another snapshot measurement, write the ADC_SNAPSHOT register again. To go back to the continuous mode, clear the ADC_HALT bit. The ADC+ and ADC- inputs allow ADC1 to measure the average voltage across the two sense resistors using resistive dividers. In parallel mode (Figure1) or low stress staged start mode (Figure13), each channel has its own sense resistor connected between corresponding sense inputs. The averaging resistors should be selected with the same ratio as the sense resistors they connect to, which allows ADC1 to still measure current accurately. In the case as shown in Figure22, the effective ADC sense resistor is RS in parallel with k * RS. Scaling the averaging resistors, RA, by the same scaling factor, k, allows ADC1 to measure the correct sense voltage for this effective sense resistor. The smallest averaging resistor should not exceed 1. input is -36V (VINPUT1) and the other is -72V (VINPUT2). All node voltages are noted in the circuit. The voltage values in parenthesis are referred to system ground RTN and the others are referred to VEE. With the ADIO1-ADIO4 voltages measured by the ADC and R1/R2 = R3/R4 = R5/ R6 = R7/R8, the input voltages are VINPUT1 = (VADIO3 - VADIO1) k * RA VD2 = VREF R7 R8 - VADIO4 F3 71.3V F4 71.3V RTN_A RTN_B R1 1M 0.1% -48V INPUT SENSE2- R2 10k 0.1% k * RA R7 + R8 R8 D3 D4 R3 1M 0.1% RS -48V_A (-36V) SENSE2+ 4284 F22 Figure22. Weighted Averaging Sense Voltages The 16 auxiliary inputs with the LTC4284 ADCs allow for extensive monitoring of board level signals. Figure23 shows an example of using ADIO1-ADIO4 as single-ended inputs to monitor individual input voltages of a dual-feed system. The 1.024V VREF is exactly half of the ADC reference voltage and level shifts the ADIO1-ADIO4 inputs within measurable range of the ADC. In Figure23 one 52 R4 10k 0.1% 35.3V RA R2 VREF is ratiometric to the ADC full-scale voltage and can be measured by ADC with one of the ADIN1-ADIN4 pins to calibrate out errors. ADC+ RA R1+ R2 The forward voltage drop of the conducting diode D2 is SENSE1+ ADC- R2 VINPUT2 = (VADIO4 - VADIO2 ) F1 OPEN: VADIO3 = VREF F2 OPEN: VADIO4 = VREF F3 OPEN: VADIO1 = VREF F4 OPEN: VADIO2 = VREF 1.024V R6 10k 0.1% k * RS SENSE1- R1+ R2 -48V_B (-72V) F1 D1 F2 D2 R5 1M 0.1% R8 10k 0.1% 1.007V 1.363V 1.720V 1.720V R7 1M 0.1% R10 10k 0.1% VREF LTC4284 ADIN1 ADIO4 ADIO3 ADIO2 ADIO1 R9 1M 0.1% CHASSIS VEE -0.7V (-71.3V) 0 4284 F23 Figure23. Feed Voltage and Open Fuse Monitoring The circuit in Figure 23 also monitors fuses on both the RTN and -48V sides. If any one of the four fuses is open, it can be detected by the ADC measurement of the corresponding ADIO input: VADIO1 = VREF indicates fuse F3 is open; VADIO2 = VREF indicates fuse F4 is open; VADIO3=VREF indicates fuse F1 is open; VADIO4 = VREF Rev. A For more information www.analog.com LTC4284 APPLICATIONS INFORMATION indicates fuse F2 is open. Additionally, chassis ground is monitored with the ADIN1 pin as shown in Figure23. Figure24 shows an example that monitors both individual feed currents and individual channel currents using four differential input pairs. Note that the ADIN2 - ADIN1 and ADIN4 - ADIN3 inputs have a full scale of 33.301mV (positive terminals are at VEE), while the SENSE1+ - SENSE1- and SENSE2+ - SENSE2- inputs have a normal full scale of 32.768mV (negative terminals are at VEE). The output voltage across the load may be calculated from the measured RTNS and DRNS voltages. If a direct measurement of the load voltage is desired, the circuit as shown in Figure25 may be used. EEPROM The LTC4284 has an onboard EEPROM to allow nonvolatile configuration and fault logging. The EEPROM registers are denoted by EE_ in the first column of register Table3. The EEPROM registers may be read and written like any other register except that the EEPROM takes about 2.2ms to write data. While the EEPROM is writing, the EEPROM_BUSY bit in the SYSTEM_STATUS register is set. During this time, the I2C interface will NACK attempted writes to EEPROM registers. EEPROM registers will return 0xFF if read while the EEPROM is busy. The FAULT_LOG_CONTROL register is tied together with EEPROM and can't be written while EEPROM is busy. See the Fault Log section for more detail. Other registers may be accessed while EEPROM write is busy. When the EEPROM finishes writing, the EEPROM_ BUSY bit will be cleared and the EEPROM_WRITTEN bit in the ADC_ALARM_LOG_1 register will beset. If the corresponding EEPROM_WRITTEN_ALERT bit in register ADC_ALERT_1 is set, a rising edge on EEPROM_ WRITTEN will set ALERT_GENERATED in the METER_ CONTROL register. As a result, the ALERT# pin is pulled down. This will alert the host that the LTC4284 EEPROM is ready for more accesses. When the LTC4284 comes out of UVLO or receives a REBOOT command, the contents of the EEPROM are copied to the corresponding operating registers. This process takes about 1.3ms. During this time, the I2C bus is not available. Any command code received will be NACKed. Registers in the address range 0x0A through 0x40 correspond to EEPROM locations 0xAA through 0xE0. Register 0x90 corresponds to EEPROM location 0xF0. The seven EEPROM bytes in the EE_SCRATCH area are available for any general purpose use. EEPROM is also used to support the fault logging feature. See details in the Fault Log section. The WP pin prevents I2C writes to the EEPROM when high. Attempts to write to the EEPROM while WP is high will result in a NACK and no action. Fault log writes can take place with WP high, except when the LTC4284 is in single-wire broadcast mode. The EEPROM can be read regardless of the WP pin setting. The current WP pin status is available for reading at the WP_STATUS bit in the REBOOT register. Factory programmed parts may optionally have the EEPROM locked. In this case the WP pin has no impact. No EEPROM writes are possible. Fault logging is also disabled when the EEPROM is locked. Bit EE_LOCK in the METER_CONTROL register is a 1 when the EEPROM is locked. LTC4284 ADIN1 F1 D1 F2 D2 INPUT1 INPUT2 ADIN2 ADIN3 ADIN4 RF1 VEE SENSE1- SENSE1+ SENSE2- SENSE2+ GATE1 GATE2 RS1 M1 RF2 RS2 M2 4284 F24 Figure24. Individual Feed Current and Channel Current Monitoring Rev. A For more information www.analog.com 53 LTC4284 APPLICATIONS INFORMATION -48V RTN R1 100k R3 100k 2 x 2N5401 QP2 QP1 LTC4284 VEE ADIN1 SENSE1- SENSE1+ SENSE2- SENSE2+ GATE1 GATE2 R2 2.49k R4 2.49k RS1 -48V INPUT M1 RS2 4284 F25 M2 Figure25. Direct Monitoring of Load Voltage Using a Single ADC Input The FET_SHORT_FAULT and POWER_FAILED bits don't cause GATE1 and GATE2 to be pulled low, so they don't cause a fault log to be written. Also, the EN#_CHANGED bit doesn't cause a fault log to be written if it is set by the falling edge of EN#. In addition, fault log writing is disabled if the WP pin is high while the LTC4284 is in single-wire broadcast mode. Fault Log Writing Sequence. This sequence takes place in the LTC4284 in response to a condition that calls for a fault log write: 1. Freeze a shadow copy of fault bits (register 0x04 and bit [7] of 0x05). Fault Log 2. Block I2C access. The LTC4284's EEPROM supports a fault logging feature. Twelve bytes hold a log for a single fault event (Table22). In addition, a thirteenth byte provides an EEPROM backup copy for the fault log control register (FAULT_LOG_ CONTROL, register 0x90, see Table21). 3.Set FAULT_LOG_START in the FAULT_LOG_ CONTROL register. 4.Write FAULT_LOG_CONTROL to its backup copy in EEPROM. Writes to FAULT_LOG_CONTROL always cause a write to the EEPROM backup byte (EE_FAULT_LOG_CONTROL). This causes the EEPROM to go busy, disabling access to all EEPROM registers for about 2.2ms. During this time, FAULT_LOG_CONTROL can be read but not written. If another EEPROM register is written first, FAULT_LOG_ CONTROL can't be written until the busy condition clears. 5. Write the 12 bytes of fault information as detailed in Table22, fault bits come from the shadow copy. Conditions Leading to a Fault Log Write. A fault condition is defined as any condition in which a bit in the FAULT register (0x04) is set or the EN#_CHANGED bit is set in the ADC_ALARM_LOG_1 register (0x05). 9. Unfreeze the shadow copy of fault bits. A fault condition will result in a fault log being written if several conditions are met: 1. The fault condition causes GATE1 and GATE2 to be pulled low. 2.VIN is above the UVLO limit. 3. FAULT_LOG_ENABLE in the FAULT_LOG_CONTROL register (0x90) is set. 4. FAULT_LOG_UNLOCK, FAULT_LOG_START and FAULT_LOG_DONE in the FAULT_LOG_CONTROL register are all clear (this ensures any previous fault log has been completely serviced). 54 6.Set FAULT_LOG_DONE in FAULT_LOG_CONTROL. 7.Write FAULT_LOG_CONTROL to its backup copy in EEPROM. 8. Set alert if FAULT_LOG_ALERT is set. 10.Allow I2C access The I2C bus is blocked for about 31ms (14 time tWRITE). During this time, any incoming byte from I2C will be NACKed. If a fault log write starts in the middle of an I2C read, bytes of 0xFF will be returned to I2C in place of expected data. Resolving Fault Priority. When one fault bit is set, more bits will typically be set soon afterward. With too many bits set, the original cause of the problem is harder to determine. The LTC4284's fault logging logic is designed to capture the first fault indication and disregard subsequent fault bits set until after fault log writing finishes. The frozen copy of fault bits mentioned in the fault log writing sequence is part of this philosophy. As soon as Rev. A For more information www.analog.com LTC4284 APPLICATIONS INFORMATION the first fault bit is set which leads to GATE1 and GATE2 low, the frozen copy of fault bits is closed and remains closed until after logging is complete. In the fault log, fault data comes from the frozen copy. During this time, fault information is still accumulated in the main fault registers. Servicing a Fault Log. After one fault log has been written, further fault log writes will be disabled until the first fault log has been serviced. The FAULT_LOG_START and FAULT_LOG_DONE bits can't be set or cleared directly by I2C accesses. To prevent an accidental clearing of fault log information, a multibyte sequence is required to fully service one fault log so another fault log can be written. The sequence is: 1.Write FAULT_LOG_CONTROL with FAULT_LOG_ UNLOCK set 2. Write a second time with FAULT_LOG_UNLOCK set and all other bits clear. This write will clear FAULT_ LOG_START and FAULT_LOG_DONE. 3. Write again with FAULT_LOG_UNLOCK, FAULT_LOG_ START and FAULT_LOG_DONE all clear. At this time, the FAULT_LOG_ENABLE and FAULT_LOG_ALERT bits may be set as desired. Additionally, to avoid inadvertently overwriting the logged data through I2C, bring WP high during servicing. Incomplete Fault Logs. A fault condition is a likely precursor to an overall loss of power in the LTC4284. For accurate fault logging, the system design must provide sufficient external capacitance as described in Input Power Supply to hold INTVCC up during the time required to write 14 bytes to EEPROM. The fault log writing sequence described earlier provides a way to detect if the fault log doesn't complete successfully. The first EEPROM write saves FAULT_LOG_ CONTROL with the FAULT_LOG_START bit set. Then the final EEPROM write saves FAULT_LOG_CONTROL with both FAULT_LOG_START and FAULT_LOG_DONE bits set. After a loss of power, the FAULT_LOG_CONTROL register is loaded back from the saved EEPROM copy. If power was lost before a fault log completed, the FAULT_LOG_CONTROL register will have FAULT_LOG_ START set, but not FAULT_LOG_END. Also after a loss of power, if the FAULT_LOG_ALERT bit is set and FAULT_ LOG_START, FAULT_LOG_DONE or FAULT_LOG_ UNLOCK are set, the ALERT# pin will be pulled down to alert the system that an unserviced fault log remains in the chip. Digital Interface The LTC4284 communicates with a bus master using a serial 2-wire interface, compatible with both I2C and SMBus. The 2-wire interface is supplemented by an SMBus-compatible ALERT# output. The LTC4284 is always a bus slave and doesn't use clock stretching. Many LTC4284 applications require unidirectional isolators such as opto-couplers between the serial interface and the host system. For convenience of opto-coupling with the host, the SDA function is split into SDAI (input) and SDAO (output). For a conventional SDA line, tie SDAI and SDAO together. When using opto-couplers, connect the SDAI pin to the output of the incoming opto-coupler and connect the SDAO pin to the input of the outgoing opto-coupler (see Figure2b). If the ALERT# line is used, connect it in the same way as the SDAO pin as shown in Figure2b. Bus Compatibility The basic LTC4284 serial interface is compliant with I2C and SMBus AC and DC specifications. The timing is compatible with 400Kbit operation for both. This includes the SMBus legacy tHD:DATO timing of 300ns minimum. In addition, the LTC4284 supports 1Mbit operation which is compatible with I2C FastMode+ and SMBus 3.0. To use this timing, the FAST_I2C_EN bit in the CONFIG_3 register must be set. This bit may be set to 1 as default by EEPROM, or it can be manually written to 1. If the bit is 0 before writing, the write must be done at 400Kbit or less. With FAST_I2C_EN set, tHD:DATO is reduced to allow higher speed transfers. The LTC4284 SDAO output is guaranteed to pull down 20mA. This allows the use of a lower value pull-up resistor to reduce the low-to-high delay time. Rev. A For more information www.analog.com 55 LTC4284 APPLICATIONS INFORMATION START, REPEATED START and STOP Conditions When the bus is idle, SCL and SDA are high. A bus master signals the start of a transfer with a START condition. START is defined by a falling edge on SDA while SCL is high. The end of the transfer is signaled by a STOP condition. STOP is defined by a rising edge on SDA while SCL is high (see Figure26). In between START and STOP, data and handshake bits are transferred with a data value on SDA and a high pulse on SCL. For data or handshake bits, SDA changes only while SCL is low. A bus master may also signal a REPEATED START condition in the middle of a transfer. Like START, REPEATED START is defined by a falling edge on SDA while SCL is high. REPEATED START is used in read transfers (see Transfer Protocol Types). ACK/NACK Data is transferred as a series of 8-bit bytes. Following each data byte is a handshake bit driven by the receiver. SDA low during this bit is interpreted as acknowledge (ACK). SDA high is interpreted as not-acknowledge(NACK). In all cases, a transfer stops after a NACK bit. If the bus master is sending a data byte, a NACK from the slave indicates an error condition. If all bytes written are ACK'ed, the bus master may also terminate a write by making a STOP condition after the final byte. If the bus master is receiving a data, it returns NACK after the last byte it wants to receive. This is normal, no error condition is implied. I2C Device Addressing The bus master addresses a slave by sending a slave address byte after either a START or REPEATED START condition. Bit 0 of the slave address byte is high to select a read transfer and low to select a write. See Transfer Protocol Types for more detail. The LTC4284 ADR1 and ADR0 pins can be configured to select its slave addresses as shown in Table2. Single-wire broadcast mode replaces the normal serialbus interface with a one-wire option which continuously broadcasts important status from the LTC4284. See more details in Single-Wire Broadcast. Transfer Protocol Types Figure26 shows basic elements of the I2C protocol. These are combined to form complete read and write transfers. Figures 27 to 32 show the transfer protocol types supported by the LTC4284. Table2. LTC4284 Device Addressing DESCRIPTION HEX DEVICE ADDRESS* LTC4284 ADDRESS PINS BINARY DEVICE ADDRESS 7-Bit 8-Bit a6 a5 a4 a3 a2 a1 a0 R/W# ADR1 ADR0 Mass Write 1F 3E 0 0 1 1 1 1 1 0 X X Alert Response 0C 19 0 0 0 1 1 0 0 1 X X 0 10 20 0 0 1 0 0 0 0 X L L 1 11 22 0 0 1 0 0 0 1 X L NC 2 12 24 0 0 1 0 0 1 0 X H NC 3 13 26 0 0 1 0 0 1 1 X L H 4 14 28 0 0 1 0 1 0 0 X NC L 5 15 2A 0 0 1 0 1 0 1 X NC NC 6 16 2C 0 0 1 0 1 1 0 X H H 7 17 2E 0 0 1 0 1 1 1 X NC H H L 8 Single-Wire Broadcast Mode H = Tie to INTVCC; L = Tie to VEE; NC = No connect or open; X = Don't Care *8-bit hexadecimal address with LSB R/W bit = 0 7-bit hexadecimal address with MSB a7 = 0 56 Rev. A For more information www.analog.com LTC4284 APPLICATIONS INFORMATION SDA a6 - a0 SCL 1-7 b7 - b0 8 9 b7 - b0 8 1-7 9 8 1-7 9 S P START CONDITION ADDRESS R/W ACK DATA ACK DATA STOP CONDITION ACK 4284 F26 Figure26. General Data Transfer over I2C S ADDRESS W A COMMAND A DATA A 001 a3:a0 0 0 b7:b0 b7:b0 0 0 FROM MASTER TO SLAVE P 4284 F27 A: ACKNOWLEDGE (LOW) A: NOT ACKNOWLEDGE (HIGH) R: READ BIT (HIGH) W: WRITE BIT (LOW) S: START CONDITION SR: REPEATED START CONDITION P: STOP CONDITION FROM SLAVE TO MASTER S ADDRESS W A COMMAND A DATA A DATA A 001 a3:a0 0 0 b7:b0 b7:b0 0 b7:b0 0 P 4284 F28 Figure27. Write Byte Protocol S 0 Figure28. Write Word Protocol ADDRESS W A COMMAND A DATA 001 a3:a0 0 0 b7:b0 b7:b0 0 * * * A DATA A 0 b7:b0 0 P 4284 F29 Figure29. Write Page Protocol S ADDRESS W A COMMAND A SR ADDRESS 001 a3:a0 0 0 b7:b0 001 a3:a0 0 R A DATA A 1 0 b7:b0 1 P 4284 F30 Figure30. Read Byte Protocol S ADDRESS W A COMMAND A SR ADDRESS 001 a3:a0 0 0 b7:b0 001 a3:a0 0 R A DATA A DATA A 1 0 b7:b0 0 b7:b0 1 P 4284 F31 Figure31. Read Word Protocol S ADDRESS W A COMMAND A SR ADDRESS 001 a3:a0 0 0 b7:b0 0 001 a3:a0 R A DATA A 1 0 b7:b0 0 * * * DATA A b7:b0 1 P 4284 F32 Figure32. Read Page Protocol S ALERT RESPONSE ADDRESS R A DEVICE ADDRESS A 0001100 1 0 001 a3:a0 0 1 P 4284 F33 Figure33. Alert Response Protocol Rev. A For more information www.analog.com 57 LTC4284 APPLICATIONS INFORMATION Command Codes and Register Addressing Read Protocols The command byte in each transfer contains the register address for the first byte being accessed. If multiple bytes are accessed in a transfer, each comes from the address following the previous byte. For example, when reading the six-byte ENERGY register, the first byte comes from address 0x7A, the second byte from address 0x7B, up through the final byte from address 0x7F (see Table3). Reads consist of two parts. First the master sends a slave address byte with bit 0 clear and a COMMAND byte to select the register to be read from. After this, a REPEATED START condition and second slave address byte are sent with bit 0 set (indicating read). The LTC4284 replies with data after the second slave address byte. It's possible to access two different registers in one transfer. For example, the SYSTEM_STATUS and ADC_STATUS registers can be accessed using a read word transfer with COMMAND equal 0x00. This addressing method is common for I2C systems, but differs from SMBus. With SMBus, each register occupies a single command code, regardless of register size. Registers 0x41 to 0x79 are implemented in 16-bit RAM words as shown in Table3. To save command codes, each occupies only one register address. Consider a four-byte read with command code of 0x41. Data will be returned in this order: 1. Most significant byte of SENSE Read page and write page refer to transfers larger than two bytes. Page accesses are convenient for reading larger registers and for synchronizing data in multiple registers (see Data Synchronization and Arbitration for details). If page accesses are required, the PAGE_READ_ WRITE_ENABLE bit in the CONTROL_1 register should be set. If the bit is not set, accesses to more than two bytes of data will be terminated. For an attempted page write, the extra bytes would be NACK'ed. For an attempted page read, the LTC4284 would return 0xFF. Byte Ordering The LTC4284 uses big endian ordering for accessing multi-byte registers. That means when a 16-bit word register is accessed, the most significant byte is transferred first, followed by the least significant byte. This is common in I2C systems. SMBus systems use little endian ordering, with least significant byte transferred first. 2. Least significant byte of SENSE 3. Most significant byte of SENSE_MIN 4. Least significant byte of SENSE_MIN Write Protocols For writes, all data bytes come from the bus master and are acknowledged by the slave. Bit 0 of the slave address byte is clear to select write. The COMMAND byte contains the register address for the first byte being written. A special slave address can be used to implement mass writes. If multiple LTC4284 chips are on the same serial bus, the mass write technique can be used to write all of them at the same time. All LTC4284s respond to a slave address of 0011_111b with the Read/Write# bit clear. Bit MASS_WRITE_ENABLE in register CONTROL_1 can be set to enable mass writes. 58 Read Page and Write Page Protocols ALERT# and Alert Response Protocol The LTC4284 fully supports the SMBus alert response mechanism. Refer to Figure33: 1. If ALERT# is low, the LTC4284 will acknowledge the SMBus alert response address (ARA). 2. In the following data byte, the LTC4284 returns its own slave address, with bit 0 clear. Multiple slave devices on the bus may be responding to the same ARA. If a conflict is detected on any bit, the LTC4284 will back off and let the higher priority device continue. 3. If the LTC4284 successfully transfers its entire slave address, it will clear its ALERT_GENERATED bit, and stop pulling ALERT# low. Rev. A For more information www.analog.com LTC4284 APPLICATIONS INFORMATION There are 52 possible conditions to set ALERT_ GENERATED. Each condition (fault or event) has a corresponding alert enable bit. Table24 has the list of fault/ event bits and alert enable bits. false stuck bus timeouts. The LTC4284 uses a modified stuck bus mechanism to prevent false timeouts. The timer is cleared If SCL is high and the LTC4284 is not pulling down SDAO. For all cases, ALERT_GENERATED will only be set by a rising edge on the combination of fault/event logically and'ed with alert enable bit. ALERT_GENERATED is set whether a fault/event bit is set first or the corresponding alert enable bit is set first. Once a fault or event bit is set, it won't contribute to ALERT_GENERATED again until the fault or event is cleared. As with other stuck bus timers, SCL stuck low causes a timeout. In addition, a timeout happens if the LTC4284 continuously pulls down SDAO for 30ms. This could happen if the bus stops with SCL high while the LTC4284 is still pulling down on SDAO. One event, ADC conversion completed, doesn't have a latched status bit. There is a corresponding ADC_CONV_ ALERT bit to enable the ALERT_GENERATED. But when servicing ALERT#, software won't have a way to verify that a completed ADC conversion caused the alert condition. Due to this limitation, the ADC conversion completed alert is not useful unless all other alert sources are masked off. Several RAM locations and registers in the LTC4284 have control shared between ADC logic and the I2C interface. ADC logic writes data and the I2C interface reads from them. The RAM locations are at addresses between 0x41 and 0x79. Registers for ENERGY and TICK_COUNTER are at addresses between 0x7A and 0x83. These registers are also written by ADC logic. Typically, software will read the event and fault registers to check status, then write 0's to clear the bits that have been serviced. Event and fault bits can also be set directly by the I2C bus. A bit set this way leads to ALERT_ GENERATED set and ALERT# low in the same way as when the chip sets the bit. ALERT_GENERATED itself can also be set by an I2C write. These features may be helpful for software test. ADC writes to ENERGY, TICK_COUNTER and the ADC RAM locations are always done while the I2C interface is idle. That ensures none of the locations can change in the middle of an I2C read. For example, when reading a two-byte RAM location, the two bytes read will always be consistent with each other. Data Synchronization and Arbitration The LTC4284 has an SMBus-style stuck bus reset. If the serial bus remains stuck for about 30ms, the I2C controller block will reset itself. When the controller is reset, it stops pulling down SDAO and searches for a new START condition. The ENERGY and TICK_COUNTER registers are larger, but the same technique can be used. To ensure consistency, read all bytes of each register in a single I2C operation. For energy calculations, you may also need ENERGY and TICK_COUNTER to be consistent with each other. This can be done by reading both registers together in a single 10-byte I2C read. The register locations are contiguous to facilitate this approach. Read 10 bytes starting at register location 0x7A. In the SMBus definition, the stuck bus timer is cleared by SCL high. Many existing LTC chips including previous hot swap controllers clear the timer when SCL and SDA are both high. This is more thorough because it can detect either SDA or SCL stuck low. There are some limits on the length of I2C transfers. If any one transfer takes longer than an ADC conversion time, some ADC data will be lost. This depends on the bus speed, transfer length and ADC conversion time. See the ADC[2:0] field in Table12. The method presents a problem with the LTC4284. With read page or write page, very long transfers are possible. For each byte of 0x00 transferred, SDA will be low for the whole byte. A long sequence of 0x00 bytes may lead to As detailed above, the I2C interface operates in parallel with ADC update logic. In some other cases, I2C access will be disabled: Stuck Bus Reset Rev. A For more information www.analog.com 59 LTC4284 APPLICATIONS INFORMATION 1. After a power-on reset or reboot, I2C access is disabled while configuration registers are being loaded from EEPROM. 2. While a fault log is being written to EEPROM 3. After a write to the REBOOT register which sets the RBT_EN bit. In these cases, the I2C controller ignores all inputs and SDAO is not pulled down. As a result, slave address and other bytes from the bus master will be NACK'ed. This behavior is common in I2C systems. Be careful with this when operating in an SMBus system. The SMBus specification requires all slave address bytes to be ACK'ed but the 4284 doesn't ACK them in the three cases listed above. While reading data from the LTC4284, the ACK for each byte comes from the bus master. There's no way for the LTC4284 to indicate a problem during the read. If the I2C controller is disabled during a read, bytes of 0xFF will be returned by the LTC4284 in place of the expected data. Single-Wire Broadcast The LTC4284 can start itself up without any I2C activity. The chip automatically loads configuration data from EEPROM to working registers after a power up or reboot. In this case, the user may not need a full I2C interface. For many system applications, a full I2C interface would require three isolators (see Figure2b). Use of the singlewire broadcast mode can reduce this to one isolator. When ADR1 is connected to INTVCC and ADR0 is connected to VEE, single-wire broadcast mode is selected. In this mode, I2C bus operation is disabled. In its place, status and ADC information are continually transmitted on SDAO. A packet of 20 bytes as shown in Table2a is transmitted once for each ADC conversion cycle using Manchester encoding. The packet is in the following format: Table2a. Single-Wire Broadcast Data Format DATA ADDRESS SIZE IN BITS Preamble--0x2A N/A 8 SENSE 0x41 16 RTNS 0x44 16 POWER 0x47 16 Most recent ADC aux reading 16 SYSTEM_STATUS 0x00 8 ADC_STATUS 0x01 8 INPUT_STATUS 0x02 8 FAULT_STATUS 0x03 8 VAUX FAULT ADC_ALARM_LOG PEC 0x04 8 0x05-0x09 40 N/A 8 Total 160 CLOCK DATA 1 0 1 0 0 1 1 1 0 0 1 MANCHESTER (AS PER G.E. THOMAS) MANCHESTER (AS PER IEEE 802.3) 4284 F34 Figure34. An Example of Manchester Encoding, Showing Both Conventions 60 Rev. A For more information www.analog.com LTC4284 APPLICATIONS INFORMATION The preamble byte is a fixed pattern to allow hardware or software to detect the packet start and bit rate as shown in Figure35. VAUX is a selected auxiliary channel measurement. In each ADC conversion cycle, one auxiliary channel may be measured. Bits [7:4] of ADC_STATUS contain the AUX_ADC_CH field to identify which ADC auxiliary input is present in the VAUX field. See the Data Converters section for an explanation of the channel select sequence. The final byte of the packet is an SMBus-compatible PEC byte. PEC uses an 8-bit CRC with the polynomial X8 + X2 + X + 1. PEC covers all bytes of the packet including the preamble. The PEC accumulator is initialized to 0x00 at the start of the packet. The data rate of single-wire broadcast can be selected using field BC in the CONFIG_3 register, see Table11. In broadcast mode, there needs to be enough time to transmit the entire 20-byte packet before another ADC update. That limit means the slowest data rates (128k and 32k) can't be used when the ADC is configured for 8-bit samples. In those two cases, the LTC4284 automatically switches to a minimum 512k data rate for single-wire broadcast. Two different conventions are followed: G.E. Thomas and IEEE 802.3 as shown in Figure34. For G.E. Thomas convention, each data 1 bit is represented by a falling edge in the middle of the bit cell. For IEEE 802.3 convention, data 1 bits are represented by a rising edge in the middle of the bit cell. G.E. Thomas convention is used for the LTC4284. This is the same as for the LTC4261. SDAO 0 0 1 0 1 0 1 0 4284 F35 Figure35. Manchester Encoding for the Preamble Byte of 0x2A Rev. A For more information www.analog.com 61 LTC4284 APPLICATIONS INFORMATION Table3. LTC4284 Register Address and Contents REGISTER NAME Register Tables DATA READ/ LENGTH WRITE (BYTES) REGISTER ADDRESS* DESCRIPTION DEFAULT VALUE SYSTEM_STATUS 0x00 System status information R 1 N/A ADC_STATUS 0x01 ADC conversion status R 1 N/A INPUT_STATUS 0x02 PGIO1-PGIO4, ADIO1-ADIO4 general purpose input status R 1 N/A FAULT_STATUS 0x03 Fault status information R 1 N/A 0x04 System fault R/W 1 0x00 ADC_ALARM_LOG FAULT 0x05-0x09 ADC measurement alarms R/W 5 0x0000_0000_00 CONTROL 0x0A-0x0B Controls the system on/off and auto-retry behaviors R/W 2 0xDB03 R 1 N/A R/W 3 0x0CC0_00 Reserved 0x0C Read only, always returns 0 CONFIG 0x0D-0x0F Configures current limit, foldback, delays, and other system parameters PGIO_CONFIG 0x10-0x11 Configures I/O states and outputs of PGIO1-PGIO4 ADIO_CONFIG ADC_SELECT FAULT_ALERT ADC_ALERT R/W 2 0x0004 R/W 1 0xF0 R/W 2 0xFF0F Controls whether ALERT# pulls low after a system fault is logged R/W 1 0x00 0x16-0x1A Controls whether ALERT# pulls low after an ADC alarm is logged R/W 5 0x0000_0000_00 0x12 Configures I/O states and outputs of ADIO1-ADIO4, controls ADC 0x13-0x14 Auxiliary ADC inputs selection 0x15 SENSE_MIN_TH 0x1B ADC alarm threshold for minimum ADC+ - ADC- R/W 1 0x00 SENSE_MAX_TH 0x1C ADC alarm threshold for maximum ADC+ - ADC- R/W 1 0xFF VPWR_MIN_TH 0x1D ADC alarm threshold for minimum VPWR(RTNS/DRNS) voltage R/W 1 0x00 VPWR_MAX_TH 0x1E ADC alarm threshold for maximum VPWR(RTNS/DRNS) voltage R/W 1 0xFF POWER_MIN_TH 0x1F ADC alarm threshold for minimum input power R/W 1 0x00 POWER_MAX_TH 0x20 ADC alarm threshold for maximum input power R/W 1 0xFF ADIN1_MIN_TH 0x21 ADC alarm threshold for minimum ADIN1 voltage R/W 1 0x00 ADIN1_MAX_TH 0x22 ADC alarm threshold for maximum ADIN1 voltage R/W 1 0xFF ADIN2_MIN_TH 0x23 ADC alarm threshold for minimum ADIN2 voltage R/W 1 0x00 ADIN2_MAX_TH 0x24 ADC alarm threshold for maximum ADIN2 voltage R/W 1 0xFF ADIN3_MIN_TH 0x25 ADC alarm threshold for minimum ADIN3 voltage R/W 1 0x00 ADIN3_MAX_TH 0x26 ADC alarm threshold for maximum ADIN3 voltage R/W 1 0xFF ADIN4_MIN_TH 0x27 ADC alarm threshold for minimum ADIN4 voltage R/W 1 0x00 ADIN4_MAX_TH 0x28 ADC alarm threshold for maximum ADIN4 voltage R/W 1 0xFF ADIO1_MIN_TH 0x29 ADC alarm threshold for minimum ADIO1 voltage R/W 1 0x00 ADIO1_MAX_TH 0x2A ADC alarm threshold for maximum ADIO1 voltage R/W 1 0xFF ADIO2_MIN_TH 0x2B ADC alarm threshold for minimum ADIO2 voltage R/W 1 0x00 ADIO2_MAX_TH 0x2C ADC alarm threshold for maximum ADIO2 voltage R/W 1 0xFF ADIO3_MIN_TH 0x2D ADC alarm threshold for minimum ADIO3 voltage R/W 1 0x00 ADIO3_MAX_TH 0x2E ADC alarm threshold for maximum ADIO3 voltage R/W 1 0xFF ADIO4_MIN_TH 0x2F ADC alarm threshold for minimum ADIO4 voltage R/W 1 0x00 ADIO4_MAX_TH 0x30 ADC alarm threshold for maximum ADIO4 voltage R/W 1 0xFF DRNS_MIN_TH 0x31 ADC alarm threshold for minimum DRNS voltage R/W 1 0x00 DRNS_MAX_TH 0x32 ADC alarm threshold for maximum DRNS voltage R/W 1 0xFF DRAIN_MIN_TH 0x33 ADC alarm threshold for minimum DRAIN voltage R/W 1 0x00 62 Rev. A For more information www.analog.com LTC4284 APPLICATIONS INFORMATION Table 3. LTC4284 Register Address and Contents (Cont.) REGISTER NAME DRAIN_MAX_TH DATA READ/ LENGTH WRITE (BYTES) REGISTER ADDRESS* DESCRIPTION 0x34 ADC alarm threshold for maximum DRAIN voltage SENSE1_MIN_TH 0x35 ADC alarm threshold for minimum SENSE1+ - SENSE1- SENSE1_MAX_TH 0x36 ADC alarm threshold for maximum SENSE1+ - SENSE1- 0x37 ADC alarm threshold for minimum SENSE2+ - SENSE2- SENSE2_MAX_TH 0x38 ADC alarm threshold for maximum SENSE2+ - SENSE2- ADIN12_MIN_TH 0x39 ADC alarm threshold for minimum ADIN2 - ADIN1 SENSE2_MIN_TH R/W DEFAULT VALUE 1 0xFF R/W 1 0x00 R/W 1 0xFF R/W 1 0x00 R/W 1 0xFF R/W 1 0x00 ADIN12_MAX_TH 0x3A ADC alarm threshold for maximum ADIN2 - ADIN1 R/W 1 0xFF ADIN34_MIN_TH 0x3B ADC alarm threshold for minimum ADIN4 - ADIN3 R/W 1 0x00 ADIN34_MAX_TH 0x3C ADC alarm threshold for maximum ADIN4 - ADIN3 R/W 1 0xFF ADIO12_MIN_TH 0x3D ADC alarm threshold for minimum ADIO2 - ADIO1 R/W 1 0x00 ADIO12_MAX_TH 0x3E ADC alarm threshold for maximum ADIO2 - ADIO1 R/W 1 0xFF ADIO34_MIN_TH 0x3F ADC alarm threshold for minimum ADIO4 - ADIO3 R/W 1 0x00 ADIO34_MAX_TH 0x40 ADC alarm threshold for maximum ADIO4 - ADIO3 R/W 1 0xFF SENSE 0x41 Most recent ADC output for ADC+ - ADC- R/W 2 0x0000 SENSE_MIN 0x42 Minimum ADC output for ADC+ - ADC- R/W 2 0x0000 SENSE_MAX 0x43 Maximum ADC output for ADC+ - ADC- R/W 2 0x0000 VPWR 0x44 Most recent ADC output for VPWR(RTNS/DRNS) R/W 2 0x0000 VPWR_MIN 0x45 Minimum ADC output for VPWR(RTNS/DRNS) R/W 2 0x0000 VPWR_MAX 0x46 Maximum ADC output for VPWR(RTNS/DRNS) R/W 2 0x0000 POWER 0x47 Most recent ADC output for power R/W 2 0x0000 POWER_MIN 0x48 Minimum ADC output for power R/W 2 0x0000 POWER_MAX 0x49 Maximum ADC output for power R/W 2 0x0000 ADIN1 0x4A Most recent ADC output for ADIN1 R/W 2 0x0000 ADIN1_MIN 0x4B Minimum ADC output for ADIN1 R/W 2 0x0000 ADIN1_MAX 0x4C Maximum ADC output for ADIN1 R/W 2 0x0000 ADIN2 0x4D Most recent ADC output for ADIN2 R/W 2 0x0000 ADIN2_MIN 0x4E Minimum ADC output for ADIN2 R/W 2 0x0000 ADIN2_MAX 0x4F Maximum ADC output for ADIN2 R/W 2 0x0000 ADIN3 0x50 Most recent ADC output for ADIN3 R/W 2 0x0000 ADIN3_MIN 0x51 Minimum ADC output for ADIN3 R/W 2 0x0000 ADIN3_MAX 0x52 Maximum ADC output for ADIN3 R/W 2 0x0000 ADIN4 0x53 Most recent ADC output for ADIN4 R/W 2 0x0000 ADIN4_MIN 0x54 Minimum ADC output for ADIN4 R/W 2 0x0000 ADIN4_MAX 0x55 Maximum ADC output for ADIN4 R/W 2 0x0000 ADIO1 0x56 Most recent ADC output for ADIO1 R/W 2 0x0000 ADIO1_MIN 0x57 Minimum ADC output for ADIO1 R/W 2 0x0000 ADIO1_MAX 0x58 Maximum ADC output for ADIO1 R/W 2 0x0000 ADIO2 0x59 Most recent ADC output for ADIO2 R/W 2 0x0000 ADIO2_MIN 0x5A Minimum ADC output for ADIO2 R/W 2 0x0000 Rev. A For more information www.analog.com 63 LTC4284 APPLICATIONS INFORMATION Table 3. LTC4284 Register Address and Contents (Cont.) REGISTER NAME ADIO2_MAX DATA READ/ LENGTH WRITE (BYTES) REGISTER ADDRESS* DESCRIPTION DEFAULT VALUE 0x5B Maximum ADC output for ADIO2 R/W 2 0x0000 ADIO3 0x5C Most recent ADC output for ADIO3 R/W 2 0x0000 ADIO3_MIN 0x5D Minimum ADC output for ADIO3 R/W 2 0x0000 ADIO3_MAX 0x5E Maximum ADC output for ADIO3 R/W 2 0x0000 ADIO4 0x5F Most recent ADC output for ADIO4 R/W 2 0x0000 ADIO4_MIN 0x60 Minimum ADC output for ADIO4 R/W 2 0x0000 ADIO4_MAX 0x61 Maximum ADC output for ADIO4 R/W 2 0x0000 DRNS 0x62 Most recent ADC output for DRNS R/W 2 0x0000 DRNS_MIN 0x63 Minimum ADC output for DRNS R/W 2 0x0000 DRNS_MAX 0x64 Maximum ADC output for DRNS R/W 2 0x0000 DRAIN 0x65 Most recent ADC output for DRAIN R/W 2 0x0000 DRAIN_MIN 0x66 Minimum ADC output for DRAIN R/W 2 0x0000 DRAIN_MAX 0x67 Maximum ADC output for DRAIN R/W 2 0x0000 SENSE1 0x68 Most recent ADC output for SENSE1+ - SENSE1- R/W 2 0x0000 SENSE1_MIN 0x69 Minimum ADC output for SENSE1+ - SENSE1- R/W 2 0x0000 SENSE1_MAX 0x6A Maximum ADC output for SENSE1+ - SENSE1- R/W 2 0x0000 0x6B Most recent ADC output for SENSE2+ - SENSE2- R/W 2 0x0000 SENSE2 SENSE2_MIN 0x6C Minimum ADC output for SENSE2+ - SENSE2- R/W 2 0x0000 SENSE2_MAX 0x6D Maximum ADC output for SENSE2+ - SENSE2- R/W 2 0x0000 ADIN12 0x6E Most recent ADC output for ADIN2 - ADIN1 R/W 2 0x0000 ADIN12_MIN 0x6F Minimum ADC output for ADIN2 - ADIN1 R/W 2 0x0000 ADIN12_MAX 0x70 Maximum ADC output for ADIN2 - ADIN1 R/W 2 0x0000 ADIN34 0x71 Most recent ADC output for ADIN4 - ADIN3 R/W 2 0x0000 ADIN34_MIN 0x72 Minimum ADC output for ADIN4 - ADIN3 R/W 2 0x0000 ADIN34_MAX 0x73 Maximum ADC output for ADIN4 - ADIN3 R/W 2 0x0000 ADIO12 0x74 Most recent ADC output for ADIO2 - ADIO1 R/W 2 0x0000 ADIO12_MIN 0x75 Minimum ADC output for ADIO2 - ADIO1 R/W 2 0x0000 ADIO12_MAX 0x76 Maximum ADC output for ADIO2 - ADIO1 R/W 2 0x0000 ADIO34 0x77 Most recent ADC output for ADIO4 - ADIO3 R/W 2 0x0000 ADIO34_MIN 0x78 Minimum ADC output for ADIO4 - ADIO3 R/W 2 0x0000 0x79 Maximum ADC output for ADIO4 - ADIO3 ADIO34_MAX R/W 2 0x0000 ENERGY 0x7A-0x7F Input energy meter R/W 6 0x0000_0000_0000 TICK_COUNTER 0x80-0x83 Tick counter for energy meter R/W 4 0x0000_0000 METER_CONTROL 0x84 Controls energy meter and tick counter R/W 1 0x00 ADC_SNAPSHOT 0x85 Controls ADC snapshot R/W 1 0x00 Reserved FAULT_LOG_CONTROL Reserved REBOOT 64 0x86-0x8F Read only, always returns 0 0x90 Enables logging fault and ADC data into EEPROM 0x91-0xA1 Read only, 0x91-0x9F return 0xFF, 0xA0 and 0xA1 return 0 0xA2 Enables reboot and configures reboot delay R 10 N/A R/W 1 0x00 R 17 N/A R/W 1 0x00 Rev. A For more information www.analog.com LTC4284 APPLICATIONS INFORMATION x. LTC4284 Register Address and Contents (Cont.) REGISTER NAME Reserved EE_FAULT DATA READ/ LENGTH WRITE (BYTES) REGISTER ADDRESS* DESCRIPTION 0xA3 Read only, always returns 0 0xA4 Records fault register in EEPROM upon a fault R 1 DEFAULT VALUE N/A R/W 1 0x00 EE_ADC_ALARM_LOG 0xA5-0xA9 Records ADC_ALARM_LOG registers in EEPROM upon a fault R/W 5 0x0000_0000_00 EE_CONTROL 0xAA-0xAB Stores default of CONTROL registers in EEPROM R/W 2 0xDB03 Reserved R 1 N/A EE_CONFIG 0xAD-0xAF Stores default of CONFIG registers in EEPROM R/W 3 0x0CC0_00 EE_PGIO_CONFIG 0xB0-0xB1 Stores default of PGIO_CONFIG registers in EEPROM EE_ADIO_CONFIG EE_ADC_SELECT EE_FAULT_ALERT EE_ADC_ALERT EE_SENSE_MIN_TH 0xAC Read only, returns 0xFF if EEPROM busy, otherwise returns 0 R/W 2 0x0004 Stores default of ADIO_CONFIG register in EEPROM R/W 1 0xF0 0xB3-0xB4 Stores default of ADC_SELECT registers in EEPROM R/W 2 0xFF0F 0xB2 0xB5 Stores default of FAULT_ALERT register in EEPROM 0xB6-0xBA Stores default of ADC_ALERT registers in EEPROM R/W 1 0x00 R/W 5 0x0000_0000_00 0x00 0xBB Stores default of SENSE_MIN_TH register in EEPROM R/W 1 EE_SENSE_MAX_TH 0xBC Stores default of SENSE_MAX_TH register in EEPROM R/W 1 0xFF EE_VPWR_MIN_TH 0xBD Stores default of VPWR_MIN_TH register in EEPROM R/W 1 0x00 EE_VPWR_MAX_TH 0xBE Stores default of VPWR_MAX_TH register in EEPROM R/W 1 0xFF EE_POWER_MIN_TH 0xBF Stores default of POWER_MIN_TH register in EEPROM R/W 1 0x00 EE_POWER_MAX_TH 0xC0 Stores default of POWER_MAX_TH register in EEPROM R/W 1 0xFF EE_ADIN1_MIN_TH 0xC1 Stores default of ADIN1_MIN_TH register in EEPROM R/W 1 0x00 EE_ADIN1_MAX_TH 0xC2 Stores default of ADIN1_MAX_TH register in EEPROM R/W 1 0xFF EE_ADIN2_MIN_TH 0xC3 Stores default of ADIN2_MIN_TH register in EEPROM R/W 1 0x00 EE_ADIN2_MAX_TH 0xC4 Stores default of ADIN2_MAX_TH register in EEPROM R/W 1 0xFF EE_ADIN3_MIN_TH 0xC5 Stores default of ADIN3_MIN_TH register in EEPROM R/W 1 0x00 EE_ADIN3_MAX_TH 0xC6 Stores default of ADIN3_MAX_TH register in EEPROM R/W 1 0xFF EE_ADIN4_MIN_TH 0xC7 Stores default of ADIN4_MIN_TH register in EEPROM R/W 1 0x00 EE_ADIN4_MAX_TH 0xC8 Stores default of ADIN4_MAX_TH register in EEPROM R/W 1 0xFF EE_ADIO1_MIN_TH 0xC9 Stores default of ADIO1_MIN_TH register in EEPROM R/W 1 0x00 EE_ADIO1_MAX_TH 0xCA Stores default of ADIO1_MAX_TH register in EEPROM R/W 1 0xFF EE_ADIO2_MIN_TH 0xCB Stores default of ADIO2_MIN_TH register in EEPROM R/W 1 0x00 EE_ADIO2_MAX_TH 0xCC Stores default of ADIO2_MAX_TH register in EEPROM R/W 1 0xFF EE_ADIO3_MIN_TH 0xCD Stores default of ADIO3_MIN_TH register in EEPROM R/W 1 0x00 EE_ADIO3_MAX_TH 0xCE Stores default of ADIO3_MAX_TH register in EEPROM R/W 1 0xFF EE_ADIO4_MIN_TH 0xCF Stores default of ADIO4_MIN_TH register in EEPROM R/W 1 0x00 EE_ADIO4_MAX_TH 0xD0 Stores default of ADIO4_MAX_TH register in EEPROM R/W 1 0xFF EE_DRNS_MIN_TH 0xD1 Stores default of DRNS_MIN_TH register in EEPROM R/W 1 0x00 EE_DRNS_MAX_TH 0xD2 Stores default of DRNS_MAX_TH register in EEPROM R/W 1 0xFF EE_DRAIN_MIN_TH 0xD3 Stores default of DRAIN_MIN_TH register in EEPROM R/W 1 0x00 EE_DRAIN_MAX_TH 0xD4 Stores default of DRAIN_MAX_TH register in EEPROM R/W 1 0xFF EE_SENSE1_MIN_TH 0xD5 Stores default of SENSE1_MIN_TH register in EEPROM R/W 1 0x00 EE_SENSE1_MAX_TH 0xD6 Stores default of SENSE1_MAX_TH register in EEPROM R/W 1 0xFF Rev. A For more information www.analog.com 65 LTC4284 APPLICATIONS INFORMATION Table 3. LTC4284 Register Address and Contents (Cont.) REGISTER NAME DATA READ/ LENGTH WRITE (BYTES) REGISTER ADDRESS* DESCRIPTION DEFAULT VALUE EE_SENSE2_MIN_TH 0xD7 Stores default of SENSE2_MIN_TH register in EEPROM R/W 1 0x00 EE_SENSE2_MAX_TH 0xD8 Stores default of SENSE2_MAX_TH register in EEPROM R/W 1 0xFF EE_ADIN12_MIN_TH 0xD9 Stores default of ADIN12_MIN_TH register in EEPROM R/W 1 0x00 EE_ADIN12_MAX_TH 0xDA Stores default of ADIN12_MAX_TH register in EEPROM R/W 1 0xFF EE_ADIN34_MIN_TH 0xDB Stores default of ADIN34_MIN_TH register in EEPROM R/W 1 0x00 EE_ADIN34_MAX_TH 0xDC Stores default of ADIN34_MAX_TH register in EEPROM R/W 1 0xFF EE_ADIO12_MIN_TH 0xDD Stores default of ADIO12_MIN_TH register in EEPROM R/W 1 0x00 EE_ADIO12_MAX_TH 0xDE Stores default of ADIO12_MAX_TH register in EEPROM R/W 1 0xFF EE_ADIO34_MIN_TH 0xDF Stores default of ADIO34_MIN_TH register in EEPROM R/W 1 0x00 EE_ADIO34_MAX_TH 0xE0 Stores default of ADIO34_MAX_TH register in EEPROM R/W 1 0xFF EE_SENSE 0xE1 Records MSB byte of SENSE registers in EEPROM upon a fault R/W 1 0x00 EE_SENSE_MIN 0xE2 Records MSB byte of SENSE_MIN registers in EEPROM upon a fault R/W 1 0x00 EE_SENSE_MAX 0xE3 Records MSB byte of SENSE_MAX registers in EEPROM upon a fault R/W 1 0x00 EE_RTNS 0xE4 Records MSB byte of RTNS registers in EEPROM upon a fault R/W 1 0x00 EE_RTNS_MIN 0xE5 Records MSB byte of RTNS_MIN registers in EEPROM upon a fault R/W 1 0x00 EE_RTNS_MAX 0xE6 Records MSB byte of RTNS_MAX registers in EEPROM upon a fault R/W 1 0x00 R 2 0x1070 POWER_PLAY_ID 0xE7-0xE8 LTpowerPlay ID for LTC4284 EE_SCRATCH 0xE9-0xEF Spare EEPROM bytes EE_FAULT_LOG_ CONTROL Reserved 0xF0 EEPROM backup of FAULT_LOG_CONTROL register 0xF1-0xFF Read only, always returns 0xFF R/W 7 0x0000_0000_0000 R/W 1 0x00 R 15 N/A *For the two-byte ADC data registers from 0x41 to 0x79, the address points to the MSB byte and increments to the LSB byte when using a Write Word or Read Word protocol. 66 Rev. A For more information www.analog.com LTC4284 APPLICATIONS INFORMATION Table4. SYSTEM_STATUS Registers (0x00) - Read Only BIT NAME OPERATION 7 FET_ON_STATUS On/off status of GATE; 1 = GATE commanded on, 0 = GATE commanded off 6 EN# State of EN# pin; 1 = EN# high, 0 = EN# low 5 GATE2_HIGH State of GATE2 pin; 1 = GATE2 high, 0 = GATE2 low 4 GATE1_HIGH State of GATE1 pin; 1 = GATE1 high, 0 = GATE1 low 3 TMR_LOW Status of TMR pin; 1 = TMR is lower than 0.1V, 0 = TMR is higher than 0.1V 2 EEPROM _BUSY Status of EEPROM writing; 1 = EEPROM is being written, 0 = EEPROM writing is completed 1 PG_STATUS Power good status; 1 = power good condition met, 0 = power good condition not met 0 MODE1 Single driver mode (Mode 1) status; 1 = Mode 1 is enabled, 0 = Mode 1 is disabled Table5. ADC_STATUS Register (0x01) - Read Only BIT NAME 7:4 AUX_ADC_CH OPERATION Channel label of the auxiliary input that completed the latest ADC measurement in continuous or snapshot mode AUX_ADC_CH [7:4] Auxiliary ADC Input Register Address 0000 ADIN1 0x4A 0001 ADIN2 0x4D 0010 ADIN3 0x50 0011 ADIN4 0x53 0100 ADIO1 0x56 0101 ADIO2 0x59 0110 ADIO3 0x5C 0111 ADIO4 0x5F 1000 DRNS 0x62 1001 DRAIN 0x65 1010 SENSE1+ - SENSE1- 0x68 1011 SENSE2+ - SENSE2- 0x6B 1100 ADIN2 - ADIN1 0x6E 1101 ADIN4 - ADIN3 0x71 1110 ADIO2 - ADIO1 0x74 1111 ADIO4 - ADIO3 0x77 3 ADC_IDLE Conversion status of ADC; 1 = ADC is idle in snapshot mode, 0 = ADC is in continuous mode or ADC is busy in snapshot mode 2 MODE2 Parallel mode (Mode 2) status; 1 = Mode 2 is enabled, 0 = Mode 2 is disabled 1 MODE3 High stress staged start mode (Mode 3) status; 1 = Mode 3 is enabled, 0 = Mode 3 is disabled 0 MODE4 Low stress staged start mode (Mode 4) status; 1 = Mode 4 is enabled, 0 = Mode 4 is disabled Rev. A For more information www.analog.com 67 LTC4284 APPLICATIONS INFORMATION Table6. INPUT_STATUS Register (0x02) - Read Only BIT NAME OPERATION 7 PGIO1_INPUT State of PGIO1 pin; 1 = PGIO1 high, 0 = PGIO1 low 6 PGIO2_INPUT State of PGIO2 pin; 1 = PGIO2 high, 0 = PGIO2 low 5 PGIO3_INPUT State of PGIO3 pin; 1 = PGIO3 high, 0 = PGIO3 low 4 PGIO4_INPUT State of PGIO4 pin; 1 = PGIO4 high, 0 = PGIO4 low 3 ADIO1_INPUT State of ADIO1 pin; 1 = ADIO1 high, 0 = ADIO1 low 2 ADIO2_INPUT State of ADIO2 pin; 1 = ADIO2 high, 0 = ADIO2 low 1 ADIO3_INPUT State of ADIO3 pin; 1 = ADIO3 high, 0 = ADIO3 low 0 ADIO4_INPUT State of ADIO4 pin; 1 = ADIO4 high, 0 = ADIO4 low Table7. FAULT_STATUS Register (0x03) - Read Only BIT NAME OPERATION 7 EXT_FAULT_STATUS State of PGIO4 pin when configured to EXT_ FAULT#/EXT_FAULT; 1 = PGIO4 low/high, 0 = PGIO4 high/low 6 FET_SHORT_STATUS FET short status; 1 = FET shorted, 0 = FET not shorted 5 VOUT_LOW VOUT low status; 1 = VOUT < VOUTTH, 0 = VOUT VOUTTH 4 PGI_STATUS State of PGIO3 when configured to PGI#/PGI when PGI check timer expires; 1 = PGIO3 high/low, 0 = PGIO3 low/high 3 FET_BAD_STATUS FET bad status; 1 = FET bad condition present, 0 = FET bad condition not present 2 OC_STATUS Active current limit status; 1 = active current limit engaged, 0 = active current limit not engaged 1 UV_STATUS Input undervoltage status; 1 = UVH and UVL are low, 0 = UVH or UVL high 0 OV_STATUS Input overvoltage status; 1 = OV high, 0 = OV low Table8. FAULT Register (0x04) - Read/Write BIT NAME OPERATION DEFAULT 7 EXT_FAULT External fault at PGIO4 pin; 1 = external fault detected, 0 = no external fault 0 6 FET_SHORT_FAULT FET short fault; 1 = FET short fault occurred, 0 = no FET short fault 0 5 POWER_FAILED VOUT was low after power good latched; 1 = VOUT low detected, 0 = VOUT has not been low 0 4 PGI_FAULT PGI fault at PGIO3 pin; 1 = PGI fault occurred, 0 = no PGI fault 0 3 FET_BAD_FAULT FET bad fault; 1 = FET bad fault occurred, 0 = no FET bad fault 0 2 OC_FAULT Overcurrent fault; 1 = overcurrent fault occurred, 0 = no overcurrent fault 0 1 UV_FAULT Undervoltage fault; 1 = undervoltage fault occurred, 0 = no undervoltage fault 0 0 OV_FAULT Overvoltage fault; 1 = overvoltage fault occurred, 0 = no overvoltage fault 0 68 Rev. A For more information www.analog.com LTC4284 APPLICATIONS INFORMATION Table9. ADC_ALARM_LOG Registers (0x05-0x09) - Read/Write BIT NAME OPERATION DEFAULT ADC_ALARM_LOG_1 (0x05) - Read/Write 7 EN#_CHANGED EN# pin changed state; 1 = EN# changed state, 0 = EN# unchanged 0 6 EEPROM_WRITTEN EEPROM was written through I2C; 1 = EEPROM was written, 0 = EEPROM write has not been written 0 5 SENSE_HIGH_ALARM ADC+ - ADC- was above SENSE_MAX_TH; 1 = ADC+ - ADC- was high, 0 = ADC+ - ADC- has not been high 0 4 SENSE_LOW_ALARM ADC+ - ADC- was below SENSE_MIN_TH; 1 = ADC+ - ADC- was low, 0 = ADC+ - ADC- has not been low 0 3 VPWR_HIGH_ALARM VPWR was above VPWR_MAX_TH; 1 = VPWR was high, 0 = VPWR has not been high 0 2 VPWR_LOW_ALARM VPWR was below VPWR_MIN_TH; 1 = VPWR was low, 0 = VPWR has not been low 0 1 POWER_HIGH_ALARM POWER was above POWER_MAX_TH; 1 = POWER was high, 0 = POWER has not been high 0 0 POWER_LOW_ALARM POWER was below POWER_MIN_TH; 1 = POWER was low, 0 = POWER has not been low 0 ADC_ALARM_LOG_2 (0x06) - Read/Write 7 ADIN1_HIGH_ALARM ADIN1 was above ADIN1_MAX_TH; 1 = ADIN1 was high, 0 = ADIN1 has not been high 0 6 ADIN1_LOW_ALARM ADIN1 was below ADIN1_MIN_TH; 1 = ADIN1 was low, 0 = ADIN1 has not been low 0 5 ADIN2_HIGH_ALARM ADIN2 was above ADIN2_MAX_TH; 1 = ADIN2 was high, 0 = ADIN2 has not been high 0 4 ADIN2_LOW_ALARM ADIN2 was below ADIN2_MIN_TH; 1 = ADIN2 was low, 0 = ADIN2 has not been low 0 3 ADIN3_HIGH_ALARM ADIN3 was above ADIN3_MAX_TH; 1 = ADIN3 was high, 0 = ADIN3 has not been high 0 2 ADIN3_LOW_ALARM ADIN3 was below ADIN3_MIN_TH; 1 = ADIN3 was low, 0 = ADIN3 has not been low 0 1 ADIN4_HIGH_ALARM ADIN4 was above ADIN4_MAX_TH; 1 = ADIN4 was high, 0 = ADIN4 has not been high 0 0 ADIN4_LOW_ALARM ADIN4 was below ADIN4_MIN_TH; 1 = ADIN4 was low, 0 = ADIN4 has not been low 0 ADC_ALARM_LOG_3 (0x07) - Read/Write 7 ADIO1_HIGH_ALARM ADIO1 was above ADIO1_MAX_TH; 1 = ADIO1 was high, 0 = ADIO1 has not been high 0 6 ADIO1_LOW_ALARM ADIO1 was below ADIO1_MIN_TH; 1 = ADIO1 was low, 0 = ADIO1 has not been low 0 5 ADIO2_HIGH_ALARM ADIO2 was above ADIO2_MAX_TH; 1 = ADIO2 was high, 0 = ADIO2 has not been high 0 4 ADIO2_LOW_ALARM ADIO2 was below ADIO2_MIN_TH; 1 = ADIO2 was low, 0 = ADIO2 has not been low 0 3 ADIO3_HIGH_ALARM ADIO3 was above ADIO3_MAX_TH; 1 = ADIO3 was high, 0 = ADIO3 has not been high 0 2 ADIO3_LOW_ALARM ADIO3 was below ADIO3_MIN_TH; 1 = ADIO3 was low, 0 = ADIO3 has not been low 0 1 ADIO4_HIGH_ALARM ADIO4 was above ADIO4_MAX_TH; 1 = ADIO4 was high, 0 = ADIO4 has not been high 0 0 ADIO4_LOW_ALARM ADIO4 was below ADIO4_MIN_TH; 1 = ADIO4 was low, 0 = ADIO4 has not been low 0 Rev. A For more information www.analog.com 69 LTC4284 APPLICATIONS INFORMATION BIT NAME OPERATION DEFAULT ADC_ALARM_LOG_4 (0x08) - Read/Write 7 DRNS_HIGH_ALARM DRNS was above DRNS_MAX_TH; 1 = DRNS was high, 0 = DRNS has not been high 0 6 DRNS_LOW_ALARM DRNS was below DRNS_MIN_TH; 1 = DRNS was low, 0 = DRNS has not been low 0 5 DRAIN_HIGH_ALARM DRAIN was above DRAIN_MAX_TH; 1 = DRAIN was high, 0 = DRAIN has not been high 0 4 DRAIN_LOW_ALARM DRAIN was below DRAIN_MIN_TH; 1 = DRAIN was low, 0 = DRAIN has not been low 3 SENSE1_HIGH_ALARM SENSE1+ - SENSE1- was above SENSE1_MAX_TH; 1 = SENSE1+ - SENSE1- was high, 0 = SENSE1+ - SENSE1- has not been high 0 2 SENSE1_LOW_ALARM SENSE1+ - SENSE1- was below SENSE1_MIN_TH; 1 = SENSE1+ - SENSE1- was low, 0 = SENSE1+ - SENSE1- has not been low 0 1 SENSE2_HIGH_ALARM SENSE2+ - SENSE2- was above SENSE2_MAX_TH; 1 = SENSE2+ - SENSE2- was high, 0 = SENSE2+ - SENSE2- has not been high 0 0 SENSE2_LOW_ALARM SENSE2+ - SENSE2- was below SENSE2_MIN_TH; 1 = SENSE2+ - SENSE2- was low, 0 = SENSE2+ - SENSE2- has not been low 0 0 ADC_ALARM_LOG_5 (0x09) - Read/Write 7 ADIN12_HIGH_ALARM ADIN2 - ADIN1 was above ADIN12_MAX_TH; 1 = ADIN2 - ADIN1 was high, 0 = ADIN2 - ADIN1 has not been high 0 6 ADIN12_LOW_ALARM ADIN2 - ADIN1 was below ADIN12_MIN_TH; 1 = ADIN2 - ADIN1 was low, 0 = ADIN2 - ADIN1 has not been low 0 5 ADIN34_HIGH_ALARM ADIN4 - ADIN3 was above ADIN34_MAX_TH; 1 = ADIN4 - ADIN3 was high, 0 = ADIN4 - ADIN3 has not been high 0 4 ADIN34_LOW_ALARM ADIN4 - ADIN3 was below ADIN34_MIN_TH; 1 = ADIN4 - ADIN3 was low, 0 = ADIN4 - ADIN3 has not been low 0 3 ADIO12_HIGH_ALARM ADIO2 - ADIO1 was above ADIO12_MAX_TH; 1 = ADIO2 - ADIO1 was high, 0 = ADIO2 - ADIO1 has not been high 0 2 ADIO12_LOW_ALARM ADIO2 - ADIO1 was below ADIO12_MIN_TH; 1 = ADIO2 - ADIO1 was low, 0 = ADIO2 - ADIO1 has not been low 0 1 ADIO34_HIGH_ALARM ADIO4 - ADIO3 was above ADIO34_MAX_TH; 1 = ADIO4 - ADIO3 was high, 0 = ADIO4 - ADIO3 has not been high 0 0 ADIO34_LOW_ALARM ADIO4 - ADIO3 was below ADIO34_MIN_TH; 1 = ADIO4 - ADIO3 was low, 0 = ADIO4 - ADIO3 has not been low 0 70 Rev. A For more information www.analog.com LTC4284 APPLICATIONS INFORMATION Table10. CONTROL Registers (0x0A-0x0B) - Read/Write BIT NAME OPERATION DEFAULT CONTROL_1 (0x0A) - Read/Write 7 ON Turns MOSFET on and off; 1 = turn MOSFET on, 0 = turn MOSFET off 1 6 DVDT Enables dV/dt inrush control during startup; 1 = enabled, 0 = disabled 1 5 THERM_TMR Turns 2a TMR pull-down off; 1 = TMR pull-down turned off, 0 = TMR pull-down turned on 0 4 FET_BAD_TURN_OFF Turns MOSFET off following a FET_BAD_FAULT; 1 = turn MOSFET off, 0 = keep MOSFET on 1 3 PWRGD_RESET_ CNTRL Configures power good reset; 1 = reset by VOUT low, 0 = reset by MOSFET off 1 2 PGIO2_ACLB Configures PGIO2; 1 = PGIO2 as inverted output for active current limit engagement after startup; 0 = normal PGIO2 function configured by 0x10 bit[3:2] 0 1 MASS_WRITE_ ENABLE Enables mass write to all LTC4284S on the I2C bus; 1 = enabled, 0 = disabled 1 0 PAGE_READ_WRITE_ ENABLE Enables I2C page read/write protocols; 1 = enabled, 0 = disabled 1 CONTROL_2 (0x0B) - Read/Write 7 EXT_FAULT_RETRY Enables auto-retry following an EXT_FAULT; 1 = unlimited retries, 0 = no retry (latch-off) 0 6 PGI_RETRY Enables auto-retry following a PGI_FAULT; 1 = unlimited retries, 0 = no retry (latch-off) 0 FET_BAD_RETRY Configures auto-retry following a FET_BAD_FAULT and MOSFET turn off 00 5:4 3:2 OC_RETRY FET_BAD_RETRY [5:4] Number of Retries 00 0 (Latch-Off) 01 1 10 7 11 Unlimited Configures auto-retry following an OC_FAULT OC_RETRY [3:2] Number of Retries 00 0 (Latch-Off) 01 1 10 7 11 Unlimited 00 1 UV_RETRY Enables auto-retry following a UV_FAULT; 1 = unlimited retries, 0 = no retry (latch-off) 1 0 OV_RETRY Enables auto-retry following an OV_FAULT; 1 = unlimited retries, 0 = no retry (latch-off) 1 Rev. A For more information www.analog.com 71 LTC4284 APPLICATIONS INFORMATION Table11. CONFIG Registers (0x0D-0x0F) - Read/Write BIT NAME OPERATION DEFAULT CONFIG_1 (0x0D) - Read/Write 7:4 3:2 ILIM FB Configures VILIM and VILIM(FAST) 0000 ILIM [7:4] VILIM [mV] VILIM(FAST) [mV] 0000 15 30 0001 16 32 0010 17 34 0011 18 36 0100 19 38 0101 20 40 0110 21 42 0111 22 44 1000 23 46 1001 24 48 1010 25 50 1011 26 52 1100 27 54 1101 28 56 1110 29 58 1111 30 60 Configures current limit foldback factor for startup and normal operation FB [3:2] Foldback Factor, [% VILIM] 00 100 (foldback disabled) 01 50 10 20 11 10 11 1 FB_DIS Disables foldback after startup; 1 = disabled, 0 = enabled. Foldback during startup is not affected 0 0 LPFB Enables load power foldback after startup; 1 = enabled, 0 = disabled 0 Configures DRAIN voltage threshold for starting FET bad fault filtering timer, VD,FET(TH) 11 CONFIG_2 (0x0E) - Read/Write 7:6 VDTH VDTH [7:6] 72 VD,FET(TH) [mV] 00 72 01 102 10 143 11 203 Rev. A For more information www.analog.com LTC4284 APPLICATIONS INFORMATION BIT NAME OPERATION 5:4 FTBD_DL Configures FET_Bad fault filtering timer delay, tDL(FETBAD) 3:1 0 COOLING_DL PORB DEFAULT FTBD_DL [5:4] tDL(FETBAD) [s] 00 0.256 01 0.512 10 1.02 11 2.05 Configures cooling delay preceding each auto-retry following OC_FAULT, FET_BAD_FAULT or EXT_FAULT, tDL(RTRY) COOLING_DL [3:1] tDL(RTRY) [s] 000 0.512 001 1.02 010 2.05 011 4.10 100 8.19 101 16.4 110 32.8 111 65.5 Resets to 0 upon power-on reset. Write this bit to 1 to use it as power-on reset indicator: 1 = power-on reset has not occurred, 0 = power-on reset occurred 00 000 0 CONFIG_3 (0x0F) - Read/Write BIT NAME OPERATION 7 EXTFLT_TURN_OFF Turns MOSFET off following an external fault; 1 = turn MOSFET off, 0 = keep MOSFET on 0 6 VPWR_SELECT Selects voltage for ADC power multiplication; 1 = selects DRNS (attenuated drain voltage for MOSFET power), 0 = selects RTNS (attenuated input voltage for input power) 0 5 FAST_I2C_EN Enables fast I2C mode; 1 = fast I2C enabled, 0 = fast I2C disabled 0 BC Configures bit rate of single-wire broadcast mode, fBC 00 4:3 2 TICK_OVERFLOW_ ALERT DEFAULT BC [4:3] fBC [kbit/s] 00 2048 01 512 10 128 (Not available for 8-bit ADC) 11 32 (Not available for 8-bit ADC) Enables alert when tick counter overflows; 1 = alert enabled, 0 = alert disabled 0 1 METER_OVERFLOW_ ALERT Enables alert when energy meter overflows; 1 = alert enabled, 0 = alert disabled 0 0 INTEGRATE_I Enables integration of current; 1 = integrate current, 0 = integrate power 0 Rev. A For more information www.analog.com 73 LTC4284 APPLICATIONS INFORMATION Table12. PGIO_CONFIG Registers (0x10:0x11) - Read/Write BIT NAME OPERATION DEFAULT PGIO_CONFIG_1 (0x10) - Read/Write 7:6 5:4 3:2 1:0 PGIO4_CONFIG PGIO3_CONFIG PGIO2_CONFIG PGIO1_CONFIG Configures behavior of PGIO4 pin 00 PGIO4_CONFIG [7:6] PGIO4 00 EXT_FAULT# 01 EXT_FAULT 10 General purpose output 11 General purpose input Configures behavior of PGIO3 pin 00 PGIO3_CONFIG [5:4] PGIO3 00 PGI# 01 PGI 10 General purpose output 11 General purpose input Configures behavior of PGIO2 pin 00 PGIO2_CONFIG [3:2] PGIO2 00 Power Good 2# 01 Power Good 2 10 General purpose output 11 General purpose input Configures behavior of PGIO1 pin 00 PGIO1_CONFIG [1:0] PGIO1 00 Power Good 1# 01 Power Good 1 10 General purpose output 11 General purpose input PGIO_CONFIG_2 (0x11) - Read/Write 7 PGIO4_OUT Output data bit to PGIO4 pin when configured as general purpose output 0 6 PGIO3_OUT Output data bit to PGIO3 pin when configured as general purpose output 0 5 PGIO2_OUT Output data bit to PGIO2 pin when configured as general purpose output 0 4 PGIO1_OUT Output data bit to PGIO1 pin when configured as general purpose output 0 3 2:0 ADC_CONV_ALERT Enables alert when ADC finishes making a conversion; 1 = enable alert, 0 = disable alert ADC Configures ADC resolution and conversion rate 74 0 100 ADC [2:0] ADC Resolution [Bits] ADC Conversion Rate fCONV [Hz] Sampling Clock Frequency fs [kHz] 000 8 996 512 010 10 125 256 100 12 15.6 128 110 14 3.91 128 xx1 16 0.977 128 Rev. A For more information www.analog.com LTC4284 APPLICATIONS INFORMATION Table13. ADIO_CONFIG Register (0x12) - Read/Write BIT NAME OPERATION DEFAULT 7 ADIO4_CONFIG Configures behavior of ADIO4 pin; 1 = general purpose input, 0 = general purpose output 1 6 ADIO3_CONFIG Configures behavior of ADIO3 pin; 1 = general purpose input, 0 = general purpose output 1 5 ADIO2_CONFIG Configures behavior of ADIO2 pin; 1 = general purpose input, 0 = general purpose output 1 4 ADIO1_CONFIG Configures behavior of ADIO1 pin; 1 = general purpose input, 0 = general purpose output 1 3 ADIO4_OUT Output data bit to ADIO4 pin when configured as general purpose output 0 2 ADIO3_OUT Output data bit to ADIO3 pin when configured as general purpose output 0 1 ADIO2_OUT Output data bit to ADIO2 pin when configured as general purpose output 0 0 ADIO1_OUT Output data bit to ADIO1 pin when configured as general purpose output 0 Table14. ADC_SELECT Registers (0x13-0x14) - Read/Write BIT NAME OPERATION DEFAULT ADC_SELECT_1 (0x13) - Read/Write 7 ADIO4_SELECT Selects ADIO4 as input for ADC measurement; 1 = selected, 0 = not selected 1 6 ADIO3_SELECT Selects ADIO3 as input for ADC measurement; 1 = selected, 0 = not selected 1 5 ADIO2_SELECT Selects ADIO2 as input for ADC measurement; 1 = selected, 0 = not selected 1 4 ADIO1_SELECT Selects ADIO1 as input for ADC measurement; 1 = selected, 0 = not selected 1 3 ADIN4_SELECT Selects ADIN4 as input for ADC measurement; 1 = selected, 0 = not selected 1 2 ADIN3_SELECT Selects ADIN3 as input for ADC measurement; 1 = selected, 0 = not selected 1 1 ADIN2_SELECT Selects ADIN2 as input for ADC measurement; 1 = selected, 0 = not selected 1 0 ADIN1_SELECT Selects ADIN1 as input for ADC measurement; 1 = selected, 0 = not selected 1 ADC_SELECT_2 (0x14) - Read/Write 7 ADIO34_SELECT Selects ADIO4 - ADIO3 as input for ADC measurement; 1 = selected, 0 = not selected 0 6 ADIO12_SELECT Selects ADIO2 - ADIO1 as input for ADC measurement; 1 = selected, 0 = not selected 0 5 ADIN34_SELECT Selects ADIN4 - ADIN3 as input for ADC measurement; 1 = selected, 0 = not selected 0 4 ADIN12_SELECT Selects ADIN2 - ADIN1 as input for ADC measurement; 1 = selected, 0 = not selected 0 1 3 SENSE2_SELECT Selects SENSE2+ - SENSE2- as input for ADC measurement; 1 = selected, 0 = not selected 2 SENSE1_SELECT Selects SENSE1+ - SENSE1- as input for ADC measurement; 1 = selected, 0 = not selected 1 1 DRAIN_SELECT Selects DRAIN as input for ADC measurement; 1 = selected, 0 = not selected 1 0 DRNS_SELECT Selects DRNS as input for ADC measurement; 1 = selected, 0 = not selected 1 Table15. FAULT_ALERT Register (0x15) - Read/Write BIT NAME OPERATION DEFAULT 7 EXT_FAULT_ALERT Enables alert for external fault; 1 = enable alert, 0 = disable alert 0 6 FET_SHORT_ALERT Enables alert for FET short fault; 1 = enable alert, 0 = disable alert 0 5 POWER_FAILED_ ALERT Enables alert for power failed fault; 1 = enable alert, 0 = disable alert 0 4 PGI_ALERT Enables alert for PGI fault; 1 = enable alert, 0 = disable alert 0 3 FET_BAD_ALERT Enables alert for FET bad fault; 1 = enable alert, 0 = disable alert 0 2 OC_ALERT Enables alert for overcurrent fault; 1 = enable alert, 0 = disable alert 0 1 UV_ALERT Enables alert for undervoltage fault; 1 = enable alert, 0 = disable alert 0 0 OV_ALERT Enables alert for overvoltage fault; 1 = enable alert, 0 = disable alert 0 Rev. A For more information www.analog.com 75 LTC4284 APPLICATIONS INFORMATION Table16. ADC_ALERT Registers (0x16-0x1A) - Read/Write BIT NAME OPERATION DEFAULT ADC_ALERT_1 (0x16) - Read/Write 7 EN#_CHANGED_ALERT Enables alert when EN# pin changed state; 1 = enable alert, 0 = disable alert 0 6 EEPROM_WRITTEN_ALERT Enables alert when EEPROM is written through I2C; 1 = enable alert, 0 = disable alert 0 5 SENSE_HIGH_ALERT Enables alert when ADC+ - ADC- was above SENSE_MAX_TH; 1 = enable alert, 0 = disable alert 0 4 SENSE_LOW_ALERT Enables alert when ADC+ - ADC- was below SENSE_MIN_TH; 1 = enable alert, 0 = disable alert 0 3 VPWR_HIGH_ALERT Enables alert when VPWR was above VPWR_MAX_TH; 1 = enable alert, 0 = disable alert 0 2 VPWR_LOW_ALERT Enables alert when VPWR was below VPWR_MIN_TH; 1 = enable alert, 0 = disable alert 0 1 POWER_HIGH_ALERT Enables alert when POWER was above POWER_MAX_TH; 1 = enable alert, 0 = disable alert 0 0 POWER_LOW_ALERT Enables alert when POWER was below POWER_MIN_TH; 1 = enable alert, 0 = disable alert 0 ADC_ALERT_2 (0x17) - Read/Write 7 ADIN1_HIGH_ALERT Enables alert when ADIN1 was above ADIN1_MAX_TH; 1 = enable alert, 0 = disable alert 0 6 ADIN1_LOW_ALERT Enables alert when ADIN1 was below ADIN1_MIN_TH; 1 = enable alert, 0 = disable alert 0 5 ADIN2_HIGH_ALERT Enables alert when ADIN2 was above ADIN2_MAX_TH; 1 = enable alert, 0 = disable alert 0 4 ADIN2_LOW_ALERT Enables alert when ADIN2 was below ADIN2_MIN_TH; 1 = enable alert, 0 = disable alert 0 3 ADIN3_HIGH_ALERT Enables alert when ADIN3 was above ADIN3_MAX_TH; 1 = enable alert, 0 = disable alert 0 2 ADIN3_LOW_ALERT Enables alert when ADIN3 was below ADIN3_MIN_TH; 1 = enable alert, 0 = disable alert 0 1 ADIN4_HIGH_ALERT Enables alert when ADIN4 was above ADIN4_MAX_TH; 1 = enable alert, 0 = disable alert 0 0 ADIN4_LOW_ALERT Enables alert when ADIN4 was below ADIN4_MIN_TH; 1 = enable alert, 0 = disable alert 0 ADC_ALERT_3 (0x18) - Read/Write 7 ADIO1_HIGH_ALERT Enables alert when ADIO1 was above ADIO1_MAX_TH; 1 = enable alert, 0 = disable alert 0 6 ADIO1_LOW_ALERT Enables alert when ADIO1 was below ADIO1_MIN_TH; 1 = enable alert, 0 = disable alert 0 5 ADIO2_HIGH_ALERT Enables alert when ADIO2 was above ADIO2_MAX_TH; 1 = enable alert, 0 = disable alert 0 4 ADIO2_LOW_ALERT Enables alert when ADIO2 was below ADIO2_MIN_TH; 1 = enable alert, 0 = disable alert 0 3 ADIO3_HIGH_ALERT Enables alert when ADIO3 was above ADIO3_MAX_TH; 1 = enable alert, 0 = disable alert 0 2 ADIO3_LOW_ALERT Enables alert when ADIO3 was below ADIO3_MIN_TH; 1 = enable alert, 0 = disable alert 0 1 ADIO4_HIGH_ALERT Enables alert when ADIO4 was above ADIO4_MAX_TH; 1 = enable alert, 0 = disable alert 0 0 ADIO4_LOW_ALERT Enables alert when ADIO4 was below ADIO4_MIN_TH; 1 = enable alert, 0 = disable alert 0 76 Rev. A For more information www.analog.com LTC4284 APPLICATIONS INFORMATION BIT NAME OPERATION DEFAULT ADC_ALERT_4 (0x19) - Read/Write 7 DRNS_HIGH_ALERT Enables alert when DRNS was above DRNS_MAX_TH; 1 = enable alert, 0 = disable alert 0 6 DRNS_LOW_ALERT Enables alert when DRNS was below DRNS_MIN_TH; 1 = enable alert, 0 = disable alert 0 5 DRAIN_HIGH_ALERT Enables alert when DRAIN was above DRAIN_MAX_TH; 1 = enable alert, 0 = disable alert 0 4 DRAIN_LOW_ALERT Enables alert when DRAIN was below DRAIN_MIN_TH; 1 = enable alert, 0 = disable alert 0 3 SENSE1_HIGH_ALERT Enables alert when SENSE1+ - SENSE1- was above SENSE1_MAX_TH; 1 = enable alert, 0 = disable alert 0 2 SENSE1_LOW_ALERT Enables alert when SENSE1+ - SENSE1- was below SENSE1_MIN_TH; 1 = enable alert, 0 = disable alert 0 1 SENSE2_HIGH_ALERT Enables alert when SENSE2+ - SENSE2- was above SENSE2_MAX_TH; 1 = enable alert, 0 = disable alert 0 0 SENSE2_LOW_ALERT Enables alert when SENSE2+ - SENSE2- was below SENSE2_MIN_TH; 1 = enable alert, 0 = disable alert 0 ADC_ALERT_5 (0x1A) - Read/Write 7 ADIN12_HIGH_ALERT Enables alert when ADIN2 - ADIN1 was above ADIN12_MAX_TH; 1 = enable alert, 0 = disable alert 0 6 ADIN12_LOW_ALERT Enables alert when ADIN2 - ADIN1 was below ADIN12_MIN_TH; 1 = enable alert, 0 = disable alert 0 5 ADIN34_HIGH_ALERT Enables alert when ADIN4 - ADIN3 was above ADIN34_MAX_TH; 1 = enable alert, 0 = disable alert 0 4 ADIN34_LOW_ALERT Enables alert when ADIN4 - ADIN3 was below ADIN34_MIN_TH; 1 = enable alert, 0 = disable alert 0 3 ADIO12_HIGH_ALERT Enables alert when ADIO2 - ADIO1 was above ADIO12_MAX_TH; 1 = enable alert, 0 = disable alert 0 2 ADIO12_LOW_ALERT Enables alert when ADIO2 - ADIO1 was below ADIO12_MIN_TH; 1 = enable alert, 0 = disable alert 0 1 ADIO34_HIGH_ALERT Enables alert when ADIO4 - ADIO3 was above ADIO34_MAX_TH; 1 = enable alert, 0 = disable alert 0 0 ADIO34_LOW_ALERT Enables alert when ADIO4 - ADIO3 was below ADIO34_MIN_TH; 1 = enable alert, 0 = disable alert 0 Table17. ENERGY Registers (0x7A-0x7F) - Read/Write BIT NAME OPERATION DEFAULT 47:0 ENERGY Data of metered energy 0x0000_0000_0000 Table18. TICK_COUNTER Registers (0x80-0x83) - Read/Write BIT NAME OPERATION DEFAULT 31:0 TICK_COUNTER Counts number of ADC conversion cycles that power measurements have been accumulated in the energy meter 0x0000_0000 Table19. METER_CONTROL Register (0x84) - Read/Write BIT NAME OPERATION 7 METER_RESET Resets energy meter and tick counter until cleared; 1 = reset, 0 = reset cleared DEFAULT 0 6 METER_HALT Halts energy meter and tick counter from accumulating; 1 = halted, 0 = not halted 0 5 TICK_OVERFLOW Tick counter has overflowed; 1 = overflowed, 0 = not overflowed 0 4 METER_OVERFLOW Energy meter accumulator has overflowed; 1 = overflowed, 0 = not overflowed 0 3 ALERT_GENERATED Latched to 1 when an alert is generated and can only be cleared via I2C; 1 = alert generated, 0 = alert has not been generated 0 2 EE_LOCK EEPROM lock status, read only; 1 = EEPROM is factory locked, 0 = EEPROM is not factory locked 0 1:0 Reserved Read only, always returns 0 00 Rev. A For more information www.analog.com 77 LTC4284 APPLICATIONS INFORMATION Table20. ADC_SNAPSHOT Register (0x85) -- Read/Write BIT NAME OPERATION 7:4 SNAPSHOT_SEL Selects one of the 16 ADC auxiliary inputs for snapshot measurement 3 2:0 DEFAULT SNAPSHOT_SEL [7:4] Auxiliary ADC Input 0000 ADIN1 0001 ADIN2 0010 ADIN3 0011 ADIN4 0100 ADIO1 0101 ADIO2 0110 ADIO3 0111 ADIO4 1000 DRNS 1001 DRAIN 1010 SENSE1+ - SENSE1- 1011 SENSE2+ - SENSE2- 1100 ADIN2 - ADIN1 1101 ADIN4 - ADIN3 1110 ADIO2 - ADIO1 1111 ADIO4 - ADIO3 ADC_HALT Enables ADC snapshot mode; 1 = snapshot, 0 = continuous conversion Reserved Read only, always returns 0 0000 0 000 Table21. FAULT_LOG_CONTROL Register (0x90) - Read/Write BIT NAME OPERATION 7 FAULT_LOG_ENABLE Enables logging fault registers and ADC data into EEPROM upon a fault; this bit can only be cleared using I2C; 1 = fault log enabled, 0 = fault log disabled 0 6 FAULT_LOG_UNLOCK Allows clearing of FAULT_LOG_START and FAULT_LOG_DONE bits to re-enable fault log following a previous fault log; 1 = clearing allowed, 0 = clearing not allowed 0 5 FAULT_LOG_START Indicates a fault log is started; I2C can not set this bit but can clear it; 1 = fault log started, 0 = fault log has not been started 0 4 FAULT_LOG_DONE Indicates a fault log is completed; I2C can not set this bit but can clear it; 1 = fault log completed, 0 = fault log has not been completed 0 3 FAULT_LOG_ALERT Enables alert when a fault log is completed; 1 = enable alert, 0 = disable alert 0 Reserved Read only, always returns 0 2:0 78 DEFAULT 000 Rev. A For more information www.analog.com LTC4284 APPLICATIONS INFORMATION Table22. Registers Recorded to EEPROM During Fault Log REGISTER NAME REGISTER ADDRESS EEPROM ADDRESS DATA LENGTH (BYTES) 0x04 0xA4 1 System fault FAULT ADC_ALARM_LOG DESCRIPTION 0x05-0x09 0xA5-0xA9 5 ADC measurement alarms SENSE 0x41 0xE1 1 MSB byte of most recent ADC output for ADC+ - ADC- SENSE_MIN 0x42 0xE2 1 MSB byte of minimum ADC output for ADC+ - ADC- SENSE_MAX 0x43 0xE3 1 MSB byte of maximum ADC output for ADC+ - ADC- VPWR 0x44 0xE4 1 MSB byte of most recent ADC output for VPWR voltage VPWR_MIN 0x45 0xE5 1 MSB byte of minimum ADC output for VPWR voltage VPWR_MAX 0x46 0xE6 1 MSB byte of maximum ADC output for VPWR voltage Table23. REBOOT Register (0xA2) - Read/Write BIT NAME OPERATION 7 RBT_EN Controls auto-reboot; 1 = reboot after delay tDL(RBT), 0 = no reboot. When set to 1, this bit remains 1 after reboot is done. Clear it before issuing the next reboot command 6:4 RBT_DL Configures delay for auto-reboot, tDL(RBT), after the REBOOT bit is set to 1 3:2 DEFAULT RBT_DL [6:4] tDL(RBT) [s] 000 0.512 001 1.02 010 2.05 011 4.10 100 8.19 101 16.4 110 32.8 111 65.5 0 000 Reserved Read only, always returns 0 00 1 DELAY_STATUS Reboot and cooling delay status; 1 = device is going through a reboot or cooling delay or in latchoff, 0 = reboot or cooling delay has expired or has not been initiated 0 0 WP_STATUS WP pin status; 1 = WP is high, 0 = WP pin is low 0 Table24. Mapping between Faults/Alarms and Alert Masks FAULT/ALARM ALERT MASK FAULT 0x04 [7:0] FAULT_ALERT 0x15 [7:0] ADC_ALARM_LOG_1 0x05 [7:0] ADC_ALERT_1 0x16 [7:0] ADC_ALARM_LOG_2 0x06 [7:0] ADC_ALERT_2 0x17 [7:0] ADC_ALARM_LOG_3 0x07 [7:0] ADC_ALERT_3 0x18 [7:0] ADC_ALARM_LOG_4 0x08 [7:0] ADC_ALERT_4 0x19 [7:0] ADC_ALARM_LOG_5 0x09 [7:0] ADC_ALERT_5 0x1A [7:0] METER_CONTROL 0x84[4:3] CONFIG_3 0x0F [2:1] ADC Conversion Completed PGIO_CONFIG_2 0x11 [3] EEPROM Fault Log Completed FAULT_LOG_CONTROL 0x90 [3] Rev. A For more information www.analog.com 79 LTC4284 PACKAGE DESCRIPTION UHG Package 44-Lead Plastic QFN (5mm x 8mm) (Reference LTC DWG # 05-08-1581 Rev O) 6.50 REF 0.70 0.05 5.50 0.05 3.55 0.05 4.10 0.05 3.50 REF 6.55 0.05 PACKAGE OUTLINE 1.00 BSC 0.25 0.05 0.50 BSC 7.10 0.05 8.50 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED R = 0.125 TYP 0.75 0.05 5.00 0.10 PIN 1 NOTCH R = 0.30 TYP OR 0.35 x 45 CHAMFER 43 44 0.00 - 0.05 0.40 0.10 PIN 1 TOP MARK (SEE NOTE 6) 1 2 0.25 0.05 6.55 0.10 6.50 REF 8.00 0.10 0.50 BSC 3.55 0.10 DETAIL A 0.325 REF 0.200 REF (UHG44) QFN 0417 REV 0 3.50 REF BOTTOM VIEW--EXPOSED PAD DETAIL A 0.08 REF 0.75 0.05 0.31 REF 0.00 - 0.05 NOTE: 1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 80 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE Rev. A For more information www.analog.com LTC4284 REVISION HISTORY REV DATE DESCRIPTION A 01/20 Added patent number 10263414. PAGE NUMBER 1 Changed RTN to VZ resistor value from 1W to 0.25W in figure. 1 ,19, 32, 34, 36 Changed all register names with RTNS reference to VPWR (i.e. RTNS_MIN changed to VPWR_MIN). 62, 63, 65, 69, 76, 79 Corrected bit number for METER_CONTROL Reserved register. Added METER_CONTROL EE_LOCK register bit. 77 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license For is granted implication or otherwise under any patent or patent rights of Analog Devices. more by information www.analog.com 81 LTC4284 TYPICAL APPLICATION -48V RTN -48V RTN (SHORT PIN) RRT 200k 1% RZ 100k R3 487k 1% R2 14.3k 1% RTH1: TDK NTCG064BH103JTB T(C) = (55 x ADIO4 ADC READING x 31.25E-06) - 28 CVCC 1F RTH2 20k 1% VEE RTNS MODE VZ VIN INTVCC SCL SDAI ADR1 ADR0 SDAO ADIO4 LTC4284 OV R1 10k 1% CIN 0.1F VEE VEE UVH UVL QIN BCP56 CZ 0.1F RRB 5.11k 1% VEE 3 ADIO1-3 4 ADIN1-4 VEE 4 PGIO1-4 SENSE2- ADC- SENSE1- SENSE1+ ADC+ SENSE2+ GATE1 GATE2 DRAIN DRNS VEE RD 100k -48V INPUT RS1 0.5m BATTERY OPERATED (SUBJECT TO -36V INPUT STEPS) RA1- 1 RA1+ 1 RA2- 1 RA2+ 1 RTH3 2k 1% RTH4 2k 1% RTH1 10k AT 25C 3.3V R4 1k VDD1 VDD2 ADuM1100 VI VO GND1 VLOAD VDD MICROCONTROLLER DIN GND2 CL 1000F GND RDB 5.11k 1% RDT 200k 1% + - VEE VOUT M1 PSMN4R8-100BSE x2 M2 PSMN4R8-100BSE x2 RS2 0.5m 4284 F36 Figure36. -48V/1200W Hot Swap Controller Monitoring System Status, Faults, Currents, Voltages, Power and Temperature and Transmitting Data at 2MBit/s in Single-Wire Broadcast Mode RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC4283 -48V Hot Swap Controller with Energy Monitor SOA Timer, 8-Bit to 16-Bit ADC Monitors Current, Voltage, Power and Energy, Internal EEPROM, I2C or Single-Wire Broadcast LTC4261/LT4261-2 -48V Hot Swap Controller with ADC and I2C dV/dt Startup Inrush, 10-Bit ADC Monitors Voltages and Current, I2C or SingleWire Broadcast, Two Sequenced Power Good Outputs, Supplies from -12V 12-Bit ADC Monitors Current, Voltage, Power and Energy ADM1075 -48V Hot Swap Controller with PMBus LTC4282/LTC4281 High Current Positive Voltage Hot Swap Controller Dual/Single Gate Drive, 12-Bit or 16-Bit ADC Monitors Current, Voltage, Power and Energy, Internal EEPROM, I2C, Supplies from 2.9V to 33V with I2C Compatible Monitoring LT4250L/LT4250H -48V Hot Swap Controller in SO-8 Active Current Limiting, Supplies from -18V to -80V LTC4251/LTC4251-1 -48V Hot Swap Controller in SOT-23 Fast Active Current Limiting, supplies from -15V LTC4252-1/LTC4252-2/ -48V Hot Swap Controller in MS8 LTC4252A-1/LTC4252A-2 Fast Active Current Limiting, Supplies from -15V, 1% UV/OV (LTC4252A) LTC4253 -48V Hot Swap Controller with Sequencer Fast Current Limiting with Three Sequenced Power Good Outputs, Supplies from -15V LTC4260 Positive High Voltage Hot Swap Controller With I2C and 8-Bit ADC, Supplies from 8.5V to 80V LTC4371 Negative Voltage Diode-OR Controller Controls Two N-Channel MOSFETs, 220ns Turn-Off LTC4151 High Voltage Current and Voltage Monitor Operates from 7V to 80V, with I2C and 12-Bit ADC 82 Rev. A 01/20 www.analog.com For more information www.analog.com ANALOG DEVICES, INC. 2018-2020