30 W-Universal Input/45 W-230 Vac Input
PWM Switching Regulators
STR-W6251D
6
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Protection Operation
OCP Threshold Voltage at Zero
Duty Cycle (0% On-Duty) VOCP1 3-5
Set VFM = 0 V and increase VOCP. (VOCP1 is the S/OCP
terminal voltage level at which D/ST changes from
low to high) Measurement circuit 5
0.71 0.78 0.86 V
Drain Peak Current Compensation
Coefficient DPC –D
PC = –0.75× SLP / fOSC(av) 1.5 1.9 2.3 mV/
DC%
OCP Threshold Voltage After
Compensation VOCP2 3-5 VOCP2 = DPC × DMAX + VOCP1 0.82 0.93 1.04 V
Leading Edge Blanking Time tblank 1-5 (The low portion of the D/ST terminal waveform at
VOCP = 2 V) Measurement circuit 5 280 400 520 ns
OLP Delay Time tOLP 1-5 (Time between setting FB terminal open and when
oscillation stops) Measurement circuit 6 – 200 – ms
Circuit Current in OLP-Operation ICC (OLP) 4-5 (Inflow current into VCC terminal after OLP operation)
Measurement circuit 6 – 410 700 μA
OVP Protection Voltage VCC(OVP) 4-5
(VCC terminal voltage at which the voltage of D/ST
terminal is switched from low to high by decreasing
VFB after setting VFM = 0 V) Measurement circuit 1,
VCC = 18.0 V through 27 to 30 V
27 28.5 30 V
Latch Circuit Sustaining Current2ICC(La.H) 4-5 (Inflow current into VCC terminal after OVP operation)
Measurement circuit 1, VCC = 8 V – 140 220 μA
Latch Circuit Release Voltage2VCC(La.OFF) 4-5
(VCC voltage at which ICC is dropped below 20 μA by
decreasing VCC after OVP operation)
VCC = 31.0 V through 7.8 to 6.4 V
6.4 7.1 7.8 V
ELP Threshold Voltage VELP 7-5
(FM/ELP terminal voltage at which the oscillation of
the D/ST terminal waveform is stopped by increasing
VFM) Measurement circuit 2
6.4 7.1 7.8 V
Inflow Current at External Latch
Protection IELP 7-5 (Inflow current at VFM = VELP) Measurement circuit 2 – 55 100 μA
Thermal Shut Down Operating
Temperature TJTSD – 135 – – °C
Power MOSFET Characteristics
Drain-to-Source Breakdown Voltage VDSS 1-3 ID = 300 μA, Measurement circuit 8 650 – – V
Drain Leakage Current IDSS 1-3 VD = 650 V, Measurement circuit 7 – – 300 μA
ON-Resistance RDS(ON) 1-3 ID = 0.6 A, VFM = 0 V Measurement circuit 10 – – 3.95 Ω
Switching Time tr1-3 Measurement circuit 9 – – 400 ns
Thermal Resistance RθJ-F – Measured between junction and internal frame – – 2.23 °C/W
Single Pulse Avalanche Energy EAS – Measurement circuit 11 – – – –
1Input and output current polarity at the device pin; plus(+) represents sink and minus(–) represents source.
2The latch circuit means a circuit operated ELP, OVP, and TSD.
ELECTRICAL CHARACTERISTICS, continued, valid at VCC = 18 V, TA = 25°C, unless otherwise specified
Characteristic Symbol Terminal Test Conditions Min. Typ. Max Units