Sensors
10 Freescale Semiconductor, Inc.
MMA52xxAKW
2.8 Dynamic Electrical Characteristics - Supply and SPI
VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, ΔT ≤ 25 K/min, unless otherwise specified
1. Parameters tested 100% at final test.
2. Parameters tested 100% at wafer probe.
3. Verified by characterization
4. * Indicates critical characteristic.
5. Verified by qualification testing.
6. Parameters verified by pass/fail testing in production.
7. Functionality guaranteed by modeling, simulation and/or design verification. Circuit integrity assured through IDDQ and scan testing. Timing
is determined by internal system clock frequency.
8. N/A.
9. Verified by simulation.
10. N/A.
11. Measured at VCC pin; VSYNC guaranteed across full VIDLE range.
12. Self-Test repeats on failure up to a ST_RPTMAX times before transmitting Sensor Error Message.
13. N/A.
14. Thermal resistance between the die junction and the exposed pad; cold plate is attached to the exposed pad.
15. Filter cutoff frequencies are directly dependent upon the internal oscillator frequency.
# Characteristic Symbol Min Typ Max Units
123 Quiescent Current Settling Time (Power Applied to Iq = IIDLE ± 2mA) tSET ⎯⎯ 5ms(3)
124 Reset Recovery Internal Delay (After internal POR) tINT_INIT ⎯16000 / fOSC ⎯s(7)
125
126
127
VCC Micro-cut (CBUF=CREG=CREGA=1 μF)
Survival Time (VCC disconnect without Reset, CBUF=CREG=CREGA=700 nF)
Survival Time (VCC disconnect without Reset, CBUF=CREG=CREGA=1 μF)
Reset Time (VCC disconnect above which Reset is guaranteed)
tVCC_MICROCUTmin
tVCC_MICROCUT
tVCC_RESET
30
50
⎯
⎯
⎯
⎯
⎯
⎯
1000
μs
μs
μs
(3)
(3)
(3)
128
129
VBUF, Capacitor Monitor Disconnect Time (Figure 9)
POR to first Capacitor Test Disconnect
Disconnect Delay, Asynchronous Mode (Figure 9)tPOR_CAPTEST
tCAPTEST_ADLY
⎯
⎯12000 / fOSC
688 / fOSC
⎯
⎯s
s(7)
(7)
130
131
VREG, VREGA Capacitor Monitor
POR to first Capacitor Test Disconnect
Disconnect Rate tPOR_CAPTEST
tCAPTEST_RATE
⎯
⎯12000 / fOSC
256 / fOSC
⎯
⎯s
s(7)
(7)
132
133
134
135
136
137
138
139
140
141
142
143
144
145
Serial Interface Timing (See Figure 6, CDOUT ≤ 80 pF, RDOUT ≥ 10 kΩ)
Clock (SCLK) period (10% of VCC to 10% of VCC)
Clock (SCLK) high time (90% of VCC to 90% of VCC)
Clock (SCLK) low time (10% of VCC to 10% of VCC)
Clock (SCLK) rise time (10% of VCC to 90% of VCC)
Clock (SCLK) fall time (90% of VCC to 10% of VCC)
CS asserted to SCLK high (CS = 10% of VCC to SCLK = 10% of VCC)
CS asserted to DOUT valid (CS = 10% of VCC to DOUT = 10/90% of VCC)
Data setup time (DIN = 10/90% of VCC to SCLK = 10% of VCC)
DIN Data hold time (SCLK = 90% of VCC to DIN = 10/90% of VCC)
DOUT Data hold time (SCLK = 90% of VCC to DOUT = 10/90% of VCC)
SCLK low to data valid (SCLK = 10% of VCC to DOUT = 10/9 0% of VCC)
SCLK low to CS high (SCLK = 10% of VCC to CS = 90% of VCC)
CS high to DOUT disable (CS = 90% of VCC to DOUT = Hi Z)
CS high to CS low (CS = 90% of VCC to CS = 90% of VCC)
tSCLK
tSCLKH
tSCLKL
tSCLKR
tSCLKF
tLEAD
tACCESS
tSETUP
tHOLD_IN
tHOLD_OUT
tVALID
tLAG
tDISABLE
tCSN
320
120
120
⎯
⎯
60
⎯
20
10
0
⎯
60
⎯
1000
⎯
⎯
⎯
15
15
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
40
28
⎯
60
⎯
⎯
⎯
50
⎯
60
⎯
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)