1
FEATURES
APPLICATIONS
DESCRIPTION
ONET1101L
SLLS883 – MARCH 2008www.ti.com
11.3 Gbps Laser Diode Driver
•Up to 11.3 Gbps Operation •Single +3.3 V Supply•Two-Wire Digital Interface •Case Temperature – 25 °C to 100 °C•Digitally Selectable Modulation Current up to •Small Surface Mount Footprint 4mm ×4mm80 mA 24-Pin, RoHS-compliant QFN Package•Digitally Selectable Bias Current up to 100 mASource or Sink
•10 Gigabit Ethernet Optical Transmitters•Automatic Power Control (APC) Loop
•8x and 10x Fibre Channel Optical Transmitters•Supports Transceiver Management System
•SONET OC-192/SDH STM-64 Optical(TMS)
Transmitters•Programmable Input Equalizer
•XFP and SFP+ Transceiver Modules•Cross-point Control
•XENPAK, XPAK, X2 and 300-pin MSA•Includes Laser Safety Features
Transponder Modules•Adjustable Coupling Ratio
The ONET1101L is a high-speed, 3.3 -V laser driver designed to directly modulate a laser at data rates from2 Gbps to 11.3 Gbps.
The device provides a two-wire serial interface that helps digital control of the modulation, plus bias currents andcross point, eliminating the need for external components. An optional input equalizer can be used forequalization of up to 300 mm (12 ” ) of microstrip or stripline transmission line on FR4 printed circuit boards.
The ONET1101L includes an integrated automatic power control (APC) loop, plus circuitry to support laser safetyand transceiver management systems.
The laser driver is characterized for operation from – 25 °C to 100 °C case temperature and is available in a smallfootprint using a 4mm ×4mm, 24-pin RoHS-compliant QFN package.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2008, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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BLOCK DIAGRAM
+
+
Limiter
DC Offset Cancellation
Equalizer
Output Driver
Boost
100 W
Equalizer
7 Bit + Sign
8 Bit Register
10 Bit Register
10 Bit Register
8 Bit Register
CP Adjust
IMOD
IBIAS
Settings
CP Adjust
CP Adjust
2-Wire Interface and Control Logic
SDA
SCK
DIS
COMP
MONB
MONP
FLT
PD
BIAS
DIN+
DIN–
SDA
SCK
DIS
MOD+
MOD–
BIAS
MONB
MONP
FLT
PD
COMP
RZTC
RZTC
4 Bit Register Settings
3 Bit + Sign Limiter Current
HC Enable
1 Bit
Power-On
Reset
Adjustable
Boost
Bias
Current
Generator
and
APC
Band-Gap
and
Analog
References
B0285-01
PACKAGE
ONET1101L
SLLS883 – MARCH 2008
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.
Figure 1 shows a block diagram of the ONET1101L device. The laser driver consists of an equalizer, a limiter, anoutput driver, DC offset cancellation with cross point control, power-on reset circuitry, a 2-wire serial interface(including a control logic block and modulation current generator), a bias current generator and automatic powercontrol loop, and an analog reference block.
Figure 1. Block Diagram of the ONET1101L
The ONET1101L is packaged in a small footprint 4mm ×4mm 24-pin, RoHS-compliant QFN package, with alead pitch of 0.5 mm. The 24-pin QFN Package top view and pin description follow.
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MONP
VCC
15
14
13
RGEPackage
(TopView)
VCC
MOD–
MOD–
MOD+
MOD+
VCC
24
23
22
21
20
19
GND
1
2
3
VCC
4
DIS
5
SCK
GND
7
8
9
DIN+
10
11
DIN–
GND
12
RZTC
18 BIAS
17 GND
16
COMP
MONB
FLT
PD
SDA
P0024-07
6
EP
ONET1101L
SLLS883 – MARCH 2008
24-Pin QFN Package, 4mm ×4mm (Top View)
PIN DESCRIPTION
PIN NAME TYPE DESCRIPTION
1 PD Analog Photodiode input. Pin can source or sink current dependent on register setting.2, 8, 11, 17, EP GND Supply Circuit ground. Exposed die pad (EP) must be grounded.3, 16, 19, 24 VCC Supply 3.3 V ± 10% supply voltage4 DIS Digital-in Disables the bias and modulation currents when set to high state. Toggle to reset a faultcondition.5 SCK Digital-in 2-wire interface serial clock. Connect a pull-up resistor (10 k Ωtypical) to VCC.6 SDA Digital-in 2-wire interface serial data input. Connect a pull-up resistor (10 k Ωtypical) to VCC.7 FLT Digital-out Fault detection flag.9 DIN + Analog-in Non-inverted data input. On-chip differentially 100 Ωterminated to DIN – . Must be ACcoupled.10 DIN – Analog-in Inverted data input. On-chip differentially 100 Ωterminated to DIN+. Must be AC coupled.12 RZTC Analog Connect external zero TC 28.7 k Ω resistor to ground (GND). Used to generate a definedzero TC reference current for internal DACs.13 MONB Analog-out Bias current monitor. Supplies a 1% replica of the bias current. Connect an external resistorto ground (GND). If the voltage at this pin exceeds 1.16 V, a fault is triggered. Choose aresistor that yields a MONB voltage of 0.8 V at the maximum desired bias current.14 MONP Analog-out Photodiode current monitor. Supplies a 12.5% replica of the photodiode current whenPDRNG = 1X, a 25% replica when PDRNG = 01 and a 50% replica when PDRNG = 00.Connect an external resistor (5 k Ωtypical) to ground (GND).15 COMP Analog Compensation pin used to control the bandwidth of the automatic power control (APC) loop.Connect a 0.01 µF capacitor to ground.18 BIAS Analog Sinks or sources average bias current for laser in both APC and open loop modes.20, 21 MOD+ CML-out Non-inverted modulation current output. IMOD flows into this pin when input data is high(current).22, 23 MOD – CML-out Inverted modulation current output. IMOD flows into this pin when input data is low (current).
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ABSOLUTE MAXIMUM RATINGS
(1)
RECOMMENDED OPERATING CONDITIONS
ONET1101L
SLLS883 – MARCH 2008
over operating free-air temperature range (unless otherwise noted)
VALUE UNIT
V
CC
Supply voltage
(2)
– 0.3 to 4.0 VV
DIS
, V
RZTC
, V
SCK
, V
SDA
, V
FLT
, Voltage at DIS, RZTC, SCK, SDA, DIN+, DIN – , FLT,
– 0.3 to 4.0 VV
MONB
, V
MONP
, V
COMP
, V
PD
, V
BIAS
MONB, MONP, COMP, PD, BIAS, MOD+, MOD –
(2)
IDIN – , IDIN+ Maximum current at input pins 25 mAIMOD+, IMOD – Maximum current at output pins 120 mAESD ESD rating at all pins 2 kV (HBM)T
J,max
Maximum junction temperature 125 °CT
STG
Storage temperature range – 65 to 150 °CT
C
Case Temperature – 40 to 110 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Device exposure to conditions outside the Absolute Maximum Ratings ranges for an extended duration canaffect device reliability.(2) All voltage values are with respect to network ground terminal.
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
V
CC
Supply voltage 2.97 3.3 3.63 VV
IH
Digital input high voltage DIS, SCK, SDA 2.0 VV
IL
Digital input low voltage DIS, SCK, SDA 0.8 VControl bit PDRNG = 1X, step size = 3 µA 3080Photodiode current range Control bit PDRNG = 01, step size = 1.5 µA 1540 µAControl bit PDRNG = 00, step size = 0.75 µA 770R
RZTC
Zero TC resistor value
(1)
1.16 V bandgap bias across resistor, E96, 1% accuracy 28.4 28.7 29 k Ω
V
IN
Differential input voltage swing EQENA = 0 100 1200 mV
p-p
t
R-IN
Input rise time 20% to 80% 30 55 pst
F-IN
Input fall time 20% to 80% 30 55 psT
C
Case Temperature – 25 100 °C
(1) Changing the value alters the DAC ranges.
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DC ELECTRICAL CHARACTERISTICS
ONET1101L
SLLS883 – MARCH 2008
Over recommended operating conditions with a 25 Ωoutput load, open loop operation, I
MOD
= 40 mA, I
BIAS
= 40 mA, andR
RZTC
= 28.7 k Ω(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
CC
Supply voltage 2.97 3.3 3.63 VI
MOD
= 40 mA, I
BIAS
= 40 mA, excluding I
MOD
and 66 85I
BIAS
, EQENA = 0I
MOD
= 80 mA, I
BIAS
= 80 mA, excluding I
MOD
and 95 118I
BIAS
, EQENA = 0I
VCC
Supply current mAI
MOD
= 40 mA, I
BIAS
= 40 mA, excluding I
MOD
and 73 95I
BIAS
, EQENA = 1Output off (DIS = HIGH), I
MOD
= 40 mA,
42I
BIAS
= 40 mA, EQENA = 0R
IN
Data input resistance Differential between DIN+ / DIN – 80 100 120 Ω
SCK, SDA, pull up to VCC – 10 10 µADigital input current
DIS, pull down to GND – 10 10 µAV
OH
Digital output high voltage FLT, pull-up to V
CC
, I
SOURCE
= 50 µA 2.4 VV
OL
Digital output low voltage FLT, pull-up to V
CC
, I
SINK
= 350 µA 0.4 VI
BIAS-MIN
Minimum bias current See table note
(1)
5 mASink, BIASPOL = 0
85 100DAC set to maximum, open and closed loopI
BIAS-MAX
Maximum bias current mASource, BIASPOL = 1
80 100DAC set to maximum, open and closed loopI
BIAS-DIS
Bias current during disable 100 µABIASPOL = 0 0.8Bias pin compliance voltage VBIASPOL = 1 V
CC
– 0.8V
PD
Photodiode reverse bias voltage APC active, I
PD
= max 1.3 2.3 VPhotodiode fault current level Percent of target I
PD
(2)
150%I
MONP
/ I
PD
with control bit PDRNG = 1X 10% 12.5% 15%Photodiode current monitor ratio I
MONP
/ I
PD
with control bit PDRNG = 01 20% 25% 30%I
MONP
/ I
PD
with control bit PDRNG = 00 40% 50% 60%Bias current monitor ratio I
MONB
/ I
BIAS
(nominal 1/100 = 1%) 0.9% 1.0% 1.2%V
CC-RST
V
CC
reset threshold voltage V
CC
voltage level which triggers power-on reset 2.5 2.8 VV
CC-RSTHYS
V
CC
reset threshold voltage Hysteresis 100 mVV
MONB-FLT
Fault voltage at MONB Fault occurs if voltage at MONB exceeds value 1.1 1.16 1.22 V
(1) The bias current can be set below the specified minimum according to the corresponding register setting; however in closed loopoperation settings below the specified value the bias current can trigger a fault.(2) Assured by simulation over process, supply, and temperature variation.
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AC ELECTRICAL CHARACTERISTICS
DETAILED DESCRIPTION
EQUALIZER
LIMITER
HIGH-SPEED OUTPUT DRIVER
ONET1101L
SLLS883 – MARCH 2008
Over recommended operating conditions with 25 Ωoutput load, open loop operation, I
MOD
= 40 mA, I
BIAS
= 40 mA, andR
RZTC
= 28.7 k Ω. Typical operating condition is at V
CC
= 3.3 V and T
A
= 25 °C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SDD11 0.01 GHz < f < 3.9 GHz – 16Differential input return gain dB3.9 GHz < f < 12.1 GHz See note
(1)
SCD11 f < 8.25 GHz – 45Differential to common mode
dBconversion gain
8.25 GHz < f < 20 GHz – 35t
R-OUT
Output rise time 20% to 80%, t
R-IN
< 40 ps, 25 Ωload, single-ended 25 35 pst
F-OUT
Output fall time 20% to 80%, t
F-IN
< 40 ps, 25 Ωload, single-ended 25 35 psI
MOD-MIN
Minimum modulation current 10 mAI
MOD-MAX
Maximum modulation current AC Coupled Outputs 70 85 mAI
MOD-STEP
Modulation current step size 10 Bit Register 83 µAEQENA = 0, K28.5 pattern at 11.3 Gbps, 100 mVpp,
5 10600 mVpp, 1200 mVpp differential input voltageDJ Deterministic output jitter ps
p-pEQENA = 1, K28.5 pattern at 11.3 Gbps, maximumequalization with 12 ” transmission line at the input, 400 7mVpp at input to transmission lineRJ Random output jitter 0.4 0.8 ps
RMS
C
APC
= 0.01 µF, I
PD
= 100 µA,τ
APC
APC time constant 120 µsPD coupling ratio, CR = 40
(2)
Cross Point Control Range 30% 70%T
OFF
Transmitter disable time Rising edge of DIS to I
BIAS
≤0.1 ×I
BIAS-NOMINAL
(2)
0.05 5 µsT
ON
Disable negate time Falling edge of DIS to I
BIAS
≥0.9 ×I
BIAS-NOMINAL
(2)
1 msT
INIT1
Power-on to initialize Power-on to registers ready to be loaded 1 10 msT
INIT2
Initialize to transmit Register load STOP command to part ready to transmit 2 msvalid data
(2)
T
RESET
DIS pulse width Time DIS must be held high to reset part
(2)
100 nsT
FAULT
Fault assert time Time from fault condition to FLT high
(2)
50 µs
(1) Differential Return Gain given by SDD11, SDD22 = – 11.6 + 13.33 ×log
10
(f ÷8.25), f expressed in GHz(2) Assured by simulation over process, supply, and temperature variation.
The data signal can be applied to an input equalizer by means of the input signal pins DIN+ / DIN – , whichprovide on-chip differential 100 Ωline-termination. The equalizer is enabled by setting EQENA = 1 (bit 1 ofregister 0). Equalization of up to 300 mm (12") of microstrip or stripline transmission line on FR4 printed circuitboards can be achieved. The amount of equalization is digitally controlled by the two-wire interface and controllogic block, and is dependant on the register settings EQADJ[0...7] (register 6). The equalizer can also be turnedoff and bypassed by setting EQENA = 0. For details about the equalizer settings, see Table 12 -RegisterFunctionality .
By limiting the output signal of the equalizer to a fixed value, the limiter removes any overshoot after the inputequalization and provides the input signal for the output driver.
The modulation current is sunk from the common emitter node of the limiting output driver differential pair bymeans of a modulation current generator, which is digitally controlled by the 2-wire serial interface.
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MODULATION CURRENT GENERATOR
DC OFFSET CANCELLATION AND CROSS POINT CONTROL
BIAS CURRENT GENERATION AND APC LOOP
ANALOG REFERENCE
ONET1101L
SLLS883 – MARCH 2008
The collector nodes of the output stages are connected to the output pins MOD+ and MOD – . The laser diodecan be AC- or DC-coupled, depending on the required modulation current. To obtain the maximum modulationcurrent of 80 mA, AC coupling is required. The modulation outputs are optimized for driving a 25 Ωload.
The modulation current generator provides the current for the current modulator described above. The circuit isdigitally controlled by the 2-wire interface block.
A 10-bit control bus, MODC[0...9] (register 2 and register 3), is used to set the desired modulation current.
The modulation current can be disabled by setting the DIS input pin high or setting ENA = 0 (bit 7 of register 0).The modulation current is also disabled in a fault condition if the internal fault detection enable register flagFLTEN is set (bit 3 of register 0).
The ONET1101L has DC offset cancellation to compensate for internal offset voltages. The offset cancellationcan be disabled by setting OCDIS = 1 (bit 3 of register 1). Disabling the offset cancellation permits the outputcrossing point to be adjusted from a minimum of 30% to 70% of the output eye diagram. The crossing point canbe moved toward the one level be setting CPSGN = 1 (bit 7 of register 7) and it can be moved toward the zerolevel by setting CPSGN = 0. The shift percentage depends upon the register settings CPADJ[0...6] (register 7)and the cross point adjustment range bits CPRNG[0...1] (register 1). Setting CPRNG1 = 0 and CPRNG0 = 0results in minimum adjustment (fine) capability and setting CPRNG1 = 1 and CPRNG0 = 1 results in maximum(coarse) adjustment capability.
The bias current generation and APC loop are controlled by means of the 2-wire interface. In open loopoperation, selected with OLENA = 1 (bit 4 of register 0), the bias current is set directly by the 10-bit control wordBIASC[0...9] (register 4 and register 5). In automatic power control mode (select with OLENA = 0), the biascurrent depends on the register settings BIASC[0...9] and the coupling ratio (CR) between the laser bias currentand the photodiode current. CR = I
BIAS
/ I
PD
. If the photodiode anode is connected to the PD pin, set PDPOL = 1(bit 0 of register 0) and if the photodiode cathode is connected to the PD pin, set PDPOL = 0.
Three photodiode current ranges can be selected by means of the PDRNG[1...0] bits (register 0). Thephotodiode range should be chosen to keep the laser bias control DAC, BIASC[0...9], close to its range center.This keeps the laser bias current set point resolution high. For details regarding the bias current setting in open-and closed-loop mode, see Table 12 .
The ONET1101L has the ability to source or sink the bias current. For the BIAS pin to act as a source setBIASPOL = 1 (bit 2 of register 1) and for the BIAS pin to act as a sink set BIASPOL = 0.
The bias current is monitored using a current mirror with a gain value equal to 0.01 (1 %). By connecting aresistor between MONB and GND, the bias current can be monitored as a voltage across the resistor. A lowtemperature coefficient precision resistor should be used.
The ONET1101L laser driver is supplied by a single 3.3 V ± 10% supply voltage connected to the VCC pins. Thisvoltage is referenced to ground (GND).
On-chip bandgap voltage circuitry generates a reference voltage, independent of the supply voltage, from whichall other internally required voltages and bias currents are derived.
An external zero temperature coefficient resistor must be connected from the RZTC pin of the device to ground(GND). This resistor is used to generate a precise, zero TC current, which is required as a reference current forthe on-chip DACs.
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POWER-ON RESET
2-WIRE INTERFACE AND CONTROL LOGIC
ONET1101L
SLLS883 – MARCH 2008
The ONET1101L has power-on reset circuitry that ensures all registers are reset to zero during startup. After thepower-on to initialize time (t
INIT1
), the internal registers are ready to load. The part is ready to transmit data afterthe initialize to transmit time (t
INIT2
), assuming that the chip enable bit ENA is set to 1 and the disable pin DIS islow.
The ONET1101L can be disabled using the ENA control register bit or the disable pin DIS. In both cases theinternal registers are not reset. After the disable pin DIS is set low or the enable bit ENA is set back to 1, the partreturns to its prior output settings.
The ONET1101L uses a 2-wire serial interface for digital control. The two circuit inputs, SDA and SCK, aredriven, respectively, by the serial data and serial clock from a microprocessor, for example. For driving theseinputs, TI recommends an open drain output.
The 2-wire interface provides write access to the internal memory map to modify control registers and readaccess to read out the control signals. The ONET1101L is a slave device only, which means that it cannot initiatea transmission itself; it always relies on the availability of the SCK signal for the duration of the transmission. Themaster device provides the clock signal plus the START and STOP commands. The protocol for a datatransmission is:1. START command2. 7-bit slave address (0001000) followed by an eighth bit which is the data direction bit (R/W). A zero indicatesa WRITE and a 1 indicates a READ.3. 8-bit register address4. 8-bit register data word5. STOP command
Regarding timing, the ONET1101L is I
2
C compatible. A typical timing diagram, shown in Figure 2 and Figure 3 ,describes a complete data transfer. Table 1 provides definitions of parameters for the Figure 2 , I
2
C TimingDiagram.
Bus Idle: Both SDA and SCK lines remain HIGH
Start Data Transfer: A change in the state of the SDA line, from HIGH to LOW, while the SCK line is HIGH,defines a START condition (S). Each data transfer begins with a START condition.
Stop Data Transfer: A change in the state of the SDA line from LOW to HIGH while the SCK line is HIGHdefines a STOP condition (P). Each data transfer ends with a STOP condition; however, if the master still wishesto communicate on the bus, it can generate a repeated START condition and address another slave without firstgenerating a STOP condition.
Data Transfer: Only one data byte can be transferred between a START and a STOP condition. The receiveracknowledges the transfer of data.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledgment bit. Thetransmitter releases the SDA line and a device that acknowledges, must pull down the SDA line during theacknowledge clock pulse simultaneously so the SDA line is stable LOW during the HIGH period of theacknowledge clock pulse. Set-up and hold times must be taken into account. When a slave-receiver fails toacknowledge the slave address, the data line must be left HIGH by the slave. The master can generate a STOPcondition to prevent the transfer. If the slave-receiver does acknowledge the slave address but some time later inthe transfer cannot receive any more data bytes, the master must cancel the transfer. This is indicated by theslave generating the not acknowledge on the first following byte. The slave leaves the data line HIGH and themaster generates the STOP condition.
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PS S P
SDA
SCK
tBUF tLOW
tSUSTA
tHIGH tHDSTA
tr
tHDSTA
tHDSTA
tSUDAT tSUSTO
tf
T0295-01
S
SDA
SCK
P
1–7 1–7 1–7
SLAVE
ADDRESS
R/W ACK
8 9 8 9
REGISTER
ADDRESS
ACK
8 9
ACK
REGISTER
FUNCTION
T0296-01
REGISTER MAPPING
ONET1101L
SLLS883 – MARCH 2008
Figure 2. I
2
C Timing Diagram
Table 1. Timing Diagram Definitions
PARAMETER MIN MAX UNIT
f
SCK
SCK clock frequency 400 kHzt
BUF
Bus free time between START and STOP conditions 1.3 µst
HDSTA
Hold time after repeated START condition. After this period, the first clock pulse is generated 0.6 µst
LOW
Low period of the SCK clock 1.3 µst
HIGH
High period of the SCK clock 0.6 µst
SUSTA
Setup time for a repeated START condition 0.6 µst
HDDAT
Data HOLD time 0 µst
SUDAT
Data setup time 100 nst
R
Rise time of both SDA and SCK signals 300 nst
F
Fall time of both SDA and SCK signals 300 nst
SUSTO
Setup time for STOP condition 0.6 µs
Figure 3. I
2
C Data Transfer
The register mapping for register addresses 0 (0x00) through 9 (0x09) are shown in Table 2 through Table 11 .
Table 12 describes the circuit functionality based on the register settings.
Table 2. Register 0 (0x00) Mapping – Control Settings
register address 0 (0x00)
bit 7 bit 6 bit 5 bit4 bit 3 bit 2 bit 1 bit 0
ENA PDRNG1 PDRNG0 OLENA FLTEN POL EQENA PDPOL
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SLLS883 – MARCH 2008
Table 3. Register 1 (0x01) Mapping – Control Settings
register address 1 (0x01)
bit 7 bit 6 bit 5 bit4 bit 3 bit 2 bit 1 bit 0
– – – – OCDIS BIASPOL CPRNG1 CPRNG0
Table 4. Register 2 (0x02) Mapping – Modulation Current
register address 2 (0x02)
bit 7 bit 6 bit 5 bit4 bit 3 bit 2 bit 1 bit 0
– – – – – – MODC1 MODC0
Table 5. Register 3 (0x03) Mapping – Modulation Current
register address 3 (0x03)
bit 7 bit 6 bit 5 bit4 bit 3 bit 2 bit 1 bit 0
MODC9 MODC8 MODC7 MODC6 MODC5 MODC4 MODC3 MODC2
Table 6. Register 4 (0x04) Mapping – Bias Current
register address 4 (0x04)
bit 7 bit 6 bit 5 bit4 bit 3 bit 2 bit 1 bit 0
– – – – – – BIASC1 BIASC0
Table 7. Register 5 (0x05) Mapping – Bias Current
register address 5 (0x05)
bit 7 bit 6 bit 5 bit4 bit 3 bit 2 bit 1 bit 0
BIASC9 BIASC8 BIASC7 BIASC6 BIASC5 BIASC4 BIASC3 BIASC2
Table 8. Register 6 (0x06) Mapping – Equalizer Adjust
register address 6 (0x06)
bit 7 bit 6 bit 5 bit4 bit 3 bit 2 bit 1 bit 0
EQADJ7 EQADJ6 EQADJ5 EQADJ4 EQADJ3 EQADJ2 EQADJ1 EQADJ0
Table 9. Register 7 (0x07) Mapping – Cross Point Adjust
register address 7 (0x07)
bit 7 bit 6 bit 5 bit4 bit 3 bit 2 bit 1 bit 0
CPSGN CPADJ6 CPADJ5 CPADJ4 CPADJ3 CPADJ2 CPADJ1 CPADJ0
Table 10. Register 8 (0x08) Mapping – Limiter Bias Current Adjust
register address 8 (0x08)
bit 7 bit 6 bit 5 bit4 bit 3 bit 2 bit 1 bit 0
– – – – LIMCSGN LIMC2 LIMC1 LIMC0
Table 11. Register 9 (0x09) Mapping – High Current Enable
register address 9 (0x09)
bit 7 bit 6 bit 5 bit4 bit 3 bit 2 bit 1 bit 0
– – – – – – – HMCENA
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ONET1101L
SLLS883 – MARCH 2008
Table 12. Register Functionality
SYMBOL REGISTER BIT FUNCTION
Enable chip bitENA Enable bit 7 1 = chip enabled. Can be toggled low to reset a fault condition.0 = chip disabled
Photodiode current range bits1X: up to 3080 µA / 3 µA resolutionPDRNG1 Photodiode current range bit 6PDRNG0 Photodiode current range bit 5
01: up to 1540 µA / 1.5 µA resolution00: up to 770 µA / 0.75 µA resolution
Open loop enable bitOLENA Open loop enable bit 4 1 = open loop bias current control0 = closed loop bias current control
Fault detection enable bitFLTEN Fault detection enable bit 3 1 = fault detection on0 = fault detection off
Output polarity switch bitPOL Output polarity switch bit 2 1: pins 20 and 21 = MOD – and pins 22 and 23 = MOD+0: pins 20 and 21 = MOD+ and pins 22 and 23 = MOD –
Equalizer enable bitEQENA Equalizer enable bit 1 1 = equalizer enabled0 = equalizer disabled
Photodiode polarity bitPDPOL Photodiode polarity bit 0 1 = photodiode cathode connected to V
CC0 = photodiode anode connected to GND
Offset cancellation disable bitOCDIS Offset cancellation disable bit 3 1 = DC offset cancellation is disabled and cross point adjust is enabled0 = DC offset cancellation is enabled and cross point adjust is disabled
Bias current polarity bitBIASPOL Bias current polarity bit 2 1 = Bias pin sources current0 = Bias pin sinks current
Cross point adjustment range bits:Cross point range bit 1CPRNG1
Minimum adjustment range for 00CPRNG0
Cross point range bit 0
Maximum adjustment range for 11
MODC9 Modulation current bit 9 (MSB) Modulation current setting
MODC8 Modulation current bit 8MODC7 Modulation current bit 7MODC6 Modulation current bit 6MODC5 Modulation current bit 5MODC4 Modulation current bit 4 Modulation current: 85 mA / 83 µA stepsMODC3 Modulation current bit 3MODC2 Modulation current bit 2MODC1 Modulation current bit 1MODC0 Modulation current bit 0 (LSB)
BIASC9 Bias current bit 9 (MSB) Closed loop (APC)
BIASC8 Bias current bit 8 Coupling ratio CR = I
BIAS
/ I
PD
, BIASC = 0...1023, I
BIAS
≤100 mABIASC7 Bias current bit 7BIASC6 Bias current bit 6 PDRNG = 00 (see Photodiode current range bits); I
BIAS
= 0.75 µA×CR ×BIASCBIASC5 Bias current bit 5 PDRNG = 01 (see Photodiode current range bits); I
BIAS
= 1.5 µA×CR ×BIASCBIASC4 Bias current bit 4 PDRNG = 1X (see Photodiode current range bits); I
BIAS
= 3 µA×CR ×BIASCBIASC3 Bias current bit 3BIASC2 Bias current bit 2 Open loop
BIASC1 Bias current bit 1 I
BIAS
= 98 µA×BIASCBIASC0 Bias current bit 0 (LSB)
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 11
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www.ti.com
LASER SAFETY FEATURES AND FAULT RECOVERY PROCEDURE
ONET1101L
SLLS883 – MARCH 2008
Table 12. Register Functionality (continued)
SYMBOL REGISTER BIT FUNCTION
EQADJ7 Equalizer adjustment bit 7 (MSB) Equalizer adjustment setting
EQADJ6 Equalizer adjustment bit 6EQADJ5 Equalizer adjustment bit 5 EQENA = 0 (see Equalizer Enable Bit)EQADJ4 Equalizer adjustment bit 4 Equalizer is turned off and bypassedEQADJ3 Equalizer adjustment bit 3EQADJ2 Equalizer adjustment bit 2 EQENA = 1 (see Equalizer Enable Bit)EQADJ1 Equalizer adjustment bit 1 Maximum equalization for 00000000EQADJ0 Equalizer adjustment bit 0 (LSB) Minimum equalization for 11111111
CPSGN Eye crossing sign bit 7 Eye cross-point adjustment setting
CPADJ6 Eye crossing adjustment bit 6 (MSB) CPSGN = 1 (positive shift)CPADJ5 Eye crossing adjustment bit 5 Maximum shift for 1111111CPADJ4 Eye crossing adjustment bit 4 Minimum shift for 0000000CPADJ3 Eye crossing adjustment bit 3 CPSGN = 0 (negative shift)CPADJ2 Eye crossing adjustment bit 2 Maximum shift for 1111111CPADJ1 Eye crossing adjustment bit 1 Minimum shift for 0000000CPADJ0 Eye crossing adjustment bit 0 (LSB)
LIMCSGN Limiter current sign bit 3 Limiter bias current setting
LIMC2 Limiter current bit 2 (MSB) LIMCSGN = 1: decrease currentLIMC1 Limiter current bit 1 LIMCSGN = 0: increase currentLIMC0 Limiter current bit 0 (LSB) No change for 000 and maximum change for 111
High modulation current enable bitHMCENA High modulation current enable bit 0 1 = high modulation current capability up to 100 mA0 = modulation current capability up to 80 mA
The ONET1101L provides built-in laser safety features and can detect these fault conditions:•Voltage at MONB exceeds the voltage at RZTC (1.16 V)•Photodiode current exceeds 150% of its set value•Bias control DAC drops in value by more than 50% in one step
If one or more fault conditions happen and the fault enable bit FLTEN is set to 1, the ONET1101L responds by:•Setting the bias current to zero.•Setting the modulation current to zero.•Asserting and latching the FLT pin.
ONET1101L Fault recovery happens using this procedure:1. The disable pin DIS or the internal enable control bit ENA are toggled for at least the fault latch reset time.2. The FLT pin de-asserts while the disable pin DIS is asserted or the enable bit ENA is de-asserted.3. If the fault condition is no longer present, the part returns to normal operation with its prior output settingsafter the disable negate time.4. If the fault condition is still present, FLT re-asserts once DIS is set to a low level and the part does not returnto normal operation.
12 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s) :ONET1101L
www.ti.com
TYPICAL OPERATION CHARACTERISTICS
TA − Free-Air Temperature − °C
0
1
2
3
4
5
6
7
8
−40 −20 0 20 40 60 80 100
Deterministic Jitter − psPP
G002
Modulation Current − mA
0
1
2
3
4
5
6
7
8
10 20 30 40 50 60 70 80
Deterministic Jitter − psPP
G001
TA − Free-Air Temperature − °C
0.0
0.1
0.2
0.3
0.4
−40 −20 0 20 40 60 80 100
Random Jitter − psrms
G004
Modulation Current − mA
0.0
0.1
0.2
0.3
0.4
0.5
10 20 30 40 50 60 70 80
Random Jitter − psrms
G003
ONET1101L
SLLS883 – MARCH 2008
Typical operating condition is at V
CC
= 3.3 V, T
A
= 25 °C, I
BIAS
= 40 mA, I
MOD
= 40 mA, V
IN
= 600 mVpp (unless otherwisenoted).
DETERMINISTIC JITTER DETERMINISTIC JITTERvs vsMODULATION CURRENT TEMPERATURE
Figure 4. Figure 5.
RANDOM JITTER RANDOM JITTERvs vsMODULATION CURRENT TEMPERATURE
Figure 6. Figure 7.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 13
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Modulation Current − mA
0
5
10
15
20
25
30
35
10 20 30 40 50 60 70 80
tt − T ransition Time − ps
G005
Fall Time
Rise Time
TA − Free-Air Temperature − °C
0
5
10
15
20
25
30
35
−40 −20 0 20 40 60 80 100
tt − T ransition Time − ps
G006
Fall Time
Rise Time
Bias Current − mA
0.0
0.2
0.4
0.6
0.8
1.0
1.2
10 20 30 40 50 60 70 80 90 100
IMONB − Bias-Monitor Current − mA
G008
Bias Current Register Setting − Decimal
0
20
40
60
80
100
120
0 200 400 600 800 1000 1200
Open Loop Bias Current − mA
G007
ONET1101L
SLLS883 – MARCH 2008
TYPICAL OPERATION CHARACTERISTICS (continued)Typical operating condition is at V
CC
= 3.3 V, T
A
= 25 °C, I
BIAS
= 40 mA, I
MOD
= 40 mA, V
IN
= 600 mVpp (unless otherwisenoted).
RISE-TIME AND FALL-TIME RISE-TIME AND FALL-TIMEvs vsMODULATION CURRENT TEMPERATURE
Figure 8. Figure 9.
BIAS CURRENT IN OPEN LOOP MODE BIAS-MONITOR CURRENT I
MONBvs vsBIASC REGISTER SETTING BIAS CURRENT
Figure 10. Figure 11.
14 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s) :ONET1101L
www.ti.com
Photodiode Current − mA
0.00
0.05
0.10
0.15
0.20
0.25
0.05 0.15 0.25 0.35 0.45 0.55 0.65 0.75 0.85
Photodiode Monitor Current − mA
G009
Modulation Current Register Setting − Decimal
0
10
20
30
40
50
60
70
80
90
0 200 400 600 800 1000 1200
Modulation Current − mA
G010
G012
14.8 ps / Div
TA − Free-Air Temperature − °C
100
110
120
130
140
150
160
170
180
190
200
−40 −20 0 20 40 60 80 100
Supply Current − mA
(Including IBIAS and IMOD)
G011
ONET1101L
SLLS883 – MARCH 2008
TYPICAL OPERATION CHARACTERISTICS (continued)Typical operating condition is at V
CC
= 3.3 V, T
A
= 25 °C, I
BIAS
= 40 mA, I
MOD
= 40 mA, V
IN
= 600 mVpp (unless otherwisenoted).
PHOTODIODE-MONITOR CURRENT I
MONP
MODULATION CURRENTvs vsPD CURRENT MODC REGISTER SETTING
Figure 12. Figure 13.
SUPPLY CURRENT (includes I
BIAS
and I
MOD
)vs EYE-DIAGRAM AT 11.3 GBPS, PRBS-31 PATTERNTEMPERATURE I
MOD
= 20 mA, EQENA = 0
Figure 14. Figure 15.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Link(s) :ONET1101L
www.ti.com
G013
14.5 ps / Div
G014
14.6 ps / Div
ONET1101L
SLLS883 – MARCH 2008
TYPICAL OPERATION CHARACTERISTICS (continued)Typical operating condition is at V
CC
= 3.3 V, T
A
= 25 °C, I
BIAS
= 40 mA, I
MOD
= 40 mA, V
IN
= 600 mVpp (unless otherwisenoted).
EYE-DIAGRAM AT 11.3GBPS, PRBS-31 PATTERN EYE-DIAGRAM AT 11.3GBPS, PRBS-31 PATTERNI
MOD
= 40 mA, EQENA = 0 I
MOD
= 60 mA, EQENA = 0
Figure 16. Figure 17.
EYE-DIAGRAM AT 11.3GBPS, PRBS-31 PATTERNI
MOD
= 40 mA, EQENA = 112" OF FR4 AT INPUTS
Figure 18.
16 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
Product Folder Link(s) :ONET1101L
www.ti.com
APPLICATION INFORMATION
MONP
DIN+
DIN–
MONB
MOD+
MOD–
VCC
PD
GND
DIS
SCK
SDA
MOD–
VCC
MOD+
GND
FLT
GND
RZTC
VCC
BIAS
GND
VCC
COMP
ONET1101L
DIN+
DIN–
FLT
MONB
MONP
SDA
SDK
DIS
Laser
VCC
0.1 Fm1000pF
0.1 Fm
0.1 Fm
0.1 Fm
0.1 Fm
(SeeNote1)
(SeeNote1)
0.1 Fm
C1
0.1 Fm
C2
0.1 Fm
R
28.7 k
ZTC
W
R
1.2 k
MONB
W
R
5 k
MONP
W
C
0.01 F
COMP
m
Monitor
Photodiode
S0319-01
BLM15HG601SN1
BLM15HD102SN1
BLM15HG601SN1
BLM15HG601SN1 ´2
BLM15HD102SN1
BLM15HD102SN1 ´2
(See
Note
1)
(See
Note1)
ONET1101L
SLLS883 – MARCH 2008
Figure 19 and Figure 20 show typical application circuits using the ONET1101L with a laser biased to VCC (BIASpin sink) and driven differentially or single-ended. The laser driver is controlled using the 2-wire interfaceSDA/SCK by a microcontroller. In a typical application, the FLT, MONB, and MONP outputs are also connectedto the microcontroller for transceiver management purposes.
The component values in Figure 19 and Figure 20 are typical examples and may be varied according to theintended application.
(1) Resistor values depend on the TOSA diode used.
Figure 19. AC Coupled Differential Drive
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 17
Product Folder Link(s) :ONET1101L
www.ti.com
MONP
DIN+
DIN–
MONB
MOD+
MOD–
VCC
PD
GND
DIS
SCK
SDA
MOD–
VCC
MOD+
GND
FLT
GND
RZTC
VCC
BIAS
GND
VCC
COMP
ONET1101L
DIN+
DIN–
FLT
MONB
MONP
SDA
SDK
DIS
Laser
VCC
Optional
0.1 Fm
0.1 Fm
0.1 Fm
0.1 Fm
0.1 Fm
25 W
C1
0.1 Fm
C2
0.1 Fm
R
28.7 k
ZTC
W
R
1.2 k
MONB
W
R
5 k
MONP
W
C
0.01 F
COMP
m
Monitor
Photodiode
50
Diff TL
W
25 TLW
S0320-01
BLM15HD102SN1
BLM15HG601SN1
BLM15HG601SN1
BLM15HD102SN1
BLM15HD102SN1 ´2
0.1 Fm1000pF
CALCULATING POWER CONSUMPTION
ONET1101L
SLLS883 – MARCH 2008
Figure 20. AC Coupled Single-Ended Drive
The power dissipation is different, depending if the BIAS pin is sourcing or sinking current. Lower powerdissipation in the ONET1101L can be achieved if the BIAS pin sinks the bias current because the BIAS pincompliance voltage is typically less than 1 V.
The power dissipation is calculated as:P = V
CC
×(I
VCC
+ I
MOD
) + (V
BIAS
×I
BIAS
)
Where:
V
CC
is the power supply voltageI
VCC
is the supply current excluding modulation and bias currentI
MOD
is the modulation currentV
BIAS
is the voltage at the BIAS pinI
BIAS
is the bias current
18 Submit Documentation Feedback Copyright © 2008, Texas Instruments Incorporated
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www.ti.com
LAYOUT GUIDELINES
ONET1101L
SLLS883 – MARCH 2008
For optimum performance, use 50 Ωtransmission lines (100 Ωdifferential) for connecting the signal source tothe DIN+ and DIN – pins and 25 Ωtransmission lines (50 Ωdifferential) for connecting the modulation currentoutputs, MOD+ and MOD – , to the laser. The length of the transmission lines should be kept as short as possibleto reduce loss and pattern-dependent jitter. It is recommended to assemble the series matching resistor as closeas possible to the TOSA diode, if required.
Copyright © 2008, Texas Instruments Incorporated Submit Documentation Feedback 19
Product Folder Link(s) :ONET1101L
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
ONET1101LRGER ACTIVE VQFN RGE 24 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ONET1101LRGERG4 ACTIVE VQFN RGE 24 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ONET1101LRGET ACTIVE VQFN RGE 24 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
ONET1101LRGETG4 ACTIVE VQFN RGE 24 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Jul-2008
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
ONET1101LRGER VQFN RGE 24 3000 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2
ONET1101LRGET VQFN RGE 24 250 330.0 12.4 4.3 4.3 1.5 8.0 12.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Apr-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
ONET1101LRGER VQFN RGE 24 3000 338.1 338.1 20.6
ONET1101LRGET VQFN RGE 24 250 338.1 338.1 20.6
PACKAGE MATERIALS INFORMATION
www.ti.com 19-Apr-2012
Pack Materials-Page 2
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