MT47H128M4FT-5 - Micron Technology, Inc.

‡PRODUCTS AND SPECIFICATIONS DISC USSED HEREIN ARE FOR EVAL UATION AND REFERENCE PURPOSES ONLY AND ARE SU BJECT TO CHANGE BY

MICRON WITHOUT NOTICE. PRODUC TS ARE ONLY WARRANTED BY MICR ON TO MEET MIC RON’S PRODUC TION DATA SHEET S PE CIFICATIONS.

09005aef80b88542

512Mb: x4, x8, x16

DDR2 SD RAM

PRELIMINARY‡

DDR2 SDRAM MT47H128M4 – 32 MEG X 4 X 4 BANKS

MT47H64M8 – 16 MEG X 8 X 4 BANKS

MT47H32M16 – 8 MEG X 16 X 4 BANKS

For the latest data sheet, please refer to the Micron Web

site: http://www.micron.com/datasheets

Features

•VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V

• JEDEC standard 1.8V I/O (SSTL_18-compatible)

• Differential data strobe (DQS, DQS#) option

• Four-bit prefetch arc h it ec ture

• Du pl i ca te outp ut strobe (RDQS) option for x8

configuration

• DLL to align DQ and DQS transitions with CK

• Four internal banks for concurrent operation

• Programmable CAS Late ncy (CL): 3 and 4

• Posted CAS additive latency (AL): 0, 1, 2, 3, an d 4

• WRITE latency = READ latency - 1 tCK

• Programmable burst lengths: 4 or 8

• Supports REA D burst interrupt by another READ

• Supports W RIT E burst interrupt by anothe r WRITE

• Ad ju st able data-output drive strength

• 64ms, 8,192-cycle refresh

• On-die term ination (ODT)

• Supports the JEDEC DDR2 functionality

requirements

Options Designation

• Configuration

128 Meg x 4 (32 Meg x 4 x 4 banks) 128M4

64 Meg x 8 (16 Meg x 8 x 4 banks) 64M8

32 Meg x 16 (8 Meg x 16 x 4 banks) 32M16

•FBGA Package

92-ball (11mm x 19mm) FBGA FT

• Timing – Cycle Time

5.0ns @ CL = 4 (DDR2-400) -5

5.0ns @ CL = 3 (DDR2-400) -5E

3.75ns @ CL = 4 (DDR2-533) -37E

Table 1: Key Timing Parameters

SPEED

GRADE

DATA RATE

(MHz) tRCD

(ns) tRP

(ns) tRC

(ns)CL = 3 CL = 4

-5 – 400 20 20 65

-5E 400 400 15 15 60

-37E 400 533 15 15 60

ARCHITECTURE 128 MEG X 4 64 MEG X 8 32 MEG X 16

Configuration

32 Meg x 4 x 4

banks 16 Meg x 8 x 4

banks 8 Meg x 16 x 4

banks

Refresh Count

8K 8K 8K

Row Addressing

16K (A0-A13) 16K (A0-A13) 8K (A0-A12)

Bank

Addressing

4 (BA0, BA1) 4 (BA0, BA1) 4 (BA0, BA1)

Column

Addressing

2K (A0-A9, A11) 1K (A0-A9 ) 1K (A0-A9)

512Mb: x4, x8, x16

DDR2 SD RAM

PRELIMINARY

09005aef80b88542 M icron Technol ogy, Inc., rese rve s the right to ch ange produc ts or spe c ifi ca t io ns w ith out notice.

Table of Contents

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Part Numbers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

FBGA Part Marking Decoder. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Mode Register (MR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

DLL Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Write Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

CAS Latency (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Extended Mode Reg ist er (EMR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

DLL Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Output Drive Streng th . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

DQS# Enable/Disab le. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

RDQS Enable/Dis able . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Output Enable/Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

On Die Termination (ODT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Off-Chip Driver (OCD) Imp edance Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Posted CAS Additive Latency (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Extended Mode Reg ist er 2 (EMR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Extended Mode Reg ist er 3 (EMR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Command Truth Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

DESELECT, NOP, and LOAD MODE Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

DESELECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

NO OPERATION (NOP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

LOAD MODE (LM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Bank/Row Activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

ACTIVE Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

ACTIVE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

READs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

WRITEs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

WRITE Operatio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

PRECHARGE Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

PRECHARGE Operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Self Refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

SELF REFRESH Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

REFRESH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

REFRESH Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Power-Down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56

Precharge Power-Down Clock Frequ e ncy Cha nge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63

RESET Func tion (CKE LOW Anytime) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

ODT Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65

Absolute Maxi mum Rati ngs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

512Mb: x4, x8, x16

DDR2 SD RAM

PRELIMINARY

09005aef80b88542 M icron Technol ogy, Inc., rese rve s the right to ch ange produc ts or spe c ifi ca t io ns w ith out notice.

AC and DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Input Electr ical Characteristics and Operat ing Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Power and Ground Clamp Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

AC Overshoot/Undershoot Sp ec ifi ca tio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Output El ec trical Characteristics and Operating Conditio ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Full Strength Pull-Down Driver Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Full Strength Pull- Up Driver Cha ra ct e ristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

FBGA Package Capacitan ce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

IDD7 Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

Data Sheet Designation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94

512Mb: x4, x8, x16

DDR2 SD RAM

PRELIMINARY

09005aef80b88542 M icron Technol ogy, Inc., rese rve s the right to ch ange produc ts or spe c ifi ca t io ns w ith out notice.

List of Figures

Figure 1: 512Mb DDR2 Part Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Figure 2: 92-ball FBGA Pin Assignmen t (x16), 11mm x 19mm (T op View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Figure 3: 92-Ball FBGA Pin Assignmen t (x 4, x 8), 11mm x 19mm (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Figure 4: Functiona l Block Diagr am (32 Meg x 16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

Figure 5: Functiona l Block Diagr am (64 Meg x 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Figure 6: Functiona l Block Diagram (128 M e g x 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

Figure 7: DDR2 Power-Up and Initialization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Figure 8: Mode Register (MR) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Figure 9: CAS Latency (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Figure 10: Extend ed M ode R eg ister Definit ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Figure 11: READ Latenc y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 12: Write Laten cy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Figure 13: Extend ed M ode R eg ister 2 (EMR2) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Figure 14: Extend ed M ode R eg ister 3 (EMR3) Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

Figure 15: ACTIVE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 16: Example: Meeting tRRD (MIN) and tRCD (MIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Figure 17: READ Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

Figure 18: READ Latenc y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Figure 19: Consecut ive READ Burst s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Figure 20: Nonconsecutive READ Bursts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Figure 21: READ Interru pted by READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36

Figure 22: READ to PRECHARGE BL = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Figure 23: READ to PRECHARGE BL = 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Figure 24: READ to WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Figure 25: Bank Read – Wi thout Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Figure 26: Bank Read – Wi th Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Figure 27: x4, x8 Data Out pu t Timing – tDQSQ, tQH, and Data Valid Window . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Figure 2 8 : x16 Data Output Timi ng – tDQSQ, tQH, and Data Valid Win d ow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Figure 29: Data Output Timing – tAC and tDQSCK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

Figure 30: WRITE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Figure 31: WRITE Burst. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Figure 32: Consecut ive WRITE to WRITE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Figure 33: Nonconsecutive WRITE to WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Figure 34: Random WRITE Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Figure 35: WRITE Interrupted by WRITE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46

Figure 36: WRITE to READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Figure 37: WRITE to PRECHARGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Figure 38: Bank Writ e–Without Auto Prechar ge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Figure 39: Bank Writ e–wit h Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50

Figure 40: WRITE–DM Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51

Figure 41: Data Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52

Figure 42: PRECHARGE Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53

Figure 43: Self Refresh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54

Figure 44: Refresh Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Figure 45: Power-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57

Figure 46: READ to Power-Down Ent ry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Figure 47: READ with Auto Precharge to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59

Figure 48: WRITE to Power-Down Entry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Figure 49: WRITE wit h Auto Precharge to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Figure 50: REFRESH command to Power-Down Ent ry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Figure 51: ACTIVE Command to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Figure 52: PRECHARGE Command to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Figure 53: LOAD MODE Command to Power-Down Entry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 54: Inpu t Clock Fr eq uency Change During PRECHARGE Power Down Mode . . . . . . . . . . . . . . . . . . . . . .63

Figure 55: RESET Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64

Figure 56: ODT Timing for Active an d “Fast- Exit” Po w er-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

512Mb: x4, x8, x16

DDR2 SD RAM

PRELIMINARY

09005aef80b88542 M icron Technol ogy, Inc., rese rve s the right to ch ange produc ts or spe c ifi ca t io ns w ith out notice.

Figure 57: ODT timing for “Slow- Exit” and Precharge Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Figure 58: ODT “Turn Of f” Timin gs wh en Entering Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Figure 59: ODT “Turn- On ” Timi ng wh en Entering Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Figure 60: ODT “Turn- Of f” Timin g when Exiting Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Figure 61: ODT “Turn On” Timing when Exiting Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Figure 62: Temperature Tes t Point Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Figure 63: Single-En ded Input Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Figure 64: Differential In pu t Sig nal Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Figure 65: AC Input Test Sign al Waveform Command/Addr e ss p ins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Figure 66: AC Input Test Signal Waveform for Data with DQS,DQS# (differential) . . . . . . . . . . . . . . . . . . . . . . . .77

Figure 67: AC Input Test Signal Waveform for Data with DQS (single-ended) . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Figure 68: AC Input Test Signal Wave form (differential). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

Figure 69: Inpu t Clam p Cha ra ct e ristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Figure 70: Overshoot. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Figure 71: Undershoot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Figure 72: Differential Output Signal Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Figure 73: AC Timing Reference Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Figure 74: Output Slew Rat e Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

Figure 75: Full Stre ngth Pull-Down Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Figure 76: Full Stre ngth Pull-up Chara ct e ristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

Figure 77: Package Drawing (x4,x8,x16 Configurations) 11mm x 19mm “FT” FBGA . . . . . . . . . . . . . . . . . . . . . . . 94

512Mb: x4, x8, x16

DDR2 SD RAM

PRELIMINARY

09005aef80b88542 M icron Technol ogy, Inc., rese rve s the right to ch ange produc ts or spe c ifi ca t io ns w ith out notice.

List of Tabl es

Table 1: Key Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Table 1: FBGA Ball Descriptions 128 Meg x 4, 64 Meg x 8, 32 Meg x 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Table 2: Burst Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Table 3: Truth Table – DDR2 Command s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

Table 4: Truth Table – Current State Bank n - Command to Bank n. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 5: Truth Table – Current State Bank n - Command to Bank m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

Table 6: Concurrent Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Table 7: READ Using Concurrent Auto Precha rge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Table 8: WRITE Using Concurrent Auto Prech ar ge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44

Table 9: CKE Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58

Table 10: ODT Timing for Active an d “Fast-Exit” Power-Do wn Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66

Table 11: ODT timing for “Slow-Exit” and Precharge Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67

Table 12: ODT “Turn Off” Timings when En ter ing Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68

Table 13: ODT “Turn-On” Timing wh en Entering Power-Down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69

Table 14: ODT “Turn-Of” Timing wh en Exiting Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70

Table 15: ODT “Turn On” Timing when Exiting Power-Down Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Table 16: Absolute Maximum DC Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Table 17: Recommended DC Operating Condi tions (SST L_ 18). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Table 18: ODT DC Electrical Ch aracterist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73

Table 19: Input DC Logic Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Table 20: Input AC Logic Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74

Table 21: Differential Input Logic Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Table 22: AC Input Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Table 23: Input Clamp Charact e ristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78

Table 24: Address and Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Table 25: Clock, Data, Strobe, and Ma sk Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79

Table 26: Differential AC Output Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Table 27: AC Output Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

Table 28: Output DC Current Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

Table 29: Output Charact e ristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81

Table 30: Pulldown Current (mA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82

Table 31: Pull-Up Current (mA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83

Table 32: Input Capacit an ce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84

Table 33: DDR2 IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Table 34: General IDD Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Table 35: IDD7 Timing Patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Table 36: AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88

512Mb: x4, x8, x16

DDR2 SD RAM

PRELIMINARY

09005aef80b88542 M icron Technol ogy, Inc., rese rve s the right to ch ange produc ts or spe c ifi ca t io ns w ith out notice.

Part Numbers

Figure 1: 512Mb DDR2 Part Numbers

NOTE: Not all speeds and all configurations are

availab l e in all packages.

FBGA Part Marking Decoder

Due to space limitations, FBGA-packaged compo-

nents have an abbreviated part marking that is differ-

ent from the part number. Micron's new FBGA Part

Marking Decoder makes it easier to understand that

part marking. Visit the web site at www.micron.com/

decoder.

General D e scrip tion

The 512Mb DDR2 SDRAM is a high-speed, CMOS

dynamic random-access memory containing

536,870,912 bits. It is internally configured as a quad-

bank DRAM. Figures 5, 6, and 7 show the functional

block diagrams of the 32 Meg x 16, 64 Meg x 8, and 128

Meg x 4 devices, respectively. Ball assignments for the

128 Meg x 4 are shown in Figure 2 and signal descrip-

tions are shown in Table1. Ball assignments for the 64

Meg x 8 an d 128 Meg x 4 are shown in Figure3 and sig-

nal descriptions are shown in Table1.

The 512Mb DDR2 SDRAM uses a double data rate

architecture to achieve high-speed operation. The

double data rate architecture is essentially a 4n-

prefetch architecture with an interface designed to

transfer two data words per clock cycle at the I/O pins.

A single read or write access for the 512Mb DDR2

SDRAM effectively consists of a single 4n-bit-wide,

one-clock-cycle data transfer at the internal DRAM

core and four corresponding n-bit-wide, one-half-

clock-cycle data transfers at the I/O pin s.

A bidir ectional data st r obe (DQS, DQ S#) is transmit-

ted externally, along with data, for use in data capture

at the receiver. DQS is a strobe transmitted by the

DDR2 SDRAM during READs and by the memory con-

troller during WRITEs. DQS is edge-aligned with data

for READs and center-aligned with data for WRITEs.

The x16 offering has two data strobes, one for the lower

byte (LDQS, LDQS#) and one for the upper byte

(UDQS, UDQS#).

The 512Mb DDR2 SDRAM operates from a differen-

tial clock (CK and CK#); the crossing of CK going HIGH

and CK# going LOW will be referred to as the positive

edge of CK. Commands (address and control signals)

are registered at every positive edge of CK. Input data

is registered on both edges of DQS, and output data is

referenced to both edges of DQS, as well as to both

edges of CK.

Read and write accesses to the DDR2 SDRAM are

burst-oriented; accesses start at a selected location

and continue for a programmed number of locations

in a programmed sequence. Accesses begin with the

registra tion of an ACTIVE co mmand, wh ich is th en fol -

lowed by a READ or WRITE command. The address

bits registered coincident with the ACTIVE command

are used to select the bank and row to be accessed.

The address bits registered coincident with the READ

or WRITE command are used to select the bank and

the starting column location for the burst access.

The DDR2 SDRAM provides for programmable read

or write burst lengths of four or eight locations. DDR2

SDRAM supports interrupting a burst read of eight

with another read, or a burst write of eight with

another write. An auto precharge function may be

enabled to provide a self-timed row precharge that is

initiated at the end of the burst access.

As with standard DDR SDRAMs, the pipelined,

multibank architecture of DDR2 SDRAMs allows for

concurrent operation, thereby providing high, effec-

tive ban dwi dth by hiding row prechar g e and act i va ti on

time.

A self refresh m ode is provided, along with a power-

saving power-down mode.

All inputs are compatible with the JEDEC standard

for SSTL_18. All full drive-strength outputs are

SSTL_18-compatible.

NOTE: 1. The functionality and the timing specifications

discussed in this data sheet are for the DLL-

enabled mode of operati on.

2. Throughout the data sheet, the various figures

and text refer to DQs as “DQ.” The DQ term is to

be interpreted as any and all DQ collectively,

ConfigurationMT47H Package Speed

Configuration

128 Meg x 4

64 Meg x 8

32 Meg x 16

128M4

64M8

32M16

Package

92-Ball 11 x 19 FBGA

Speed Grade

tCK = 5ns, CL = 4

tCK = 5ns, CL = 3

tCK = 3.75ns, CL = 4

-5

-5E

-37E

Example Part Number: MT47H64M8FT-37E

512Mb: x4, x8, x16

DDR2 SD RAM

PRELIMINARY

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unless specifically stated ot her w ise. Additionally,

the x16 is divided into two bytes, the lower byte

and upper byte. For the lower byte (DQ0 through

DQ7) DM refers to LDM and DQS refers to LDQS.

For the upper byte (DQ8 through DQ15) DM

refers to UDM and DQS refers to UDQS.

3. Complete functionality is described throughout

the document and any page or diagram may

have been simplified to convey a topic and may

not be inclusive of all requirements.

4. Any specific requirement takes precedence over

a general statement.

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Figure 2: 92-b a ll F BGA Pi n Assignment

(x16), 11mm x 19mm (Top View) Figure 3: 92-Ball FBGA Pi n Assignment

(x 4, x 8), 11mm x 19mm (Top V iew)

1234 67895

VDD

DQ14

VDDQ

DQ12

VDD

DQ6

VDDQ

DQ4

VDDL

RFU(BA2)

VSS

VDD

VSSQ

DQ9

VSSQ

DQ1

VSSQ

VREF

CKE

BA0

A10

A12

VSS

UDM

VDDQ

DQ11

VSS

LDM

VDDQ

DQ3

VSS

WE#

BA1

RFU (A14)

VSSQ

UDQS

VDDQ

DQ10

VSSQ

LDQS

VDDQ

DQ2

VSSDL

RAS#

CAS#

A11

RFU (A15)

VDDQ

DQ15

VDDQ

DQ13

VDDQ

DQ7

VDDQ

DQ5

VDD

ODT

VDD

VSS

UDQS#/NU

VSSQ

DQ8

VSSQ

LDQS#/NU

VSSQ

DQ0

VSSQ

CK#

CS#

NC (A13)

1234 67895

VDD

NF,DQ6

VDDQ

NF,DQ4

VDDL

RFU (BA2)

VSS

VDD

NC,RDQS#/NU

VSSQ

DQ1

VSSQ

VREF

CKE

BA0

A10

A12

VSS

DM,DM/RDQS

VDDQ

DQ3

VSS

WE#

BA1

RFU (A14)

VSSQ

DQS

VDDQ

DQ2

VSSDL

RAS#

CAS#

A11

RFU (A15)

VDDQ

NF,DQ7

VDDQ

NF,DQ5

VDD

ODT

VDD

VSS

DQS#/NU

VSSQ

DQ0

VSSQ

CK#

CS#

A13

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Table 1: FBGA Ball Descriptions 128 Meg x 4 , 64 Meg x 8, 32 Meg x 16

x16 FBGA

BALL

ASSIGNMENT

x4, x8 FBGA

BALL

ASSIGNMENT SYMBOL TYPE DESCRIPTION

N9 N9 ODT Input On-Die Termination: ODT (registered HIGH) enables termination

resis tanc e in ter nal to the D DR2 SDRAM. When enabled, ODT is only

applied to each of the following pins: DQ0–DQ15, LDM, UDM,

LDQS, LDQS#, UDQS, and UDQS# for the x16; DQ0-DQ7, DQS, DQS#,

RDQS, RDQS#, and DM for the x8; DQ0-DQ3, DQS, DQS#, and DM

for the x4. The ODT input will be ignored if disabled via the LOAD

MOD E com m and.

M8, N8 M8, N8 CK, CK# Input Clock: CK and CK# are differential clock inputs. All address and

control input signals are sampled on the crossing of the positive

edge of CK and negative edge of CK#. Output data (DQs and DQS/

DQS#) is referenced to the crossings of CK and CK#.

N2 N2 CKE Input Clock Enable: CKE (registered HIGH) activates and CKE (registered

LOW) deactivates clocking circuitry on the DDR2 SDRAM. The

specific circuitry that is enabled/disabled is dependent on the DDR2

SDRAM configuration and operating mode. CKE LOW provides

PRECHAR GE POWER-DOWN and SELF REFRESH operatio ns (all banks

idle), or ACTIVE POWER-DOWN (row ACTIVE in any bank). CKE is

synchronous for POWER-DOWN entry, POWER-DOWN exit, output

disable, and for SELF REFRESH entry. CKE is asynchronous for SELF

REFRESH exit. Input buffers (excluding CK, CK#, CKE, and ODT) are

disabled during POWER-DOWN. Input buffers (excluding CKE) are

disabled during SELF REFRESH. CKE is an SSTL_18 input but will

detect a LVCMOS LOW level once Vdd is applied during first power-

up. After Vref has become stable during the power on and

initialization sequence, it must be maintained for proper operation

of the CKE receiver. For proper self-refresh operation Vref must be

maintained to this input.

P8 P8 CS# Input Chip Select: CS# enables (registered LOW) and disables (registered

HIGH) the command decoder. All commands are masked when CS#

is registered HIGH. CS# provides for exter nal bank selection on

systems with multiple ranks. CS# is considered part of the command

code.

N7, P7, N3 N7, P7, N3 RAS#,

CAS#,

WE#

Input Comm and Inputs: RAS #, CAS#, and WE # (along w ith CS#) defi ne the

command being entered.

J3, E3 J3, E3 LDM,

UDM Input Input Data Mask: DM is an input mask signal for write data. Input

data is masked when DM is sampled HIGH along with that input

data during a WRITE access. DM is sampled on both edges of DQS.

Although DM pins are input-only, the DM loading is designed to

match that of DQ and DQS pins. LDM is DM f or lower byte DQ0–

DQ7 and UDM is DM for upper byte DQ8–DQ15.

P2, P3 P2, P3 BA0, BA1 Input Bank Address Inputs: BA0 and B A1 define to whi ch bank an ACTIVE ,

READ, WRITE, or PRECHARGE command is being applied. BA0 and

BA1 define which mode register including MR, EMR, EMR(2), and

EMR(3) is loaded during the LOAD MODE command.

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R8,R3,R7,T2,

T8,T3,T7,U2,

U8,U3,R2,U7,

– A0–A12 Input Address Inputs: Provide the row address for ACTIVE commands, and

the column address and auto precharge bit (A10) for Read/Write

commands, to select one location out of the memory array in the

respective bank. A10 sampled during a PRECHARGE command

determines whether the PRECHARGE applies to one bank (A10

LOW, bank selected by BA0, BA1) or all banks (A10 HIGH). The

address inputs also provide the op-code during a LOAD MODE

command.

– R8,R3,R7,T2,

T8,T3,T7,U2,

U8,U3,R2,U7,

V2,V8

A0–A13 Input Ad dress Inputs: Provide the row address for ACTIVE commands, and

the column address and auto precharge bit (A10) for Read/Write

commands, to select one location out of the memory array in the

respective bank. A10 sampled during a PRECHARGE command

determines whether the PRECHARGE applies to one bank (A10

LOW, bank selected by BA0, BA1) or all banks (A10 HIGH). The

address inputs also provide the op-code during a LOAD MODE

command.

K8,K2,L7,L3,

L1,L9,J1,J9,

F8,F2,G7,G3,

G1,G9,E1,E9

–DQ0–

DQ15 I/O Data Input/Output: Bidirectional data bus for 128 Meg x 4.

– K8,K2,L7,L3,

L1,L9,J1,J9 DQ0–DQ7 I/O Data Input/Output: Bidirectional data bus for 64 Meg x 8.

– K8,K2,L7,L3 DQ0–DQ3 I/O Data Input/Output: Bidirectional data bus for 32 Meg x 16.

E7,D8 – UDQS,

UDQS# I/O Data Strobe for Upper Byte: Output with read data, input with

write data for source synchronous operation. Edge-aligned with

read data , center -aligne d with write d ata. UDQS# is o nly use d when

differential data strobe mode is enabled via the LOAD MODE

command.

J7,H8 – LDQS,

LDQS# I/O Data Strobe for Lower Byte: Output with read data, input with

write data for source synchronous operation. Edge-aligned with

read data, cen ter-aligned w ith write data . LDQS# is onl y use d when

differential data strobe mode is enabled via the LOAD MODE

command.

– J7,H8 DQS,

DQS# I/O Data Strobe: Output with read data, input with write data for

source syn chronous opera tion. Edge-aligne d with re ad data, ce nter

aligned with write data. DQS# is only used when differential data

strobe mode is enabled via the LOAD MODE command.

–J3,H2RDQS,

RDQS# Output Redundant Data Strobe for 64 Meg x 8 only. RDQS is enabled/

disabled via the LOAD MODE command to the Extended Mode

data only and is ig nored during w rite data. When RDQ S is disab led,

pin B3 becomes Data Mask (see DM pin). RDQS# is only used when

RDQS is enabled AND differential data strobe mode is enabled.

D1,H1,M9,R9,

V1 D1,H1,M9,R9,

V1 VDD Supply Power Supply: 1.8V ±0.1V

M1 M1 VDDL Supply DLL Pow er Suppl y: 1.8V ±0.1 V

D9,F1,F3,F7,

F9,H9,K1,K3,

K7,K9

D9,H9,K1,

K3,K7,K9 VDDQ Supply DQ Power Supply: 1.8V ±0.1V. Isolated on the device for improved

noise immunity.

M2 M2 VREF Supply SSTL_18 reference voltage.

Table 1: FBGA Ball Descriptions 128 Meg x 4 , 64 Meg x 8, 32 Meg x 16

x16 FBGA

BALL

ASSIGNMENT

x4, x8 FBGA

BALL

ASSIGNMENT SYMBOL TYPE DESCRIPTION

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D3,H3,M3,T1,

U9 D3,H3,M3,T1,

U9 VSS Supply Ground.

M7 M7 VSSDL Supply DLL Ground. Isolated on the device from VSS and VSSQ.

D7,E2,E8,G2,

G8,H7,J2,J8,

L2,L8,

D7,H7,J2,

J8,L2,L8 VSSQ Supply DQ Ground. Isolated on the device for improved noise immunity.

A1,A2,A8,A9

D2,H2,V8,

AA1,AA2,AA8,

AA9

A1,A2,A8,A9,

D2,D8,E1-E3,

E7-E9,F1-F3,

F7-F9, G1-G3,

G7-G9,H2,J1,

J9,L1,L9,AA1,

AA2,AA8,AA9

NC – No Connect: These pins should be left unconnected.

– D1, D9, B1, B9 NF – No Function: These pins are used as DQ4-DQ7 on the 64 Meg x 8,

but are NF (No Function) on the 128 Meg x 4 configuration.

D8,H8 H2,H8 NU – Not Used: If EMR[E10] = 0, D8 and H8 are UDQS# and LDQS#.

If EMR[E10] = 1, then D8 and H8 are Not Used.

P1, V3, V7 P1, V3, V7 RFU – Reserved for Future Use; 8 Bank address bit BA2(P1) for 1Gb, 2Gb,

4Gb densities. Row address bits A14(V3) and A15(V7) are reserved

for higher densities.

Table 1: FBGA Ball Descriptions 128 Meg x 4 , 64 Meg x 8, 32 Meg x 16

x16 FBGA

BALL

ASSIGNMENT

x4, x8 FBGA

BALL

ASSIGNMENT SYMBOL TYPE DESCRIPTION

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Functio n a l D e scrip tion

The 512Mb DDR2 SDRAM is a high-speed, CMOS

dynamic random-access memory containing

536,870,912 bits. The 512Mb DDR2 SDRAM is inter-

nally configured as a fo ur-bank DRAM.

The 512Mb DDR2 SDRAM uses a double data rate

architecture to achieve high-speed operation. The

DDR2 architecture is essentially a 4n-prefetch archi-

tec ture, with an i n ter face designed to transfer two data

words per clock cycle at the I/O pins. A single read or

write access for t he 512Mb DDR2 SDR AM c onsist s of a

single 4n-bit-w ide, one-clock -cycle da ta transfer at the

internal DRAM core and four corresponding n-bit-

wide, one-half-clock-cycle data transfers at the I/O

pins.

Prior to normal operation, the DDR2 SDRAM must

be initialized. The following sections provide detailed

information cov ering device initialization, register def-

inition, c o mmand descriptions, and device operation.

Figure 4: Functional Block Diag ram (32 Meg x 16)

13 ROW-

ADDRESS

MUX

CONTROL

LOGIC

COLUMN-

ADDRESS

COUNTER/

LATCH

MODE REGISTERS

A0-A12,

BA0, BA1

ADDRESS

256

(x64)

16,384

I/O GATING

DM MASK LOGIC

COLUMN

DECODER

BANK0

MEMORY

ARRAY

(8,192 x 256 x 64)

BANK0

ROW-

ADDRESS

LATCH

DECODER

8,192

SENSE AMPLIFIERS

BANK

CONTROL

LOGIC

BANK1

BANK2

BANK3

REFRESH

COUNTER

16 16

RCVRS

CK OUT

DATA

UDQS, UDQS#

LDQS, LDQS#

CK,CK#

COL0,COL1

CK IN

DRVRS

DLL

MUX

DQS

GENERATOR

UDQS, UDQS#

LDQS, LDQS#

READ

LATCH

WRITE

FIFO

DRIVERS

DATA

MASK

BANK1

BANK2

BANK3

INPUT

REGISTERS

UDM, LDM

DQ0 - DQ15

VDDQ

sw1 sw2

VssQ

sw1 sw2

ODT CONTROL

RAS#

CAS#

CS#

WE#

CK#

COMMAND

DECODE

CKE

ODT

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Figure 5: Functional Block Diagram (64 Meg x 8)

Figure 6: Functional Block Diag ram (128 Meg x 4)

14 ROW-

ADDRESS

MUX

CONTROL

LOGIC

COLUMN-

ADDRESS

COUNTER/

LATCH

MODE REGISTERS

COMMAND

DECODE

A0-A13,

BA0, BA1

ADDRESS

256

(x32)

8,192

I/O GATING

DM MASK LOGIC

COLUMN

DECODER

BANK0

MEMORY

ARRAY

(16,384 x 256 x 32)

BANK0

ROW-

ADDRESS

LATCH

DECODER

16,384

SENSE AMPLIFIERS

BANK

CONTROL

LOGIC

BANK1

BANK2

BANK3

REFRESH

COUNTER

RCVRS

CK OUT

DATA

DQS, DQS#

Internal

CK,CK#

COL0,COL1

CK IN

DRVRS

DLL

MUX

DQS

GENERATOR

DQ0 - DQ7

DQS, DQS#

READ

LATCH

WRITE

FIFO

DRIVERS

DATA

MASK

BANK1

BANK2

BANK3

INPUT

REGISTERS

RDQS#

VDDQ

sw1 sw2

VssQ

sw1 sw2

ODT CONTROL

RAS#

CAS#

CS#

WE#

CK#

CKE

RDQS

ODT

RAS#

CAS#

ROW-

ADDRESS

MUX

CS#

WE#

CK#

CONTROL

LOGIC

COLUMN-

ADDRESS

COUNTER/

LATCH

MODE REGISTERS

COMMAND

DECODE

A0-A13,

BA0, BA1

CKE

ADDRESS

512

(x16)

8,192

I/O GATING

DM MASK LOGIC

COLUMN

DECODER

BANK0

MEMORY

ARRAY

(16,384 x 512 x 16)

BANK0

ROW-

ADDRESS

LATCH

DECODER

16,384

SENSE AMPLIFIERS

BANK

CONTROL

LOGIC

BANK1

BANK2

BANK3

REFRESH

COUNTER

RCVRS

CK OUT

DATA

DQS, DQS#

Internal

CK, CK#

COL0,COL1

CK IN

DRVRS

DLL

MUX

DQS

GENERATOR

DQ0 - DQ3

DQS, DQS

READ

LATCH

WRITE

FIFO

DRIVERS

DATA

MASK

BANK1

BANK2

BANK3

INPUT

REGISTERS

VDDQ

sw1 sw2

VssQ

sw1 sw2

ODT

sw1 sw2

ODT CONTROL

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Initialization

The following sequence is required for power-up

and initia lization and is shown in Figure7.

1. Apply power; if CKE is maintained below 0.2*

VDDQ, outputs remain disabled. To guarantee Rtt

(ODT Resistance) is off, VREF must be valid and a

low lev el must be applied to the ODT pin (all other

inputs may be undefined). At least one of the fol-

lowing two sets of conditions (A or B) must be

met:

A.CONDITION SET A

•V

DD, VDDL and VDDQ are driven from a single

power co nverter output

•V

TT is limited to 0.95V MAX

•V

REF tra c ks VDDQ/2.

B.CONDITION SET B

•Apply V

DD before or at the same time as VDDL.

•Apply V

DDL before or at the same time as VDDQ.

•Apply V

DDQ before or at the same time as VTT

and VREF.

2. For a minimum of 200µs after stable power and

clock (CK, CK#), apply NOP or DESELECT com-

mands and take CKE HIGH.

3. Wait a minimum of 400ns, then issue a PRE-

CHARGE ALL command.

4. Issue an LOAD MODE command to the EMR(2)

LOW to BA0, and HIGH to BA1.)

5. Issue a LOAD MODE command to the EMR(3)

HIGH to BA0 and BA1.)

6. Issue an LOAD MODE command to the EMR reg-

ister to en able DLL. To issue a DLL ENAB LE com-

mand, provide LOW to BA1, A0 and provide HIGH

to BA0. Bits E7, E8, and E9 must all be set to 0.

7. Issue a LOAD MODE command for DLL Reset.

200 cycles of clock input is required to lock the

DLL. (To issue a DLL Reset, provide HIGH to A8

and provide LOW to BA1 and BA0.)

8. Issue PRECHARGE ALL command.

9. Issue two or more REFRESH commands.

10. Issue a L OAD MODE c omman d with LO W to A8 to

initialize device operation (i.e., to program oper-

ating parameters without resetting the DLL).

11. The DDR2 SDRAM is now intialized and ready for

normal operation 200 clocks after DLL Reset in

step 7.

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Figure 7: DDR2 Power-Up and Init ialization

NOTE:

1. VTT is not applied directly to the dev ic e; howev er, tVTD should be grea ter than or e qua l to zero to avoid devi ce la tch-u p.

One of the following two conditions (a or b) MUST be met:

a)VDD, VDDL, and VDDQ are driven from a single power converter output.

VTT may be 0.95V maximum during power up.

VREF tracks VDDQ/2.

b)Apply VDD before or at the same time as VDDL.

Apply VDDL before or at the same time as VDDQ.

Apply VDDQ before or at the same time as VTT and V REF.

2. Either a NOP or DESELECT command may be applied.

3. 200 cycles of clock (CK, CK#) are required before a READ command can be issued.

4. Two or more REFRESH commands are required.

5. Bits E7, E8, and E9 must all be set to 0.

6. PRE = PRECHARGE command, LM = LOAD MODE command, REF = REFRESH command, ACT = ACTIVE command, RA =

Row Address, BA = Bank Address.

7. DM represents DM for x4, x8 configuration and UDM, LDM for x16 configuration.

DQS represents DQS, DQS#, UDQS, UDQS#, LDQS, LDQS#, RDQS, RDQS# for the appropriate configuration (x4,

x8, x16). DQ represents DQ0–DQ3 for x4, DQ0–DQ 7 for x8, and DQ0–DQ15 for x16.

8. CKE pin uses LVCMOS input levels prior to state T0. After state T0, CKE pin uses SSTL_18 input levels.

9. The LM command for EMR(2) and EMR(3) may be before or after LM command for MR (Tf0) and EMR (Te0).

10. ADDRESS represents A13-A0 for x4, x8, and A12-A0 for x16, BA0, and BA1. A10 should b e HIGH at states Tb0 and Tg0 to

ensure a PRECHARGE (all banks) command is issued.

VTD

CKE

Rtt

Power-up:

VDD and stable

clock (CK, CK#)

T = 200µs (min)

High-Z

DQS

High-Z

ADDRESS10

CK#

REF

DDL

COMMAND

6NOP

PRE

T0 Ta0

DON’T CARE

ODT

High-Z

T = 400ns (min)

Tb0

200 cycles of CK

EMR with

DLL Enable

MR with

DLL Reset

tMRD tMRD tRP tRFC tRFC

CODE9

LM PRELM

REF

LM5

CODE10 CODE10

Tg0 Th0 Ti0 Tj0

MR w/o

DLL Reset

tMRD

Tk0

Te0 Tf0

VALID

NORMAL

OPERATION

EMR(2)

EMR(3)

tMRD tMRD

CODE10 CODE10

tRP

Tc0 Td0

LVCMOS

LOW LEVEL

SSTL_18

LOW LEVEL

Indicates a break in

time scale

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Mode Register (MR)

The mode register is used to define the specific

mode of operation of the DDR2 SDRAM. This defini-

tion includes the selection of a burst length, burst type,

CAS latency, operating mode, DLL reset, write recov-

ery, and power-down mode as shown in Figure 8. Con-

tents of the mode register can be altered by re-

executing the LOAD MODE (LM) command. If the

user chooses to modify only a subset of the MR vari-

ables, all variables (M0–M14) must be programmed

when the LOAD MODE command is issued.

The mode register is programmed via the LM com-

mand (bits BA1, BA0 = 0, 0) and other bits (M13 - M0

for x4 and x8, M12 - M0 for x16) will retain the stored

information until it is programmed again or the device

loses power (except for bit M8, which is self-clearing).

Reprogramming the mode register will not alter the

contents of the memory array, pr ovided it is perf ormed

correctly.

The LOAD MODE command can only be issued (or

reissued) when all banks are in the precharged state.

The controller must wait the specified time tMRD

before initiating any subsequen t op era tions such as an

ACTIVE command. Violating either of these require-

ments will resul t in unspec ified operation.

Bur s t Le ng th

Burst length is defined by bits M0–M3 as shown in

Figure 8. Read and writ e ac cesse s to th e DD R2 SDRA M

are burst-oriented, with the burst length being pro-

grammable to either four or eight. The burst length

determines the maximum number of column loca-

tions that can be accessed for a given READ or WRITE

command.

When a READ or WRITE command is issued, a block

of columns equal to the burst length is effectively

selected. All accesses for that burst take place within

this block, meaning that the burst will wrap within the

block if a boundary is reached. The block is uniquely

selected by A2–Ai when the burst length is set to four

and by A3–Ai when the burst length is set to eight

(where Ai is the most significant column address bit for

a given configuration). The remaining (least signifi-

cant) address bit(s) is (are) used to select the starting

location within the block. The programmed burst

length applies to both READ and WRITE bursts.

Figure 8: Mode Register (MR)

Definition

Burst Type

Accesses within a given burst may be programmed

to be either sequential or interleaved. The burst type is

selected via bit M3 as shown in Figu re 8. The order ing

of accesses within a burst is determined by the burst

length, the burst ty pe, and the starting column address

as shown in Table 2. DDR2 SDRAM supports 4-bit

burst a nd 8-bit burs t modes only. F or 8-bit bu rst mode ,

full interleave addres s ordering is supported; however,

sequential address ordering is nibble-based.

Burst LengthCAS# Latency BT

A9 A7 A6 A5 A4 A3A8 A2 A1 A0

Mode Register (Mx

)

Address Bus

9765438210

A10A12 A11BA0BA1

10111213

*M13 (A13) is reserved for future use and must be programmed to '0.'

A13 is not used in x16 configuration.

Burst Length

Reserved

Burst Type

Sequential

Interleaved

CAS Latency

Reserved

Mode

Normal

Test

15 DLL TM

DLL Reset

Yes

WRITE RECOVERY

Reserved

M10

M11

A13

Mode Register Definition

Mode Register (MR)

Extended Mode Register (EMR)

Extended Mode Register (EMR2)

Extended Mode Register (EMR3)

M15

PD mode

Fast Exit

(Normal)

Slow Exit

(Low Power)

M12

M14

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Operati ng Mo de

The n ormal op erating mode is selec ted by issuing a

LOAD MODE command with bit M7 set to zero, and all

other bits set to the desired values as shown in

Figure8. When bit M7 is ‘1,’ no other bits of the mode

places the DDR2 SDRAM into a test mode that is only

used by the Manufacturer and should NOT be used. No

operation or functionality is guarante ed if M7 bit is ‘1.’

DLL Reset

DLL rese t is de fined by bi t M8 as shown in Figu re 8.

Programming bit M8 to ‘1’ will activate the DLL RESET

function. Bit M8 is self-clearing, meaning it returns

back to a value of ‘0’ after the DLL RESET function has

been issued .

Anytime the DLL RESET function is used, 200 clock

cycles must occur before a READ command can be

issued to allow time for the internal clock to be syn-

chronized with the external clock. Failing to wait for

synchronization to occur may result in a violation of

the tAC or tDQSC K paramet e rs.

Write Recovery

Wr i te recovery (WR) time is defined by bits M9–M11

as shown in Figure8. The WR Register is used by the

DDR2 SDRAM during WRITE /w AUTO PRECHARGE

operation. During WRITE /w AUTO PRECHARGE

opera ti on, th e DDR2 SDRAM delays the in terna l AUTO

PRECHARGE operat ion by WR clocks (programmed in

bits M9-M11) from the last data burst. An example of

Write /w AUTO PRECHARGE is shown in Figure39 on

page 50.

Write Recovery ( WR) values of 2, 3, 4, 5, or 6 clocks

may be used for programming bits M9–M11. The user

is required to program the value of write recovery,

which is calculated by dividing tWR (in ns) by tCK (in

ns) and rounding up a noninteger value to the next

integer; WR [cycles] = tWR [ns] / tCK [ns]. Reserved

states should not be used as unknown operation or

incompatibility with f ut ure versions may result.

Power-Down Mode

Active power-down (PD) mode is defined by bit M12

as shown in Figure8. PD mode allows the user to

determine the active power-down mode, which deter-

mines performance vs. power savings. PD mode bit

M12 does not apply to precharge power-down mode.

When bit M12 = 0, standard Active Power-down

mode or ‘fast-exit’ active power-down mode is

enabled. The tXARD parameter is used for ‘fast-exit’

active power-down exit timing. The DLL is expected to

be enabled and running during this mode.

When bit M12 = 1, a lower power active power-down

mode or ‘slow-exit’ active power-down mode is

enabled. The tXARDS parameter is used for ‘slow-exit’

active power-down exit timing. The DLL can be

enabled, but ‘frozen’ during active power-down mode

since the exit-to-READ command timing is relaxed.

The power difference expected between PD ‘normal’

and PD ‘low-power’ mode is defined in the IDD table.

CAS Latency (CL)

The CAS Latency (CL) is defined by bits M4–M6 as

shown in Figure8. CAS Latency is the delay, in clock

cycles, between the registration of a READ command

and the availability of the first bit of output data. The

CAS Latency can be set to 3 or 4 clocks. CAS Latency of

2 or 5 clocks are JEDEC optional features and may be

enabled in future speed grades. DDR2 SDRAM does

not support any half clock latencies. Reserved states

should not be used as unknown operation or incom-

patibility with future versions may result.

DDR2 SDRAM also supports a feature called Posted

CAS additive latency (AL). This feature allows the

READ command to be issued prior to tRCD(MIN) by

delaying the internal command to the DDR2 SDRAM

by AL clocks . The AL featur e is described in mor e detail

in the Extended Mode Register (EMR) and Operational

sections.

Table 2: Burst Definition

BURST

LENGTH

STARTING

COLUMN

ADDRESS

(A2, A1,

A0)

ORDER OF ACCESSES WITHIN

A BURST

BURST TYPE =

SEQUENTIAL BURST TYPE =

INTERLEAVED

4 0 0 0 0,1,2,3 0,1,2,3

0 0 1 1,2,3,0 1,0,3,2

0 1 0 2,3,0,1 2,3,0,1

0 1 1 3,0,1,2 3,2,1,0

8 0 0 0 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7

0 0 1 1,2,3,0,5,6,7,4 1,0,3,2,5,4,7,6

0 1 0 2,3,0,1,6,7,4,5 2,3,0,1,6,7,4,5

0 1 1 3,0,1,2,7,4,5,6 3,2,1,0,7,6,5,4

1 0 0 4,5,6,7,0,1,2,3 4,5,6,7,0,1,2,3

1 0 1 5,6,7,4,1,2,3,0 5,4,7,6,1,0,3,2

1 1 0 6,7,4,5,2,3,0,1 6,7,4,5,2,3,0,1

1 1 1 7,4,5,6,3,0,1,2 7,6,5,4,3,2,1,0

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Examples of CL = 3 and CL = 4 are shown in Figure 9;

both assume AL = 0. If a READ command is registered

at clock edge n, and the CAS Latency is m clocks, the

data will be available nominally coincident with clock

edge n + m (this assumes AL = 0). Figure 9: CAS Latency (CL)

OUT

n + 3

OUT

n + 2

OUT

n + 1

CK#

COMMAND

DQS, DQS#

CL = 3 (AL = 0)

READ

Burst length = 4

Posted CAS# additive latency (AL) = 0

Shown with nominal tAC, tDQSCK, and tDQSQ

T0 T1 T2

DON’T CARETRANSITIONING DATA

NOP NOP NOP

OUT

T3 T4 T5

NOP NOP

NOP

OUT

n + 3

OUT

n + 2

OUT

n + 1

CK#

COMMAND

DQS, DQS#

CL = 4 (AL = 0)

READ

T0 T1 T2

NOP NOP NOP

OUT

T3 T4 T5

NOP NOP

NOP

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Extended Mode Register (EMR)

The extended mode register controls functions

beyond those controlled by the mode register; these

additional functions are DLL enable/disable, output

drive strength, ODT (RTT), Posted CAS additive latency

(AL), off-chip driver impedance calibration (OCD),

DQS# enable/disable, RDQS/RDQS# enable/disable,

and OUTPUT disable/enable. These functions are

controlled via the bits shown in Figure 10. The

extended mode register is programmed via the LOAD

MODE (LM) command and will retain the stored infor-

mation until it is programmed again or the device

loses power. Reprogramming the extended mode reg-

ister will not alter the contents of the memory array,

provided it is perfor med correctly.

The extended mode register must be loaded when

all banks are idle and no bursts are in progress, and the

controller must wait the specified time tMRD before

init iati ng an y su bseq uent o per atio n. Violat in g eit her o f

these requirements could result in unspecified opera-

tion.

Figure 10: Extended Mode Register

Definition

DLL Enable/Di sabl e

The DLL may be enabled or disabled by program-

ming bit E0 during the LOAD MODE command as

shown in Figure 1 0. The DLL must be ena bled for nor-

mal operation. DLL enable is required during power-

up initialization and upon returning to normal opera-

tion after having disabled the DLL for the purpose of

debugging or evaluation. Enabling the DLL should

always be f ollowed by resetting the D LL using a LOAD

MODE command.

The DLL is automatically disabled when entering

self refresh operation and is automatically re-enabled

and reset upo n e xit of self refresh operatio n.

Any time the DLL is enabled (and subsequently

reset), 200 clock cycles must occur before a READ

command can be issued to allow time for the internal

clock to be synchronized with the external clock. Fail-

ing to wait for synchronization to occur may result in a

violation of the tAC or tDQSCK parameters.

Output Drive Strength

The output drive strength is defined by bit E1 as

shown in Figure 10. The normal drive strength for all

outputs are specified to be SSTL_18. Programming bit

E1 = 0 selects normal (100 percent) drive strength for

all outputs. Selecting a reduced drive strength option

(bit E1 = 1) will redu ce all outputs to approximately 60

percent of the SSTL_18 drive strength. This option is

intended for the support of the lighter load and/or

point-to-point environments.

DQS# Enable/Disable

The DQS# enable function is defined by bit E10.

When enabled (bit E10 = 0), DQS# is the complement

of the differential data strobe pair DQS/DQS#. When

disabled (bit E10 = 1), DQS is used in a single-ended

mode and the DQS# pin is disabled. This function is

also used to enable/disable RDQS#. If RDQS is enabled

(E11 = 1) and DQS# is enabled (E10 = 0), then both

DQS# and RDQS# will be enabled.

RDQS Enable/Disable

The RDQS enable function is defined by bit E11 as

shown in Figure 10. This feature is only applicable to

the 32 Meg x 8 con figuration. When enabled (E11 = 1),

RDQS is identical i n fu nc ti on and timing to da ta strobe

DQS during a READ. During a WRITE operation, RDQS

is ignored by the DDR2 SDRAM.

DLLPosted CAS# Rttout

A9 A7 A6 A5 A4 A3A8 A2 A1 A0

Extended Mode

Address Bus

9765438210

A10A12 A11BA0BA1

10111213

Output Drive Strength

100%

60%

Posted CAS# Additive Latency (AL)

Reserved

DLL Enable

Enable (Normal)

Disable (Test/Debug)

RDQS Enable

Yes

E11

OCD Program

A13

ODS

Rtt

DQS#

DQS# Enable

Enable

Disable

E10

RDQS

Rtt (nominal)

Rtt Disabled

75 ohm

150 ohm

Reserved

OCD Operation

OCD Not Supported

Reserved

Outputs

Enabled

Disabled

E12

Mode Register Definition

Mode Register (MR)

Extended Mode Register (EMR)

Extended Mode Register (EMR2)

Extended Mode Register (EMR3)

E15

E14

EMR

*M13 (A13) is reserved for future use and must be programmed to '0.'

M13 is not used in x16 configuration.

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Output Enable/Disable

The OUTPUT enable function is defined by bit E12

as shown in Figure 10. When enabled (E12 = 0 ) , all out-

puts (DQs, DQS, DQS#, RDQS, RDQS#) function nor-

mally. When disabled (E12 = 1), all DDR2 SDRAM

outputs (DQs, DQS, DQS#, RDQS, RDQS#) are disabled

removing output buffer current. The OUTPUT disable

featu re is intended t o be used during IDD characteriza-

tion of read current.

On Die Termination (ODT)

ODT effe c tive resist ance RTT (EFF) is defined by bits

E2 and E6 of the EMR as shown in Figure 10. T he ODT

feature is designed to improve signal integrity of the

memory channel by allowing the DDR2 SDRAM con-

troller to independently turn on/off ODT for any or all

devices. RTT effective resistance values of 75W and

150W are selectable and apply to each DQ, DQS/DQS#,

RDQS/RDQS#, UDQS/UDQS#, LDQS/LDQS#, DM,

and UDM/LDM signals. A functional representation of

ODT is shown in block diagrams Figure 4 on page 13,

Figure5 on p age 14, and Figure 6 on page 14 for the x4,

x8, and x16 configurations, respectively. Bits (E6, E2)

determine what ODT resistance is enabled by turning

on/off ‘sw1’ or ‘sw2’. The ODT effective resistance

value is selected by enabling switch ‘sw1,’ which

enable s all ‘R1’ values th at are 150W each, enabling an

effective resistance of 75W (RTT (EFF1) = ‘R1’ / 2). Sim-

ilarly, if ‘sw2’ is enabled, all ‘R2’ values that are 300W

each, enable an effective ODT resistance of 150W (RTT

(EFF2) = ‘R2’/2). Reserved states should not be used, as

unknown operatio n or incompatibility with future ver-

sions may result.

The ODT control pin is used to determine when

RTT(EFF) is turned on and off, assuming ODT has been

enabled via bits E2 and E6 of the EMR. The ODT fea-

ture and ODT input pin are only used during active,

active power-down (both fast-exit and slow-exit

modes), and precharge power-down modes of opera-

tion. If SELF REFRESH operation is used, RTT (EFF)

should always be disabled and the ODT input pin is

disabled by the DDR2 SDRAM. During power-up and

initial izat ion of the DDR2 SDRA M, ODT should be d is-

abled until the EMR command is issued to enable the

ODT feature, at which point the ODT pin will deter-

mine the RTT (EFF) value. See “ODT Timing” on

page 65 f or ODT timing diagrams.

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Off-Chip Driver (OCD) Impedan c e Calibratio n

The OCD function is no longer supported and must

be set to the de fault state. E7, E8, and E9 must be set t o

Posted CAS Additive Laten cy (AL)

Posted CAS additive latency (AL) is supported to

make the command and data bus efficient for sustain-

able bandwidths in DDR2 SDRAM. Bits E3–E5 define

the value of AL as shown in Figure 10. Bits E3–E5 allow

the user to program the DDR2 SDRAM with a CAS#

Additive latency of 0, 1, 2, 3, or 4 clocks. Reserved states

should not be used as unknown operation or incom-

patibility with future versions may result.

In this operation, th e DDR2 SDRAM allows a READ

or WRITE command to be issued prior to tRCD (M IN )

with the requirement that AL £ tRCD(MIN). A typical

application using this feature would set AL = tRCD

(MIN) - 1 x tCK. The READ or WRITE command is held

for the time of the additive latency (AL) before it is

issued internally to the DDR2 SDRAM device. READ

Latency (RL) is controlled by the sum of the Posted

CAS additive latency (AL) and CAS Latency (CL); RL =

AL + CL. Write latency (WL) is equal to READ latency

minus one clock; WL = AL + CL - 1 x tCK. An example

of a READ latency is shown in Figure 11. An example of

a WRITE la t en cy is shown in Figure12.

Figure 11: READ Laten c y

Figure 12: Write Latency

OUT

n + 3

OUT

n + 2

OUT

n + 1

CK#

COMMAND

DQS, DQS#

AL = 2

ACTIVE n

Burst length = 4

Shown with nominal tAC, tDQSCK, and tDQSQ

T0 T1 T2

DON’T CARETRANSITIONING DATA

READ nNOP NOP

OUT

T3 T4 T5

NOP

T7 T8

NOP NOP

CL = 3

RL = 5

CAS# latency (CL) = 3

Additive latency (AL) = 2

READ latency (RL) = AL + CL = 5

tRCD (MIN)

NOP

CK#

COMMAND

DQS, DQS#

ACTIVE n

Burst length = 4

T0 T1 T2

DON’T CARETRANSITIONING DATA

NOP NOP

T3 T4 T5

NOPWRITE n

NOP

n + 3

n + 2

n + 1

WL = AL + CL - 1 = 4

NOP

CAS# latency (CL) = 3

Additive latency (AL) = 2

WRITE latency = AL + CL -1 = 4

RCD (MIN)

NOP

AL = 2 CL - 1 = 2

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Extended Mode Register 2 (EMR2)

The Extended Mode Register 2 (EMR2) controls

functions beyond those controlled by the mode regis-

ter. Currently all bits in EMR2 are reserved as shown in

Figure 13. The EMR2 is programmed via the LOAD

MODE command and will retain the stored informa-

tion until it is programmed again or the device loses

power. Reprogramming the extended mode register

will not alter the contents of the memory array, pro-

vided it is performed correctly.

The extended mode register must be loaded when

all banks are idle and no bursts are in progress, and the

controller must wait the specified time tMRD before

initiating any subsequent operation. Violating either

of these r equir em ents coul d r es ult in uns pecif ied oper -

ation.

Figure 13: Extended Mode Register 2

(EMR2) Definition

Extended Mode Register 3 (EMR3)

The Extended Mode Register 3 (EMR3) controls

functions beyond those controlled by the mode regis-

ter. Currently all bits in EMR3 are reserved as shown in

Figure 14. The EMR3 is programmed via the LOAD

MODE command and will retain the stored informa-

tion until it is programmed again or the device loses

power. Reprogramming the extended mode register

will not alter the contents of the memory array, pro-

vided it is performed correctly.

The extended mode register must be loaded when

all banks are idle and no bursts are in progr ess, and the

controller must wait the specified time tMRD before

initiating any subsequent operation. Violating either of

these requirements could result in unspecified opera-

tion.

Figure 14: Extended Mode Register 3

(EMR3) Definition

A9 A7 A6 A5 A4 A3A8 A2 A1 A0

Extended Mode

Address Bus

9765438210

A10A12 A11BA0BA1

10111213

* E13 (A13) - E0 (A0) are reserved for future

use and must all be programmed to '0'.

A13 is not used in x16 configuration.

A13

Mode Register Definition

Mode Register (MR)

Extended Mode Register (EMR)

Extended Mode Register (EMR2)

Extended Mode Register (EMR3)

M15

M14

EMR2 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0*

A9 A7 A6 A5 A4 A3A8 A2 A1 A0

Extended Mode

Address Bus

9765438210

A10A12 A11BA0BA1

10111213

1415

A13

Mode Register Definition

Mode Register (MR)

Extended Mode Register (EMR)

Extended Mode Register (EMR2)

Extended Mode Register (EMR3)

M15

M14

EMR3 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0* 0*

* E13 (A13) - E0 (A0) are reserved for future

use and must all be programmed to '0'.

A13 is not used in x16 configuration.

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Command Truth Tables

The following tables provide a quick reference of

DDR2 SDRAM available commands, including CKE

power-down modes, and bank-to-bank commands.

NOTE:

1. All DDR2 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE#, and CKE at the rising edge of the clock.

2. Bank addresses (BA) BA0, BA1 determine which bank is to be operated upon. BA during a Load Mode command selects

which mode register is programmed.

3. Burst reads or writes at BL = 4 cannot be terminated or interrupted. See sections “Read Interrupted by a Read” and

“Write Interrupted by a Write” for other restrictions and details.

4. The Power Down Mode does not perform any refresh operations. The duration of power-down is therefore limited by

the refresh requirements outlined in the AC parametric section.

5. The state of ODT does not affect the states described in this table. The ODT function is not available during self refresh.

See the ODT section for details.

6. “X” means “H or L” (but a defined logic level).

7. Self refresh exit is asynchronous.

Table 3: Truth Table – DDR2 Commands

Notes: 1, 5, and 6 apply to the entire Table.

FUNCTION CKE CS# RAS# CAS# WE# BA1,

BA0 A13–

A11 A10 A9–A0 NOTES

CYCLE CURRENT

CYCLE

Load Mode H H L L L L BA OP Code 2

Refresh HHLLLHXXXX

Self Refresh Entry HLLLLHXXXX

Self Refresh Exit LH

HXXX XXXX 7

LHHH

Single Bank

Precharge HHLLHLBAXLX2

ALL Banks Prechar ge HHLLHLXXHX

Bank Activate H H L L H H BA Row Address

Write HHLHLLBA

Column

Address LColumn

Address 2, 3

Write with Auto

Precharge HHLHLLBA

Column

Address HColumn

Address 2, 3

Read HHLHLHBA

Column

Address LColumn

Address 2, 3

Read with Auto

Precharge HHLHLHBA

Column

Address HColumn

Address 2, 3

No Operation HXLHHHXXXX

Device Deselect HXHXXXXXXX

Power -Down Entry HL

HXXX XXXX 4

LHHH

Power -D o wn Exi t LH

HXXX XXXX 4

LHHH

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NOTE:

1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH (see Table 4) and after tXSNR has been met (if the pr evious

state was self refresh).

2. This table is b ank-sp ecific, ex cept w here noted (i.e ., the current state is for a specific bank and the commands shown a re

those allowed to be issued to that bank when in that state). Exceptions are covered in the notes below.

3. Current state definitions:

Idle: The bank has been precha rged , and tRP has been met.

Row Active : A row in the bank has bee n ac tivated, and tRCD ha s been met. No data bursts/accesses and no reg-

ister accesses are in progress.

Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated.

4. The following states must not be interrupted by a command issued to the same bank. DESELECT or NOP commands, or

allowable commands to the other bank, should be issued on any clock edge occurring during these states. Allowable

commands to the other bank are determined by its current state and Ta ble 4, and according to Table 5.

Precharging: Starts with registration of a PRECHARGE command and ends when tRP is met. Once tRP is met, the

bank will be in the idle state.

Row Activating: Starts with registration of an ACTIVE command and ends when tRCD is met. Once tRCD is met,

the bank will be in the “row active” state.

Read with Auto Precharge Enabled: Starts with registration of a READ command with auto precharge enabled

and ends when tRP has been met. Once tRP is met, the bank will be in the idle state.

Write with Auto Precharge Enabled: Starts with registration of a WRI TE command with au to precharge enabled

and ends when tRP has been met. Once tRP is met, the bank will be in the idle state.

5. The following states must not be interrupted by any executable command; DESELECT or NOP commands must be

applied on each positive clock edge during these states.

Refreshing: Starts with registration of an REFRESH command and ends when tRFC is met. Once tRFC is met, the

DDR2 SDRAM will be in the all banks idle state.

Accessing Mode Register: Starts with registration of a LOAD MODE command and ends when tMRD has been

met. On ce tMRD is met, the DDR2 SDRAM will be in the all banks idle state.

Precharging All: Starts with registration of a PRECHARGE ALL command and ends when tRP is met. Once tRP is

met, all banks will be in the idle state.

6. All states and sequences not shown are illegal or reserved.

Table 4: Truth Table – Current State Bank n - Command to Bank n

Notes: 1–6; notes appear below and on next page

CURRENT

STATE CS# RAS# CAS# WE# COMMAND/ACTION NOTES

Any HXXX

DESELECT (NOP/continue previous operation)

LHHH

NO OPERATION (NOP/continue previous

operation)

Idle L L H H ACTIVE (select and activate row)

LLLH

REFRESH 7

LLLL

LOAD MODE 7

Row ActiveLHLH

READ (select column and start READ burst) 9

LHLL

WRITE (select column and start WRITE burst) 9

LLHL

PRECHARGE (deactivate row in bank or banks) 8

Read (Auto-

Precharge

Disabled

LHLH

READ (select column and start new READ burst) 9

LHLL

WRITE (select column and start WRITE burst) 9, 11

LLHL

PRECHARGE ( start precharge) 8

Write (Auto-

Precharge

Disabled)

LHLH

READ (select column and start READ burst) 9, 10

LHLL

WRITE (select column and start ne w WRITE burst) 9

LLHL

PRECHARGE (start precharge) 8, 10

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7. Not bank-specific; requires that all banks are idle, and bursts are not in progress.

8. May or may not be bank-specific; if multiple banks are to be precharged, each must be in a valid state for precharging.

9. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and

READs or WRITEs with auto precharge disabled.

10. Requires appropriate DM masking.

11. AWRITE command may be applied after the completion of the READ burst.

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NOTE:

1. This table applies when CKEn - 1 was HIGH and CKEn is HIGH (see Tr uth Table 2) and after tXSNR has been met (if the

previous state was self refresh).

2. This table describes alternate bank operation, except where noted (i.e., the current state is for bank n and the com-

mands shown are those allowed to be issued to bank m, assuming that bank m is in such a state that the given com-

mand is allowable). Exceptions are covered in the notes below.

3. Current state definitions:

Idle: The bank has been precharged, and tRP has been met.

Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no reg-

ister accesses are in progress.

Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated.

Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated.

Read with Aut o Prech arg e Ena bled : See following text – 3a

Write with Auto Precharge Enabled: See following text – 3a

3a.The read with auto precharge enabled or write with auto precharge enabled states can each be broken into

two parts: the access period and the precharge period. For read with auto precharge, the precharge period is

defined as if the same burst was executed with auto precharge disabl ed and then fo llowed with the earlie st pos-

sible PRECHARGE command that still accesses all of the data in the burst. For write with auto precha rge, the pre-

charge period begins when tWR ends, with tWR measured as if auto precharge was disabled. The access period

starts with registration of the command and ends where the precharge period (or tRP) begins.

This device suppo rts concurrent auto precharge such that wh en a read with auto prec harge is enabled or a write

with auto precharge is enabled any command to other banks is allowed, as long as that command does not

interrupt the read or write data transfer already in process. In either case, all other related limitations apply

(e.g., contention between read data and write data must be avoided).

Table 5: Truth Table – Current State Bank n - Command to Bank m

Notes: 1–6; notes appear below

CURRENT STATE CS# RAS# CAS# WE# COMMAND/ACTION NOTES

Any HXXX

DESELECT (NOP/continue previous operation)

LHHH

NO OPERATION (NOP/continue previous operation)

Idle XXXX

Any Command Otherwise Allowed to Bank m

Row Activating,

Act ive, or

Precharging

LLHH

ACT IVE (s elect and activate row)

LHLH

READ (select column and start READ burst) 7

LHLL

WRITE (select column and start WRITE burst) 7

LLHL

PRECHARGE

Read (Auto

Precharge

Disabled

LLHH

ACT IVE (s elect and activate row)

LHLH

READ (select column and start new READ burst) 7

LHLL

WRITE (select column and start WRITE burst) 7, 9

LLHL

PRECHARGE

Write (Auto

Precharge

Disabled.)

LLHH

ACT IVE (s elect and activate row)

LHLH

READ (select column and start READ burst) 7, 8

LHLL

WRITE (select column and start new WRITE burst) 7

LLHL

PRECHARGE

Read (with Auto-

Precharge)

LLHH

ACT IVE (s elect and activate row)

LHLH

READ (select column and start new READ burst) 7, 3a

LHLL

WRITE (select column and start WRITE burst) 7, 9, 3a

LLHL

PRECHARGE

Write (w ith Auto-

Precharge)

LLHH

ACT IVE (s elect and activate row)

LHLH

READ (select column and start READ burst) 7, 3a

LHLL

WRITE (select column and start new WRITE burst) 7, 3a

LLHL

PRECHARGE

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3b.The minimum delay from a read or write command with auto precharge enabled, to a command to a differ-

ent bank is summarized below.

4. REFRESH and LOAD MODE commands may only be issued when all banks are idle.

5. Not used.

6. All states and sequences not shown are illegal or reserved.

7. READs or WRITEs listed in the Command/Action column include READs or WRITEs with auto precharge enabled and

READs or WRITEs with auto precharge disabled.

8. Requires appropriate DM masking.

9. A WRITE command may be applied after the completion of the READ burst.

Table 6: Concurrent Auto Precharge

CL = CAS Latency; BL = bust length; WL = WRITE latency

FROM

COMMAND

(BANK n)TO COMMAND (BANK m)MINIMUM DELAY (WITH CONCURRENT

AUTO PRECHARGE) UNITS

WRITE with

Auto

Precharge

READ or READ w/AP (CL - 1) + (BL / 2) + tWTR tCK

WRITE or WRITE w/AP (BL / 2) tCK

PRECHARGE or ACTIVE 1 tCK

READ with

Auto

Precharge

READ or READ w/AP (BL / 2) tCK

WRITE or WRITE w/AP (BL / 2) + 2 tCK

PRECHARGE or ACTIVE 1 tCK

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DESELECT, NOP, and LOAD MODE Commands

DESELECT

The DESELECT function (CS# HIGH) prevents new

commands from being executed by the DDR2 SDRAM.

The DDR2 SDRAM is effectively deselected. Opera-

tion s al ready in pr og ress are not affec ted.

NO OPERATION (NOP)

The NO OPERATION (NOP) command is used to

instruct the selected DDR2 SDRAM to perform a NOP

(CS# is LOW; RAS#, CAS#, and WE are HIGH). This pre-

vent s unwanted commands fr om bei n g registered dur-

ing idle or wait states. Operations already in progress

are not af fecte d.

LOAD MODE (LM)

The mode registers are loaded via inputs BA1, BA0

and A13 – A0 for x4 and x8, and A12 - A0 for x16 config-

urations. BA1 and BA0 determine whic h mode reg ister

will be programmed. See “Mode Register (MR)” on

page 17. The LOAD MODE command can only be

issued when all banks are idle, and a subsequent exe-

cutable command cannot be issued until tMRD is met.

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Bank/Row Activation

ACTIVE Command

The ACTIVE command is used to open (or activate)

a row in a part icular b ank for a sub sequent acce ss. The

value on the BA0, BA1 inputs selects the bank , and the

address provided on inputs A0–A12 selects the row.

This row remains active (or open) for accesses until a

PRECHARGE command is issued to that bank. A PRE-

CHARGE command must be issued before opening a

different row in the same bank.

ACTIVE Operation

Before any READ or WRITE commands can be

issued to a bank within the DDR2 SDRAM, a row in

that bank must be “opened” (activated). This is accom-

plished via the ACTIVE command, which selects both

the bank and the row to be activated, as shown in

Figure 15.

After a row is opened with an ACTIVE command, a

READ or WRITE command may be issued to that row,

subject to the tRCD specification. tRCD (MIN) s hould

be divided by the clock period and rounded up to the

next whole number to determine the earliest clock

edge after the ACTIVE command on which a READ or

WRITE comman d c an be entered. Th e s ame pr oc edu re

is used to convert other specification limits from time

units to cloc k cycles. For example, a tRC D(M IN ) s pe ci-

fication of 20ns with a 266 MHz clock (tCK = 3.75ns)

results in 5.3 clocks rounded up to 6. This is reflected

in Figure 16, which covers any case where 5 < tRCD

(MIN) / tCK £ 6. Figure 16 also shows the case for tRRD

wher e 2 < tRRD (MIN) / tCK £ 3.

A subsequent ACTIVE command to a different row

in the same bank can only be issued after the previous

active row has been “closed” (precharged). The mini-

mum time interval between successive ACTIVE com-

mands to the sam e bank is def ined by tRC.

A subsequent ACTIVE command to another bank

can be issued while the first bank is being accessed,

which results in a reduction of total row-access over-

head. The minimum time inter val between successive

ACTIVE commands to different banks is defined by

tRRD.

DDR2 SDRAM also supports the Posted CAS addi-

tive latency (AL) feature, which allows a READ or

WRITE command to be issued prior to tRCD (MIN) by

delaying the actual registration of the READ/WRITE

command to the internal device by AL clock cycles.

Examples of additive latency are shown in the READ

Command operation section.

Figure 15: ACTIVE Command

Figure 16: Example: Meeting tRRD (MIN) and tRCD (MIN)

DON’T CARE

CK#

CS#

RAS#

CAS#

WE#

CKE

Row

Bank

ADDRESS

BA0, BA1

COMMAND

DON’T CARE

T1T0 T2 T3 T4 T5 T6 T7

RRD

Row Row Col

Bank xBank yBank y

NOPACT NOP NOPACT NOP NOP RD/WR

RCD

BA0, BA1

CK#

ADDRESS

T8 T9

NOP NOP

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READs

READ Comma nd

The R EAD com mand is used t o initiate a burs t read

access to an active row. The value on the BA0, BA1

inputs selects the bank, and the address provided on

inputs A0– i (where i = A9 for x16, A9 for x8, or A9, A11

for x4) selects the starting column location. The value

on input A10 determines whether or not auto pre-

charge is used. If auto precharge is selected, the row

being accessed will be precharged at the end of the

READ burst; if auto precharge is not selected, the row

will remain open for subsequent accesses.

READ Operation

READ bursts are initiated with a READ command, as

shown in Figure 17. The starting column and bank

addresses are provided with the READ command and

auto precharge is either enabled or disabled for that

burst access. If auto precharge is enabled, the row

being accessed is automatically precharged at the

completion of the burst. If auto precharge is disabled,

the row will be left open after the completion of the

burst.

Figure 17: READ Command

During READ bursts, the valid data-out element

from the starting column address will be available

READ latency (RL) clocks later. READ latency (RL) is

defined as th e sum of Posted CAS additive latenc y (AL)

and CAS Latency (CL); RL = AL + CL. The value for AL

and CL are programmable via the MR and EMR com-

mands, respectively. Each subsequent data-out ele-

ment will be valid nominally at the next positive or

negative clock edge (i.e., at the next crossing of CK and

CK#). Figure18 shows examples of READ latency

based on different AL and CL settings.

DON’T CARE

CK#

CS#

RAS#

CAS#

WE#

CKE

Col

Bank

ADDRESS

BA0, BA1

AUTO PRECHARGE

ENABLE

DISABLE

A10

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Figure 18: READ Latency

NOTE:

1. DO n = data-out from column n.

2. Burst length = 4.

3. Three subsequent elements of data-out appear in the programmed order following DO n.

4. Shown with nominal tAC, tDQSCK, and tDQSQ.

READ NOP NOP NOP NOP NOP

Bank a,

Col n

CK#

COMMAND

ADDRESS

DQS,DQS#

T0 T1 T2 T3 T4n T5nT4 T5

CK#

COMMAND

READ NOP NOP NOP NOP NOP

ADDRESS

Bank a,

Col n

RL = 3 (AL = 0, CL = 3)

DQS, DQS#

T0 T1 T2 T3 T3n T4nT4 T5

CK#

COMMAND

READ NOP NOP NOP NOP NOP

ADDRESS

Bank a,

Col n

RL = 4 (AL = 0, CL = 4)

DQS, DQS#

T0 T1 T2 T3 T3n T4nT4 T5

AL = 1 CL = 3

RL = 4 (AL + CL)

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DQS/DQS# is driven by the DDR2 SDRAM along

with output data. The initial LOW state on DQS and

HIGH state on DQS# is known as the READ preamble

(tRPRE). The LOW state on DQS and HIGH state on

DQS# coincident with the last data-out element is

known as the read postamble (tRPST).

Upon completion of a burst, assuming no other

commands have been initiated, the DQs will go High-

Z. A detailed explanation of tDQSQ (valid data-out

skew), tQH (data-out window hold), the valid data win-

dow are depicted in Figur e 27 on page 40 and Figure 28

on page 41. A detailed explanation of tDQSCK (DQS

transition skew to CK) and tAC (data-out transition

skew to CK) is shown in Figure 29 on page42.

Data from any READ burst may be concatenated

with data from a subsequent READ command to pro-

vide a continuous flow of data. The first data element

from the new burst follows the last element of a com-

pleted burst. The new READ command should be

issued x cycl es af ter the first REA D comman d, where x

equals BL / 2 cycles. This is shown in Figure 19.

Figure 19: Consecutive READ Bursts

NOTE:

1. 1. DO n (or b) = data-out from col umn n (or column b).

2. Burst length = 4.

3. Three subsequent elements of data-out appear in the programmed order following DO n.

4. Three subsequent elements of data-out appear in the programmed order following DO b.

5. Shown with nominal tAC, tDQSCK, and tDQSQ.

6. Example applies only when READ commands are issued to same device.

CK#

COMMAND

READ NOP READ NOP NOP NOP NOP

ADDRESS

Bank,

Col nBank,

Col b

COMMAND

READ NOP READ NOP NOP NOP

ADDRESS

Bank,

Col nBank,

Col b

RL = 3

CK#

COMMAND

ADDRESS

DQS, DQS#

RL = 4

DQS, DQS#

nDO

T0 T1 T2 T3 T3n T4nT4 T5 T6

T5n T6n

T0 T1 T2 T3T2n

NOP

T3n T4nT4 T5 T6

T5n T6n

DON’T CARE TRANSITIONING DATA

tCCD

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Figure 20: Nonconsecutive READ Bursts

NOTE:

1. DO n (or b) = data-out from column n (or column b).

2. Burst length = 4.

3. Three subsequent elements of data-out appear in the programmed order following DO n.

4. Three subsequent elements of data-out appear in the programmed order following DO b.

5. Shown with nominal tAC, tDQSCK, and tDQSQ.

6. Example applies when READ commands are issued to different devices or nonconsecutive READs.

Non consecuti ve read data is i llustrated in Fig ure 20

on page 34. Full-speed random read accesses within a

page (or pages) ca n be pe rf orme d. DDR 2 SDRA M sup-

ports the use of concurrent auto precharge timing,

which is shown in Tabl e 7 on page 35.

DDR2 SDRAM does not allow interrupting or trun-

cating of any READ burst using BL = 4 operations.

Once the BL = 4 READ command is registered, it must

be allowed to complete the entire READ burst. How-

ever, a READ (with AUTO PRECHARGE disabled) using

BL = 8 operation may be interrupted and truncated

ONLY by another READ burst as long as the interrup-

tion occurs on a four-bit boundary due to the 4n

prefetch architecture of DDR2 SDRAM. READ burst BL

= 8 operations may not be interrupted or truncated

with an y c ommand exc ept another READ co mmand as

shown in Figure21 on page 36 .

CK#

COMMAND READ NOP NOP NOP NOP NOP NOP NOP

ADDRESS Bank,

Col n

READ

Bank,

Col b

COMMAND

ADDRESS

CL = 3

CK#

COMMAND

ADDRESS

DQS, DQS#

CL = 4

DQS, DQS#

T0 T1 T2 T3 T3n T4 T5 T7 T8T6T4n T6n T7n

NOP NOP NOP NOP

T5 T7 T8T5n T6T4n T7n

READ NOP NOP NOP

Bank,

Col n

READ

Bank,

Col b

T0 T1 T2 T3 T4

nDO

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Data from any READ burst must be completed

before a subsequent WRITE burst is allowed. An exam-

ple of a READ burst followed by a WRITE burst is

shown in Figure 24. The tDQSS (MIN) case is shown;

the tDQSS (MAX) case has a longer bus idle time.

(tDQSS [MIN] and tDQSS [MAX] are defined in the sec-

tion on WRITEs.)

A READ burst may be followed by a PRECHARGE

command to the same bank provided that AUTO PRE-

CHARGE is not activated. Examples of READ to PRE-

CHARGE are shown in Figure 22 for BL=4 and

Figure 23 for BL=8. The delay from READ command to

PRECHARGE command to the same bank is AL + BL/2

+ tRTP - 2 clocks.

If A10 is HIGH when a READ command is issued,

the READ with AUTO PRECHARGE function is

engaged. The DDR2 SDRAM starts an AUTO PRE-

CHARGE operation on the rising edge which is (AL +

BL/2) cycles later than the READ with AP command if

tRAS (MI N) and tRTP are satisfied. If tRAS (MIN) is not

satisfied at the edge, the start point of AUTO PRE-

CHARGE operation will be delayed until tRAS (MIN) is

satisf ied. If tRTP ( MIN) is not sa tisfie d at the ed ge, t he

start point of the AUTO PRECHARGE operation will be

delayed until tRTP (MIN) is satisfied. In case the inter-

nal precharge is pushed out by tRTP, tRP starts at the

point where th e internal p recharg e h ap pen s (not at the

next ri sing clock edg e a fter this event). S o f or BL = 4 the

minimum ti me fr om READ with AP to the next acti va te

command becomes AL + (tRTP + tRP)* (see Figure 22

on page37); for BL = 8 the time from READ with AP to

the next activate is AL + 2 clocks + (tRTP + tRP)* (see

Figure 23 on page 37), where * means each parameter

term is divi ded b y tCK and r ound ed up to th e next i nte-

ger. I n an y ev ent , inte rna l precharge does not s tart ear-

lier than two cl ocks aft er the last four-bit prefetch .

Table 7: READ Using Concurrent Auto Precharge

BL = burst length.

FROM

COMMAND

(BANK n)TO COMMAND

(BANK m)MINIMUM DELAY (WITH CONCURRENT

AUTO PRECHARGE) UNITS

READ with

Auto

Precharge

READ or READ w/AP (BL/2) tCK

WRITE or WRITE w/AP (BL/2) + 2 tCK

PRECHARGE or ACTIVE 1 tCK

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Figure 21: READ Interrupted by READ

NOTE:

1. Burst length = 8 required, AUTO PRECHARGE must be disabled (A10 = LOW).

2. READ command can be issued to an y valid bank a nd row ad dress (READ co mmand a t T0 and T2 can be eithe r same ban k

or differe nt bank).

3. Interupting READ command must be issued exactly 2 x tCK from previous READ.

4. AUTO PRECHARGE can be either enabled (A10 = HIGH) or disabled (A10 = LOW) by the interupting REA D command.

5. NOP or COMMAND INHIBIT comma nds a re vali d. PRECHARGE command cannot be issued to bank s used for READs at T0

and T2.

6. Earliest READ-to-PRECHARGE (tRTP) timing for READ at T0; tRTP = AL + BL/2 where BL = 8 from the mode register, not

the BL of the truncated burst.

7. Example shown uses additive latency = 0; CAS Latency = 3, BL = 8, shown with nominal tAC, tDQSCK, and tDQSQ.

OUT

CK#

COMMAND

DQS, DQS#

CL = 3 (AL = 0)

READ

T0 T1 T2

DON’T CARETRANSITIONING DATA

NOP

OUT

T3 T4 T5

VALID

VALIDREAD

OUT

VALID VALID VALID

T7 T8 T9

CL = 3 (AL = 0)

CCD

ADDRESS

A10

VALID

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Figure 22: READ to PRECHARGE BL = 4

Figure 23: READ to PRECHARGE BL = 8

Figure 24: READ to WRITE

OUT

CK#

COMMAND

DQS, DQS#

CL = 3

READ

Read Latency = 4 (AL = 1, CL = 3), BL = 4, tRTP ≥ 2 clocks

Shown with nominal tAC, tDQSCK, and tDQSQ

T0 T1 T2

DON’T CARETRANSITIONING DATA

NOP PRECHARGE

OUT

T3 T4 T5 T6

ACTIVE

ADDRESS

A10

AL=1

NOP

Bank a

≥tRTP(MIN)

Bank a

≥tRAS(MIN)

Bank a

≥tRP(MIN)

NOP NOP

AL + BL/2 + tRTP - 2 clocks

NOP

≥tRC(MIN)

4-bit

prefetch

Valid Valid

OUT

CK#

COMMAND

DQS, DQS#

CL = 3

READ

Read Latency = 4 (AL=1, CL=3), BL=8, tRTP ≥ 2 clocks

Shown with nominal tAC, tDQSCK, and tDQSQ

T0 T1 T2

DON’T CARETRANSITIONING DATA

NOP

OUT

T3 T4 T5 T6 T7 T8

ADDRESS

A10

AL=1

NOP

Bank a

≥tRC(MIN)

≥tRTP(MIN)

NOP

OUT

first 4-bit

prefetch second 4-bit

prefetch

≥tRP(MIN)

PRECHARGE

Bank a Bank a

NOP

AL + BL/2 + tRTP - 2 clocks

NOP ACTIVE

≥tRAS(MIN)

Valid Valid

OUT

n + 3

OUT

n + 2

OUT

n + 1

CK#

COMMAND

DQS, DQS#

AL = 2

ACTIVE n

Burst length = 4

Shown with nominal tAC, tDQSCK, and tDQSQ

T0 T1 T2

DON’T CARETRANSITIONING DATA

READ nNOP NOP

OUT

T3 T4 T5

NOP WRITE n

NOP

n + 3

n + 2

n + 1

WL = RL - 1 = 4

T7 T8

NOP NOP NOP

T9 T10 T11

NOP NOP

CL = 3

RL = 5

CAS# read latency (CL) = 3

Posted CAS# additive latency (AL) = 2

tRCD = 3

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Figure 25: Bank Read – Without Auto Precharge

NOTE:

1. DO n = data-out from column n; subsequent elements are applied in the programmed order.

2. Burst length = 4 and AL = 0 in the case shown.

3. Disable auto precharge.

4. “Don’t Care” if A1 0 is HIGH at T5.

5. PRE = PRECHARGE, ACT = ACTIVE, RA = row address, BA = bank address.

6. NOP commands are shown for ease of illustration; ot her commands may be valid at these times.

7. The PRECHARGE command can only be applied at T6 if tRAS minimum is met.

8. Read to Precharge = AL +BL/2 + tRTP-2 clocks.

CK#

CKE

A10

BA0, BA1

RCD

RAS7

CL = 3

T0 T1 T2 T3 T4 T5 T5n T6nT6 T7 T8

DQ1

DQS, DQS#

Case 1: tAC (MIN)

and tDQSCK (MIN)

Case 2: tAC (MAX)

and tDQSCK (MAX)

DQ1

DQS, DQS#

RPRE

RPST

DQSCK (MIN)

DQSCK (MAX)

LZ (MIN)

LZ (MAX)

AC (MIN)

LZ (MIN)

HZ (MAX)

AC (MAX)

LZ (MIN)

NOP6

COMMAND5ACT

RA Col n

PRE

Bank x

Bank xBank x4

ACT

Bank x

NOP6NOP6NOP6NOP6

HZ (MIN)

ONE BANK

ALL BANKS

DON’T CARE

TRANSITIONING DATA

ADDRESS

tRTP

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Figure 26: Bank Read – With Auto Precharge

NOTE:

1. DO n = data-out from column n; subsequent elements are applied in the programmed order.

2. Burst length = 4, RL = 4 (AL = 1, CL = 3) in the case shown.

3. Enable auto precharge.

4. ACT = ACTIVE, RA = row address, BA = bank address.

5. NOP commands are shown for ease of illustration; ot her commands may be valid at these times.

6. The DDR2 SDRAM internally delays auto precharge until both tRAS (MIN) and tRTP (MIN) have been satisfied.

CK#

CKE

A10

BA0, BA1

RCD

RAS

CL = 3

T0 T1 T2 T3 T4 T5 T5n T6nT6 T7 T8

DQS,DQS#

Case 1:

AC (MIN)

and

DQSCK (MIN)

Case 2:

AC (MAX)

and

DQSCK (MAX)

DQS, DQS#

RPRE

RPST

DQSCK (MIN)

DQSCK (MAX)

LZ (MIN)

LZ (MAX)

AC (MIN)

LZ (MIN)

HZ (MAX)

AC (MAX)

LZ (MAX)

NOP5

COMMAND

5ACT

RA Col n

Bank x

ACT

Bank x

NOP5NOP5NOP5NOP5NOP5

HZ (MIN)

DON’T CARE

TRANSITIONING DATA

ADDRESS

AL=1

4-bit

prefetch

tRTP

Internal

precharge

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Figure 27: x4, x8 Data Output Timing – tDQSQ, tQH, and Data Valid Window

NOTE:

1. DQs transitioning after DQS transition define tDQSQ window. DQS transitions at T2 and at T2n are “early DQS,” at T3

are “nominal DQS,” and at T3n are "late DQS."

2. For a x4, only two DQs apply.

3. tDQSQ is derived at e ach DQS clock edge and is not cum ulative over time and begins with DQS transitions and end s with

the last valid transition of DQs .

4. tQH is derived from tHP: tQH = tHP - tQHS.

5. tHP is the lesser of tCL or tCH clock transitions collectively when a bank is active.

6. The data valid window is derived for each DQS transition and is defined as tQH minus tDQSQ.

DQ (Last data valid)

DQ2

DQS#

DQS1

DQ (Last data valid)

DQ (First data no longer valid)

All DQs and DQS, collectively6

Earliest signal transition

Latest signal transition

T2n

T3n

CK#

T1 T2 T3 T4T2n T3n

tQH

tHP

tQH

tHP

tQH

tDQSQ

Data

Valid

window

Data

Valid

window

Data

Valid

window

Data

Valid

window

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Figure 28: x16 Data Output Timing – tDQSQ, tQH, and Data Valid Window

NOTE:

1. DQs transitioning after DQS transitions define the tDQSQ window. LDQS defines the lower byte, and UDQS defines the

upper byte.

2. DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, or DQ7.

3. tDQSQ is derived at e ach DQS clock edge and is not cum ulative over time and begins with DQS transitions and end s with

the last valid transition of DQs.

4. tQH is derived from tHP: tQH = tHP - tQHS.

5. tHP is the lesser of tCL or tCH clock transitions collectively when a bank is active.

6. The data valid window is derived for each DQS transition and is tQH minus tDQSQ.

7. DQ8, DQ9, DQ10, D11, DQ12, DQ13, DQ14, or DQ15.

DQ (Last data valid)2

DQ2

LDSQ#

LDQS1

DQ (Last data valid)2

DQ (First data no longer valid)2

DQ0–DQ7 and LDQS, collectively6

T2n

T3n

CK#

T1 T2 T3 T4T2n T3n

tQH

tDQSQ

Data Valid

window Data Valid

window

DQ (Last data valid)7

DQ7

UDQS#

UDQS1

DQ (Last data valid)7

DQ (First data no longer valid)7

DQ8–DQ15 and UDQS, collectively6

T2n

T3n

tQH

tDQSQ

tHP

tQH

Data Valid

window

Data Valid

window Data Valid

window

Upper Byte

Lower Byte

Data Valid

window

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Figure 29: Data Output Timing – tAC and tDQSCK

NOTE:

1. tDQSCK is the DQS output window relative to CK and is the“long-term” component of DQS skew.

2. DQs transitioning after DQS transitions define tDQSQ window.

3. All DQs must transition by tDQSQ after DQS transitions, regardless of tAC.

4. tAC is the DQ output window relative to CK and is the“long term” component of DQ skew.

5. tLZ (MIN) and tAC (MIN) are the first valid signal transitions.

6. tHZ (MAX) and tAC (MAX) are the latest valid signal transitions.

7. READ command with CL=3, AL=0 issued at T0.

CK#

DQS#/DQS, or

LDQS#/LDQS / UDQ#/UDQS2

T07T1 T2 T3 T3n T4 T4n T5 T5n T6 T6n T7

tRPST

tLZ (MIN)

tDQSCK

(MAX)

tDQSCK

(MIN) tDQSCK

(MAX)

tDQSCK

(MIN)

tHZ (MAX)

tRPRE

DQ (Last data valid)

DQ (First data valid)

All DQs collectively3

tAC

(MIN) tAC

(MAX)

tLZ (MIN) tHZ (MAX)

T3n T4n T5n T6n

T3n

T4n

T5n

T6n

T3 T4 T5 T6

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WRITEs

WRITE Command

The WRITE command is used to initiate a burst

write access to an active row. The value on the BA0,

BA1 inputs selects the bank, and the address provided

on inputs A0–i (where i = A9 for x8 and x16; or A9, A11

for x4) selects the starting column location. The value

on input A10 determines whether or not auto pre-

charge is used. If auto precharge is selected, the row

being accessed will be precharged at the end of the

write burst; if auto precharge is not selected, the row

will remain open for subsequent accesses.

Figure 30: WRITE Command

Input data appearing on the DQs is written to the

memory array subject to the DM input logic level

appear ing coincid ent with the dat a. If a given DM sig-

nal is registered LOW, the corresponding data will be

written to memory; if the DM signal is registered

HIGH, the corresponding data inputs will be ignored,

and a write will not be executed to that byte/column

location (Figure 40) .

WRITE Operation

WRITE bursts are initia ted with a WRITE command ,

as shown in Figure 30. DDR2 SDRAM uses Write

Latency (WL) equal to Read Latency minus 1 clock

cycle ( WL = RL - 1 = AL + CL - 1). The starti ng column

and bank address es are provided with the WRITE c om-

mand, and auto precharge is either enabled or dis-

abled f or that acce ss. If au to precharge is enable d, the

row being accessed is precharged at the completion of

the burst. For the generic WRITE commands used in

the following illustrations, auto precharge is disabled.

During WRITE bursts, the first valid data-in element

will be registered on the fir st ri sin g edg e of DQS f o llow-

ing the WRITE command, and subsequent data ele-

ments will be registered on successive edges of DQS.

The LOW state on DQS between the WRITE command

and the first rising edge is known as the write pream-

ble; the LOW state on DQS following the last data-in

element is known as the write postamble.

The time between the WRITE command and the

first corresponding rising edge of DQS (tDQSS) is spec-

ified with a relatively wide range (from 75 percent to

125 percent of one clock cycle). All of the WRITE dia-

grams show the nominal case, and where the two

extreme cases (i.e., tDQSS [MIN] and tDQSS [MAX])

might not be intuitive, they have also been included.

Figure 31 shows the nominal case and the extremes of

tDQSS for a burst of 4. Upon completion of a burst,

assu ming no o ther commands have been initiated, the

DQs will remain High-Z and any additional input data

will be ignored.

Data for any WRITE burst may be concatenated

with a subsequent WRITE command to provide con-

tinuo us flow of input data. T he new WRITE co mmand

can be issued on any positive edge of CK following the

previous WRITE command. The first data element

from the new burs t is app lied after t he last elem ent of a

complet ed burst. Th e new WRITE comma nd should be

issued x cycles after the first WRITE command, where

x equals BL/ 2.

Figure 32 shows concatenated bursts of 4. An exam-

ple of nonconsecutive WRITEs is shown in Figure 33.

Full-speed random write accesses within a page or

pages can be performed as shown in Figure 34. DDR2

SDRAM supports concurrent auto precharge options

shown in Table 8.

DDR2 SDRAM does not allow interrupting or trun-

cating any WRITE burst using BL = 4 operation. Once

the BL = 4 WRITE command is registered, it must be

allowed to complete the entire WRITE burst cycle.

CS#

WE#

CAS#

RAS#

CKE

A10

BA0, BA1

HIGH

EN AP

DIS AP

CK#

CA = column address

BA = bank address

EN AP = enable auto precharge

DIS AP = disable auto precharge

DON’T CARE

ADDRESS

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Howe ver, a WR ITE ( with AUTO PRECH ARGE disabled )

using BL = 8 operations may be interr upted and trun-

cated ONLY by another WRITE burst as long as the

interr uption occurs on a four-bit boundar y due to the

4n prefetch architecture of DDR2 SDRAM. WRITE

burst BL = 8 operations may NOT be interrupted or

truncated with any command except another WRITE

command as shown in Figure35.

Data for any WRITE bu rst may be fol l owed by a sub-

sequent READ command. To follow a WRITE tWTR

should be met as shown in Figure 36. Data for any

WRITE burst may be followed by a subsequent PRE-

CHARGE command. tWR must be met as shown in

Figure 30.

Figu re 31: WRI TE Burst

NOTE:

1. DI b = data-in for column b.

2. Three subsequent elements of data-in are applied in the programmed order following DI b.

3. A burst of 4 is shown with AL = 0, CL = 3; thus, WL = 2.

4. A10 is LOW with the WRITE command (auto precharge is disabled).

Table 8: WRITE Using Concurrent Auto Precharge

CL = CAS latency, BL = burst length

FROM

COMMAND

(BANK n)TO COMMAND

(BANK m)MINIMUM DELAY (WITH CONCURRENT

AUTO PRECHARGE) UNITS

WRITE with

Auto

Precharge

READ or READ w/AP (CL-1) + (BL/2) + tWTR tCK

WRITE or WRITE w/AP (BL/2) tCK

PRECHARGE or ACTIVE 1 tCK

DQS, DQS#

tDQSS (MAX)

tDQSS (NOM)

tDQSS (MIN)

tDQSS

CK#

COMMAND

WRITE NOP NOP

ADDRESS

Bank a,

Col b

NOP NOP

T0 T1 T2 T3T2n T4T3n

DQS, DQS#

tDQSS

DQS, DQS#

tDQSS

DON’T CARE TRANSITIONING DATA

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Figure 32: Consecutive WRITE to WRITE

NOTE:

1. DI b, etc. = data-in for column b, etc.

2. Three subsequent elements of data-in are applied in the programmed order following DI b.

3. Three subsequent elements of data-in are applied in the programmed order following DI n.

4. A burst of 4 is shown with AL = 0, CL = 3; thus, WL = 2.

5. Each WRITE command may be to any bank.

Figure 33: Nonconsecutive WRITE to WRITE

NOTE:

1. DI b, etc. = data-in for column b, etc.

2. Three subsequent elements of data-in are applied in the programmed order following DI b.

3. Three subsequent elements of data-in are applied in the programmed order following DI n.

4. A burst of 4 is shown. AL = 0, CL = 3; thus, WL = 2.

5. Each WRITE command may be to any bank.

CK#

COMMAND

WRITE NOP WRITE NOP NOP NOP

ADDRESS

Bank,

Col b

NOP

Bank,

Col n

T0 T1 T2 T3T2n T4 T5T4n T6T5nT3nT1n

DQS, DQS#

DON’T CARE TRANSITIONING DATA

tDQSS

tDQSS (NOM)

WL = 2

tCCD

WL = 2

CK#

COMMAND

WRITE NOP NOP NOP NOP NOP

ADDRESS

Bank,

Col b

WRITE

Bank,

Col n

T0 T1 T2 T3T2n T4 T5T4nT3n T5n T6 T6n

DQS, DQS#

tDQSS (NOM) tDQSS

DON’T CARE TRANSITIONING DATA

WL = 2 WL = 2

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Figure 34: Ran dom W RITE Cycles

NOTE:

1. DI b, etc. = data-in for column b, etc.

2. Three subsequent elements of data-in are applied in the programmed order following DI b.

3. Three subsequent elements of data-in are applied in the programmed order following DI n.

4. An burst of 4 is shown. AL = 0, CL = 3; thus, WL = 2.

5. Each WRITE command may be to any bank.

Figure 35: WRITE Interrupted by WRIT E

NOTE:

1. Burst length = 8 required, AUTO PRECHARGE must be disabled (A10 = LOW).

2. WRITE command can be issued to any valid bank and row address (WRITE command at T0 and T2 can be either same

bank or different bank).

3. Interupting WRITE command must be issued exactly 2 x tCK from previous WRITE.

4. AUTO PRECHARGE can be either enabled (A10 = HIGH) or disabled (A10 = LOW) by the interupting WRITE command.

5. NOP or COMMAND INHIBIT commands are valid. PRECHARGE command can not be issued to banks used for WRITEs at

T0 and T2.

6. Earliest WRITE-to-PRECHARGE timing for WRITE at T0 is WL + BL/2 + tWR where tWR starts with T7 and not T5 (since BL

= 8 from MR and not the truncated length).

7. Example shown uses Additive Latency = 0; CAS Latency = 4, BL = 8.

CK#

COMMAND

WRITE NOP WRITE NOP NOP NOP

ADDRESS

Bank,

Col b

NOP

Bank,

Col n

T0 T1 T2 T3T2n T4 T5T4n T6T5nT3nT1n

DQS, DQS#

DON’T CARE TRANSITIONING DATA

tDQSS

tDQSS (NOM)

WL = 2

tCCD

WL = 2

DIN

a + 3

DIN

a + 2

DIN

a + 1

CK#

COMMAND

DQS, DQS#

WL = 3

WRITE

T0 T1 T2

DON’T CARETRANSITIONING DATA

DIN

T3 T4 T5 T6

WRITE

DIN

b + 3

DIN

b + 2

DIN

b + 1

DIN

bDIN

b + 7

DIN

b + 6

DIN

b + 5

DIN

b + 4

T7 T8 T9

WL = 32 clock requirement

ADDRESS

A10

VALID

NOP

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Figure 36: WRITE to READ

NOTE:

1. DI b = data-in for column b; Dout n = data out from column n.

2. A burst of 4 is shown; AL = 0, CL = 3; thus, WL = 2.

3. One subsequent element of data-in is applied in the programmed order following DI b.

4. tWTR is referenced from the first positive CK edge after the last data-in pair.

5. A10 is LOW with the WRITE command (auto precharge is disabled).

tDQSS (NOM)

CK#

COMMAND

WRITE NOP NOP NOP NOP NOP NOP NOP

ADDRESS

Bank a,

Col bBank a,

Col n

READ

T0 T1 T2 T3T2n T4 T5 T9nT3n T6 T7 T8 T9

tWTR

CL = 3

DQS, DQS#

bDI

tDQSS (MIN)

DQS, DQS#

tDQSS (MAX)

DQS, DQS#

bDout

DON’T CARE TRANSITIONING DATA

tDQSS

NOP

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Figure 37: WRITE to PRECHARGE

NOTE:

1. DI b = data-in for column b.

2. Three subsequent elements of data-in are applied in the programmed order following DI b.

3. A burst of 4 is shown. CL = 3; AL = 0; thus, WL = 2.

4. tWR is referenced from the first positive CK edge after the last data-in pair.

5. The PRECHARGE and WRITE commands are to the same bank. However, the PRECHARGE and WRITE commands may be

to different banks, in which case tWR is not required and the PRECHARGE command could be applied earlier.

6. A10 is LOW with the WRITE command (auto precharge is disabled).

7. PRE = PRECHARGE command.

tDQSS (NOM)

CK#

COMMAND

WRITE NOP NOP NOP NOPNOP

ADDRESS

Bank a,

Col bBank,

(a or all)

NOP

T0 T1 T2 T3T2n T4 T5T3n T6 T7

tWR tRP

DQS#

DQS

tDQSS (MIN)

DQS#

DQS

tDQSS (MAX)

DQS#

DQS

DON’T CARE TRANSITIONING DATA

tDQSS

PRE7

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Figure 38: Bank Write–Without Auto Precharge

NOTE:

1. DI n = data-in from column n; subsequent elements are applied in the programmed order.

2. Burst length = 4, AL = 0, and WL = 2 in the case shown.

3. Disable auto precharge.

4. “Don’t Care” if A1 0 is HIGH at T8.

5. PRE = PRECHARGE, ACT = ACTIVE, RA = row address, BA = bank address.

6. NOP commands are shown for ease of illustration; ot her commands may be valid at these times.

7. tDSH is applicable during tDQSS (MIN) and is referenced from CK T5 or T6.

8. tDSS is applicable during tDQSS (MAX) and is referenced from CK T6 or T7.

CK#

CKE

A10

BA0, BA1

RCD

RAS

T0 T1 T2 T3 T5 T6 T6n T7 T8 T9T5n

NOP6

COMMAND

ACT

RA Col n

WRITE2NOP6

ONE BANK

ALL BANKS

Bank x

PRE

Bank x

NOP6NOP6NOP6

DQSL

DQSH

WPST

Bank x4

DON’T CARE

TRANSITIONING DATA

DQSS (NOM)

WPRE

WPRES

DQS, DQS#

ADDRESS

NOP6

WL=2

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Figure 39: Bank Write–with Auto Precharge

NOTE:

1. DI n = data-in from column n; subsequent elements are applied in the programmed order.

2. Burst length = 4, AL = 0, and WL = 2 shown.

3. Enable auto precharge.

4. ACT = ACTIVE, RA = row address, BA = bank address.

5. NOP commands are shown for ease of illustration; ot her commands may be valid at these times.

6. tDSH is applicable during tDQSS (MIN) and is referenced from CK T5 or T6.

7. tDSS is applicable during tDQSS (MAX) and is referenced from CK T6 or T7.

8. WR is programmed via MR[11,10,9] and is calculated by dividing tWR(ns) by tCK and rounding up to the next integer

value.

CK#

CKE

A10

BA0, BA1

tCK tCH tCL

tRCD

tRAS tRP

T0 T1 T2 T3 T4 T5 T5n T6 T7 T8T6n

NOP5

COMMAND

ACT

RA Col n

WRITE2NOP5

Bank x

NOP5

Bank x

NOP5NOP5NOP5

tDQSL tDQSH tWPST

tDQSS (NOM)

DON’T CARE

TRANSITIONING DATA

WPRES

WPRE

DQS,DQS#

ADDRESS

NOP5

WL = 2

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Figure 40: WRITE–DM Operation

NOTE:

1. DI n = data-in from column n; subsequent elements are applied in the programmed order.

2. Burst length = 4, AL = 1, and WL = 2 in the case shown.

3. Disable auto precharge.

4. “Don’t Care” if A1 0 is HIGH at T8.

5. PRE = PRECHARGE, ACT = ACTIVE, RA = row address, BA = bank address.

6. NOP commands are shown for ease of illustration; ot her commands may be valid at these times.

7. tDSH is applicable during tDQSS (MIN) and is referenced from CK T6 or T7.

8. tDSS is applicable during tDQSS (MAX) and is referenced from CK T7 or T8.

CK#

CKE

A10

BA0, BA1

RCD

RAS tRP

tWR

T0 T1 T2 T3 T4 T5 T7nT6 T7 T8T6n

NOP6

COMMAND5

ACT

RA Col n

WRITE2NOP6

ONE BANK

ALL BANKS

Bank xBank x

NOP6NOP6NOP6NOP6NOP6NOP6

DQSL

DQSH

WPST

Bank x4

DQ1

DON’T CARE

TRANSITIONING DATA

DQSS (NOM)

WPRES

WPRE

PRE

DQS, DQS#

ADDRESS

T9 T10 T11

AL=1 WL=2

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Figure 41: Data Input Timing

NOTE:

1. tDSH (MIN) generally occurs during tDQSS (MIN).

2. tDSS (MIN) generally occurs during tDQSS (MAX).

3. WRITE command issued at T0.

4. For x16, LDQS controls the lower byte and UDQS controls the upper byte.

5. WRITE command with WL=2 (CL=3, AL=0) issued at T0.

DQS#

DQS

tDQSS(nominal)

tDQSH tWPST

tDQSL

tDSS2tDSH1

tDSH1tDSS2

CK# T1T0 T1n T2 T2n T3 T4T3n

DON’T CARE

TRANSITIONING DATA

WPRE

WPRES

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Precharge

PRECHARGE Command

The PRECHARGE command, illustrated in

Figure42, is used to deactivate the open row in a par-

ticular bank or the open row in all banks. The bank(s)

will be available for a subsequent row activation a

specified time (tRP) after the precharge command is

issued, except in the case of concurrent auto pre-

charge, where a READ or WRITE command to a differ-

ent ba nk is allowed as long as it does not interru pt the

data transfer in the current bank and does not violate

any other timing parameters. Once a bank has been

precharged, it is in th e idle stat e and must be ac ti vated

prior to any READ or WRITE commands being issued

to that bank. A PRE CHARGE command will be treated

as a NOP if there is no open row in that bank (idle

state) or if the previously open row is already in the

process of precharging.

PRECHARGE Operation

Input A10 determines whether one or all banks are

to be precharged, and in the case where only one bank

is to be precharged, inputs BA0, BA1 select the bank.

Otherwise BA0, BA1 are treated as “Don’t Care.”

When all banks are to be precharged, inputs BA0,

BA1 are treated as “Don’t Care.” Once a bank has been

precharged, it is in th e idle stat e and must be ac ti vated

prior to any READ or WRITE commands being issued

to that ba nk.

Figure 42: PRECHARGE Command

CS#

WE#

CAS#

RAS#

CKE

A10

BA0, BA1

HIGH

ALL BANKS

ONE BANK

ADDRESS

CK#

BA = bank address (if A10 is LOW;

otherwise “Don’t Care”)

DON’T CARE

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Self Refresh

SELF REFRESH Command

The SELF REFRESH command can be used to reta in

data in the DDR2 SDRAM, eve n if the res t of the system

is powered down. When in the self refresh mode, the

DDR2 SDRAM retains data without external clocking.

All power supply inputs (including VREF) must be

maintain ed at valid levels upon e ntry/ exit AND dur in g

self refr es h operation.

The SELF REFRESH command is initiated like a

REFRESH command except CKE i s (LOW). T he DLL is

automatically disabled upon entering self refresh and

is automatical ly enabled upon ex iting self refresh (200

clock cycles must then occur before a READ command

can be issu ed). Clock should remain stable and meet-

ing tCKE specifications at least 1 x tCK after entering

self refresh mode. All command and address input sig-

nals except CKE are “Don’t Care” during self refresh.

The procedure for exiting self refresh requires a

sequence of commands. First, CK,CK# must be stable

and m eeting tCK spe cificat ions at lea st 1 x tCK prior to

CKE going back HIGH. Once CKE is HIGH, the DDR2

SDRAM must have NOP or DESELECT commands

issued for tXSNR because time is required for the com-

pletion of any internal refresh in progress. A simple

algorithm for meeting both refresh and DLL require-

ments is to apply NOP or DESELECT commands for

200 clock cycles before applying any other command.

Figure 43: Self Refresh

NOTE:

1. Clock must be stable and meeting tCK s pecifications at least 1 x tCK after entering self refresh and at least 1 x tCK prior

to exiting self refresh mode.

2. Device must be in the all banks idle state prior to entering self refresh mode.

3. tXSNR is required before any non-READ command can be applied.

4. tXSRD (200 cycles of CK) is required before a READ command can be applied at state Td0.

5. REF = REFRESH command.

6. Self Refresh exit is asynchronous, however, tXSNR and tXSRD timing starts at the first rising clock edge where CKE HIGH

satisfies tISXR.

7. NOP or DESELECT commands are required prior to exiting SELF REFRESH until state Tc0, which allows any non-READ

command.

8. ODT must be disabled and Rtt off (tAOFD and tAOFPD have been satisfied) prior to entering Self Refresh at state T1.

9. Once Self Refresh has been entered tCKE(min) must be satisfied prior to exiting self refresh.

CK#

COMMAND

5NOP REF

ADDRESS

CKE

VALID

DQS#,

DQS

NOP7

tRP

tCH tCL tCK

tXSNR

3,6

tISXR

Enter Self Refresh

Mode (synchronous) Exit Self Refresh

Mode (asynchronous)

T0 T1 Ta2Ta1

DON’T CARE

Ta0 Tc0Tb0

tXSRD

4,6

VALID3

tCKE (MIN)

NOP7

tCKE (MIN)

tCK

ODT

tAOFD / tAOFPD

Td0

VALID4

VALID3

Indicates a break in

time scale

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REFRESH

REFRESH Command

REFRESH is used during normal operation of the

DDR2 SDRAM and is analogous to CAS#-BEFORE-

RAS# (CBR) refresh. This command is nonpersistent,

so it must be issued each time a refresh is required.

The addressing is generated by the internal refresh

controller. This makes the address bits a “Don’t Care”

during an REFRESH command. The 512Mb DDR2

SDRAM requires REFRESH cycles at an average inter-

val of 7.8125µs (maximum). To allow for improved effi-

ciency in scheduling and switching between tasks,

some flexibility in the absolute refresh interval is pro-

vided. A maximum of eight REFRESH commands can

be posted to any given DDR2 SDRAM, meaning that

the maximum absolute interval between any

REFRES H c o mman d a nd the next REF RE SH co mman d

is 9 × 7.8125µs (7 0.3µs ). This maxi mum absolut e int er-

val is to allow future support for DLL updates internal

to the DDR2 SDRAM to be restricted to REFRESH

cycles, with out allowing excess ive dr ift in tAC b e t we e n

updates. The REFRESH period begins when the

REFRESH command is registered and ends tRFC later.

Figure 44: Refresh Mode

NOTE:

1. PRE = PRECHARGE, ACT = ACTIVE, AR = REFRESH, RA = row address, BA = bank address.

2. NOP commands are shown for ease of illustration; other valid commands may be possible at these times. CKE must be

active during clock positive transitions.

3. “Don’t Care” if A10 is HIGH at this point; A10 must be HIGH if more than one bank is active (i.e., must precharge all

active banks).

4. DM, DQ, and DQS signals are all “Don’t Care”/High-Z for operations shown.

5. The second REFRESH is not required and is only shown as an example of two back-to-back REFRESH commands.

CK#

COMMAND1NOP2

NOP 2NOP2

PRE

CKE

ADDRESS

A101

BA0, BA11Bank(s)3BA

REF NOP2REF5NOP2ACTNOP2

ONE BANK

ALL BANKS

tCK tCH tCL

DQ4

DM4

DQS, DQS#4

tRFC

tRP tRFC(MIN)

T0 T1 T2 T3 T4 Ta0 Tb0

Ta1 Tb1 Tb2

DON’T CARE

Indicates a break in

time scale

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Power-Down Mode

DDR2 SDRAMs support multiple power-down

modes that al low a signif icant p owe r savings over nor-

mal operating modes. The CKE input pin is used to

enter and exit different power-down modes. Power-

down entry and exit timings are shown in Figure 45.

Detailed power-down entry conditions are shown in

Figur e 46 through Figure 53. The Truth Table for CKE is

shown in Table 9 on page 58 for DDR2 SDRAM.

DDR2 SDRAMs require CKE to be active at all times

an acce ss is in prog ress: from th e iss uing of a REA D or

WRITE command until completion of the burst. Thus

a clock suspend is not supported. For READs, a burst

comp letio n is def ined when the read posta mbl e is sa t-

isfied; for WRITEs, a burst completion is defined when

the write postamble is satisfied.

Power-down in Figure 45, is entered when CKE is

registered LOW coincident with a NOP or DESELECT

command. If power-down occurs when all banks are

idle, this mode is referred to as precharge power -do wn.

If power-down occurs when there is a row active in any

bank, this mode is referred to as active power-down.

Entering power-down deactivates the input and out-

put buffers, excluding CK, CK#, ODT, and CKE. For

maximu m po w er sa ving s, t he DLL is fro z en d uring pre-

charge power-down. Exiting active power-down

requires the device to be at the same voltage and fre-

quency as when it entered power-down. Exiting pre-

charge power-down requires the device to be at the

same voltage as when it entered power-down; how-

ever, the clock frequency is allowed to change (See

"Pre cha rge Powe r-Down Clock Frequency Cha nge " on

page 63.)

The maximum duration for either active or pre-

charge power-down is limited by the refresh require-

ments of the device tRFC (MAX). The minimum

duration for power-down entry and exit is limited by

tCKE(min) parameter. While in power-down mode,

CKE LOW, a stable clock signal, and stable power sup-

ply signals must be maintained at the inputs of the

DDR2 SDRAM, while all other input signals are “Don’t

Care” except ODT. Detailed ODT timing diagrams for

different power-down modes are shown starting on

page 66 for Figure 56 through Figure 61.

The power-down state is synchronously exited

when CKE is registered HIGH (in conjunction with a

NOP or DESELECT command) as shown in Figure 45.

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Figure 45: Power-Down

NOTE:

1. If this command is a PRECHARGE (or if the device is already in the idle state), then the power-down mode shown is pre-

charge po wer-down. If this com ma nd is an ACTIVE (or if at le ast one row i s alrea dy a ctive), then the pow er -d ow n mod e

shown is active power-down.

2. No column accesses are allowed to be in progress at the time power-down is entered.

3. tCKE (MIN) = 3 x tCK.

4. tXP timing is used for exit precharge power-down and active power-down to any non-READ command.

5. tXPRD timing is used for exit precharge power-down to any READ command

6. tXARD timing is used for exit active power-down to READ command if 'fast exit' is selected via MR (bit 12 = 0).

7. tXARDS timing is used for exit active power-down to READ command if 'slow exit' is selected via MR (bit 12 = 1).

CK#

COMMAND

VALID1NOP

ADDRESS

CKE

DQS, DQS#

VALID

Enter

Power-Down

Mode2

Exit

Power-Down

Mode

T0 Ta0 Ta2 Tb0 Tb1Ta1

NOP

DON’T CARE

VALIDVALID

CKE (MIN)

Tc0 Td0

VALID

VALID1

VALID

CKE (MIN)

Td1

XPRD

XARD

XARDS

Indicates a break in

time scale

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NOTE:

1. CKE (n) is the logic state of CKE at clock edge n; CKE (n-1) was the state of CKE at the previous clock edge.

2. Current state is the state of the DDR2 SDRAM immediately prior to clock edge n.

3. COMMAND (n) is the command registered at clock edge n, and ACTION (n) is a result of COMMAND (N).

4. All states and sequences not shown are illegal or reserved unless explicitely described elsewhere in this document.

5. On self refresh exit, DESELECT or NOP commands must be issued on every clock edge occurring during the tXSNR p eriod.

Read commands may be issued only after tXSRD (200 clocks) is satisfied.

6. Self refresh mode can only be entered from the all banks idle state.

7. Must be a legal command as defined in the Command Truth Table.

8. Valid commands for power-down entry and exit are NOP and DESELECT only.

9. Valid commands for Self Refresh Exit are NOP and DESELECT only.

10. Power -do wn and self refresh can not be entered while READ or WRITE operations, LOAD MODE operations, or PRE-

CHARGE or REFRESH operations are in progress. See Power-Down and Self Refresh sections for a list of detailed restric-

tions.

11. Minimum CKE HIGH time is tCKE = 3 x tCK. Minimum CKE low time is tCKE = 3 x tCK.

12. The state of on-die termination (ODT) does not affect the stat es described in this table. The ODT function is not avail-

able during self refresh. See ODT section for more details and specific restrictions.

13. Power-down modes do not perform any refresh operations. The duration of power-down mode is therefore limited by

the refresh requirements.

14. CKE must be maintained HIGH while the SDRAM is in off-chip driver (OCD) calibration mode, i.e., if any of the bits A7,

A8, A9 in EMR(1) are set to “1.”

15. “X” means “ Don’t Care” ( includi ng floating around V REF) in self re fresh a nd power -d own. Howev er, ODT must be driv en

HIGH or LOW in power-down if the ODT function is enabled via EMR(1).

Table 9: CKE Truth Table

Notes 1–3, 12, 14

CURRENT STATE

CKE

COMMAND (n)

CS#,RAS#,CAS#,WE# ACTION (n)NOTES

CYCLE (n-1) CURRENT

CYCLE (n)

Power Down L L X Maintain Power-Down 13, 15

L H DESELECT or NOP Power-Down Exit 4, 8

Self Refresh L L X Maintain Self Refresh 15

L H DESELE CT or NOP Self Refresh Exit 4, 5, 9

Bank(s) Active H L DESELECT or NOP Active Power-Down Entry 4, 8, 10, 11

All Banks Idle H L DESELECT or NOP Precharge Power-Down Entry 4, 8, 10

H L REFR ESH Self Refresh Entry 6, 9, 11

H H Refer to Command Truth Table on page 24 7

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Figure 46: READ to Power-Down Entry

NOTE:

1. Power-down entry may occur after the READ burst completes.

2. In the example shown, READ burst completes at T5; earliest power-down entry is at T6.

Figure 47: READ with Auto Precharge to Power-Down Entry

NOTE:

1. Power -do wn ent ry may occ ur 1 x tCK after the internal precharge is issued and may be prior to tRP being satisfied.

2. Timing shown above assumes internal PRECHARGE was issued at T5 or earlier.

3. Refer to READ-to-PRECHARGE section for internal precharge timing details.

OUT

CK#

COMMAND

DQS, DQS#

RL = 3

T0 T1 T2

DON’T CARETRANSITIONING DATA

NOP NOP

OUT

T3 T4 T5

VALID

T6 T7 T8 T9

tCKE (MIN)

ADDRESS

A10

NOP

CKE

READ

VALID

T10

Power-Down

Entry

NOP

OUT

CK#

COMMAND

DQS, DQS#

RL = 3

T0 T1 T2

DON’T CARETRANSITIONING DATA

NOP NOP

OUT

T3 T4 T5

VALID VALID

T6 T7 T8 T9

tCKE (MIN)

ADDRESS

A10

NOP

CKE

READ

VALID

T10

Power-Down

Entry

NOP

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Figure 48: WRITE to Power-Down Entry

Figure 49: WRITE with Au to Precharge to Power-Down Entry

NOTE:

1. Write Recovery (WR) is programmed through MR[9,10,11] and represents [tWR (MIN) ns / tCK] rounded up to next inte-

ger tCK.

2. Internal PRECHARGE occurs at Ta0 when WR has completed; power-down entry may occur 1 x tCK later at Ta1 prior to

tRP being satisfied. Figure 50: REFRESH command to Power-Down Entry

NOTE:

1. The earliest PRECHARGE power-down entry may occur is at T2 which is 1 x tCK after the REFRESH command. Precharge

power down entry occurs prior to tRFC (MIN) being satisfied.

OUT

CK#

COMMAND

DQS, DQS#

WL = 3

T0 T1 T2

DON’T CARETRANSITIONING DATA

NOP NOP

OUT

T3 T4 T5

VALID VALID

VALID

T7 T8 T9

tCKE (MIN)

ADDRESS

A10

NOP

CKE

WRITE

VALID

T10

Power-Down

Entry

tWTR

NOP

OUT

CK#

COMMAND

DQS, DQS#

WL = 3

T0 T1 T2

DON’T CARETRANSITIONING DATA

NOP NOP

OUT

T3 T4 T5

VALID VALID

Ta0

VALID

NOP

Ta1 Ta2 Ta3

tCKE (MIN)

ADDRESS

A10

NOP

CKE

WRITE

VALID

Ta4

Power-Down

Entry

WR1

Indicates a break in

time scale

CK#

COMMAND

DON’T CARE

T0 T1

VALID REFRESH

T2 T3 T4 T5

tCKE (MIN)

CKE

Power-Down

Entry

1 x tCK

NOP

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Figure 51: ACTIVE Command to Power-Down Entry

NOTE:

1. The earliest PRECHARGE power-down entry may occur is at T2, which is 1 x tCK after the ACTIVE command. Active

power-down entry occurs prior to tRCD (MIN) being satisfied.

Figure 52: PRECHARGE Command to Power-Down Entry

NOTE:

1. The earliest power-down entry may occur is at T2, which is 1 x tCK after the PRECHARGE command. Power-down entry

occurs prior to tRP (MIN) being satisfied.

CK#

COMMAND

DON’T CARE

T0 T1

VALID ACTIVE

NOP

T3 T4 T5

tCKE (MIN)

CKE

Power-Down

Entry

1 tCK

ADDRESS VALID

CK#

COMMAND

DON’T CARE

T0 T1

VALID

PRECHARGE

NOP

T3 T4 T5

tCKE (MIN)

CKE

Power-Down

Entry

1 x tCK

ADDRESS

A10

VALID

ALL BANKS

SINGLE BANK

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Figure 53: LO AD MODE C omm a nd to Power-Down Entry

NOTE:

1. The earliest PRECHARGE power-down entry is at T3, which is after tMRD is satisfied.

2. All banks must be in the precharged state and tRP met prior to issuing LM command.

3. Valid address for LM command includes MR, EMR, EMR(2), and EMR(3) registers.

CK#

COMMAND

DON’T CARE

T0 T1

VALID LM

NOP VALID

T3 T4 T5

tCKE (MIN)

CKE

Power-Down

Entry

tMRD

ADDRESS VALID

tRP

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Precharge Power-Down Clock

Frequency Change

When the DRAM is in precharged power-down

mode, on-die termination (ODT) must be turned off

and CKE must be at a logic LOW level. A minimum of

two clocks must pass after CKE goes LOW before clock

frequency may change. The DRAM input clock fre-

quency is allowed to change onl y withi n minimum a nd

maximum operating frequencies specified for the par-

ticular speed grade. During input clock frequency

change, ODT and CKE must be held at stable LOW lev-

els. Once the input clock frequency is changed, new

stable clocks must be provided to the DRAM before

precharge power-down may be exited and DLL must

be RESET via EMR after precharge power-down exit.

Depending on the new clock frequency an additional

MR command may need to be issued to appropriately

set the WR MR[11, 10, 9] register. During the DLL

relock period of 200 cycles, OD T mu st remain off. After

the DLL lock time, the DRAM is r eady to operate with a

new clock frequency.

Figure 54: Input Clock Frequency Chang e During PRECHARGE Power Down Mode

NOTE:

1. If this command is a PRECHARGE (or if the device is already in the idle state), then the power-down mode shown is pre-

charge power-down, which is required prior to the clock frequency change.

2. A minimum of 2 x tCK is required after entering PRECHARGE power-down prior to changing clock frequencies.

3. Once the new clock frequency has changed and is stable, a minimum of 1 x tCK is required prior to exiting PRECHARGE

power-down.

4. CKE minimum HIGH and LOW time; tCKE (MIN) = 3 x tCK.

CK#

COMMAND

VALID1NOP

ADDR

CKE

DQS, DQS#

NOP

tCK

Enter PRECHARGE

Power-Down Mode Exit PRECHARGE

Power-Down Mode

T0 T1 T3 Ta0T2

DON’T CARE

VALID

tCKE (MIN)

tXP

DLL RESET

VALID

NOP

tCH tCL

Ta1 Ta2 Tb0Ta3

2 x tCK (MIN)

1 x tCK (MIN)

tCH tCL

tCK

ODT

200 x tCK

NOP

Ta4

PREVIOUS CLOCK FREQUENCY NEW CLOCK FREQUENCY

Frequency

Change

High-Z

Indicates a break in

time scale

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RESET Function (CKE LOW Anytime)

DDR2 SDRAM applications may go into a RESET

state at any time during normal operation. If an appli-

cation enters a reset condition, the CKE input pin is

used to ensu re the DDR2 SDRAM device resumes nor-

mal operation after reinitializing. All data will be lost

during a reset condition; however, the DDR2 SDRAM

device will continue to operate properly if the follow-

ing condi tions outl ine d in this section are satisfied .

The RESET condition defined here assumes all sup-

ply voltages (VDD, VDDQ, VDDL, and Vref) are stable

and meet all DC specifications prior to, during, and

after the RESET operation. All other input pins of the

DDR2 SDRAM device are a “don’t care” during RESET

with the exception of CKE.

If CKE asynchronously drops LOW during any valid

operation (including a READ or WRITE burst), the

memory controller must satisfy the timing parameter

tDELAY before turning off the clocks . Stable clocks must

exist at the CK,CK# inputs of DRAM before CKE is

raised HIGH, at which time the normal initialization

sequence must occur (See “Initialization” on page15).

The DDR2 SDRAM is now ready for normal operation

after the initialization sequence. Figure 55 shows the

proper sequence for a RESET condition.

Figure 55: RESET Condition

CKE

Rtt

BA0, BA1

High-Z

DQS

High-Z

ADDRESS

A10

CK#

tCL

COMMAND6

NOP

PRE

ALL BANKS

Ta0

DON’T CARE TRANSITIONING DATA

tRP

tCL

tCK

ODT

High-Z

T = 400ns (MIN)

Tb0

READ NOP

T0 T1 T2

Col n

Bank a

tDELAY

DOUTDOUT

()()

READ NOP

Col n

Bank b

DOUT

High-Z

Unknown RTT ON

System

RESET

T3 T4 T5

Start of Normal

Initialization

Sequence

NOP

Indicates a break in

time scale

For Initilization timing, see time sequence Ta0 in

Figure 7, DDR2 Power-Up and Initialization, on

page 16

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ODT Timing

There are two timing categories for ODT, turn-on

and turn-off. During active mode (CKE HIGH) and

“fast-exit” power-down mode (any row of any bank

open, CKE LOW, MR[bit1 2 = 0]), tAOND, tAON, tAOFD,

and tAOF timing parameters are applied as shown in

Figure 56 and Table 10 on page 66. During “slow-exit”

power-down mode (any row of any bank open, CKE

LOW, MR[bit12=1]) and precharge power-down mode

(all banks/rows precharged and idle, CKE LOW),

tAONPD and tAOFPD ti mi n g parameters are applied as

shown in Figure 57 an d Table 11 on page 67.

ODT turn-off timing prior to entering any power-

down mode is determined by the parameter tANPD

(MIN) shown in Figure 58. At state T2 the ODT HIGH

signal satisfies tANPD (MIN) prior to entering power-

down mode at T5. When tANPD (MIN) is satisfied

tAOFD and tAOF timing parameters apply. Figure 58

also shows the example where tANPD (MIN) is NOT

satisfied since ODT HIGH does not occur until state

T3. Whe n tANPD (MIN) is NOT satisfied, tAO F PD t im -

ing parameters apply.

ODT turn-on timing prior to entering any power-

down mode is determined by the parameter tANPD

shown in Figure 59. At state T2, the ODT HIGH signal

satisfies tANPD (MIN) prior to entering power-down

mode at T5. When tANPD (MIN) is satisfied tAOND

and tAON timing parameters apply. Figure 59 also

shows the example where tANPD (MIN) is NOT satis-

fied since ODT HIGH does not occur until state T3.

When tANPD (MIN) is NOT satisfied, tAONPD timing

parameters apply.

ODT turn-off timing after exiting any power-down

mode is determined by the parameter tAXPD (MIN)

shown in Figure 60. At state Ta1, the ODT LOW signal

satisfies tAXPD (MIN) after exiting power-down mode

at state T1. When tAXPD (MIN) is sa tisfied, tAO F D a nd

tAOF timing parameters apply. Figure60 also shows

the example where tAXPD (MIN) is NOT satis fied sin ce

ODT LOW occurs at state Ta0. When tAXPD (MIN) is

NO T satis fied, tA OF PD timi n g parameters appl y.

ODT turn-on timing after exiting any power-down

mode is determined by the parameter tAXPD (MIN)

shown in Figure 61. At state Ta1, the ODT HIG H sig nal

satisfies tAXPD (MIN) after exiting power-down mode

at state T1. When tAXPD (MIN) is satisfied, tAOND and

tAON timing parameters apply. Figure61 also shows

the example where tAXPD (MIN) is NOT sat isfied sin ce

ODT HIGH occurs at state Ta0. When tAXPD (MIN) is

NO T satis fied, tAONPD timing parameters apply.

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Figure 56: ODT Timing for Active and “Fast-Exit” Power-Down Mode

T1T0 T2 T3 T4 T5 T6

VALIDVALID VALID VALIDVALID VALID VALID

CK#

CKE

tAOF (MAX)

ODT

RTT tAON (MIN)

tAON (MAX)

tAOND

ADDR

tAOFD

tAOF (MIN)

VALIDVALID VALID VALIDVALID VALID VALID

CMD

DON’T CARE

Unknown R

Table 10: ODT Timing for Active and “Fast-Exit” Power-Down Modes

PARAMETER SYMBOL MIN MAX UNITS

ODT turn-on delay tAOND 22

tCK

ODT turn-on tAON tAC (MIN) tAC (MAX) + 1,000 ps

ODT turn-off delay tAOFD 2.5 2.5 tCK

ODT turn-off tAOF tAC (MIN) tAC (MAX) + 600 ps

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Figure 57: ODT timing for “Slow-Exit” and Precharge Power-Down Modes

DON’T CARE

T1T0 T2 T3 T4 T5 T6

VALIDVALID VALID VALIDVALID VALID VALID

CK#

CKE

ODT

RTT

ADDR

VALIDVALID VALID VALIDVALID VALID VALID

CMD

tCH tCL

tCK

tAONPD (MIN)

tAONPD (MAX)

tAOFPD (MIN) tAOFPD (MAX)

Transitioning RTT

VALID

RTT Unknown RTT On

Table 11: ODT timing for “Slow-Exit” and Precharge Power-Down Modes

PARAMETER SYMBOL MIN MAX UNITS

ODT turn-on (power-down mode) tAONPD tAC (MIN) + 2,000 2 x tCK+tAC (MAX) + 1,000 ps

ODT turn-off (power-down mode) tAOFPD tAC (MIN) + 2,000 2.5 x tCK + tAC (MAX) + 1,000 ps

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Figure 58: ODT “Turn Off” Timings when Entering Power-Down Mode

T1T0 T2 T3 T4 T5 T6

NOPNOP NOP NOPNOP NOP NOP

CK#

CKE

tANPD (MIN)

ODT

RTT tAOF (MIN)

tAOF (MAX)

tAOFD

ODT

RTT tAOFPD (MIN)

tAOFPD (MAX)

DON’T CARE

Transitioning RTT RTT Unknown RTT On

Table 12: ODT “Turn Off” Ti mi ngs wh en Enterin g Power-Down Mode

PARAMETER SYMBOL MIN MAX UNITS

ODT turn-off delay tAOFD 2.5 2.5 tCK

ODT turn-off tAOF tAC (MIN) tAC (MAX) + 600 ps

ODT turn-off (power-down mode) tAOFPD tAC (MIN) + 2,000 2.5 x tCK + tAC (MAX) + 1,000 ps

ODT to power-down entry latency tANPD 3tCK

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Figure 59: ODT “Tur n-On” Timing when Entering Power-Down Mode

T1T0 T2 T3 T4 T5 T6

NOPNOP NOP NOPNOP NOP NOP

CK#

CKE

tANPD (MIN)

ODT

RTT

tAON (MIN)

tAON (MAX)

tAOND

ODT

RTT

tAONPD (MIN)

tAONPD (MAX)

DON’T CARE

Transitioning RTT RTT Unknown RTT On

Table 13: ODT “Turn-On” Timing when Entering Power-Down Mode

PARAMETER SYMBOL MIN MAX UNITS

ODT turn-on delay tAOND 22

tCK

ODT turn-on tAON tAC (MIN) tAC (MAX) + 1,000 ps

ODT turn-on (power-down mode) tAONPD tAC (MIN) + 2,000 2 x tCK + tAC (MAX) + 1,000 ps

ODT to power-down entry latency tANPD 3tCK

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Figure 60: ODT “Turn-Off” Timing when Exiting Power-Down Mode

T1T0 T2 T3 T4 Ta0 Ta1

NOPNOP NOP NOPNOP NOP NOP

CK#

CKE

tAXPD (MIN)

ODT

tAOF (MAX)

ODT

tAOFPD (MIN)

tAOFPD (MAX)

COMMAND

tCKE (MIN)

Ta2 Ta3 Ta4 Ta5

NOPNOP NOP NOP

DON’T CARE

Transitioning R

Unknown R

tAOF (MIN)

tAOFD

Indicates a break in

time scale

Table 14: ODT “Turn-Of” Timing when Exiting Power-Down Mode

PARAMETER SYMBOL MIN MAX UNITS

ODT turn-off delay tAOFD 2.5 2.5 tCK

ODT turn-off tAOF tAC (MIN) tAC (MAX) + 600 ps

ODT turn-off (power-down mode) tAOFPD tAC (MIN) + 2,000 2.5 x tCK + tAC (MAX) + 1,000 ps

ODT to power-down exit latency tAXPD 8tCK

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Figure 61: ODT “Turn On” Timing when Exiting Power-Down Mode

T1T0 T2 T3 T4 Ta0 Ta1

NOPNOP NOP NOPNOP NOP NOP

CK#

CKE

tAXPD (MIN)

COMMAND

tCKE (MIN)

Ta2 Ta3 Ta4 Ta5

NOPNOP NOP NOP

ODT

RTT

tAON (MIN)

tAON (MAX)

tAOND

ODT

RTT

tAONPD (MIN)

tAONPD (MAX)

DON’T CARE

Transitioning RTT RTT Unknown RTT On Indicates a break in

time scale

Table 15: ODT “Tur n On” Timing when Exiting Power-Down Mode

PARAMETER SYMBOL MIN MAX UNITS

ODT turn-on delay tAOND 22

tCK

ODT turn-on tAON tAC (MIN) tAC (MAX) + 1,000 ps

ODT turn-on (power-down mode) tAONPD tAC (MIN) + 2,000 2 x tCK + tAC (MAX) + 1,000 ps

ODT to power-down exit latency tAXPD 8tCK

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Absolute Maximum Ratings

Stresses greater than those listed may cause perma-

nent damage to the device. This is a stress rating only,

and functional operation of the device at these or any

other conditions above those indicated in the opera-

tional sections of this specification is not implied.

Exposure to absolute maximum rating conditions for

extended peri ods may affec t reliabilit y.

Figure 62: Temperature Test Point Location

Table 16: Absolute Maximum DC Ratings

SYMBOL PARAMETER MIN MAX UNITS

VDD VDD Supply Voltage Relative to VSS -1.0 2.3 V

VDDQVDDQ Supply Voltage Relative to VSS -0.5 2.3 V

VDDLVDDL Supply Voltage Relative to Vss -0.5 2.3 V

VIN, VOUT Voltage on any Pin Relative to VSS -0.5 2.3 V

TSTG Storage Temperature (Tcase)1-55 100 °C

TCOperating Temperature (Tcase)1,2 085°C

IIInput Leaka ge Current

Any input 0V <= Vin <= VDD

Vref input 0V <= Vin <= 0.95V

(All other pins not under test = 0V)

-5 5 uA

IOZ Output Leakage Current

0V <= Vout <= VddQ

DQs and ODT are disabled

-5 5 uA

NOTE:

1. MAX operating case temperature; TC is measured in the center of the package illustrated in Figure 62.

2. Device functionality is not guaranteed if the DRAM device exceeds the maximum TC during operation.

8.00

4.00

12.00

6.00

Test Point

8mm x 12mm “FP” FBGA

8.00

4.00

14.00

7.00

8mm x 14mm “FG” FBGA

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AC and DC Operating Conditions

NOTE:

1. VDD and VDDQ must track each other. VDDQ must be less than or equal to VDD.

2. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-

peak noise (non-common mode) on Vref may not exceed ±1% of the DC value. Peak-to-peak AC noise on VREF may not

exceed ±2 percent of VREF (DC). This measurement is to be taken at the nearest VREF bypass capacitor.

3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal

to Vref and must track variations in the DC level of VREF.

4. VDDQ tracks with VDD; VDDL tracks with VDD.

NOTE:

1. RTT1(EFF) and RTT2(EFF) a re determin ed by a pplying VIH(AC) and VIL(AC) to pin unde r test separately, then measure current

I(VIH(AC)) and I(VIL(AC)) respectively.

2. Measure voltage (VM) at tested pin with no load.

Table 17: Recommended DC Operating Conditions (SSTL_18)

All voltages referenced to VSS

PARAMETER SYMBOL MIN NOM MAX UNITS NOTES

Supply Voltage VDD 1.7 1.8 1.9 V 1

VDDL Supply Voltage VDDL 1.7 1.8 1.9 V 4

I/O Supply Voltage VDDQ 1.7 1.8 1.9 V 4

I/O Reference Voltage VREF 0.49 x VDDQ0.50 x VDDQ0.51 X VDDQV 2

I/O Termination Voltage (system) VTT VREF - 40 VREF VREF + 40 mV 3

Table 18: ODT DC Electrical Characteristics

All voltages referenced to VSS

PARAMETER SYMBOL MIN NOM MAX UNITS NOTES

RTT effective impedance value for 75W setting

EMR (A6, A2) = 0, 1 RTT1(EFF)60 75 90 W1

RTT effective impedance value for 150W setting

EMR (A6, A2) = 1, 0 RTT2(EFF) 120 150 180 W1

Deviation of VM with respect to VDDQ/2 DVM -3.75 +3.75 % 2

RTT EFF() VIH AC()VIL AC()–

IH AC()()IVIL AC()()–

-------------------------------------------------------------=

DVM 2VM´

VDDQ

------------------1–

èø

æö

100%´=

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Input Electrical Characteristics and Operating Conditions

Figur e 63: Single-Ended Input Signal Levels

NOTE:

Numbers in diagram reflect nomimal values.

Table 19: Input DC Logic Levels

All voltages referenced to VSS

PARAMETER SYMBOL MIN MAX UNITS NOTES

Input High (Logic 1) Voltage VIH(DC)VREF + 125 VDDQ + 300 mV

Input Low (Logic 0) Voltage VIL(DC)-300 VREF - 125 mV

Table 20: Input AC Logic Levels

All voltages referenced to VSS

PARAMETER SYMBOL MIN MAX UNITS NOTES

Input High (Logic 1) Voltage VIH(AC)VREF + 250 - mV

Input Low (Logic 0) Voltage VIL(AC)– VREF - 250 mV

650mV

775mV

864mV

882mV

900mV

918mV

936mV

1,025mV

1,150mV

VIL (AC)

VIL (DC)

VREF - AC Noise

VREF - DC Error

VREF + DC Error

VREF + AC Noise

VIH (DC)

VIH (AC)

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NOTE:

1. VIN (DC) specifies the allowable DC execution of each input of differential pair such as CK, CK#, DQS, DQS#, LDQS,

LDQS#, UDQS, UDQS#, and RDQS, RDQS#.

2. VID (DC) specifies the input differential voltage | VTR - VCP | required for switching, where VTR is the true input (such as

CK, DQS, LDQS, UDQS, RDQS) level and VCP is the compleme ntary input (such as CK #, DQS#, LDQS# , UDQ S#, R DQS#). The

minimum value is equal to VIH (DC) - VIL (DC). Differential input signal levels are shown in Figure 64.

3. VID (AC) specifies the input differential voltage | VTR - VCP | required for switching, where VTR is the true input (such as

CK, DQS, LDQS, UDQS, RDQS) level and VCP is the compleme ntary input (such as CK #, DQS#, LDQS# , UDQ S#, R DQS#). The

minimum value is equal to VIH (AC) - VIL (AC) from Table 20 on page 74.

4. The typical value of VIX (AC) is expected to be about 0.5 x VDDQ of the transmitting device and VIX (AC) is expected to

track variations in VDDQ. V IX (AC) indicates the voltage at which differential input signals must cross as shown in

Figure 64. Figure 64: Differential Input Signal Levels

NOTE:

1. This provides a minimum of 850mV to a maximum of 950mV and is always VDDQ/2.

2. TR and CP must cross in this region.

3. TR and CP must meet at least VID (DC) min when static and is centered around VMP (DC).

4. TR and CP must have a minimum 500mV peak-to-peak swing.

5. TR and CP may not be more positive than VDDQ + 0.3V or more negative than VSS - 0.3V.

6. For AC operation, all DC clock requirements must also be satisfied.

7. Numbers in diagram reflect nominal values.

8. TR represents the CK, DQS, RDQS, LDQS and UDQS signals; CP represents CK#, DQS#, RDQS#, LDQS# and UDQS# signals.

Table 21: Differential Input Logic Levels

All voltages referenced to VSS

PARAMETER SYMBOL MIN MAX UNITS NOTES

DC Input Signal Voltage VIN (DC) -300 VDDQ + 300 mV 2

DC Differe nt ial Inpu t Voltage VID (DC) 250 VDDQ + 600 mV 3

AC Differe nt ial Inpu t Voltage VID (AC) 500 VDDQ + 600 mV 4

AC Differential Cross-Point Voltage VIX (AC) 0.50 x VDDQ - 175 0.50 x VDDQ + 175 mV 5

CP8

TR8

2.1 V

@ V

Q=1.8V

Maximum Clock Level

Minimum Clock Level

- 0.30V

0.9V

1.075 V

0.725 V V

(AC)

(DC)

(DC) V

(AC)

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NOTE:

1. All voltages referenced to VSS.

2. Input waveform setup timing (tIS) is referenced from the input signal crossing at the VIH(ac) level for a rising s ignal and

VIL(DC) for a falling signal applied to the device under test as shown in Figure 65.

3. Input waveform hold (tIH) timing is referenced from the input signal crossing at the VIL(DC) level for a rising signal and

VIH(DC) for a falling signal applied to the device under test as shown in Figure 65

4. Input waveform setup timing (tDS) a nd hold timing (tDH) for single-end ed data strobe is referenced from the crossing of

DQS, UDQS, or LDQS through the VREF level applied to the device under test as shown in Figure 67.

5. Input waveform setup timing (tDS) and hold timing (tDH) when differential data strobe is enabled is referenced from

the crosspoint of DQS,DQS# or UDQS,UDQS# or LDQS,LDQS# as shown in Figure 66.

6. Input waveform timing is referenced to the crossing point level (Vix) of two input signals (Vtr and Vcp) applied to the

device under test, where Vtr is the “true” input signal and Vcp is the “complementary” input signal shown in Fig ure 68.

Figure 6 5: AC Input Test Signal Waveform Command/Address pins

Table 22: AC Input Test Conditions

PARAMETER SYMBOL MIN MAX UNITS NOTES

Input setup timing measurement reference level

BA0-BA1, A0-A13, CS #, RAS#, CAS#, WE# , ODT, DM, UDM,

LDM and CKE

Vrs See Note 2 1,2

Input hold timing measurement reference level

BA0-BA1, A0-A13, CS #, RAS#, CAS#, WE# , ODT, DM, UDM,

LDM and CKE

Vrh See Note3 1,3

Input timing m easure men t refere nc e l eve l (sin gle- ende d)

DQS for x4x8; UDQS, LDQS for x16 VREF VDDQ*0.49 VDDQ*0.51 V 1,4

Input timing measurement reference level (differential)

CK, CK# for x4,x8,x16

DQS, DQS# for x4,x8; RDQS, RDQS# for x8

UDQS, UDQS#, LDQS, LDQS# for x16

Vrd VIX(cross point) See Note 5 V 1,5

Input signal minimum slew rate (single-ended) SLEW 1.0 V/ns 1,6

Input signal minimum slew rate (differential) SLEW 2.0 V/ns 1,6

VREF

VIL(DC) MAX

VIL(AC) MAX

VSSQ

VIH(DC) MIN

VIH(AC) MIN

VDDQ

VSWING (MAX)

tIS tIH

CK#

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Figure 66: AC Input Test Signal Waveform for Data with DQS,DQS# (differential)

Figure 67: AC Input Test Signal Waveform for Data with DQS (single-ended)

Figur e 68: AC Input Test Signal Waveform (dif ferential)

VREF

VIL(DC) MAX

VIL(AC) MAX

VSSQ

VIH(DC) MIN

VIH(AC) MIN

VDDQ

VSWING (MAX)

tDS tDH

DQS#

DQS

tDS tDH

VREF

VIL(DC) MAX

VIL(AC) MAX

VSSQ

VIH(DC) MIN

VIH(AC) MIN

VDDQ

VSWING (MAX)

tDS tDH

DQS

tDS tDH

VREF

VTR

VSWING

VCP

VDDQ

VSSQ

VIX

Crossing Point

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Power and Ground Clamp Characte ristics

Power and ground clamps are required on the fol-

lowing input-only pins: BA1, BA0, A13–A0 for x4 and

x8; A12-A0 for x16, CS#, RAS#, CAS#, WE#, ODT, and

CKE.

Figure 69: Input Clamp Characteristics

Table 23: Input Clamp Characteristics

VOLTAGE ACROSS CLAMP

(V) MINIMUM POWER CLAMP CURRENT

(mA) MINIMUM GROUND CLAMP

CURRENT (mA)

0.0 0.0 0.0

0.1 0.0 0.0

0.2 0.0 0.0

0.3 0.0 0.0

0.4 0.0 0.0

0.5 0.0 0.0

0.6 0.0 0.0

0.7 0.0 0.0

0.8 0.1 0.1

0.9 1.0 1.0

1.0 2.5 2.5

1.1 4.7 4.7

1.2 6.8 6.8

1.3 9.1 9.1

1.4 11.0 11.0

1.5 13.5 13.5

1.6 16.0 16.0

1.7 18.2 18.2

1.8 21.0 21.0

0.0

5.0

10.0

15.0

20.0

25.0

0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8

Voltage Across Clamp (V)

Minimum Clamp Current (mA)

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AC Overshoot/Undershoot Specification

Figure 70: Overshoot

Figure 71: Undershoot

Table 24: Address and Control Pins

Applies to A0–A12, BA0–BA1, CS#, RAS#, CAS#, WE#, CKE, ODT

PARAMETER

SPECIFICATION

-5, -5E -37E

Maximum peak amplitude allowed for overshoot area (See Figure 70) 0.9V 0.9V

Maximum peak amplitude allowed for undershoot area (See Figure 71) 0.9V 0.9V

Maximum overshoot area above VDD (See Figure 70) 0.75V/ns 0.56V/ns

Maximum undershoot area below VSS (See Figure 71) 0.75V/ns 0.56V/ns

Table 25: Clock, Data, Strobe, and Mask Pins

Applies to DQ0–DQ15, DQS, DQS#, RDQS, RDQS#, UDQS, UDQS#, LDQS, LDQS#, DM, UDM, LDM

PARAMETER

SPECIFICATION

-5, -5E -37E

Maximum peak amplitude allowed for overshoot area (See Figure 70) 0.9V 0.9V

Maximum peak amplitude allowed for undershoot area (See Figure 70) 0.9V 0.9V

Maximum overshoot area above VDDQ ( See Figur e 70) 0.38V/ns 0.28V/ns

Maximum undershoot area below VSSQ (See Figure 71) 0.38V/ns 0.28V/ns

Overshoot Area

Maximum Amplitude

VDD/VDDQ

VSS/VSSQ

Volts

Time (ns)

(V)

Undershoot Area

Maximum Amplitude

VSS/VSSQ

Volts

Time (ns)

(V)

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Output Electrical Characteristics and Operating Conditions

NOTE:

1. The typical value of VOX (AC) is expected to be about 0.5 x VDDQ of the transmitting device and VOX (AC) is expected to

track variations in VDDQ. V OX (AC) indicates the voltage at which differential output signals must cross.

Figure 72: Differential Output Signal Levels

NOTE:

1. All voltages referenced to VSS.

2. See AC Timing Reference Load in Figure 73.

3. The VDDQ of the device under test is referenced.

Figure 73: AC Timing Reference Load

Table 26: Differential AC Output Parameters

PARAMETER SYMBOL MIN MAX UNITS NOTES

AC Differential Cross-Point Voltage VOX (AC) 0.50 x VDDQ - 125 0.50 x VDDQ + 125 mV 1

VTR

VID

VCP

VDDQ

VSSQ

VOX

Crossing Point

Table 27: AC Output Test Conditions

PARAMETER SYMBOL VALUE UNITS NOTES

Output timing measurement reference level VOTR 0.5 x VDDQV 1, 3

Output

(VOUT)Reference

Point

25Ω

VTT = VDDQ/2

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NOTE:

1. For IOH (DC); VDDQ = 1.7V, VOUT = 1420mV. (VOUT - VDDQ)/IOH must be less than 21W for values of VOUT between VDDQ

and VDDQ - 280mV.

2. For IOL (DC); VDDQ = 1.7V, VOUT = 280mV. VOUT/IOL must be less than 21W for values of VOUT between 0V and 280mV.

3. The DC value of VREF applied to the receiving device is set to VTT.

4. The values of IOH (DC) and IOL (DC) are based on the conditions given in Notes 1 and 2. Th ey are used to test device drive

current capability to ensu re V IH (MIN) plus a noise margin and VIL (MAX) minus a noise margin are delivered to an

SSTL_18 receiver. The actual current values are derived by shifting the desired driver operating point (See output IV

curves) along a 21W load line to define a convenient driver current for measurement.

NOTE:

1. Absolute specifications: 0°C £ Tcase £ +85°C; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V.

2. Impedance measurement co ndition for output source DC current: VDDQ = 1.7V; VOUT = 1420mV; (VOUT - VDDQ)/IOH must

be less than 23.4W for values of VOUT between VDDQ and VDDQ - 28 0m V. Impedance me asurem ent cond ition for o utput

sink DC current: VDDQ = 1.7V; VOUT = 280mV; VOUT/IOL must be less than 23.4W for va l u es o f VOUT between 0V and

280mV.

3. Mismatch is absolute value between pull-up and pull-down, both are measured at same temperature and voltage.

4. Output slew rate for falling and rising edges is measured between VTT - 250mV and VTT + 250mV for single ended sig-

nals. For dif ferentia l signals (e.g. DQ S - DQS) output slew rate is measu red betwee n DQS - DQS = -50 0mV and DQS - DQS

= +500mV. Output slew rate is guaranteed by design, but is not necessarily tested on each device.

5. The absolute value of the slew rate as measured from VIL (DC)MAX to VIH (DC) MIN is equal to or greater than the slew

rate as measured from VIL (AC) MAX to VIH (AC) MIN. This is guaranteed by design and characterization.

Figure 74: Outp ut Slew Rate Load

Table 28: Output DC Current Drive

PARAMETER SYMBOL VALUE UNITS NOTES

Output Minimum Source DC Current IOH -13.4 mA 1,3,4

Output Minimum Sink DC Current IOL 13.4 mA 2,3,4

Table 29: Output Characteristics

PARAMETER SYMBOL MIN NOM MAX UNITS NOTES

Output impedance 12.6 18 23.4 Ws1,2

Pull-up and Pull-down mismatch 04

Ws1,2,3

Output slew rate 1.5 5 V/ns 1,4,5

Output

(VOUT)Reference

Point

25Ω

VTT = VDDQ/2

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Full Strength Pull-Down Driver Characteristics

Figure 75: Ful l Strength Pull-Do wn Chara c teristics

Pull- down Charact er istics

0.00

20.00

40.00

60.00

80.00

100.00

120.00

0.0 0.5 1.0 1.5

Vout (V)

Iout (mA)

Table 30: Pull dow n Cur rent (mA)

VOLTAGE (V) MINIMUM NOMINAL MAXIMUM

0.0 0.00 0.00 0.00

0.1 4.60 5.63 7.90

0.2 9.20 11.3 15.90

0.3 12.90 16.52 23.80

0.4 17.50 22.19 31.80

0.5 21.60 27.59 39.70

0.6 25.32 32.86 47.70

0.7 28.36 37.51 55.00

0.8 30.53 41.77 62.30

0.9 32.16 45.70 69.40

1.0 33.26 48.85 75.30

1.1 33.96 51.51 80.50

1.2 34.40 53.55 84.60

1.3 34.71 55.08 87.70

1.4 34.94 56.58 90.80

1.5 35.11 57.60 92.90

1.6 35.25 58.57 94.90

1.7 35.37 59.57 97.00

1.8 35.48 60.56 99.10

1.9 35.57 61.50 101.10

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Full Strength Pull-Up D river Characteristics

Figure 76: Full Strength Pull-up Characteristics

Pull-u p Character istics

-120.0

-100.0

-80.0

-60.0

-40.0

-20.0

0.0 0.0 0.5 1.0 1.5

VDDQ - Vout (V)

Iout (mA)

Table 31: Pull-Up Curr ent (mA)

VOLTAGE (V) MINIMUM NOMINAL MAXIMUM

0.0 0.0 0.0 0.0

0.1 -4.60 -5.63 -7.9

0.2 -9.20 -11.30 -15.9

0.3 -13.80 -16.92 -23.8

0.4 -18.40 -22.59 -31.8

0.5 -21.94 -27.74 -39.7

0.6 -24.27 -32.39 -47.7

0.7 -26.01 -36.45 -55.0

0.8 -27.43 -40.38 -62.3

0.9 -28.40 -44.01 -69.4

1.0 -29.16 -47.01 -75.3

1.1 -29.79 -49.63 -80.5

1.2 -30.32 -51.71 -84.6

1.3 -30.79 -53.32 -87.7

1.4 -31.19 -54.90 -90.8

1.5 -31.60 -56.03 -92.9

1.6 -31.93 -57.07 -94.9

1.7 -32.24 -58.16 -97.0

1.8 -32.78 -59.35 -99.1

1.9 -33.02 -60.35 -101.1

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FBGA Package Capacitance

NOTE:

1. This parameter is sampled. VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V, VREF = VSS, f = 100 MHz, TCASE = 25°C, VOUT (DC) =

VDDQ/2, VOUT (pea k to peak) = 0.1V. DM input is groupe d with I/O pins, reflecting the fact that they are matched in load-

ing.

2. The input capacitance per pin group will not differ by more than this maximum amount for any given device.

3. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maximum amount for any given

device.

Table 32: Input Capacitance

PARAMETER SYMBOL MIN MAX UNITS NOTES

Input Capacitance: CK, CK# CCK 1.0 2.0 pF 1

Delta Input Capacitance: CK, CK# CDCK – 0.25 pF 2

Input Capacitance: BA0, BA1, A0-A12, CS#, RAS#,

CAS#, WE#, CKE, ODT CI 1.0 2.0 pF 1

Delta Input Capacitance: BA0, BA1, A0-A12, CS#,

RAS#, CAS#, WE#, CKE, ODT CDI – 0.25 pF 2

Input/Output Capacitance: DQs, DQS, DM, NF CIO 2.5 4.0 pF 1

Delta Input/Output Capacitance: DQs, DQS, DM, NF CDIO – 0.5 pF 3

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IDD Specifications an d Conditio ns

Table 33: DDR2 IDD Specificatio ns and Condit ions

Notes: 1–5; notes appear on page 86.

PARAMETER/CONDITION SYMBOL CONFIG -37E -5E -5 UNITS

Operating one bank active-precharge current;

tCK = tCK (IDD), tRC = tRC (IDD), tRAS = tRAS MIN (IDD); CKE is

HIGH, CS# is HIGH between valid commands; Address bus inputs

are SWITCHING; Data bus inputs are SWITCHING.

IDD0 x4, x8, x16 TBD TBD TBD mA

Operating one bank active-read-precharge current;

IOUT = 0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK (IDD),

tRC = tRC (IDD), tRAS = tRAS MIN (IDD), tRCD = tRCD (IDD); CKE is

HIGH, CS# is HIGH between valid commands; Address bus inputs

are SWITCHING; Data pattern is same as IDD4W.

IDD1 x4, x8, x16 TBD TBD TBD mA

Precharge power-down current;

All banks idle; tCK = tCK (IDD); CKE is LOW; Other control and

address bus inputs are STABLE; Data bus inputs are FLOATING. IDD2P x4, x8, x16 TBD TBD TBD mA

Precharge quiet standby current;

All banks idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; Other

control and address bus inputs are STABLE; Data bus inputs are

FLOATING.

IDD2Q x4, x8, x16 TBD TBD TBD mA

Precharge standby current;

All banks idle; tCK = tCK (IDD); CKE is HIGH, CS# is HIGH; Other

control and address bus inputs are SWITCHING; Data bus inputs

are SWITCHING.

IDD2N x4, x8, x16 TBD TBD TBD mA

Active power-down current;

All banks open; tCK = tCK (IDD); CKE is LOW; Other control and

address bus inputs are STABLE; Data bus inputs are FLOATING. IDD3P

Fast PDN Exit

MR[12] = 0 TBD TBD TBD mA

Slow PDN Exit

MR[12] = 1 TBD TBD TBD mA

Active standby current;

All banks open; tCK = tCK(IDD), tRAS = tRAS MAX (IDD), tRP =

tRP(IDD); CKE is HIGH, CS# is HIGH between valid commands;

Other control and address bus inputs are SWITCHING; Data bus

inputs are SWITCHING.

IDD3N x4, x8, x16 TBD TBD TBD mA

Operating burst write current;

All banks open, Continuous burst writes; BL = 4, CL = CL (IDD),

AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD), tRP = tRP (IDD);

CKE is HIGH, CS# is HIGH between valid commands; Address bus

inputs are SWITCHING; Data bus inputs are SWITCHING.

IDD4W x4, x8 TBD TBD TBD mA

x16 TBD TBD TBD mA

Operating burst read current;

All banks open, Continuous burst reads, IOUT = 0mA; BL = 4,

CL = CL (IDD), AL = 0; tCK = tCK (IDD), tRAS = tRAS MAX (IDD),

tRP = tRP (IDD); CKE is HIGH, CS# is HIGH between valid

commands; Address bus inputs are SWITCHING; Data bus inputs

are SWITCHING.

IDD4R

x4, x8 TBD TBD TBD mA

x16 TBD TBD TBD mA

Burst refresh current;

tCK = tCK (IDD); Refresh command at every tRFC (IDD) interval;

CKE is HIGH, CS# is HIGH between valid commands; Other

control and address bus inputs are SWITCHING; Data bus inputs

are SWITCHING.

IDD5 x4, x8, x16 TBD TBD TBD mA

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NOTE:

1. IDD specifications are tested after the device is properly initialized. 0°C £TCASE £ 85°C.

VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V, VDDL= +1.8V ±0.1V, VREF=VDDQ/2.

2. Input slew rate is specified by AC Parametric Test Conditions.

3. IDD parameters are specified with ODT disabled.

4. Data bus consists of DQ, DM, DQS, DQS#, RDQS, RDQS#, LDQS, LDQS#, UDQS, and UDQS#. IDD values must be me t with

all combinations of EMR bits 10 and 11.

5. Definit i on s for IDD Condi ti ons:

LOW is defined as VIN £ VIL (AC) (MAX).

HIGH is defined as VIN ³ VIH (AC) (MIN).

STABLE is defined as inputs stable at a HIGH or LOW level.

FLOATING is defined as inputs at VREF = VDDQ/2.

SWITCHING is defined as inputs changing between HIGH and LOW every other clock cycle (once per two clocks)

for address and control signals.

Switching is defined as inputs changing between HIGH and LOW every other data transfer (once per clock) for

DQ signals not including masks or strobes.

Self refresh current;

CK and CK# at 0V; CKE £ 0.2V; Other control and address bus

inputs are FLOATING ; Dat a bus inputs are FLOATING. IDD6 x4, x8, x16 TBD TBD TBD mA

Operating bank interleave read current;

All bank interleaving reads, IOUT= 0mA; BL = 4, CL = CL (IDD),

AL = tRCD (IDD)-1 x tCK (IDD); tCK = tCK (IDD), tRC = tRC(IDD),

tRRD = tRRD(IDD), tRCD = tRCD(IDD); CKE is HIGH, CS# is HIGH

between valid commands; Address bus inputs are STABLE

during DESELECTs; Data bus inputs are SWITCHING; See IDD7

Conditions for detail.

IDD7 x4, x8, x16 TBD TBD TBD mA

Table 33: DDR2 IDD Specificatio ns an d Conditio ns (Continu ed)

Notes: 1–5; notes appear on page 86.

PARAMETER/CONDITION SYMBOL CONFIG -37E -5E -5 UNITS

Table 34: General IDD Parameters

IDD PARAMETER -37E -5E -5 UNITS

CL (IDD)434

tCK

tRCD ( IDD)15 15 20 ns

tRC (IDD)60 60 65 ns

tRRD ( IDD) - x4/x8 7.5 7.5 7.5 ns

tRRD ( IDD) - x16 10 10 10 ns

tCK (IDD)3.75 5 5 ns

tRAS MIN (IDD)45 45 45 ns

tRAS MAX (IDD)70,000 70,000 70,000 ns

tRP (IDD)15 15 20 ns

tRFC (IDD)105 105 105 ns

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IDD7 Conditions

The detailed timings are shown below for IDD7.

Changes will be required if timing parameter changes

are made to the specification.

NOTE:

1. Legend: A = active; RA = read auto precharge; D = deselect.

2. All banks are being interleaved at minimum tRC (IDD) without violating tRRD (IDD) using a burst length of 4.

3. Control and address bus inputs are STABLE during DESELECTs.

4. IOUT = 0mA.

Table 35: IDD7 Timing Patterns

All Bank Interleave Read operation

SPEED GRADE IDD7 TIMING PATTERNS FOR x4/x8/x16

-5

A0 RA0 A1 RA 1 A2 R A2 A3 RA3 D D D D D

-5E

A0 RA0 A1 RA 1 A2 R A2 A3 RA3 D D D D

-37E

A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D

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Table 36: AC Operati ng Conditions (Sheet 1 of 4)

Notes: 1–5; notes appear on page 92; 0°C £ Tcase £ +85°C; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V

AC CHARACTERISTICS -37E -5E -5

PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES

Clock

Clock cycle

time CL = 4 tCK (4) 3, 750 8, 000 5,000 8,000 5,000 8,000 ps 16, 25

CL = 3 tCK (3) 5,000 8,000 5,000 8,000 – – ps 16, 25

CK high-level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK 19

CK low-level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK 19

Half clock period tHP MIN

(tCH,

tCL)

MIN

(tCH,

tCL)

MIN

(tCH,

tCL) ps 20

Clock jitter tJIT TBD TBD TBD TBD TBD TBD ps 18

Data

DQ output access time

from CK/CK# tAC -500 +500 -600 +600 -600 +600 ps

Data-out high-impe dance

window from CK/CK# tHZ tAC MAX tAC MAX tAC MAX ps 8, 9

Data-out low-impedance

window from CK/CK# tLZ tAC MIN tAC MAX tAC MIN tAC MAX tAC MIN tAC MAX ps 8, 10

DQ and DM input setup

time relative to DQS tDS 100 150 150 ps 7, 15,

DQ and DM input hold

time relative to DQS tDH 225 275 275 ps 7, 15,

DQ and DM input pulse

width (for each input) tDIPW 0.35 0.35 0.35 tCK

Data hold skew factor tQHS 400 450 450 ps

DQ–DQS hold, DQS to

first DQ to go nonvalid,

per access tQH tHP -

tQHS

tHP -

tQHS

tHP -

tQHS ps 15, 17

Data valid output

window (DVW) tDVW tQH -

tDQSQ

tQH -

tDQSQ tQH -

tDQSQ ns 15, 17

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Data Strobe

DQS input high pulse

width tDQSH 0.35 0.35 0.35 tCK

DQS input low pulse

width tDQSL 0.35 0.35 0.35 tCK

DQS output access time

from CK/CK# tDQSCK -450 +450 -500 +500 -500 +500 ps

DQS falling edge to CK

rising – setup time tDSS 0.2 0.2 0.2 tCK

DQS falling edge from CK

rising – hold time tDSH 0.2 0.2 0.2 tCK

DQS–DQ skew , DQS to last

DQ valid, per group, per

access tDQSQ 300 350 350 ps 15, 17

DQS r ead p reamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK

DQS read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK

DQS write preamble

setup time tWPRES 000ps12, 13

DQS write preamble tWPRE 0.25 0.25 0.25 tCK

DQS write postamble tWPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK 11

Write command to first

DQS latching transition tDQSS WL -

0.25 WL +

0.25 WL -

0.25 WL +

0.25 WL -

0.25 WL +

0.25 tCK

Table 36: AC Operati ng Conditions (Sheet 2 of 4)

Notes: 1–5; notes appear on page 92; 0°C £ Tcase £ +85°C; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V

AC CHARACTERISTICS -37E -5E -5

PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES

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Command and Address

Address and control inpu t

pulse width for each

input tIPW 0.6 0.6 0.6 tCK

Address and control inpu t

setup time tIS 250 350 350 ps 6, 22

Address and control inpu t

hold time tIH 375 475 475 ps 6, 22

CAS# to CAS# command

delay tCCD 222

tCK

ACTIVE to ACTIVE (same

bank) command tRC 60 60 65 ns

ACTIVE bank a to ACTIVE

bank b co mma nd

tRRD

(x4, x8) 7.5 7.5 7.5 ns 28

tRRD

(x16) 10 10 10 ns 28

ACTIVE to READ or WRITE

delay tRCD 15 15 20 ns

ACTIVE to PRECHARGE

command tRAS 45 70,000 45 70,000 45 70,000 ns 21

Internal READ to

precharge command

delay tRTP 7.5 7.5 7.5 ns 24, 28

Write recovery time tWR 15 15 15 ns 28

Auto precharge write

recovery + precharge time tDAL tWR +

tRP

tWR +

tRP

tWR +

tRP ns 23

Internal WRITE to REA D

command dela y tWTR 7.5 10 10 ns 28

PRECHARGE command

period tRP 15 15 20 ns

LOAD MODE command

cycle time tMRD 222

tCK

CKE low to CK,CK#

uncertainty tDELAY 4.375 4.375 5.83 5.83 5.83 5.83 ns 29

Refresh

REFRESH to Active

command interval tRFC 105 70,000 105 70,000 105 70,000 ns 14

Aver age periodic refresh

interval tREFI 7.8 7.8 7.8 µs 14

Self Refresh

Exit self refresh to non-

READ command tXSNR

tRFC

(MIN) +

tRFC

(MIN) +

tRFC

(MIN) +

10 ns

Exit self refresh to READ

command tXSRD 200 200 200 tCK

Exit self refresh timing

reference tISXR 250 350 350 ps 6, 30

Table 36: AC Operati ng Conditions (Sheet 3 of 4)

Notes: 1–5; notes appear on page 92; 0°C £ Tcase £ +85°C; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V

AC CHARACTERISTICS -37E -5E -5

PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES

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ODT

ODT turn-on delay tAOND 222222

tCK

ODT turn-on tAON tAC

(MIN)

tAC

(MAX) +

1,000

tAC

(MIN)

tAC

(MAX) +

1000

tAC

(MIN)

tAC

(MAX) +

1000 ps 26

ODT turn-off delay tAOFD 2.5 2.5 2.5 2.5 2.5 2.5 tCK

ODT turn-off tAOF tAC

(MIN)

tAC

(MAX) +

600

tAC

(MIN)

tAC

(MAX) +

600

tAC

(MIN)

tAC

(MAX) +

600 ps 27

ODT turn-on (power-

down mode) tAONPD

tAC

(MIN) +

2000

2 x tCK +

tAC

(MAX) +

1,000

tAC

(MIN) +

2,000

2 x tCK +

tAC

(MAX) +

1000

tAC

(MIN) +

2,000

2 x tCK +

tAC

(MAX) +

1000

ODT turn-off (power-

down mode) tAOFPD

tAC

(MIN) +

2,000

2.5 x tCK

+ tAC

(MAX) +

1,000

tAC

(MIN) +

2,000

2.5 x tCK

+ tAC

(MAX) +

1,000

tAC

(MIN) +

2,000

2.5 x tCK

+ tAC

(MAX) +

1,000

ODT to power-down

entry latency tANPD 333

tCK

ODT power-down exit

latency tAXPD 888

tCK

Power-Down

Exit active power-down to

READ command,

MR[bit12=0] tXARD 222tCK

Exit active power-down to

READ command,

MR[bit12=1] tXARDS 6 - AL 6 - AL 6 - AL tCK

Exit precharge power-

down to any non-READ

command. tXP 222

tCK

Exit precharge power-

down to READ command. tXPRD 6 - AL 6 - AL 6 - AL tCK

CKE minimum high/low

time tCKE 333

tCK

Table 36: AC Operati ng Conditions (Sheet 4 of 4)

Notes: 1–5; notes appear on page 92; 0°C £ Tcase £ +85°C; VDDQ = +1.8V ±0.1V, VDD = +1.8V ±0.1V

AC CHARACTERISTICS -37E -5E -5

PARAMETER SYMBOL MIN MAX MIN MAX MIN MAX UNITS NOTES

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Notes

1. All voltages referenced to VSS.

2. Tests for AC timing, IDD, and el ectrical AC and DC

characteristics may be conducted at nominal ref-

er enc e/ s upp l y volta ge level s, but the related spec-

ifications and device operation are guaranteed for

the full voltage range specified.

3. Outputs measured with equivalent load:

4. AC t iming and IDD tests may use a VIL-to-VIH swing

of up to 1.0V in the test environment and parame-

ter specifications are guaranteed for the specified

AC input level s und er nor mal u se cond itions. The

minimum slew rate for the input signals used to

test the device is 1.0V/ns for signals in the range

between VIL (AC) and VIH (AC).

5. The AC and DC input level specifications are as

defined in the SSTL_18 standard (i.e., the receiver

will effectively switch as a result of the signal

crossing th e AC input level and will remain in th at

state as long as the signal does not ring back

above [below] the DC input LOW [HIGH] level).

6. Command/Address minimum input slew rate =

1.0V/ns and is referenced to the crosspoint of CK/

CK#. tIS ti mi ng is referenced to VIH(ac) for a rising

signal and VIL(ac) for a falling signal as shown in

Figure65 on page 76. tIH timing is referenced to

VIH(dc) for a rising signal and VIL(DC) for a fal ling

signal as shown in Figure65 on page 76. Derating

values for Command/Address input signal slew

rates < 1.0V/ns is TBD.

7. Data minimum input slew rate = 1.0V/ns and is

referenced to the crosspoint of DQS/DQS# if dif-

ferential strobe feature is enabled. tDS timing is

referenced to VIH(ac) for a rising signal and

VIL(AC) for a falling signal as shown in Figure66

on page 77. tDH timing is referenced to VIH(DC)

for a rising signal and VIL(DC) for a falling signal

as shown in Figure 66 on p age 77. Derating values

for Data input signal slew rates < 1.0V/ns is TBD . I f

single-ended data strobe is enabled, the timing

reference used for DQS is VREF as shown in

Figure67 on page 77.

8. tHZ and tLZ transitions occur in the same access

time windows as valid data transitions. These

para meters ar e not referenc ed to a s peci fic v oltag e

level, but specify when the device output is no

longer dr iving (tHZ) or begins driving (tLZ).

9. This maximum value is derived from the refer-

enced test load. tHZ (MAX) will prevail over

tDQSCK (MAX) + tRPST (MAX) cond it ion.

10. tLZ (MIN) will prevail over a tDQSCK (MIN) +

tRPRE (MAX) condition.

11. The intent of the Don’t Car e st ate after completion

of the postamble is the DQS-driven signal should

either be high, low or high-Z and that any signal

transition wi thin the input swit ching region mu st

follow valid input requirements. That is if DQS

transitions high (above VIHDC(min) then it must

not transition low (below VIH(DC) prior to

tDQSH(min).

12. This is not a device limit. The device will operate

with a negative value, but system performance

could be degraded due to bus turnaround.

13. It is recommended that DQS be valid (HIGH or

LOW) on or before the WRITE command. The

case shown (DQS going from High-Z to logic

LO W) applies when no WRITEs were previously in

progress on the bus. If a previous WRITE was in

progress, DQS could be HIGH during this time,

depending on tDQSS.

14. The refresh period is 64ms. This equates to an

average refresh rate of 7.8125µs. However, an

REFRESH command must be asserted at least

once every 70.3µs or tRFC (MAX). To ensure all

rows of all banks are properly refreshed, 8192

REFRESH commands must be issued every 64ms.

15. Referenced to each output group: x4 = DQS with

DQ0-DQ3; x8 = DQS with DQ0–DQ7; x16 = LDQS

with DQ0–DQ7; and UDQS with DQ8–DQ15.

16. CK and CK# input slew rate must be ³ 1 V/ns (³ 2

V/ns if measured differentially).

17. The data valid window is derived by achieving

other specifications - tHP. (tCK/2), tDQSQ, and

tQH(tQH=tHP-tQHS). The data valid window der-

ates in direct proportion to the clock duty cycle

and a practical data valid window can be derived.

18. tJIT specification is currently TBD.

19. MIN( tCL, tCH) refers to the smaller of the actual

clock low time and the actual clock high time as

provided to the device (i.e. this value can be

greater than the minimum specification limits for

tCL and tCH). For example, tCL and tCH are = 50

percent of the period, less the half period jitter

Output

(VOUT)Reference

Point

25Ω

VTT = VDDQ/2

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[tJIT(HP)] of the clock source, and less the half

period jitter due to cross talk [tJIT(cross talk)] into

the clo ck traces.

20. tHP (MIN) is the lesser of tCL minimum and tCH

minimum actually applied to the device CK and

CK# inputs .

21. READs and WRITEs with auto precharge are

allowed to be issued before tRAS (MIN) is satisfied

since tRAS lockout feature is supported in DDR2

SDRAM.

22. VIL/VIH DDR2 overshoot/undershoot. See “AC

Overshoot/Un dershoot Sp ecification” on page 79.

23. tDAL = (nWR) + (tRP/tCK): For each of the terms

above, if not already an integer, round to the next

highes t inte ger. tCK refers t o the app licat ion c lock

period; nWR refers to th e tWR p aram eter st ored in

the MR[11,10,9] . Example: For -37E at tCK = 3.75

ns wit h tWR programmed to fo ur clocks. tDAL = 4

+ (15 ns/3.75 ns) clocks = 4 +(4)cl ocks = 8 clocks.

24. This is a minimum requirement. Minimum READ

to internal PRECHARGE timing is AL + BL/2 pro-

viding the tRTP and tRAS (MIN) have been satis-

fied. The DDR2 SDRAM will automatically delay

the internal PRECHARGE command until tRAS

(MIN) has been satisfied.

25. Operating frequency is only allowed to change

during self refresh mode (See “Self Refresh” on

page54), precharge power-down mode (See

“Power-Down Mode” on page 56), and system

reset condition (see “RESET Function (CKE LOW

Anytime)” on page 64.

26. OD T tu r n -o n ti me tAON (MIN) is when the device

leaves high impedance and ODT resistance

begins to turn on. ODT turn-on time tAO N ( MA X)

is when the ODT resistance is fully on. Both are

measured from tAOND.

27. ODT turn-off time tAOF (MIN) is when the device

starts to turn off ODT resistance. ODT turn off

time tAOF (MAX) is when the bus is in high

impedance. Both are measured from tAOFD.

28. This parameter has a two clock minimum require-

ment at any tCK.

29. tDELAY is calculated from tIS + tCK + tIH so that

CKE registration LOW is guaranteed prior to CK,

CK# being removed in a system RESE T condition.

See “RESET Function (CKE LOW Anytime)” on

page 64.

30. tISXR is equal to tIS and is used for CKE setup time

during self refresh exit shown in Figure 43 on

page 54.

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8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

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All other trademarks are the property of their respective owners.

Figure 77: Package Drawing (x4,x8,x16 Configurations) 11mm x 19mm “FT” FBGA

NOTE:

All dimensions are in millimeters.

Data Sheet Designation

Preliminary: Initial characterization limits, subject

to change upon full characterization of production

devices.

BALL A1 ID

SUBSTRATE: PLASTIC LAMINATE

MOLD COMPOUND: EPOXY NOVOLAC

SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb

OR 62% Sn, 36% Pb, 2% Ag

SOLDER BALL PAD: Ø 0.33mm

SEATING PLANE

0.850 ±0.075

BALL A9

SOLDER BALL DIAMETER

REFERS TO POST REFLOW

CONDITION. THE PRE-

REFLOW DIAMETER

IS Ø 0.40.

0.08 C C

0.100 ±0.013

0.80

TYP

16.00

1.20 MAX

8.00 ±0.05

9.50 ±0.05

1.80 ±0.05

CTR

BALL A1 ID

BALL A1

0.80

TYP

5.50 ±0.053.20 ±0.05

11.00 ±0.10

6.40

0.4592X Ø

19.00 ±0.10