| FAIRCHILD eee SEMICONDUCTOR 74ACT2708 February 1989 Revised January 1999 64 x 9 First-In, First-Out Memory General Description The ACT2708 is an expandable first-in, first-out memory organized as 64 words by 9 bits. An 85 MHz shift-in and 60 MHz shift-out typical data rate makes it ideal for high-speed applications. It uses a dual port RAM architecture with pointer logic to achieve the high speed with negligible fall- through time. Separate Shift-In (Sl) and Shift-Out (SO) clocks control the use of synchronous or asynchronous write or read. Other controls include a Master Reset (MR) and Output Enable (OE) for initializing the internal registers and allowing the data outputs to be 3-STATE. Input Ready (IR) and Output Ready (OR) signal when the FIFO is ready for I/O opera- tions. The status flags HF and FULL indicate when the FIFO is full, empty or half full. The FIFO can be expanded to provide different word lengths by tying off unused data inputs. Features lf 64-words by 9-bit dual port RAM organization M85 Miz shift-in, 60 MHz shift-out data rate, typical i Expandable in word width only HB TTL-compatible inputs lf Asynchronous or synchronous operation lf Asynchronous master reset Hi Outputs source/sink 8 mA @ 3-STATE outputs Mf Full ESD protection Hf Input and output pins directly in line for easy board lay- out lH TRW 1030 work-alike operation Applications * High-speed disk or tape controllers + A/D output buffers * High-speed graphics pixel buffer + Video time base correction Digital filtering Ordering Code: Order Number | Package Number Package Description 74ACT2708PC N28B 28-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering code. Connection Diagram Pin Assignment for DIP FULL J1 4 28 Vee HF {2 27;/- WR IR] 3 26 so si-]4 25F- OR Dy 5 24 0 D6 23F-0, Dp 47 22-0, D; 48 21-0; 49 20; 0, Ds { 10 19 0, Ds J tt 18 05 Dy 412 17-0, Dg 4] 13 16 03 GND | 14 15; OF FACT is a trademark of Fairchild Semiconductor Corporation. Pin Descriptions Pin Names Description Do-Dg Data Inputs MR Master Reset OE Output Enable Input Sl Shift-In so Shift-Out IR Input Ready OR Output Ready HF Half Full Flag FULL Full Flag Op-Og Data Outputs 1999 Fairchild Semiconductor Corporation DSO10144.prf www.fairchildsemi.com AOWASW 1NO-3S.14 Ul-}S4l4 6 X 79 BOZZLOVPZL74ACT2708 Logic Symbol Block Diagram MR Sl so d11 OE Dy D; Dy Dz Dy Ds Dg Dy Dg IR OR HF Og 0, 07 0; Oy Os Og 07 Og FULL Dg ~ Dg INPUT REGISTER Sl so MR IR-- CONTROL . LOGIC OR -+ FLAG LOGIC | HF FULL POINTER CONTROL 64x9 RAM ARRAY OUTPUT REGISTER 3-STATE BUFFER 9 - Oyg www.fairchildsemi.com NoFunctional Description INPUTS Data Inputs (DpDg) Data inputs for 9-bit wide data are TTL-compatible. Word width can be reduced by trying unused inputs to ground and leaving the corresponding outputs open. Reset (MR) Reset is accomplished by pulsing the MR input LOW. Dur- ing normal operation MR is HIGH. A reset is required after power up to guarantee correct operation. On reset, the data outputs go LOW, IR goes HIGH, OR goes LOW, FH and FULL go LOW. During reset, both internal read and write pointers are set to the first location in the array. Shift-In (SI) Data is written into the FIFO by pulsing SI HIGH. When Shift-In goes HIGH, the data is loaded into an internal data latch. Data setup and hold times need to be adhered to with respect to the falling edge of SI. The write cycle is complete after the falling edge of SI. The shift-in is inde- pendent of any ongoing shift-out operation. After the first word has been written into the FIFO, the falling edge of Sl makes HF go HIGH, indicating a non-empty FIFO. The first data word appears at the output after the falling edge of SI. After half the memory is filled, the next rising edge of Sl makes FULL go HIGH indicating a half-full FIFO. When the FIFO is full, any further shift-ins are disabled. When the FIFO is empty and OE is LOW, the falling edge of the first SI will cause the first data word just shifted-in to appear at the output, even though SO may be LOW. Shift-Out (SO) Data is read from the FIFO by the Shift-Out signal provided the FIFO is not empty. SO going HIGH causes OR to go LOW indicating that output stage is busy. On the falling edge of SO, new data reaches the output after propagation delay tp. If the last data has been shifted-out of the mem- ory, OR continues to remain LOW, and the last word shifted-out remains on the output pins. Output Enable (OE) OE LOW enables the 3-STATE output buffers. When OE is HIGH, the outputs are in a 3-STATE mode. OUTPUTS Data Outputs (O,Og) Data outputs are enabled when OE is LOW and in the 3- STATE condition when OE is HIGH. Input Ready (IR) IR HIGH indicates data can be shifted-in. When SI goes HIGH, IR goes LOW, indicating input stage is busy. IR stays LOW when the FIFO is full and goes HIGH after the falling edge of the first shift-out. Output Ready (OR) OR HIGH indicates data can be shifted-out from the FIFO. When SO goes HIGH, OR goes LOW, indicating output stage is busy. OR is LOW when the FIFO is reset or empty and goes HIGH after the falling edge of the first shift-in. Half-Full (HF) This status flag along with the FULL status flag indicates the degree of fullness of the FIFO. On reset, HF is LOW; it rises on the falling edge of the first SI. The rising edge of the SI pulse that fills up the FIFO makes HF go LOW. Going from the empty to the full state with SO LOW, the falling edge of the first Sl causes HF to go HIGH, the rising edge of the 33rd SI causes FULL to go HIGH, and the ris- ing edge of the 64th SI causes HF to go LOW. When the FIFO is full, HF is LOW and the falling edge of the first shift-out causes HF to go HIGH indicating a non- full FIFO. Full Flag (FULL) This status flag along with the HF status flag indicates the degree of fullness of the FIFO. On reset, FULL is LOW. When half the memory is filled, on the rising edge of the next SI, the FULL flag goes HIGH. It remains set until the difference between the write pointer and the read pointer is less than or equal to one-half of the total memory of the device. The FULL flag then goes LOW on the rising edge of the next SO. Status Flags Truth Table HF FULL Status Flag Condition L L Empty L H Full H L <32 Locations Filled H H 232 Locations Filled H = HIGH Voltage Level L = LOW Voltage Level Reset Truth Table Inputs Outputs MR SI SO| IR) OR HF FULL 0 9-0, H xX xX xX xX xX xX L xX xX L L L L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial www.fairchildsemi.com 80Z2L0VPZ74ACT2708 MODES OF OPERATION Mode 1: Shift in Sequence for FIFO Empty to Full Sequence of Operation 1. Input Ready is initially HIGH; HF and FULL flags are LOW. The FIFO is empty and prepared for valid data. OR is LOW indicating that the FIFO is not yet ready to output data. Shift-In is set HIGH, and data is loaded into the FIFO. Data has to be settled t, before the falling edge of SI and held t, after. Input Ready (IR) goes LOW propagation delay ti, after Sl goes HIGH: input stage is busy. Shift-In is set LOW; IR goes HIGH indicating the FIFO is ready for additional data. Data just shifted-in arrives at output propagation delay tops after SI falls. OR goes HIGH propagation delay tor after SI goes LOW, indi- cating the FIFO has valid data on its outputs. HF goes HIGH propagation delay teafter SI falls, indicating the FIFO is no longer empty. The process is repeated through the 64th data word. On the rising edge of the 33rd SI, FULL flag goes HIGH propagation delay typ after SI, indicating a half-full FIFO. HF goes LOW propagation delay tip after the ris- ing edge of the 64th pulse indicating that the FIFO is full. Any further shift-ins are disabled. ist PULSE 33rd PULSE 64th PULSE t SIL | sin . SI \ \ } SJ tale tig i R SJ | \ ' 4, DATA VALID S Dp - Dg ist |) 2nd FS tth ee >| fT 45 FULL 45 the em be tip LC ae ad HF t | 1OR _ CC / S 5 QT tons CC Ss SS ist DATA WORD . 09 ~ 0s Ss 55 Note: SO and OE are LOW; MRis HIGH. FIGURE 1. Modes of Operation Mode 1 www.fairchildsemi.comMode 2: Master Reset Sequence of Operation 1. Input and Output Ready, HF and FULL can be in any state before the reset sequence with Master Reset (MR) HIGH. Master Reset goes LOW and clears the FIFO, setting up all essential internal states. Master Reset must be LOW pulse width typw before rising again. 3. Master Reset rises. trw turiRH OR so HF FULL uRo Sl {WRONL IR rises (if not HIGH already) to indicate ready to write state recovery time typiRH after the falling edge of MR. Both HF and FULL will go LOW indicating an empty FIFO, occurring recovery times tyre and tyro respec- tively after the falling edge of MR. OR falls recovery time tyrorL after MR falls. Data at outputs goes LOW recovery time tyront after MR goes LOW. Shift-In can be taken HIGH after a minimum recovery time tyrsin after MR goes HIGH. tuRsIH FIGURE 2. Mode of Operation Mode 2 www.fairchildsemi.com 80Z2L0VPZ74ACT2708 Mode 3: With FIFO Full, Shift-In is Held HIGH tp. New data is written into the FIFO after SO goes in Anticipation of an Empty Location LOW. Sequence of Operation 3. Input Ready goes HIGH one fall-through time, te7, after 1. The FIFO is initially full and Shift-In goes HIGH. OR is the falling edge of SO. Also, HF goes HIGH one tor initially HIGH. Shift-Out is LOW. IR is LOW. after SO falls, indicating that the FIFO is no longer full. 2. Shift-Out is pulsed HIGH, ShiftOut pulse propagates 4. IR returns LOW pulse width t|p after rising and shifting and the first data word is latched on the rising edge of new data in. Also, HF returns LOW pulse width tsp after SO. OR falls on this edge. On the falling edge of SO, ee : rising, indicating the FIFO is once more full. the second data word appears after propagation delay 5. Shift-In is brought LOW to complete the shift-in process and maintain normal operation. ee en | SI / \ se" Lae tp me tp HF FULL FULL Dy - Dg x NEW DATA x a) Op - Op ist WORD 2nd WORD Note: MR and FULL are HIGH; OE is LOW. FIGURE 3. Modes of Operation Mode 3 www.fairchildsemi.com 6Mode 4: Shift-Out Sequence, FIFO Full to Empty Sequence of Operation 1. FIFO is initially full and OR is HIGH, indicating valid data is at the output. IR is LOW. SO goes HIGH, resulting in OR going LOW one propa- gation delay, tor, after SO rises. OR LOW indicates output stage is busy. SO goes LOW, new data reaches output one propaga- tion delay, tp, after SO falls; OR goes HIGH one propa- gation delay, ton, after SO falls and HF rises one ist PULSE propagation delay, tor, after SO falls. IR rises one fall- through time, try, after SO falls. Repeat process through the 64th SO pulse. FULL flag goes LOW one propagation delay, tour, after the rising edge of 33rd SO, indicating that the FIFO is less than half full. On the falling edge of the 64th SO, HF goes LOW one propagation delay, tog, after SO, indicating the FIFO is empty. The SO pulse may rise and fall again with an attempt to unload an empty FIFO. This results in no change in the data on the outputs as the 64th word stays latched. 33rd PULSE 64th PULSE | 1a SOL tson > PAPAS tor vy /\_/ \ YY VY he /*\_/ \ el tes dF | ty aJ X 2nd word} Op - Og ist WORD tour HL [- 6 IF FULL | tor HF Note: SI and OE are LOW; MR is HIGH; DyDg are immaterial. FIGURE 4. Modes of Operation Mode 4 www.fairchildsemi.com 80Z2L0VPZ74ACT2708 Mode 5: With FIFO Empty, Shift-Out is Held HIGH in Anticipation of Data Sequence of Operation 1. FIFO is initially empty; Shift-Out goes HIGH. 2. Shift-In pulse loads data into the FIFO and IR falls. HF rises propagation delay ty, after the falling edge of SI. 3. OR rises a fall-through time of tpto after the falling edge of Shift-In, indicating that new data is ready to be Data arrives at output one propagation delay, tops, after the falling edge of Shift-In. OR goes LOW pulse width top after rising and HF goes LOW pulse width tyg after rising, indicating that the FIFO is empty once more. Shift-Out goes LOW, necessary to complete the Shift- Out process. output. SI / \ so __/ tto | je \ l+ top OR IR \ / t ODS 09 - Og NEW DATA Dg - Dg + NEW DATA EMPTY HF / EMPTY [st tx 1 pe txd Note: FULL is LOW; MRis HIGH; OE is LOW; tpog = teTo tops: Data output transitionvalid data arrives at output stage tpo after OR is HIGH. FIGURE 5. Modes of Operation Mode 5 www.fairchildsemi.comFIFO Expansion Word Width Expansion Word width can be increased by connecting the corresponding input control signals of multiple devices. Flags can be mon- itored to obtain a composite signal by ANDing the corresponding flags. FULL 1 DIN (0-8) DIN (9-17) FULL 2 Note: AND the corresponding flags to obtain a composite signal. FIGURE 6. Word Width Expansion64 x 18 FIFO OUTPUT y CONTROL ri teat teez | oy DATA out Vino Kx Vo, +0.3V 7) Vmi = 50% Vpp for AC/ACQ devices; 1.5V for ACT/ACTQ devices Vimo = 50% Vpp for AC/ACT, ACQ/ACTQ devices FIGURE 7. 3-STATE Output Low Enable and Disable Times for AC/ACT, ACQ/ACTQ pout (0-8) IR 1 OR 1 HF 4 IRA COMPOSITE IR2 IR OR 1 COMPOSITE OR 2 OR HF 1 COMPOSITE HF 2 HF FULL 1 COMPOSITE IR2 FULL 2 FULL OR2 HF 2 DoUT (9-17) OUTPUT 7 CONTROL mi *ezu toyz | my DATA y Vou Vino Kon 70-3 Vi = 50% Vpp for AC/ACQ devices; 1.5V for ACT/ACTQ devices Vino = 50% Vpp for AC/ACT, ACQ/ACTQ devices FIGURE 8. 3-STATE Output High Enable and Disable Times for AC/ACT, ACQ/ACTQ www.fairchildsemi.com 80Z2L0VPZ74ACT2708 Absolute Maximum Ratingsinote 1) Supply Voltage (Vcc) 0.5V to +7.0V DC Input Diode Current (I)x) Junction Temperature (Tj) PDIP Wis 08N 20m Conditions Vi= Veco + 0.5V +20 mA DC Input Voltage (V)) -0.5VtoVoo +0.5V Supply Voltage (Voc) DC Output Diode Current (lox) Input Voltage (V\) Vo =-0.5V -20 mA Output Voltage (Vo) Vo =Voc + 0.5V +20 mA Operating Ternperature (Ta) DC Output Voltage (Vo) -0.5V to Veg + 0.5V = Minimum Input Edge Rate (AV/At) DC Output Source Vin from 0.8V to 2.0V or Sink Current (Io) +32 mA Voc @ 4.5V, 5.5V DC Voc or Ground Current 140C Recommended Operating 4.5V to 5.5V OV to Voc OV to Voc 40C to +85C 125 mV/ns Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, with- per Output Pin (leg or lanp) +32 mA out exception, to ensure that the system design is reliable over its power Storage Temperature (Tgtq) -65C to +150C DC Electrical Characteristics supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. Symbol Parameter Vee Ta = 25C Ta =40 to +85C Units Conditions (V) Typ aranteed Limits Vin Minimum High Level 45 1.5 2.0 2.0 Vv Vout = 0.1V Input Voltage 5.5 1.5 2.0 2.0 or Veg -0.1V Vit Maximum Low Level 45 1.5 0.8 0.8 Vout = 0.1V Input Voltage 5.5 1.5 0.8 0.8 or Veg -0.1V Vou Minimum High Level 45 449 44 44 Vv lout =50 pA 5.5 5.49 5.4 5.4 Vin= Vit or Vin 45 3.86 3.76 Vv lon =-8 mA 5.5 4.86 4.76 lou =8 mA (Note 2) Voi Maximum Low Level 4.5 0.001 0.1 0.1 v lout = 50 pA Output Voltage 5.5 0.001 0.1 0.1 Vin= Vir or Vin 45 0.36 0.44 Vv lol =8 mA 5.5 0.36 0.44 lo. =8 mA (Note 2) lI Maximum Input 5.5 +0.1 +1.0 pA Vi= Veco, GND loz Maximum 5.5 +0.5 +5.0 pA Vi= Vin Vin 3-STATE Current Vo = Voc, GND loot Maximum Igo/Input 5.5 0.6 1.0 1.5 mA Vi= Veo -2.1V lotp Maximum Dynamic 5.5 32 mA VoLp = 1.65V Toup _| Output Current (Note 3) 5.5 32 mA | Voup =3.85V loc Maximum Quiescent 5.5 8.0 80 pA Vin= Veco Supply Current or GND loop Supply Current 5.5 125 150 150 mA f=20 MHz 20 MHz Loaded (Note 4) Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 2.0 ms, one output loaded at a time. Note 4: Test load 50 pF, 5002 to ground www.fairchildsemi.com 10AC Electrical Characteristics Veco Ta =+28C Ta =40C to +85C Symbol Parameter (V) C, = 50 pF C_ =50 pF Units (Note 5) Min Typ Max Min Max teLH Propagation Delay, tia 5.0 2.0 6.5 11.0 1.5 12.5 ns Sl to IR tPHL Propagation Delay, tia 5.0 2.0 6.5 11.0 1.5 12.0 ns Sl to IR teLH Propagation Delay, tye 5.0 4.0 10.5 17.0 4.0 19.5 ns Sl to > HF tPHL Propagation Delay, tr 5.0 4.5 10.5 16.5 45 19.5 ns S| to Full Condition teLH Propagation Delay, tie 5.0 4.0 10.0 15.5 4.0 17.5 ns S| to Not Empty teLH Propagation Delay, tion 5.0 4.0 13.5 16.5 4.0 19.0 ns Sl to OR teLH Propagation Delay tyriRy 5.0 3.0 8.5 13.5 3.0 15.5 ns MR to IR tPHL Propagation Delay, tyrorL 5.0 7.0 16.5 25.5 7.0 29.0 ns MR to OR tPHL Propagation Delay, tyro 5.0 3.5 9.0 14.0 3.5 16.0 ns MR to Full Flag tPHL Propagation Delay, tyre 5.0 8.0 17.5 27.5 8.0 30.5 ns MR to HF Flag tPHL Propagation Delay, tyRoNnL 5.0 3.0 9.0 15.0 3.0 17.0 ns MR to O,, LOW teLy Propagation Delay, tp 5.0 6.5 18.5 27.0 6.5 31.0 ns SO to Data Out tpHL Propagation Delay, tp 5.0 6.5 18.5 29.5 6.5 34.5 ns SO to Data Out tPHL Propagation Delay, tour 5.0 3.5 8.5 13.5 3.5 15.5 ns SO to < HF teLH Propagation Delay, tor 5.0 5.0 12.5 19.5 5.0 22.0 ns SO to Not Full teu, teu Propagation Delay, ton 5.0 2.5 7.0 11.5 2.5 13.5 ns SO to OR tpHL Propagation Delay, tog 5.0 3.5 9.5 15.5 3.0 17.5 ns SO to Empty teLH Propagation Delay, tops 5.0 7.0 19.0 30.5 6.0 35.5 ns S| to New Data Out tPHL Propagation Delay, tops 5.0 7.0 19.0 29.5 6.0 34.5 ns S| to New Data Out teLH Propagation Delay, ty, 5.0 3.5 10.0 16.0 2.5 18.0 ns S| to HF tpLy Fall-Through Time, teto 5.0 3.5 13.5 21.0 1.5 24.0 ns Sl to OR tw R Pulse Width, top 5.0 12.5 17.0 26.0 12.5 30.5 ns ll www.fairchildsemi.com 80Z2L0VPZ74ACT2708 AC Electrical Characteristics (continued) Veco Ta = +25C Ta =40C to +85C Symbol Parameter (V) C, =50 pF C_ =50 pF Units (Note 5) Min Typ Max Min Max tw HF Pulse Width, ty3 5.0 14.5 20.5 30.5 14.5 36.5 ns tw IR Pulse Width, tip 5.0 16.5 28.0 43.0 16.5 51.5 ns tw HF Pulse Width, t3- 5.0 17.5 30.0 46.5 17.5 56.0 ns tpLy Fall-Through Times, ter 5.0 6.0 15.0 23.5 2.5 28.0 ns SO to IR tpzL Output Enable 5.0 2.0 6.5 11.0 1.5 12.0 ns OE to O, tpiz Output Disable 5.0 1.5 5.0 8.5 1.5 9.5 ns OE to O, tpzy Output Enable 5.0 2.0 7.0 12.0 1.5 13.0 ns OE to O, tpuz Output Disable 5.0 1.5 7.0 12.0 1.5 13.0 ns OE to O, fg) Maximum $1 5.0 55 85 45 MHz Clock Frequency fso0 Maximum SO 5.0 42 60 35 MHz Clock Frequency Note 5: Voltage Range 5.0 is 5.0V+0.5V AC Operating Requirements Vee Ta =+28C Ta =40C to +85C Symbol Parameter (V) C, = 50 pF C, =50 pF Units (Note 6) Typ Guaranteed Minimum tyw(H) SI Pulse Width, tgiy 5.0 3.5 6.5 75 ns tw(L) SI Pulse Width, tgy_ 5.0 6.0 10.0 12.0 ns ts Setup Time, HIGH or 5.0 1.0 3.5 45 ns LOW, D, to SI ty Hold Time, HIGH or 5.0 1.5 3.5 45 ns LOW, D, to SI tw MR Pulse Width, turw 5.0 13.0 20.0 24.5 ns trec Recovery Time, tyrsin 5.0 45 7.5 8.5 ns MR to SI tyw(H) SO Pulse Width, tgoy 5.0 75 6.5 8.0 ns tw(L) SO Pulse Width, tgo. 5.0 9.0 14.0 17.0 ns Note 6: Voltage Range 5.0 is 5.0V + 0.5V Capacitance Symbol Parameter Typ Units Conditions Cn Input Capacitance 45 pF Voc = OPEN Cpp Power Dissipation Capacitance 20.0 pF Voc =5.0V www.fairchildsemi.com 12Physical DimensiONS inches (millimeters) unless otherwise noted Pal el el a) ll Gf fl | 0.510+0.005 J (12.95 + 0.127) ~ 0.062 (1.575) PIN NO. 1 IDENT: HET E OE Ee 1.393-1.420 0.030 0.6000.620 0.1450.210 ~~ MAX + Se (0.762) (15,24 15.78) (3.683 5.334) Y is + 0.009 0.015 Tt (0.229-0.381) 0.580 MIN 0.050 + 0.015 14,73] (14.73) (1.2700.381) be 0.625 + 9-925 "* 0.015 +-| 635 (15.00) Sm) (35,38 36.07) 0.050 TYP = mmm gaa - 0.020 MIN rT (0.508) 86 94 TYP 0.100 0.010 0.018+ 0.003 r ere | oo 0,125 -0.145 (2.540 + 0.254) (0.457 + 0.076) (3.175 3.683) N28B REV E} 28-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.600 Wide Package Number N28B LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. Accritical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com Faircrild does not assume any responsibility for use of any circuitry described, no drcuit patent licanses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. AOWASW 1NO-3S.14 Ul-}S4l4 6 X 79 BOZZLOVPZL