TPS2100, TPS2101
VAUX POWER-DISTRIBUTION SWITCHES
SLVS197D – JUNE 1999 – REVISED JUNE 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
features
D
Dual-Input, Single-Output MOSFET Switch
With No Reverse Current Flow (No Parasitic
Diodes)
D
IN1 . . . 250-mΩ, 500-mA N-Channel;
16-µA Max Supply Current
D
IN2 . . . 1.3-Ω, 10-mA P-Channel;
1.5-µA Max Supply Current (VAUX Mode)
D
Advanced Switch Control Logic
D
CMOS- and TTL-Compatible Enable Input
D
Controlled Rise, Fall, and Transition Times
D
2.7-V to 4 V Operating Range
D
SOT-23-5 and SOIC-8 Package
D
–40°C to 70°C Ambient Temperature Range
D
2-kV Human-Body-Model, 750-V CDM,
200-V Machine-Model Electrostatic-
Discharge Protection
typical applications
D
Notebook and Desktop PCs
D
Palmtops and PDAs
description
The TPS2100 and TPS2101 are dual-input, single-output power switches designed to provide uninterrupted
output voltage when transitioning between two independent power supplies. Both devices combine one
n-channel (250 mΩ) and one p-channel (1.3 Ω) MOSFET with a single output. The p-channel MOSFET (IN2)
is used with auxiliary power supplies that deliver lower current for standby modes. The n-channel MOSFET
(IN1) is used with a main power supply that delivers higher current required for normal operation. Low
on-resistance makes the n-channel the ideal path for higher main supply current when power-supply regulation
and system voltage drops are critical. When using the p-channel MOSFET, quiescent current is reduced to
0.75 µA to decrease the demand on the standby power supply. The MOSFETs in the TPS2100 and TPS2101
do not have the parasitic diodes, found in discrete MOSFETs, which allow the devices to prevent back-flow
current when the switch is off.
DBV PACKAGE
(TOP VIEW)
GND
IN2
IN1
OUT
EN
GND
IN2
IN1
OUT
EN
DBV PACKAGE
(TOP VIEW)
TPS2100
TPS2101
NC – No internal connection
Figure 2. VAUX CardBus Implementation
PCI12xx / PCI14xx
CardBus Controller
PCI Bus VAUX 3.3 V
VGA TPS210x
VCC D3-STAT
1
2
3
4
8
7
6
5
IN2
GND
EN
NC
OUT
OUT
NC
IN1
D PACKAGE
(TOP VIEW)
D PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
IN2
GND
EN
NC
OUT
OUT
NC
IN1
1
2
3
5
4
1
2
3
5
4
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Figure 1. Typical Dual-Input Single-Output
Application
TPS2100
IN1
IN2
EN
3.3 V VCC
3.3 V VAUX
D3 or PME Status
Control Signal Hold-Up
Capacitor
Controller
(CardBus,
1394,
PCI,
et al.)
3.3 V
TPS2100, TPS2101
VAUX POWER-DISTRIBUTION SWITCHES
SLVS197D – JUNE 1999 – REVISED JUNE 2000
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
AVAILABLE OPTIONS
PACKAGED DEVICES
TJDEVICE ENABLE SOT-23-5
(DBV)†SOIC-8
(D)
40
°
C to 85
°
C
TPS2100 EN TSP2100DBV†TPS2100D
–
40°C
to
85°C
TPS2101 EN TPS2101DBV†TPS2101D
Both packages are available left-end taped and reeled. Add an R suffix to the D device type
(e.g., TPS2101DR).
†Add T (e.g., TPS2100DBVT) to indicate tape and reel at order quantity of 250 parts.
Add R (e.g., TPS2100DBVR) to indicate tape and reel at order quantity of 3000 parts.
TPS2100 functional block diagram
VCC
Select
Charge
Pump
Driver
GND
OUT
SW2
1.3 Ω
SW1
250 mΩ
Pullup
Circuit
Driver
IN1
EN
IN2
Discharge
Circuit
TPS2101 functional block diagram
VCC
Select
Charge
Pump
Driver
GND
OUT
SW2
1.3 Ω
SW1
250 mΩ
Driver
IN1
EN
IN2
Pulldown
Circuit
Discharge
Circuit
TPS2100, TPS2101
VAUX POWER-DISTRIBUTION SWITCHES
SLVS197D – JUNE 1999 – REVISED JUNE 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Function Tables
TPS2100 TPS2101
VIN1 VIN2 EN OUT VIN1 VIN2 EN OUT
0 V 0 V XX GND 0 V 0 V XX GND
0 V 3.3 V L GND 0 V 3.3 V H GND
3.3 V 3.3 V L VIN1 3.3 V 3.3 V H VIN1
3.3 V 0 V L VIN1 3.3 V 0 V H VIN1
0 V 3.3 V H VIN2 0 V 3.3 V L VIN2
3.3 V 0 V H VIN2 3.3 V 0 V L VIN2
3.3 V 3.3 V H VIN2 3.3 V 3.3 V L VIN2
XX = don’t care
Terminal Functions
TERMINAL
NO.
DESCRIPTION
NAME TPS2100 TPS2101 I/O
DESCRIPTION
DBV D DBV D
EN 1 3 Active-high enable for IN1-OUT switch
EN 1 3 I Active-low enable for IN1-OUT switch
GND 2 2 2 2 I Ground
IN1 5 5 5 5 I Main Input voltage, NMOS drain (250 mΩ)
IN2 3 1 3 1 I Auxilliary input voltage, PMOS drain (1.3 Ω)
OUT 4 7, 8 47, 8 OPower switch output
NC 4, 6 4, 6 No connection
detailed description
power switches
n-channel MOSFET
The IN1-OUT n-channel MOSFET power switch has a typical on-resistance of 250 mΩ at 3.3-V input voltage,
and is configured as a high-side switch.
p-channel MOSFET
The IN2-OUT p-channel MOSFET power switch with typical on-resistance of 1.3 Ω at 3.3-V input voltage and
is configured as a high-side switch. When operating, the p-channel MOSFET quiescent current is reduced to
less than 1.5 µA.
charge pump
An internal charge pump supplies power to the driver circuit and provides the necessary voltage to pull the gate
of the MOSFET above the source. The charge pump operates from input voltages as low as 2.7 V and requires
very little supply current.
driver
The driver controls the gate voltage of the IN1-OUT and IN2-OUT power switches. To limit large current surges
and reduce the associated electromagnetic interference (EMI) produced, the drivers incorporate circuitry that
controls the rise times and fall times of the output voltage.
TPS2100, TPS2101
VAUX POWER-DISTRIBUTION SWITCHES
SLVS197D – JUNE 1999 – REVISED JUNE 2000
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description (continued)
enable
The logic enable will turn on the IN2-OUT power switch when a logic high is present on EN (TPS2100) or logic
low is present on EN (TPS2101). A logic low input on EN (TPS2100) or logic high on EN (TPS2101) restores
bias to the drive and control circuits and turns on the IN1-OUT power switch. The enable input is compatible
with both TTL and CMOS logic levels.
the VAUX application for CardBus controllers
The PC Card specification requires the support of VAUX to the CardBus controller as well as to the PC Card
sockets. Both are 3.3-V requirements; however the CardBus controller’s current demand from the V AUX supply
is limited to 10 µA, whereas the PC Card may consume as much as 200 mA. In either implementation, if support
of a wake-up event is required, the controller and the socket will transition from the 3.3-V VCC rail to the 3.3-V
VAUX rail when the equipment moves into a low power mode such as D3. The transition from VCC to VAUX needs
to be seamless in order to maintain all memory and register information in the system. If V AUX is not supported,
the system will lose all register information when it transitions to the D3 state.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Input voltage range, VI(IN1) (see Note1) –0.3 V to 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI(IN2) (see Note1) –0.3 V to 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI at EN or EN –0.3 V to 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) –0.3 V to 5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO(IN1) 700 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO(IN2) 70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See dissipation rating table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, TJ –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . .
Electrostatic discharge (ESD) protection: Human body model 2 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Machine model 200 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Charged device model (CDM) 750 V. . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTE 1: All voltages are with respect to GND.
DISSIPATION RATING TABLE
PACKAGE TA < 25°C
POWER RATING DERATING F ACTOR
ABOVE TA = 25°CTA = 70°C
POWER RATING TA = 85°C
POWER RATING
DBV 309 mW 3.1 mW/°C170 mW 123 mW
D568 mW 5.7 mW/°C313 mW 227 mW
recommended operating conditions
MIN MAX UNIT
Input voltage, VI(INx) 2.7 4 V
Input voltage, VI at EN and EN 0 4 V
Continuous output current, IO(IN1) 500 mA
Continuous output current, IO(IN2) 10‡mA
Operating virtual junction temperature, TJ–40 85 °C
‡The device can deliver up to 220 mA at IO(IN2). However, operation at the higher current levels will result in greater voltage drop across the device,
and greater voltage droop when switching between IN1 and IN2.
TPS2100, TPS2101
VAUX POWER-DISTRIBUTION SWITCHES
SLVS197D – JUNE 1999 – REVISED JUNE 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating junction temperature range,
VI(IN1) = V(IN2) = 3.3 V, IO = rated current (unless otherwise noted)
power switch
PARAMETER TEST
CONDITIONS†MIN TYP MAX UNIT
IN1 OUT
TJ = 25°C 250
mΩ
rDS( )
On state resistance
IN1
-
OUT
TJ = 85°C 300 375
mΩ
r
DS(on)
On
-
state
resistance
IN2 OUT
TJ = 25°C 1.3
Ω
IN2
-
OUT
TJ = 85°C 1.5 2.1
Ω
†Pulse-testing techniques maintain junction temperature close to ambient termperature; thermal ef fects must be taken into account separately .
enable input (EN and EN)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH High-level input voltage 2.7 V ≤ VI(INx) ≤ 4 V 2 V
VIL Low-level input voltage 2.7 V ≤ VI(INx) ≤ 4 V 0.8 V
II
In
p
ut current
TPS2100 EN = 0 V or EN = VI(INx) –0.5 0.5 µA
I
I
Inp
u
t
c
u
rrent
TPS2101 EN = 0 V or EN = VI(INx) –0.5 0.5 µA
supply current
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
EN = H
,
TJ = 25°C 0.75
µA
TPS2100
EN
H,
IN2 selected –40°C ≤TJ ≤85°C 1.5 µ
A
TPS2100
EN = L
,
TJ = 25°C 10
µA
II
Su
pp
ly current
EN
L,
IN1 selected –40°C ≤TJ ≤85°C 16 µ
A
I
I
S
u
ppl
y
c
u
rrent
EN = L, TJ = 25°C 0.75
µA
TPS2101
,
IN2 selected –40°C ≤TJ ≤85°C 1.5 µ
A
TPS2101
EN = H, TJ = 25°C 10
µA
,
IN1 selected –40°C ≤TJ ≤85°C 16 µ
A
TPS2100, TPS2101
VAUX POWER-DISTRIBUTION SWITCHES
SLVS197D – JUNE 1999 – REVISED JUNE 2000
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics, TJ = 25°C, VI(IN1) = VI(IN2) = 3.3 V (unless otherwise noted)†
PARAMETER TEST CONDITIONS†MIN TYP MAX UNIT
CL = 1 µF, IL = 500 mA 830
IN1-OUT VI(IN2) = 0 CL = 10 µF, IL = 500 mA 840
t
Out
p
ut rise time
()
CL = 1 µF, IL = 10 mA 640
µs
t
r
O
u
tp
u
t
rise
time
CL = 1 µF, IL = 10 mA 5.5 µ
s
IN2-OUT VI(IN1) = 0 CL = 10 µF, IL = 10 mA 70
()
CL = 1 µF, IL = 1 mA 5.5
CL = 1 µF, IL = 500 mA 8
IN1-OUT VI(IN2) = 0 CL = 10 µF, IL = 500 mA 93
tf
Out
p
ut fall time
()
CL = 1 µF, IL = 10 mA 23
µs
t
f
O
u
tp
u
t
fall
time
CL = 1 µF, IL = 10 mA 690 µ
s
IN2-OUT VI(IN1) = 0 CL = 10 µF, IL = 10 mA 6900
()
CL = 1 µF, IL = 1 mA 6900
tPLH
Pro
p
agationdelaytime low to highout
p
ut
IN1-OUT VI(IN2) = 0
CL=10µF
IL=10mA
75
µs
t
PLH
Propagation
dela
y
time
,
lo
w-
to
-
high
o
u
tp
u
t
IN2-OUT VI(IN1) = 0
C
L =
10
µ
F
,
I
L =
10
mA
2µ
s
tPHL
Pro
p
agationdelaytime high to lowout
p
ut
IN1-OUT VI(IN2) = 0
CL=10µF
IL=10mA
3
µs
t
PHL
Propagation
dela
y
time
,
high
-
to
-
lo
w
o
u
tp
u
t
IN2-OUT VI(IN1) = 0
C
L =
10
µ
F
,
I
L =
10
mA
370 µ
s
†All timing parameters refer to Figure 3.
TPS2100, TPS2101
VAUX POWER-DISTRIBUTION SWITCHES
SLVS197D – JUNE 1999 – REVISED JUNE 2000
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
tPLH tPHL
EN or EN
VO
EN or EN
VO
50%
10%
VI
GND
GND
VI90%
50%
90%
10%
VOGND
VI
trtf
Propagation Delay Time, Low-to-High-Level Output Propagation Delay Time, High-to–Low-Level Output
Rise/Fall Time
ton toff
EN or EN
VO
EN or EN
VO
50%
10%
VI
GND
GND
VI
90%
50%
Turn-on T ransition Time Turn-off T ransition Time
WAVEFORMS
OUT
CLIO
LOAD CIRCUIT
Figure 3. Test Circuit and Voltage Waveforms
Table of Timing Diagrams†
FIGURE
Propagation Delay and Rise Time With 0.1-µF Load, IN1 4
Propagation Delay and Rise T ime With 0.1-µF Load, IN2 5
Propagation Delay and Fall T ime With 0.1-µF Load, IN1 6
Propagation Delay and Fall T ime With 0.1-µF Load, IN2 7
Propagation Delay and Rise T ime With 1-µF Load, IN1 8
Propagation Delay and Rise T ime With 1-µF Load, IN2 9
Propagation Delay and Fall T ime With 1-µF Load, IN1 10
Propagation Delay and Fall T ime With 1-µF Load, IN2 11
†W aveforms shown in Figures 4–11 refer to TPS2100 at TJ = 25°C
TPS2100, TPS2101
VAUX POWER-DISTRIBUTION SWITCHES
SLVS197D – JUNE 1999 – REVISED JUNE 2000
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Figure 4. Propagation Delay and Rise Time
With 0.1-µF Load, IN1
EN
(
2 V/div)
t – Time – 250 µs/div
VO
(
2 V/div)
VI(IN1) = 3.3 V
VI(IN2) = 0 V
CL = 0.1 µF
RL = 330 Ω
Figure 5. Propagation Delay and Fall Time
With 0.1-µF Load, IN2
EN
(2 V/div)
t – Time – 1 µs/div
VO
(2 V/div)
VI(IN1) = 0 V
VI(IN2) = 3.3 V
CL = 0.1 µF
RL = 330 Ω
Figure 6. Propagation Delay and Fall Time
With 0.1-µF Load, IN1
EN
(2 V/div)
t – Time – 5 µs/div
VO
(2 V/div)
VI(IN1) = 3.3 V
VI(IN2) = 0 V
CL = 0.1 µF
RL = 330 Ω
Figure 7. Propagation Delay and Fall Time
With 0.1-µF Load, IN2
EN
(2 V/div)
t – Time – 50 µs/div
VO
(2 V/div)
VI(IN1) = 0 V
VI(IN2) = 3.3 V
CL = 0.1 µF
RL = 330 Ω
TPS2100, TPS2101
VAUX POWER-DISTRIBUTION SWITCHES
SLVS197D – JUNE 1999 – REVISED JUNE 2000
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
EN
(2 V/div)
t – Time – 250 µs/div
VO
(2 V/div)
VI(IN1) = 3.3 V
VI(IN2) = 0 V
CL = 1 µF
RL = 330 Ω
Figure 8. Propagation Delay and Rise Time
With 1-µF Load, IN1 Figure 9. Propagation Delay and Rise Time
With 1-µF Load, IN2
EN
(2 V/div)
t – Time – 2.5 µs/div
VO
(2 V/div)
VI(IN1) = 0 V
VI(IN2) = 3.3 V
CL = 1 µF
RL = 330 Ω
Figure 10. Propagation Delay and Fall Time
With 1-µF Load, IN1
EN
(2 V/div)
t – Time – 10 µs/div
VO
(2 V/div)
VI(IN1) = 3.3 V
VI(IN2) = 0 V
CL = 1 µF
RL = 330 Ω
Figure 11. Propagation Delay and Fall Time
With 1-µF Load, IN2
EN
(2 V/div)
t – Time – 250 µs/div
VO
(2 V/div)
VI(IN1) = 0 V
VI(IN2) = 3.3 V
CL = 1 µF
RL = 330 Ω
TPS2100, TPS2101
VAUX POWER-DISTRIBUTION SWITCHES
SLVS197D – JUNE 1999 – REVISED JUNE 2000
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
IN1 Switch Rise T ime vs Output Current 12
IN2 Switch Fall T ime vs Output Current 13
IN1 Switch Fall T ime vs Output Current 14
IN2 Switch Fall T ime vs Output Current 15
Output Voltage Droop vs Output Current When Output Is Switched From IN2 to IN1 16
Inrush Current vs Output Capacitance 17
IN1 Supply Current vs Junction Temperature (IN1 Enabled) 18
IN1 Supply Current vs Junction Temperature (IN1 Disabled) 19
IN2 Supply Current vs Junction Temperature (IN2 Enabled) 20
IN2 Supply Current vs Junction Temperature (IN2 Disabled) 21
IN1-OUT On-State Resistance vs Junction Temperature 22
IN2-OUT On-State Resistance vs Junction Temperature 23
Figure 12
700
650
600
500
0.01 0.1 1 10
– Rise Time –
800
850
IN1 SWTICH RISE TIME
vs
OUTPUT CURRENT
900
100 1000
750
550
CL = 100 µF
CL = 47 µF
CL = 10 µF
CL = 1 µF
CL = 0.1 µF
IO – Output Current – mA
trsµ
VI(IN1) = 3.3 V
VI(IN2) = 0 V
TJ = 25°C
Figure 13
10
1
0.1 0123456
100
IN2 SWTICH RISE TIME
vs
OUTPUT CURRENT
1000
78910
– Rise Time –
CL = 100 µF
CL = 47 µF
CL = 10 µF
CL = 1 µF
CL = 0.1 µF
IO – Output Current – mA
trsµ
VI(IN1) = 0 V
VI(IN2) = 3.3 V
TJ = 25°C
TPS2100, TPS2101
VAUX POWER-DISTRIBUTION SWITCHES
SLVS197D – JUNE 1999 – REVISED JUNE 2000
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 14
100
10
1
0.01 0.1 1 10
1000
IN1 SWITCH FALL TIME
vs
OUTPUT CURRENT
10000
100 1000
– Fall Time –
CL = 100 µF
CL = 47 µF
CL = 10 µF
CL = 1 µF
CL = 0.1 µF
IO – Output Current – mA
tfsµ
VI(IN1) = 3.3 V
VI(IN2) = 0 V
TJ = 25°C
Figure 15
10
1
0.1
0.01 0.1
100
IN2 SWITCH FALL TIME
vs
OUTPUT CURRENT
1000
110
– Output Fall Time – ms
CL = 100 µF
CL = 10 µF
CL = 1 µF
CL = 0.1 µF
IO – Output Current – mA
tf
VI(IN1) = 0 V
VI(IN2) = 3.3 V
TJ = 25°CCL = 47 µF
Figure 16
0.4
0.2
0
0.01 0.1
0.6
0.8
1
110
– Output Voltage Droop – V
OUTPUT VOLTAGE DROOP
vs
OUTPUT CURRENT WHEN OUTPUT
IS SWITCHED FROM IN2 TO IN1
VO
CL = 100 µF
CL = 10 µF
CL = 1 µF
CL = 0.1 µF
IO – Output Current – mA
VI(IN1) = 3.3 V
VI(IN2) = 3.3 V
TJ = 25°C
CL = 47 µF
Figure 17
1
0.6
0.2
00 100 200 300
Inrush Current – A
1.2
1.4
INRUSH CURRENT
vs
OUTPUT CAPACITANCE
1.6
400 500
0.8
0.4
Co – Output Capacitance – µF
VI(IN1) = 3.3 V
VI(IN2) = 0 V
RL = 6.6 Ω
TJ = 25°C
TPS2100, TPS2101
VAUX POWER-DISTRIBUTION SWITCHES
SLVS197D – JUNE 1999 – REVISED JUNE 2000
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 18
10
8
6
–40 –20 0 20 40
– Supply Currenmt –
12
IN1 SUPPLY CURRENT
vs
JUNCTION TEMPERATURE (IN1 ENABLED)
14
60 80 100
ICC Aµ
VI(INx) = 4 V
VI(INx) = 3.3 V
VI(INx) = 2.7 V
TJ Junction Temperature – °C
Figure 19
0.19
0.17
0.15
–40 –20 0 20 40
0.21
0.23
IN1 SUPPLY CURRENT
vs
JUNCTION TEMPERATURE (IN1 DISABLED)
0.25
60 80 100
– Supply Currenmt –ICC Aµ
VI(INx) = 4 V
VI(INx) = 3.3 V
VI(INx) = 2.7 V
TJ Junction Temperature – °C
Figure 20
0.6
0.55
0.5
–40 –20 0 20 40
0.65
0.7
IN2 SUPPLY CURRENT
vs
JUNCTION TEMPERATURE (IN2 ENABLED)
0.75
60 80 100
– Supply Currenmt –ICC Aµ
VI(INx) = 4 V
VI(INx) = 3.3 V
VI(INx) = 2.7 V
TJ Junction Temperature – °C
Figure 21
0.48
0.44
0.4
–40 –20 0 20 40
0.52
0.56
IN2 SUPPLY CURRENT
vs
JUNCTION TEMPERATURE (IN2 DISABLED)
0.6
60 80 100
– Supply Currenmt –ICC Aµ
VI(INx) = 4 V
VI(INx) = 3.3 V
VI(INx) = 2.7 V
TJ Junction Temperature – °C
TPS2100, TPS2101
VAUX POWER-DISTRIBUTION SWITCHES
SLVS197D – JUNE 1999 – REVISED JUNE 2000
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 22
230
205
180
–40 –20 0 20 40
– IN1-OUT On-State resistance –
255
280
IN1-OUT ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
305
60 80 100
ron mΩ
VI(INx) = 4 V
VI(INx) = 3.3 V
VI(INx) = 2.7 V
TJ Junction Temperature – °C
Figure 23
1.25
1
0.75
0.5
–40 –20 0 20 40
1.5
1.75
IN2-OUT ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
2
60 80 100
– IN1-OUT On-State resistance –
ron Ω
VI(INx) = 4 V
VI(INx) = 3.3 V
VI(INx) = 2.7 V
TJ Junction Temperature – °C
APPLICATION INFORMATION
EN
IN1
IN2
OUT
GND
3.3 V VAUX
3.3 V VCC
CardBus or System Controller TPS2100
0.1 µF
0.1 µF0.1 µF xx µF
3.3 V
Figure 24. Typical Application
power supply considerations
A 0.01-µF to 0.1-µF ceramic bypass capacitor between IN and GND, close to the device is recommended. The
output capacitor should be chosen based on the size of the load during the transition of the switch. A 47-µF
capacitor is recommended for 10-mA loads. T ypical output capacitors (xx µF, shown in Figure 24) required for
a given load can be determined from Figure 16 which shows the output voltage droop when output is switched
from IN2 to IN1. The output voltage droop is insignificant when output is switched from IN1 to IN2. Additionally ,
bypassing the output with a 0.01-µF to 0.1-µF ceramic capacitor improves the immunity of the device to
short-circuit transients.
TPS2100, TPS2101
VAUX POWER-DISTRIBUTION SWITCHES
SLVS197D – JUNE 1999 – REVISED JUNE 2000
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
power supply considerations (continued)
switch transition
The n-channel MOSFET on IN1 uses a charge-pump to create the gate-drive voltage, which gives the IN1 switch
a rise time of approximately 1 ms. The p-channel MOSFET on IN2 has a simpler drive circuit that allows a rise
time of approximately 8 µs. Because the device has two switches and a single enable pin, these rise times are
seen as transition times, from IN1 to IN2, or IN2 to IN1, by the output. The controlled transition times help limit
the surge currents seen by the power supply during switching.
thermal protection
Thermal protection provided on the IN1 switch prevents damage to the IC when heavy-overload or short-circuit
faults are present for extended periods of time. The increased dissipation causes the junction temperature to
rise to dangerously high levels. The protection circuit senses the junction temperature of the switch and shuts
it off at approximately 125°C (TJ). The switch remains off until the junction temperature has dropped. The switch
continues to cycle in this manner until the load fault or input power is removed.
undervoltage lockout
An undervoltage lockout function is provided to ensure that the power switch is in the off state at power-up.
Whenever the input voltage falls below approximately 2 V, the power switch quickly turns off. This function
facilitates the design of hot-insertion systems that may not have the capability to turn off the power switch before
input power is removed. Upon reinsertion, the power switch will be turned on with a controlled rise time to reduce
EMI and voltage overshoots.
power dissipation and junction temperature
The low on-resistance on the n-channel MOSFET allows small surface-mount packages, such as SOIC, to pass
large currents. The thermal resistances of these packages are high compared to that of power packages; it is
good design practice to check power dissipation and junction temperature. First, find ron at the input voltage,
and operating temperature. As an initial estimate, use the highest operating ambient temperature of interest and
read ron from Figure 22 or Figure 23. Next calculate the power dissipation using:
PD
+
ron
I2
Finally, calculate the junction temperature:
TJ
+
PD
R
q
JA
)
TA
Where:
TA = Ambient temperature
RθJA = Thermal resistance
Compare the calculated junction temperature with the initial estimate. If they do not agree within a few degrees,
repeat the calculation using the calculated value as the new estimate. Two or three iterations are generally
sufficient to obtain a reasonable answer.
ESD protection
All TPS2100 and TPS2101 terminals incorporate ESD-protection circuitry designed to withstand a 2-kV
human-body-model discharge as defined in MIL-STD-883C.
TPS2100, TPS2101
VAUX POWER-DISTRIBUTION SWITCHES
SLVS197D – JUNE 1999 – REVISED JUNE 2000
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
DBV (R-PDSO-G5) PLASTIC SMALL-OUTLINE
0,10
M
0,20
0,95
0°–8°
0,25
0,35
0,55
Gage Plane
0,15 NOM
4073253-4/E 05/99
2,60
3,00
0,50
0,30
1,50
1,70
45
31
2,80
3,00
0,95
1,45 0,05 MIN
Seating Plane
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-178
TPS2100, TPS2101
VAUX POWER-DISTRIBUTION SWITCHES
SLVS197D – JUNE 1999 – REVISED JUNE 2000
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
4040047/D 10/96
0.228 (5,80)
0.244 (6,20)
0.069 (1,75) MAX 0.010 (0,25)
0.004 (0,10)
1
14
0.014 (0,35)
0.020 (0,51)
A
0.157 (4,00)
0.150 (3,81)
7
8
0.044 (1,12)
0.016 (0,40)
Seating Plane
0.010 (0,25)
PINS **
0.008 (0,20) NOM
A MIN
A MAX
DIM
Gage Plane
0.189
(4,80)
(5,00)
0.197
8
(8,55)
(8,75)
0.337
14
0.344
(9,80)
16
0.394
(10,00)
0.386
0.004 (0,10)
M
0.010 (0,25)
0.050 (1,27)
0°–8°
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).
D. Falls within JEDEC MS-012
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TPS2100DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2100DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2100DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2100DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2101D ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2101DBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2101DBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2101DBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2101DBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2101DG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 7-May-2007
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS2100DBVR SOT-23 DBV 5 3000 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3
TPS2100DBVT SOT-23 DBV 5 250 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3
TPS2101DBVR SOT-23 DBV 5 3000 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3
TPS2101DBVT SOT-23 DBV 5 250 180.0 9.0 3.15 3.2 1.4 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2100DBVR SOT-23 DBV 5 3000 182.0 182.0 20.0
TPS2100DBVT SOT-23 DBV 5 250 182.0 182.0 20.0
TPS2101DBVR SOT-23 DBV 5 3000 182.0 182.0 20.0
TPS2101DBVT SOT-23 DBV 5 250 182.0 182.0 20.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 2
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