Sample & Buy Product Folder Support & Community Tools & Software Technical Documents LM5010A, LM5010A-Q1 SNVS376F - OCTOBER 2005 - REVISED MAY 2016 LM5010A, LM5010A-Q1 High-Voltage 1-A Step-Down Switching Regulator 1 Features 2 Applications * * * * 1 * * * * * * * * * * * * * * LM5010A-Q1 Qualified for Automotive Applications AEC-Q100 Qualified With the Following Results: - Device Temperature Grade 1: -40C to 125C Ambient Operating Temperature Range - Device Temperature Grade 0: -40C to 150C Ambient Operating Temperature Range - Device HBM ESD Classification Level 2 - Device CDM ESD Classification Level C5 Wide 6-V to 75-V Input Voltage Range Valley Current Limit at 1.25 A Programmable Switching Frequency Up To 1 MHz Integrated 80-V N-Channel Buck Switch Integrated High Voltage Bias Regulator No Loop Compensation Required Ultra-Fast Transient Response Nearly Constant Operating Frequency With Line and Load Variations Adjustable Output Voltage 2.5-V, 2% Feedback Reference Programmable Soft-Start Thermal Shutdown Exposed Thermal Pad for Improved Heat Dissipation Non-Isolated Telecommunications Regulators Secondary Side Post Regulators Automotive Electronics 3 Description The LM5010Ax step-down switching regulator is an enhanced version of the LM5010 with the input operating range extended to 6-V minimum. The LM5010Ax features all the functions needed to implement a low-cost, efficient, buck regulator capable of supplying in excess of 1-A load current. This high-voltage regulator integrates an N-Channel Buck Switch, and is available in thermally enhanced 10-pin WSON and 14-pin HTSSOP packages. The constant ON-time regulation scheme requires no loop compensation resulting in fast load transient response and simplified circuit implementation. The operating frequency remains constant with line and load variations due to the inverse relationship between the input voltage and the ON-time. The valley current limit detection is set at 1.25 A. Additional features include: VCC undervoltage lockout, thermal shutdown, gate drive undervoltage lockout, and maximum duty cycle limiter. Device Information(1) PART NUMBER LM5010Ax PACKAGE BODY SIZE (NOM) WSON (10) 4.00 mm x 4.00 mm HTSSOP (14) 4.40 mm x 5.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Basic Step-Down Regulator 6V - 75V Input VCC VIN C3 C1 LM5010A RON BST C4 L1 RON/SD SHUTDOWN VOUT SW D1 SS R1 R3 ISEN C2 C6 FB RTN SGND R2 Copyright (c) 2016, Texas Instruments Incorporated 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LM5010A, LM5010A-Q1 SNVS376F - OCTOBER 2005 - REVISED MAY 2016 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 4 4 4 4 5 5 6 8 Absolute Maximum Ratings ...................................... ESD Ratings: LM5010A ............................................ ESD Ratings: LM5010A-Q1, LM5010-Q0 ................. Recommended Operating Conditions ...................... Thermal Information ................................................. Electrical Characteristics........................................... Switching Characteristics .......................................... Typical Characteristics .............................................. Detailed Description .............................................. 9 7.1 Overview .................................................................. 9 7.2 Functional Block Diagram ......................................... 9 7.3 Feature Description................................................... 9 7.4 Device Functional Modes........................................ 13 8 Application and Implementation ........................ 14 8.1 Application Information............................................ 14 8.2 Typical Application .................................................. 14 8.3 Do's and Don'ts ....................................................... 20 9 Power Supply Recommendations...................... 21 10 Layout................................................................... 21 10.1 Layout Guidelines ................................................. 21 10.2 Layout Example .................................................... 22 11 Device and Documentation Support ................. 23 11.1 11.2 11.3 11.4 11.5 Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 23 23 23 23 23 12 Mechanical, Packaging, and Orderable Information ........................................................... 23 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (February 2013) to Revision F * Page Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .................................................................................................. 1 Changes from Revision D (February 2013) to Revision E * 2 Page Changed layout of National Data Sheet to TI format ............................................................................................................. 1 Submit Documentation Feedback Copyright (c) 2005-2016, Texas Instruments Incorporated Product Folder Links: LM5010A LM5010A-Q1 LM5010A, LM5010A-Q1 www.ti.com SNVS376F - OCTOBER 2005 - REVISED MAY 2016 5 Pin Configuration and Functions DPR Package 10-Pin WSON Top View PWP Package 14-Pin HTSSOP Top View SW 1 10 VIN NC 1 14 NC BST 2 9 VCC SW 2 13 VIN I SEN 3 8 R BST 3 12 VCC 4 7 SS I SEN 4 11 R 5 6 FB 5 10 SS RTN 6 9 FB NC 7 8 NC S GND RTN ExposedPad ON /SD S GND ExposedPad ON /SD Pin Functions PIN NAME I/O DESCRIPTION WSON HTSSOP BST 2 3 I EP -- -- -- FB 6 9 I Voltage feedback input from the regulated output: Input to both the regulation and overvoltage comparators. The FB pin regulation level is 2.5 V. ISEN 3 4 I Current sense: During the buck switch OFF-time, the inductor current flows through the internal sense resistor, and out of the ISEN pin to the free-wheeling diode. The current limit comparator keeps the buck switch off if the ISEN current exceeds 1.25 A (typical). NC -- 1, 7, 8, 14 -- RON/SD 8 11 I RTN 5 6 -- Circuit ground: Ground return for all internal circuitry other than the current sense resistor. SGND 4 5 -- Sense ground: Recirculating current flows into this pin to the current sense resistor. SS 7 10 I Soft start: An internal 11.5-A current source charges the SS pin capacitor to 2.5 V to softstart the reference input of the regulation comparator. SW 1 2 O Switching node: Internally connected to the buck switch source. Connect to the inductor, free-wheeling diode, and bootstrap capacitor. Boost pin for bootstrap capacitor: Connect a capacitor from SW to the BST pin. The capacitor is charged from VCC through an internal diode during the buck switch OFFtime. Exposed pad No connection. Can be connected to ground plane to improve heat dissipation. ON-time control and shutdown: An external resistor from VIN to this pin sets the buck switch ON-time. Grounding this pin shuts down the regulator. VCC 9 12 I Output of the bias regulator: The voltage at VCC is nominally equal to VIN for VIN < 8.9 V, and regulated at 7 V for VIN > 8.9 V. Connect a 0.47-F, or larger capacitor from VCC to ground, as close as possible to the pins. An external voltage can be applied to this pin to reduce internal dissipation if VIN is greater than 8.9 V. MOSFET body diodes clamp VCC to VIN if VCC > VIN. VIN 10 13 I Input supply: Nominal input range is 6 V to 75 V. Input bypass capacitors should be located as close as possible to the VIN pin and RTN pin. Copyright (c) 2005-2016, Texas Instruments Incorporated Product Folder Links: LM5010A LM5010A-Q1 Submit Documentation Feedback 3 LM5010A, LM5010A-Q1 SNVS376F - OCTOBER 2005 - REVISED MAY 2016 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT 6 75 V VIN to RTN -0.3 76 V BST to RTN -0.3 90 V -1.5 V BST to VCC 76 V BST to SW 14 V VIN SW to RTN (steady state) VCC to RTN -0.3 14 V SGND to RTN -0.3 0.3 V SS to RTN -0.3 4 V 76 V 7 V VIN to SW All other inputs to RTN -0.3 Lead temperature (soldering, 4 sec) (2) 260 C Junction temperature (LM5010A, Q1,Q0) -40 150 C Storage temperature, Tstg -65 150 C (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions . Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. For detailed information on soldering plastic HTSSOP and WSON packages, see Mechanical, Packaging, and Orderable Information. 6.2 ESD Ratings: LM5010A VALUE V(ESD) (1) (2) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) UNIT 2000 Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) V 750 JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 ESD Ratings: LM5010A-Q1, LM5010-Q0 VALUE V(ESD) (1) (2) (3) Electrostatic discharge Human-body model (HBM), per AEC Q100-002 (1) (2) UNIT 2000 Charged-device model (CDM), per AEC Q100-011 (3) V 750 AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. Level listed above is the passing level per ANSI/ESDA/JEDEC JS-001. JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process. Level listed above is the passing level per EIA-JEDEC JESD22-C101. JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process. 6.4 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VIN Input voltage IO Output current Ext-VCC TJ (1) 4 External bias voltage NOM 6 (1) Operating junction temperature MAX UNIT 75 V 1 A 8 13 V LM5010A -40 125 C LM5010A-Q1, LM5010-Q0 -40 150 C VCC provides bias for the internal gate drive and control circuits. Device thermal limitations limit external loading. Submit Documentation Feedback Copyright (c) 2005-2016, Texas Instruments Incorporated Product Folder Links: LM5010A LM5010A-Q1 LM5010A, LM5010A-Q1 www.ti.com SNVS376F - OCTOBER 2005 - REVISED MAY 2016 6.5 Thermal Information LM5010A, LM5010A-Q1 THERMAL METRIC (1) DPR (WSON) PWP (HTSSOP) 10 PINS 14 PINS UNIT 36 41.1 C/W RJA Junction-to-ambient thermal resistance RJC(top) Junction-to-case (top) thermal resistance 31.9 26.5 C/W RJB Junction-to-board thermal resistance 13.2 22.5 C/W JT Junction-to-top characterization parameter 0.3 0.7 C/W JB Junction-to-board characterization parameter 13.5 22.2 C/W RJC(bot) Junction-to-case (bottom) thermal resistance 3 3.3 C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. 6.6 Electrical Characteristics Typical values correspond to TJ = 25C, minimum and maximum limits apply over TJ = -40C to 125C, VIN = 48 V, and RON = 200 k (unless otherwise noted). (1) PARAMETER TEST CONDITIONS MIN TYP MAX 6.6 7 7.4 UNIT VCC REGULATOR VCCReg VCC regulated output V VIN - VCC ICC = 0 mA, FS < 200 kHz, 6 V VIN 8.5 V 100 mV VCC Bypass threshold VIN increasing 8.9 V VCC Bypass hysteresis VIN decreasing 260 mV VIN = 6 V VCC Output impedance (0 mA ICC 5 mA) 55 VIN = 8 V VCC Current limit 0.21 VIN = 48 V, VCC = 0 V UVLOVCC VCC undervoltage lockout threshold 50 VIN = 48 V 15 mA VCC increasing 5.25 V UVLOVCC hysteresis VCC decreasing 180 mV UVLOVCC filter delay 100 mV overdrive IIN Operating current Non-switching, FB = 3 V 675 950 A IIN Shutdown current RON/SD = 0 V 100 200 A 8 11.5 15 A 1 1.25 1.5 A 3 s SOFT-START PIN ISS Internal current source CURRENT LIMIT ILIM Threshold Current out of ISEN Resistance from ISEN to SGND 130 m Response time 150 ns ON TIMER, RON/SD PIN Shutdown threshold Voltage at RON/SD rising 0.3 Threshold hysteresis 0.7 1.05 40 V mV REGULATION AND OVER-VOLTAGE COMPARATORS (FB PIN) VREF FB regulation threshold TJ 125C 2.445 TJ 150C, over full operating junction temperature range 2.435 2.5 2.55 V 2.44 FB overvoltage threshold FB bias current (1) 2.9 V 1 nA All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control. Copyright (c) 2005-2016, Texas Instruments Incorporated Product Folder Links: LM5010A LM5010A-Q1 Submit Documentation Feedback 5 LM5010A, LM5010A-Q1 SNVS376F - OCTOBER 2005 - REVISED MAY 2016 www.ti.com Electrical Characteristics (continued) Typical values correspond to TJ = 25C, minimum and maximum limits apply over TJ = -40C to 125C, VIN = 48 V, and RON = 200 k (unless otherwise noted).(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT THERMAL SHUTDOWN Thermal shutdown temperature TSD Thermal shutdown hysteresis 175 C 20 C 6.7 Switching Characteristics Typical values correspond to TJ = 25C, minimum and maximum limits apply over TJ = -40C to 125C, and VIN = 48 V (unless otherwise noted) (1) PARAMETER TEST CONDITIONS MIN TJ 125C RDS(ON) Buck switch ISW = 200 mA UVLOGD Gate drive UVLO VBST - VSW increasing TYP MAX 0.35 0.8 TJ 150C, over full operating junction temperature range 0.85 1.7 UVLOGD Hysteresis 3 4 UNIT V 400 mV 260 ns OFF TIMER tOFF Minimum OFF-time ON TIMER tON - 1 ON-time VIN = 10 V, RON = 200 k 2.1 2.75 3.4 s tON - 2 ON-time VIN = 75 V, RON = 200 k 290 390 496 ns (1) 6 All minimum and maximum limits are specified by correlating the electrical characteristics to process and temperature variations while applying statistical process control. Submit Documentation Feedback Copyright (c) 2005-2016, Texas Instruments Incorporated Product Folder Links: LM5010A LM5010A-Q1 LM5010A, LM5010A-Q1 www.ti.com SNVS376F - OCTOBER 2005 - REVISED MAY 2016 VIN 7.0V UVLO VCC SW Pin Inductor Current 2.5V SS Pin VOUT t2 t1 Figure 1. Start-Up Sequence Copyright (c) 2005-2016, Texas Instruments Incorporated Product Folder Links: LM5010A LM5010A-Q1 Submit Documentation Feedback 7 LM5010A, LM5010A-Q1 SNVS376F - OCTOBER 2005 - REVISED MAY 2016 www.ti.com 6.8 Typical Characteristics at TA = 25C (unless otherwise noted) 10 8 VIN = 8V 7 8.0 VCC (V) VCC (V) VIN = 6V 5 6.0 4.0 4 VCC UVLO 3 2 ICC = 0 mA 2.0 VCC Externally Loaded 1 0 FS = 400 kHz 0 0 1 2 3 4 5 6 7 8 9 10 0 3 6 9 12 15 ICC (mA) VIN (V) Figure 2. VCC vs VIN Figure 3. VCC vs ICC 10 100 9 FS = 700 kHz 8 FS = 400 kHz 7 ON-TIME (Ps) ICC INPUT CURRENT(mA) VIN = 48V VIN = 9V 6 6 5 4 FS = 80 kHz 3 10 RON = 500k 300k 1.0 100k 2 VIN = 48V 1 0.1 0 7 8 9 10 11 12 13 0 6 14 20 40 60 80 VIN (V) EXTERNALLY APPLIED VCC (V) Figure 5. ON-Time vs VIN and RON Figure 4. ICC vs Externally Applied VCC 1000 4.0 800 3.0 700 FB = 3V 115k IIN (PA) RON/SD PIN VOLTAGE (V) 900 RON = 50k 301k 2.0 511k 600 500 400 300 1.0 200 RON/SD = 0V 100 0 0 0 6 20 40 60 80 0 6 VIN (V) Submit Documentation Feedback 40 60 80 VIN (V) Figure 7. IIN vs VIN Figure 6. Voltage at RON/SD Pin 8 20 Copyright (c) 2005-2016, Texas Instruments Incorporated Product Folder Links: LM5010A LM5010A-Q1 LM5010A, LM5010A-Q1 www.ti.com SNVS376F - OCTOBER 2005 - REVISED MAY 2016 7 Detailed Description 7.1 Overview The LM5010Ax step-down switching regulator features all the functions needed to implement a low-cost, efficient, buck bias power converter. This high-voltage regulator contains a 75-V N-channel buck switch, is easy to implement, and is provided in HTSSOP-14 and thermally-enhanced, WSON-10 packages. The regulator is based on a control scheme using an ON-time inversely proportional to VIN. The control scheme requires no loop compensation. The functional block diagram of the LM5010Ax is shown in the Functional Block Diagram. The LM5010Ax can be applied in numerous applications to efficiently regulate down higher voltages. This regulator is well-suited for 48-V telecom and 42-V automotive power bus ranges. Additional features include: thermal shutdown, VCC undervoltage lockout, gate drive undervoltage lockout, maximum duty cycle limit timer, and the valley current limit functionality. 7.2 Functional Block Diagram Input 6V-75V LM5010A 7V BIAS REGULATOR VIN VIN SENSE C1 C5 VCC Q2 UVL BYPASS SWITCH VCC THERMAL SHUTDOWN C3 BST Gate Drive UVLO GND RON 0.7V 260 ns OFF TIMER START ON TIMER START RON COMPLETE RON/SD COMPLETE SD VIN C4 Q1 LEVEL SHIFT L1 DRIVER SW Shutdown Input Driver D1 CURRENT LIMIT COMPARATOR 2.5V 62.5 mV 11.5 PA SS RCL RSENSE (optional) 50 m: + SGND R1 2.9V C6 VOUT ISEN LOGIC R3 FB OVER-VOLTAGE COMPARATOR C2 R2 RTN REGULATION COMPARATOR GND Copyright (c) 2016, Texas Instruments Incorporated 7.3 Feature Description 7.3.1 Control Circuit Overview The LM5010Ax employs a control scheme based on a comparator and a one-shot ON timer, with the output voltage feedback (FB) compared to an internal reference (2.5 V). If the FB voltage is below the reference the buck switch is turned on for a time period determined by the input voltage and a programming resistor (RON). Following the ON-time the switch remains off for a fixed 260 ns OFF-time, or until the FB voltage falls below the reference, whichever is longer. The buck switch then turns on for another ON-time period. Referring to the Block Diagram, the output voltage is set by R1 and R2. The regulated output voltage is calculated with Equation 1. VOUT = 2.5 V x (R1 + R2) / R2 (1) The LM5010Ax requires a minimum of 25 mV of ripple voltage at the FB pin for stable fixed-frequency operation. If the output capacitor's ESR is insufficient, additional series resistance may be required (R3 in the Block Diagram). Copyright (c) 2005-2016, Texas Instruments Incorporated Product Folder Links: LM5010A LM5010A-Q1 Submit Documentation Feedback 9 LM5010A, LM5010A-Q1 SNVS376F - OCTOBER 2005 - REVISED MAY 2016 www.ti.com Feature Description (continued) The LM5010Ax operates in continuous conduction mode at heavy load currents, and discontinuous conduction mode at light load currents. In continuous conduction mode current always flows through the inductor, never decaying to zero during the OFF-time. In this mode the operating frequency remains relatively constant with load and line variations. The minimum load current for continuous conduction mode is one-half the inductor's ripple current amplitude. Calculate the operating frequency in the continuous conduction mode with Equation 2. FS = VOUT x (VIN 1.4V) 1.18 x 10 -10 x (RON + 1.4 k:) x VIN (2) The buck switch duty cycle is equal to Equation 3. DC = VOUT tON tON + tOFF = tON x FS = VIN (3) Under light load conditions, the LM5010Ax operates in discontinuous conduction mode, with zero current flowing through the inductor for a portion of the OFF-time. The operating frequency is always lower than that of the continuous conduction mode, and the switching frequency varies with load current. Conversion efficiency is maintained at a relatively high level at light loads because the switching losses diminish as the power delivered to the load is reduced. Calculate the discontinuous mode operating frequency with Equation 4. FS = VOUT2 x L1 x 1.4 x 1020 RL x RON 2 where * RL is the load resistance (4) 7.3.2 Start-Up Regulator (VCC) A high voltage bias regulator is integrated within the LM5010Ax. The input pin (VIN) can be connected directly to line voltages between 6 and 75 V. Referring to the block diagram and the graph of VCC vs VIN, when VIN is between 6 V and the bypass threshold (nominally 8.9 V), the bypass switch (Q2) is on, and VCC tracks VIN within 100 mV to 150 mV. The bypass switch on-resistance is approximately 50 , with inherent current limiting at approximately 100 mA. When VIN is above the bypass threshold, Q2 is turned off, and VCC is regulated at 7 V. The VCC regulator output current is limited at approximately 15 mA. When the LM5010Ax is shutdown using the RON/SD pin, the VCC bypass switch is shut off, regardless of the voltage at VIN. When VIN exceeds the bypass threshold, the time required for Q2 to shut off is approximately 2 to 3 s. The capacitor at VCC (C3) must be a minimum of 0.47 F to prevent the voltage at VCC from rising above its absolute maximum rating in response to a step input applied at VIN. C3 must be located as close as possible to the LM5010Ax pins. In applications with a relatively high input voltage, power dissipation in the bias regulator is a concern. An auxiliary voltage of between 7.5 V and 14 V can be diode connected to the VCC pin (D2 in Figure 8) to shut off the VCC regulator, reducing internal power dissipation. The current required into the VCC pin is shown in the Typical Performance Characteristics. Internally a diode connects VCC to VIN requiring that the auxiliary voltage be less than VIN. The turn-on sequence is shown in Figure 1. When VCC exceeds the undervoltage lockout threshold (UVLO) of 5.25 V (t1 in Figure 1), the buck switch is enabled, and the SS pin is released to allow the soft-start capacitor (C6) to charge up. The output voltage VOUT is regulated at a reduced level which increases to the desired value as the soft-start voltage increases (t2 in Figure 1). 10 Submit Documentation Feedback Copyright (c) 2005-2016, Texas Instruments Incorporated Product Folder Links: LM5010A LM5010A-Q1 LM5010A, LM5010A-Q1 www.ti.com SNVS376F - OCTOBER 2005 - REVISED MAY 2016 Feature Description (continued) VCC C3 BST C4 LM5010A L1 D2 SW VOUT D1 ISEN R1 R3 SGND R2 C2 FB Figure 8. Self Biased Configuration 7.3.3 Regulation Comparator The feedback voltage at the FB pin is compared to the voltage at the SS pin (2.5 V, 2%). In normal operation an ON-time period is initiated when the voltage at FB falls below 2.5 V. The buck switch conducts for the ON-time programmed by RON, causing the FB voltage to rise above 2.5 V. After the ON-time period the buck switch remains off until the FB voltage falls below 2.5 V. Input bias current at the FB pin is less than 5 nA over temperature. 7.3.4 Overvoltage Comparator The feedback voltage at FB is compared to an internal 2.9-V reference. If the voltage at FB rises above 2.9 V the ON-time is immediately terminated. This condition can occur if the input voltage, or the output load, changes suddenly. The buck switch remains off until the voltage at FB falls below 2.5 V. 7.3.5 ON-Time Control The ON-time of the internal buck switch is determined by the RON resistor and the input voltage (VIN), and is calculated with Equation 5. 1.18 x 10 tON = -10 x (RON + 1.4k) (VIN - 1.4V) + 67 ns (5) The RON resistor can be determined from the desired ON-time by re-arranging Equation 5 to Equation 6. RON = (tON - 67 ns) x (VIN - 1.4V) 1.18 x 10 -10 - 1.4 k: (6) To set a specific continuous conduction mode switching frequency (fS), the RON resistor is determined with Equation 7. VOUT x (VIN - 1.4V) RON = -10 - 1.4 k: VIN x FS x 1.18 x 10 (7) In high frequency applications the minimum value for tON is limited by the maximum duty cycle required for regulation and the minimum OFF-time of the LM5010Ax (260 ns, 15%). The fixed OFF-time limits the maximum duty cycle achievable with a low voltage at VIN. The minimum allowed ON-time to regulate the desired VOUT at the minimum VIN is determined with Equation 8. Copyright (c) 2005-2016, Texas Instruments Incorporated Product Folder Links: LM5010A LM5010A-Q1 Submit Documentation Feedback 11 LM5010A, LM5010A-Q1 SNVS376F - OCTOBER 2005 - REVISED MAY 2016 www.ti.com Feature Description (continued) VOUT x 300 ns tON(min) = (VIN(min) VOUT) (8) 7.3.6 Soft Start The soft start feature allows the regulator to gradually reach a steady-state operating point, thereby reducing start-up stresses and current surges. At turnon, while VCC is below the undervoltage threshold (t1 in Figure 1), the SS pin is internally grounded, and VOUT is held at 0 V. When VCC exceeds the undervoltage threshold (UVLO) an internal 11.5-A current source charges the external capacitor (C6) at the SS pin to 2.5 V (t2 in Figure 1). The increasing SS voltage at the non-inverting input of the regulation comparator gradually increases the output voltage from zero to the desired value. The softstart feature keeps the load inductor current from reaching the current limit threshold during start-up, thereby reducing inrush currents. An internal switch grounds the SS pin if VCC is below the undervoltage lockout threshold, or if the circuit is shutdown using the RON/SD pin. 7.3.7 N-Channel Buck Switch and Driver The LM5010Ax integrates an N-Channel buck switch and associated floating high voltage gate driver. The peak current through the buck switch should not exceed 2 A, and the load current should not exceed 1.5 A. The gate driver circuit is powered by the external bootstrap capacitor between BST and SW (C4), which is recharged each OFF-time from VCC through the internal high voltage diode. The minimum OFF-time, nominally 260 ns, ensures sufficient time during each cycle to recharge the bootstrap capacitor. A 0.022-F ceramic capacitor is recommended for C4. 7.3.8 Current Limit Current limit detection occurs during the OFF-time by monitoring the recirculating current through the internal current sense resistor (RSENSE). The detection threshold is 1.25 A, 0.25 A. Referring to Functional Block Diagram, if the current into SGND during the OFF-time exceeds the threshold level the current limit comparator delays the start of the next ON-time period. The next ON-time starts when the current into SGND is below the threshold and the voltage at FB is below 2.5 V. Figure 9 illustrates the inductor current waveform during normal operation and during current limit. The output current IO is the average of the inductor ripple current waveform. The low load current waveform illustrates continuous conduction mode operation with peak and valley inductor currents below the current limit threshold. When the load current is increased (high load current), the ripple waveform maintains the same amplitude and frequency since the current falls below the current limit threshold at the valley of the ripple waveform. Note the average current in the high load current portion of Figure 9 is above the current limit threshold. Since the current reduces below the threshold in the normal OFF-time each cycle, the start of each ON-time is not delayed, and the circuit's output voltage is regulated at the correct value. When the load current is further increased such that the lower peak would be above the threshold, the OFF-time is lengthened to allow the current to decrease to the threshold before the next ON-time begins (Current Limited portion of Figure 9). Both VOUT and the switching frequency are reduced as the circuit operates in a constant current mode. The load current (IOCL) is equal to the current limit threshold plus half the ripple current (I/2). The ripple amplitude (I) is calculated with Equation 9. 'I = (VIN - VOUT) x tON L1 (9) The current limit threshold can be increased by connecting an external resistor (RCL) between SGND and ISEN. RCL typically is less than 1 , and the calculation of its value is explained in Application and Implementation. If the current limit threshold is increased by adding RCL, the maximum continuous load current should not exceed 1.5 A, and the peak current out of the SW pin should not exceed 2 A. 12 Submit Documentation Feedback Copyright (c) 2005-2016, Texas Instruments Incorporated Product Folder Links: LM5010A LM5010A-Q1 LM5010A, LM5010A-Q1 www.ti.com SNVS376F - OCTOBER 2005 - REVISED MAY 2016 Feature Description (continued) IPK IOCL Inductor Current Current Limit Threshold Io 'I High Load Current Low Load Current Current Limited Normal Operation Figure 9. Inductor Current, Current Limit Operation 7.3.9 Thermal Shutdown The LM5010Ax should be operated below the maximum operating junction temperature rating. If the junction temperature increases during a fault or abnormal operating condition, the internal thermal shutdown circuit activates typically at 175C. The Thermal Shutdown circuit reduces power dissipation by disabling the buck switch and the ON timer. This feature helps prevent catastrophic failures from accidental device overheating. When the junction temperature reduces below approximately 155C (20C typical hysteresis), normal operation resumes. 7.4 Device Functional Modes 7.4.1 Shutdown The LM5010Ax can be remotely shut down by forcing the RON/SD pin below 0.7 V with a switch or open drain device. See Figure 10. In the shutdown mode the SS pin is internally grounded, the ON-time one-shot is disabled, the input current at VIN is reduced, and the VCC bypass switch is turned off. The VCC regulator is not disabled in the shutdown mode. Releasing the RON/SD pin allows normal operation to resume. The nominal voltage at RON/SD is shown in the Typical Performance Characteristics. When switching the RON/SD pin, the transition time should be faster than one to two cycles of the regulator's nominal switching frequency. VIN Input Voltage RON LM5010A RON/SD STOP RUN Figure 10. Shutdown Implementation Copyright (c) 2005-2016, Texas Instruments Incorporated Product Folder Links: LM5010A LM5010A-Q1 Submit Documentation Feedback 13 LM5010A, LM5010A-Q1 SNVS376F - OCTOBER 2005 - REVISED MAY 2016 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The LM5010A is a non-synchronous buck regulator converter designed to operate over a wide input voltage and output current range. Spreadsheet-based calculator tools, available on the TI product website at Quick-Start Calculator, can be used to design a single output non-synchronous buck converter. Alternatively, online WEBENCH(R) software is available to create a complete buck design and generate the bill of materials, estimated efficiency, solution size, and cost of the complete solution. 8.2 Typical Application The final circuit is shown in Figure 11, and its performance is shown in Figure 16 and Figure 17. Current limit measured at approximately 1.3 A. 6 - 60V Input VIN C1 4.4 PF VCC 12 13 C5 0.1 PF LM5010A RON BST 3 C4 200k C3 0.47 PF 0.022 PF L1 100 PH RON/SD SW 11 C6 0.022 PF 5V 2 VOUT D1 SS 10 ISEN R1 1.0k 4 SGND 5 FB 9 6 R2 1.0k RTN R3 1.5 C2 22 PF GND Copyright (c) 2016, Texas Instruments Incorporated Figure 11. LM5010A Example Circuit 8.2.1 Design Requirements Table 1 lists the operating parameters for Figure 11. Table 1. Design Parameters 14 Submit Documentation Feedback PARAMETER EXAMPLE VALUE Input voltage 6 V to 60 V Output voltage 5V Load current 200 mA to 1 A Soft-start time 5 ms Copyright (c) 2005-2016, Texas Instruments Incorporated Product Folder Links: LM5010A LM5010A-Q1 LM5010A, LM5010A-Q1 www.ti.com SNVS376F - OCTOBER 2005 - REVISED MAY 2016 8.2.2 Detailed Design Procedure The procedure for calculating the external components is illustrated with a design example. Configure the circuit in Figure 11 according to the components listed in Table 2. Table 2. List of Components for LM5010A Example Circuit ITEM DESCRIPTION VALUE C1 Ceramic capacitor (2) 2.2 F, 100 V C2 Ceramic capacitor 22 F, 16 V C3 Ceramic capacitor 0.47 F, 16 V C4, C6 Ceramic capacitor 0.022 F, 16 V C5 Ceramic capacitor 0.1 F, 100 V D1 Schottky diode 100V, 6 A L1 Inductor 100 H R1 Resistor 1 k R2 Resistor 1 k R3 Resistor 1.5 RON Resistor 200 k U1 LM5010Ax -- 8.2.2.1 Component Selection 8.2.2.1.1 R1 and R2 These resistors set the output voltage, and calculate their ratio with Equation 10. R1/R2 = (VOUT / 2.5 V) - 1 (10) R1 and R2 calculates to 1. The resistors should be chosen from standard value resistors in the range of 1 k to 10 k. A value of 1 k is used for R1 and R2. 8.2.2.1.2 RON, FS RON can be chosen using Equation 7 to set the nominal frequency, or from Equation 6 if the ON-time at a particular VIN is important. A higher frequency generally means a smaller inductor and capacitors (value, size and cost), but higher switching losses. A lower frequency means a higher efficiency, but with larger components. Generally, if PC board space is tight, a higher frequency is better. The resulting ON-time and frequency have a 25% tolerance. Using Equation 7 at a nominal VIN of 8 V, RON is calculated with Equation 11. RON = 5V x (8V - 1.4V) 8V x 175 kHz x 1.18 x 10 -10 - 1.4 k: = 198 k: (11) A value of 200 k will be used for RON, yielding a nominal frequency of 161 kHz at VIN = 6 V, and 205 kHz at VIN = 60 V. 8.2.2.1.3 L1 The guideline for choosing the inductor value in this example is that it must keep the circuit's operation in continuous conduction mode at minimum load current. This is not a strict requirement since the LM5010Ax regulates correctly when in discontinuous conduction mode, although at a lower frequency. However, to provide an initial value for L1 the above guideline will be used. See Figure 12. Copyright (c) 2005-2016, Texas Instruments Incorporated Product Folder Links: LM5010A LM5010A-Q1 Submit Documentation Feedback 15 LM5010A, LM5010A-Q1 SNVS376F - OCTOBER 2005 - REVISED MAY 2016 www.ti.com IPK+ L1 Current IO IOR IPK- 0 mA 1/Fs Figure 12. Inductor Current To keep the circuit in continuous conduction mode, the maximum allowed ripple current is twice the minimum load current, or 400 mAp-p. Using this value of ripple current, the inductor (L1) is calculated using Equation 12 and Equation 13. VOUT x (VIN(max) - VOUT) L1 = IOR x FS(min) x VIN(max) where * L1 = FS(min) is the minimum frequency of 154 kHz (205 kHz - 25%) at VIN(max) 5V x (60V - 5V) 0.40A x 154 kHz x 60V (12) = 74.4 PH (13) Equation 13 provides the minimum value for inductor L1. When selecting an inductor, use a higher standard value (100 uH). To prevent saturation, and possible destructive current levels, L1 must be rated for the peak current which occurs if the current limit and maximum ripple current are reached simultaneously (IPK in Figure 9). The maximum ripple amplitude is calculated by rearranging Equation 12 using VIN(max), FS(min), and the minimum inductor value, based on the manufacturer's tolerance. Assume for Equation 14, Equation 15, and Equation 16 that the inductor's tolerance is 20%. VOUT x (VIN(max) - VOUT) IOR(max) = IOR(max) = L1min x FS(min) x VIN(max) 5V x (60V - 5V) 80 PH x 154 kHz x 60V (14) = 372 mAp-p (15) IPK = ILIM + IOR(max) = 1.5 A + 0.372 A = 1.872 A where * ILIM is the maximum current limit threshold (16) At the nominal maximum load current of 1 A, the peak inductor current is 1.186 A. 8.2.2.1.4 RCL Since it is obvious that the lower peak of the inductor current waveform does not exceed 1 A at maximum load current (see Figure 12), it is not necessary to increase the current limit threshold. Therefore RCL is not needed for this exercise. For applications where the lower peak exceeds 1 A, see Increasing The Current Limit Threshold. 16 Submit Documentation Feedback Copyright (c) 2005-2016, Texas Instruments Incorporated Product Folder Links: LM5010A LM5010A-Q1 LM5010A, LM5010A-Q1 www.ti.com SNVS376F - OCTOBER 2005 - REVISED MAY 2016 8.2.2.1.5 C1 This capacitor limits the ripple voltage at VIN resulting from the source impedance of the supply feeding this circuit, and the on and off nature of the switch current into VIN. At maximum load current, when the buck switch turns on, the current into VIN steps up from zero to the lower peak of the inductor current waveform (IPK- in Figure 12), ramps up to the peak value (IPK+), then drops to zero at turnoff. The average current into VIN during this ON-time is the load current. For a worst case calculation, C1 must supply this average current during the maximum ON-time. The maximum ON-time is calculated at VIN = 6 V using Equation 5, with a 25% tolerance added in Equation 17. tON(max) = 1.18 x 10 -10 x (200k + 1.4k) 6V - 1.4V + 67 ns x 1.25 = 6.5 Ps (17) The voltage at VIN should not be allowed to drop below 5.5 V in order to maintain VCC above its UVLO as in Equation 18. C1 = IO x tON = 'V 1.0A x 6.5 Ps = 13 PF 0.5V (18) Normally a lower value can be used for C1 since the above calculation is a worst case calculation which assumes the power source has a high source impedance. A quality ceramic capacitor with a low ESR should be used for C1. 8.2.2.1.6 C2 and R3 Since the LM5010Ax requires a minimum of 25 mVp-p of ripple at the FB pin for proper operation, the required ripple at VOUT is increased by R1 and R2, and is equal to Equation 19. VRIPPLE = 25 mVp-p x (R1 + R2) / R2 = 50 mVp-p (19) This necessary ripple voltage is created by the inductor ripple current acting on C2's ESR + R3. First, the minimum ripple current is determined which occurs at minimum VIN, maximum inductor value, and calculate the maximum frequency with Equation 20. VOUT x (VIN(min) - VOUT) IOR(min) = = L1max x FS(max) x VIN(min) 5V x (6V - 5V) 120 PH x 201 kHz x 6V = 34.5 mAp-p (20) The minimum ESR for C2 is then equal to Equation 21. ESR(min) = 50 mV = 1.45: 34.5 mA (21) If the capacitor used for C2 does not have sufficient ESR, R3 is added in series as shown in the Block Diagram. The value chosen for C2 is application dependent, and it is recommended that it be no smaller than 3.3 F. C2 affects the ripple at VOUT, and transient response. Experimentation is usually necessary to determine the optimum value for C2. 8.2.2.1.7 C3 The capacitor at the VCC pin provides noise filtering and stability, prevents false triggering of the VCC UVLO at the buck switch ON and OFF transitions, and limits the peak voltage at VCC when a high voltage with a short rise time is initially applied at VIN. C3 should be no smaller than 0.47 F, and must be a good quality, low ESR, ceramic capacitor, physically close to the IC pins. 8.2.2.1.8 C4 The recommended value for C4 is 0.022 F. A high quality ceramic capacitor with low ESR is recommended as C4 supplies the surge current to charge the buck switch gate at each turnon. A low ESR also ensures a complete recharge during each OFF-time. Copyright (c) 2005-2016, Texas Instruments Incorporated Product Folder Links: LM5010A LM5010A-Q1 Submit Documentation Feedback 17 LM5010A, LM5010A-Q1 SNVS376F - OCTOBER 2005 - REVISED MAY 2016 www.ti.com 8.2.2.1.9 C5 This capacitor suppresses transients and ringing due to lead inductance at VIN. TI recommends a low ESR, 0.1 F ceramic chip capacitor, placed physically close to the LM5010Ax. 8.2.2.1.10 C6 The capacitor at the SS pin determines the soft-start time (that is the time for the reference voltage at the regulation comparator and the output voltage) to reach their final value. Determine the capacitor value with Equation 22. C6 = tSS x 11.5 PA 2.5V (22) For a 5 ms soft-start time, C6 calculates to 0.022 F. 8.2.2.1.11 D1 A Schottky diode is recommended. Ultra-fast recovery diodes are not recommended as the high speed transitions at the SW pin may inadvertently affect the IC's operation through external or internal EMI. The diode should be rated for the maximum VIN (60 V), the maximum load current (1 A), and the peak current which occurs when current limit and maximum ripple current are reached simultaneously (IPK in Figure 9), previously calculated to be 1.87 A. The diode's forward voltage drop affects efficiency due to the power dissipated during the OFFtime. The average power dissipation in D1 is calculated from Equation 23. PD1 = VF x IO x (1 - D) where * * IO is the load current D is the duty cycle (23) 8.2.2.2 Low Output Ripple Configurations For applications where low output voltage ripple is required the output can be taken directly from the low ESR output capacitor (C2) as shown in Figure 13. However, R3 slightly degrades the load regulation. The specific component values, and the application determine if this is suitable. L1 SW LM5010A R3 R1 FB VOUT R2 C2 Figure 13. Low Ripple Output Where the circuit of Figure 13 is not suitable, the circuits of Figure 14 or Figure 15 can be used. SW L1 VOUT LM5010A Cff R1 FB R2 R3 C2 Figure 14. Low Output Ripple Using a Feed-Forward Capacitor 18 Submit Documentation Feedback Copyright (c) 2005-2016, Texas Instruments Incorporated Product Folder Links: LM5010A LM5010A-Q1 LM5010A, LM5010A-Q1 www.ti.com SNVS376F - OCTOBER 2005 - REVISED MAY 2016 In Figure 14, Cff is added across R1 to AC-couple the ripple at VOUT directly to the FB pin. This allows the ripple at VOUT to be reduced, in some cases considerably, by reducing R3. In the circuit of Figure 11, the ripple at VOUT ranged from 50 mVp-p at VIN = 6 V to 320 mVp-p at VIN = 60 V. By adding a 1000 pF capacitor at Cff and reducing R3 to 0.75 , the VOUT ripple was reduced by 50%, ranging from 25 mVp-p to 160 mVp-p. SW LM5010A FB L1 VOUT RA CB C2 CA R1 R2 Figure 15. Low Output Ripple Using Ripple Injection To reduce VOUT ripple further, the circuit of Figure 15 can be used. R3 has been removed, and the output ripple amplitude is determined by C2's ESR and the inductor ripple current. RA and CA are chosen to generate a 40 to 50 mVp-p sawtooth at their junction, and that voltage is AC-coupled to the FB pin via CB. In selecting RA and CA, VOUT is considered a virtual ground as the SW pin switches between VIN and -1 V. Since the ON-time at SW varies inversely with VIN, the waveform amplitude at the RA and CA junction is relatively constant. R1 and R2 must typically be increased to more than 10k each to not significantly attenuate the signal provided to FB through CB. Typical values for the additional components are RA = 200 k, CA = 680 pF, and CB = 0.01 F. 8.2.2.3 Increasing The Current Limit Threshold The current limit threshold is nominally 1.25 A, with a minimum value of 1 A. If, at maximum load current, the lower peak of the inductor current (IPK- in Figure 12) exceeds 1 A, resistor RCL must be added between SGND and ISEN to increase the current limit threshold to be equal or exceed that lower peak current. This resistor diverts some of the recirculating current from the internal sense resistor so that a higher current level is needed to switch the internal current limit comparator. Calculate IPK- with Equation 24. IPK- = IO(max) - IOR(min) 2 where * * IO(max) is the maximum load current IOR(min) is the minimum ripple current calculated using Equation 20 (24) RCL is calculated from Equation 25. RCL = 1.0A x 0.11: IPK- - 1.0A where * 0.11 is the minimum value of the internal resistance from SGND to ISEN (25) The next smaller standard value resistor must be used for RCL. With the addition of RCL, and when the circuit is in current limit, the upper peak current out of the SW pin (IPK in Figure 9) can be as high as Equation 26. 1.5A x (150 m: + RCL) IPK = RCL + IOR(MAX) where * IOR(max) is calculated using Equation 14 (26) The inductor L1 and diode D1 must be rated for this current. If IPK exceeds 2 A , the inductor value must be increased to reduce the ripple amplitude. This will necessitate recalculation of IOR(min), IPK-, and RCL. Increasing the circuit's current limit will increase power dissipation and the junction temperature within the LM5010Ax. See Layout Guidelines for guidelines on this issue. Copyright (c) 2005-2016, Texas Instruments Incorporated Product Folder Links: LM5010A LM5010A-Q1 Submit Documentation Feedback 19 LM5010A, LM5010A-Q1 SNVS376F - OCTOBER 2005 - REVISED MAY 2016 www.ti.com 8.2.3 Application Curves 100 250 200 VIN = 6V FREQUENCY (kHz) EFFICIENCY (%) 80 12V 60V 60 40 20 0 200 150 100 Load Curent = 500 mA 50 400 600 800 1000 0 6 20 40 60 VIN (V) LOAD CURRENT (mA) Figure 17. Frequency vs VIN Figure 16. Efficiency vs Load Current and VIN 8.3 Do's and Don'ts A minimum load current of 500 A is required to maintain proper operation. If the load current falls below that level, the bootstrap capacitor can discharge during the long OFF-time and the circuit either shuts down or cycles ON and OFF at a low frequency. If the load current is expected to drop below 500 A in the application, choose the feedback resistors to be low enough in value to provide the minimum required current at nominal VOUT. 20 Submit Documentation Feedback Copyright (c) 2005-2016, Texas Instruments Incorporated Product Folder Links: LM5010A LM5010A-Q1 LM5010A, LM5010A-Q1 www.ti.com SNVS376F - OCTOBER 2005 - REVISED MAY 2016 9 Power Supply Recommendations The LM5010Ax is designed to operate with an input power supply capable of supplying a voltage range from 6 V to 75 V. The input power supply must be well-regulated and capable of supplying sufficient current to the regulator during peak load operation. Also, like in all applications, the power-supply source impedance must be small compared to the module input impedance to maintain the stability of the converter. 10 Layout 10.1 Layout Guidelines The LM5010Ax regulation, overvoltage, and current limit comparators are very fast, and respond to short duration noise pulses. Therefore, layout considerations are critical for optimum performance. The layout must be as neat and compact as possible, and all the components must be as close as possible to their associated pins. The two major current loops have currents which switch very fast, and so the loops should be as small as possible to minimize conducted and radiated EMI. The first loop is that formed by C1 (CIN), through the VIN to SW pins, L1 (LIND), C2 (COUT), and back to C1. The second loop is that formed by D1, L1, C2, and the SGND and ISEN pins. The ground connection from C2 to C1 should be as short and direct as possible, preferably without going through vias. Directly connect the SGND and RTN pin to each other, and they should be connected as directly as possible to the C1/C2 ground line without going through vias. The power dissipation within the IC can be approximated by determining the total conversion loss (PIN - POUT), and then subtracting the power losses in the free-wheeling diode and the inductor. The power loss in the diode is approximately Equation 27. PD1 = IO x VF x (1 - D) where * * * IO is the load current VF is the diode's forward voltage drop D is the duty cycle (27) The power loss in the inductor is approximately Equation 28. PL1 = IO2 x RL x 1.1 where * * RL is the inductor's DC resistance the 1.1 factor is an approximation for the AC losses (28) If it is expected that the internal dissipation of the LM5010Ax will produce high junction temperatures during normal operation, good use of the PC board's ground plane can help considerably to dissipate heat. The exposed pad on the IC package bottom should be soldered to a ground plane, and that plane should both extend from beneath the IC, and be connected to exposed ground plane on the board's other side using as many vias as possible. The exposed pad is internally connected to the IC substrate. The use of wide PC board traces at the pins, where possible, can help conduct heat away from the IC. The four no connect pins on the HTSSOP package are not electrically connected to any part of the IC, and may be connected to ground plane to help dissipate heat from the package. Judicious positioning of the PC board within the end product, along with the use of any available air flow (forced or natural convection) can help reduce the junction temperature. Copyright (c) 2005-2016, Texas Instruments Incorporated Product Folder Links: LM5010A LM5010A-Q1 Submit Documentation Feedback 21 LM5010A, LM5010A-Q1 SNVS376F - OCTOBER 2005 - REVISED MAY 2016 www.ti.com 10.2 Layout Example VOUT CA COUT LIND GND RA Cbyp CIN SW CBST SW LM5010A BST D1 ISEN GND VLINE VIN VCC Exp Thermal Pad RON RON CVCC CSS SGND SS RTN FB FB RFB2 CB RFB1 Via to Ground Plane Figure 18. LM5010A Buck Layout Example With the WSON Package 22 Submit Documentation Feedback Copyright (c) 2005-2016, Texas Instruments Incorporated Product Folder Links: LM5010A LM5010A-Q1 LM5010A, LM5010A-Q1 www.ti.com SNVS376F - OCTOBER 2005 - REVISED MAY 2016 11 Device and Documentation Support 11.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 3. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY LM5010A Click here Click here Click here Click here Click here LM5010A-Q1 Click here Click here Click here Click here Click here 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.5 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright (c) 2005-2016, Texas Instruments Incorporated Product Folder Links: LM5010A LM5010A-Q1 Submit Documentation Feedback 23 PACKAGE OPTION ADDENDUM www.ti.com 29-Mar-2016 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LM5010AMH/NOPB ACTIVE HTSSOP PWP 14 94 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 150 L5010 AMH LM5010AMHE/NOPB ACTIVE HTSSOP PWP 14 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 150 L5010 AMH LM5010AMHX NRND HTSSOP PWP 14 2500 TBD Call TI Call TI -40 to 150 L5010 AMH LM5010AMHX/NOPB ACTIVE HTSSOP PWP 14 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 150 L5010 AMH LM5010AQ0MH/NOPB ACTIVE HTSSOP PWP 14 94 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 150 L5010A Q0MH LM5010AQ0MHX/NOPB ACTIVE HTSSOP PWP 14 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 150 L5010A Q0MH LM5010AQ1MH/NOPB ACTIVE HTSSOP PWP 14 94 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L5010A Q1MH LM5010AQ1MHX/NOPB ACTIVE HTSSOP PWP 14 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 L5010A Q1MH LM5010ASD NRND WSON DPR 10 1000 TBD Call TI Call TI -40 to 150 L00065B LM5010ASD/NOPB ACTIVE WSON DPR 10 1000 Green (RoHS & no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 150 L00065B LM5010ASDX/NOPB ACTIVE WSON DPR 10 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 150 L00065B (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 29-Mar-2016 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF LM5010A, LM5010A-Q1 : * Catalog: LM5010A * Automotive: LM5010A-Q1 NOTE: Qualified Version Definitions: * Catalog - TI's standard catalog product * Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 28-Jan-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LM5010AMHE/NOPB HTSSOP PWP 14 250 178.0 12.4 LM5010AMHX B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.95 5.6 1.6 8.0 12.0 Q1 HTSSOP PWP 14 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1 LM5010AQ0MHX/NOPB HTSSOP PWP 14 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1 LM5010AQ1MHX/NOPB HTSSOP PWP 14 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1 LM5010ASD WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM5010ASD/NOPB WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM5010ASDX/NOPB WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 28-Jan-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5010AMHE/NOPB HTSSOP PWP LM5010AMHX HTSSOP PWP 14 250 210.0 185.0 35.0 14 2500 367.0 367.0 35.0 LM5010AQ0MHX/NOPB HTSSOP LM5010AQ1MHX/NOPB HTSSOP PWP 14 2500 367.0 367.0 35.0 PWP 14 2500 367.0 367.0 LM5010ASD 35.0 WSON DPR 10 1000 210.0 185.0 35.0 LM5010ASD/NOPB WSON DPR 10 1000 210.0 185.0 35.0 LM5010ASDX/NOPB WSON DPR 10 4500 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA PWP0014A MXA14A (Rev A) www.ti.com MECHANICAL DATA DPR0010A SDC10A (Rev A) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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