DESCRIPTION
The 7540 Group is the 8-bit microcomputer based on the 740 fam-
ily core technology.
The 7540 Group has a serial I/O, 8-bit timers, a 16-bit timer, and
an A-D converter, and is useful for control of home electric appli-
ances and office automation equipment.
FEATURES
•Basic machine-language instructions ...................................... 71
•The minimum instruction execution time ......................... 0.34 µs
(at 6 MHz oscillation frequency, double-speed mode for the
shortest instruction)
•Memory size ROM............................................ 8 K to 32 K bytes
RAM ............................................. 384 to 768 bytes
•Programmable I/O ports....................... 29 (25 in 32-pin version)
•Interrupts ................................................. 15 sources, 15 vectors
................................. (14 sources, 14 vectors for 32-pin version)
•Timers............................................................................. 8-bit ✕ 4
...................................................................................... 16-bit ✕ 1
•Serial I/O1 ................... 8-bit ✕ 1 (UART or Clock-synchronized)
•Serial I/O2 (Note 1).....................8-bit ✕ 1 (Clock-synchronized)
•A-D converter ............................................... 10-bit ✕ 8 channels
.................................................... (6 channels for 32-pin version)
•Clock generating circuit............................................. Built-in type
(low-power dissipation by a ring oscillator enabled)
(connect to external ceramic resonator or quartz-crystal oscilla-
tor permitting RC oscillation)
•Watchdog timer ............................................................ 16-bit ✕ 1
•Power source voltage
X
IN
oscillation frequency at ceramic oscillation, in double-speed mode
At 6 MHz.................................................................... 4.5 to 5.5 V
XIN oscillation frequency at ceramic oscillation, in high-speed mode
At 8 MHz.................................................................... 4.0 to 5.5 V
At 4 MHz.................................................................... 2.4 to 5.5 V
At 2 MHz.................................................................... 2.2 to 5.5 V
XIN oscillation frequency at RC oscillation in high-speed mode or
middle-speed mode
At 4 MHz.................................................................... 4.0 to 5.5 V
At 2 MHz.................................................................... 2.4 to 5.5 V
At 1 MHz.................................................................... 2.2 to 5.5 V
•Power dissipation
Mask ROM version.......................................22.5 mW (standard)
One Time PROM version ................................30 mW (standard)
•Operating temperature range...................................–20 to 85 °C
(–40 to 85 °C for extended operating temperature version)
(–40 to 125 °C for extended operating temperature 125 °C ver-
sion (Note 2))
APPLICATION
Office automation equipment, factory automation equipment,
home electric appliances, consumer electronics, car, etc.
Notes 1: Serial I/O2 can be used in the following cases;
(1) Serial I/O1 is not used,
(2) Serial I/O1 is used as UART and BRG output divided by 16 is
selected as the synchronized clock.
2: In this version, the operating temperature range and total time
are limited as follows;
55 °C to 85 °C: within total 6000 hours,
85 °C to 125 °C: within total 1000 hours.
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Rev.3.20 2003.05.28 page 1 of 83
7540 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER REJ03B0011-0320Z
Rev.3.20
2003.05.28
Rev.3.20 2003.05.28 page 2 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 2 Pin configuration (36P2R-A type)
Packa
g
e t
yp
e: 36P2R-A
10
1
2
3
4
6
7
8
9
11
12
14
15
16
5
13
17
18
36
35
34
33
31
30
26
25
24
23
22
21
20
19
32
27
29
28
P0
0
/CNTR
1
CNV
SS
X
OUT
X
IN
V
SS
P0
1
/TY
OUT
P0
2
/TZ
OUT
P0
3
/TX
OUT
P0
4
P3
0
(LED
0
)
Vcc
V
REF
P0
5
P1
0
/R
X
D
1
P2
6
/AN
6
P2
7
/AN
7
P1
1
/T
X
D
1
P1
2
/S
CLK1
/S
CLK2
P1
3
/S
RDY1
/S
DATA2
P2
3
/AN
3
P2
2
/AN
2
P2
1
/AN
1
P2
0
/AN
0
P3
1
(LED
1
)
P3
6
(LED
6
)/INT
1
P2
4
/AN
4
P2
5
/AN
5
P0
6
P0
7
P3
7
/INT
0
RESET
M37540Mx-XXXFP
M37540MxT-XXXFP
M37540MxV-XXXFP
M37540E8FP
M37540E8T-XXXFP
M37540E8V-XXXFP
P1
4
/CNTR
0
P3
5
(LED
5
)
P3
4
(LED
4
)
P3
3
(LED
3
)
P3
2
(LED
2
)
PIN CONFIGURATION (TOP VIEW)
Fig. 1 Pin configuration (32P6U-A type)
Package type: 32P6U-A
P0
7
P1
0
/R
X
D
1
P1
1
/T
X
D
1
P1
2
/S
CLK1
/S
CLK2
P1
3
/S
RDY1
/S
DATA2
P1
4
/CNTR
0
P2
0
/AN
0
P2
1
/AN
1
32
31
30
29
28
27
26
25
P3
4
(LED
4
)
P3
3
(LED
3
)
P3
2
(LED
2
)
P3
1
(LED
1
)
P3
0
(LED
0
)
V
SS
X
OUT
X
IN
9
10
11
12
13
14
15
16
2
8
7
6
5
3
1
4
V
CC
CNV
SS
RESET
P2
2
/AN
2
P0
5
20
17
18
19
21
24
P0
2
/TZ
OUT
P0
4
P0
3
/TX
OUT
P0
6
23
22
P0
1
/TY
OUT
P0
0
/CNTR
1
P3
7
/INT
0
M37540Mx-XXXGP
M37540MxT-XXXGP
M37540MxV-XXXGP
M37540ExGP
M37540E8T-XXXGP
M37540E8V-XXXGP
P2
3
/AN
3
P2
4
/AN
4
P2
5
/AN
5
V
REF
Rev.3.20 2003.05.28 page 3 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 4 Pin configuration (42S1M type)
Outline 42S1M
10
1
2
3
4
6
7
8
9
11
12
14
15
16
5
13
17
18
36
35
34
33
31
30
26
25
24
23
22
32
27
29
28
19
20
21
42
41
40
39
37
38
P00/CNTR1
CNVSS
XOUT
XIN
VSS
P01/TYOUT
P02/TZOUT
P03/TXOUT
P04
P30(LED0)
Vcc
VREF
P05
P12/SCLK1/SCLK2
P25/AN5
P26/AN6
P13/SRDY1/SDATA2
P14/CNTR0
NC
P22/AN2
NC
P21/AN1
P20/AN0
P31(LED1)
P36(LED6)/INT1
P23/AN3
P24/AN4
P06
P07
P37/INT0
RESET
M37540RSS
NC
P35(LED5)
P34(LED4)
P33(LED3)
P32(LED2)
NC
P10/RXD1
P11/TXD1
NC
NC
P27/AN7
Fig. 3 Pin configuration (32P4B-A type)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CNV
SS
P1
2
/S
CLK1
/S
CLK2
P1
3
/S
RDY1
/S
DATA2
P1
4
/CNTR
0
P2
0
/AN
0
P2
1
/AN
1
P2
2
/AN
2
P2
3
/AN
3
P2
4
/AN
4
V
CC
X
IN
X
OUT
V
SS
P1
1
/T
X
D
1
P1
0
/R
X
D
1
P0
7
P0
6
P0
5
P0
4
P3
0
(LED
0
)
P2
5
/AN
5
V
REF
RESET
P0
0
/CNTR
1
P3
3
(LED
3
)
P3
2
(LED
2
)
P3
1
(LED
1
)
M37540Mx-XXXSP
M37540ExSP
32
P0
1
/TY
OUT
P0
2
/TZ
OUT
P0
3
/TX
OUT
14
15
16
P3
7
/INT
0
P3
4
(LED
4
)
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Package type: 32P4B
Rev.3.20 2003.05.28 page 4 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
FUNCTIONAL BLOCK
Fig. 5 Functional block diagram (32P6U package)
FUNCTIONAL BLOCK DIAGRAM (Package: 32P6U)
X
IN OUT
X
SI/O1(8)
RAM ROM
CPU
A
X
Y
S
PC
H
PC
L
PS
V
SS
11
RESET
6
V
CC
87
CNV
SS
P1(5)
30 28 2629 27
32 31
P2(6)
P3(6)
1215 13
5
Reset input
I/O port P2 I/O port P1I/O port P3
Clock generating circuit
Clock input Clock output
910
42
31
A-D
converter
(10)
V
REF
Watchdog timer
Reset
0
14
INT
0
1617
SI/O2(8)
CNTR
0
I/O port P0
Prescaler Y (8)
Prescaler Z (8)
Timer X (8)
Timer Z (8)
Timer Y (8)
Key-on wakeup
TY
OUT
TZ
OUT
Prescaler X (8)
CNTR
1
Timer A (16)
P0(8)
25 23 21 19
24 22 20 18
INT
0
Timer 1 (8)
Prescaler 1 (8)
TX
OUT
Rev.3.20 2003.05.28 page 5 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 6 Functional block diagram (36P2R package)
FUNCTIONAL BLOCK DIAGRAM (Package: 36P2R)
A-D
converter
(10)
X
IN OUT
X
CPU
V
SS
18
RESET
13
V
CC
15 14
CNV
SS
P0(8)
34 32 30 28
33 31 29 27
P1(5)
31
35
236
756 4
P2(8)
P3(8)
2023 21 19
12
I/O port P2 I/O port P0I/O port P1I/O port P3
16 17
11 9
10 8
0
22
26 2425
SI/O1(8)
RAM ROM A
X
Y
S
PC
H
PC
L
PS
Reset input
Clock generating circuit
Clock input Clock output
V
REF
Watchdog timer Reset
INT
0
SI/O2(8)
CNTR
0
Prescaler Y (8)
Prescaler Z (8)
Timer X (8)
Timer Z (8)
Timer Y (8)
Key-on wakeup
TYOUT
TZOUT
Prescaler X (8)
CNTR1
Timer A (16)
INT0
Timer 1 (8)
Prescaler 1 (8)
TXOUT
INT1
Rev.3.20 2003.05.28 page 6 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 7 Functional block diagram (32P4B package)
FUNCTIONAL BLOCK DIAGRAM (Package: 32P4B)
16 11
13 12
P1(5)
3131
232
54
P2(6)
P3(6)
1720 18
10
14 15
97
86
0
19
2122
P0(8)
30 28 26 24
29 27 25 23
A-D
converter
(10)
X
IN OUT
X
CPU
V
SS
RESET
V
CC
CNV
SS
I/O port P2 I/O port P0I/O port P1
I/O port P3
SI/O1(8)
RAM ROM
A
X
Y
S
PC
H
PC
L
PS
Reset input
Clock generating circuit
Clock input Clock output
VREF
Watchdog timer
Reset
INT0
SI/O2(8)
CNTR0
Prescaler Y (8)
Prescaler Z (8)
Timer X (8)
Timer Z (8)
Timer Y (8)
Key-on wakeup
TYOUT
TZOUT
Prescaler X (8)
CNTR1
Timer A (16)
INT0
Timer 1 (8)
Prescaler 1 (8)
TXOUT
Rev.3.20 2003.05.28 page 7 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
PIN DESCRIPTION
Table 1 Pin description Function
•Apply voltage of 2.2 to 5.5 V to Vcc, and 0 V to Vss.
•Reference voltage input pin for A-D converter
•Chip operating mode control pin, which is always connected to Vss.
•Reset input pin for active “L”
•Input and output pins for main clock generating circuit
•Connect a ceramic resonator or quartz crystal oscillator between the XIN and XOUT pins.
•For using RC oscillator, short between the XIN and XOUT pins, and connect the capacitor and resistor.
•If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
• When the ring oscillator is selected as the main clock, connect X
IN
pin to V
SS
and leave X
OUT
open.
Function expect a port function
Name
Power source
(Note 1)
Analog reference
voltage
CNVss
Reset input
Clock input
I/O port P0
I/O port P1
Pin
Vcc, Vss
VREF
CNVss
RESET
XIN
P00/CNTR1
P01/TYOUT
P02/TZOUT
P03/TXOUT
P04–P07
Notes 1: VCC = 2.4 to 5.5 V for the extended operating temperature version and the extended operating temperature 125 °C version.
2: P26/AN6 and P27/AN7 do not exist for the 32-pin version, so that Port P2 is a 6-bit I/O port.
3: P35 and P36/INT1 do not exist for the 32-pin version, so that Port P3 is a 6-bit I/O port.
• Key-input (key-on wake up
interrupt input) pins
• Timer Y, timer Z, timer X and
timer A function pin
•8-bit I/O port.
•I/O direction register allows each pin to be individually pro-
grammed as either input or output.
•CMOS compatible input level
•CMOS 3-state output structure
•Whether a built-in pull-up resistor is to be used or not can be de-
termined by program.
•5-bit I/O port
•I/O direction register allows each pin to be individually pro-
grammed as either input or output.
•CMOS compatible input level
•CMOS 3-state output structure
•CMOS/TTL level can be switched for P10, P12 and P13
•8-bit I/O port having almost the same function as P0
•CMOS compatible input level
•CMOS 3-state output structure
•8-bit I/O port
P10/RxD1
P11/TxD1
P12/SCLK1/SCLK2
P1
3
/S
RDY1
/S
DATA2
P14/CNTR0
P2
0
/AN
0
–P2
7
/AN
7
P30–P35
P36/INT1
P37/INT0
I/O port P2
(Note 2)
I/O port P3
(Note 3)
• Serial I/O1 function pin
• Serial I/O1 function pin
• Serial I/O2 function pin
• Timer X function pin
• Input pins for A-D converter
• Interrupt input pins
•I/O direction register allows each pin to be individually programmed as either input or output.
•CMOS compatible input level (CMOS/TTL level can be switched for P36 and P37).
•CMOS 3-state output structure
•P30 to P36 can output a large current for driving LED.
XOUT Clock output
•Whether a built-in pull-up resistor is to be used or not can be de-
termined by program.
Rev.3.20 2003.05.28 page 8 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
GROUP EXPANSION
plans to expand the 7540 group as follow:
Memory type
Support for Mask ROM version, One Time PROM version, and
Emulator MCU .
Memory size
ROM/PROM size ................................................. 8 K to 32 K bytes
RAM size .............................................................. 384 to 768 bytes
Package
32P4B ..................................................32-pin plastic molded SDIP
32P6U-A ...................... 0.8 mm-pitch 32-pin plastic molded LQFP
36P2R-A ...................... 0.8 mm-pitch 36-pin plastic molded SSOP
42S1M....................................42-pin shrink ceramic PIGGY BACK
Fig. 8 Memory expansion plan
3
8
4
3
2
K
R
O
M
s
i
z
e
(
b
y
t
e
s
)
R
A
M
s
i
z
e
(
b
y
t
e
s
)
5
1
27
6
8
16
K
0
U
n
d
e
r
d
e
v
e
l
o
p
m
e
n
t
M
3
7
5
4
0
E
8
M37540M4
M37540M4T
N
o
t
e
:
P
r
o
d
u
c
t
s
u
n
d
e
r
d
e
v
e
l
o
p
m
e
n
t
•
•
•
t
h
e
d
e
v
e
l
o
p
m
e
n
t
s
c
h
e
d
u
l
e
a
n
d
s
p
e
c
i
f
i
c
a
t
i
o
n
m
a
y
b
e
r
e
v
i
s
e
d
w
i
t
h
o
u
t
n
o
t
i
c
e
.
8K
M
3
7
5
4
0
E
8
T
M
3
7
5
4
0
E
8
V
U
n
d
e
r
d
e
v
e
l
o
p
m
e
n
t
M
3
7
5
4
0
M
2
T
M
3
7
5
4
0
M
2
M37540E2
U
n
d
e
r
d
e
v
e
l
o
p
m
e
n
t
M37540M2V
M37540M4V
Rev.3.20 2003.05.28 page 9 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Currently supported products are listed below.
Table 2 List of supported products
Part Number (P) ROM size (bytes)
ROM size for User ()
8192
(8062)
16384
(16254)
8192
(8062)
32768
(32638)
RAM size
(bytes)
384
512
384
768
768
Package
32P4B
36P2R-A
32P6U-A
32P4B
36P2R-A
32P6U-A
32P4B
36P2R-A
32P6U-A
32P4B
36P2R-A
32P6U-A
42S1M
Remarks
Mask ROM version
Mask ROM version
Mask ROM version (extended operating temperature version)
Mask ROM version (extended operating temperature 125 °C version)
Mask ROM version
Mask ROM version (extended operating temperature version)
Mask ROM version (extended operating temperature 125 °C version)
Mask ROM version
Mask ROM version
Mask ROM version (extended operating temperature version)
Mask ROM version (extended operating temperature 125 °C version)
Mask ROM version
Mask ROM version (extended operating temperature version)
Mask ROM version (extended operating temperature 125 °C version)
One Time PROM version (blank)
One Time PROM version (blank)
One Time PROM version (blank)
One Time PROM version (blank)
One Time PROM version (blank)
One Time PROM version
(shipped after programming, extended operating temperature version)
One Time PROM version (shipped after programming, extended
operating temperature 125 °C version)
One Time PROM version (blank)
One Time PROM version
(shipped after programming, extended operating temperature version)
One Time PROM version (shipped after programming, extended
operating temperature 125 °C version)
Emulator MCU
M37540M2-XXXSP
M37540M2-XXXFP
M37540M2T-XXXFP
M37540M2V-XXXFP
M37540M2-XXXGP
M37540M2T-XXXGP
M37540M2V-XXXGP
M37540M4-XXXSP
M37540M4-XXXFP
M37540M4T-XXXFP
M37540M4V-XXXFP
M37540M4-XXXGP
M37540M4T-XXXGP
M37540M4V-XXXGP
M37540E2SP*
M37540E2FP*
M37540E2GP*
M37540E8SP
M37540E8FP
M37540E8T-XXXFP*
M37540E8V-XXXFP*
M37540E8GP
M37540E8T-XXXGP*
M37540E8V-XXXGP*
M37540RSS
*: Under development
Rev.3.20 2003.05.28 page 10 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
b7 b0
X
b7 b0
S
b7 b0
Y
b7 b0
PC
L
Processor Status Register (PS)
Carry Flag
b7 b0
b7 b0
A
b15
PC
H
Zero Flag
Interrupt Disable Flag
Decimal Mode Flag
Break Flag
Index X Mode Flag
Overflow Flag
Negative Flag
Program Counter
Stack Pointer
Index Register Y
Index Register X
Accumulator
CZIDBTVN
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
The MCU uses the standard 740 family instruction set. Refer to
the table of 740 family addressing modes and machine-language
instructions or the SERIES 740 <SOFTWARE> USER’S MANUAL
for details on each instruction set.
Machine-resident 740 family instructions are as follows:
1. The FST and SLW instructions cannot be used.
2. The MUL and DIV instructions can be used.
3. The WIT instruction can be used.
4. The STP instruction can be used.
This instruction cannot be used while CPU operates by a ring os-
cillator.
Accumulator (A)
The accumulator is an 8-bit register. Data operations such as data
transfer, etc., are executed mainly through the accumulator.
Index register X (X), Index register Y (Y)
Both index register X and index register Y are 8-bit registers. In
the index addressing modes, the value of the OPERAND is added
to the contents of register X or register Y and specifies the real
address.
When the T flag in the processor status register is set to “1”, the
value contained in index register X becomes the address for the
second OPERAND.
Stack pointer (S)
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. The stack is used to store the current address data
and processor status when branching to subroutines or interrupt
routines.
The lower eight bits of the stack address are determined by the
contents of the stack pointer. The upper eight bits of the stack ad-
dress are determined by the Stack Page Selection Bit. If the Stack
Page Selection Bit is “0”, then the RAM in the zero page is used
as the stack area. If the Stack Page Selection Bit is “1”, then RAM
in page 1 is used as the stack area.
The Stack Page Selection Bit is located in the SFR area in the
zero page. Note that the initial value of the Stack Page Selection
Bit varies with each microcomputer type. Also some microcom-
puter types have no Stack Page Selection Bit and the upper eight
bits of the stack address are fixed. The operations of pushing reg-
ister contents onto the stack and popping them from the stack are
shown in Fig. 9.
Program counter (PC)
The program counter is a 16-bit counter consisting of two 8-bit
registers PCH and PCL. It is used to indicate the address of the
next instruction to be executed.
Fig. 9 740 Family CPU register structure
Rev.3.20 2003.05.28 page 11 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Execute JSR
On-going Routine
M (S) (PCH)
(S) (S – 1)
M (S) (PCL)
Execute RTS
(PCL) M (S)
(S) (S – 1)
(S) (S + 1)
(S) (S + 1)
(PCH) M (S)
Subroutine
Restore Return
Address
Store Return Address
on Stack M (S) (PS)
Execute RTI
(PS) M (S)
(S) (S – 1)
(S) (S + 1)
Interrupt
Service Routine
Restore Contents of
Processor Status Register
M (S) (PCH)
(S) (S – 1)
M (S) (PCL)
(S) (S – 1)
(PCL) M (S)
(S) (S + 1)
(S) (S + 1)
(PCH) M (S)
Restore Return
Address
I Flag “0” to “1”
Fetch the Jump Vector
Store Return Address
on Stack
Store Contents of Processor
Status Register on Stack
Interrupt request
(Note)
Note : The condition to enable the interrupt Interrupt enable bit is “1”
Interrupt disable flag is “0”
Table 3 Push and pop instructions of accumulator or processor status register
Accumulator
Processor status register
Push instruction to stack
PHA
PHP
Pop instruction from stack
PLA
PLP
Fig. 10 Register push and pop at interrupt generation and subroutine call
Rev.3.20 2003.05.28 page 12 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Processor status register (PS)
The processor status register is an 8-bit register consisting of
flags which indicate the status of the processor after an arithmetic
operation. Branch operations can be performed by testing the
Carry (C) flag, Zero (Z) flag, Overflow (V) flag, or the Negative (N)
flag. In decimal mode, the Z, V, N flags are not valid.
After reset, the Interrupt disable (I) flag is set to “1”, but all other
flags are undefined. Since the Index X mode (T) and Decimal
mode (D) flags directly affect arithmetic operations, they should
be initialized in the beginning of a program.
(1) Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
(2) Zero flag (Z)
The Z flag is set if the result of an immediate arithmetic operation
or a data transfer is “0”, and cleared if the result is anything other
than “0”.
(3) Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt generated
by the BRK instruction. Interrupts are disabled when the I flag is
“1”.
When an interrupt occurs, this flag is automatically set to “1” to
prevent other interrupts from interfering until the current interrupt
is serviced.
(4) Decimal mode flag (D)
The D flag determines whether additions and subtractions are ex-
ecuted in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
(5) Break flag (B)
The B flag is used to indicate that the current interrupt was gener-
ated by the BRK instruction. The BRK flag in the processor status
register is always “0”. When the BRK instruction is used to gener-
ate an interrupt, the processor status register is pushed onto the
stack with the break flag set to “1”. The saved processor status is
the only place where the break flag is ever set.
(6) Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed be-
tween accumulator and memory, e.g. the results of an operation
between two memory locations is stored in the accumulator. When
the T flag is “1”, direct arithmetic operations and direct data trans-
fers are enabled between memory locations, i.e. between memory
and memory, memory and I/O, and I/O and I/O. In this case, the
result of an arithmetic operation performed on data in memory lo-
cation 1 and memory location 2 is stored in memory location 1.
The address of memory location 1 is specified by index register X,
and the address of memory location 2 is specified by normal ad-
dressing modes.
(7) Overflow flag (V)
The V flag is used during the addition or subtraction of one byte
of signed data. It is set if the result exceeds +127 to -128. When
the BIT instruction is executed, bit 6 of the memory location oper-
ated on by the BIT instruction is stored in the overflow flag.
(8) Negative flag (N)
The N flag is set if the result of an arithmetic operation or data
transfer is negative. When the BIT instruction is executed, bit 7 of
the memory location operated on by the BIT instruction is stored in
the negative flag.
Table 4 Set and clear instructions of each bit of processor status register
Set instruction
Clear instruction
C flag
SEC
CLC
Z flag
–
–
I flag
SEI
CLI
D flag
SED
CLD
B flag
–
–
T flag
SET
CLT
V flag
–
CLV
N flag
–
–
Rev.3.20 2003.05.28 page 13 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
[CPU mode register] CPUM
The CPU mode register contains the stack page selection bit.
This register is allocated at address 003B16.
Switching method of CPU mode register
Switch the CPU mode register (CPUM) at the head of program af-
ter releasing Reset in the following method.
Fig. 12 Switching method of CPU mode register
Fig. 11 Structure of CPU mode register
Oscillation mode selection bit (Note 1)
0 : Ceramic oscillation
1 : RC oscillation
CPU mode register
(CPUM: address 003B
16
, initial value: 80
16
)
Stack page selection bit
0 : 0 page
1 : 1 page
Clock division ratio selection bits
b7 b6
0 0 : f(φ) = f(X
IN
)/2 (High-speed mode)
0 1 : f(φ) = f(X
IN
)/8 (Middle-speed mode)
1 0 : applied from ring oscillator
1 1 : f(φ) = f(X
IN
) (Double-speed mode)(Note 2)
Ring oscillator oscillation control bit
0 : Ring oscillator oscillation enabled
1 : Ring oscillator oscillation stop
X
IN
oscillation control bit
0 : Ceramic or RC oscillation enabled
1 : Ceramic or RC oscillation stop
Processor mode bits (Note 1)
b1 b0
0 0 Single-chip mode
0 1
1 0
1 1 Not available
b7 b0
2: These bits are used only when a ceramic oscillation is selected.
Note 1: The bit can be rewritten only once after releasing reset. After rewriting
it is disable to write any data to the bit. However, by reset the bit is
initialized and can be rewritten, again.
(It is not disable to write any data to the bit for emulator MCU
“M37540RSS”.)
Do not use these when an RC oscillation is selected.
After releasing reset
Switch the oscillation mode
selection bit (bit 5 of CPUM)
Switch the clock division ratio
selection bits (bits 6 and 7 of CPUM)
Main routine
Start with a built-in ring oscillator
An initial value is set as a ceramic
oscillation mode. When it is switched to an
RC oscillation, its oscillation starts.
Select 1/1, 1/2, 1/8 or ring oscillator.
Wait by ring oscillator operation until
establishment of oscillator clock
When using a ceramic oscillation, wait until
establlishment of oscillation from oscillation starts.
When using an RC oscillation, wait time is not
required basically (time to execute the instruction to
switch from a ring oscillator meets the requirement).
Rev.3.20 2003.05.28 page 14 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Memory
Special function register (SFR) area
The SFR area in the zero page contains control registers such as
I/O ports and timers.
RAM
RAM is used for data storage and for a stack area of subroutine
calls and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is a user area for storing programs.
Interrupt vector area
The interrupt vector area contains reset and interrupt vectors.
Zero page
The 256 bytes from addresses 000016 to 00FF16 are called the
zero page area. The internal RAM and the special function regis-
ters (SFR) are allocated to this area.
The zero page addressing mode can be used to specify memory
and register addresses in the zero page area. Access to this area
with only 2 bytes is possible in the zero page addressing mode.
Special page
The 256 bytes from addresses FF0016 to FFFF16 are called the
special page area. The special page addressing mode can be
used to specify memory addresses in the special page area. Ac-
cess to this area with only 2 bytes is possible in the special page
addressing mode.
Fig. 13 Memory map diagram
0100
16
0000
16
0040
16
0440
1
6
FF00
16
FFDC
1
6
FFFE
16
FFFF
16
3
8
4
5
1
2
7
6
8
XXXX
16
0
1
B
F1
6
0
2
3
F
1
6
0
3
3
F
1
6
8
1
9
2
1
6
3
8
4
3
2
7
6
8
E00016
C000
16
8000
16
E
0
8
01
6
C
0
8
0
1
6
8
0
8
0
1
6
Y
Y
Y
Y
1
6
ZZZZ
16
RAM
ROM
R
e
s
e
r
v
e
d
a
r
e
a
S
F
R
a
r
e
a
Not used
I
n
t
e
r
r
u
p
t
v
e
c
t
o
r
a
r
e
a
R
O
M
a
r
e
a
Reserved ROM area
(128 bytes)
Z
e
r
o
p
a
g
e
Special page
R
A
M
a
r
e
a
R
A
M
c
a
p
a
c
i
t
y
(
b
y
t
e
s
)address
XXXX
16
R
O
M
c
a
p
a
c
i
t
y
(
b
y
t
e
s
)a
d
d
r
e
s
s
Y
Y
Y
Y
1
6
Reserved ROM area
a
d
d
r
e
s
s
Z
Z
Z
Z
1
6
Rev.3.20 2003.05.28 page 15 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 14 Memory map of special function register (SFR)
Note : Do not access to the SFR area including nothing.
0000
16
0001
16
0002
16
0003
16
0004
16
0005
16
0006
16
0007
16
0008
16
0009
16
000A
16
000B
16
000C
16
000D
16
000E
16
000F
16
0010
16
0011
16
0012
16
0013
16
0014
16
0015
16
0016
16
0017
16
0018
16
0019
16
001A
16
001B
16
001C
16
001D
16
001E
16
001F
16
Port P0 (P0)
Port P0 direction register (P0D)
Port P1 (P1)
Port P1 direction register (P1D)
Port P2 (P2)
Port P2 direction register (P2D)
Port P3 (P3)
Port P3 direction register (P3D)
Pull-up control register (PULL)
Transmit/Receive buffer register (TB/RB)
Serial I/O1 status register (SIO1STS)
Serial I/O1 control register (SIO1CON)
UART control register (UARTCON)
Baud rate generator (BRG)
Port P1P3 control register (P1P3C)
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002A
16
002B
16
002C
16
002D
16
002E
16
002F
16
0030
16
0031
16
0032
16
0033
16
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003A
16
003B
16
003C
16
003D
16
003E
16
003F
16
Timer count source set register (TCSS)
A-D conversion register (low-order) (ADL)
Prescaler 1 (PRE1)
Timer 1 (T1)
One-shot start register (ONS)
Timer X mode register
(TXM)
Prescaler X
(PREX)
Timer X
(TX)
Serial I/O2 control register (SIO2CON)
Serial I/O2 register (SIO2)
A-D control register (ADCON)
A-D conversion register (high-order) (ADH)
MISRG
Watchdog timer control register (WDTCON)
Interrupt edge selection register
(INTEDGE)
CPU mode register (CPUM)
Interrupt request register 1 (IREQ1)
Interrupt control register 1 (ICON1)
Timer A mode register (TAM)
Timer A (low-order) (TAL)
Timer A (high-order) (TAH)
Timer Y, Z mode register (TYZM)
Prescaler Y (PREY)
Timer Y secondary (TYS)
Timer Y primary (TYP)
Timer Y, Z waveform output control register (PUM)
Prescaler Z (PREZ)
Timer Z secondary (TZS)
Timer Z primary (TZP)
Interrupt request register 2 (IREQ2)
Interrupt control register 2 (ICON2)
Rev.3.20 2003.05.28 page 16 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
I/O Ports
[Direction registers] PiD
The I/O ports have direction registers which determine the input/
output direction of each pin. Each bit in a direction register corre-
sponds to one pin, and each pin can be set to be input or output.
When “1” is set to the bit corresponding to a pin, this pin becomes
an output port. When “0” is set to the bit, the pin becomes an in-
put port.
When data is read from a pin set to output, not the value of the pin
itself but the value of port latch is read. Pins set to input are float-
ing, and permit reading pin values.
If a pin set to input is written to, only the port latch is written to and
the pin remains floating.
[Pull-up control register] PULL
By setting the pull-up control register (address 001616), ports P0
and P3 can exert pull-up control by program. However, pins set to
output are disconnected from this control and cannot exert pull-up
control.
Note: P26/AN6, P27/AN7, P35 and P36 do not exist for the 32-pin
version.
Accordingly, the following settings are required;
. Set direction registers of ports P26 and P27 to output.
. Set direction registers of ports P35 and P36 to output.
[Port P1P3 control register] P1P3C
By setting the port P1P3 control register (address 001716), a
CMOS input level or a TTL input level can be selected for ports
P10, P12, P13, P36, and P37 by program.
Fig. 16 Structure of port P1P3 control register
Fig. 15 Structure of pull-up control register
Port P1P3 control register
(P1P3C: address 0017
16
, initial value: 00
16
)
b7 b0
P37/INT0 input level selection bit
0 : CMOS level
1 : TTL level
P36/INT1 input level selection bit
0 : CMOS level
1 : TTL level
P10,P12,P13 input level selection bit
0 : CMOS level
1 : TTL level
Not used
Note: Keep setting the P3
6
/INT
1
input level selection bit
to “0” (initial value) for 32-pin version.
Pull-up control register
(PULL: address 001616, initial value: 0016)
P0
0
pull-up control bit
b7 b0
0 : Pull-up Off
1 : Pull-up On
Note : Pins set to out
p
ut
p
orts are disconnected from
p
ull-u
p
control.
P3
7
pull-up control bit
P3
5
, P3
6
pull-up control bit
P3
4
pull-up control bit
P3
0
– P3
3
pull-up control bit
P0
4
– P0
7
pull-up control bit
P0
2
, P0
3
pull-up control bit
P0
1
pull-up control bit
Rev.3.20 2003.05.28 page 17 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Table 5 I/O port function table
Pin
P00/CNTR1
P01/TYOUT
P02/TZOUT
P03/TXOUT
P04–P07
P10/RxD1
P11/TxD1
P12/SCLK1/SCLK2
P13/SRDY1/SDATA2
P14/CNTR0
P20/AN0–
P27/AN7
P30–P35
P36/INT1
P37/INT0
Input/output
I/O individual
bits
I/O format
•CMOS compatible
input level
•CMOS 3-state output
(Note 1)
Non-port function
Key input interrupt
Timer X function output
Timer Y function output
Timer Z function output
Timer A function input
Serial I/O1 function
input/output
Serial I/O2 function
input/output
Timer X function input/output
A-D conversion input
External interrupt input
Related SFRs
Pull-up control register
Timer Y mode register
Timer Z mode register
Timer X mode register
Timer Y,Z waveform
output control register
Timer A mode register
Serial I/O1 control register
Serial I/O1 control register
Serial I/O2 control register
Timer X mode register
A-D control register
Interrupt edge selection
register
Diagram No.
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
Notes 1: Ports P10, P12, P13, P36, and P37 are CMOS/TTL level.
2: P26/AN6 and P27/AN7 do not exist for the 32-pin version.
3: P35 and P36/INT1 do not exist for the 32-pin version.
Name
I/O port P0
I/O port P1
I/O port P2
(Note 2)
I/O port P3
(Note 3)
Rev.3.20 2003.05.28 page 18 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 17 Block diagram of ports (1)
(6)Port P1
1
Data bus Port latch
Serial I/O1 output
P1
1
/T
x
D
1
P-channel output disable bit
(5)Port P1
0
(4)Ports P0
4–
P0
7
(1)Port P0
0
Direction
register
Data bus Port latch
Pull-up control
To key input interrupt
generating circuit
CNTR
1
interrupt input
(2)Ports P0
1,
P0
2
Programmable waveform generation mode
Timer output
(7)Port P1
2
Serial I/O1, serial I/O2 clock output
Serial I/O1 mode selection bit
Serial I/O1 enable bit
Serial I/O1 enable bit
Serial I/O1 synchronous
clock selection bit
S
CLK2
pin
selection bit
(3)Port P0
3
Direction
register
Data bus Port latch
Pull-up control
To key input interrupt
generating circuit
Direction
register
Data bus Port latch
Pull-up control
To key input interrupt
generating circuit
Timer output
P0
3
/TX
OUT
output valid
Direction
register
Data bus Port latch
Pull-up control
To key input interrupt
generating circuit
Direction
register
Data bus Port latch
Serial I/O1 enable bit
Receive enable bit
Serial I/O1 input
P1
0
, P1
2
, P1
3
input level
selection bit
Direction
register
Serial I/O1 enable bit
Transmit enable bit
Direction
register
Data bus Port latch
Serial I/O1, serial I/O2 clock input
P1
0
, P1
2
, P1
3
input level
selection bit
*
*
*P1
0
, P1
2
, P1
3
, P3
6
, and P3
7
input level are switched to the CMOS/TTL level by the port P1P3 control register.
P0
0
key-on wakeup
selection bit
When the TTL level is selected, there is no hysteresis characteristics.
Rev.3.20 2003.05.28 page 19 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 18 Block diagram of ports (2)
Pull-up control
INT interrupt input
P3 input level
selection bit
(11) Ports P3
0
–P3
5
Pull-up control
(9) Port P1
4
Data bus
Serial I/O1 ready output
Serial I/O2 output Serial I/O2 input
S
DATA2
pin selection bit
Port latch
Direction
register
S
DATA2
output in operation signal
CNTR
0
interrupt input
Pulse output mode
Timer output
P1
0
, P1
2
, P1
3
input level
selection bit
Serial I/O mode selection bit
Serial I/O1 enable bit
S
RDY1
output enable bit
P1
0
, P1
2
, P1
3
, P3
6
, and P3
7
input level are switched to the CMOS/TTL level by the port P1P3 control register.
Data bus Port
latch
Direction
register
Data bus Port
latch
Direction
register
Data bus Port latch
Direction
register
A-D converter input Analog input pin
selection bit
(12) Ports P3
6
, P3
7
Data bus Port
latch
Direction
register
*
*
(10) Ports P2
0
–P2
7
*
(8) Port P1
3
When the TTL level is selected
,
there is no h
y
steresis characteristics.
Rev.3.20 2003.05.28 page 20 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Interrupts
Interrupts occur by 15 different sources : 5 external sources, 9 in-
ternal sources and 1 software source.
Interrupt control
All interrupts except the BRK instruction interrupt have an interrupt
request bit and an interrupt enable bit, and they are controlled by
the interrupt disable flag. When the interrupt enable bit and the in-
terrupt request bit are set to “1” and the interrupt disable flag is set
to “0”, an interrupt is accepted.
The interrupt request bit can be cleared by program but not be set.
The interrupt enable bit can be set and cleared by program.
The reset and BRK instruction interrupt can never be disabled with
any flag or bit. All interrupts except these are disabled when the
interrupt disable flag is set.
When several interrupts occur at the same time, the interrupts are
received according to priority.
Interrupt operation
Upon acceptance of an interrupt the following operations are auto-
matically performed:
1. The processing being executed is stopped.
2. The contents of the program counter and processor status reg-
ister are automatically pushed onto the stack.
3. The interrupt disable flag is set and the corresponding interrupt
request bit is cleared.
4. Concurrently with the push operation, the interrupt destination
address is read from the vector table into the program counter.
■ Notes on use
When setting the followings, the interrupt request bit may be set to
“1”.
•When setting external interrupt active edge
Related register: Interrupt edge selection register (address
003A16)
Timer X mode register (address 2B 16)
Timer A mode register (address 1D16)
When not requiring the interrupt occurrence synchronized with
these setting, take the following sequence.
➀ Set the corresponding interrupt enable bit to “0” (disabled).
➁ Set the interrupt edge select bit (active edge switch bit) to “1”.
➂ Set the corresponding interrupt request bit to “0” after 1 or
more instructions have been executed.
➃ Set the corresponding interrupt enable bit to “1” (enabled).
Table 6 Interrupt vector address and priority
Vector addresses (Note 1)
High-order
Priority Low-order Interrupt request generating conditions RemarksInterrupt source
FFFC16
FFFA16
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
FFE216
FFE016
FFDE16
FFDC16
FFFD16
FFFB16
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFE316
FFE116
FFDF16
FFDD16
Note 1: Vector addressed contain internal jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
3: It is an interrupt which can use only for 36 pin version.
Non-maskable
Valid only when serial I/O1 is selected
Valid only when serial I/O1 is
selected
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt (valid at falling)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
STP release timer underflow
Non-maskable software interrupt
At reset input
At completion of serial I/O1 data receive
At completion of serial I/O1 transmit shift or
when transmit buffer is empty
At detection of either rising or falling edge of
INT0 input
At detection of either rising or falling edge of
INT1 input
At falling of conjunction of input logical level
for port P0 (at input)
At detection of either rising or falling edge of
CNTR0 input
At detection of either rising or falling edge of
CNTR1 input
At timer X underflow
At timer Y underflow
At timer Z underflow
At timer A underflow
At completion of transmit/receive shift
At completion of A-D conversion
At timer 1 underflow
Not available
At BRK instruction execution
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Reset (Note 2)
Serial I/O1 receive
Serial I/O1 transmit
INT0
INT1 (Note 3)
Key-on wake-up
CNTR0
CNTR1
Timer X
T imer Y
Timer Z
T imer A
Serial I/O2
A-D conversion
Timer 1
Reserved area
BRK instruction
Rev.3.20 2003.05.28 page 21 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 19 Interrupt control
Fig. 20 Structure of Interrupt-related registers
Interrupt disable flag I
Interrupt request
Interrupt request bit
Interrupt enable bit
BRK instruction
Reset
b7 b0
b7 b0
b7 b0
Interrupt edge selection register
INT
0
interrupt edge selection bit
0 : Falling edge active
1 : Rising edge active
INT
1
interrupt edge selection bit
0 : Falling edge active
1 : Rising edge active
Not used (returns “0” when read)
P0
0
key-on wakeup enable bit
0 : Key-on wakeup enabled
1 : Key-on wakeup disabled
(INTEDGE : address 003A
16
, initial value : 00
16
)
Interrupt request register 1
Serial I/O1 receive interrupt request bit
Serial I/O1 transmit interrupt request bit
INT
0
interrupt request bit
INT
1
interrupt request bit
Key-on wake up interrupt request bit
CNTR
0
interrupt request bit
CNTR
1
interrupt request bit
Timer X interrupt request bit 0 : No interrupt request issued
1 : Interrupt request issued
(IREQ1 : address 003C
16
, initial value : 00
16
)
b7 b0 Interrupt control register 1
Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit interrupt enable bit
INT
0
interrupt enable bit
INT
1
interrupt enable bit (Do not write “1” to this bit for 32-pin version)
Key-on wake up interrupt enable bit
CNTR
0
interrupt enable bit
CNTR
1
interrupt enable bit
Timer X interrupt enable bit 0 : Interrupts disabled
1 : Interrupts enabled
(ICON1 : address 003E
16
, initial value : 00
16
)
Interrupt request register 2
Timer Y interrupt request bit
Timer Z interrupt request bit
Timer A interrupt request bit
Serial I/O2 interrupt request bit
A-D conversion interrupt request bit
Timer 1 interrupt request bit
Not used (returns “0” when read) 0 : No interrupt request issued
1 : Interrupt request issued
(IREQ2 : address 003D
16
, initial value : 00
16
)
b7 b0 Interrupt control register 2
Timer Y interrupt enable bit
Timer Z interrupt enable bit
Timer A interrupt enable bit
Serial I/O2 interrupt enable bit
A-D conversion interrupt enable bit
Timer 1 interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit) 0 : Interrupts disabled
1 : Interrupts enabled
(ICON2 : address 003F
16
, initial value : 00
16
)
Rev.3.20 2003.05.28 page 22 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Key Input Interrupt (Key-On Wake-Up)
A key-on wake-up interrupt request is generated by applying “L”
level to any pin of port P0 that has been set to input mode.
In other words, it is generated when the AND of input level goes
from “1” to “0”. An example of using a key input interrupt is shown
in Figure 21, where an interrupt request is generated by pressing
one of the keys provided as an active-low key matrix which uses
ports P00 to P03 as input ports.
Fig. 21 Connection example when using key input interrupt and port P0 block diagram
Port PXx
“L” level output
PULL register
bit 3 = “0”
Port P0
7
latch
Port P0
7
Direction register = “1”
***
P0
7
output
Key input interrupt request
Port P0
Input read circuit
* P-channel transistor for pull-up
** CMOS output buffer
PULL register
bit 3 = “0”
Port P0
6
latch
Port P0
6
Direction register = “1”
***
P0
6
output
PULL register
bit 3 = “0”
Port P0
5
latch
Port P0
5
Direction register = “1”
***
P0
5
output
PULL register
bit 3 = “0”
Port P0
4
latch
Port P0
4
Direction register = “1”
***
P0
4
output
PULL register
bit 2 = “1”
Port P0
3
latch
Port P0
3
Direction register = “0”
***
P0
3
input
PULL register
bit 2 = “1”
Port P0
2
latch
Port P0
2
Direction register = “0”
***
P0
2
input
PULL register
bit 1 = “1”
Port P0
1
latch
Port P0
1
Direction register = “0”
***
P0
1
input
PULL register
bit 0 = “1”
Port P0
0
latch
Port P0
0
Direction register = “0”
***
P0
0
input
Falling edge
detection
Falling edge
detection
Falling edge
detection
Falling edge
detection
Falling edge
detection
Falling edge
detection
Falling edge
detection
Falling edge
detection
Port P0
0
key-on wakeup
selection bit
Rev.3.20 2003.05.28 page 23 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Timers
The 7540 Group has 5 timers: timer 1, timer A, timer X, timer Y
and timer Z.
The division ratio of every timer and prescaler is 1/(n+1) provided
that the value of the timer latch or prescaler is n.
All the timers are down count timers. When a timer reaches “0”, an
underflow occurs at the next count pulse, and the corresponding
timer latch is reloaded into the timer. When a timer underflows, the
interrupt request bit corresponding to each timer is set to “1”.
●Timer 1
Timer 1 is an 8-bit timer and counts the prescaler output.
When Timer 1 underflows, the timer 1 interrupt request bit is set to
“1”.
Prescaler 1 is an 8-bit prescaler and counts the signal which is the
oscillation frequency divided by 16.
Prescaler 1 and Timer 1 have the prescaler 1 latch and the timer 1
latch to retain the reload value, respectively. The value of
prescaler 1 latch is set to Prescaler 1 when Prescaler 1
underflows.The value of timer 1 latch is set to Timer 1 when Timer
1 underflows.
When writing to Prescaler 1 (PRE1) is executed, the value is writ-
ten to both the prescaler 1 latch and Prescaler 1.
When writing to Timer 1 (T1) is executed, the value is written to
both the timer 1 latch and Timer 1.
When reading from Prescaler 1 (PRE1) and Timer 1 (T1) is ex-
ecuted, each count value is read out.
Timer 1 always operates in the timer mode.
Prescaler 1 counts the signal which is the oscillation frequency di-
vided by 16. Each time the count clock is input, the contents of
Prescaler 1 is decremented by 1. When the contents of Prescaler
1 reach “0016”, an underflow occurs at the next count clock, and
the prescaler 1 latch is reloaded into Prescaler 1 and count contin-
ues. The division ratio of Prescaler 1 is 1/(n+1) provided that the
value of Prescaler 1 is n.
The contents of Timer 1 is decremented by 1 each time the under-
flow signal of Prescaler 1 is input. When the contents of Timer 1
reach “0016”, an underflow occurs at the next count clock, and the
timer 1 latch is reloaded into Timer 1 and count continues. The di-
vision ratio of Timer 1 is 1/(m+1) provided that the value of Timer
1 is m. Accordingly, the division ratio of Prescaler 1 and Timer 1 is
1/((n+1)✕(m+1)) provided that the value of Prescaler 1 is n and
the value of Timer 1 is m.
Timer 1 cannot stop counting by software.
●Timer A
Timer A is a 16-bit timer and counts the signal which is the oscil-
lation frequency divided by 16. When Timer A underflows, the
timer A interrupt request bit is set to “1”.
Timer A consists of the low-order of Timer A (TAL) and the high-or-
der of Timer A (TAH).
Timer A has the timer A latch to retain the reload value. The value
of timer A latch is set to Timer A at the timing shown below.
• When Timer A undeflows.
• When an active edge is input from CNTR1 pin (valid only when
period measurement mode and pulse width HL continuously mea-
surement mode).
When writing to both the low-order of Timer A (TAL) and the high-
order of Timer A (TAH) is executed, the value is written to both the
timer A latch and Timer A.
When reading from the low-order of Timer A (TAL) and the high-or-
der of Timer A (TAH) is executed, the following values are read out
according to the operating mode.
• In timer mode, event counter mode:
The count value of Timer A is read out.
• In period measurement mode, pulse width HL continuously mea-
surement mode:
The measured value is read out.
Be sure to write to/read out the low-order of Timer A (TAL) and the
high-order of Timer A (TAH) in the following order;
Read
Read the high-order of Timer A (TAH) first, and the low-order of
Timer A (TAL) next and be sure to read out both TAH and TAL.
Write
Write to the low-order of Timer A (TAL) first, and the high-order of
Timer A (TAH) next and be sure to write to both TAL and TAH.
Timer A can be selected in one of 4 operating modes by setting
the timer A mode register.
(1) Timer mode
Timer A counts the oscillation frequency divided by 16. Each time
the count clock is input, the contents of Timer A is decremented by
1. When the contents of Timer A reach “000016”, an underflow oc-
curs at the next count clock, and the timer A latch is reloaded into
Timer A. The division ratio of Timer A is 1/(n+1) provided that the
value of Timer A is n.
(2) Period measurement mode
In the period measurement mode, the pulse period input from the
P00/CNTR1 pin is measured.
CNTR1 interrupt request is generated at rising/falling edge of
CNTR1 pin input singal. Simultaneousuly, the value in the timer A
latch is reloaded inTimer A and count continues. The active edge
of CNTR1 pin input signal can be selected from rising or falling by
the CNTR1 active edge switch bit .The count value when trigger
input from CNTR1 pin is accepted is retained until Timer A is read
once.
Rev.3.20 2003.05.28 page 24 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
(3) Event counter mode
Timer A counts signals input from the P00/CNTR1 pin.
Except for this, the operation in event counter mode is the same
as in timer mode.
The active edge of CNTR1 pin input signal can be selected from
rising or falling by the CNTR1 active edge switch bit .
(4) Pulse width HL continuously measurement mode
In the pulse width HL continuously measurement mode, the pulse
width (“H” and “L” levels) input to the P00/CNTR1 pin is measured.
CNTR1 interrupt request is generated at both rising and falling
edges of CNTR1 pin input signal. Except for this, the operation in
pulse width HL continuously measurement mode is the same as in
period measurement mode.
The count value when trigger input from the CNTR1 pin is ac-
cepted is retained until Timer A is read once.
Timer A can stop counting by setting “1” to the timer A count stop
bit in any mode.
Also, when Timer A underflows, the timer A interrupt request bit is
set to “1”.
Note on Timer A is described below;
■ Note on Timer A
CNTR1 interrupt active edge selection
CNTR1 interrupt active edge depends on the CNTR1 active edge
switch bit.
When this bit is “0”, the CNTR1 interrupt request bit is set to “1” at
the falling edge of the CNTR1 pin input signal. When this bit is “1”,
the CNTR1 interrupt request bit is set to “1” at the rising edge of
the CNTR1 pin input signal.
However, in the pulse width HL continuously measurement mode,
CNTR1 interrupt request is generated at both rising and falling
edges of CNTR1 pin input signal regardless of the setting of
CNTR1 active edge switch bit.
Fig. 22 Structure of timer A mode register
Timer A mode register
(TAM : address 001D16, initial value: 0016)
b7 b0
Not used (return “0” when read)
Timer A operating mode bits
b5 b4
0 0 : Timer mode
0 1 : Period measurement mode
1 0 : Event counter mode
1 1 : Pulse width HL continuously
measurement mode
CNTR1 active edge switch bit
0 : Count at rising edge in event counter mode
Measure the falling edge period in period
measurement mode
Falling edge active for CNTR1 interrupt
1 : Count at falling edge in event counter mode
Measure the rising edge period in period
measurement mode
Rising edge active for CNTR1 interrupt
Timer A count stop bit
0 : Count start
1 : Count stop
●Timer X
Timer X is an 8-bit timer and counts the prescaler X output.
When Timer X underflows, the timer X interrupt request bit is set
to “1”.
Prescaler X is an 8-bit prescaler and counts the signal selected by
the timer X count source selection bit.
Prescaler X and Timer X have the prescaler X latch and the timer
X latch to retain the reload value, respectively. The value of
prescaler X latch is set to Prescaler X when Prescaler X
underflows.The value of timer X latch is set to Timer X when Timer
X underflows.
When writing to Prescaler X (PREX) is executed, the value is writ-
ten to both the prescaler X latch and Prescaler X.
When writing to Timer X (TX) is executed, the value is written to
both the timer X latch and Timer X.
When reading from Prescaler X (PREX) and Timer X (TX) is ex-
ecuted, each count value is read out.
Timer X can can be selected in one of 4 operating modes by set-
ting the timer X operating mode bits of the timer X mode register.
(1) Timer mode
Prescaler X counts the count source selected by the timer X count
source selection bits. Each time the count clock is input, the con-
tents of Prescaler X is decremented by 1. When the contents of
Prescaler X reach “0016”, an underflow occurs at the next count
clock, and the prescaler X latch is reloaded into Prescaler X and
count continues. The division ratio of Prescaler X is 1/(n+1) pro-
vided that the value of Prescaler X is n.
The contents of Timer X is decremented by 1 each time the under-
flow signal of Prescaler X is input. When the contents of Timer X
reach “0016”, an underflow occurs at the next count clock, and the
timer X latch is reloaded into Timer X and count continues. The di-
vision ratio of Timer X is 1/(m+1) provided that the value of Timer
X is m. Accordingly, the division ratio of Prescaler X and Timer X is
1/((n+1)✕(m+1)) provided that the value of Prescaler X is n and
the value of Timer X is m.
(2) Pulse output mode
In the pulse output mode, the waveform whose polarity is inverted
each time timer X underflows is output from the CNTR0 pin.
The output level of CNTR0 pin can be selected by the CNTR0 ac-
tive edge switch bit. When the CNTR0 active edge switch bit is “0”,
the output of CNTR0 pin is started at “H” level. When this bit is “1”,
the output is started at “L” level.
Also, the inverted waveform of pulse output from CNTR0 pin can
be output from TXOUT pin by setting “1” to the P03/TXOUT output
valid bit.
When using a timer in this mode, set the port P14 and P03 direc-
tion registers to output mode.
(3) Event counter mode
The timer A counts signals input from the P14/CNTR0 pin.
Except for this, the operation in event counter mode is the same
as in timer mode.
The active edge of CNTR0 pin input signal can be selected from
rising or falling by the CNTR0 active edge switch bit .
Rev.3.20 2003.05.28 page 25 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
(4) Pulse width measurement mode
In the pulse width measurement mode, the pulse width of the sig-
nal input to P14/CNTR0 pin is measured.
The operation of Timer X can be controlled by the level of the sig-
nal input from the CNTR0 pin.
When the CNTR0 active edge switch bit is “0”, the signal selected
by the timer X count source selection bit is counted while the input
signal level of CNTR0 pin is “H”. The count is stopped while the
pin is “L”. Also, when the CNTR0 active edge switch bit is “1”, the
signal selected by the timer X count source selection bit is
counted while the input signal level of CNTR0 pin is “L”. The count
is stopped while the pin is “H”.
Timer X can stop counting by setting “1” to the timer X count stop
bit in any mode.
Also, when Timer X underflows, the timer X interrupt request bit is
set to “1”.
Note on Timer X is described below;
■ Note on Timer X
CNTR0 interrupt active edge selection
CNTR0 interrupt active edge depends on the CNTR0 active edge
switch bit.
When this bit is “0”, the CNTR0 interrupt request bit is set to “1” at
the falling edge of CNTR0 pin input signal. When this bit is “1”, the
CNTR0 interrupt request bit is set to “1” at the rising edge of
CNTR0 pin input signal.
Fig. 23 Structure of timer X mode register
Fig. 24 Timer count source set register
Timer X mode register
(TXM : address 002B16, initial value: 0016)
CNTR0 active edge switch bit
0 : Interrupt at falling edge
Count at rising edge
(in event counter mode)
1 : Interrupt at rising edge
Count at falling edge
(in event counter mode)
Timer X operating mode bits
b1 b0
0 0 : Timer mode
0 1 : Pulse output mode
1 0 : Event counter mode
1 1 : Pulse width measurement mode
Not used (return “0” when read)
Timer X count stop bit
0 : Count start
1 : Count stop
b7 b0
P03/TXOUT output valid bit
0 : Output invalid (I/O port)
1 : Output valid (Inverted CNTR0 output)
Timer count source set register
(TCSS : address 002E
16
, initial value: 00
16
)
b7 b0
Timer X count source selection bits
b1 b0
0 0 : f(X
IN
)/16
0 1 : f(X
IN
)/2
1 0 : f(X
IN
) (Note 1)
1 1 : Not available
Timer Y count source selection bits
b3 b2
0 0 : f(X
IN
)/16
0 1 : f(X
IN
)/2
1 0 : Ring oscillator output (Note 2)
1 1 : Not available
Timer Z count source selection bits
b5 b4
0 0 : f(X
IN
)/16
0 1 : f(X
IN
)/2
1 0 : Timer Y underflow
1 1 : Not available
Fix this bit to “0”.
Not used (return “0” when read)
Notes 1: f(X
IN
) can be used as timer X count source when using
a ceramic resonator or ring oscillator.
Do not use it at RC oscillation.
2: System operates using a ring oscillator as a count source
by setting the ring oscillator to oscillation enabled by bit 3
of CPUM.
Rev.3.20 2003.05.28 page 26 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
●Timer Y
Timer Y is an 8-bit timer and counts the prescaler Y output.
When Timer Y underflows, the timer Y interrupt request bit is set to
“1”.
Prescaler Y is an 8-bit prescaler and counts the signal selected by
the timer Y count source selection bit.
Prescaler Y has the prescaler Y latch to retain the reload value.
Timer Y has the timer Y primary latch and timer Y secondary latch
to retain the reload value.
The value of prescaler Y latch is set to Prescaler Y when
Prescaler Y underflows.The value of timer Y primary latch or timer
Y secondary latch are set to Timer Y when Timer Y underflows.
As for the value to transfer to Timer Y, either of timer Y primary or
timer Y secondary is selected depending on the timer Y operating
mode.
When writing to Prescaler Y (PREY), timer Y primary (TYP) or
timer Y secondary (TYS) is executed, writing to “latch only” or
“latch and prescaler (timer)” can be selected by the setting value
of the timer Y write control bit. Be sure to set the timer Y write con-
trol bit because there are some notes according to the operating
mode.
When reading from Prescaler Y (PREY) is executed, the count
value of Prescaler Y is read out. When reading from timer Y pri-
mary (TYP) is executed, the count value of Timer Y is read out.
The count value of Timer Y can be read out by reading from the
timer Y primary (TYP) even when the value of timer Y primary
latch or timer Y secondary latch is counted. When reading the
timer Y secondary (TYS) is executed, the undefined value is read
out.
Timer Y can be selected in one of 2 operating modes by setting
the timer Y operating mode bits of the timer Y, Z mode register.
(1) Timer mode
Prescaler Y counts the count source selected by the timer Y count
source selection bits. Each time the count clock is input, the con-
tents of Prescaler Y is decremented by 1. When the contents of
Prescaler Y reach “0016”, an underflow occurs at the next count
clock, and the prescaler Y latch is reloaded into Prescaler Y. The
division ratio of Prescaler Y is 1/(n+1) provided that the value of
Prescaler Y is n.
The contents of Timer Y is decremented by 1 each time the under-
flow signal of Prescaler Y is input. When the contents of Timer Y
reach “0016”, an underflow occurs at the next count clock, and the
timer Y primary latch is reloaded into Timer Y and count continues.
(In the timer mode, the contents of timer Y primary latch is
counted. Timer Y secondary latch is not used in this mode.)
The division ratio of Timer Y is 1/(m+1) provided that the value of
Timer Y is m. Accordingly, the division ratio of Prescaler Y and
Timer Y is 1/((n+1)✕(m+1)) provided that the value of Prescaler Y
is n and the value of Timer Y is m.
In the timer mode, writing to “latch only” or “latches and Prescaler
Y and timer Y primary” can be selected by the setting value of the
timer Y write control bit.
(2) Programmable waveform generation mode
In the programmable waveform generation mode, timer counts the
setting value of timer Y primary and the setting value of timer Y
secondary alternately, the waveform inverted each time Timer Y
underflows is output from TYOUT pin.
When using this mode, be sure to set “1” to the timer Y write con-
trol bit to select “write to latch only”. Also, set the port P01 direction
registers to output mode.
The active edge of output waveform is set by the timer Y output
level latch (b5) of the timer Y, Z waveform output control register
(PUM). When “0” is set to b5 of PUM, “H” interval by the setting
value of TYP or “L” interval by the setting value of TYS is output
alternately. When “1” is set to b5 of PUM, “L” interval by the setting
value of TYP or “H” interval by the setting value of TYS is output
alternately.
Also, in this mode, the primary interval and the secondary interval
of the output waveform can be extended respectively for 0.5 cycle
of timer count source clock by setting the timer Y primary wave-
form extension control bit (b2) and the timer Y secondary
waveform extension control bit (b3) of PUM to “1”. As a result, the
waveforms of more accurate resolution can be output.
When b2 and b3 of PUM are used, the frequency and duty of the
output waveform are as follows;
Waveform frequency:
FYOUT=
Duty:
DYOUT=
TMYCL: Timer Y count source (frequency)
TYP: Timer Y primary (8bit)
TYS: Timer Y secondary (8bit)
EXPYP: Timer Y primary waveform extension control bit (1bit)
EXPYS: Timer Y secondary waveform extension control bit (1bit)
In the programmable waveform generation mode, when values of
the TYP, TYS, EXPYP and EXPYS are changed, the output wave-
form is changed at the beginning (timer Y primary waveform
interval) of waveform period.
When the count values are changed, set values to the TYS,
EXPYP and EXPYS first. After then, set the value to TYP. The val-
ues are set all at once at the beginning of the next waveform
period when the value is set to TYP. (When writing at timer stop is
executed, writing to TYP at last is required.)
Notes on programmable waveform generation mode is described
below;
2✕TMYCL
2✕(TYP+1)+2✕(TYS+1)+(EXPYP+EXPYS)
2✕(TYP+1)+EXPYP
(2✕(TYP+1)+EXPYP)+(2✕(TYS+1)+EXPYS)
Rev.3.20 2003.05.28 page 27 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
■ Notes on programmable generation waveform mode
• Count set value
In the programmable waveform generation mode, values of TYS,
EXPYP, and EXPYS are valid by writing to TYP because the set-
ting to them is executed all at once by writing to TYP. Even when
changing TYP is not required, write the same value again.
• Write timing to TYP
In the programmable waveform generation mode, when the set-
ting value is changed while the waveform is output, set by
software in order not to execute the writing to TYP and the timing
of timer underflow during the secondary interval simultanesously.
• Usage of waveform extension function
The waveform extension function by the timer Y waveform exten-
sion control bit can be used only when “0016” is set to Prescaler Y.
When the value other than “0016” is set to Prescaler Y, be sure to
set “0” to EXPYP and EXPYS.
• Timer Y write mode
When using this mode, be sure to set “1” to the timer Y write con-
trol bit to select “write to latch only”.
Timer Y can stop counting by setting “1” to the timer Y count stop
bit in any mode.
Also, when Timer Y underflows, the timer Y interrupt request bit is
set to “1”.
Timer Y reloads the value of latch when counting is stopped by the
timer Y count stop bit. (When timer is read out while timer is
stopped, the value of latch is read. The value of timer can be read
out only while timer is operating.)
Rev.3.20 2003.05.28 page 28 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
●Timer Z
Timer Z is an 8-bit timer and counts the prescaler Z output.
When Timer Z underflows, the timer Z interrupt request bit is set to
“1”.
Prescaler Z is an 8-bit prescaler and counts the signal selected by
the timer Z count source selection bit.
Prescaler Z has the prescaler Z latch to retain the reload value.
Timer Z has the timer Z primary latch and timer Z secondary latch
to retain the reload value.
The value of prescaler Z latch is set to Prescaler Z when Prescaler
Z underflows.The value of timer Z primary latch or timer Z second-
ary latch are set to Timer Z when Timer Z underflows.
As for the value to transfer to Timer Z, either of timer Z primary or
timer Z secondary is selected depending on the timer Z operating
mode.
When writing to Prescaler Z (PREZ), timer Z primary (TZP) or
timer Z secondary (TZS) is executed, writing to “latch only” or
“latches and Prescaler Z and Timer Z” can be selected by the set-
ting value of the timer Z write control bit. Be sure to set the write
control bit because there are some notes according to the operat-
ing mode.
When reading from Prescaler Z (PREZ) is executed, the count
value of Prescaler Z is read out. When reading from timer Z pri-
mary (TZP) is executed, the count value of Timer Z is read out.
The count value of Timer Z can be read out by reading from the
timer Z primary (TZP) even when the value of timer Z primary
latch or timer Z secondary latch is counted. When reading the
timer Z secondary (TZS) is executed, the undefined value is read
out.
Timer Z can be selected in one of 4 operating modes by setting
the timer Z operating mode bits of the timer Y, Z mode register.
(1) Timer mode
Prescaler Z counts the count source selected by the timer Z count
source selection bits. Each time the count clock is input, the con-
tents of Prescaler Z is decremented by 1. When the contents of
Prescaler Z reach “0016”, an underflow occurs at the next count
clock, and the prescaler Z latch is reloaded into Prescaler Z. The
division ratio of Prescaler Z is 1/(n+1) provided that the value of
Prescaler Z is n.
The contents of Timer Z is decremented by 1 each time the under-
flow signal of Prescaler Z is input. When the contents of Timer Z
reach “0016”, an underflow occurs at the next count clock, and the
timer Z primary latch is reloaded into Timer Z and count continues.
(In the timer mode, the contents of timer Z primary latch is
counted. Timer Z secondary latch is not used in this mode.)
The division ratio of Timer Z is 1/(m+1) provided that the value of
Timer Z is m. Accordingly, the division ratio of Prescaler Z and
Timer Z is 1/((n+1) ✕(m+1)) provided that the value of Prescaler Z
is n and the value of Timer Z is m.
In the timer mode, writing to “latch only” or “latches and Prescaler
Z and timer Z primary” can be selected by the setting value of the
timer Z write control bit.
(2) Programmable waveform generation mode
In the programmable waveform generation mode, timer counts the
setting value of timer Z primary and the setting value of timer Z
secondary alternately, the waveform inverted each time Timer Z
underflows is output from TZOUT pin.
When using this mode, be sure to set “1” to the timer Z write con-
trol bit to select “write to latch only”. Also, set the port P02 direction
registers to output mode.
The active edge of output waveform is set by the timer Z output
level latch (b4) of the timer Y, Z waveform output control register
(PUM). When “0” is set to b4 of PUM, “H” interval by the setting
value of TZP or “L” interval by the setting value of TZS is output al-
ternately. When “1” is set to b4 of PUM, “L” interval by the setting
value of TZP or “H” interval by the setting value of TZS is output
alternately.
Also, in this mode, the primary interval and the secondary interval
of the output waveform can be extended respectively for 0.5 cycle
of timer count source clock by setting the timer Z primary wave-
form extension control bit (b0) and the timer Z secondary
waveform extension control bit (b1) of PUM to “1”. As a result, the
waveforms of more accurate resolution can be output.
When b0 and b1 of PUM are used, the frequency and duty of the
output waveform are as follows;
Waveform frequency:
FZOUT=
Duty:
DZOUT=
TMZCL: Timer Z count source (frequency)
TZP: Timer Z primary (8bit)
TZS: Timer Z secondary (8bit)
EXPZP: Timer Z primary waveform extension control bit (1bit)
EXPZS: Timer Z secondary waveform extension control bit (1bit)
In the programmable waveform generation mode, when values of
the TZP, TZS, EXPZP and EXPZS are changed, the output wave-
form is changed at the beginning (timer Z primary waveform
interval) of waveform period.
When the count values are changed, set values to the TZS,
EXPZP and EXPZS first. After then, set the value to TZP. The val-
ues are set all at once at the beginning of the next waveform
period when the value is set to TZP. (When writing at timer stop is
executed, writing to TZP at last is required.)
2✕TMZCL
2✕(TZP+1)+2✕(TZS+1)+(EXPZP+EXPZS)
2✕(TZP+1)+EXPZP
(2✕(TZP+1)+EXPZP)+(2✕(TZS+1)+EXPZS
Rev.3.20 2003.05.28 page 29 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Notes on the programmable waveform generation mode are de-
scribed below;
■ Notes on programmable waveform generation mode
• Count set value
In the programmable waveform generation mode, values of TZS,
EXPZP, and EXPZS are valid by writing to TZP because the set-
ting to them is executed all at once by writing to TZP. Even when
changing TZP is not required, write the same value again.
• Write timing to TZP
In the programmable waveform generation mode, when the set-
ting value is changed while the waveform is output, set by
software in order not to execute the writing to TZP and the timing
of timer underflow during the secondary interval simultanesously.
• Usage of waveform extension function
The waveform extension function by the timer Z waveform exten-
sion control bit can be used only when “0016” is set to Prescaler Z.
When the value other than “0016” is set to Prescaler Z, be sure to
set “0” to EXPZP and EXPZS. Also, when the timer Y underflow is
selected as the count source, the waveform extension function
cannot be used.
• Timer Z write mode
When using this mode, be sure to set “1” to the timer Z write con-
trol bit to select “write to latch only”.
(3) Programmable one-shot generation mode
In the programmable one-shot generation mode, the one-shot
pulse by the setting value of timer Z primary can be output from
TZOUT pin by software or external trigger. When using this mode,
be sure to set “1” to the timer Z write control bit to select “write to
latch only”. Also, set the port P02 direction registers to output
mode. In this mode, TZS is not used.
The active edge of output waveform is set by the timer Z output
level latch (b5) of the timer Y, Z waveform output control register
(PUM). When “0” is set to b5 of PUM, “H” pulse during the interval
of the TZP setting value is output. When “1” is set to b5 of PUM,
“L” pulse during the interval of the TZP setting value is output.
Also, in this mode, the interval of the one-shot pulse output can be
extended for 0.5 cycle of timer count source clock by setting the
timer Z primary waveform extension control bit (b2) of PUM to “1”.
As a result, the waveforms of more accurate resolution can be
output.
In the programmable one-shot generation mode, the trigger by
software or the external INT0 pin can be accepted by writing “0” to
the timer Z count stop bit after the count value is set. (At the time
when “0” is written to the timer Z count stop bit, Timer Z stops.)
By writing “1” to the timer Z one-shot start bit, or by inputting the
valid trigger to the INT0 pin after the trigger to the INT0 pin be-
comes valid by writing “1” to the INT0 pin one-shot trigger control
bit, Timer Z starts counting, at the same time, the output of TZOUT
pin is inverted. When Timer Z underflows, the output of TZOUT pin
is inverted again and Timer Z stops. When also the trigger of INT0
pin is accepted, the contents of the one-shot start bit is changed to
“1” by hardware.
The falling or rising can be selected as the edge of the valid trig-
ger of INT0 pin by the INT0 pin one-shot trigger edge selection bit.
During the one-shot pulse output interval, the one-shot pulse out-
put can be stopped forcibly by writing “0” to the timer Z one-shot
start bit.
In the programmable one-shot generation mode, when the count
values are changed, set value to the EXPZP first. After then, set
the value to TZP. The values are set all at once at the beginning of
the next one-shot pulse when the value is set to TZP. (When writ-
ing at timer stop is executed, writing to TZP at last is required.)
Notes on the programmable one-shot generation mode are de-
scribed below;
■ Notes on programmable one-shot generation mode
• Count set value
In the programmable one-shot generation mode, the value of
EXPZP becomes valid by writing to TZP. Even when changing
TZP is not required, write the same value again.
• Write timing to TZP
In the programmable one-shot generation mode, when the setting
value is changed while the waveform is output, set by software in
order not to execute the writing to TZP and the timing of timer un-
derflow simultanesously.
• Usage of waveform extension function
The waveform extension function by the timer Z waveform exten-
sion control bit can be used only when “0016” is set to Prescaler Z.
When the value other than “0016” is set to Prescaler Z, be sure to
set “0” to EXPZP. Also, when the timer Y underflow is selected as
the count source, the waveform extension function cannot be
used.
• Timer Z write mode
When using this mode, be sure to set “1” to the timer Z write con-
trol bit to select “write to latch only”.
Rev.3.20 2003.05.28 page 30 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
(4) Programmable wait one-shot generation mode
In the programmable wait one-shot generation mode, the one-shot
pulse by the setting value of timer Z secondary can be output from
TZOUT pin by software or external trigger to INT0 pin after the wait
by the setting value of the timer Z primary. When using this mode,
be sure to set “1” to the timer Z write control bit to select “write to
latch only”. Also, set the port P02 direction registers to output
mode.
The active edge of output waveform is set by the timer Z output
level latch (b5) of the timer Y, Z waveform output control register
(PUM). When “0” is set to b5 of PUM, after the wait during the in-
terval of the TZP setting value, “H” pulse during the interval of the
TZS setting value is output. When “1” is set to b5 of PUM, after the
wait during the interval of the TZP setting value, “L” pulse during
the interval of the TZS setting value is output.
Also, in this mode, the intervals of the wait and the one-shot pulse
output can be extended for 0.5 cycle of timer count source clock
by setting EXPZP and EXPZS of PUM to “1”. As a result, the
waveforms of more accurate resolution can be output.
In the programmable one-shot generation mode, the trigger by
software or the external INT0 pin can be accepted by writing “0” to
the timer Z count stop bit after the count value is set. (At the time
when “0” is written to the timer Z count stop bit, Timer Z stops.)
By writing “1” to the timer Z one-shot start bit, or by inputting the
valid trigger to the INT0 pin after the trigger to the INT0 pin be-
comes valid by writing “1” to the INT0 pin one-shot trigger control
bit, Timer Z starts counting.
While Timer Z counts the TZP, the initial value of the TZOUT pin
output is retained. When Timer Z underflows, the value of TZS is
reloaded, at the same time, the output of TZOUT pin is inverted.
When Timer Z underflows, the output of TZOUT pin is inverted
again and Timer Z stops. When also the trigger of INT0 pin is ac-
cepted, the contents of the one-shot start bit is changed to “1” by
hardware.
The falling or rising can be selected as the edge of the valid trig-
ger of INT0 pin by the INT0 pin one-shot trigger edge selection bit.
During the wait interval and the one-shot pulse output interval, the
one-shot pulse output can be stopped forcibly by writing “0” to the
timer Z one-shot start bit.
In the programmable wait one-shot generation mode, when the
count values are changed, set values to the TZS, EXPZP and
EXPZS first. After then, set the value to TZP. The values are set all
at once at the beginning of the next wait interval when the value is
set to TZP. (When writing at timer stop is executed, writing to TZP
at last is required.)
Notes on the programmable wait one-shot generation mode are
described below;
■ Notes on programmable wait one-shot generation mode
• Count set value
In the programmable wait one-shot generation mode, values of
TZS, EXPZP and EXPZS are valid by writing to TZP. Even when
changing TZP is not required, write the same value again.
• Write timing to TZP
In the programmable wait one-shot generation mode, when the
setting value is changed while the waveform is output, set by soft-
ware in order not to execute the writing to TZP and the timing of
timer underflow during the secondary interval simultanesously.
• Usage of waveform extension function
The waveform extension function by the timer Z waveform exten-
sion control bit can be used only when “0016” is set to Prescaler Z.
When the value other than “0016” is set to Prescaler Z, be sure to
set “0” to EXPZP and EXPZS. Also, when the timer Y underflow is
selected as the count source, the waveform extension function
cannot be used.
• Timer Z write mode
When using this mode, be sure to set “1” to the timer Z write con-
trol bit to select “write to latch only”.
Timer Z can stop counting by setting “1” to the timer Z count stop
bit in any mode.
Also, when Timer Z underflows, the timer Z interrupt request bit is
set to “1”.
Timer Z reloads the value of latch when counting is stopped by the
timer Z count stop bit. (When timer is read out while timer is
stopped, the value of latch is read. The value of timer can be read
out only while timer is operating.)
Rev.3.20 2003.05.28 page 31 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 26 Structure of timer YZ waveform output control register
Fig. 27 Structure of one-shot start register
Fig. 25 Structure of timer Y, Z mode register
b7 b0
Timer Y, Z mode register
(TYZM : address 0020
16
, initial value: 00
16
)
Timer Y operating mode bit
0 : Timer mode
1 : Programmable waveform generation mode
Not used (return “0” when read)
Timer Y write control bit
0 : Write to latch and timer simultaneously
1 : Write to only latch
Timer Y count stop bit
0 : Count start
1 : Count stop
Timer Z operating mode bits
b5 b4
0 0 : Timer mode
0 1 : Programmable waveform generation mode
1 0 : Programmable one-shot generation mode
1 1 : Programmable wait one-shot generation mode
Timer Z write control bit
0 : Write to latch and timer simultaneously
1 : Write to only latch
Timer Z count stop bit
0 : Count start
1 : Count stop
b7 b0
Timer Y, Z waveform output control register
(PUM : address 0024
16
, initial value: 00
16
)
Timer Y primary waveform extension control bit
0 : Waveform not extended
1 : Waveform extended
Timer Y secondary waveform extension control bit
0 : Waveform not extended
1 : Waveform extended
Timer Z primary waveform extension control bit
0 : Waveform not extended
1 : Waveform extended
Timer Z secondary waveform extension control bit
0 : Waveform not extended
1 : Waveform extended
Timer Y output level latch
0 : “L” output
1 : “H” output
Timer Z output level latch
0 : “L” output
1 : “H” output
INT
0
pin one-shot trigger control bit
0 : INT
0
pin one-shot trigger invalid
1 : INT
0
pin one-shot trigger valid
INT
0
pin one-shot trigger active edge selection bit
0 : Falling edge trigger
1 : Rising edge trigger
b7 b0 One-shot start register
(ONS : address 002A16, initial value: 0016)
Timer Z one-shot start bit
0 : One-shot stop
1 : One-shot start
Not used (return “0” when read)
Rev.3.20 2003.05.28 page 32 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 28 Block diagram of timer 1 and timer A
Timer A (low-order) latch (8)
Timer A (low-order) (8)
Timer A (high-order) latch (8)
Timer A (high-order) (8)
Data bus
P00/CNTR1
CNTR1 active
edge switch bit
f(XIN)/16
Rising edge detected
Falling edge detected
Timer A operation mode bit
Timer A count
stop bit
Prescaler 1 latch (8)
Prescaler 1 (8)
Timer 1 latch (8)
Timer 1 (8)
f(XIN)/16
Data bus
Timer A interrupt
request bit
Timer 1 interrupt
request bit
Pulse width HL
continuously
measurement mode
Period measurement mode
Rev.3.20 2003.05.28 page 33 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 29 Block diagram of timer X, timer Y and timer Z
Q
QT
Toggle flip-flop
Timer Y count
stop bit
Programmable waveform
gengeration mode
f(X
IN
)/16
f(X
IN
)/2
Timer Y count
source selection bits
Waveform extension function
Timer Y primary waveform
extension control bit
P0
1
/TY
OUT
Timer Y output level latch
Q
QT
f(X
IN
)/16
Waveform extension function
Timer Z primary waveform
extenstion control bit
P0
2
/TZ
OUT
INT0
interrupt
request bit
P3
7
/INT
0
f(X
IN
)/2
Timer Z count
stop bit
Ring oscillator clock RING
(ring oscillator output
in Fig. 51, 52)
Q
Q
P1
4
/CNTR
0
R
T
f(X
IN
)/16
f(X
IN
)/2
Timer X
interrupt
request bit
Toggle flip-flop
Timer X count stop bit
Pulse width
measurement
mode
Event
counter
mode CNTR
0
interrupt
request bit
Pulse output mode
Port P1
4
latch
Port P1
4
direction
register
CNTR
0
active
edge switch bit
Timer mode
Pulse output
mode
CNTR
0
active
edge switch bit
Timer X count
source selection bits
f(X
IN
)
P0
3
/
TX
OUT
Prescaler X latch (8)
Prescaler X (8)
Timer X latch (8)
Timer X (8)
Data bus
“0”
“1”
“0”
“1”
Writing to timer X latch
Pulse output mode
P03/TXOUT output valid
Port P0
3
latch
Port P0
3
direction
register Prescaler Y latch (8)
Prescaler Y (8)
Timer Y primary latch (8)
Timer Y (8)
Data bus
Timer Y secondary latch (8)
Timer Y
interrupt
request bit
Port P0
1
latch
Port P0
1
direction
register
Timer Y secondary
waveform extension
control bit
Prescaler Z latch (8)
Prescaler Z (8)
Timer Z primary latch (8)
Timer Z (8)
Data bus
Timer Z secondary latch (8)
Timer Z
interrupt
request bit
Timer Z count
source selection bits
One-shot pulse
trigger input
INT0 pin trigger active edge
selection bit
Programmable one-shot generation mode
Programmable wait one-shot generation mode
Timer Z one-shot start bit
Timer Z secondary waveform
extenstion control bit
Port P0
2
latch
Port P0
2
direction
register
Toggle flip flop
Timer Z output
level latch
Programmable waveform generation mode
Programmable one-shot generation mode
Programmable wait one-shot generation mode
Rev.3.20 2003.05.28 page 34 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 30 Block diagram of clock synchronous serial I/O1
Fig. 31 Operation of clock synchronous serial I/O1 function
Serial I/O
●Serial I/O1
Serial I/O1 can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer is also provided for
baud rate generation.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O1 mode can be selected by setting
the serial I/O1 mode selection bit of the serial I/O1 control register
(bit 6) to “1”.
For clock synchronous serial I/O1, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB.
1/4
1/4
F/F
P12/SCLK1
Serial I/O1 status register
Serial I/O1 control register
P13/SRDY1
P10/RXD1
P11/TXD1
XIN
Receive buffer register
Address 001816
Receive shift register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Clock control circuit
Shift clock
Serial I/O1 synchronous
clock selection bit
Frequency division ratio 1/(n+1)
Baud rate generator
Address 001C16
BRG count source selection bit
Clock control circuit
Falling-edge detector
Transmit buffer register
Data bus Address 001816
Shift clock Transmit shift completion flag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
Transmit interrupt source selection bit
Address 001916
Data bus
Address 001A16
Transmit shift register
D
7
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
0
D
1
D
2
D
3
D
4
D
5
D
6
RBF = 1
TSC = 1
TBE = 0 TBE = 1
TSC = 0
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD
Serial input RxD
Write pulse to receive/transmit
buffer register (address 0018
16
)
Overrun error (OE)
detection
Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after
the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the
serial I/O1 control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial
data is output continuously from the TxD pin.
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Receive enable signal
S
RDY1
Rev.3.20 2003.05.28 page 35 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 32 Block diagram of UART serial I/O1
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by
clearing the serial I/O1 mode selection bit of the serial I/O1 control
register to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
XIN
1/4
OE
PE FE
1/16
1/16
Data bus
Receive buffer register
Address 001816
Receive shift register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Baud rate generator
Frequency division ratio 1/(n+1)
Address 001C16
ST/SP/PA generator
Transmit buffer register
Data bus
Transmit shift register
Address
0018
16
Transmit shift completion flag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
Address
0019
16
ST detector
SP detector UART control register
Address 001B
16
Character length selection bit
Address 001A16
BRG count source selection bit
Transmit interrupt source selection bit
Serial I/O1 synchronous clock selection bit
Clock control circuit
Character length selection bit
7 bits
8 bits
Serial I/O1 control register
P12/SCLK1
Serial I/O1 status register
P10/RXD1
P11/TXD1
The transmit and receive shift registers each have a buffer, but the
two buffers have the same address in memory. Since the shift reg-
ister cannot be written to or read from directly, transmit data is
written to the transmit buffer register, and receive data is read
from the receive buffer register.
The transmit buffer register can also hold the next data to be
transmitted, and the receive buffer register can hold a character
while the next character is being received.
Fig. 33 Operation of UART serial I/O1 function
TSC=0
TBE=1
RBF=0
TBE=0 TBE=0
RBF=1 RBF=1
STD0D1SP D0D1
ST SP
TBE=1 TSC=1
STD0D1SP D0D1
ST SP
Transmit or receive clock
Transmit buffer write
signal
Generated at 2nd bit in 2-stop-bit mode
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit (s)
1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).
2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit
interrupt source selection bit (TIC) of the serial I/O1 control register.
3: The receive interrupt (RI) is set when the RBF flag becomes “1.”
4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0.
Notes
✽
✽
Serial output TXD
Serial input RXD
Receive buffer read
signal
Rev.3.20 2003.05.28 page 36 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
[Transmit buffer register/receive buffer register (TB/RB)]
001816
The transmit buffer register and the receive buffer register are lo-
cated at the same address. The transmit buffer is write-only and
the receive buffer is read-only. If a character bit length is 7 bits, the
MSB of data stored in the receive buffer is “0”.
[Serial I/O1 status register (SIO1STS)] 001916
The read-only serial I/O1 status register consists of seven flags
(bits 0 to 6) which indicate the operating status of the serial I/O1
function and various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is cleared to “0” when the receive
buffer register is read.
If there is an error, it is detected at the same time that data is
transferred from the receive shift register to the receive buffer reg-
ister, and the receive buffer full flag is set. A write to the serial I/O1
status register clears all the error flags OE, PE, FE, and SE (bit 3
to bit 6, respectively). Writing “0” to the serial I/O1 enable bit SIOE
(bit 7 of the serial I/O1 control register) also clears all the status
flags, including the error flags.
Bits 0 to 6 of the serial I/O1 status register are initialized to “0” at
reset, but if the transmit enable bit of the serial I/O1 control regis-
ter has been set to “1”, the transmit shift completion flag (bit 2)
and the transmit buffer empty flag (bit 0) become “1”.
[Serial I/O1 control register (SIO1CON)] 001A16
The serial I/O1 control register consists of eight control bits for the
serial I/O1 function.
[UART control register (UARTCON)] 001B16
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set
the data format of an data transfer and one bit (bit 4) which is al-
ways valid and sets the output structure of the P11/TXD1 pin.
[Baud rate generator (BRG)] 001C16
The baud rate generator determines the baud rate for serial transfer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate generator.
■ Notes on serial I/O
• Serial I/O interrupt
When setting the transmit enable bit to “1”, the serial I/O transmit
interrupt request bit is automatically set to “1”. When not requiring
the interrupt occurrence synchronized with the transmission en-
abled, take the following sequence.
➀ Set the serial I/O transmit interrupt enable bit to “0” (disabled).
➁ Set the transmit enable bit to “1”.
➂ Set the serial I/O transmit interrupt request bit to “0” after 1 or
more instructions have been executed.
➄ Set the serial I/O transmit interrupt enable bit to “1” (enabled).
• I/O pin function when serial I/O1 is enabled.
The functions of P12 and P13 are switched with the setting values
of a serial I/O1 mode selection bit and a serial I/O1 synchronous
clock selection bit as follows.
(1) Serial I/O1 mode selection bit → “1” :
Clock synchronous type serial I/O is selected.
Setup of a serial I/O1 synchronous clock selection bit
“0” : P12 pin turns into an output pin of a synchronous clock.
“1” : P12 pin turns into an input pin of a synchronous clock.
Setup of a SRDY1 output enable bit (SRDY)
“0” : P13 pin can be used as a normal I/O pin.
“1” : P13 pin turns into a SRDY output pin.
(2) Serial I/O1 mode selection bit → “0” :
Clock asynchronous (UART) type serial I/O is selected.
Setup of a serial I/O1 synchronous clock selection bit
“0”: P12 pin can be used as a normal I/O pin.
“1”: P12 pin turns into an input pin of an external clock.
When clock asynchronous (UART) type serial I/O is selected, it is
P13 pin. It can be used as a normal I/O pin.
Rev.3.20 2003.05.28 page 37 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 34 Structure of serial I/O1-related registers
b7
b7
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
Overrun error flag (OE)
0: No error
1: Overrun error
Parity error flag (PE)
0: No error
1: Parity error
Framing error flag (FE)
0: No error
1: Framing error
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Not used (returns “1” when read)
Serial I/O1 status register
Serial I/O1 control register
b0 b0
BRG count source selection bit (CSS)
0: f(XIN)
1: f(XIN)/4
Serial I/O1 synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O is selected, BRG output divided by 16
when UART is selected.
1: External clock input when clock synchronous serial
I/O is selected, external clock input divided by 16
when UART is selected.
SRDY1 output enable bit (SRDY)
0: P13 pin operates as ordinary I/O pin
1: P13 pin operates as SRDY1 output pin
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Serial I/O1 mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
Serial I/O1 enable bit (SIOE)
0: Serial I/O1 disabled
(pins P10 to P13 operate as ordinary I/O pins)
1: Serial I/O1 enabled
(pins P10 to P13operate as serial I/O pins)
b7 UART control register
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P11/TXD1 P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Not used (return “1” when read)
b0
(SIO1STS : address 001916, initial value: 0016) (SIO1CON : address 001A 16, initial value: 0016)
(UARTCON : address 001B 16, initial value: E016)
Rev.3.20 2003.05.28 page 38 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
●Serial I/O2
The serial I/O2 function can be used only for clock synchronous
serial I/O.
For clock synchronous serial I/O2 the transmitter and the receiver
must use the same clock. When the internal clock is used, transfer
is started by a write signal to the serial I/O2 register.
Note: Serial I/O2 can be used in the following cases;
(1) Serial I/O1 is not used,
(2) Serial I/O1 is used as UART and BRG output divided by 16 is
selected as the synchronized clock.
[Serial I/O2 control register] SIO2CON
The serial I/O2 control register contains 8 bits which control vari-
ous serial I/O functions.
• Set “0” to bit 3 to receive.
• At reception, clear bit 7 to “0” by writing a dummy data to the se-
rial I/O2 register after completion of shift.
Fig. 35 Structure of serial I/O2 control registers
Fig. 36 Block diagram of serial I/O2
Internal synchronous clock selection bits
000 : f(XIN)/8
001 : f(XIN)/16
010 : f(XIN)/32
011 : f(XIN)/64
110 : f(XIN)/128
111 : f(XIN)/256
b7 b0
Not used
(returns “0” when read)
Transfer direction selection bit
0 : LSB first
1 : MSB first
SCLK2 pin selection bit
0 : External clock (SCLK2 is an input)
1 : Internal clock (SCLK2 is an output)
Transmit / receive shift completion flag
0 : shift in progress
1 : shift completed
Note : When using it as a SDATA input, set the port P13
direction register to “0”.
Serial I/O2 control register
(SIO2CON: address 003016, initila value: 0016)
SDATA2 pin selection bit (Note)
0 : I/O port / SDATA2 input
1 : SDATA2 output
“1”
“0”
“0”
“1”
“0”
“1”
1/8
1/16
1/32
1/64
1/128
1/256
X
IN
Data bus
Serial I/O2
interrupt request
S
DATA2
pin selection bit
Serial I/O counter 2 (3)
Serial I/O shift register 2 (8)
S
CLK2
pin selection bit
Internal synchronous
clock selection bits
Divider
P1
2
/S
CLK2
P1
3
/S
DATA2
P1
2
latch
S
CLK2 pin
selection bit
S
CLK
P1
3
latch
S
DATA2
pin selection bit
Rev.3.20 2003.05.28 page 39 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Serial I/O2 operation
By writing to the serial I/O2 register (address 003116) the serial I/
O2 counter is set to “7”.
After writing, the SDATA2 pin outputs data every time the transfer
clock shifts from “H” to “L”. And, as the transfer clock shifts from
“L” to “H”, the SDATA2 pin reads data, and at the same time the
contents of the serial I/O2 register are shifted by 1 bit.
When the internal clock is selected as the transfer clock source,
the following operations execute as the transfer clock counts up to
8.
• Serial I/O2 counter is cleared to “0”.
• Transfer clock stops at an “H” level.
• Interrupt request bit is set.
• Shift completion flag is set.
Also, the SDATA2 pin is in a high impedance state after the data
transfer is completed (refer to Fig.37).
When the external clock is selected as the transfer clock source,
the interrupt request bit is set as the transfer clock counts up to 8,
but external control of the clock is required since it does not stop.
Notice that the SDATA2 pin is not in a high impedance state on the
completion of data transfer.
Also, after the receive operation is completed, the transmit/receive
shift completion flag is cleared by reading the serial I/O2 register.
At transmit, the transmit/receive shift completion flag is cleared
and the transmit operation is started by writing to serial I/O2 regis-
ter.
Fig. 37 Serial I/O2 timing (LSB first)
D0
Note :
Synchronous clock
Serial I/O2 register
write signal
Transfer clock
(Note)
SDATA2 at serial I/O2
input receive
SDATA2 at serial I/O2
output transmit
Serial I/O2 interrupt request bit set
Transmit/receive shift completion flag set
D1D2D3D4D5D6D7
When the internal clock is selected as the transfer and the direction register of P1 3/SDATA2 pin is set to the input mode,
the SDATA2 pin is in a high impedance state after the data transfer is completed.
Rev.3.20 2003.05.28 page 40 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
A-D Converter
The functional blocks of the A-D converter are described below.
[A-D conversion register] AD
The A-D conversion register is a read-only register that stores the
result of A-D conversion. Do not read out this register during an A-
D conversion.
[A-D control register] ADCON
The A-D control register controls the A-D converter. Bit 2 to 0 are
analog input pin selection bits. Bit 4 is the AD conversion comple-
tion bit. The value of this bit remains at “0” during A-D conversion,
and changes to “1” at completion of A-D conversion.
A-D conversion is started by setting this bit to “0”.
[Comparison voltage generator]
The comparison voltage generator divides the voltage between
AVSS and VREF by 1024, and outputs the divided voltages.
[Channel selector]
The channel selector selects one of ports P27/AN7 to P20/AN0,
and inputs the voltage to the comparator.
[Comparator and control circuit]
The comparator and control circuit compares an analog input volt-
age with the comparison voltage and stores its result into the A-D
conversion register. When A-D conversion is completed, the con-
trol circuit sets the AD conversion completion bit and the AD
interrupt request bit to “1”. Because the comparator is constructed
linked to a capacitor, set f(XIN) to 500 kHz or more during A-D con-
version.
Fig. 38 Structure of A-D control register
Fig. 39 Structure of A-D conversion register
Fig. 40 Block diagram of A-D converter
A-D control register
(ADCON : address 003416, initial value: 1016)
Not used (returns “0” when read)
Not used (returns “0” when read)
AD conversion completion bit
0 : Conversion in progress
1 : Conversion completed
b7 b0
Analog input pin selection bits
000 : P20/AN0
001 : P21/AN1
010 : P22/AN2
011 : P23/AN3
100 : P24/AN4
101 : P25/AN5
110 : P26/AN6 (Note)
111 : P27/AN7 (Note)
Note: These can be used only for 36 pin version.
Read 8-bit (Read only address 0035
16
)
b7 b0
b9 b8 b7 b6 b5 b4 b3 b2
(Address 0035
16
)
Read 10-bit (read in order address 0036
16
, 0035
16
)
b7 b0
b9 b8
(Address 0036
16
)
b7 b0
b7 b6 b5 b4 b3 b2 b1 b0
(Address 0035
16
)
Note: High-order 6-bit of address 0036
16
returns “0” when read.
A-D control register
(Address 0034
16
)
Channel selector
A-D control circuit
Resistor ladder
V
REF
Comparator
A-D interrupt request
b7 b0
Data bus
3
10
P2
0
/AN
0
P2
1
/AN
1
P2
2
/AN
2
P2
3
/AN
3
P2
4
/AN
4
P2
5
/AN
5
P2
6
/AN
6
P2
7
/AN
7
A-D conversion register (low-order)
(Address 0036
16
)
(Address 0035
16
)
A-D conversion register (high-order)
V
SS
Rev.3.20 2003.05.28 page 41 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Watchdog Timer
The watchdog timer gives a means for returning to a reset status
when the program fails to run on its normal loop due to a runaway.
The watchdog timer consists of an 8-bit watchdog timer H and an
8-bit watchdog timer L, being a 16-bit counter.
Standard operation of watchdog timer
The watchdog timer stops when the watchdog timer control regis-
ter (address 003916) is not set after reset. Writing an optional
value to the watchdog timer control register (address 003916)
causes the watchdog timer to start to count down. When the
watchdog timer H underflows, an internal reset occurs. Accord-
ingly, it is programmed that the watchdog timer control register
(address 003916) can be set before an underflow occurs.
When the watchdog timer control register (address 003916) is
read, the values of the high-order 6-bit of the watchdog timer H,
STP instruction disable bit and watchdog timer H count source se-
lection bit are read.
Initial value of watchdog timer
By a reset or writing to the watchdog timer control register (ad-
dress 003916), the watchdog timer H is set to “FF16” and the
watchdog timer L is set to “FF16”.
Operation of watchdog timer H count source selection bit
A watchdog timer H count source can be selected by bit 7 of the
watchdog timer control register (address 003916). When this bit is
“0”, the count source becomes a watchdog timer L underflow sig-
nal. The detection time is 131.072 ms at f(XIN)=8 MHz.
When this bit is “1”, the count source becomes f(XIN)/16. In this
case, the detection time is 512 µs at f(XIN)=8 MHz.
This bit is cleared to “0” after reset.
Operation of STP instruction disable bit
When the watchdog timer is in operation, the STP instruction can
be disabled by bit 6 of the watchdog timer control register (ad-
dress 003916).
When this bit is “0”, the STP instruction is enabled.
When this bit is “1”, the STP instruction is disabled, and an inter-
nal reset occurs if the STP instruction is executed.
Once this bit is set to “1”, it cannot be changed to “0” by program.
This bit is cleared to “0” after reset.
Fig. 41 Block diagram of watchdog timer
Fig. 42 Structure of watchdog timer control register
X
IN
Data bus
“0”
“1”
1/16
Watchdog timer H count
source selection bit
Reset
circuit
STP Instruction disable bit
Watchdog timer H (8)
Write "FF
16
" to the
watchdog timer
control register
Internal reset
RESET
Watchdog timer L (8)
STP Instruction
Write “FF
16
” to the
watchdog timer
control register
Watchdog timer control register
(WDTCON: address 0039
16
, initial value: 3F
16
)
Watchdog timer H (read only for high-order 6-bit)
STP instruction disable bit
0 : STP instruction enabled
1 : STP instruction disabled
Watchdog timer H count source selection bit
0 : Watchdog timer L underflow
1 : f(X
IN
)/16
b7 b0
Rev.3.20 2003.05.28 page 42 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Reset Circuit
The microcomputer is put into a reset status by holding the RE-
SET pin at the “L” level for 2 µs or more when the power source
voltage is 2.2 to 5.5 V and XIN is in stable oscillation.
After that, this reset status is released by returning the RESET pin
to the “H” level. The program starts from the address having the
contents of address FFFD16 as high-order address and the con-
tents of address FFFC16 as low-order address.
In the case of f(φ) ≤ 6 MHz, the reset input voltage must be 0.9 V
or less when the power source voltage passes 4.5 V.
In the case of f(φ) ≤ 4 MHz, the reset input voltage must be 0.8 V
or less when the power source voltage passes 4.0 V.
In the case of f(φ) ≤ 2 MHz, the reset input voltage must be 0.48 V
or less when the power source voltage passes 2.4 V.
In the case of f(φ) ≤ 1 MHz, the reset input voltage must be 0.44 V
or less when the power source voltage passes 2.2 V.
Fig. 43 Example of reset circuit
Fig. 44 Timing diagram at reset
(Note)
0.2 VCC
0 V
0 V
Poweron
VCCRESET
VCC
RESET
Power source
voltage
detection circuit
Power source
voltage
Reset input
voltage
Note : Reset release voltage Vcc = 2.2 V
Data
Address
8-13 clock cycles
Reset address from the
vector table
1 : A built-in ring oscillator applies about RING•2 MHz, φ•250 kHz frequency clock
at average of Vcc = 5 V.
2 : The mark “?” means that the address is changeable depending on the previous state.
3 : These are all internal signals except RESET.
Notes
?? FFFC FFFD ADH,ADL
???
?? ADLADH???
Clock from built-in
ring oscillator RING
φ
RESET
RESETOUT
SYNC
Rev.3.20 2003.05.28 page 43 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 45 Internal status of microcomputer at reset
Prescaler 1
Timer 1
One-shot start register
Timer X mode register
Prescaler X
Timer X
Timer count source set register
Serial I/O2 control register
A-D control register
MISRG
Watchdog timer control register
Interrupt edge selection register
CPU mode register
Interrupt request register 1
Interrupt control register 1
Processor status register
Program counter
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
(25)
(26)
Contents of address FFFC
16
(PCH)
(PCL)
FF
16
0116
0016
0016
FF16
FF16
0016
0016
1016
0016
002816
002916
002A16
002B16
002C16
002D16
002E16
003016
003416
003816
003916
003A16
003B16
003C16
003E16
(PS)
Note X : Undefined
Contents of address FFFD
16
00111111
0016
0016
0016
10000000
XXXXX1XX
Port P0 direction register
Port P1 direction register
Port P2 direction register
Port P3 direction register
Pull-up control register
(1)
(2)
(3)
(4)
(5)
Register contents
0016
0016
0016
0016
000116
000316
000516
000716
001616
Serial I/O1 control register
UART control register
(8)
(9)
Serial I/O1 status register
(7)
001A16
001B16
0016
11100000
001916 10000000
XXX0 0000
Address
Port P1P3 control register
(6) 001716 0016
Timer A mode register
Timer A (low-order)
Timer A (high-order)
0016
FF16
FF16
001D16
001E16
001F16
Timer Y, Z mode register
Prescaler Y
Timer Y secondary
0016
FF16
FF16
002016
002116
002216
Timer Y primary
Timer Y, Z waveform output control register
Prescaler Z
FF16
0016
FF16
002316
002416
002516
Timer Z secondary FF16
002616
Timer Z primary FF16
002716
(27)
(28)
(29)
(30)
(31)
(32)
(33)
(34)
(35)
(36)
Serial I/O2 register 0016
003116
Interrupt request register 2 003D16 0016
Interrupt control register 2 003F16 0016
(37)
(38)
(39)
(40)
Rev.3.20 2003.05.28 page 44 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 46 External circuit of ceramic resonator
Fig. 47 External circuit of RC oscillation
XI
N
CO
U
T
CIN
XO
U
T
M
3
7
5
4
0
R
d
XI
N
XO
U
T
C
R
M
3
7
5
4
0
Fig. 48 External clock input circuit
X
IN
X
O
U
T
E
x
t
e
r
n
a
l
o
s
c
i
l
l
a
t
i
o
n
c
i
r
c
u
i
t
V
CC
V
SS
O
p
e
n
M37540
X
I
N
X
O
U
T
M
3
7
5
4
0
Open
Fig. 49 Processing of XIN and XOUT pins at ring oscillator op-
eration
Clock Generating Circuit
An oscillation circuit can be formed by connecting a resonator be-
tween XIN and XOUT, and an RC oscillation circuit can be formed
by connecting a resistor and a capacitor.
Use the circuit constants in accordance with the resonator
manufacturer's recommended values.
(1) Ring oscillator operation
When the MCU operates by the ring oscillator for the main clock,
connect XIN pin to VSS and leave XOUT pin open.
The clock frequency of the ring oscillator depends on the supply
voltage and the operation temperature range.
Be careful that variable frequencies when designing application
products.
(2) Ceramic resonator
When the ceramic resonator is used for the main clock, connect
the ceramic resonator and the external circuit to pins XIN and
XOUT at the shortest distance. A feedback resistor is built in be-
tween pins XIN and XOUT.
(3) RC oscillation
When the RC oscillation is used for the main clock, connect the
XIN pin and XOUT pin to the external circuit of resistor R and the
capacitor C at the shortest distance.
The frequency is affected by a capacitor, a resistor and a micro-
computer.
So, set the constants within the range of the frequency limits.
(4) External clock
When the external signal clock is used for the main clock, connect
the XIN pin to the clock source and leave XOUT pin open.
Externally connect a
damping resistor Rd de-
pending on the
oscillation frequency.
(A feedback resistor is
built-in.)
Use the resonator
manufacturer’s recom-
mended value because
constants such as ca-
pacitance depend on the
resonator.
Note:
Connect the external
circuit of resistor R
and the capacitor C at
the shortest distance.
The frequency is af-
fected by a capacitor,
a resistor and a micro-
computer.
So, set the constants
within the range of the
frequency limits.
Note:
The clock frequency of the
ring oscillator depends on
the supply voltage and the
operation temperature
range.
Be careful that variable fre-
quencies and obtain the
sufficient margin.
Note:
Rev.3.20 2003.05.28 page 45 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
● Oscillation stop detection circuit (Note)
The oscillation stop detection circuit is used for reset occurrence
when a ceramic resonator or an oscillation circuit stops by discon-
nection. When internal reset occurs, reset because of oscillation
stop can be detected by setting “1” to the oscillation stop detection
status bit.
Also, when using the oscillation stop detection circuit, a built-in
ring oscillator is required.
Figure 53 shows the state transition.
Note: The oscillation stop detection circuit is not included in the
emulator MCU “M37540RSS”.
Fig. 50 Structure of MISRG
MISRG(address 0038
16
, initial value: 00
16
)
b7 b0
Oscillation stabilization time set bit after
release of the STP instruction
0: Set “01
16
” in timer1, and “FF
16
”
in prescaler 1 automatically
1: Not set automatically
Ceramic or RC oscillation stop detection
function active bit
0: Detection function inactive
1: Detection function active
Reserved bits (return “0” when read)
(Do not write “1” to these bits)
Not used (return “0” when read)
Oscillation stop detection status bit
0: Oscillation stop not detected
1: Oscillation stop detected
(1) Oscillation control
• Stop mode
When the STP instruction is executed, the internal clock φ stops at
an “H” level and the XIN oscillator stops. At this time, timer 1 is set
to “0116” and prescaler 1 is set to “FF16” when the oscillation sta-
bilization time set bit after release of the STP instruction is “0”. On
the other hand, timer 1 and prescaler 1 are not set when the
above bit is “1”. Accordingly, set the wait time fit for the oscillation
stabilization time of the oscillator to be used. f(XIN)/16 is forcibly
connected to the input of prescaler 1. When an external interrupt
is accepted, oscillation is restarted but the internal clock φ remains
at “H” until timer 1 underflows. As soon as timer 1 underflows, the
internal clock φ is supplied. This is because when a ceramic oscil-
lator is used, some time is required until a start of oscillation. In
case oscillation is restarted by reset, no wait time is generated. So
apply an “L” level to the RESET pin while oscillation becomes
stable.
Also, the STP instruction cannot be used while CPU is operating
by a ring oscillator.
• Wait mode
If the WIT instruction is executed, the internal clock φ stops at an
“H” level, but the oscillator does not stop. The internal clock re-
starts if a reset occurs or when an interrupt is received. Since the
oscillator does not stop, normal operation can be started immedi-
ately after the clock is restarted. To ensure that interrupts will be
received to release the STP or WIT state, interrupt enable bits
must be set to “1” before the STP or WIT instruction is executed.
■ Notes on clock generating circuit
For use with the oscillation stabilization set bit after release of the
STP instruction set to “1”, set values in timer 1 and prescaler 1 af-
ter fully appreciating the oscillation stabilization time of the
oscillator to be used.
• Switch of ceramic and RC oscillations
After releasing reset the operation starts by starting a built-in ring
oscillator. Then, a ceramic oscillation or an RC oscillation is se-
lected by setting bit 5 of the CPU mode register.
• Double-speed mode
When a ceramic oscillation is selected, a double-speed mode can
be used. Do not use it when an RC oscillation is selected.
• CPU mode register
Bits 5, 1 and 0 of CPU mode register are used to select oscillation
mode and to control operation modes of the microcomputer. In or-
der to prevent the dead-lock by error-writing (ex. program
run-away), these bits can be rewritten only once after releasing re-
set. After rewriting it is disable to write any data to the bit. (The
emulator MCU “M37540RSS” is excluded.)
Also, when the read-modify-write instructions (SEB, CLB) are ex-
ecuted to bits 2 to 4, 6 and 7, bits 5, 1 and 0 are locked.
• Clock division ratio, XIN oscillation control, ring oscillator control
The state transition shown in Fig. 52 can be performed by setting
the clock division ratio selection bits (bits 7 and 6), XIN oscillation
control bit (bit 4), ring oscillator oscillation control bit (bit 3) of CPU
mode register. Be careful of notes on use in Fig. 52.
Rev.3.20 2003.05.28 page 46 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 51 Block diagram of internal clock generating circuit (for ceramic resonator)
Fig. 52 Block diagram of internal clock generating circuit (for RC oscillation)
S
R
QS
R
Q
1
/
2
R
S
Q
R
f
1/4 1/2
WIT
instruction STP instruction
Timing φ
(Internal clock)
S
T
P
i
n
s
t
r
u
c
t
i
o
n
Interrupt request
Reset
Interrupt disable flag l
High-speed mode
M
i
d
d
l
e
-
s
p
e
e
d
m
o
d
e
P
r
e
s
c
a
l
e
r
1T
i
m
e
r
1
Main clock division
ratio selection bit
Doubl e- speed mode
Ring osci l lat or mod e
R
i
n
g
o
s
c
i
l
l
a
t
o
r
R
I
N
G
XO
U
TXI
N
1
/
8
M
a
i
n
c
l
o
c
k
d
i
v
i
s
i
o
n
r
a
t
i
o
s
e
l
e
c
t
i
o
n
b
i
t
M
i
d
d
l
e
-
,
h
i
g
h
-
,
l
o
w
-
s
p
e
e
d
m
o
d
e
R
i
n
g
o
s
c
i
l
l
a
t
o
r
m
o
d
e
R
E
S
E
T
S
R
QS
R
Q
1
/
2
R
S
Q
1/4 1
/
2
W
I
T
i
n
s
t
r
u
c
t
i
o
nSTP instruction
T
i
m
i
n
g
φ
(
I
n
t
e
r
n
a
l
c
l
o
c
k
)
STP instruction
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
R
e
s
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t
Interrupt disable flag l
H
i
g
h
-
s
p
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d
m
o
d
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M
i
d
d
l
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-
s
p
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m
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P
r
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c
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1Timer 1
Main clock division
ratio selection bit
D
o
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X
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1
/
8
Main clock division ratio selection bit
Middle- , hi gh -, lo w -speed mode
R
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S
E
T
Rev.3.20 2003.05.28 page 47 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 53 State transition
S
t
o
p
m
o
d
e Wait mode
W
I
T
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←1
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MISRG
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r
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STP
instruction
WIT
instruction
I
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p
t
MISRG
1
←0
2
C
P
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M
3
←1
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3
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C
P
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M
7
6
←1
0
2
C
P
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M
7
6
←0
0
2
0
1
2
1
1
2
(
N
o
t
e
2
)
C
P
U
M
4
←0
2
MISRG
1
←1
2
MISRG
1
←0
2
Reset released
S
t
a
t
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1
O
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:
f
(X
I
N
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(
N
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1
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f
(X
I
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o
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R
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c
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l
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a
t
o
r
s
t
o
p
State 2
Operation clock source:
f(X
IN
) (Note 1)
f(X
IN
) oscillation enabled
Ring oscillator enabled
State 3
Operation clock source:
Ring oscillator (Note 3)
f(X
IN
) oscillation enabled
Ring oscillator enalbed
S
t
a
t
e
4
O
p
e
r
a
t
i
o
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c
l
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k
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:
R
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c
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r
(
N
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3
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f
(X
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)
o
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s
w
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h
o
f
c
l
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k
(
1
)
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a
t
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k
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=
f
(X
I
N
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t
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.
●
f
(
X
I
N
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/
2
(
h
i
g
h
-
s
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d
m
o
d
e
)
●
f
(
X
I
N
)
/
8
(
m
i
d
d
l
e
-
s
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d
m
o
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e
)
●
f
(
X
I
N
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(
d
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b
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d
m
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,
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a
m
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c
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c
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l
l
a
t
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n
)
(
2
)
E
x
e
c
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e
s
t
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o
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t
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3
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m
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f
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C
P
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c
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d
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v
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r
a
t
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(
4
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h
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s
t
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r
a
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s
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t
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s
t
a
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2
→
s
t
a
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3
→
s
t
a
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4
i
s
p
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r
f
o
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x
e
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t
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f
C
P
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c
l
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c
k
.
•
C
P
U
M
7
6
→
1
0
2
(
S
t
a
t
e
2
→
s
t
a
t
e
3
)
•
N
O
P
i
n
s
t
r
u
c
t
i
o
n
•
C
P
U
M
4
→
1
2
(
S
t
a
t
e
3
→
s
t
a
t
e
4
)
D
o
u
b
l
e
-
s
p
e
e
d
m
o
d
e
a
t
r
i
n
g
o
s
c
i
l
l
a
t
o
r
:
N
O
P
✕
3
H
i
g
h
-
s
p
e
e
d
m
o
d
e
a
t
r
i
n
g
o
s
c
i
l
l
a
t
o
r
:
N
O
P
✕
1
M
i
d
d
l
e
-
s
p
e
e
d
m
o
d
e
a
t
r
i
n
g
o
s
c
i
l
l
a
t
o
r
:
N
O
P
✕
0
Reset state
CPUM
76
←10
2
CPUM
76
←00
2
01
2
11
2
(Note 2)
S
t
a
t
e
2
’
O
p
e
r
a
t
i
o
n
c
l
o
c
k
s
o
u
r
c
e
:
f
(X
I
N
)
(
N
o
t
e
1
)
f
(X
I
N
)
o
s
c
i
l
l
a
t
i
o
n
e
n
a
b
l
e
d
R
i
n
g
o
s
c
i
l
l
a
t
o
r
e
n
a
b
l
e
d
S
t
a
t
e
3
’
O
p
e
r
a
t
i
o
n
c
l
o
c
k
s
o
u
r
c
e
:
R
i
n
g
o
s
c
i
l
l
a
t
o
r
(
N
o
t
e
3
)
f
(
X
I
N
)
o
s
c
i
l
l
a
t
i
o
n
e
n
a
b
l
e
d
R
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n
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o
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c
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l
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a
t
o
r
e
n
a
l
b
e
d
Rev.3.20 2003.05.28 page 48 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
NOTES ON PROGRAMMING
Processor Status Register
The contents of the processor status register (PS) after reset are
undefined except for the interrupt disable flag I which is “1”. After
reset, initialize flags which affect program execution. In particular,
it is essential to initialize the T flag and the D flag because of their
effect on calculations.
Interrupts
The contents of the interrupt request bit do not change even if the
BBC or BBS instruction is executed immediately after they are
changed by program because this instruction is executed for the
previous contents. For executing the instruction for the changed
contents, execute one instruction before executing the BBC or
BBS instruction.
Decimal Calculations
• For calculations in decimal notation, set the decimal mode flag
D to “1”, then execute the ADC instruction or SBC instruction. In
this case, execute SEC instruction, CLC instruction or CLD in-
struction after executing one instruction before the ADC instruction
or SBC instruction.
• In the decimal mode, the values of the N (negative), V (overflow)
and Z (zero) flags are invalid.
Ports
• The values of the port direction registers cannot be read.
That is, it is impossible to use the LDA instruction, memory opera-
tion instruction when the T flag is “1”, addressing mode using
direction register values as qualifiers, and bit test instructions such
as BBC and BBS.
It is also impossible to use bit operation instructions such as CLB
and SEB and read/modify/write instructions of direction registers
for calculations such as ROR.
For setting direction registers, use the LDM instruction, STA in-
struction, etc.
A-D Conversion
Do not execute the STP instruction during A-D conversion.
Instruction Execution Timing
The instruction execution time can be obtained by multiplying the
frequency of the internal clock φ by the number of cycles men-
tioned in the machine-language instruction table.
The frequency of the internal clock φ is the same as that of the XIN
in double-speed mode, twice the XIN cycle in high-speed mode
and 8 times the XIN cycle in middle-speed mode.
CPU Mode Register
The oscillation mode selection bit and processor mode bits can be
rewritten only once after releasing reset. However, after rewriting it
is disable to write any value to the bit. (Emulator MCU is ex-
cluded.)
When a ceramic oscillation is selected, a double-speed mode of
the clock division ratio selection bits can be used. Do not use it
when an RC oscillation is selected.
State transition
Do not stop the clock selected as the operation clock because of
setting of CM3, 4.
NOTES ON HARDWARE
Handling of Power Source Pin
In order to avoid a latch-up occurrence, connect a capacitor suit-
able for high frequencies as bypass capacitor between power
source pin (Vcc pin) and GND pin (Vss pin). Besides, connect the
capacitor to as close as possible. For bypass capacitor which
should not be located too far from the pins to be connected, a ce-
ramic capacitor of 0.01 µF to 0.1 µF is recommended.
One Time PROM Version
The CNVss pin is connected to the internal memory circuit block
by a low-ohmic resistance, since it has the multiplexed function to
be a programmable power source pin (VPP pin) as well.
To improve the noise reduction, connect a track between CNVss
pin and Vss pin with 1 to 10 kΩ resistance.
The mask ROM version track of CNVss pin has no operational in-
terference even if it is connected via a resistor.
Rev.3.20 2003.05.28 page 49 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
NOTES ON PERIPHERAL FUNCTIONS
■ Interrupt
When setting the followings, the interrupt request bit may be set to
“1”.
•When setting external interrupt active edge
Related register: Interrupt edge selection register (address
003A16)
Timer X mode register (address 2B16)
Timer A mode register (address 1D16)
When not requiring the interrupt occurrence synchronized with
these setting, take the following sequence.
➀ Set the corresponding interrupt enable bit to “0” (disabled).
➁ Set the interrupt edge select bit (active edge switch bit) to “1”.
➂ Set the corresponding interrupt request bit to “0” after 1 or
more instructions have been executed.
➃ Set the corresponding interrupt enable bit to “1” (enabled).
■ Timers
• When n (0 to 255) is written to a timer latch, the frequency divi-
sion ratio is 1/(n+1).
• When a count source of timer X, timer Y or timer Z is switched,
stop a count of timer X.
■ Timer A
CNTR1 interrupt active edge selection
CNTR1 interrupt active edge depends on the CNTR1 active edge
switch bit.
When this bit is “0”, the CNTR1 interrupt request bit is set to “1” at
the falling edge of the CNTR1 pin input signal. When this bit is “1”,
the CNTR1 interrupt request bit is set to “1” at the rising edge of
the CNTR1 pin input signal.
However, in the pulse width HL continuously measurement mode,
CNTR1 interrupt request is generated at both rising and falling
edges of CNTR1 pin input signal regardless of the setting of
CNTR1 active edge switch bit.
■ Timer X
CNTR0 interrupt active edge selection
CNTR0 interrupt active edge depends on the CNTR0 active edge
switch bit.
When this bit is “0”, the CNTR0 interrupt request bit is set to “1” at
the falling edge of CNTR0 pin input signal. When this bit is “1”, the
CNTR0 interrupt request bit is set to “1” at the rising edge of
CNTR0 pin input signal.
■ Timer Y: Programmable Generation
Waveform Mode
• Count set value
In the programmable waveform generation mode, values of TYS,
EXPYP, and EXPYS are valid by writing to TYP because the set-
ting to them is executed all at once by writing to TYP. Even when
changing TYP is not required, write the same value again.
• Write timing to TYP
In the programmable waveform generation mode, when the set-
ting value is changed while the waveform is output, set by
software in order not to execute the writing to TYP and the timing
of timer underflow during the secondary interval simultanesously.
• Usage of waveform extension function
The waveform extension function by the timer Y waveform exten-
sion control bit can be used only when “0016” is set to Prescaler Y.
When the value other than “0016” is set to Prescaler Y, be sure to
set “0” to EXPYP and EXPYS.
• Timer Y write mode
When using this mode, be sure to set “1” to the timer Y write con-
trol bit to select “write to latch only”.
Timer Y can stop counting by setting “1” to the timer Y count stop
bit in any mode.
Also, when Timer Y underflows, the timer Y interrupt request bit is
set to “1”.
Timer Y reloads the value of latch when counting is stopped by the
timer Y count stop bit. (When timer is read out while timer is
stopped, the value of latch is read. The value of timer can be read
out only while timer is operating.)
■ Timer Z: Programmable Waveform
Generation Mode
• Count set value
In the programmable waveform generation mode, values of TZS,
EXPZP, and EXPZS are valid by writing to TZP because the set-
ting to them is executed all at once by writing to TZP. Even when
changing TZP is not required, write the same value again.
• Write timing to TZP
In the programmable waveform generation mode, when the set-
ting value is changed while the waveform is output, set by
software in order not to execute the writing to TZP and the timing
of timer underflow during the secondary interval simultanesously.
• Usage of waveform extension function
The waveform extension function by the timer Z waveform exten-
sion control bit can be used only when “0016” is set to Prescaler Z.
When the value other than “0016” is set to Prescaler Z, be sure to
set “0” to EXPZP and EXPZS. Also, when the timer Y underflow is
selected as the count source, the waveform extension function
cannot be used.
• Timer Z write mode
When using this mode, be sure to set “1” to the timer Z write con-
trol bit to select “write to latch only”.
Rev.3.20 2003.05.28 page 50 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
■ Timer Z: Programmable One-shot
Generation Mode
• Count set value
In the programmable one-shot generation mode, the value of
EXPZP becomes valid by writing to TZP. Even when changing
TZP is not required, write the same value again.
• Write timing to TZP
In the programmable one-shot generation mode, when the setting
value is changed while the waveform is output, set by software in
order not to execute the writing to TZP and the timing of timer un-
derflow simultanesously.
• Usage of waveform extension function
The waveform extension function by the timer Z waveform exten-
sion control bit can be used only when “0016” is set to Prescaler Z.
When the value other than “0016” is set to Prescaler Z, be sure to
set “0” to EXPZP. Also, when the timer Y underflow is selected as
the count source, the waveform extension function cannot be
used.
• Timer Z write mode
When using this mode, be sure to set “1” to the timer Z write con-
trol bit to select “write to latch only”.
■ Timer Z: Programmable Wait One-shot
Generation Mode
• Count set value
In the programmable wait one-shot generation mode, values of
TZS, EXPZP and EXPZS are valid by writing to TZP. Even when
changing TZP is not required, write the same value again.
• Write timing to TZP
In the programmable wait one-shot generation mode, when the
setting value is changed while the waveform is output, set by soft-
ware in order not to execute the writing to TZP and the timing of
timer underflow during the secondary interval simultanesously.
• Usage of waveform extension function
The waveform extension function by the timer Z waveform exten-
sion control bit can be used only when “0016” is set to Prescaler Z.
When the value other than “0016” is set to Prescaler Z, be sure to
set “0” to EXPZP and EXPZS. Also, when the timer Y underflow is
selected as the count source, the waveform extension function
cannot be used.
• Timer Z write mode
When using this mode, be sure to set “1” to the timer Z write con-
trol bit to select “write to latch only”.
Timer Z can stop counting by setting “1” to the timer Z count stop
bit in any mode.
Also, when Timer Z underflows, the timer Z interrupt request bit is
set to “1”.
Timer Z reloads the value of latch when counting is stopped by the
timer Z count stop bit. (When timer is read out while timer is
stopped, the value of latch is read. The value of timer can be read
out only while timer is operating.)
■ Serial I/O
• Serial I/O interrupt
When setting the transmit enable bit to “1”, the serial I/O transmit
interrupt request bit is automatically set to “1”. When not requiring
the interrupt occurrence synchronized with the transmission en-
abled, take the following sequence.
➀ Set the serial I/O transmit interrupt enable bit to “0” (disabled).
➁ Set the transmit enable bit to “1”.
➂ Set the serial I/O transmit interrupt request bit to “0” after 1 or
more instructions have been executed.
➄ Set the serial I/O transmit interrupt enable bit to “1” (enabled).
• I/O pin function when serial I/O1 is enabled.
The functions of P12 and P13 are switched with the setting values
of a serial I/O1 mode selection bit and a serial I/O1 synchronous
clock selection bit as follows.
(1) Serial I/O1 mode selection bit → “1” :
Clock synchronous type serial I/O is selected.
Setup of a serial I/O1 synchronous clock selection bit
“0” : P12 pin turns into an output pin of a synchronous clock.
“1” : P12 pin turns into an input pin of a synchronous clock.
Setup of a SRDY1 output enable bit (SRDY)
“0” : P13 pin can be used as a normal I/O pin.
“1” : P13 pin turns into a SRDY output pin.
(2) Serial I/O1 mode selection bit → “0” :
Clock asynchronous (UART) type serial I/O is selected.
Setup of a serial I/O1 synchronous clock selection bit
“0”: P12 pin can be used as a normal I/O pin.
“1”: P12 pin turns into an input pin of an external clock.
When clock asynchronous (UART) type serial I/O is selected, it is
P13 pin. It can be used as a normal I/O pin.
■ A-D Converter
The comparator uses internal capacitors whose charge will be lost
if the clock frequency is too low.
Make sure that f(XIN) is 500kHz or more during A-D conversion.
Rev.3.20 2003.05.28 page 51 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
DATA REQUIRED FOR MASK ORDERS
The following are necessary when ordering a mask ROM produc-
tion:
1.Mask ROM Order Confirmation Form *
2.Mark Specification Form *
3.Data to be written to ROM, in EPROM form (three identical cop-
ies) or one floppy disk.
DATA REQUIRED FOR ROM PROGRAMMING
ORDERS
The following are necessary when ordering a One Time PROM
production:
1.ROM Programming Order Confirmation Form *
2.Mark Specification Form *
3.Data to be written to ROM, in EPROM form (three identical cop-
ies) or one floppy disk.
* For the mask ROM confirmation and the mark specifications,
refer to the "Renesas Technology Corp." Homepage
(http://www.renesas.com/en/rom).
ROM PROGRAMMING METHOD
The built-in PROM of the blank One Time PROM version can be
read or programmed with a general-purpose PROM programmer
using a special programming adapter. Set the address of PROM
programmer in the user ROM area.
The PROM of the blank One Time PROM version is not tested or
screened in the assembly process and following processes. To en-
sure proper operation after programming, the procedure shown in
Figure 54 is recommended to verify programming.
Package
32P4B
32P6U-A
36P2R-A
Name of Programming Adapter
PCA7435SPG02
PCA7435GPG03
PCA7435FPG02
Table 7 Special programming adapter
Fig. 54 Programming and testing of One Time PROM version
Programming with
PROM programmer
Screening (Caution)
(150 °C for 40 hours)
Verification with PROM
programmer
Functional check in
target device
The screening temperature is far higher
than the storage temperature. Never
expose to 150 °C exceeding 100 hours.
Caution:
Rev.3.20 2003.05.28 page 52 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
ELECTRICAL CHARACTERISTICS
1.7540Group (General purpose)
Applied to: M37540M2-XXXFP/SP/GP, M37540M4-XXXFP/SP/GP, M37540E2FP/SP/GP, M37540E8FP/SP/GP
Absolute Maximum Ratings (General purpose)
Table 8 Absolute maximum ratings
–0.3 to 6.5 (Note 1)
–0.3 to VCC + 0.3
–0.3 to VCC + 0.3
–0.3 to 13
–0.3 to VCC + 0.3
300 (Note 3)
–20 to 85
–40 to 125
Power source voltage
Input voltage
P00–P07, P10–P14, P20–P27, P30–P37, VREF
Input voltage RESET, XIN
Input voltage CNVSS (Note 2)
Output voltage
P00–P07, P10–P14, P20–P27, P30–P37, XOUT
Power dissipation
Operating temperature
Storage temperature
V
V
V
V
V
mW
°C
°C
VCC
VI
VI
VI
VO
Pd
Topr
Tstg
Conditions
Symbol Ratings Unit
Parameter
All voltages are
based on VSS.
Output transistors
are cut off.
Ta = 25°C
Notes 1: This is the rating value for the Mask ROM version.
The rating value for the One Time PROM version is –0.3 to 7.0 V.
2: It is a rating only for the One Time PROM version. Connect to VSS for the mask ROM version.
3: 200 mW for the 32P6U package product.
Rev.3.20 2003.05.28 page 53 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Recommended Operating Conditions (General purpose)
Table 9 Recommended operating conditions (1) (VCC = 2.2 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
VCC
VCC
4.0
2.4
2.2
4.5
4.0
2.4
2.2
4.0
2.4
2.2
2.0
0.8VCC
2.0
0.8VCC
0
0
0
0
Min. Typ. Max.
Symbol Parameter Unit
Power source voltage (ceramic) f(XIN) = 8 MHz (High-, Middle-speed mode)
f(XIN) = 4 MHz (High-, Middle-speed mode)
f(XIN) = 2 MHz (High-, Middle-speed mode)
f(XIN) = 6 MHz (Double-speed mode)
f(XIN) = 4 MHz (Double-speed mode)
f(XIN) = 2 MHz (Double-speed mode)
f(XIN) = 1 MHz (Double-speed mode)
f(XIN) = 4 MHz (High-, Middle-speed mode)
f(XIN) = 2 MHz (High-, Middle-speed mode)
f(XIN) = 1 MHz (High-, Middle-speed mode)
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
0
Limits
VCC V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
Power source voltage
Analog reference voltage
“H” input voltage
P00–P07, P10–P14, P20–P27, P30–P37
“H” input voltage (TTL input level selected)
P10, P12, P13, P36, P37 (Note 1)
“H” input voltage
RESET, XIN
“L” input voltage
P00–P07, P10–P14, P20–P27, P30–P37
“L” input voltage (TTL input level selected)
P10, P12, P13, P36, P37 (Note 1)
“L” input voltage
RESET, CNVSS
“L” input voltage
XIN
“H” total peak output current (Note 2)
P00–P07, P10–P14, P20–P27, P30–P37
“L” total peak output current (Note 2)
P00–P07, P10–P14, P20–P27, P37
“L” total peak output current (Note 2)
P30–P36
“H” total average output current (Note 2)
P0
0
–P0
7
, P1
0
–P1
4
, P2
0
–P2
7
, P3
0
–P3
7
“L” total average output current (Note 2)
P00–P07, P10–P14, P20–P27, P37
“L” total average output current (Note 2)
P30–P36
Note 1: Vcc = 4.0 to 5.5V
2: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured
over 100 ms. The total peak current is the peak value of all the currents.
VCC
VCC
0.3VCC
0.8
0.2VCC
0.16VCC
–80
80
60
–40
40
30
VSS
VREF
VIH
VIH
VIH
VIL
VIL
VIL
VIL
∑IOH(peak)
∑IOL(peak)
∑IOL(peak)
∑IOH(avg)
∑IOL(avg)
∑IOL(avg)
Power source voltage (RC)
Rev.3.20 2003.05.28 page 54 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Recommended Operating Conditions (General purpose)(continued)
Table 10 Recommended operating conditions (2) (VCC = 2.2 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
“H” peak output current (Note 1) P00–P07, P10–P14, P20–P27, P30–P37
“L” peak output current (Note 1) P00–P07, P10–P14, P20–P27, P37
“L” peak output current (Note 1) P30–P36
“H” average output current (Note 2) P00–P07, P10–P14, P20–P27, P30–P37
“L” average output current (Note 2) P00–P07, P10–P14, P20–P27, P37
“L” average output current (Note 2) P30–P36
Internal clock oscillation frequency (Note 3) VCC = 4.5 to 5.5 V
at ceramic oscillation or external clock input Double-speed mode
Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V
at ceramic oscillation or external clock input Double-speed mode
Internal clock oscillation frequency (Note 3) VCC = 2.4 to 5.5 V
at ceramic oscillation or external clock input Double-speed mode
Internal clock oscillation frequency (Note 3) VCC = 2.2 to 5.5 V
at ceramic oscillation or external clock input Double-speed mode
Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V
at ceramic oscillation or external clock input High-, Middle-speed mode
Internal clock oscillation frequency (Note 3) VCC = 2.4 to 5.5 V
at ceramic oscillation or external clock input High-, Middle-speed mode
Internal clock oscillation frequency (Note 3) VCC = 2.2 to 5.5 V
at ceramic oscillation or external clock input High-, Middle-speed mode
Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V
at RC oscillation High-, Middle-speed mode
Internal clock oscillation frequency (Note 3) VCC = 2.4 to 5.5 V
at RC oscillation High-, Middle-speed mode
Internal clock oscillation frequency (Note 3) VCC = 2.2 to 5.5 V
at RC oscillation High-, Middle-speed mode
Symbol Parameter Limits Max.Typ.Min. –10
10
30
–5
5
15
6
4
2
1
8
4
2
4
2
1
Notes 1: The peak output current is the peak current flowing in each port.
2: The average output current IOL (avg), IOH (avg) in an average value measured over 100 ms.
3: When the oscillation frequency has a duty cycle of 50 %.
IOH(peak)
IOL(peak)
IOL(peak)
IOH(avg)
IOL(avg)
IOL(avg)
f(XIN)
mA
mA
mA
mA
mA
mA
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
Rev.3.20 2003.05.28 page 55 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Electrical Characteristics (General purpose)
Table 11 Electrical characteristics (1) (VCC = 2.2 to 5.5 V, V SS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Min. Typ. Max.
Symbol Parameter Limits Unit
IOH = –5 mA
VCC = 4.0 to 5.5 V
IOH = –1.0 mA
VCC = 2.2 to 5.5 V
IOL = 5 mA
VCC = 4.0 to 5.5 V
IOL = 1.5 mA
VCC = 4.0 to 5.5 V
IOL = 1.0 mA
VCC = 2.2 to 5.5 V
IOL = 15 mA
VCC = 4.0 to 5.5 V
IOL = 1.5 mA
VCC = 4.0 to 5.5 V
IOL = 10 mA
VCC = 2.2 to 5.5 V
VI = VCC
(Pin floating. Pull up
transistors “off”)
VI = VCC
VI = VCC
VI = VSS
(Pin floating. Pull up
transistors “off”)
VI = VSS
VI = VSS
VI = VSS
(Pull up transistors “on”)
When clock stopped
VCC = 5.0 V, Ta = 25 °C
VCC = 5.0 V, Ta = 25 °C
Test conditions
VCC–1.5
VCC–1.0
2.0
1000
62.5
“H” output voltage
P00–P07, P10–P14, P20–P27, P30–P37 (Note 1)
“L” output voltage
P00–P07, P10–P14, P20–P27, P37
“L” output voltage P30–P36
Hysteresis
CNTR0, CNTR1, INT0, INT1(Note 2)
P00–P07 (Note 3)
Hysteresis
RXD, SCLK1, SCLK2, SDATA2 (Note 2)
Hysteresis
RESET
“H” input current
P00–P07, P10–P14, P20–P27, P30–P37
“H” input current
RESET
“H” input current
XIN
“L” input current
P00–P07, P10–P14, P20–P27, P30–P37
“L” input current
RESET, CNVSS
“L” input current
XIN
“L” input current
P00–P07, P30–P37
RAM hold voltage
Ring oscillator oscillation frequency
Oscillation stop detection circuit detection frequency
1.5
0.3
1.0
2.0
0.3
1.0
5.0
5.0
–5.0
–5.0
–0.5
5.5
3000
187.5
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
mA
V
kHz
kHz
VOH
VOL
VOL
VT+–VT–
VT+–VT–
VT+–VT–
IIH
IIH
IIH
IIL
IIL
IIL
IIL
VRAM
ROSC
DOSC
0.4
0.5
0.5
4.0
–4.0
–0.2
2000
125
Notes 1: P11 is measured when the P11/TXD1 P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: RXD1, SCLK1, SCLK2, SDATA2, INT0, and INT1 have hysteresises only when bits 0 to 2 of the port P1P3 control register are set to “0” (CMOS level).
3: It is available only when operating key-on wake up.
Rev.3.20 2003.05.28 page 56 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Electrical Characteristics (General purpose)(continued)
Table 12 Electrical characteristics (2) (VCC = 2.2 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Min. Typ. Max.
Symbol Parameter Limits UnitTest conditions
Power source
current 8.0
1.5
10.0
5.0
1000
3.2
450
1.0
10
6.5
1.2
8.0
5.0
900
3.2
450
1.0
10
mA
mA
mA
mA
µA
mA
mA
µA
mA
µA
µA
mA
mA
mA
mA
µA
mA
mA
µA
mA
µA
µA
ICC 5.0
0.5
6.0
2.0
350
1.6
0.2
150
0.5
0.1
3.5
0.4
4.5
2.0
300
1.6
0.2
150
0.5
0.1
High-speed mode, f(XIN) = 8 MHz
Output transistors “off”
High-speed mode, f(XIN) = 2 MHz, VCC = 2.2 V
Output transistors “off”
Double-speed mode, f(XIN) = 6 MHz
Output transistors “off”
Middle-speed mode, f(XIN) = 8 MHz
Output transistors “off”
Ring oscillator operation mode, VCC = 5 V
Output transistors “off”
f(XIN) = 8 MHz (in WIT state),
functions except timer 1 disabled,
Output transistors “off”
f(XIN) = 2 MHz, VCC = 2.2 V (in WIT state),
functions except timer 1 disabled,
Output transistors “off”
Ring oscillator operation mode, VCC = 5V
Output transistors “off”
Increment when A-D conversion is executed
f(XIN) = 8 MHz, VCC = 5 V
All oscillation stopped
(in STP state)
Output transistors “off”
High-speed mode, f(XIN) = 8 MHz
Output transistors “off”
High-speed mode, f(XIN) = 2 MHz, VCC = 2.2 V
Output transistors “off”
Double-speed mode, f(XIN) = 6 MHz
Output transistors “off”
Middle-speed mode, f(XIN) = 8 MHz
Output transistors “off”
Ring oscillator operation mode, VCC = 5 V
Output transistors “off”
f(XIN) = 8 MHz (in WIT state),
functions except timer 1 disabled,
Output transistors “off”
f(XIN) = 2 MHz, VCC = 2.2 V (in WIT state),
functions except timer 1 disabled,
Output transistors “off”
Ring oscillator operation mode, VCC = 5V
Output transistors “off”
Increment when A-D conversion is executed
f(XIN) = 8 MHz, VCC = 5 V
All oscillation stopped
(in STP state)
Output transistors “off”
One T ime PROM
version
Mask ROM version
Ta = 25 °C
Ta = 85 °C
Ta = 25 °C
Ta = 85 °C
Rev.3.20 2003.05.28 page 57 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
A-D Converter Characteristics (General purpose)
Table 13 A-D Converter characteristics
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Resolution
Linearity error
Differential nonlinear error
Zero transition voltage
Full scale transition voltage
Conversion time
Ladder resistor
Reference power source input current
A-D port input current
Resolution
Linearity error
Differential nonlinear error
Zero transition voltage
Full scale transition voltage
Conversion time
Ladder resistor
Reference power source
input current
A-D port input current
Min. Typ. Max.
Symbol Parameter Limits UnitTest conditions
VCC = 2.7 to 5.5 V
Ta = 25 °C
VCC = 2.7 to 5.5 V
Ta = 25 °C
VCC = VREF = 5.12 V
VCC = VREF = 3.072 V
VCC = VREF = 5.12 V
VCC = VREF = 3.072 V
VREF = 5.0 V
VREF = 3.0 V
VCC = 2.7 to 5.5 V
Ta = 25 °C
VCC = 2.7 to 5.5 V
Ta = 25 °C
VCC = VREF = 5.12 V
VCC = VREF = 3.072 V
VCC = VREF = 5.12 V
VCC = VREF = 3.072 V
VREF = 5.0 V
VREF = 3.0 V
Bits
LSB
LSB
mV
mV
mV
mV
tc(XIN)
kΩ
µA
µA
Bits
LSB
LSB
mV
mV
mV
mV
tc(XIN)
kΩ
µA
µA
10
±3
±0.9
20
15
5125
3075
122
200
120
5.0
10
±3
±1.5
35
21
5150
3090
122
200
120
5.0
—
—
—
VOT
VFST
tCONV
RLADDER
IVREF
II(AD)
—
—
—
VOT
VFST
tCONV
RLADDER
IVREF
II(AD)
5
3
5115
3069
55
150
70
15
9
5125
3075
55
150
70
0
0
5105
3060
50
50
0
0
5105
3060
50
50
One T ime
PROM version
Mask ROM version
Rev.3.20 2003.05.28 page 58 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Timing Requirements (General purpose)
Table 14 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Min. Typ. Max.
Symbol Parameter Limits Unit
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0 input cycle time
CNTR0, INT0, INT1, input “H” pulse width
CNTR0, INT0, INT1, input “L” pulse width
CNTR1 input cycle time
CNTR1 input “H” pulse width
CNTR1 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input set up time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 input set up time
Serial I/O2 input hold time
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(CNTR0)
tWH(CNTR0)
tWL(CNTR0)
tC(CNTR1)
tWH(CNTR1)
tWL(CNTR1)
tC(SCLK1)
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD1–SCLK1)
th(SCLK1–RxD1)
tC(SCLK2)
tWH(SCLK2)
tWL(SCLK2)
tsu(SDATA2–SCLK2)
th(SCLK2–SDATA2)
2
125
50
50
200
80
80
2000
800
800
800
370
370
220
100
1000
400
400
200
200
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O1 is selected).
When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4.
Table 15 Timing requirements (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Min. Typ. Max.
Symbol Parameter Limits Unit
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0 input cycle time
CNTR0, INT0, INT1, input “H” pulse width
CNTR0, INT0, INT1, input “L” pulse width
CNTR1 input cycle time
CNTR1 input “H” pulse width
CNTR1 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input set up time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 input set up time
Serial I/O2 input hold time
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(CNTR0)
tWH(CNTR0)
tWL(CNTR0)
tC(CNTR1)
tWH(CNTR1)
tWL(CNTR1)
tC(SCLK1)
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD1–SCLK1)
th(SCLK1–RxD1)
tC(SCLK2)
tWH(SCLK2)
tWL(SCLK2)
tsu(SDATA2–SCLK2)
th(SCLK2–SDATA2)
2
250
100
100
500
230
230
4000
1600
1600
2000
950
950
400
200
2000
950
950
400
400
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O1 is selected).
When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4.
Rev.3.20 2003.05.28 page 59 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Table 16 Timing requirements (3) (VCC = 2.2 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Min. Typ. Max.
Symbol Parameter Limits Unit
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0 input cycle time
CNTR0, INT0, INT1, input “H” pulse width
CNTR0, INT0, INT1, input “L” pulse width
CNTR1 input cycle time
CNTR1 input “H” pulse width
CNTR1 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input set up time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 input set up time
Serial I/O2 input hold time
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(CNTR0)
tWH(CNTR0)
tWL(CNTR0)
tC(CNTR1)
tWH(CNTR1)
tWL(CNTR1)
tC(SCLK1)
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD1–SCLK1)
th(SCLK1–RxD1)
tC(SCLK2)
tWH(SCLK2)
tWL(SCLK2)
tsu(SDATA2–SCLK2)
th(SCLK2–SDATA2)
2
500
200
200
1000
460
460
8000
3200
3200
4000
1900
1900
800
400
4000
1900
1900
800
800
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O1 is selected).
When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4.
Rev.3.20 2003.05.28 page 60 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Switching Characteristics (General purpose)
Table 17 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
tC(SCLK1)/2–30
tC(SCLK1)/2–30
–30
tC(SCLK2)/2–30
tC(SCLK2)/2–30
0
Min. Typ. Max.
Symbol Parameter Limits Unit
tWH(SCLK1)
tWL(SCLK1)
td(SCLK1–TxD1)
tv(SCLK1–TxD1)
tr(SCLK1)
tf(SCLK1)
tWH(SCLK2)
tWL(SCLK2)
td(SCLK2–SDATA2)
tv(SCLK2–SDATA2)
tr(SCLK2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time
Serial I/O1 output valid time
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output rising time
Serial I/O2 clock output falling time
CMOS output rising time (Note 1)
CMOS output falling time (Note 1)
Note 1: Pin XOUT is excluded.
Table 18 Switching characteristics (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Min. Typ. Max.
Symbol Parameter Limits Unit
350
50
50
350
50
50
50
50
Note 1: Pin XOUT is excluded.
tWH(SCLK1)
tWL(SCLK1)
td(SCLK1–TxD1)
tv(SCLK1–TxD1)
tr(SCLK1)
tf(SCLK1)
tWH(SCLK2)
tWL(SCLK2)
td(SCLK2–SDATA2)
tv(SCLK2–SDATA2)
tr(SCLK2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time
Serial I/O1 output valid time
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output rising time
Serial I/O2 clock output falling time
CMOS output rising time (Note 1)
CMOS output falling time (Note 1)
tC(SCLK1)/2–50
tC(SCLK1)/2–50
–30
tC(SCLK2)/2–50
tC(SCLK2)/2–50
0
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
140
30
30
140
30
30
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev.3.20 2003.05.28 page 61 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Table 19 Switching characteristics (3) (VCC = 2.2 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Min. Typ. Max.
Symbol Parameter Limits Unit
450
70
70
450
70
70
70
70
Note 1: Pin XOUT is excluded.
Switching characteristics measurement circuit diagram (Gen-
eral purpose)
/ / /
Measured
output pin
CMOS output
100 pF
tWH(SCLK1)
tWL(SCLK1)
td(SCLK1–TxD1)
tv(SCLK1–TxD1)
tr(SCLK1)
tf(SCLK1)
tWH(SCLK2)
tWL(SCLK2)
td(SCLK2–SDATA2)
tv(SCLK2–SDATA2)
tr(SCLK2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time
Serial I/O1 output valid time
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output rising time
Serial I/O2 clock output falling time
CMOS output rising time (Note 1)
CMOS output falling time (Note 1)
tC(SCLK1)/2–70
tC(SCLK1)/2–70
–30
tC(SCLK2)/2–70
tC(SCLK2)/2–70
0
25
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev.3.20 2003.05.28 page 62 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 55 Timing chart (General purpose)
0.2V
CC
t
d
(S
CLK1
-TxD
1
)
t
f
0.2V
CC
0.8V
CC
0.8V
CC
t
r
t
su
(RxD
1
-S
CLK1
)t
h
(S
CLK1
-RxD
1
)
t
v
(S
CLK1
-TxD
1
)
t
C
(S
CLK1
)
t
WL
(S
CLK1
) t
WH
(S
CLK1
)
R
X
D
1
(at receive)
S
CLK1
0.2V
CC
t
WL
(X
IN
)
0.8V
CC
t
WH
(X
IN
)t
C
(X
IN
)
X
IN
0.2V
CC
0.8V
CC
t
W
(RESET)
RESET
0.2V
CC
t
WL
(CNTR
0
)
0.8V
CC
t
WH
(CNTR
0
)
t
C
(CNTR
0
)
T
X
D
1
(at transmit)
CNTR
0
0.2V
CC
t
WL
(CNTR
0
)
0.8V
CC
t
WH
(CNTR
0
)
INT
0
, INT
1
0.2V
CC
t
WL
(CNTR
1
)
0.8V
CC
t
WH
(CNTR
1
)
t
C
(CNTR
1
)
CNTR
1
0.2V
CC
t
d
(S
CLK2
-S
DATA2
)
t
f
0.2V
CC
0.8V
CC
0.8V
CC
t
r
t
su
(S
DATA2
-S
CLK2
)t
h
(S
CLK2
-S
DATA2
)
t
v
(S
CLK2
-S
DATA2
)
t
C
(S
CLK2
)
t
WL
(S
CLK2
) t
WH
(S
CLK2
)
S
DATA2
(at receive)
S
CLK2
S
DATA2
(at transmit)
Rev.3.20 2003.05.28 page 63 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
ELECTRICAL CHARACTERISTICS
2.7540Group (Extended operating temperature version)
Applied to: M37540M2T-XXXFP/GP, M37540M4T-XXXFP/GP, M37540E8T-XXXFP/GP
Absolute Maximum Ratings (Extended operating temperature version)
Table 20 Absolute maximum ratings
–0.3 to 6.5 (Note 1)
–0.3 to VCC + 0.3
–0.3 to VCC + 0.3
–0.3 to VCC + 0.3
300 (Note 2)
–40 to 85
–65 to 150
Power source voltage
Input voltage
P00–P07, P10–P14, P20–P27, P30–P37, VREF
Input voltage RESET, XIN, CNVSS
Output voltage
P00–P07, P10–P14, P20–P27, P30–P37, XOUT
Power dissipation
Operating temperature
Storage temperature
V
V
V
V
mW
°C
°C
VCC
VI
VI
VO
Pd
Topr
Tstg
ConditionsSymbol Ratings UnitParameter
All voltages are
based on VSS.
Output transistors
are cut off.
Ta = 25°C
Notes 1: This is the rating value for the Mask ROM version.
The rating value for the One Time PROM version is –0.3 to 7.0 V.
2: 200 mW for the 32P6U package product.
Rev.3.20 2003.05.28 page 64 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Recommended Operating Conditions (Extended operating temperature version)
Table 21 Recommended operating conditions (1) (VCC = 2.4 to 5.5 V, Ta = –40 to 85 °C, unless otherwise noted)
5.5
5.5
5.5
5.5
5.5
5.5
5.5
VCC
VCC
VCC
VCC
4.0
2.4
4.5
4.0
2.4
4.0
2.4
2.0
0.8VCC
2.0
0.8VCC
0
0
0
0
Min. Typ. Max.
Symbol Parameter Unit
Power source voltage (ceramic) f(XIN) = 8 MHz (High-, Middle-speed mode)
f(XIN) = 4 MHz (High-, Middle-speed mode)
f(XIN) = 6 MHz (Double-speed mode)
f(XIN) = 4 MHz (Double-speed mode)
f(XIN) = 2 MHz (Double-speed mode)
f(XIN) = 4 MHz (High-, Middle-speed mode)
f(XIN) = 2 MHz (High-, Middle-speed mode)
5.0
5.0
5.0
5.0
5.0
5.0
5.0
0
Limits
VCC V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
Power source voltage
Analog reference voltage
“H” input voltage
P00–P07, P10–P14, P20–P27, P30–P37
“H” input voltage (TTL input level selected)
P10, P12, P13, P36, P37 (Note 1)
“H” input voltage
RESET, XIN
“L” input voltage
P00–P07, P10–P14, P20–P27, P30–P37
“L” input voltage (TTL input level selected)
P10, P12, P13, P36, P37 (Note 1)
“L” input voltage
RESET, CNVSS
“L” input voltage
XIN
“H” total peak output current (Note 2)
P00–P07, P10–P14, P20–P27, P30–P37
“L” total peak output current (Note 2)
P00–P07, P10–P14, P20–P27, P37
“L” total peak output current (Note 2)
P30–P36
“H” total average output current (Note 2)
P0
0
–P0
7
, P1
0
–P1
4
, P2
0
–P2
7
, P3
0
–P3
7
“L” total average output current (Note 2)
P00–P07, P1 0–P14, P20–P27, P37
“L” total average output current (Note 2)
P30–P36
Note 1: Vcc = 4.0 to 5.5V
2: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured
over 100 ms. The total peak current is the peak value of all the currents.
0.3VCC
0.8
0.2VCC
0.16VCC
–80
80
60
–40
40
30
VSS
VREF
VIH
VIH
VIH
VIL
VIL
VIL
VIL
∑IOH(peak)
∑IOL(peak)
∑IOL(peak)
∑IOH(avg)
∑IOL(avg)
∑IOL(avg)
Power source voltage (RC)
Rev.3.20 2003.05.28 page 65 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Recommended Operating Conditions (Extended operating temperature version)(continued)
Table 22 Recommended operating conditions (2) (VCC = 2.4 to 5.5 V, Ta = –40 to 85 °C, unless otherwise noted)
“H” peak output current (Note 1) P00–P07, P10–P14, P20–P27, P30–P37
“L” peak output current (Note 1) P00–P07, P10–P14, P20–P27, P37
“L” peak output current (Note 1) P30–P36
“H” average output current (Note 2) P00–P07, P10–P14, P20–P27, P30–P37
“L” average output current (Note 2) P00–P07, P10–P14, P20–P27, P37
“L” average output current (Note 2) P30–P36
Internal clock oscillation frequency (Note 3) VCC = 4.5 to 5.5 V
at ceramic oscillation or external clock input Double-speed mode
Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V
at ceramic oscillation or external clock input Double-speed mode
Internal clock oscillation frequency (Note 3) VCC = 2.4 to 5.5 V
at ceramic oscillation or external clock input Double-speed mode
Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V
at ceramic oscillation or external clock input High-, Middle-speed mode
Internal clock oscillation frequency (Note 3) VCC = 2.4 to 5.5 V
at ceramic oscillation or external clock input High-, Middle-speed mode
Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V
at RC oscillation High-, Middle-speed mode
Internal clock oscillation frequency (Note 3) VCC = 2.4 to 5.5 V
at RC oscillation High-, Middle-speed mode
mA
mA
mA
mA
mA
mA
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Symbol Parameter Limits Unit
Max.Typ.Min. –10
10
30
–5
5
15
6
4
2
8
4
4
2
Notes 1: The peak output current is the peak current flowing in each port.
2: The average output current IOL (avg), IOH (avg) in an average value measured over 100 ms.
3: When the oscillation frequency has a duty cycle of 50 %.
IOH(peak)
IOL(peak)
IOL(peak)
IOH(avg)
IOL(avg)
IOL(avg)
f(XIN)
Rev.3.20 2003.05.28 page 66 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Electrical Characteristics (Extended operating temperature version)
Table 23 Electrical characteristics (1) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Min. Typ. Max.
Symbol Parameter Limits Unit
IOH = –5 mA
VCC = 4.0 to 5.5 V
IOH = –1.0 mA
VCC = 2.4 to 5.5 V
IOL = 5 mA
VCC = 4.0 to 5.5 V
IOL = 1.5 mA
VCC = 4.0 to 5.5 V
IOL = 1.0 mA
VCC = 2.4 to 5.5 V
IOL = 15 mA
VCC = 4.0 to 5.5 V
IOL = 1.5 mA
VCC = 4.0 to 5.5 V
IOL = 10 mA
VCC = 2.4 to 5.5 V
VI = VCC
(Pin floating. Pull up
transistors “off”)
VI = VCC
VI = VCC
VI = VSS
(Pin floating. Pull up
transistors “off”)
VI = VSS
VI = VSS
VI = VSS
(Pull up transistors “on”)
When clock stopped
VCC = 5.0 V, Ta = 25 °C
VCC = 5.0 V, Ta = 25 °C
Test conditions
VCC–1.5
VCC–1.0
2.0
1000
62.5
“H” output voltage
P00–P07, P10–P14, P20–P27, P30–P37 (Note 1)
“L” output voltage
P00–P07, P10–P14, P20–P27, P37
“L” output voltage P30–P36
Hysteresis
CNTR0, CNTR1, INT0, INT1(Note 2)
P00–P07 (Note 3)
Hysteresis
RXD, SCLK1, SCLK2, SDATA2 (Note 2)
Hysteresis
RESET
“H” input current
P00–P07, P10–P14, P20–P27, P30–P37
“H” input current
RESET
“H” input current
XIN
“L” input current
P00–P07, P10–P14, P20–P27, P30–P37
“L” input current
RESET, CNVSS
“L” input current
XIN
“L” input current
P00–P07, P30–P37
RAM hold voltage
Ring oscillator oscillation frequency
Oscillation stop detection circuit detection frequency
1.5
0.3
1.0
2.0
0.3
1.0
5.0
5.0
–5.0
–5.0
–0.5
5.5
3000
187.5
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
mA
V
kHz
kHz
VOH
VOL
VOL
VT+–VT–
VT+–VT–
VT+–VT–
IIH
IIH
IIH
IIL
IIL
IIL
IIL
VRAM
ROSC
DOSC
0.4
0.5
0.5
4.0
–4.0
–0.2
2000
125
Notes 1: P11 is measured when the P11/TXD1 P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: RXD1, SCLK1, SCLK2, SDATA2, INT0, and INT1 have hysteresises only when bits 0 to 2 of the port P1P3 control register are set to “0” (CMOS level).
3: It is available only when operating key-on wake up.
Rev.3.20 2003.05.28 page 67 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Electrical Characteristics (Extended operating temperature version)(continued)
Table 24 Electrical characteristics (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Min. Typ. Max.
Symbol Limits Unit
8.0
1.5
10.0
5.0
1000
3.2
450
1.0
10
6.5
1.2
8.0
5.0
900
3.2
450
1.0
10
mA
mA
mA
mA
µA
mA
mA
µA
mA
µA
µA
mA
mA
mA
mA
µA
mA
mA
µA
mA
µA
µA
ICC 5.0
0.5
6.0
2.0
350
1.6
0.2
150
0.5
0.1
3.5
0.4
4.5
2.0
300
1.6
0.2
150
0.5
0.1
High-speed mode, f(XIN) = 8 MHz
Output transistors “off”
High-speed mode, f(XIN) = 2 MHz, VCC = 2.4 V
Output transistors “off”
Double-speed mode, f(XIN) = 6 MHz,
Output transistors “off”
Middle-speed mode, f(XIN) = 8 MHz,
Output transistors “off”
Ring oscillator operation mode, VCC = 5 V
Output transistors “off”
f(XIN) = 8 MHz (in WIT state),
functions except timer 1 disabled,
Output transistors “off”
f(XIN) = 2 MHz, VCC = 2.4 V (in WIT state),
functions except timer 1 disabled,
Output transistors “off”
Ring oscillator operation mode, VCC = 5V (in WIT state),
functions except timer 1 disabled, Output transistors “off”
Increment when A-D conversion is executed
f(XIN) = 8 MHz, VCC = 5 V
All oscillation stopped
(in STP state)
Output transistors “off”
High-speed mode, f(XIN) = 8 MHz
Output transistors “off”
High-speed mode, f(XIN) = 2 MHz, VCC = 2.4 V
Output transistors “off”
Double-speed mode, f(XIN) = 6 MHz
Output transistors “off”
Middle-speed mode, f(XIN) = 8 MHz
Output transistors “off”
Ring oscillator operation mode, VCC = 5 V
Output transistors “off”
f(XIN) = 8 MHz (in WIT state),
functions except timer 1 disabled,
Output transistors “off”
f(XIN) = 2 MHz, VCC = 2.4 V (in WIT state),
functions except timer 1 disabled,
Output transistors “off”
Ring oscillator operation mode, VCC = 5V (in WIT state),
functions except timer 1 disabled, Output transistors “off”
Increment when A-D conversion is executed
f(XIN) = 8 MHz, VCC = 5 V
All oscillation stopped
(in STP state)
Output transistors “off”
Ta = 25 °C
Ta = 85 °C
Test conditions
One Time PROM version
Mask ROM version
Ta = 25 °C
Ta = 85 °C
Rev.3.20 2003.05.28 page 68 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
A-D Converter Characteristics (Extended operating temperature version)
Table 25 A-D Converter characteristics
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Resolution
Linearity error
Differential nonlinear error
Zero transition voltage
Full scale transition voltage
Conversion time
Ladder resistor
Reference power source input current
A-D port input current
Resolution
Linearity error
Differential nonlinear error
Zero transition voltage
Full scale transition voltage
Conversion time
Ladder resistor
Reference power source
input current
A-D port input current
Min. Typ. Max.
Symbol Parameter Limits UnitTest conditions
VCC = 2.7 to 5.5 V
Ta = 25 °C
VCC = 2.7 to 5.5 V
Ta = 25 °C
VCC = VREF = 5.12 V
VCC = VREF = 3.072 V
VCC = VREF = 5.12 V
VCC = VREF = 3.072 V
VREF = 5.0 V
VREF = 3.0 V
VCC = 2.7 to 5.5 V
Ta = 25 °C
VCC = 2.7 to 5.5 V
Ta = 25 °C
VCC = VREF = 5.12 V
VCC = VREF = 3.072 V
VCC = VREF = 5.12 V
VCC = VREF = 3.072 V
VREF = 5.0 V
VREF = 3.0 V
Bits
LSB
LSB
mV
mV
mV
mV
tc(XIN)
kΩ
µA
µA
Bits
LSB
LSB
mV
mV
mV
mV
tc(XIN)
kΩ
µA
µA
10
±3
±0.9
20
15
5125
3075
122
200
120
5.0
10
±3
±1.5
35
21
5150
3090
122
200
120
5.0
—
—
—
VOT
VFST
tCONV
RLADDER
IVREF
II(AD)
—
—
—
VOT
VFST
tCONV
RLADDER
IVREF
II(AD)
5
3
5115
3069
55
150
70
15
9
5125
3075
55
150
70
0
0
5105
3060
50
50
0
0
5105
3060
50
30
One T ime
PROM version
Mask ROM version
Rev.3.20 2003.05.28 page 69 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Timing Requirements (Extended operating temperature version)
Table 26 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Min. Typ. Max.
Symbol Parameter Limits Unit
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0 input cycle time
CNTR0, INT0, INT1, input “H” pulse width
CNTR0, INT0, INT1, input “L” pulse width
CNTR1 input cycle time
CNTR1 input “H” pulse width
CNTR1 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input set up time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 input set up time
Serial I/O2 input hold time
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(CNTR0)
tWH(CNTR0)
tWL(CNTR0)
tC(CNTR1)
tWH(CNTR1)
tWL(CNTR1)
tC(SCLK1)
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD1–SCLK1)
th(SCLK1–RxD1)
tC(SCLK2)
tWH(SCLK2)
tWL(SCLK2)
tsu(SDATA2–SCLK2)
th(SCLK2–SDATA2)
2
125
50
50
200
80
80
2000
800
800
800
370
370
220
100
1000
400
400
200
200
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O1 is selected).
When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4.
Table 27 Timing requirements (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Min. Typ. Max.
Symbol Parameter Limits Unit
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0 input cycle time
CNTR0, INT0, INT1, input “H” pulse width
CNTR0, INT0, INT1, input “L” pulse width
CNTR1 input cycle time
CNTR1 input “H” pulse width
CNTR1 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input set up time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 input set up time
Serial I/O2 input hold time
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(CNTR0)
tWH(CNTR0)
tWL(CNTR0)
tC(CNTR1)
tWH(CNTR1)
tWL(CNTR1)
tC(SCLK1)
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD1–SCLK1)
th(SCLK1–RxD1)
tC(SCLK2)
tWH(SCLK2)
tWL(SCLK2)
tsu(SDATA2–SCLK2)
th(SCLK2–SDATA2)
2
250
100
100
500
230
230
4000
1600
1600
2000
950
950
400
200
2000
950
950
400
400
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O1 is selected).
When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4.
Rev.3.20 2003.05.28 page 70 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Switching characteristics measurement circuit diagram (Gen-
eral purpose)
/ / /
Measured
output pin
CMOS output
100 pF
Switching Characteristics (Extended operating temperature version)
Table 28 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
tC(SCLK1)/2–30
tC(SCLK1)/2–30
–30
tC(SCLK2)/2–30
tC(SCLK2)/2–30
0
Min. Typ. Max.
Symbol Parameter Limits Unit
tWH(SCLK1)
tWL(SCLK1)
td(SCLK1–TxD1)
tv(SCLK1–TxD1)
tr(SCLK1)
tf(SCLK1)
tWH(SCLK2)
tWL(SCLK2)
td(SCLK2–SDATA2)
tv(SCLK2–SDATA2)
tr(SCLK2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time
Serial I/O1 output valid time
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output rising time
Serial I/O2 clock output falling time
CMOS output rising time (Note 1)
CMOS output falling time (Note 1)
Note 1: Pin XOUT is excluded.
Table 29 Switching characteristics (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted)
Min. Typ. Max.
Symbol Parameter Limits Unit
350
50
50
350
50
50
50
50
Note 1: Pin XOUT is excluded.
tWH(SCLK1)
tWL(SCLK1)
td(SCLK1–TxD1)
tv(SCLK1–TxD1)
tr(SCLK1)
tf(SCLK1)
tWH(SCLK2)
tWL(SCLK2)
td(SCLK2–SDATA2)
tv(SCLK2–SDATA2)
tr(SCLK2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time
Serial I/O1 output valid time
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output rising time
Serial I/O2 clock output falling time
CMOS output rising time (Note 1)
CMOS output falling time (Note 1)
tC(SCLK1)/2–50
tC(SCLK1)/2–50
–30
tC(SCLK2)/2–50
tC(SCLK2)/2–50
0
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
140
30
30
140
30
30
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev.3.20 2003.05.28 page 71 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 56 Timing chart (Extended operating temperature version)
0.2V
CC
t
d
(S
CLK1
-TxD
1
)
t
f
0.2V
CC
0.8V
CC
0.8V
CC
t
r
t
su
(RxD
1
-S
CLK1
)t
h
(S
CLK1
-RxD
1
)
t
v
(S
CLK1
-TxD
1
)
t
C
(S
CLK1
)
t
WL
(S
CLK1
) t
WH
(S
CLK1
)
R
X
D
1
(at receive)
S
CLK1
0.2V
CC
t
WL
(X
IN
)
0.8V
CC
t
WH
(X
IN
)t
C
(X
IN
)
X
IN
0.2V
CC
0.8V
CC
t
W
(RESET)
RESET
0.2V
CC
t
WL
(CNTR
0
)
0.8V
CC
t
WH
(CNTR
0
)
t
C
(CNTR
0
)
T
X
D
1
(at transmit)
CNTR
0
0.2V
CC
t
WL
(CNTR
0
)
0.8V
CC
t
WH
(CNTR
0
)
INT
0
, INT
1
0.2V
CC
t
WL
(CNTR
1
)
0.8V
CC
t
WH
(CNTR
1
)
t
C
(CNTR
1
)
CNTR
1
0.2V
CC
t
d
(S
CLK2
-S
DATA2
)
t
f
0.2V
CC
0.8V
CC
0.8V
CC
t
r
t
su
(S
DATA2
-S
CLK2
)t
h
(S
CLK2
-S
DATA2
)
t
v
(S
CLK2
-S
DATA2
)
t
C
(S
CLK2
)
t
WL
(S
CLK2
) t
WH
(S
CLK2
)
S
DATA2
(at receive)
S
CLK2
S
DATA2
(at transmit)
Rev.3.20 2003.05.28 page 72 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
ELECTRICAL CHARACTERISTICS
3.7540Group (Extended operating temperature 125 °C version)
Applied to: M37540M2V-XXXFP/GP, M37540M4V-XXXFP/GP, M37540E8V-XXXFP/GP
Absolute Maximum Ratings (Extended operating temperature 125 °C version)
Table 30 Absolute maximum ratings
–0.3 to 6.5 (Note 1)
–0.3 to VCC + 0.3
–0.3 to VCC + 0.3
–0.3 to VCC + 0.3
300 (Note 2)
–40 to 125 (Note 3)
–65 to 150
Power source voltage
Input voltage
P00–P07, P10–P14, P20–P27, P30–P37, VREF
Input voltage RESET, XIN, CNVSS
Output voltage
P00–P07, P10–P14, P20–P27, P30–P37, XOUT
Power dissipation
Operating temperature
Storage temperature
V
V
V
V
mW
°C
°C
VCC
VI
VI
VO
Pd
Topr
Tstg
ConditionsSymbol Ratings UnitParameter
All voltages are
based on VSS.
Output transistors
are cut off.
Ta = 25°C
Notes 1: This is the rating value for the Mask ROM version.
The rating value for the One Time PROM version is –0.3 to 7.0 V.
2: 200 mW for the 32P6U package product.
3: In this version, the operating temperature range and total time are limited as follows;
55 °C to 85 °C: within total 6000 hours,
85 °C to 125 °C: within total 1000 hours.
Rev.3.20 2003.05.28 page 73 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Recommended Operating Conditions (Extended operating temperature 125 °C version)
Table 31 Recommended operating conditions (1) (VCC = 2.4 to 5.5 V, Ta = –40 to 125 °C, unless otherwise noted)
5.5
5.5
5.5
5.5
5.5
5.5
VCC
VCC
VCC
VCC
4.0
2.4
4.0
2.4
4.0
2.4
2.0
0.8VCC
2.0
0.8VCC
0
0
0
0
Min. Typ. Max.
Symbol Parameter Unit
Power source voltage (ceramic) f(XIN) = 8 MHz (High-, Middle-speed mode)
f(XIN) = 4 MHz (High-, Middle-speed mode)
f(XIN) = 4 MHz (Double-speed mode)
f(XIN) = 2 MHz (Double-speed mode)
f(XIN) = 4 MHz (High-, Middle-speed mode)
f(XIN) = 2 MHz (High-, Middle-speed mode)
5.0
5.0
5.0
5.0
5.0
5.0
0
Limits
VCC V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
Power source voltage
Analog reference voltage
“H” input voltage
P00–P07, P10–P14, P20–P27, P30–P37
“H” input voltage (TTL input level selected)
P10, P12, P13, P36, P37 (Note 1)
“H” input voltage
RESET, XIN
“L” input voltage
P00–P07, P10–P14, P20–P27, P30–P37
“L” input voltage (TTL input level selected)
P10, P12, P13, P36, P37 (Note 1)
“L” input voltage
RESET, CNVSS
“L” input voltage
XIN
“H” total peak output current (Note 2)
P00–P07, P10–P14, P20–P27, P30–P37
“L” total peak output current (Note 2)
P00–P07, P10–P14, P20–P27, P37
“L” total peak output current (Note 2)
P30–P36
“H” total average output current (Note 2)
P0
0
–P0
7
, P1
0
–P1
4
, P2
0
–P2
7
, P3
0
–P3
7
“L” total average output current (Note 2)
P00–P07, P1 0–P14, P20–P27, P37
“L” total average output current (Note 2)
P30–P36
Note 1: Vcc = 4.0 to 5.5V
2: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured
over 100 ms. The total peak current is the peak value of all the currents.
0.3VCC
0.8
0.2VCC
0.16VCC
–80
80
60
–40
40
30
VSS
VREF
VIH
VIH
VIH
VIL
VIL
VIL
VIL
∑IOH(peak)
∑IOL(peak)
∑IOL(peak)
∑IOH(avg)
∑IOL(avg)
∑IOL(avg)
Power source voltage (RC)
Rev.3.20 2003.05.28 page 74 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Recommended Operating Conditions (Extended operating temperature 125 °C version)
(continued)
Table 32 Recommended operating conditions (2) (VCC = 2.4 to 5.5 V, Ta = –40 to 125 °C, unless otherwise noted)
“H” peak output current (Note 1) P00–P07, P10–P14, P20–P27, P30–P37
“L” peak output current (Note 1) P00–P07, P10–P14, P20–P27, P37
“L” peak output current (Note 1) P30–P36
“H” average output current (Note 2) P00–P07, P10–P14, P20–P27, P30–P37
“L” average output current (Note 2) P00–P07, P10–P14, P20–P27, P37
“L” average output current (Note 2) P30–P36
Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V
at ceramic oscillation or external clock input Double-speed mode
Internal clock oscillation frequency (Note 3) VCC = 2.4 to 5.5 V
at ceramic oscillation or external clock input Double-speed mode
Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V
at ceramic oscillation or external clock input High-, Middle-speed mode
Internal clock oscillation frequency (Note 3) VCC = 2.4 to 5.5 V
at ceramic oscillation or external clock input High-, Middle-speed mode
Internal clock oscillation frequency (Note 3) VCC = 4.0 to 5.5 V
at RC oscillation High-, Middle-speed mode
Internal clock oscillation frequency (Note 3) VCC = 2.4 to 5.5 V
at RC oscillation High-, Middle-speed mode
mA
mA
mA
mA
mA
mA
MHz
MHz
MHz
MHz
MHz
MHz
Symbol Parameter Limits Unit
Max.Typ.Min. –10
10
30
–5
5
15
4
2
8
4
4
2
Notes 1: The peak output current is the peak current flowing in each port.
2: The average output current IOL (avg), IOH (avg) in an average value measured over 100 ms.
3: When the oscillation frequency has a duty cycle of 50 %.
IOH(peak)
IOL(peak)
IOL(peak)
IOH(avg)
IOL(avg)
IOL(avg)
f(XIN)
Rev.3.20 2003.05.28 page 75 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Electrical Characteristics (Extended operating temperature 125 °C version)
Table 33 Electrical characteristics (1) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –40 to 125 °C, unless otherwise noted)
Min. Typ. Max.
Symbol Parameter Limits Unit
IOH = –5 mA
VCC = 4.0 to 5.5 V
IOH = –1.0 mA
VCC = 2.4 to 5.5 V
IOL = 5 mA
VCC = 4.0 to 5.5 V
IOL = 1.5 mA
VCC = 4.0 to 5.5 V
IOL = 1.0 mA
VCC = 2.4 to 5.5 V
IOL = 15 mA
VCC = 4.0 to 5.5 V
IOL = 1.5 mA
VCC = 4.0 to 5.5 V
IOL = 10 mA
VCC = 2.4 to 5.5 V
VI = VCC
(Pin floating. Pull up
transistors “off”)
VI = VCC
VI = VCC
VI = VSS
(Pin floating. Pull up
transistors “off”)
VI = VSS
VI = VSS
VI = VSS
(Pull up transistors “on”)
When clock stopped
VCC = 5.0 V, Ta = 25 °C
VCC = 5.0 V, Ta = 25 °C
Test conditions
VCC–1.5
VCC–1.0
2.0
1000
62.5
“H” output voltage
P00–P07, P10–P14, P20–P27, P30–P37 (Note 1)
“L” output voltage
P00–P07, P10–P14, P20–P27, P37
“L” output voltage P30–P36
Hysteresis
CNTR0, CNTR1, INT0, INT1(Note 2)
P00–P07 (Note 3)
Hysteresis
RXD, SCLK1, SCLK2, SDATA2 (Note 2)
Hysteresis
RESET
“H” input current
P00–P07, P10–P14, P20–P27, P30–P37
“H” input current
RESET
“H” input current
XIN
“L” input current
P00–P07, P10–P14, P20–P27, P30–P37
“L” input current
RESET, CNVSS
“L” input current
XIN
“L” input current
P00–P07, P30–P37
RAM hold voltage
Ring oscillator oscillation frequency
Oscillation stop detection circuit detection frequency
1.5
0.3
1.0
2.0
0.3
1.0
5.0
5.0
–5.0
–5.0
–0.5
5.5
3000
187.5
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
mA
V
kHz
kHz
VOH
VOL
VOL
VT+–VT–
VT+–VT–
VT+–VT–
IIH
IIH
IIH
IIL
IIL
IIL
IIL
VRAM
ROSC
DOSC
0.4
0.5
0.5
4.0
–4.0
–0.2
2000
125
Notes 1: P11 is measured when the P11/TXD1 P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”.
2: RXD1, SCLK1, SCLK2, SDATA2, INT0, and INT1 have hysteresises only when bits 0 to 2 of the port P1P3 control register are set to “0” (CMOS level).
3: It is available only when operating key-on wake up.
Rev.3.20 2003.05.28 page 76 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Electrical Characteristics (Extended operating temperature 125°C version)(continued)
Table 34 Electrical characteristics (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –40 to 125 °C, unless otherwise noted)
Min. Typ. Max.
Symbol Limits Unit
8.0
1.5
5.0
1000
3.2
450
1.0
50
6.5
1.2
5.0
900
3.2
450
1.0
50
mA
mA
mA
µA
mA
mA
µA
mA
µA
µA
mA
mA
mA
µA
mA
mA
µA
mA
µA
µA
ICC 5.0
0.5
2.0
350
1.6
0.2
150
0.5
0.1
3.5
0.4
2.0
300
1.6
0.2
150
0.5
0.1
High-speed mode, f(XIN) = 8 MHz
Output transistors “off”
High-speed mode, f(XIN) = 2 MHz, VCC = 2.4 V
Output transistors “off”
Middle-speed mode, f(XIN) = 8 MHz,
Output transistors “off”
Ring oscillator operation mode, VCC = 5 V
Output transistors “off”
f(XIN) = 8 MHz (in WIT state),
functions except timer 1 disabled,
Output transistors “off”
f(XIN) = 2 MHz, VCC = 2.4 V (in WIT state),
functions except timer 1 disabled,
Output transistors “off”
Ring oscillator operation mode, VCC = 5V (in WIT state),
functions except timer 1 disabled, Output transistors “off”
Increment when A-D conversion is executed
f(XIN) = 8 MHz, VCC = 5 V
All oscillation stopped
(in STP state)
Output transistors “off”
High-speed mode, f(XIN) = 8 MHz
Output transistors “off”
High-speed mode, f(XIN) = 2 MHz, VCC = 2.4 V
Output transistors “off”
Middle-speed mode, f(XIN) = 8 MHz,
Output transistors “off”
Ring oscillator operation mode, VCC = 5 V
Output transistors “off”
f(XIN) = 8 MHz (in WIT state),
functions except timer 1 disabled,
Output transistors “off”
f(XIN) = 2 MHz, VCC = 2.4 V (in WIT state),
functions except timer 1 disabled,
Output transistors “off”
Ring oscillator operation mode, VCC = 5V (in WIT state),
functions except timer 1 disabled, Output transistors “off”
Increment when A-D conversion is executed
f(XIN) = 8 MHz, VCC = 5 V
All oscillation stopped
(in STP state)
Output transistors “off”
Ta = 25 °C
Ta = 125 °C
Test conditions
One Time PROM version
Mask ROM version
Ta = 25 °C
Ta = 125 °C
Rev.3.20 2003.05.28 page 77 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
A-D Converter Characteristics (Extended operating temperature 125 °C version)
Table 35 A-D Converter characteristics
(VCC = 2.7 to 5.5 V, VSS = 0 V, Ta = –40 to 125 °C, unless otherwise noted)
Resolution
Linearity error
Differential nonlinear error
Zero transition voltage
Full scale transition voltage
Conversion time
Ladder resistor
Reference power source input current
A-D port input current
Resolution
Linearity error
Differential nonlinear error
Zero transition voltage
Full scale transition voltage
Conversion time
Ladder resistor
Reference power source
input current
A-D port input current
Min. Typ. Max.
Symbol Parameter Limits UnitTest conditions
VCC = 2.7 to 5.5 V
Ta = 25 °C
VCC = 2.7 to 5.5 V
Ta = 25 °C
VCC = VREF = 5.12 V
VCC = VREF = 3.072 V
VCC = VREF = 5.12 V
VCC = VREF = 3.072 V
VREF = 5.0 V
VREF = 3.0 V
VCC = 2.7 to 5.5 V
Ta = 25 °C
VCC = 2.7 to 5.5 V
Ta = 25 °C
VCC = VREF = 5.12 V
VCC = VREF = 3.072 V
VCC = VREF = 5.12 V
VCC = VREF = 3.072 V
VREF = 5.0 V
VREF = 3.0 V
Bits
LSB
LSB
mV
mV
mV
mV
tc(XIN)
kΩ
µA
µA
Bits
LSB
LSB
mV
mV
mV
mV
tc(XIN)
kΩ
µA
µA
10
±3
±0.9
20
15
5125
3075
122
200
120
7.0
10
±3
±1.5
35
21
5150
3090
122
200
120
7.0
—
—
—
VOT
VFST
tCONV
RLADDER
IVREF
II(AD)
—
—
—
VOT
VFST
tCONV
RLADDER
IVREF
II(AD)
5
3
5115
3069
55
150
70
15
9
5125
3075
55
150
70
0
0
5105
3060
50
30
0
0
5105
3060
50
30
One T ime
PROM version
Mask ROM version
Rev.3.20 2003.05.28 page 78 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Timing Requirements (Extended operating temperature 125 °C version)
Table 36 Timing requirements (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 125 °C, unless otherwise noted)
Min. Typ. Max.
Symbol Parameter Limits Unit
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0 input cycle time
CNTR0, INT0, INT1, input “H” pulse width
CNTR0, INT0, INT1, input “L” pulse width
CNTR1 input cycle time
CNTR1 input “H” pulse width
CNTR1 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input set up time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 input set up time
Serial I/O2 input hold time
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(CNTR0)
tWH(CNTR0)
tWL(CNTR0)
tC(CNTR1)
tWH(CNTR1)
tWL(CNTR1)
tC(SCLK1)
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD1–SCLK1)
th(SCLK1–RxD1)
tC(SCLK2)
tWH(SCLK2)
tWL(SCLK2)
tsu(SDATA2–SCLK2)
th(SCLK2–SDATA2)
2
125
50
50
200
80
80
2000
800
800
800
370
370
220
100
1000
400
400
200
200
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O1 is selected).
When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4.
Table 37 Timing requirements (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –40 to 125 °C, unless otherwise noted)
Min. Typ. Max.
Symbol Parameter Limits Unit
Reset input “L” pulse width
External clock input cycle time
External clock input “H” pulse width
External clock input “L” pulse width
CNTR0 input cycle time
CNTR0, INT0, INT1, input “H” pulse width
CNTR0, INT0, INT1, input “L” pulse width
CNTR1 input cycle time
CNTR1 input “H” pulse width
CNTR1 input “L” pulse width
Serial I/O1 clock input cycle time (Note)
Serial I/O1 clock input “H” pulse width (Note)
Serial I/O1 clock input “L” pulse width (Note)
Serial I/O1 input set up time
Serial I/O1 input hold time
Serial I/O2 clock input cycle time
Serial I/O2 clock input “H” pulse width
Serial I/O2 clock input “L” pulse width
Serial I/O2 input set up time
Serial I/O2 input hold time
tW(RESET)
tC(XIN)
tWH(XIN)
tWL(XIN)
tC(CNTR0)
tWH(CNTR0)
tWL(CNTR0)
tC(CNTR1)
tWH(CNTR1)
tWL(CNTR1)
tC(SCLK1)
tWH(SCLK1)
tWL(SCLK1)
tsu(RxD1–SCLK1)
th(SCLK1–RxD1)
tC(SCLK2)
tWH(SCLK2)
tWL(SCLK2)
tsu(SDATA2–SCLK2)
th(SCLK2–SDATA2)
2
250
100
100
500
230
230
4000
1600
1600
2000
950
950
400
200
2000
950
950
400
400
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: In this time, bit 6 of the serial I/O1 control register (address 001A16) is set to “1” (clock synchronous serial I/O1 is selected).
When bit 6 of the serial I/O1 control register is “0” (clock asynchronous serial I/O1 is selected), the rating values are divided by 4.
Rev.3.20 2003.05.28 page 79 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Switching characteristics measurement circuit diagram (Gen-
eral purpose)
/ / /
Measured
output pin
CMOS output
100 pF
Switching Characteristics (Extended operating temperature 125 °C version)
Table 38 Switching characteristics (1) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 125 °C, unless otherwise noted)
tC(SCLK1)/2–30
tC(SCLK1)/2–30
–30
tC(SCLK2)/2–30
tC(SCLK2)/2–30
0
Min. Typ. Max.
Symbol Parameter Limits Unit
tWH(SCLK1)
tWL(SCLK1)
td(SCLK1–TxD1)
tv(SCLK1–TxD1)
tr(SCLK1)
tf(SCLK1)
tWH(SCLK2)
tWL(SCLK2)
td(SCLK2–SDATA2)
tv(SCLK2–SDATA2)
tr(SCLK2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time
Serial I/O1 output valid time
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output rising time
Serial I/O2 clock output falling time
CMOS output rising time (Note 1)
CMOS output falling time (Note 1)
Note 1: Pin XOUT is excluded.
Table 39 Switching characteristics (2) (VCC = 2.4 to 5.5 V, VSS = 0 V, Ta = –40 to 125 °C, unless otherwise noted)
Min. Typ. Max.
Symbol Parameter Limits Unit
350
50
50
350
50
50
50
50
Note 1: Pin XOUT is excluded.
tWH(SCLK1)
tWL(SCLK1)
td(SCLK1–TxD1)
tv(SCLK1–TxD1)
tr(SCLK1)
tf(SCLK1)
tWH(SCLK2)
tWL(SCLK2)
td(SCLK2–SDATA2)
tv(SCLK2–SDATA2)
tr(SCLK2)
tf(SCLK2)
tr(CMOS)
tf(CMOS)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time
Serial I/O1 output valid time
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time
Serial I/O2 output valid time
Serial I/O2 clock output rising time
Serial I/O2 clock output falling time
CMOS output rising time (Note 1)
CMOS output falling time (Note 1)
tC(SCLK1)/2–50
tC(SCLK1)/2–50
–30
tC(SCLK2)/2–50
tC(SCLK2)/2–50
0
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
140
30
30
140
30
30
30
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev.3.20 2003.05.28 page 80 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Fig. 57 Timing chart (Extended operating temperature 125 °C version)
0.2V
CC
t
d
(S
CLK1
-TxD
1
)
t
f
0.2V
CC
0.8V
CC
0.8V
CC
t
r
t
su
(RxD
1
-S
CLK1
)t
h
(S
CLK1
-RxD
1
)
t
v
(S
CLK1
-TxD
1
)
t
C
(S
CLK1
)
t
WL
(S
CLK1
) t
WH
(S
CLK1
)
R
X
D
1
(at receive)
S
CLK1
0.2V
CC
t
WL
(X
IN
)
0.8V
CC
t
WH
(X
IN
)t
C
(X
IN
)
X
IN
0.2V
CC
0.8V
CC
t
W
(RESET)
RESET
0.2V
CC
t
WL
(CNTR
0
)
0.8V
CC
t
WH
(CNTR
0
)
t
C
(CNTR
0
)
T
X
D
1
(at transmit)
CNTR
0
0.2V
CC
t
WL
(CNTR
0
)
0.8V
CC
t
WH
(CNTR
0
)
INT
0
, INT
1
0.2V
CC
t
WL
(CNTR
1
)
0.8V
CC
t
WH
(CNTR
1
)
t
C
(CNTR
1
)
CNTR
1
0.2V
CC
t
d
(S
CLK2
-S
DATA2
)
t
f
0.2V
CC
0.8V
CC
0.8V
CC
t
r
t
su
(S
DATA2
-S
CLK2
)t
h
(S
CLK2
-S
DATA2
)
t
v
(S
CLK2
-S
DATA2
)
t
C
(S
CLK2
)
t
WL
(S
CLK2
) t
WH
(S
CLK2
)
S
DATA2
(at receive)
S
CLK2
S
DATA2
(at transmit)
Rev.3.20 2003.05.28 page 81 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
PACKAGE OUTLINE
LQFP32-P-0707-0.80 Weight(g)
–
JEDEC Code
EIAJ Package Code Lead Material
Cu Alloy
32P6U-A
Plastic 32pin 7✕7mm body LQFP
–
0.1
–
––
0.2
–
–
––
–
–––
–
Symbol Min Nom Max
A
A
2
b
c
D
E
H
E
L
L
1
y
b
2
Dimension in Millimeters
H
D
A
1
––
I
2
1.0 ––
M
D
––
M
E
10°0°0.1
1.0 0.7
0.2
0.50.3
0.8
6.9 7.0 7.1
6.9 7.0 7.1
8.8 9.0 9.2
8.8 9.0 9.2
0.1750.1250.105 0.450.370.32 1.4
01.7
e
Lp 0.45
–
–
0.6
0.5
7.4
7.4
0.25
–
0.75
–
x
A3
Recommended Mount Pad
Detail F
A
E
H
E
H
D
D
1
8
24
17
2532
169
M
D
b
2
M
E
e
F
e
y
b
x
M
A
1
A
2
L
L
1
Lp
A3
c
I
2
MMP
SSOP36-P-450-0.80 Weight(g)
–
JEDEC Code 0.53
EIAJ Package Code Lead Material
Alloy 42
36P2R-A
Plastic 36pin 450mil SSOP
Symbol Min Nom Max
A
A
2
b
c
D
E
L
L
1
y
Dimension in Millimeters
H
E
A
1
I
2
–
–
.350
.050
.130.814.28–
.6311.30–
–
–
.271
–
–
.02.40.150.015.48.80.9311.50.7651
–
.4311–
–
.42
–
.50.20.215.68–
.2312.70–
.150
–
b
2
–.50–
–
0°–10°
e
e
1
36 19
18
1
H
E
E
D
ey
F
A
A
2
A
1
L
1
L
c
eb
2
e
1
I
2
Recommended Mount Pad
Detail F
z
Z
1
Detail G
–
–
Z
1
0.7
––
0.85
z
b
G
MMP
Rev.3.20 2003.05.28 page 82 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
SDIP32-P-400-1.78 Weight(g)
–2.2
JEDEC Code
EIAJ Package Code Lead Material
Alloy 42/Cu Alloy
32P4B
Plastic 32pin 400mil SDIP
Symbol Min Nom Max
A
A2
b
b1
b2
c
E
D
L
Dimension in Millimeters
A10.51 ––
–3.8 –
0.35 0.45 0.55
0.9 1.0 1.3
0.63 0.73 1.03
0.22 0.27 0.34
27.8 28.0 28.2
8.75 8.9 9.05
–1.778 –
–10.16 –
3.0 ––
0°–15°
––5.08
e
e1
32 17
16
1
E
c
e1
A2
A1
b2
b
b1
e
LA
SEATING PLANE
D
MMP
Rev.3.20 2003.05.28 page 83 of 83
7540 Group
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
Keep safety first in your circuit designs!
1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with
them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of
nonflammable material or (iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer’s application; they
do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party.
2. Renesas Technology Corporation assumes no responsibility for any damage, or infringement of any third-party’s rights, originating in the use of any product data, diagrams, charts,
programs, algorithms, or circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these
materials, and are subject to change by Renesas Technology Corporation without notice due to product improvements or other reasons. It is therefore recommended that customers
contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor for the latest product information before purchasing a product listed
herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corporation by various means, including the Renesas Technology Corporation Semiconductor home page
(http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information
as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corporation assumes no responsibility for any damage,
liability or other loss resulting from the information contained herein.
5. Renesas Technology Corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially
at stake. Please contact Renesas Technology Corporation or an authorized Renesas Technology Corporation product distributor when considering the use of a product contained
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6. The prior written approval of Renesas Technology Corporation is necessary to reprint or reproduce in whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be
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8. Please contact Renesas Technology Corporation for further details on these materials or the products contained therein.
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
http://www.renesas.com
Copyright © 2003. Renesas Technology Corporation, All rights reserved. Printed in Japan.
Rev. Rev.
No. date
1.0 First Edition 991122
2.0 Page 1: 010108
FEATURES
• The minimum instruction execution time revised;
0.34 µs (at 6 MHz oscillation frequency, double-speed mode for the shortest instruction)
• Power source voltage added;
XIN oscillation frequency at ceramic oscillation , in high-speed mode
At 6 MHz.......................................4.5 to 5.5 V
• Power dissipation revised;
Mask ROM version........................22.5 mW (standard)
One Time PROM version..............30 mW (standard)
PIN CONFIGURATION
Fig. 1 revised; Package type → 32P6U-A, Product name “M37540M4T-XXXGP” added
Page 2: Fig. 2 revised; Product name “M37540M4T-XXXFP” added
Page 3: Fig. 4 M37540RSS pin configuration (42S1M) added
Page 4: Fig. 5 Functional block diagram revised; Package type → 32P6U
Page 7: PIN DESCRIPTION revised; Notes 1 to 3 added
Page 8: Package type revised;
→ 32P6U-A.....0.8 mm-pitch plastic molded LQFP
→ 36P2R-A.....0.8 mm-pitch plastic molded SSOP
Table 2 revised; Package type → 32P6U-A
Pages 9 to 11: Structure of CPU added
Page 12: Fig. 11 Initial value added, Fig. 12 Description revised
Page 16: Table 5 Non-port function of port P0 revised, Notes 2 and 3 added
Page 17: Fig. 17 Port P0 revised
Page 18: Fig. 18 Note added
Page 20: Fig. 20 Initial values added, Interrupt enable bit of ICON1; Note added
Page 21: Fig. 21 Port P00 key-on wakeup selection bit added
REVISION DESCRIPTION LIST 7540 Group DATA SHEET
(1/5)
Revision Description
Rev. Rev.
No. date
2.0 (continued) 010108
Pages 22 to 30: Description of timers revised all
Page 31: Fig. 25 to Fig. 27 Initial values added
Page 33: Fig. 29 Reference of Figure revised → Fig. 50, 51
Page 36: Description of SIO1STS revised; “All bits” → “Bits 0 to 6”
Description of UARTCON revised; “P12/SCLK1” pin eliminated
Page 37: Fig. 34 Initial value added
Page 38: Fig. 35 Initial value added
Page 39: Fig. 37 Note revised
Page 40: Fig. 38 Initial value added
Page 41: Fig. 42 Initial value added
Page 42: Description in the case of 6 MHz added
Page 43: Fig. 45 Contents of (7), (8) revised
Page 45: Fig. 49 Functions of b1 and b7 revised, Initial value added
Page 46: Fig. 50 A resistor of XOUT pin eliminated
Page 47: Description of oscillation stop detection circuit added, Fig. 52 revised
Page 48: Notes on Ports revised
Pages 50 to 68: Electrical characteristics revised all
Page 69: Package type revised; 32P6U-A
3.0 All pages: The following is eliminated; 020610
“PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change.”
Page 1: • Memory size ROM/RAM size revised,
• Operating temperature range 125 °C version added, and Note revised
Page 2: Fig. 1 and Fig. 2 Product name revised
Page 3: Fig. 3 Product name revised
Page 7: Table 1 XIN, XOUT Functional description added, Note 1 125 °C version added
Page 8: Memory size ROM/RAM size, Package description, and Fig. 8 revised
Page 9: Table 2 revised
Page 14: Fig. 13 ROM/RAM area added
REVISION DESCRIPTION LIST 7540 Group DATA SHEET
(2/5)
Revision Description
REVISION DESCRIPTION LIST 7540 Group DATA SHEET
Revision Description
Rev. Rev.
No. date
3.0 (continued) 020610
Page 19: Fig. 18 (9) Port P14 revised
Page 20: Note revised
Page 23:
● Timer 1 “Prescaler 1 counts the signal which is the oscillation frequency divided by 16.”
(1) Timer mode “Timer A counts the oscillation frequency divided by 16.”
Page 24: ● Timer X “Timer X can can be selected in one of 4 operating modes by setting the
timer X operating mode bits of the timer X mode register.”
(1) Timer mode
“Prescaler X counts the count source selected by the timer X count source selection bits.”
Page 26: ● Timer Y “Timer Y can can be selected in one of 4 operating modes by setting the
timer Y operating mode bits of the timer Y mode register.”
(1) Timer mode
“Prescaler Y counts the count source selected by the timer Y count source selection bits.”
Page 27: Note on reading timer added.
Page 28: ● Timer Z “Timer Z can can be selected in one of 4 operating modes by setting the
timer Z operating mode bits of the timer Z mode register.”
(1) Timer mode
“Prescaler Z counts the count source selected by the timer Z count source selection bits.”
Page 30: Note on reading timer added.
Page 36: Note on Serial I/O added.
Page 44: Clock generating circuit The following description added.
(1) Ring oscillator operation, (2) Ceramic resonator, (3) RC oscillation, and (4) External clock
Fig. 46 Resistor and Note added, Fig. 47 Note added, and Fig. 49 added.
Page 45: ● Oscillation stop detection circuit Note added.
Page 46: Fig. 51 and Fig. 52 revised.
Page 47: Fig. 53 Note 4 added.
Pages 48 to 50: Notes revised
Page 51: DATA REQUIRED FOR MASK ORDERS revised
DATA REQUIRED FOR ROM PROGRAMMING ORDERS added
(3/5)
(4/5)
REVISION DESCRIPTION LIST 7540 Group DATA SHEET
Revision Description
Rev. Rev.
No. date
3.0 (continued) 020610
Page 52: Product name added, Table 8 Note revised.
Page 57: Table 13 Ladder resistor value revised, Layout revised.
Page 63: Product name added, Table 20 Note revised.
Page 67: Table 24 Characteristics for One Time PROM version added.
Mask ROM version; “VCC = 5 V” eliminated from the following Test condition.
f(XIN) = 6 MHz
f(XIN) = 8MHz, middle-speed mode
Page 68: Table 25 Ladder resistor value revised, Layout revised.
Page 72 to 80: Extended operating temperature 125 °C version added.
3.1 Page 57: Table 13, Page 68: Table 25 and Page 77: Table 35 020701
Error of the ladder resistor in A-D converter characteristics corrected.
As usual, (Rev.2.0 or before), the value is not changed from Typical 55 kΩ.
REVISION HISTORY
Rev. Date Description
Page Summary
(5/5)
7540 Group Data Sheet
3.20 May. 28, 2003 [Pull-up control register] PULL; Note added.
Fig.15; Note 2 eliminated.
Fig.17; (2) Ports P01,P02 revised.
Fig.29; Port P03 direction register block, Port P01 direction register block and
Port P02 direction register block revised.
(3) RC oscillation revised.
16
18
33
44
