71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
SEPTEMBER 2011
© 2005-2011 Teridian Semiconductor Corporation Page: 1 of 104
A Maxim Integrated Products Brand
GENE RAL DES CRIPTION
The 71M6513 is a hi ghly i ntegrated system-on-chip SoC with an MPU core,
real-time clock (RTC), flash, and LCD driver. Our Single Converter
Technology® with a 21-bit delta-sigma ADC, six analog inputs, digital tem-
perat ur e comp ens ation, prec isio n volt age refer ence, and 32-b it computation
engine (CE) supports a wide range of poly -phase metering appl ications with
very few low-cost external components. A 32kHz crystal time base for the
entire system and internal battery-backup support for RAM and RTC f urther
reduce system cost.
Maxim um design flexibility is supported with multiple UARTs, I2C, a power-
fail comparator, a 5V LCD charge pump, up to 22 DIO pins, and an in-
system programmable flash. The device is offered in high (0.1%) and
standard (0.5%) accuracy versions for multifunction residential/commercial
meter applications requiring multiple voltage/current inputs and complex
LCD or DIO configurations.
A com plete array of ICE and dev elopment t ool s, programming libraries and
reference designs enable rapid devel opm ent and certification of m eters that
m eet most demanding worldwide el ectricity met ering standards.
FEATURES
Wh Accuracy < 0.1% Over 2,000:1
Current Range
Exceeds IEC 62053/ANSIC 12.20
Voltage Reference
< 10ppm /°C (71M6513H)
< 40ppm/°C (71M6513)
Six Sensor Inputs—VDD Referenced
Auxiliary Analog Input for Neutral
Current
Low Jitter Wh/V ARh Pulse Outputs
Pulse Count For Pul se Outputs
Four-Quadrant Metering
Phase Sequencing
Line Frequency Count for RTC
Digital Temperature Compensation
Sag Detection
Independent 32-Bit Compute Engine
40-70Hz Line Frequency Range with
Same Calibr ation
Phase Compensation (±7°)
Battery Backup for RAM and RTC
22mW at 3.3V, 7. 2µW Backup
Flash Memory Option wit h Security
8-Bit MPU (80515)—One Clock
Cycle per Instruction
LCD Driver (≤ 168 Pixels)
High-Speed S S I Seri al Output
RTC for Time-of-Use Functions
Hardware Watchdog Tim er
Up to 22 General-Purpose I/O Pins
64KB Fl ash, 7K B RAM
Two UARTs for IR and AMR
100-Pin LQFP Package
MPU
RTC
TIMERS
IA
VA
IB
VB
XIN
XOUT
VREF
RX
TX
V1
TX
RX
COM0..3
V2
V3
V3.3A V3.3D
VBAT
V2.5
VLCD
VBIAS
VDRV
IC
VC
SEG0..23
GNDA GNDD
SEG 24..27
DIO 0..11
SEG 32..41
DIO 12..21
ICE
LIVE
LIVE
LIVE
NEUTRAL
LOAD
88.88.8888
MISC
POWER
FAULT
Etc.
IR
AMR
EEPROM
BATTERY
COMPARATOR
SENSE
DRIVE
SERIAL PORTS
OSC/PLL
CONVERTER
LCD DRIVER
DIO, PULSE
COMPUTE
ENGINE
FLASH
RAM
VOLTAGE REF
32 kHz
REGULATOR
5V BOOST
CT /COIL
POWER SUPPLY
TERIDIAN
71M6513
3/5V LCD
TEMP SENSOR
19-5360; Rev 3; 9/11
S ing le C onv erter Techn o logy is a registered trademark of
Max im Inte grated Pr oducts , Inc .
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
AUGUST 2011
Page: 2 of 104 © 2005-2011 Teridian Semiconductor Corporation
A Maxim Integrated Products Brand
Table of Contents
FEATURES ............................................................................................................................ 1
HARDWARE DESCRI PTION ................................................................................................................ 9
Hardware Overview ................................................................................................................. 9
Analog Front End ( AFE) .......................................................................................................... 9
Multiplexer................................................................................................................. 9
ADC .......................................................................................................................... 10
FI R Filter ................................................................................................................... 10
Volta ge Refer ence ..................................................................................................... 10
Temp erature S ensor .................................................................................................. 11
V3 ............................................................................................................................. 11
Functional Description ............................................................................................... 11
Computation Engin e (C E) ........................................................................................................ 12
Met er Equations ........................................................................................................ 12
Pulse Generator ........................................................................................................ 13
Real-Tim e Monitor ..................................................................................................... 13
CE Functiona l Overvie w ............................................................................................ 13
80515 M PU Core .................................................................................................................... 16
80515 Overvie w ........................................................................................................ 16
Me mory Organiz ation ................................................................................................ 16
Special Function Registers (SFRs) ............................................................................. 18
Special Function Registers (Generi c 80515 SFRs) ..................................................... 19
Special Function Registers Speci fi c to t he 71M6513 ................................................... 22
Instruction Set ........................................................................................................... 23
UART ........................................................................................................................ 23
Timers and Co unter s ................................................................................................. 26
WD Timer (S oftware Watchdog T ime r) ....................................................................... 28
Interrupts ................................................................................................................... 31
Ex ternal Interrupts ..................................................................................................... 34
Interrupt Prior it y Level Structure ................................................................................. 35
Interru pt S our ces and Vectors .................................................................................... 37
On-Chip Resour ces ................................................................................................................. 39
DIO Ports .................................................................................................................. 39
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
SEPTEMBER 2011
© 2005-2011 Teridian Semiconductor Corporation Page: 3 of 104
A Maxim Integrated Products Brand
Physical Memory ....................................................................................................... 41
Oscillator ................................................................................................................... 42
Real-Time Clock (RTC).............................................................................................. 42
Com parators (V2, V3) ................................................................................................ 42
LCD Dri v ers .............................................................................................................. 43
LCD Voltage Boost Circui try....................................................................................... 43
UART ( UART0) and Optic al P ort ( UART1).................................................................. 44
Hardware Reset Mechanisms .................................................................................... 44
Reset Pin (RESETZ).................................................................................................. 44
Hardware Watchdog T imer ........................................................................................ 44
Crystal Fr equency Monitor ......................................................................................... 44
V1 Pin ....................................................................................................................... 44
Internal Cl ock s and Cl ock Dividers ............................................................................. 45
I2C Interfa c e ( E E PR OM) ........................................................................................... 45
Battery ...................................................................................................................... 47
Intern al Voltag es (VBIAS, VBAT, V2P5) ..................................................................... 47
Test Ports ................................................................................................................. 47
FUNCTI ONAL DESCRIPTION .............................................................................................................. 49
Theory of Operation ................................................................................................................ 49
System Timing Summary......................................................................................................... 50
Data Flow ............................................................................................................................... 52
CE/MPU Communicati o n ......................................................................................................... 52
Fault, Reset, Po wer -Up ........................................................................................................... 53
Battery Ope ration .................................................................................................................... 54
Power Save Modes ................................................................................................................. 54
Chopping Ci rcuitry ................................................................................................................... 55
Int ernal/External Pulse Gener ati on and Pulse Counting ............................................................ 57
Program Se curity .................................................................................................................... 58
FIRMWARE INTERFACE ..................................................................................................................... 59
I/O RAM MAP – In Numerical Order ......................................................................................... 59
SFR MAP (SFR s Specific to Teridi an 8051 5) – In Numerical Order ........................................... 60
I/O R AM (Config ur a tion RAM) – Alphabetical Order.................................................................. 61
CE Pr ogr am an d Enviro nment ................................................................................................. 67
CE Pr ogr am .............................................................................................................. 67
Formats..................................................................................................................... 67
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
AUGUST 2011
Page: 4 of 104 © 2005-2011 Teridian Semiconductor Corporation
A Maxim Integrated Products Brand
Constants .................................................................................................................. 67
Environment .............................................................................................................. 67
CE Calculations ......................................................................................................... 68
CE RAM Locati ons .................................................................................................... 68
CE Front End Data ( Raw Data) .................................................................................. 69
CE Status Word......................................................................................................... 69
CE Tr ans fer Variabl es ............................................................................................... 70
TYPICAL PERFORMANCE DATA......................................................................................................... 77
Wh Ac cur ac y at Room Temp era ture ........................................................................................ 77
VARh Accur ac y at Room T emp eratu re .................................................................................... 77
Harmonic Performance ............................................................................................................ 78
APPLICATION INFORMATION ............................................................................................................. 79
Connecti on of Sensors (CT, Res i stive Shunt, Rogowski Coil) ................................................... 79
Distinction between 71M6513 and 71M6513H Parts ................................................................. 79
Temper ature Com pensation and Mains Frequency Stabilization for t he RTC............................. 80
External Tem perature Compens ation ....................................................................................... 81
Temp erature Measuremen t ..................................................................................................... 81
Crystal Os cillato r ..................................................................................................................... 83
Connecti ng LCDs .................................................................................................................... 84
Connecti ng I2C EEPRO Ms ...................................................................................................... 85
Connecti ng 5V D evices ........................................................................................................... 85
Optical Inter face ...................................................................................................................... 87
Connecti ng V1 and Reset Pins ................................................................................................ 87
Connecti ng the V3 Pin ............................................................................................................. 88
Connecti ng a Battery ............................................................................................................... 88
Flash Programming ................................................................................................................. 89
MPU Firmware Library............................................................................................................. 89
SPECIFICATIONS ................................................................................................................................ 90
Electrical Specifications ........................................................................................................... 90
LOGI C LEVELS......................................................................................................... 91
VREF, VBIAS ............................................................................................................ 93
CRYSTAL OSCILLATOR ........................................................................................... 93
LCD BOO ST ............................................................................................................. 95
LCD DRI VERS .......................................................................................................... 95
RTC .......................................................................................................................... 95
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
SEPTEMBER 2011
© 2005-2011 Teridian Semiconductor Corporation Page: 5 of 104
A Maxim Integrated Products Brand
RESETZ.................................................................................................................... 95
COMPARATORS ...................................................................................................... 96
RAM AND FLASH MEMORY ..................................................................................... 96
FLASH MEMO RY TI MING ......................................................................................... 96
EEPROM INTERFACE .............................................................................................. 96
Recommended External Component s ...................................................................................... 97
Packaging Informa t ion ............................................................................................................. 98
Pinout (Top View) ...................................................................................................... 99
Pin Descriptions ........................................................................................................ 100
I/O E quivalent Circuit s: .............................................................................................. 102
ORDERING INFORMAT IO N ................................................................................................... 103
Figures
Figure 1: IC Functional Block Diagram .......................................................................................................................... 8
Figure 2: General Topology of a Chopped Amplifier ..................................................................................................... 10
Figure 3: AFE Block Diagram...................................................................................................................................... 11
Figure 4: Samples in Multiplexer Cycle ....................................................................................................................... 14
Figure 5: Accumulation Interval.................................................................................................................................. 14
Figure 6: Memory Map .............................................................................................................................................. 16
Figure 7: Interrupt Structure ...................................................................................................................................... 38
Figure 8: DIO Ports Block Diagram ............................................................................................................................. 39
Figure 9: Oscillator Circuit ......................................................................................................................................... 42
Figure 10: LCD Voltage Boost Circuitry ....................................................................................................................... 43
Figure 11: Voltage Range for V1 ................................................................................................................................ 45
Figure 12: Voltage. Current, Momentary and Accumulated Energy................................................................................ 49
Figure 13: Timing Relationship between ADC MUX, CE, and Serial Transfers ................................................................ 50
Figure 14: RTM Output Format .................................................................................................................................. 51
Figure 15: SSI Timing, (SSI_FPOL = SSI_RDYPOL = 0) ............................................................................................ 51
Figure 16: SSI Timing, 16-bit Field Example (External Device Delays SRDY) ................................................................. 51
Figure 17: MPU/CE Data Flow .................................................................................................................................... 52
Figure 18: MPU/CE Communication (Functional) ......................................................................................................... 53
Figure 19: MPU/CE Communication (Processing Sequence) ........................................................................................ 53
Figure 20: Timing Diagram for Voltages, Current and Operation Modes after Power-Up ................................................. 54
Figure 21: Chop Polarity w/ Automatic Chopping ........................................................................................................ 56
Figure 22: Sequence with Alternate Multiplexer Cycles ................................................................................................ 56
Figure 23: Sequence with Alternate Multiplexer Cycles and Controlled Chopping ........................................................... 57
Figure 24: Wh Accuracy, 0.3A - 200A/240V ................................................................................................................ 77
Figure 25: VARh Accuracy for 0.3A to 200A/240V Performance ................................................................................... 78
Figure 27: Meter Accuracy over Harmonics at 240V, 30A ............................................................................................ 78
Figure 29: Resistive Voltage Divider (left), Current Transformer (right) ......................................................................... 79
Figure 30: Resistive Shunt (left), Rogowski Coil (right) ............................................................................................... 79
Figure 31: Crystal Frequency over Temperature .......................................................................................................... 80
Figure 32: Crystal Compensation ............................................................................................................................... 81
Figure 33: Error Band for VREF over Temperature (Regular-Accuracy Parts)................................................................. 83
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
AUGUST 2011
Page: 6 of 104 © 2005-2011 Teridian Semiconductor Corporation
A Maxim Integrated Products Brand
Figure 34: Error Band for VREF over Temperature (High-Accuracy Parts) ..................................................................... 83
Figure 33: Connecting LCDs ...................................................................................................................................... 84
Figure 34: LCD Boost Circuit...................................................................................................................................... 85
Figure 35: EEPROM Connection ................................................................................................................................. 85
Figure 36: Interfacing RX to a 0-5V Signal .................................................................................................................. 86
Figure 37: Connection for Optical Components ........................................................................................................... 87
Figure 38: Voltage Divider for V1 ............................................................................................................................... 87
Figure 39: External Components for RESETZ .............................................................................................................. 88
Tables
Table 1: Inputs S elect ed in Reg ul ar and Alter nat e M ultiplexer C yc les.......................................................... 9
Table 2: CE DRAM Locations for ADC Results ......................................................................................... 12
Table 3: Standard Met er Equations ( i nputs shown gr ay are scanned but not used f or calculation) .............. 13
Table 4: Stretch Memory Cycle Width ...................................................................................................... 17
Table 5: Internal Data Memory Map ......................................................................................................... 18
Table 6: Special Function Registers Locati ons ......................................................................................... 18
Table 7: Special Function Registers Reset Values .................................................................................... 20
Table 8: PSW Regi s ter Fl ags ................................................................................................................... 20
Table 9: PSW bit functions ...................................................................................................................... 21
Table 10: Port Reg isters .......................................................................................................................... 22
Table 11: S pecial Functio n Regis ters ....................................................................................................... 23
Table 12: Baud Rat e Gener ation.............................................................................................................. 24
Table 13: UART Modes ........................................................................................................................... 24
Table 14: The S0CON Register ................................................................................................................. 24
Table 15: The S1CON register .................................................................................................................. 25
Table 16: The S0CON Bit Functi ons.......................................................................................................... 25
Table 17: The S1CON Bit Functi ons.......................................................................................................... 26
Table 18: The TMOD R egist er ................................................................................................................. 26
Table 19: TMOD Regi ster Bi t Desc r iption ................................................................................................. 27
Table 20: Ti mers/ Count ers Mode Descr ipt ion ........................................................................................... 27
Table 21: The TCON Register .................................................................................................................. 27
Table 22: The TCON Regi ster Bit Functions ............................................................................................. 28
Table 23: Timer Modes............................................................................................................................ 28
Table 24: The P CON Regi ster ................................................................................................................. 28
Tab le 2 5: T he IEN0 Regist er (s ee also Table 3 2) ...................................................................................... 29
Table 26: The IEN0 Bit Funct ions (see also Table 32) ............................................................................... 29
Table 27: The I EN1 Regi ster ( see a lso Ta bles 30/3 1) ............................................................................... 29
Table 28: The IEN1 Bit Funct i ons (see also Tables 30/31) ........................................................................ 29
Table 29: The I P0 Reg ist er (s ee also Table 4 5) ........................................................................................ 30
Table 30: The IP0 bit Functions (see also Table 45) ................................................................................. 30
Table 31: The WDTRE L Regist er ............................................................................................................. 30
Table 32: The W DTREL Bit Funct i ons ...................................................................................................... 30
Table 33: The IEN0 Register .................................................................................................................... 32
Table 34: The IEN0 Bit Functions ............................................................................................................. 32
Table 35: The IEN1 Regist er ................................................................................................................... 32
Table 36: The I EN1 Bit Funct ions ............................................................................................................ 32
Table 37: The IEN2 Regist er ................................................................................................................... 33
Table 38: The I EN2 Bit Funct ions ............................................................................................................ 33
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
SEPTEMBER 2011
© 2005-2011 Teridian Semiconductor Corporation Page: 7 of 104
A Maxim Integrated Products Brand
Table 39: The TCON Register .................................................................................................................. 33
Table 40: The TCON Bi t Functions ........................................................................................................... 33
Table 41: The IRCON Register ................................................................................................................. 33
Table 42: The IRCON Bit Functio ns .......................................................................................................... 34
Table 43: Ext ern al M P U Inter ru pts ........................................................................................................... 34
Table 44: Control Bi t s for External Interrupts ............................................................................................ 35
Table 45: Priority Lev el Groups ................................................................................................................ 35
Table 46: The I P0 Reg ist er : ..................................................................................................................... 36
Table 47: The I P1 Reg ist er : ..................................................................................................................... 36
Table 48: Priority Lev els .......................................................................................................................... 36
Table 49: Interr upt Polling Sequence ....................................................................................................... 36
Table 50: I nterr upt Vec tors ...................................................................................................................... 37
Table 51: D ata R egisters, Di rec tio n Registers and I nternal R esources for DIO Pin Gro ups ........................ 39
Table 52: DIO_DIR Control Bit ................................................................................................................. 40
Table 53: Sel ectable Controls using th e DIO_DIR Bits .............................................................................. 40
Table 54: MPU Data Memory Map ........................................................................................................... 41
Table 55: Liq uid C ryst al Disp l ay S egmen t Table (Ty pic al) ......................................................................... 43
Table 56: EECTRL Status Bits .................................................................................................................. 46
Tab le 5 7: TMUX[3:0] Selections .............................................................................................................. 47
Table 58: SSI Pin A ssignment ................................................................................................................. 48
Table 59: Power Saving Measur es........................................................................................................... 54
Table 60: CHOP_EN Bits.......................................................................................................................... 55
Table 61: Freq uency over T emp eratur e ................................................................................................... 80
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
AUGUST 2011
Page: 8 of 104 © 2005-2011 Teridian Semiconductor Corporation
A Maxim Integrated Products Brand
Figure 1: IC Functional Block Diagram
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
SEPTEMBER 2011
© 2005-2011 Teridian Semiconductor Corporation Page: 9 of 104
A Maxim Integrated Products Brand
HARDWARE DESCRIPTION
Hardw are Overview
The 71M6513 single-chip polyphase meter integrates all primary functional blocks required to implement a solid-state
electri ci ty m et er. Included on chip are an analog front end (AFE), an 8051-comp ati bl e m i cro pro ces so r (M PU) w hic h exe cu tes
one instruction per clock cycle (80515), an independent 32-bit digital computation engine (CE), a voltage reference, a
temperature sensor, LCD drivers, RAM, flash memory, a real time clock (RTC), and a variety of I/O pins. Various current
sensor technolog ies are supported includ ing Curre nt Tran sfor mers (CT), Resistive Shunt s, and Rogowski (di/dt) Coils.
In addition to advanced measurem ent functions, the real time cl ock function allows the 71M6513/ 6513H to record tim e of use
(TOU) m eteri ng information for multi-rate appl ications. Measurem ents can be displayed on either a 3V or a 5V LCD. Flexi ble
mapping of LCD display segments will facilitate i ntegration with any LCD form at. The desi gn trade-of f b et ween t h e nu mber o f
LCD segm ents and DIO pins can be flexi bly configured using memory-mapped I/O to accommodate vari ous requi r em ents.
The 71M6513 includes several I/O per ipheral functions that improve the functionality of the devic e and r educe the component
count for m ost m eter applications. The I/O peripherals include two UARTs, digital I/O, compar ator inputs, LC D disp l ay dr i ver s ,
I2C i nterface and an opt ical/IR i nterface.
One of the t wo i nternal UARTs ( UART1) i s adapted to support an Infr ar ed LED with internal dr ive output and sense input but it
can also functi on as a standard UART.
A block diagram of the chip is shown in Figure 1. A d eta i led descri ption of va r ious har dware blocks follows.
Analog Front End (AFE)
The AFE of the 71M6513 Power Meter IC is comprised of an input multiplexer, a delta-sigma A/D converter with a voltage
r eferen ce, fo ll owed by an FIR fi lter. A block diagram of t he AFE is show n in Figure 3.
Multiplexer
The input m ultiplexer support s eight input signals that ar e applied to the pins I A, VA, IB, VB, IC, VC, and V3 plus the output of
the inter nal temp era ture sensor. The multiplex er c an b e opera ted in two m odes:
• Du ring a normal multipl exer cycle, the signal s fr om the six pins IA, VA, IB, VB, IC, and VC a re s elect ed.
• During the alternate multiplexer cycle, the temperature signal (TEMP) and the additional monitor input, V3, are
selected, along with t he other signal sources shown in Table 1: I nputs Selected i n Regular and Alternate Multiplexer
Cycles.
Al t ern ate m ul ti plex er c ycl es ar e us uall y perf or m ed infreq uen tl y ( ever y s econd or s o). VA, VB, and VC a re n ot r epl aced i n the
alternate multiplexer cycles. In some equations, currents must be delayed in allpass networks and therefore cannot be
replaced in the alter nate selection. Mi ssing samples due to alternate m ultiplexer cycles are aut omatically interpolated by the
CE.
Regular multiplexer sequence
Mux State: A lternate mul t iplexer sequence
Mux State:
0 1 2 3 4 5 0 1 2 3 4 5
IA VA IB VB IC VC TEMP VA V3 VB IC VC
Table 1: Inputs Sel ected in Regular and Alternate M ultiplexer Cycles
In a typical application, the IA, IB, and IC inputs are connect ed to current transformer s that sense the current on each phase of
the line voltage. VA, VB, and VC are typically connect ed to voltage sensors through r esistor dividers .
The Multiplexer Control Circuit handles the setting of the multiplexer. The function of the Multiplexer Control Circuit is
governed by the I/O RAM registers MUX_ALT (0x2005[2]), EQU (0x2000[7:5]), and MUX_DIV (0x2002[7:6]). MUX_DIV controls
the num ber of samples per cyc le. It c an req ues t 2 , 3, 4, or 6 multiplex er st ates per cycle.
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
AUGUST 2011
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The MUX_ALT bit requests an alternate multiplexer cycle. The bit may be asserted on any MPU cycle and may be sub-
sequently de-asserted on any cycle including the next one. A rising edge on MUX_ALT will cause the Control Circuit to wait
until the next multiplex er c ycle and implement a singl e alternate c ycle.
Multiplexer Control Circuit also controls the FIR filter initiation and the chopping of the ADC reference voltage, VREF. The
M u ltip lexer Control Circuit is clocked by C K32, the 32768H z clock f ro m the P LL block, and launches each pass through the C E
program.
ADC
A single 2 1/2 2-bit d elt a-sigma A/D converter digitizes the power inputs to the AFE. The resolution of the ADC is programmable
using t he I/O RAM regist er FIR_LEN register (0x2005[4]). ADC resolution may be selected to be 21 bits (FIR_LEN=0), or 22
bits (FIR_LEN=1). Conv ers ion time is two cycles of CK32 w it h FIR_LEN = 0 and t hr ee cy cl es with FIR_LEN = 1.
Accuracy , timing and func tion al spec ificatio ns in this data sheet are based on FIR_LEN = 0 ( two CK32 cycles) .
Initiation of each ADC conversion is controlled by the Multiplexer Control Circuit as described previously.
FIR Fi lt e r
The finite impulse response (FIR) filter is an integral part of the ADC and it is optimized for use with the multiplexer. The
purpose of the FIR is to decimate the ADC output to the desired resolution. At the end of each ADC conversion, the output
data of the FIR filter (raw data) is stored into the CE DRAM location determined by t he multiplexer sel ect i on. The locati on of
the raw data in the CE DRAM is speci fi ed in the CE Pr ogram and Environment Section.
Voltage Reference
The 71M6513/6513H includes an on-chip precision bandgap voltage reference that incorporates auto-zero techniques. The
reference of t he 71M6513H is trimmed in pr oduction to minimize er r or s caused by component mismatch and drift. The result is
a voltage out put with a pr edictable temperature coeffici ent.
The voltage reference i s chopper stabilized, i.e. the polarity can be switched by the MPU using t he I/O RAM register CHOP_EN
(0x2002[5:4]). The two bits in the CHOP_EN register enable the MPU to operate the chopper circuit in regular or inverted
operation, or in “toggling” mode. When the chopper circuit is toggled in between multiplexer cycles, DC offsets on the
measured signals w i ll aut omaticall y be averaged out.
The general topology of a chopped amplifier is given in Figure 2.
Figure 2: General Topology of a Chopped Amplifier
It is assum ed that an off set voltage Voff appears at the positive amplifier input. With all switches, as controlled by CROSS in
the “A” position, the out put voltage i s:
Voutp – Vout n = G ( Vi np + Voff – Vinn) = G (Vinp – Vi n n) + G Voff
G
-
+V
inp
V
outp
V
outn
V
inn
CROSS
A
B
A
B
A
B
A
B
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
SEPTEMBER 2011
© 2005-2011 Teridian Semiconductor Corporation Page: 11 of 104
A Maxim Integrated Products Brand
W ith all swi t c hes set to t he “B” positi on by applying the i nverted CROSS signal, the output voltage is:
Voutn – Vout p = G ( Vi nn – Vinp + Voff) = G (Vinn – Vi n p) + G Voff, or
Voutp – Vout n = G ( Vi np – Vinn) - G Voff
Thus, w hen CROSS is toggl ed, e.g. aft er ea ch mul tiplexer cy cle, t he of fset w ill alt ern ately appear on th e out put as positiv e and
nega tiv e, which r esu lts in th e offset ef fec ti vely being el im i nat ed, reg ardl ess of it s po larity or m agnit ude.
The Functional Descr ipt ion Sec tion con tains a chapt er with a deta iled des criptio n on contr ol lin g t he CHOP_EN register.
Temperature Sensor
The 71M6513/6513H includes an on-chip temperature sensor implemented as a bandgap r eference. It is used to determine
the die temperature The MPU may request an alternate multiplexer cycle containing the temperature sensor output by
asserting MUX_ALT.
The prim ary use of t he tem perature data is to determine the magni tude of compensation required to offset the therm al drift in
the system ( see secti on ti tled “ Temper at ure Comp ens atio n”).
The z ero refer ence fo r the temperat ure s ensor is V BIAS.
V3
V3 is an additional analog monitor input that can be used for analog measurements, such as neutral current. It is sampled
when th e multiplexer performs an alternate multiplexer cycle. The zer o ref eren ce f or the V3 in put is VBIAS.
V3 is also routed into the comparator block where it is compared to VBIAS. Comparator interrupts should be disabled when
the V3 input is use d for analog meas urements.
Funct io nal Description
The AFE functions as a data acquisition system, controlled by the MPU. The main signals (IA, VA, IB, VB, IC, VC) are
sampled and t he ADC counts obtained are s t ored in CE RAM where they can be accessed by the CE and, if necessary, by the
MPU. Alternate multiplexer cycles are i nitiated less frequently by the MPU to gather access t o the sl ow signals, tem per ature
and V3.
Figure 3: AFE Block Diagram
IA
VA
IB
VB
MUX
VREF VBIAS
IC
VBIAS
(1.5V)
TEMP
CK32
VREF
VREF_ D IS
MUX
CTRL
MUX_DIV
CHOP_EN
EQU
VC
MUX
V3
MUX_ALT
V3P3A
FIR_LEN
FIR
FILTER
∆Σ ADC
CONVERTER
+
-
VREF
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Co m putation Engine (CE)
The CE, a dedicated 32-bit RISC processor, performs the precision computations necessary to accurately measure energy.
The CE calculations a nd pr ocess es include:
• Multiplication of each current sample with its associated voltage sample to obtain the energy per sample (when
multiplied wi th the constant sample time).
• Frequency-insensitive delay cancellation on all six channels (to compensat e for the delay between sam ples caused
by the multiplexing scheme).
• 90° ph ase s hifter (for VA R c alculat io ns).
• Pulse generati on.
• Monitoring of the input si gnal freque ncy (for fre quency and ph ase information) .
• Monitoring of the input si gnal amplitude (f or sag detection).
• Scaling of the processed samples based on chip temperature (temperature compensation) and calibration
coefficients.
The CE program RAM (CE PRAM) is loaded at boot time by the MPU and then executed by the CE. Each CE i nstruction word
is 2 bytes long. The CE program counter begins a pass through the CE code each tim e multiplexer state 0 begi ns. The code
pass ends when a HALT instr uction is execut ed. For proper operat i on, the code pass must be completed befor e the
m ult iplex er cycle ends (s ee System Tim in g Summar y in t he Functi onal D escri pt ion Sect io n).
The CE data RAM (CE DRAM) can be accessed by the FI R filt er block, the RTM circuit, the CE, and the MPU. Assigned t i me
s lots are reserv ed f or FIR, R TM, and M PU, r esp ect ively, suc h th at memor y ac cesses t o CE _RA M d o not colli de. Hol ding r e-
gisters are used to convert 8-bit wide M PU d ata to/from 32-bit wi de CE DRAM dat a, and wait states are insert ed as needed,
depending on the frequency of CKMPU.
Table 2 shows the CE DRAM addr esses allocated t o analog input s from the AFE.
Address Name Zero
Reference Description
0x00
IA
V3P3
Phase A cur ren t
0x01 VA V3P3 Phase A voltage
0x02
IB
V3P3
Phase B cur ren t
0x03 VB V3P3 Phase B voltage
0x04 IC V3P3 Phas e C cur rent
0x05 VC V3P3 Phase C voltage
0x06 TEMP VBIAS Temperature
0x07 V3 VBIAS V 3 monitor
Table 2: CE DRAM Locati on s for ADC Results
Meter Equ at io ns
The Compute Engine (CE) program for industrial meter configurations implements the equations in Table 3. The I/O RAM
register EQU specifies the equat i on to be used based on the number and arrangement of phases used f or metering. In c ase of
single and two-phase metering, the unconnected inputs should be tied to V3P3A, the analog supply voltage. The EQU
selection enabl es the 71M6513 to calculate polyphase power m easurem ent based on the type of service used. Table 3 also
s tates the sequence of t he multipl exer in t he AF E.
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EQU Watt & VAR Formula Inputs used from MUX se-
quence
Mux State:
Inputs us ed from alternate MUX
sequence
Mux State:
0 1 2 3 4 5 0 1 2 3 4 5
0 VA IA
(1 element, 2W 1ø)
IA VA IB VB IC VC TEMP VA V3 VC IC VC
1 VA(IA-IB)/2
(1 element, 3W 1ø)
IA VA IB VB IC VC TEMP VA IB V3 VC VC
2 VA IA + VB IB
(2 element, 3W 3 øDelt a) IA VA IB VB IC VC TEMP VA V3 VB VC VC
3 VA (IA - IB)/2 + VC IC
(2 element, 4W 3ø Delt a)
IA VA IB VB IC VC TEMP VA IB V3 IC VC
4 VA(IA-IB)/2 + VB(IC-IB)/2
( 2 element , 4W 3ø Wye) IA VA IB VB IC VC TEMP VA IB V3 IC VC
5 VA IA + VB IB + VC IC
( 3 element , 4W 3ø Wye)
IA VA IB VB IC VC TEMP VA V3 VB IC VC
Table 3: Standard Meter Equations (inputs shown gr ay are scanned but not used for calculati on)
Pulse Generator
The CE co nt ain s two pulse genera to rs whic h cr eat e low jitt er pu lses at a rate s et b y the C E DR A M regi sters APULSEW*WRATE
and APULSER*WRATE if EXT_PULSE (a CE input variable in CE DRAM) is 15. This mode puts the MPU in control of pulse
generation by placing v alue s into the APULSEW and APULSER r egist ers (“ex ternal puls e genera tio n”).
If EXT_PULSE is 0, APULSEW is replaced with WSUM_X and APULSER is replaced with VARSUM_X. In this mode, the CE
generates pulse based on its internal computation of WSUM_X and VARSUM_X, the signed sums of energy from all three
elemen ts ( “i nternal pul se gener atio n”).
The DIO_PV and DIO_PW bit s as described in the Digital I/O secti on can be programm ed to route WPULSE and VARPULSE
to the output pins DIO6 and DIO7 respect ively. DIO6 and DIO7 can be configured to generate int er rupts, whi ch can be useful
for pul se c ount ing by th e M PU (see O n-Chip R esour ces , DIO Ports secti on) .
Real-Time Monitor
The CE contains a Real Time Monitor (RTM), which can be programmed to monitor four selectable CE RAM lo catio ns at full
sample rate. The four monitored locations are serially output to the TMUXOUT pin via the digital output multiplexer at the
beginning of each CE code pass (see t he Test Ports Sect ion fo r det ai ls)
CE Functional Overview
The ADC proces ses o n e sampl e p er c ha n nel p er mul t i pl exer c yc l e. Figure 4 shows the timi ng of the si x sampl es taken duri ng
one multiplexer cycle.
The number of samples processed during one accumulation cycle is controlled by the I/O RAM registers PRE_SAMPS
(0x2001[7:6]) and SUM_CYCLES (0x2001[5:0]). The integr ati on time for each energy output i s
PRE_SAMPS * SUM_CYCLES / 2520.6, wher e 2520.6 i s th e sampl e rate [ Hz]
For ex ample, PRE_SAMPS = 42 and SUM_CYCLES = 5 0 will est ablish 2100 samples per ac cum ulation cyc le. PRE_SAMPS = 100
and SUM_CYCLES = 21 will result in the exact same accumulation cycle of 2100 samples or 833ms. After an accumulation
c ycle i s com pleted , the XF ER_ BUS Y int er ru pt signals to the M PU th at ac cum ulat ed data are avail able.
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Figure 4: Sampl es in Mu l tiplexer Cycl e
The end of each multiplexer cycle is signaled to the MPU by the CE_BUSY interrupt. At the end of each multiplexer cycle,
s tatus information, such as sag data and the digitized input signal, is available to the MPU.
Figure 5: Accumulation Interval
Figure 5 shows the accumulation interval r esulti ng from PRE_SAMPS = 42 and SUM_CYCLES = 50, consisting of 2100 samples
of 397µs each (onl y one phase is shown) followed by t he XFER_BUSY interrupt. The sam pling in this exam ple is applied to a
50Hz signal.
Th ere i s no corr elati on bet ween th e li ne signal fr equ ency a nd t he c hoi ce of PRE_SAMPS or SUM_CYCLES (even though when
SUM_CYCLES = 42 one set of SUM_CYCLES happens to sampl e a peri od of 16.6m s). Furthermor e, s am pl i ng d oes n ot h ave t o
start when t he line voltage crosses the zero line.
Delay Co mpensation
When measuring the energy of a phase (i.e., Wh and VARh) in a service, the voltage and current for that phase must be
s ampled at the same instant . Ot herwise, the phase difference, Ф, introduces errors.
VA
VB
IB
VC
IC
IA
1/ 2520.6Hz = 397µs
2/32768Hz =
61.04µs
13/32768Hz = 397µs
per mux cycle
A
C
B
VA
VB
IB
VC
IC
IA
1/ 2520.6Hz = 397µs
2/32768Hz =
61.04µs
13/32768Hz = 397µs
per mux cycle
A
C
B
XFER_BUSY
Interrupt to MPU
20ms
833ms
XFER_BUSY
Interrupt to MPU
20ms
833ms
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o
delay
o
delay ft
T
t360360 ⋅⋅=⋅=
φ
Where f is the fr equency of the input signal and tdelay is t he sampling del ay b etween v oltage and c urrent .
In t raditional m eter ICs, sampling is accomplished by using two A/D converters per phase (one for vol tage and the other one
for current) controlled to sample simultaneously. Our Single-Converter Technology, however, exploits the 32-bit signal
processing capability of its CE to implement “constant delay” all-pass filters. These all-pass filters correct for the conversion
time difference between the voltage and the corresponding current samples that are obtained with a single multiplexed A/D
converter.
The “constant delay” all-pass filters provide a broad-band delay β that is precisely matched to the difference in sam ple t ime
between the voltage and the current of a given phase. This digital filter does not affect the amplitude of the signal, but
pr ovid es a prec isel y co ntr oll ed phase res po nse. Th e del ay com p ens ati on im pl em ented in t he CE al igns t he v olta ge s ampl es
with their correspondi ng current samples by routing the voltage samples through the all-pass filter, thus del aying the voltage
samples by β, resu lting in the residual phase error β – Ф. The residual phase error is negligible, and is typically less than ±1.5
milli-de gre es at 100Hz, thus it does not contribute to errors in the energy measureme nts.
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80515 MPU Co re
80515 Overvi ew
The 71M6513/6513H includes an 80515 MPU (8-bit, 8051-compatible) that processes most instructions in one clock cycle.
Using a 5MHz clock results in a proce ssing th roughp ut of 5 MIPS. The 80515 architectu re eliminates redundant bus sta te s and
implements parallel execution of fetch and execution phases. Norm ally a machine cy cl e is aligned with a m emory fetch, there-
fore, most of the 1-byte instructions are performed in a single cycle. This leads to an 8x performance (in average)
improvem ent (in terms of MI PS) over t he I ntel 8 051 device run ning at the same cloc k f req uency.
Actual processor clocking speed can be adjusted to the total processing demand of the application (metering calculations,
AMR management, memory management, LCD driver management and I/O management) using the I/O RAM register
MPU_DIV[2:0].
Typical measurement and metering functions based on the results provided by the internal 32-bit compute engine (CE) are
available for the MPU as part of Teridian’s standard library. A standard ANSI “C” 80515-application programming interface
li brary i s ava i labl e to h elp red uce des ig n cy cle.
Memory Organ izat io n
The 80515 MPU core incorporates t he Har vard archit ecture wit h separate code and dat a spaces.
Memory organization in the 80515 is similar to that of the industry standard 8051. There are three memory areas: Program
memory (flash), external data memory (XRAM), physically consisting of XRAM, CE DRAM, CE PRAM and I/O RAM, and
internal dat a me mo ry (Interna l RAM ). Figure 6 shows the me mory map (se e also Table 54).
I nter n al a nd Ext e r n al Dat a Memor y: Both i nternal and exter nal data mem ory are physical ly located on the 71M6513 IC. Ex-
ternal data mem ory is only external to the 80515 MPU c or e.
0xFFFF
Flash memory
0xFFFF
---
0x4000
0x3FFF
CE PRAM
0x3000
0x2FFF
---
0x2100
0x20FF
I/O R AM
0x2000
0x1FFF
---
0x1400
0x13FF
CE DRAM
0x1000
0x0FFF
---
0x0800
0x07FF
XRAM
0xFF
SFRs, RAM,
reg. banks
0x0000
0x0000
0x00
Pro gra m me mory External data me mory Internal data memor y
Figure 6: Me mo ry Map
Prog ram Memory : The 80515 can address up to 64KB of program m emory space from 0x0000 to 0xFFFF. Program m emory
is read when the MPU fetches i nstructions or performs a MOVC oper ation.
After r eset, t he MP U star t s pr ogr am execut ion from l ocati on 0x 0000. T he l ower pa r t of th e pro gr am mem ory inc ludes res et and
interru pt vectors. The int errupt vect ors are s paced at 8-byte intervals, starting from 0x0003.
External Data Memory: While the 80515 can address up to 64KB of external data memory in the space from 0x0000 to
0xFFFF, only t he m em ory ranges shown in Figure 6 contain physi cal memory. The 80515 writes into external data memory
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when the MPU ex ec utes a MOVX @Ri ,A or MOVX @DPTR,A instruct ion. The MPU reads ext ernal data m em ory by execut ing
a M OVX A, @Ri or MO VX A,@DPTR instr ucti on (SFR USR2 provides the upper 8 byt es for the MOVX A,@Ri instruction).
Clock Stretching: MOVX instructions can access f ast or slow ext ernal RAM and ext ernal peripherals. The three l ow ordered
bits of t he CKCON register define the stretch m em ory cycles. Setting all the CKCON stretch bits to one allows access to very
s lo w external RA M or exter nal peripher als.
Table 4 shows how the signals of the External Memo ry Interface change when stretch values are set from 0 t o 7. The widths of
the signals are counted in MPU clock cycles. The post-reset state of the CKCON register, which is in bold in the table,
performs the MOVX i nstructions wi th a st r etch value equal to 1.
CKCON register St r etch Value Read si gnals width Write signal width
CKCON.2 CKCON.1 CKCON.0 memaddr memrd memaddr memwr
0 0 0 0 1 1 2 1
0
0
1
1
2
2
3
1
0 1 0 2 3 3 4 2
0 1 1 3 4 4 5 3
1 0 0 4 5 5 6 4
1 0 1 5 6 6 7 5
1 1 0 6 7 7 8 6
1 1 1 7 8 8 9 7
Table 4: S t re t ch M emo ry Cycl e W id t h
There ar e two types of i nstructions, differing in whet her they provide an eight-b it or s i xt een -bit indirect address to the external
data RAM.
In the first type (MOVX A,@Ri), the contents of R0 or R1, i n the cur rent register bank, pr ovide t he eight lower-ordered b its of
address. The eight high-or dered bits of address are specified with the USR2 SFR. This method allows the user paged access
(256 pages of 256 bytes each) to the full 64KB of external data RAM. In the second type of MOVX instruction (MOVX
A,@DPTR), the da t a point er g en er ates a sixt een -bit address. This form is faster and more efficient when accessi ng ver y large
data arrays (up to 64 Kbytes), since no addi tional instructions are needed to set up the ei ght high order ed bits of address.
It is possible to m ix t he tw o MOV X typ es. Thi s prov ides t he us er wit h fo ur s epa rat e dat a p ointer s, two wit h di rec t ac ces s an d
two with paged access to t he entire 64KB of ext ernal m emory range.
Dual Data Pointer: The Dual Data Pointer accelerates the block moves of data. The standard DPTR is a 16-bi t register t hat is
used to address external mem or y or peri pheral s. In the 80515 core, t he standard data pointer is call ed DPTR, the second dat a
point er is c alled DPTR1. The data point er select bit chooses the active pointer. The dat a pointer select bi t i s located at t he LSB
of the DPS register (DPS.0). DPTR is select ed when DPS. 0 = 0 and DPTR1 is select ed wh en DPS.0 = 1.
The user switches between pointers by toggling the LSB of the DPS register. All DPTR-related instructions use the currently
selected DPTR for any activity.
The second dat a pointer may not be supported by cer t ain compiler s.
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Internal Data Memory: The Internal data memory provides 256 bytes (0x00 to 0xFF) of data memory. The internal data
memory address is always 1 byte wide and can be accessed by either direct or indirect addressing. The Special Function
Registers occupy the upper 128 bytes. This SFR area is available only by direct addressing. Indirect addressing
accesses the upper 128 bytes of Internal RAM .
The lower 128 bytes contain working registers and bit-addressable memory. The lower 32 bytes form four banks of eight
registers (R0-R7). Two bit s on the program mem ory st atus wor d (PSW) select which bank is in use. The next 16 bytes form a
bl ock of bit-addressable memory space at bit addressees 0x00-0x7F. All of the bytes in the lower 128 bytes are accessible
through direct or indirect addres sing. Table 5 shows the internal data memory map.
Address
Direct addr essin g
Indirect addressing
0xFF Special Functi on Registers
(SFRs) RAM
0x80
0x7F Byte-addressable area
0x30
0x2F Bit-addr essab le area
0x20
0x1F Regist er banks R0…R7
0x00
Table 5: Internal Data Memory Map
Special Function Regist ers ( SFRs)
A m ap of the Special Function Registers is shown in Table 6.
Hex\Bin Bit-address-
able Byte-addressable Bin/Hex
X000
X001
X010
X011
X100
X101
X110
X111
F8
INTBITS
FF
F0
B
F7
E8
WDI
EF
E0
A
E7
D8
WDCON
DF
D0
PSW
D7
C8
CF
C0
IRCON
C7
B8
IEN1
IP1
S0RELH
S1RELH
USR2
BF
B0
FLSHCTL
PGADR
B7
A8
IEN0
IP0
S0RELL
AF
A0
P2
DIR2
DIR0
A7
98
S0CON
S0BUF
IEN2
S1CON
S1BUF
S1RELL
EEDATA
EECTRL
9F
90
P1
DIR1
DPS
ERASE
97
88
TCON
TMOD
TL0
TL1
TH0
TH1
CKCON
8F
80
P0
SP
DPL
DPH
DPL1
DPH1
WDTREL
PCON
87
Table 6: Special Function Re gi sters Locations
Only a few addresses are occupi ed, the others are not implemented. SFRs spec ific t o the 651X are shown in bold print. Any
read access to unimplemented addresses will return undef ined dat a, while a n y w r i t e a c ces s wil l h av e n o ef f ec t . Th e r eg i s t er s
at 0x80, 0x88, 0x90, etc., are bit-a ddr ess abl e, all oth ers ar e byt e-addressable.
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Special Function Regist ers ( Generi c 80515 S FRs)
Table 7 shows the location of the SFRs and t he value they assume at reset or power-up.
Name Location Reset valu e Description
P0
0x80
0xFF
Port 0
SP
0x81
0x07
Stack Po inter
DPL
0x82
0x00
Dat a Poi nter Low 0
DPH
0x83
0x00
Dat a Poi nter High 0
DPL1
0x84
0x00
Dat a Poi nter Low 1
DPH1
0x85
0x00
Dat a Poi nter High 1
WDTREL
0x86
0x00
Wat chdog Ti mer R elo ad r egist er
PCON
0x87
0x00
UART Speed Control
TCON
0x88
0x00
Timer/Counter Control
TMOD
0x89
0x00
Timer Mode Control
TL0
0x8A
0x00
Timer 0, low byte
TL1
0x8B
0x00
Timer 1, high byte
TH0
0x8C
0x00
Timer 0, low byte
TH1
0x8D
0x00
Timer 1, high byte
CKCON
0x8E
0x01
Clock Control (Stretch=1)
P1
0x90
0xFF
Port 1
DPS
0x92
0x00
Dat a Poi nter select Regi ster
S0CON
0x98
0x00
Serial Port 0, Control Reg ister
S0BUF
0x99
0x00
Serial Port 0, Data B uffer
IEN2
0x9A
0x00
Int errupt Enabl e Regis ter 2
S1CON
0x9B
0x00
Serial Port 1, Control Reg ister
S1BUF
0x9C
0x00
Serial Port 1, Data B uffer
S1RELL
0x9D
0x00
Serial Port 1, Relo ad Regi s ter, low byt e
P2
0xA0
0x00
Port 2
IEN0
0xA8
0x00
Int errupt Enabl e Regis ter 0
IP0
0xA9
0x00
Int errupt Prior it y Reg ister 0
S0RELL
0xAA
0xD9
Serial Port 0, Relo ad Regi s ter, low byt e
P3
0xB0
0xFF
Port 3
IEN1
0xB8
0x00
Int errupt Enabl e Regis ter 1
IP1
0xB9
0x00
Int errupt Prior it y Reg ister 1
S0RELH
0xBA
0x03
Serial Port 0, Relo ad Regi s ter, high by te
S1RELH
0xBB
0x03
Serial Port 1, Relo ad Regi s ter, high by te
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Name
Location
Reset value
Description
USR2
0xBF
0x00
User 2 Por t , high ad dres s by te for MOVX@Ri
IRCON
0xC0
0x00
Int errupt R equ est Control Register
PSW
0xD0
0x00
Program Status Word
WDCON
0xD8
0x00
Baud Rate Cont rol R egister (o nly WDCO N.7 bit used)
A
0xE0
0x00
Accumulator
B
0xF0
0x00
B R egist er
Table 7: S pecial Function Regi sters Reset Values
Accumulator (ACC, A): ACC is the accumulator register. Most instructions use the accumulator to hold the operand. The
mnemonics for accumulator-sp ecif ic ins tr uct ions r efer to accumula tor as “ A”, not ACC.
B Register: The B regi ster is used during multiply and divide instructions. It can also be used as a s cr atch-pad register to hold
temporary data.
Program Status Word (PSW):
MSB LSB
CV AC F0 RS1 RS OV - P
Table 8: PSW Register Flags
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Bit Symbol Function
PSW.7
CV
Carry flag
PSW.6
AC
Auxiliary Carry flag f or BCD operations
PSW.5 F0 G eneral p urp ose Flag 0 availa ble for us er . Not to be confused with the F0 flag
in the
CESTATUS
register.
PSW.4 RS1 Regist er b ank select control bits. The contents of RS1 and RS0 select the working
register bank:
RS1/RS0
Bank sel ected
Location
00 Bank 0 (0x00 – 0x07)
01 Bank 1 (0x08 – 0x0F)
10 Bank 2 (0x10 – 0x17)
11 Bank 3 (0x18 – 0x1F)
PSW.3 RS0
PSW.2 OV Ov er flow fla g
PSW.1 - User defined flag
PSW.0 P
Parity flag, affec t ed by hardware to indicate odd / even num ber of “one” bits i n the
Acc umu lator , i.e. even pa r i ty.
Table 9: PSW bit functions
Stack Pointer (SP): The stack pointer is a 1-byte register initialized to 0x07 after reset. This register is incremented before
PUSH and CALL instructions, causing the stack t o begin at location 0x08.
Data Pointer: The data poi nter (DPTR) is 2 bytes wi de. The lower part is DPL, and the highes t is DPH. It can be loaded as a 2-
by t e r eg i st er (MO V DPTR, #d at a 1 6) or as tw o r eg i st er s ( e. g. MOV DPL,#data8). It is gener ally used t o access external code or
data space (e.g. MOVC A,@A+DPTR or MOVX A,@DPTR respectively).
Program Counter: The program counter (PC) is 2 bytes wide initialized to 0x0000 after reset. This register is incremented
during the fet ching operation c ode or when operating on data from program memory.
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Port Registers: The I/O ports are controlled by Special Function Regi ster s P0, P1, and P2. The contents of the SFR can be
observed on corresponding pins on the chip. Writing a ‘1’ to any of the ports (see Table 10) causes the corresponding pin t o
be at high level (V3P3), and writing a ‘0’ causes the corresponding pin to be held at low level (GND). The data direction
registers DIR0, DIR1, and DIR2 define individual pins as input or output pins (see section On-Chip Resources, DIO Ports for
details).
Register SFR
Address R/W Description
P0
0x80
R/W
Regist er for port 0 read and write operations (pins DIO0…DIO7)
DIR0
0xA2
R/W
Data direction register for port 0. Setting a bit to 1 means that the correspondi ng pin is
an output.
P1
0x90
R/W
Regist er for port 1 read and write operations (pins DIO8…DIO15)
DIR1
0x91
R/W
Data direction register for port 1.
P2
0xA0
R/W
Regist er for port 2 read and write operations (pins DIO16…DIO21)
DIR2
0xA1
R/W
Data direction register for port 2.
Table 10: Port Registers
All four ports on the chip ar e bi-di rectional. Each of them cons ists of a Lat ch (SFR ‘P0’ t o ‘P3’), an output dri ver, and an input
buff er, theref or e the MPU can output or r ead data t hrough any of these ports. Even if a DI O pin is configured as an output, the
state of the pi n can still be read by the MPU, for exam ple when counting pulses issued via DIO pins that are under CE contr ol .
Special Function Regist ers S pecific to the 71M 6513
Table 11 shows the location and description of the 71M6513-speci fic SFRs.
Register Alternative
Name SFR
Address R/W Description
ERASE
FLSH_ERASE
0x94
W
This r egist er is used to i nit iate eit her t he Flash Ma ss Eras e cyc le or
the F lash Page E rase cyc le. Specific patt ern s ar e expected for
FLSH_ERASE in or der t o ini ti at e t he approp r iat e Era se cy cle
(def ault =
0x00).
0x55 – Ini t iat e Fla sh Page Era se c ycle. M ust b e pr oceeded by a writ e
to FLSH_PGADR @ SFR 0xB7.
0xAA – Initiat e Flash M ass E rase cycle. M ust be proceeded by a
write to FLSH_MEEN @ SFR 0xB2 and the debug port must
be enabled.
Any other patt ern written t o FLSH_ERASE wi ll have no effec t .
PGADDR
FLSH_PGADR
0xB7
R/W
Flash Page Erase Address register containing the flash m emor y
page address (page 0 thru 127) that will be erased during the Page
Erase cycle (default = 0x00).
Must be re-writ ten f or ea ch new Page Era se cy cle.
EEDATA
0x9E
R/W
I2C EEP ROM i nterf ac e dat a reg ister
EECTRL
0x9F
R/W
I2C EEP ROM i nterf ac e cont rol regi st er. I f t he MP U wis hes to wr it e a
byte of dat a to E EPROM, i t plac es the dat a i n EEDATA and then
writes the ‘Transmit’ code to EECTRL. T he wr ite to EECTRL initiates
the transm it sequence. See the secti on I2C Interface (EEPROM) for
a description of the command and status bits available for EECTRL.
0xB2
R/W
Bit 0 (FLSH_PWE): Pro gram Writ e Enable:
0 – MOVX commands ref er to XRAM Space, normal operation
(default).
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Register Alternative
Name SFR
Address R/W Description
W
R/W
R
1 – MOVX @DPTR, A m ov es A to Program Space (flash) @ DPTR.
This bi t is aut omaticall y r eset after e ach byte written to flash . Wr i tes
to this bit are inhibited when interrupts ar e enabled.
Bit 1 (FLSH_MEEN): M ass Era se Enable:
0 – Ma ss Er as e dis abled (d efa ult ) .
1 – Mass Erase enabl ed.
Must be re-writ ten f or ea ch new M as s Er ase cycle.
Bit 6 (SECURE):
Enables sec urity provisions that prevent exter nal r eading of flash
m emory and CE program RAM. This bit is reset on c hip reset and
m ay o nly be set. Attempts t o writ e zero ar e ignor ed.
Bit 7 (PREBOOT):
Indic ates t hat the preb oot sequence is act ive.
WDI
0xE8
R/W
R/W
W
Only byt e operations on t he whole WDI register should be used
when writing. Th e byte m us t have all bits set excep t the bits that are
to be cleared.
The multi-pu rpose reg ister WDI contain s the followin g bits:
Bit 0 ( IE_XFER): X FER Int errupt Fl ag:
This flag monitor s th e XFE R_B USY interrupt. It is set by har dw ar e
and must be cleared by the int errupt handler
Bit 1 ( IE_RTC): RTC I nterr upt Fl ag:
This flag moni t ors the RTC_1SEC int errupt. It is set by har dware and
m ust be clear ed by the int errupt handler
Bit 7 (WD_RST): WD Timer Reset:
The WD T is res et w hen a 1 is wr i tten to t his b it.
INTBITS
INT0…INT6
0xF8
R
Int errupt i nputs. The MPU may read these bits to see the input t o
external interrupts INT0, INT1, up to INT6. These bits do not have
any mem ory and ar e primarily intended for debug use
Table 11: Special Function Registers
Instruction Set
All instructions of the generic 8051 microcontroller are supported. A complete l ist of the i nstruction set and of the associated
op-codes i s contained in the 651X Software User’s Guide (SUG).
UART
The 71M6513 includes a UART (UART0) that can be progr ammed to com municate with a variety of AMR mo d ul es . A s ec on d
UART (UART1) is connect ed to the optical port, as described in the opt ical port description.
The UA RT is a dedicat ed 2-wire seri al inter face, which can communicate with an external host proc essor at up to 38, 400 bits/ s
((with MPU clock = 1.2288MHz). The operati on of each pin is as follows:
RX: Serial input dat a are applied at this pin. Conforming to RS-232 standard, the byt es are input LSB first. The voltage appli ed
at RX must not exceed 3. 6V.
TX: T his pin is u sed t o out pu t t he serial d at a. The bytes ar e out put LSB f i rst.
The 71M6513 has s ever a l U AR T-related registers for the control and buffering of serial data.. A sin gl e S FR r eg is t er s er ves a s
both the transmit buffer and receive buff er (S0BUF, SFR 0x99 for UART0 and S1BUF, SFR 0x9C for UART1). W hen written by
the MPU, SxBUF acts as the transmit buffer, and when read by the MPU, it acts as the receive buffer. Writing data to the
transmit buffer starts the transmission by the associated UART. Received data are available by reading from the receive
buff er. Both UARTs can simultaneously transmit and receive data.
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WDCON[7] selects whet her timer 1 or the internal baud rate generator is used. All UART transfers are program mab le for par it y
enable, parity, 2 stop bits/1 stop bit and XON/XOFF options for variable communication baud rates from 300 to 38400 bps.
Table 12 shows how the baud rates are calculated. Table 13 shows t he selectable UART operation modes .
Using Timer 1
Using Internal Baud Rate Generator
Serial Interface 0
2smod * fCKMPU/ (384 * ( 256-TH1)) 2smod * fCKMPU/(6 4 * ( 210-S0REL))
Serial Interface 1
N/A fCKMPU/( 32 * (210-S1REL))
Note: S0REL and S1REL are 10-bit values derived by combining bits from the respective tim er reload registers. SMOD is t he
SMOD bit in th e S FR PCON. TH1 is t he high byt e of timer 1.
Table 12: Baud Rate Generation
UART 0
UART 1
Mode 0 N/A Start bit, 8 data bits, parit y, stop bit, variable
baud rate (internal baud rate generator)
Mode 1 Start bit, 8 data bits, stop bit,
variable baud rat e (internal baud
rate generator or timer 1)
Start bit, 8 dat a bits, stop bi t, variable baud rat e
( internal baud rate generato r)
Mode 2
Start bit, 8 data bits, parity, stop bit,
fi xed bau d rate 1/32 or 1/64 of
fCKMPU N/A
Mode 3
Start bit, 8 data bits, parity, stop bit,
variable baud rat e (internal baud
rate generator or timer 1) N/A
Table 13: UART Modes
No t e: P ar it y of s er i al da t a i s av a il a bl e t hr o u gh t h e P f l ag o f the a c cumul at o r. S ev en -bit serial modes with parity, such as those
used by the FLAG protocol, can be simulated by set ting and reading bit 7 of 8-bit output data. Seven-bit serial modes without
parity can be simulated by setting bit 7 to a constant 1. 8-bit serial modes with parity can be simulated by set ting and readi ng
t he 9th bit, using the control bits TB80 (S0CON.3) and TB81 (S1CON. 3) in t h e S0CON and S1CON SFRs for transmit and RB81
(S1CON.2) f or receive operations. SM20 (S0CON.5) and SM21 (S1CON.5) c an be used as handshake signal s for int er-processor
communication in multi-pr ocessor systems.
Serial Int erface 0 Control Regi st er (S0CON).
The function of the UART0 depends on the setting of the Serial Port Control Register S0CON.
MSB LSB
SM0
SM1
SM20
REN0
TB80
RB80
TI0
RI0
Table 14: The S0CON Register
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Serial Int erface 1 Control Regi st er (S1CON).
The function of the serial port depends on the sett i ng of the Serial Port Control Regi ster S1CON.
MSB LSB
SM - SM21 REN1 TB81 RB81 TI1 RI1
Table 15: The S1CON register
Bit Symbol Function
S0CON.7 SM0 These tw o bi ts set t he UA RT0 mode:
Mode
Description
SM0
SM1
0
N/A
0
0
1 8-bit UART 0 1
2 9-bit UART 1 0
3 9-bit UART 1 1
S0CON
.6
SM1
S0CON.5
SM20
Enables the inter-process or c om mu nicatio n fea ture.
S0CON
.4
REN0
If set, enabl es serial recepti on. Cleared by software to disable reception.
S0CON.3 TB80 The 9
th
tra nsmitted dat a bit in M odes 2 and 3. Set or clear ed by the
MPU, depending on the function it perform s (parity check, multiprocessor
c ommunication et c . )
S0CON.2 RB80 I n Modes 2 and 3 it is the 9
th
data bit received. In Mode 1, if SM20 is 0,
RB80 is the st op bit. In Mode 0 this bit is not used. Must be cleared by
software
S0CON.1
TI0
Tra nsmit interr upt flag, s et b y har dware a f ter c omplet ion of a seria l
tr ansfer. Must be c lea red by s oftware.
S0CON.0 RI0 Receive i nterr upt flag, set by har dware after completion of a ser ial
recept ion. Must be cleared by software
Table 16: The S0CON Bit Functions
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Bit
Symbol
Function
S1CON.7 SM Sets t he baud rate for UART1
SM
Mode
Description
Baud Ra te
0 A 9-bit UART variable
1 B 8-bit UART variable
S1CON.5 SM21 Enables the inter-proces sor commu nic ati on f eature.
S1CON.4 REN1 If set , enables serial reception. Cleared by softwar e t o disable recepti on.
S1CON.3 TB81 The 9
th
tra nsmitted dat a bit in M ode A. Set or c leared by t he MP U,
dependi ng on the func tion it performs (parity check, multiprocessor
c ommunication et c . )
S1CON.2 RB81 I n Modes 2 and 3, it is the 9
th
data bit rec eived. In Mod e B, if SM21 is 0,
RB81 is th e stop bi t. Must be cl eared by softwar e
S1CON.1
TI1
Tra nsmit interr upt flag, s et b y har dware a f ter c omplet ion of a seria l
tr ansfer. Must be c lea red by s oftware.
S1CON.0 RI1 Receive i nterr upt fl ag, set by har dware aft er complet io n of a serial
recept ion. Must be c lea red by s oftware
Table 17: The S1CON Bit Functions
Ti mers and Count ers
The 80515 has two 16-bit tim er/counter registers: Timer 0 and Timer 1. These registers can be configured for counter or t imer
operations.
In timer mode, the register is increm ented every machine cycle m eaning that it counts up after every 12 periods of the MPU
clock signal.
In counter m ode, the register is increm ented when the falling edge is observed at the corresponding input signal T0 or T1 (T0
and T1 are the timer gating inputs derived from certain DIO pins, see t he DIO Ports chapter). Since i t takes 2 m achine cycl es
to recognize a 1-to-0 event, the maximum input count rate is 1/2 of the oscillator frequency. There are no rest rictions on the
duty cycle, however to ensu re p rop er recognit ion of 0 or 1 state, an in pu t should be sta ble for at lea st 1 mac hin e cy cle.
Four operating modes can be selected for Tim er 0 and Tim er 1. Two Spec ial Function Regi ster s (TMOD and TCON) ar e u sed
to select the appropriate mode.
Timer/C ounte r Mode Control register (TMOD):
MSB LSB
GATE C/T M1 M0 GATE C/T M1 M0
Timer 1 Timer 0
Table 18: The TMOD Register
Bits TR1 (TCON.6) and TR0 (TCON.4) in the TCON r egister ( see Table 21 and Table 22) start their associated timers when set .
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Bit
Symbol
Function
TMOD.7
TMOD.3 Gate If s et, enables external gate c ontro l ( pin int0 or int1 for Cou nter 0 or 1,
respe ctively). When int0 or int1 is high, and TRX bit is set ( see TCON reg ister) , a
counter is incremented ever y f alling edge on t0 or t1 input pin
TMOD.6
TMOD.2 C/T Selects Timer or Counter operat ion. When set to 1, a Count er oper ation is
perfo r med. Wh en cleared to 0, the cor res ponding reg ister will fu nctio n as a Ti mer.
TMOD.5
TMOD.1
M1
Selects the mode for Timer/ Counter 0 or Tim er/Counter 1, as shown in TMOD
description.
TMOD.4
TMOD.0 M0 Selects the mode for Tim er/Counter 0 or Timer /Count er 1, as shown in TMOD
description.
Table 19: TMOD Regi ster Bit Descri ption
M1
M0
Mode
Function
0 0 Mode 0 13-bit C ounter/Timer w it h 5 lower b i ts in the
TL0
or
TL1
re giste r and the
remaining 8 bits in the TH0 or TH1 regi ster ( f or T i mer 0 and Ti mer 1,
r esp ect ively) . The 3 high or der bi ts of TL0 and TL1 are h eld at zero.
0 1 Mode 1 16-bit C ounter/Timer .
1
0
Mode2
8-bit aut o-reload Counter/Timer. The reload value is kept in TH0 or TH1,
while TL0 or TL1 is increme nte d every machine cyc le. When TL(x )
overf lows, a value f rom TH(x) is co pied to TL(x).
1
1
Mode3
If Ti mer 1 M1 and M0 bit s ar e set to '1', Timer 1 st ops. If Timer 0 M1 and M0
bits are set t o '1', Tim er 0 acts as two i ndependent 8-bit Timer/Counters.
Table 20: Timers/Counters Mode Desc ription
Note: TL0 i s affected by TR0 and gate cont r ol bits, and sets TF0 flag on overflow.
TH0 is affected by TR1 bit, and sets TF1 flag on overflow.
Tim er/Counter Cont r ol Register (TCON)
MSB LSB
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Table 21: The TCON Register
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Bit
Symbol
Function
TCON.7 TF1 The Timer 1 overflow flag is set by hardware when Timer 1 overfl ows. This flag
c an be cleared by software a nd i s aut omatical ly cleared whe n an interrupt is
processed.
TCON.6 TR1 Timer 1 Run control bit. If cl eared, Tim er 1 st ops.
TCON.5 TF0 Ti mer 0 overflo w
flag set by hardware when Timer 0 overflows. This flag can be
c lea red by s oftware a nd i s aut omatical ly clear ed wh en an interr upt is
processed.
TCON.4 TR0 Timer 0 Run control bit. If cl eared, Tim er 0 st ops.
TCON.3 IE1 Int errupt 1 edge f lag is set by har dware when the falling edge on external pin
int1 is observ ed. Cleared when an interrupt is processed.
TCON.2 IT1
Interrupt 1 type control bit. Selects either the falling edge or low level on input
pin to c aus e an i nterr upt.
TCON.1 IE0
Interrupt 0 edge flag is set by hardware when the falling edge on external pin
int0 is observ ed. Cleared when an interrupt is processed.
TCON.0 IT0
Interrupt 0 type control bit. Selects either the falling edge or low level on input
pin to c aus e inter ru pt.
Table 22: The TCON Register Bi t Functions
Table 23 s pec i fies t he combin ati ons of o per atio n m odes allo wed f or timer 0 a nd ti mer 1:
Timer 1
Mode 0 Mode 1 Mode 2
Timer 0 - mode 0
YES
YES
YES
Timer 0 - mode 1 YES YES YES
Timer 0 - mode 2
Not all owed Not allowed YES
Table 23: Timer Modes
Timer/C ounte r Mode Control Register ( PCON):
MSB LSB
SMOD
Table 24: The PCON Register
The SMOD bit in the PCON regist er do ubles th e baud rat e w hen set.
WD Timer (S oftware Watchdog Timer)
The software watchdog timer is a 16-bit counter that is incremented once every 24 or 384 clock cycles. After a reset, the
watchdog tim er is disabled and all r egisters are set to zero. The watchdog consists of a 16-bit cou nter ( WDT), a re load registe r
(WDTREL), prescalers (by 2 and by 16), and control logic. Once the watchdog is started, it cannot be stopped unless the
internal reset signal becomes active.
Note: It is recomme nded to use the hardware watchdog t imer instead of the software watchdog timer.
WD Timer Start Procedure: The W D T is s t ar t ed b y s et ti n g t h e SWDT fl ag. When t he WDT r egi ster ent er s th e st ate 0x7CFF ,
an asynchronous WDTS signal will becom e active. The si gnal W DTS set s bit 6 i n t he IP0 register and request s a reset stat e.
WDTS is clear ed ei th er by th e r eset signal or by changing t he stat e of the WD T.
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Refreshing the WD Timer: The watchdog timer must be refreshed regularly to prevent the reset request signal from
becoming active. This requirement imposes an obligation on the programmer to issue two instructions. The first instruction
sets WDT and the second instruction sets SWDT. The maximum delay allowed between setting WDT and SWDT is 12 clock
cycles. If this period has expired and SWDT has not been set, WDT is automatically reset, otherwise the watchdog timer is
reloaded with the content of the WDTREL register and WDT is automatically reset. Since the WDT requires exact timing,
firmware needs to be designed with special care in order to avoid unwanted WDT resets. Teridian strongly discourages the
use of the software WDT.
Special Function Registers for the WD Timer
Interrupt Enable 0 Register ( IEN0):
MSB LSB
EAL WDT ET2 ES0 ET1 EX1 ET0 EX0
Table 25: The IEN0 Regist er (see al so Table 32)
Bit
Symbol
Function
IEN0.6 WDT Watchdog timer refresh flag.
Set to initiat e a refr esh of the watchdog ti mer. Must be s et direct ly before SWDT is
s et to pr event a n un intent ional refres h of t he watc hdog timer . WDT is r eset by
hardware 12 clock cycles aft er it has been set.
Table 26: The IEN0 Bit Functi ons ( see also Table 32)
Not e: T he r em aini ng bits in t he IEN0 r egister are not used f or watchdog control
Int errupt Enable 1 Register (IEN1):
MSB LSB
EXEN2 SWDT EX6 EX5 EX4 EX3 EX2
Table 27: The IEN1 Regi ster (see also Tables 30/ 31)
Bit
Symbol
Function
IEN1.6 SWDT Wat ch dog t imer start/r efres h f la g.
Set to acti vate/refresh th e watc hdog ti mer. When dir ectly s et after s etting WDT, a
watchdog time r refresh is perfor med. Bit SWDT is re set by the hardware 12 cl oc k
cycles after it has been set.
Table 28: The IEN1 Bit Functi ons ( see also Tables 30/31)
Note: The r emai ning bi ts in the IEN1 register are not used for watchdog control
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Int errupt Priorit y 0 Register (IP0):
MSB LSB
-- WDTS IP0.5 IP0.4 IP0.3 IP0.2 IP0.1 IP0.0
Table 29: The IP0 Register (see al so Tabl e 45)
Bit
Symbol
Function
IP0.6
WDTS
W atchdog tim er st atus flag. Set when the watc hdog timer was started. Can be
r ead by software.
Table 30: The IP0 bit Functions (see also Table 45)
Note: The r emai ning bi ts in the IP0 r egister ar e not used for wat chdog contr ol
Watchdog Timer Reload Register (WDTREL):
MSB LSB
7 6 5 4 3 2 1 0
Table 31: The WDTREL Register
Bit
Symbol
Function
WDTREL.7 7 Prescaler select bit. W hen set, the watchdog is clocked t hrough an additional
divide-by-1 6 pr escaler
WDTREL.6
to
WDTREL.0 6-0 Se ve n bit re load valu e for the hig h-byt e of th e wat chdog t imer. Thi s val ue is
loaded to the WDT when a ref r esh is triggered by a consecutive sett i ng of bits
WDT and SWDT.
Table 32: The WDTREL Bit Functions
The WDTREL register can be loaded a nd re ad at any ti me.
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Interrupts
The 80515 provides 11 interrupt sources with four priority levels. Each source has its own request flag(s) located in a special
function register (TCON, IRCON, and SCON). Each interrupt request ed by the correspondi ng fl ag can be individually enabled or
disabled by the enabl e bits in SFRs IEN0, IEN1, and IEN2.
External interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other parts of the
71M6513/6513H, for example t he CE, DI O , RTC EEP ROM i nterf ace, comp ara tors.
Interrupt Overview : When an i nterrupt occurs, the MPU will vector to the predeter m ined addr ess as shown i n Table 50. Once
interrupt service has begun, it can be interrupted only by a higher priority interrupt. The interrupt service is terminated by a
return from instruction, "RETI". When a RETI instruction is perform ed, the processor will return to the instruction that would
have been next when the interrupt occurred.
When the interrupt condition occurs, the processor will also indicate this by setting a flag bit. This bit is set regardless of
wh eth er t he int erru pt i s en abled or di sabl ed. Eac h inter rupt f la g is sam pl ed once per m ac hine c ycl e, then sam pl es ar e pol led
by the har dware. If t he s ample indic ates a pendin g interr upt when th e interr upt i s en abl ed, then th e i nt errupt requ est f lag i s set.
On the next instruction cycle, the interrupt will be acknowledged by hardware forcing an LCALL to the appropriate vector
address, if the foll owing conditions are met:
• No inter rupt o f equal or higher pr iority is alr ead y in progress.
• An instruction is currently bei ng executed and is not com pleted.
• Th e inst ruction in pro gres s is not RET I or any write a ccess to the registers IEN0, IEN1, IEN2, IP0 or IP1.
Interrupt response will require a varying amount of time dependi ng on the state of the MPU when the interrupt occurs. If the
MPU is performing an i nterrupt servi ce wit h equal or greater priority, the new i nterrupt will not be invoked. I n other cases, the
response time depends on the current instruction. The fastest possible response to an interrupt is 7 machine cycles. This
includes one machine cycle for detecting the interrupt and six cycle s to perform the LCAL L.
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Special Function Registers for Interrupts:
Int errupt Enable 0 re gister (IE0)
MSB LSB
EAL WDT ES0 ET1 EX1 ET0 EX0
Table 33: The IEN0 Register
Bit Symbol Function
IEN0
.7
EAL
EAL
=0 – di sa ble a ll i nt errupts
IEN0.6
WDT
Not used for interrupt control
IEN0.5 -
IEN0.4 ES0 ES0=0 – dis able ser ia l channel 0 int errupt
IEN0.3 ET1 ET1=0 – di sable t i mer 1 overflow interrupt
IEN0.2 EX1 EX1=0 – dis able ext ern al interru pt 1
IEN0.1 ET0 ET0=0 – di sable t i mer 0 overflow interrupt
IEN0.0 EX0 EX0=0 – dis able ext ern al interru pt 0
Table 34: The IEN0 Bit Funct ions
Int errupt Enable 1 Register (IEN1)
MSB LSB
SWDT EX6 EX5 EX4 EX3 EX2
Table 35: The IEN1 Register
Bit
Symbol
Function
IEN1.7 -
IEN1.6
SWDT
Not used for interrupt control
IEN1.5 EX6 EX6=0 – di sable external interru pt 6
IEN1.4 EX5 EX5=0 – di sable external interru pt 5
IEN1.3 EX4 EX4=0 – di sable external interru pt 4
IEN1.2 EX3 EX3=0 – disable external inte r rupt 3
IEN1.1 EX2 EX2=0 – di sable external interru pt 2
IEN1.0 -
Table 36: The IEN1 Bit Funct ions
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Int errupt Enable 2 re gister (IE2)
MSB LSB
- - - - - - - ES1
Table 37: The IEN2 Register
Bit Symbol Function
IEN2.0 ES1 ES1=0 – dis abl e seria l channel 1 interru pt
Table 38: The IEN2 Bit Funct ions
Tim er/Counter Cont r ol register ( TCON)
MSB LSB
TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Table 39: The TCON Register
Bit Symbol Function
TCON.7
TF1
Timer 1 overflo w fla g
TCON.6 TR1 Not used for interrupt control
TCON.5 TF0 Ti mer 0 overflo w fla g
TCON.4 TR0 Not used for interrupt control
TCON.3 IE1 Exter nal interrupt 1 flag
TCON.2 IT1 Ex te rnal inte r rupt 1 typ e control b it
TCON.1 IE0 Exter nal interrupt 0 flag
TCON.0 IT0 External interrupt 0 type cont r ol bit
Table 40: The TCON Bit Func tions
Interrup t Reques t registe r (IRCON)
MSB LSB
EX6 IEX5 IEX4 IEX3 IEX2
Table 41: The IRCON Register
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Bit Symbol Function
IRCON.7 -
IRCON.6 -
IRCON.5 IEX6 External interrupt 6 edge fl ag
IRCON.4 IEX5 External interrupt 5 edge fl ag
IRCON.3
IEX4
External interrupt 4 edge fl ag
IRCON.2
IEX3
External interrupt 3 edge flag
IRCON.1
IEX2
External interrupt 2 edge fl ag
IRCON.0 -
Table 42: The IRCON Bit Func tions
Note: Only TF0 and TF1 (tim er 0 and tim er 1 overflow fl ag) will be automatically cl eared by hardware when the serv ice routine
is call ed (Signals T0ACK and T1ACK – por t ISR – activ e hig h when t he servic e rou ti ne is ca l led) .
Extern al Interrupts
The external interrupts are connected as shown in Table 43. The polarit y of interrupts 2 and 3 is programmable in the MPU.
Interrupts 2 and 3 should be programmed for falling sensitivity. The generic 8051 MPU literature states that interrupts 4
through 6 are defined as rising edge sensitive. Thus, the hardware signals attached to interrupts 5 and 6 are inverted to
achieve the edge polarity shown in Table 43.
SFR (special f unction register) enable bits must be set to permit any of these i nterrupts to occur. Likewi se, each i nterrupt has
its own flag bit that is set by the interrupt hardware and is reset automatically by the MPU interrupt handler (0 through 5).
XFER_BUSY and RTC_1SEC, which are OR-ed together, have their own enable and flag bits in addition to the interrupt 6
enable and flag b its (see Table 44), and t hese int errupts must be clea red by t he MPU software.
External
Interrupt Connection Polarity Flag Reset
0 Digit al I/O High Priority see DIO_Rx automatic
1 Digital I/O Low Priority see DIO_Rx automatic
2 Comparator 2 or 3 falling automatic
3 CE_BUSY falling automatic
4 Comparator 2 or 3 rising automatic
5
EEPROM busy
falling
automatic
6 XFER_BUSY OR RTC_1SEC falling manual
Table 43: Ex te rnal MPU Interru pts
Interrupt 6 is edge-sensitive. The RTC_1SEC interrupt from the RTC and the XFER_BUSY interrupt from the CE are com-
bined using a logic OR function and the result is routed into interrupt 6. Therefore, both flags must be cleared at least once
durin g ini ti ali zati on, a nd both fl ags m us t alw ays be cl eared bef or e exiting t he int errupt ser v ice routin e ( IS R ) for i nterr upt 6.
Note 1: If cleari ng of both fl ags i s not performed, t hen no edge can occur to trigger int errupt 6 later r esulting in t he I SR for the
XFER_BUSY ce asing to run.
Note 2: Clearing bot h fl ags reliably requires some care. Ei ther flag can be set by hardware while interrupt 6 code is running on
behalf of the other int errupt. In t his situation, the unprocessed int errupt can cr eate a lockout conditi on similar to the one in note
1. To preven t thi s l oc kout one m us t alw ays process both int er ru pt flags in t he same s ervic e r outi ne.
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Not e 3: A f ter a r eset from an in-circu i t em ul ator, the IE_XFER flag m ay not be cleared because the CE may continue to run.
The fla gs fo r the RTC_1SEC and the XFER_BU SY in te rrupts are located in the WDI SFR (add re ss 0xE8) .
Enable Bit
Description
Flag Bi t
Description
EX0 Enable exter nal interrupt 0 IE0 External interrupt 0 flag
EX1
Enable external interrupt 1
IE1
External interrupt 1 flag
EX2 Enable exter nal interrupt 2 IEX2 External interrupt 2 flag
EX3
Enable external interrupt 3
IEX3
External interrupt 3 flag
EX4
Enable e x te rnal inte r rupt 4
IEX4
External interrupt 4 flag
EX5 Enable exter nal interrupt 5 IEX5 External interrupt 5 flag
EX6 Enable exter nal interrupt 6 IEX6 External interrupt 6 flag
EX_XFER Enable XFER_BUSY interrupt IE_XFER XFER_BUSY i nterr upt flag
EX_RTC Enable RTC_1SEC inter r upt IE_RTC RTC_1SEC interrupt flag
Table 44: Control Bits for External Interrupts
In t errup t P rio rity Level Structure
All interrupt sources are combined in groups, as shown in Table 45:
Group
0 Ex ternal interrupt 0 S eria l ch annel 1 inter rup t
1 Timer 0 inter ru pt - Ex ternal interrupt 2
2 Ex ternal interrupt 1 - Ex ternal interrupt 3
3 Timer 1 inter ru pt - Ex ternal interrupt 4
4 Seria l ch annel 0 i nt errupt - External inte r rupt 5
5 - - Ex ternal interrupt 6
Table 45: Priority Level Gr oups
Each group of interrupt sources can be programmed individually to one of four priority levels by setting or clearing one bit in
the special function register IP0 and one in IP1. If req ues ts o f the s am e priori ty l evel a re r eceiv ed si m ultan eously , an int ern al
polling sequence as per Table 49 det er mines which request i s s ervic ed fi rs t .
IEN enable bits m ust be set to permit any of these int errupts to occur. Likewise, each interrupt has it s own flag bit that is set by
t he i nt erru pt hardware and is reset automatically by the MPU inter rupt handler (0 through 5). XFER_BUSY and RTC_1SEC,
which are OR-ed together , have their own enable and flag bits in addi ti on to the int errupt 6 enabl e and fl ag bits (see Table 44),
and these int errupts m ust be cl eared by the MPU sof twar e.
An over v iew of the i nterrupt stru ctur e i s sh own in Figure 7.
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Int errupt Priorit y 0 Register (IP0)
MSB LSB
-- WDTS IP0.5 IP0.4 IP0.3 IP0.2 IP0.1 IP0.0
Table 46: The IP0 Register:
Note: WDTS is not used for interrupt controls
Int errupt Priorit y 1 Register (IP1)
MSB LSB
- -
IP1.5
IP1.4
IP1.3
IP1.2
IP1.1
IP1.0
Table 47: The IP1 Register:
IP1.x IP0.x Priority Level
0
0
Level0 (lo w est)
0 1 Level1
1 0 Level2
1 1 Level 3 ( highest)
Table 48: Priority Levels
Ex ternal interrupt 0
Polling sequence
Serial channel 1 in terr upt
Timer 0 inter ru pt
Ex ternal interrupt 2
Ex ternal interrupt 1
Ex ternal interrupt 3
Timer 1 inter ru pt
Ex ternal interrupt 4
Serial channel 0 in terr upt
Ex ternal interrupt 5
Ex ternal interrupt 6
Table 49: Int errupt Polling Sequence
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In t errup t Sources and Vectors
Table 50 shows the interrupts with their ass ociated flags and vector addresses.
Int errupt Request Flag Description Interrupt Vector Address
IE0 Ex te rnal inte r rupt 0 0x0003
TF0
Timer 0 inter ru pt 0x000B
IE1
Ex ternal interrupt 1
0x0013
TF1 Timer 1 inter ru pt 0x001B
RI0/TI0 Seria l chann el 0 interrupt 0x0023
RI1/TI1 Serial c hannel 1 in terr upt 0x0083
IEX2 Ex te rnal inte r rupt 2 0x004B
IEX3
Ex ternal interrupt 3 0x0053
IEX4
Ex ternal interrupt 4 0x005B
IEX5
Ex ternal interrupt 5
0x0063
IEX6 Ex te rnal inte r rupt 6 0x006B
Table 50: Interrup t V e ctors
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Figure 7: Interrupt Structure
IE0
External
Interrupt
Flags
RI1
TI1
Internal
Interrupt
Flags
Source
>=1
TF0
INT2
IE1
INT3
TF1
INT4
RI0
TI0 >=1
INT5
INT6
>=1
IRCON.1
I2FR
IRCON.2
I3FR
IRCON.3
IRCON.4
IRCON.5
IEN0.7
IP1.0/
IP0.0
IP1.1/
IP0.1
IP1.2/
IP0.2
IP1.3/
IP0.3
IP1.4/
IP0.4
IP1.5/
IP0.5
Interrupt
Control
Register
Priority
Assignment
Interrupt
Vector
Polling Sequence
Interrupt
Enable
Logic and
Polarity
Selection
DIO
UART1
(optical)
Tim er 0
Compar-
ators
Compar-
ators
DIO
Tim er 1
CE_BUSY
UART0
EEPROM/
I2C
XFER_BUSY
RTC_1S
IEN0.0
IEN2.0
IEN0.1
IEN1.1
IEN0.2
IEN1.2
IEN0.3
IEN1.3
IEN0.4
IEN1.4
IEN1.5
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On-Chip Resources
DIO Por t s
The 71M6513/6513H includes up to 22 pins of general purpose digital I/O. 18 of these pins are dual function and can
alternat ively be used as LCD dr iver s. Figure 8 shows a blo ck diagram of t he DI O sec t ion.
On reset or power-up, all DIO pins are i nputs until they are configured for the desired direction. The pins are configured and
controlled by t he DIO and DIO_DIR reg is ters ( SF Rs) and by th e fi ve bit s of t he I/O r egi ster LCD_NUM (0x2020[ 4:0]). See the
description for LCD_NUM i n the I/O RAM Section for a t able listing the available segm ent pins versus DIO pins, depending on
the selection for LCD_NUM. Generally, increasing the value for LCD_NUM will configure an increasing number of general
purpose pins to be LCD segment pins, starting at the higher pi n num bers.
Figure 8: DIO Port s Block Diagram
DIO
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Pin numbe r
18
19
20
21
60
61
62
63
67
68
69
70
98
99
30
31
Pin type
DIO
Multi-use
Multi-use
Dat a Register bit
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
DIO0=P0 (SFR 0x80)
DIO1=P1 (SFR 0x90)
Directi on Register
bit
--
--
--
--
4
5
6
7
0
1
2
3
4
5
6
7
DIO_DIR0 (SFR 0xA2)
DIO_DIR1 (SFR 0x91)
Internal Resources
Configurable
Y Y Y Y Y Y Y Y Y Y Y Y N N N N
DIO
16
17
18
19
20
21
22
23
Pin numbe r
34
16
17
64
65
66
--
--
Pin type
Multi-use
Dat a Register bit
0
1
2
3
4
5
--
--
DIO2=P2 (SFR 0xA0)
Directi on Register
bit
0
1
2
3
4
5
--
--
DIO_DIR2 (SFR 0xA1)
Internal Resources
Configurable
N N N N N N -- --
Table 51: Dat a Registers, Dir ection Registers and Internal Resources for DI O Pin G roups
COM0..3
LCD DI SPLAY
DRIVER
DIGITAL I/O
LCD_E N
LCD_CL K
LCD_MODE
DIO_GP
SEG20..23
DIO_0..3
SEG28/DIO8 ..
SEG31/DIO11
LCD_NUM
DIO_OUT
DIO_IN
LCD_NUM
PULS EV/W
SEG24/DIO4 ..
SEG27/DIO7
SEG32/DIO12 ..
SEG41/DIO21
SEG0..2, SEG3/SCLK,
SEG4/SSDATA,
SEG5/SFR, SEG7..19
DIO_EEX
SEG6/SRDY
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Each pin declared as DIO can be configured independentl y as an input or output wit h the bits of the DIO_DIRn registers. Table
51 lists the directi on registers and configurability associated with each group of DIO pins. Table 52 shows the configuration for
a DIO pin through its associated bi t in its DIO_DIR register.
DIO_DIR bit
0 1
DIO Pin Func tion input output
Table 52: DIO_DIR Control B it
Values read from and writt en into the DIO ports use the data registers P0, P1 and P2.
A 3-bit configuration word, I/O RAM register, DIO_Rx (0x2009[2:0] through 0x200E[6:4]) can be used for certain pins, when
configured as DIO, t o individually assign an internal resource such as an int errupt or a timer control (see Table 51 for D IO pins
available for thi s option). This way, DIO pins can be tracked even if they are config ured as out puts. This f eatur e i s usef ul for
pulse counti ng. The control resources selectable for the DIO pins are li sted in Table 53. If more than one input is connected to
the same resource, the resource s are combine d using a logical OR.
DIO_R
Value Resource Selected f or DIO Pin
0 NONE
1 Reserved
2 T0 (count er0 clock)
3 T1 (count er1 clock)
4 High priority I/O inte rrupt (INT0 rising)
5 Low prior i ty I / O i nterr upt (INT1 rising)
6
High priority I/O interrupt (INT0 fall ing)
7 Low prior i ty I / O i nterr upt (IN T1 f all in g)
Table 53: Selectable Controls using the DIO_DIR Bits
Additionally, if DIO6 and DIO7 are declared outputs, they can be configured as dedicated pulse outputs (WPULSE = DIO6,
VARPULSE = DIO 7) using t he I/O RAM r egisters DIO_PW (0x2008[2]) and DIO_PV (0x2008[3]). In this case, DIO6 and DI O7
are under CE cont rol. DIO4 and DIO5 can be configured to impl ement the EEPROM Interface by s et ting the I/O RAM r egi ster
DIO_EEX (0x2008[4]).
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Physical Memory
Data bus addr ess space i s alloc at ed to on-chip memory as shown in Table 54.
Address
(hex) Memory
Technology Memory Type Typical Usage Wait States
(at 5MHz) Memory Size
(bytes)
0000-FFFF Flash Memory Non-volatile
Program and non-volatile
data
0 64KB
0000-07FF
Static RAM
Battery-buffered
MPU dat a RAM
0
2KB
1000-13FF
Static RAM
Volatile
CE data
5
1KB
2000-20FF Static RAM Volatile
Configuration RAM
(I/O RAM)
0 256
3000-3FFF
Static RAM
Volatile
CE Program code
5
4KB
Table 54: MPU Data Memory Map
Flash Memory: The 71M 6513 includes 64KB of on-chip flash me mory. The flash me mory is inte nded to prima rily conta in MPU
program code. In a typi cal application, it also contains images of the CE program code, CE coefficients, MPU RAM, and I/O
RAM. On power-up, befor e enabling the CE, the MPU must copy these images to t heir respective m em ory locations.
Th e I/O RAM bit reg ist er FLASH66Z defines t he pulse width for accessing flash m emory. To minimize supply current draw,
thi s bit should be set to 1.
Flash erasure is initiated by writing a specific data pattern to specific SFR registers in the proper sequence. These special
patt ern/sequence requirements prevent inadvertent er asure of the flash mem ory.
The mass era se s equence is:
1. Write 1 t o the FLSH_MEEN bi t (SFR addr ess 0xB2[ 1].
2. Write pattern 0xAA to FLSH_ERASE (SFR addre ss 0x 94)
Note: The mass er as e cycle can only be initiated when the ICE port i s enabled.
The page erase sequenc e is:
1. Write the page addre ss to FLSH_PGADR (SFR address 0xB7[7:1]
2. Write pattern 0x55 t o FLSH_ERASE (SFR addres s 0x94)
Writing to flash memory:
The MPU may write to the flash memory for non-volatile data storage or when implementing a boot-loader. The I/O RAM
register FLSH_PWE (flash program write enable, SFR B2[0]) differentiates 80515 data store instructions (MOVX@DPTR,A)
between Flash and XRAM writes. Before setting FLSH_PWE, all interrupts need to be disabled by setting EAL =1. After the
write oper ation, FLSH_PWE must be clea red .
The original state of a flash byte is 0xFF (all bi ts are 1 ). Overwriting programmed flash cells with a different value usually re-
quir es that the c el l i s erased first. Since cel ls c annot be erased indi vidually, the page has t o be copied to RAM, followed by a
page erase. After this, the page can be updated in RAM and then written back to the fl ash mem or y.
Writing to flash locations will affect the corresponding XRAM cells, i.e. 0x2000 to 0x20FF (I/O RAM), 0x0000 to
0x07FF (MPU RAM), plus CE DRAM and CE PRAM. It is critical to maintain the integrity of the cells 0x2000…0x2007
as a mi nimum ( where im portant system settings are stor ed) during the flas h-write oper at ion. This can be achieved by
excluding the critical address es from the write oper ation.
MPU RAM: The 71M6513 includes 2KB of stat ic RAM memory on-chip (XRAM), which are backed-up by t he battery pl us 256-
bytes of inter nal RAM in t he MPU core. The 2KB of static RAM are used for data s t orage during normal MPU operations.
CE DRAM: The C E D RA M is the data memory of the CE. The MPU can read and write the CE DRAM as the prima ry mea ns of
data com mu nicat ion between t he t wo proc ess or s.
CE PRAM: The CE PRAM is t he program m emory of the CE. The CE PRAM has to be loaded wit h CE code before the CE
starts operating. CE PRAM cannot be accessed by the MPU when the CE is runn ing .
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Oscillator
The oscillator drives a standard 32.768kHz wat ch crystal (see Figure 9). Crystals of t his type are accurate and do not require a
high current oscillator circuit. The oscillator in the 71M6513 Power Meter IC has been designed specifically to handle watch
crystals and is compat ible with their hi gh impedance and limited power handl ing capabil ity. The os cillator power dissipation is
very low to m aximize the lifetim e of any battery backup devi ce att ached to the VBAT pin.
Figure 9: Oscillator C ircuit
The oscillator shoul d be placed as close as possible t o the IC, and vias should be avoided.
An external resisto r across the crystal must no t be adde d.
Real-T ime Clo ck ( RTC)
The RTC is driven directly by the crystal oscillator. In the absence of the 3.3V supply, the RTC is powered by the external
battery (VBA T pin) . The RT C consists of a counter chain and output registers. The counte r chain consists of se conds, minute s,
hours, day of week, day of mont h, month, and year. The RTC is capabl e of processing leap years. Each count er has its own
output regi ster. W henever the MPU reads the sec onds register, all other output registers are automatically updated. Since the
RTC clock is not coherent to the MPU clock, the MPU must read the seconds register until two consecutive reads are the
sam e (r equ ir es ei ther 2 or 3 rea ds) . At thi s poi nt, al l R TC o ut put reg ister s will h av e th e co rr ect tim e. Regard less of t he MPU
clock speed, RTC reads require one wait state.
The RTC int errupt must be enabl ed using t he I/O RAM register EX_RTC ( addr ess 0x2002[1]). RTC tim e is set by writing to the
I/O RAM registers RTC_SEC, RTC_MIN, through RTC_YR. Each byte written to RTC must be delayed at least 3 CK32 cycles
from any pr evious byte wr itten to RTC.
Two time correction bits, the I/O RAM registers RTC_DEC_SEC (0x201C[1]) and RTC_INC_SEC (0x201C[0]) are provided to
adjust the RTC time. A pulse on one of these bits causes the time to be decremented or incremented by an addit i onal second
at the next update of the RTC_SEC register. Thus, if the crystal temperature coefficient is known, the MPU firmware can
integ rate t emperatur e and correct the RTC time as neces sar y as discussed i n temperatur e compensation.
Comp arat ors (V2, V3)
The 71M6513/6513H includes two programmable comparators that are connected to the V2 and V3 pins. The I/O RAM
register COMP_INT (0x2003[4:3]) al l ows th e u s er t o det er m i ne i f compa r at ors 2 and 3 wi ll t rigger an interrupt to the MPU. The
output of each comparator is available in the COMPSTAT register. VBIAS is used as the threshold, and built-in hysteresis
prevents eac h com parator from repeatedly respondin g to low -amplitude noi se.
Comparators 2 and 3 can be used f or early warning of power faults, or for monitoring of batter y or other DC voltages. If they
are both selected to int errupt the MPU, their out puts will be XORed together . The volt age at V3 i s al so available to t he ADC in
the A FE, but t he c omp ara tor should not b e used when V 3 is used f or analo g mea suremen ts.
Com parator 1 i s part of the power fault cir cuitry ( see section V1 Pin) and cannot be pr ogramm ed.
crystal
XOUT
XIN
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LCD Dri vers
The 71M6513 contains 24 dedicated LCD segm ent drivers and 18 multi-purpose pi ns which may be configured as additional
LC D s eg men t d ri v er s ( s ee I / O RA M r eg i s t er LCD_NUM). The 71M6513/6513H i s capable of drivi ng between 96 t o 168 pi xel s
of LCD display with 25% duty cycle. At seven segments per digit, the LCD can be designed for 13 to 24 digits for display.
Since each pixel is addressed individually, the LCD display can be a combination of alphanumeric digits and enunciator
symbols. The information to be displayed is written into the lower four bits of I/O RAM registers LCD_SEG0 through
LCD_SEG41. Bit 0 corresponds to t he segmen t selected when COM0 pin is acti ve while b i t 1 is allo cated to COM1.
The LCD driver circuitry is grouped i nto 4 common outputs (COM0 to COM3) and up to 42 segment out puts (see Table 55).
The typical LCD map is shown below.
SEG0 SEG1 SEG2 SEG3 … SEG27 … SEG41
COM0 P0 P4 P8 P12 ... P108 ... P164
COM1 P1 P5 P9 P13 … P109 ... P165
COM2
P2
P6
P10
P14
...
P110
...
P166
COM3
P3
P7
P11
P15
...
P111
...
P167
Table 55: Liquid Crystal Display Segment Table (Typical)
Note: P0, P1, … R epr esen t the pixel/s egment numb ers on the LCD.
A charge pum p suitable for driving VLCD is included on-chi p. Thi s circuit creates 5V from the 3.3V supply. A contrast DAC i s
provided that permits the LCD full-scale voltage to be adjusted between VLCD and 70% of VLCD. The LCD_NUM register
defin es the num ber of dual purpose pins used for LCD segm ent interf ace.
LCD Vol t age Boost Circu itry
A voltage boost circuit may be used to generate 5V from the 3.3V supply to support low-power 5V devices, such as LCDs.
Figure 10 shows a block diagram of the voltage boost circuitry including the voltage regulators for V2P5 and V2P5NV. When
activated using the I/O RAM regi ster LCD_BSTEN (0x2020[7]), the boost circuitry provides an AC voltage at the VDRV output
pin (see t he Appl ications section for details).
Figure 10: LCD Vol t age Boost Circuitry
GNDD
V3P3D
VBAT
VOLT
REG
0.1V
V2P5
VLCD
VDRV
VOLTAGE
BOOST
LCD_BSTEN
LCD_IBST
GNDD
GNDD GNDD
V2P5
V3P3D
V2P5NV
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UART (UART0) and Optical Port (UART1)
The 71M6513/6513H includes an interface to implement an IR or optical port. The pin OPT_TX is designed to directly drive an
external LED for transmitting data on an optical link (low-active). The pin O PT_RX, also low-active, i s designed to sense the
input from an external photo detector used as the receiver for the optical link. These two pins are connected to a dedicated
UART port . O PT_TX can be tristated if it is desired to multiplex another I/O pin to the OPT_TX output. The control bit for the
OPT_TX output i s the I /O RAM register OPT_TXDIS (0x2008[5]).
Hardw are Reset M echanisms
Sever al conditions will cause a har dware reset of the 71M6513/6513H:
• Voltage at the RESETZ pin low
• Voltage at the E_RST pin low
• Vo lt age at the V1 pi n b elo w r eset t hres hold (VBIA S )
• The cr ystal frequency monitor detected a cr y stal malfunction
• Hardware Watchdog timer
Reset Pi n (RE S ETZ)
When the RESETZ pin is pulled low (or when V1 < VBIAS), all digital activity in the chip stops while analog circuits are still
active. The osci ll ator and RTC module continue to run. Additionally, all I/O RAM bits are cl eared.
Hardware Watchd og Timer
In addition to the basic software watchdog timer i ncluded in the 80515 MPU, an independent, r obust, fi xed-duration, hardware
watchdog timer (W DT) is included in the 71M6513/6513H. This tim er will reset t he MPU if it is not refreshed periodi cally, and
can be used to recover the MPU in situations where program control is lost.
The watchdog tim er uses t he RTC crystal oscillator as its time base and requir es a reset under MPU program control at least
every 1.5 seconds. When the WDT overflo w oc c ur s, t he M PU i s m oment a ri l y res et a s if R ES ET Z w er e p ul l ed l o w f or hal f o f a
crystal oscillator cycle. Thus, after 4100 cycles of CK32 (32768Hz c l ock) , the MPU program will be launched fr om address 00.
An I/O RAM register status bit, WD_OVF (0x2002[2]), i s set when WDT overflow occurs. This bit i s powered by the VBAT
pin and can be read by the MPU to determi ne if the part is initializing after a W DT overflow event or after a power up. After
r ead in g this bit, MP U f irmw are must clear WD_OVF. The WD_OVF bit is also clear ed by th e RES ETZ pin .
The watchdog timer also includes an oscillator check. If the crystal oscillator stops or slows down, WD_OVF is set and a
s ystem reset will be performed when t he crysta l oscillator r esumes .
Th ere i s no i nt ern al digi tal state that deactivates the WDT. For debug purposes, however, the W DT can be di sabl ed by tying
the V1 pin to V3P3 (see Figure 11 and WD Disable Threshold [V1-V3P3A] in the Comparator Section of the Electrical
Specif ications). Of course, t his also deactivates the power fault detection implem ented wi th V1. Since t here is no way in firm-
ware to disable the crystal oscillator or the WDT, it is guaranteed that whatever state the MPU might find itself in, it will be
reset to a known s t ate upon watchdog timer over flow.
In normal operation, the WDT is r eset by per iodically writing a one t o t he WDT_RST bi t . The watchdog timer is also r eset when
WAKE=0 and, dur ing development, when a 0x14 command is r eceived from the ICE port.
Crystal Frequency Monit or
The hardware watchdog timer also includes an oscillator check. If the crystal oscillator stops or slows down, the I/O RAM
register WD_OVF is set and a s ystem reset will be performed wh en the cr ystal o scillator r esumes.
V1 Pin
The c ompara tor at t he V1 pi n co ntrols t he st ate of th e digital c ircuitry on the chi p. When V1 < VBIAS (or when the RESETZ pin
is pull ed low), all di gital activity in the chip st ops while analog circuits including the oscillator and RTC modul e are st il l active.
Additionally, when V1 < VBIAS, al l I/O RAM bits are cleared. As long as V1 i s greater t han VBIAS, the i nternal 2.5V regulator
wil l continu e to p rovid e power to t he digital s ectio n.
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Figure 11: Voltage Range for V1
In t ernal Clocks and Clo ck Dividers
All internal clocks are based on the watch crystal frequency (CK32 = 32,768Hz) applied to the XIN and XOUT pins. The PLL
multiplies this frequency by 150 to 4.9152MHz. This frequency is supplied to the ADC, the FIR filter (CKFIR), the clock test
output pin (CKTEST), the CE DRAM and the clock generator. The clock generator provides two clocks, one for the MPU
( CKMPU) and one for the CE ( CKC E).
The MPU clock frequency is determined by the I/O RAM register MPU_DIV (0x2004[2:0]) and can be CE*2-MPU_DIV Hz
where MPU_DIV varies from 0 t o 7 (MPU_DIV is 0 on power-up). This makes the MPU clock scalable from 4.9152MHz d own
to 38. 4kHz.
The circuit also generates a 2x MPU clock for use by the emulator. This clock is not generated when the I/O RAM register
ECK_DIS (0x2005[5]) is ass erted by the MPU.
I2C Int erf ace ( E E P ROM)
A dedicat ed 2-pi n serial int erface implem ents an I2C driv er that can be used to communi c at e w it h ext er n a l EE PRO M dev i c es .
The interface can be multiplexed onto the DIO pins DIO4 (SCK) and DIO5 (SDA) by setting the I/O RAM register DIO_EEX
(0x2008[4]). The MPU communicates wit h the interface through t wo SFR registers: EEDATA (0x9E) and EECTRL (0x9F). If the
MPU wishes to writ e a byte of data to EEPROM, it places the data in EEDATA and then writ es the ‘Transmit ’ code to EECTRL.
Th e w r i t e t o EECTRL initiates the transmit sequence. By obser ving t he BUSY bit i n EECTRL the MPU can determine when the
transmit operation is finished (i.e. when the BUSY bit tr ansitions from 1 to 0) . INT5 i s also as serted when BUSY fal ls. The M P U
can then check the RX_ACK bit to s ee if the EEPROM acknowledged t he transmission.
A b yt e is rea d by wri ti ng t he ‘ Recei ve’ command to EECTRL and waiting for BUSY t o fal l. Up on compl et ion , t he r ecei ved data
will appear in EEDATA.
The serial transmit and receive clock is 78kHz during each transmission, and SCL is held in a high state until the next
tr ansm ission. The bits in EECTRL are show n in Table 56.
The EEPROM interface can also be operat ed by controlling the DIO4 and DIO5 pins directly. However, controlling DIO4 and
DIO5 directly is discouraged, because it may tie up the MPU to the point where it may become t oo busy to process
interrupts.
V3P3
V3P3 -
400mV
V3P3-10mV
VBIAS
0V
Battery or
reset
mode
Normal
operation,
WDT
enabled
WDT dis-
abled
V1
when
(V1 < VBIAS)
the battery is
enabled
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Note: Clock stretching and multi-mas te r operat ion are no t sup ported fo r the I2C i nt erfac e.
Status
Bit
Name Read/
Write
Reset
State
Polarity Description
7 ERROR R 0 Positive 1 when an illegal com m and is received.
6 BUSY R 0 Positive 1 when serial dat a bus is busy.
5 RX_ACK R 1 Negative 0 indicates that the EEPROM sent an ACK bi t.
4
TX_ACK
R
1
Negative
0 indicates when an ACK bit has been sent to the EEPROM
3-0 CMD[3:0] W 0 Positive,
s ee C M D
Table
CMD Operation
0 No-op. Applying the no-op command will stop the I2C clock
( SCK , DIO4) . Fail ure to issu e t he no-op command wi ll keep
the SCK signal toggling.
2 Receive a byt e f rom EEPROM an d send ACK.
3 Transmit a byte to EEPROM.
5 Issue a ‘ STOP ’ s equ ence.
6
Receive t he l ast byt e from E EPROM an d do not s end ACK .
9 Issue a ‘ START ’ seq uence.
Others No Operati on, set the ERROR bit.
Table 56: EECTRL Status Bits
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Battery
The VBAT pin provides an input for an external battery t hat can be used to support t he crystal oscillator, RTC, the WD_OVF bit
and XRAM in the absence of the main power suppl y. If t he batt ery is not used, t he VBAT pin shoul d be connected to V3P3.
Internal Vol tages (VBIAS, VBAT, V2P5)
The 71M6513 requires two supply voltages, V3P3A, for the anal og section, and V3P3D, for the digital section. Bot h voltages
can be tied together out side the chi p. The i nternal supply voltage V2P5 is generated by a regulator from t he 3.3V suppli es.
The batt ery volt age, VBAT, is r equi red when crystal oscillator, RTC and XRAM are required t o keep operati ng whil e V3P3D i s
removed (battery mode). VBAT, usually supplied by an external battery, powers crystal oscillator, RTC and XRAM (and the
WD_OVF bit).
VBIAS ( 1.5V) is generated int ernally and used for the comparators V1, V2 and V3.
Test Ports
TMU XO UT P i n: One out of 16 di gital or 4 analog signals can be s elected to be output on the TMUXOUT pin. The function of
the multiplexer is controlled with the I / O R A M r egist er TMUX (0x2000[3:0]), as shown in Table 57.
TMUX[3:0] Mode Function
0 analog DGND
1 analog IBIAS
2 analog PLL_2.5V
3 analog VBIAS
4 digital RT M (R eal ti me output from C E)
5 digital WDTR_EN (Comparator 1 O utput AND V1LT3)
6 digital V2_OK (Compar ator 2 Output)
7
digital
V3_OK (Comparator 3 Output)
8 digital RXD (from Optical interface)
9 digital MUX_SYNC
A digital CK_10M
B digital CK_MPU
C -- r eserved f or p ro duc t ion test
D
digital
RTCLK
E digital CE_BUSY
F digital XFER_BUSY
Table 57: TMUX[3:0] Selections
Em ulator Port: The em ulator port, consisting of the pins E_RST, E_TCLK and E_RXTX provides cont rol of the MPU through
an external in-circuit emulator. The E_TBUS[3:0] pins, together with the E_ISYNC/BRKRQ add trace capability to the
emula t or. The emulat or port is c omp atible wi th the ADM51 em ulat ors manufa c tu red by Si gn um Sys tems.
The s ig nals of t he emula tor por t have w eak pul l-ups . Adding 1k Ω pull-up resistors on the PCB is recommended.
Real-Time Monitor: The RTM output of the C E is available as one of the digital multiplexe r options. RTM data is read fro m the
CE DRAM locations specifi ed by I/O RAM registers RTM0, RTM1, RTM2, and RTM3 after the rise of MUX_SYNC. The RTM c an
be enabled and di sabled with I/O RAM regi ster RTM_EN. The RTM output is clocked by CKTEST. Each RTM word i s clocked
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out in 35 cycles and c ontains a leading flag bit. Figure 13 in th e S ys tem Timing S ectio n il lustrat es the R TM o utp ut f or mat. RTM
is low when not in use.
SSI I nt erface: A high -speed serial interface with handshake capabili ty is available to send a contiguous block of CE data to an
external data logger or DSP. The block of data, configurable as to location and size, is sent starting 1 cycl e of 32kHz before
each CE code pass begins. If the block of data is big enough that transmission has not compl eted when the code pass begi ns,
it will complete during the CE code pass with no timing impact to t he CE or the serial data. In this case, care must be taken
that the transmitted data is not modified unexpectedly by the CE. The SSI int erface is enabled by the SSI_EN bit and consists
of SCLK, SSDATA, and SFR as outputs and, optionally, SRDY as input. The interface is compatible with 16bit and 32bit
processors. The operation of each pin is as follows:
SCLK is the serial clock. The clock can be 5MHz or 10MHz, as specified by the SSI_10M bit. The SSI_CKGATE bit controls
whether SCLK runs c ontinuously or is gated off when no SSI activity is occurring. If SCLK is gat ed, it will begin 3 cycles before
SFR rises and will pers i st 3 c ycles after t he last data bi t is outp ut .
Th e pi ns us ed f or the SS I a re m ul ti plex ed wit h the LCD segm ent outputs, as shown in Table 58. Thus, the LCD should be
disabled when the SSI is in use.
SSI Signal LCD Segment
Output Pin
SCLK
SEG3
SSDATA SEG4
SFR SEG5
SRDY SEG6
Table 58: SSI Pin Assignm ent
SRDY is an optional handshake input that indicates that the DSP or data-logging device i s r eady t o r eceive dat a. SRDY must
be true (t he polarity of SRDY is selectable with SSI_FPOL) to enable SFR to ri se and initiate the tr ansfer of the next fi eld. It is
expect ed that SRDY changes state on the rising edges of SCLK. If SRDY is not true when the SSI port is ready to transmit the
next field, transm ission wi ll be delayed until it is. SRDY i s ignored exc ept at the begi nning of a field transmissi on. If SRDY is
not enabled ( by SSI_RDYEN), the SSI port will behave as i f SRDY is al ways true.
SSDATA is the serial output data. SSDATA changes on the rising edge of SCLK and outputs the cont ents of a block of CE
RAM words st arting with address SSI_STRT and ending with SSI_END. The words ar e output MS B f ir st.
Th e f i eld si ze i s s et wi t h t h e SSI_FSIZE register: 0 entire data block, 1-8 bit fi elds, 2-16 bit fields, 3-32 bi t fi el d s. Th e p o l ari t y of
the SFR pulse can be inverted with SSI_FPOL (SSI_FPOL = 0 SRDY high-active). If SRDY does not delay it, the first SFR
pulse in a frame will rise on the third SCLK after MUX_SYNC (or the fourth SCLK if 10MHz). MUX_SYNC can be used to
s ynchr onize t he fields arri ving at the data l ogger or DSP.
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FUNCT IONAL DESCRIPTION
Theory of Operation
The ener gy deliv ered by a power s our ce int o a load can be expressed as:
∫
=
tdttItVE
0
)()(
Assuming phase angles are constant , the follow ing for mulae apply:
P = Real E ner gy [Wh] = V * A * cos φ* t
Q = Reactiv e Energ y [V ARh] = V * A * sin φ * t
S = Appar ent Energy [VAh] =
22 QP +
For a practical meter, not only voltage and current amplitudes, but also phase angles and harmonic content may change
constantly. Thus, simple RMS m easurem ents ar e inherently inaccurate. A m odern solid-st at e elec tri cit y m eter I C such as th e
71M6513/6513H functions by emulating the integral operation above, i.e. it processes current and voltage sam ples through an
ADC at a constant frequenc y. As long as the ADC resolution is high enough and the sam ple frequency is beyond the harmonic
range of interest, the cur r ent and voltage sampl es, m ultiplied wit h the time period of sampli ng will yield an accur ate quant it y for
the momentar y ener gy. S um ming up the momentary ener gy quantities over time will res ult i n ac cum ulat ed energ y.
Figure 12: Voltage. Current, Momentary and Accum ulated Energy
Figure 12 sh o ws t h e s ha p es of V( t) , I ( t), t h e moment ar y en er g y an d t h e t ot al ac cumul a t ed ener g y , r es ul t in g f r om 5 0 s am p l es
of the voltage and current signals over a period of 20m s. The application of 240VAC and 100A results in an accumulation of
480Ws over the 20ms per iod, as indicated by the cur ve for Accumulated Energy.
The desc ribed s ampling method work s rel ia bly, ev en in th e pres ence o f d ynam ic phase s hif t an d har mo nic dist or tion.
-500
-400
-300
-200
-100
0
100
200
300
400
500
0 5 10 15 20
time [ms]
V [V], I [A], P [Ws]
Current [A]
V oltage [V]
Energy per Interval [Ws]
A ccumulated Energy [Ws]
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System Timing Summary
Figure 13 summarizes the timing relati onships bet ween the input MUX states, the CE_BUSY signal, and the two ser ial output
s t r eam s. I n th i s exa mpl e, MUX_DIV=0 ( six mu x st ates) and FIR_LEN = 0 ( 2 C K32 cy cles) . Since F IR filt er conversions req ui re
two or three CK32 cycles, the duration of each MUX cycle is 1 + 2 * states defined by MUX_DIV if FIR_LEN = 0, and 1 + 3 *
s tates defi ned by MUX_DIV if FIR_LEN = 1. Followed by the conversions is a single CK32 c ycle.
Each CE program pass begins when MUX_SYNC falls. Depending on the length of the CE program, it may continue runni ng
until the end of the ADC5 conversion. CE opcodes are constructed to ensure that all CE code passes consume exactly the
sam e num ber of cycles. The result of each ADC conversi on is i nsert ed into the CE DRAM when the conversion is complete.
The CE code is designed to tolerate sudden changes i n ADC data. The exact CK count when each ADC value is l oaded int o
DRAM is sh own in Figure 13.
Figure 13 also shows tha t the two se rial data stre ams, RTM and SS I, begin transmit ting at the be ginning of M U X_SY NC . R T M ,
consisting of 140 CK cycl es, will always finish before the next code pass starts. The SSI port begins transmitting at the sam e
tim e as RTM, but may significantly overrun the next code pass if a large block of data is requir ed. Neit her the CE nor the SSI
port will be affected by this overlap.
CK32
MUX STATE 0012345
MUX_DIV Convers i ons (MUX_DIV=6 is s hown) Settle
ADC MUX Frame
ADC EXECUTION
S
MUX_SYNC
S
CE_EXECUTION
RTM 140
SSI
MAX CK COUNT
BEGIN SSI TRANSFERLAST SSI TRANSFER
0300
150
600 900 1200 1500 1800
ADC0 ADC1 ADC2 ADC3 ADC4 ADC5
CK COUNT = CE_CYCLES + floor(CE_ CYCLES + 2) / 5)
NOTES: 1. ALL DIMENSIONS ARE 5MHZ CK COUNTS .
2. THE PRECISE FREQUENCY OF CK IS 150*CRYSTAL FREQUENCY = 4.9152MHz.
3. XFER_BUSY OCCURS ONCE EVERY (PRESAMPS * SUM_CYCLES) CODE PASSES.
CE_BUSY
XFER_BUSY INITIATED BY A CE OPCODE AT END OF SUM INTERVAL
ADC TIM ING
CE TIMING
RTM and S S I TIMING
Figure 13: Timing Rel ati onship between ADC MUX, CE, and Serial Transfer s
Figure 14, Figure 15, and Figure 16 show the RTM and SSI timing, respecti vely.
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CKTEST
TMUXOUT/RTM
FLAG
RTM DATA0 (32 bits)
LSB
SIGN
LSB
SIGN
RTM DATA1 (32 bits)
LSB
LSB
SIGN
SIGN
RTM DATA2 (32 bits)
RTM DATA3 (32 bits)
0 1 30 31 0 1 30 31 0 1 30 31 0 1 30 31
FLAG FLAG FLAG
MUX_SYNC
CK32
Figure 14: R TM Ou tp ut Format
SCLK (Output)
SSDATA (Output)
SFR (Output)
SRDY (Input)
31 30 16 15 1 0 31
SSI_BEG
30 16 15 1 0 31
SSI_BEG+1
1 0
SSI_END
If 16bit fields If 32bit fields
If SSI_CKGATE =1 If SSI_CKGATE =1
MUX_SYNC
Figure 15: S SI Timin g , (SSI_FPOL = SSI_RDYPOL = 0)
SC L K (Out put)
SSDATA (Output)
SF R (O utput)
SR D Y (Input)
31 30 16 15 14 13
16 16 16 12
29 18 17
Next field is del ayed while SRDY is low
Figure 16: S SI Timin g , 1 6-bit Fiel d Exam pl e (Exter nal Device Delays SRDY)
SFR is the f ram ing pulse. Although CE words are always 32 bits, the SSI i nterfac e will fram e the ent ir e data block as a single
f i el d, a s m ul tipl e 1 6 -b it f i el d s, or a s m ul t i pl e 3 2-bit f ields. The SFR pulse is one SCLK clock cycle wide, changes state on the
r ising edge of SCLK and prec edes th e fi rst bit of each field.
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Data Flo w
The data flow between CE and MPU is shown in Figure 17. In a typical application, the 32-bit compute engine (CE)
sequentially processes the samples from the voltage inputs on pins IA, VA, IB, VB, IC, and VC performing calculations to
m ea s ur e a c t iv e p ow er (Wh) , r ea c ti v e p o wer ( V AR h) , A 2h, a nd V 2h for four-quadrant m etering. These m easurem ents are then
accessed by the MPU, processed further and output usi ng the peripheral devices available to the MPU.
Figure 17: MPU/CE Data Flow
CE/M P U Communication
Figure 18 shows the functional relationship between CE and MPU. The CE i s controll ed by the MPU via shared registers in the
I/O RAM and by registers in the CE DRAM. The CE outputs two interrupt signals to the MPU: CE_BUSY and XFER_BUSY,
which are connected to the MPU interrupt service inputs as external interrupts. CE_BUSY indicates that the CE is actively
processing dat a. This signal will occur onc e ev ery mult i plexer cycle. XFER_BUSY indicates that the CE is updating data to the
output region of the CE RAM. Thi s will occur whenever the CE has finished generati ng a sum by c ompleting an accum ulation
interval determined by SUM_CYCLES * PRE_SAMPS samples. Interrupts to the MPU occur on the falling edges of the
XFER_BUSY and CE_BUSY signals.
Figure 19 shows the sequence of events between CE and MPU upon reset or power-up. In a typ ical application, the seque nce
of events is as follows:
1) Upon power-up, the MP U initi alizes t he hardware, including disabling the CE
2) The MPU loads t he code for the CE into the CE PRAM
3) The MPU loads CE data into the CE DRAM.
4) Th e M PU st arts the C E by setting t he CE_EN bit in t he I/O RAM .
5) Th e CE then repetitiv ely exec ut es it s code, genera ting result s and storing them in the CE DRAM
It is important to note that the length of the accumulation interval, as determined by NACC, the product of SUM_CYCLES and
PRE_SAMPS is not an exac t multiple of 1000ms . For exam ple, if SUM_CYCLES = 60, and PRE_SAMPS = 00 (4 2), the r esul ti ng
accumulation interval is:
ms
Hz
Hz
f
N
S
ACC
75.999
62.2520
2520
13
32768
4260 ==
⋅
==
τ
This means t hat ac cur ate time measur emen ts req uire th e RTC .
CE MPU
Pre-
Processor Post-
Processor
IRQ
Processed
Metering
Data
Pulses
I/O RAM (Configuration RAM )
Samples Data
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Figure 18: MPU/CE Com munication (Functional)
The MPU will wai t for th e CE to s ignal that fresh data is ready (t he XFER interrupt). It wi ll r ead the data and perf orm additional
processing suc h as energy accumulation.
Figure 19: MPU/CE Co m munication (Processing Sequence)
Fau lt, Reset, Power-Up
Reset Mod e: When the RESETZ pin is pulled low or whe n V1 < VBIAS, all digital activity in the chip stops while analog circuits
are still active. The oscillator and RTC m odule continue to run. Additionally, all I/O RAM bits are cl eared. As long as V1, the
input voltage at the power fault block, is greater t han VBIAS, the internal 2.5V regulator wi ll continue to provide power to the
digital secti on.
Once initiated, the reset mode will persist until the reset timer times out, signified by WAKE rising. This will occur in 4100
cycles of the real time clock after RESETZ goes high, at which time the MPU will begin executing its preboot and boot
s equences from addr ess 00. See the sec urity sectio n f or more d esc ript ion of preb oot and boot .
I/O RAM (CONFIGURATION RAM)
MPU
CE
PULSES
DATA
INTERRUPTS
DISPLAY (me-
mory-mapped
LCD segments)
DIO
EEPROM
(I2C)
SERIAL
(UART0/1)
SAMPLES
APULSEW
APULSER
VAR (DIO7) W (DIO6)
VARSUM
WSUM
ADC
EXT_PULSE
CE_BUSY
XFER_BUSY
Mux Ctrl.
CE_EN
CE PRAM
COMPUTATION
ENGINE
CE DRAM
FLASH
MPU
XFER Interrupt
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Power-Up: After p o wer -up, the 71M6513/6513H is in reset as long as V1 < VBI AS. As soon as V1 exceeds VBIAS, the reset
t im er i s star ted whic h takes th e MPU out of reset after 410 0 os cil lat or cy cl es ( see Figure 20) . Th e MPU th en i nit iates it s pr e-
boot phase lasting 32 cycles. The supply current will be low but not zero during power-up. It will increase, once V1 exceeds
VBIAS and will increase to the nominal value once the preboot phase starts. The supply current may then be reduced under
firm ware control, following the steps specified in Battery Operation and Power Save Modes .
Figure 20: Timing Di agr am for Voltages, Cur r ent and Operation Modes after Power-Up
Battery O peration
W hen V1 is lower than VBIAS, the external battery will power t he following parts of the 71M6513/6513H:
• RTC
• Cryst al o scillator cir c uit r y
• MPU XRAM
• WD_OVF bit Power Save Modes
In normal mode of operation, running on 3.3V supply, various resources of the 71M6513/6513H may be shut down by the
MPU firmware in order to reduce power consumption while other essential resources such as UARTs may remain active.
Table 59 o utl in es these res ources and t heir typical c urrent consumptio n (b ased on i nit ial condition MPU_DIV = 0) .
Power Saving Measur e Software Control
Typical
Savings
Disable the C E CE_EN = 0 0.16mA
Disable the ADC ADC_DIS = 1 1.8mA
Disable c lock test out put CKT EST CKOUTDIS = 1 0.6mA
Disable emulator clock ECK_DIS = 1 *) 0.1mA
Set flash rea d pulse t im i ng to 33 ns
FLASH66Z
=1 0.04mA
Disable the LCD v oltag e boost c i rcui t ry
LCD_BSTEN
= 0 0.9mA
Disable RTM o utput s RTM_EN = 0 0.01mA
Incr ease t he c lock divid er for the M PU MPU_DIV = X 0.4mA/MHz
*) This bit is to be used with caution! Inadvertently setting this bit will inhibit access to the part with the ICE interface and thus
preclude flash erase and programming oper ati ons.
Table 59: Power Savi ng M easures
V3P3
V1
SUPPLY CURRENT
3.3V
1.5V
PRE-
BOOT
RESET TI MER FIRMWARE HAS CONTROL OVER CHIP ...
1ms
0V
V2P5
POWER
DOWN
V1 > VBIAS
PWR
UP
0mA
nominal
125ms
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Tem perature Com pensation
Int ernal Compensation: The internal voltage reference is cali brated duri ng device m anufacture. Trim data is stored in on-chip
fuses.
For the 71M6513, the temperature coefficients TC1 and TC2 are given as constants that represent typical component
behavior.
For the 71M6513H, the temperature characteristics of the chip are measured during production and then stored in the fuse
registers TRIMBGA, TRIMBGB and TRIMM[2:0]. TC1 and TC2 can be deri ved from the f us es by using the relations given in the
Elect r ical Specif ications s ectio n. T C 1 and TC2 can be f urther pro ces sed to g enerate the coef fi cients PPMC and PPMC2.
TRIMM[2:0], TRIMBGA and TRIMBGB are read by first writing either 4, 5 or 6 t o TRIMSEL ( 0x20FD) and then reading the value
of TRIM (0x20FF).
When the EXT_TEMP register in CE DRAM (address 0x38) is set to 0, the CE automatically compensates for temperature
errors by controlling the GAIN_ADJ register (address 0x2E) based on the PPMC, PPMC2, and TEMP_X r egi st er v alu es. In th e
case of internal compensati on, GAIN_ADJ is an output of the CE.
External Compensation: Rather than internally compensating for the temperature variation, the bandgap temperature is
provided to the embedded MPU, which then may digitally compensate the power outputs. This permits a system-wide
temperat ure correction over t he enti re system rather than local to the chip. The incorporated thermal coefficients may include
the current sensors , the voltage se nsors, and other influence s. Since the band gap is chopper stabilize d via the CHOP_EN bits,
the mos t signi fi cant l ong-term drift mechanism in the voltage reference is re moved.
W hen the EXT_TEMP regi ster i n CE DRA M is set t o 1 5, t he CE ig nor es t he PPMC, PPMC2, and TEMP_X register values and
applies the gain supplied by the MPU in GAIN_ADJ. E xt er n al comp en s at i on en a b l es t h e MPU t o c ont r o l th e C E g ai n ba sed o n
any variable, and when EXT_TEMP = 15, GAIN_ADJ is an in put to th e C E.
Chopping Circuitry
As explained in the hardware section, the bits of the I/O RAM register CHOP_EN[1:0] have to be toggled in between
m ult iplex er cycles t o achieve t he desired eli minati on of DC off set.
Th e amp l if i er wi t hin t h e r ef er en c e i s aut o -zeroed by m eans of an internal si gnal that is controlled by t he CHOP_EN bits. W h en
t his si gnal is HIG H, t he c on nec tion o f t he am pli fi er i np uts i s rev ers ed. Th is pr eser ves th e ov era ll pol arity of t he am pli fi er gain
but i nver ts t he input offset. By alt ern ately rev ersi ng t he c onnectio n, the of fset of the amplifier is averaged to zero. The two bit s
of the CHOP_EN r egister hav e the f unction speci fied in Table 60.
CHOP_EN
[1]
CHOP_EN
[0]
Function
0 0 Toggle c hop signal
0 1 Reference connection positive
1 0 Ref eren ce connec tio n rev ers ed
1 1 Toggle c hop signal
Table 60: CHOP_EN Bits
For automatic chopping, the CHOP_EN bits are set to either 00 or 11. In this mode, the polarity of the signals feeding the
reference amplifier will be automatically toggled for each multiplexer cycle as shown in Figure 21. With an even num ber of
m ult iplex er cycles i n eac h accumulatio n interval, the numb er of cy cles with positive r eference c onnectio n will equal t he n umber
of cycles with reversed connection, and the offset for each sampled signal will be averaged to zero. This sequence is
acceptable when only t he primary signals (meter voltage, meter c urrent) are of interest.
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3-Phase Energy Meter IC
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Figure 21: Chop Pol arity w/ Automatic Chopping
If tem perature compensation or accurate reading of the die temperature is required, alt ernate multiplexer cycles have to be
inserted in between the regular cycles. This is done under MPU firmware control by asserting the MUX_ALT bit whenever
necessary. Since die temperature usually changes very slowly, alternate multiplexer cycles have to be inserted very
infrequently. Usually, an alternate multiplexer cycle is inserted once for every accumulation period, i.e. after each
XFER _BU SY inter rup t . T his sequence is sho w n i n Figure 22.
Figure 22: Sequence with Alternate Multi plexer Cycl es
This sequence has the disadvantage that the alternate multiplexer cycle is always operated with positive connection.
Consequently, DC of fset wil l appear on the t em perature measurem ent, which will decrease the accuracy of this measurem ent
and thus cause temper atur e reading and compensation t o be less accurate.
The sequence shown in Figure 23 uses t he CHOP_EN bits to control the chopper polarity after each XFER_BUSY interrupt.
CHOP_EN is controlled to alternate between 10 (positive) and 01 (reversed) for the first multiplexer cycle following each
Accumulation Interval m
MUX
cycle n
MUX
cycle 2 MUX
cycle 3
Chop Polarity
Positive Positive Positive Positive
Re-
versed Re-
versed Re-
versed Re-
versed
MUX
cycle n
MUX
cycle 1 MUX
cycle 1 MUX
cycle 1
Accumulation Interval m+1
CE_BUSY interrupt
(falling edge)
XFER_BUSY interrupt
(falling edge)
Accumulation Interval m+2
Positive Positive
Re-
versed
Accumulation Interval m
MUX
cycle n
MUX
cycle 2 MUX
cycle 3
Chop Polar it y
Positive Positive Positive Positive
Re-
versed Re-
versed Re-
versed Re-
versed
MUX
cycle n
Accumulation Interval m+1
alt. M UX
cycle alt. MUX
cycle alt. MUX
cycle
CE_BUSY interrupt
XFER_BUSY interrupt
Accumulation Interval m+2
Positive Positive
Re-
versed
MUX_ALT
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XFER_BUSY interrupt. After these first two cycles, CHOP_EN returns t o 11 (automatic toggle). The v alue of CHOP_EN, when
set after the XFER_BUSY interrupt, is in force for the entire following multiplexer cycle.
When using this sequence, the alternate multiplexer cycle is toggled between positive and reversed connection resulting in
accurate temperature measurement.
An example for proper application of the CHOP_EN bits can be found in the Demo Code shipped with the 6513 Demo Kits.
Fir mware implementations should closely f oll ow this example.
Figure 23: Sequence with Alternate Multiplexer Cyc l es and Controlled Choppi ng
Internal/External Pulse Generation and Pulse Counting
The CE is the source for pulses. It can generate pulses directly based on the voltage and current inputs and the configured
pulse generation parameters. This is called “internal pulse generation”, and applies when the CE RAM register EXT_PULSE
(address 0x37) equals 0. Alternatively, t he CE can be configured to gener ate pulses based on r egisters that are controlled by
the MPU (“external pul se generation”), i.e. when the regist er EXT_PULSE equals 15. In t he case of external pulse gen erati on,
the M P U writes values to the CE reg isters APULSEW (0x26) and APULSER (0x27).
The pulse rate, usually inversely expr ess ed as “Kh” ( and m easur ed i n W h per pulse), is determined by the CE RAM regi sters
WRATE, PULSE_SLOW, PULSE_FAST, In_8, as well as by the sensor sca l ing VMAX and IMAX per the equation:
]/[
8_ 1782.66 pulseWh
XNWRATEIn IMAXVMAX
Kh
ACC ⋅⋅⋅
⋅⋅
=
where
In_8 is t he gain factor ( 1 or 8) controlled by the CE variable In_SHUNT,
X is t he pulse gain f actor controlled by the CE variables PULSE_SLOW and PULSE_FAST
NACC is the accumu lation count (PRE_SAMPS * SUM_CYCLES)
alt. MUX
cycle alt. MUX
cycle alt. MUX
cycle
Accum ulation Interval m Accumul ation Interval m+1
Positive Positive
Positive Positive Positive
Accum ulation Interval m+2
Positive Positive
re-
versed re-
versed re-
versed re-
versed re-
versed
MUX
cycle 2 MUX
cycle 2 MUX
cycle 2
MUX
cycle 3 MUX
cycle 3 MUX
cycle 3
MUX
cycle n MUX
cycle n MUX
cycle n
Chop Polarity
01 11 01 11(11) (11) (11) (11)(11) (11)(11) 10 11 (11)
CHOP_EN
(11)
CE_BUSY interrupt
XFER_BUSY interrupt
MUX_ALT
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Program Security
When enabl ed, the securi ty feature limits the I CE to global flash erase operations only. All other ICE operations are blocked.
This guarantees the security of t he user’s MPU and CE pr ogram code. Security is enabl ed by MPU co d e t hat is ex ec ut ed i n a
32 cycle preboot interval before the primary boot sequence begins. Once security is enabled, the only way to disabl e it is to
perform a global er as e of the flash memory, followed by a chip reset. Global flash erase also clears the CE PRAM.
The fi r st 32 cycl es of t he MPU boot code are call ed the preboot phase becaus e during t his phase the ICE is inhibited. A r ead-
only st atus bit, PREBOOT (SFR 0xB2[7]), identifies these cycles to the MPU. Upon completion of the preboot sequence, the
ICE can be enabled and i s permitted to take control of the MPU.
SECURE (SFR 0xB2[6]), the secur ity enable bit, is reset whenever t he MPU is r eset. Hardware ass ociat ed with the bit permits
only ones to be written to it. Thus, preboot code may set SECURE to enable the security f eature but may not reset it. Once
SECURE is set , the preboot code i s protected and no ext ernal read of program code is possible.
Specifically, when SECURE is set:
• Th e IC E is l im i ted to bul k f lash era se only.
• Page zero of flash m emory, the pref erred location for the user’s pr eboot code, may not be page-erased by either MPU or
ICE. Page zero may only be e rase d with globa l flash erase . Note that global flash e rase erases C E program RA M whether
SECURE i s set or no t.
• Writes t o page zero, whether by MPU or ICE, ar e inhibited.
The SECURE bit is to be used with caution! Inadvertently setting this bit will inhibit access to the part via the ICE
interface, if no mechanism for actively resetting the part between reset and erase operations is provided (see ICE
Int erface description).
Additionally, by se tting the I/O RAM re gister ECK_DIS to 1, the emulator clock is disabled, inhibiting access to the program with
the emu lator . See the cautionary note in the I/O RAM Register descr i ption!
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FIRMWARE INTERFACE
I/O RAM MAP – In Numerical Order
‘Not Used’ bits are blacked out and contain no memory and are read by the MPU as zero. RESERVED bits are in use and
should not be changed.
Name Addr
Bi t 7 Bit 6 Bit 5 Bi t 4 Bit 3 Bit 2 Bi t 1 Bi t 0
Configuration:
CE0
2000
EQU[2:0]
CE_EN
TMUX[3:0]
CE1
2001
PRE_SAMPS[1:0]
SUM_CYCLES[5:0]
CE2
2002
MUX_DIV[1:0]
CHOP_EN[1:0]
RTM_EN
WD_OVF
EX_RTC
EX_XFR
COMP0
2003
COMP_INT[1:0]
COMP_STAT[2:0]
CONFIG0
2004
VREF_CAL
RESERVED
CKOUT_DIS
VREF_DIS
MPU_DIV
CONFIG1
2005
RESERVED
ECK_DIS
FIR_LEN
ADC_DIS
MUX_ALT
FLASH66Z
MUX_E
VERSION
2006
VERSION[7:0]
Dig ital I/O:
DIO0
2008
OPT_TXDIS
DIO_EEX
DIO_PW
DIO_PV
DIO1
2009
DIO_R1[2:0]
DIO_R0[2:0]
DIO2
200A
DIO_R3[2:0]
DIO_R2[2:0]
DIO3
200B
DIO_R5[2:0]
DIO_R4[2:0]
DIO4
200C
DIO_R7[2:0]
DIO_R6[2:0]
DIO5
200D
DIO_R9[2:0]
DIO_R8[2:0]
DIO6
200E
DIO_R11[2:0]
DIO_R10[2:0]
Real Tim e Clock:
RTC0
2015
RTC_SEC[5:0]
RTC1
2016
RTC_MIN[5:0]
RTC2
2017
RTC_HR[4:0]
RTC3
2018
RTC_DAY[2:0]
RTC4
2019
RTC_DATE[4:0]
RTC5
201A
RTC_MO[3:0]
RTC6
201B
RTC_YR[7:0]
RTC7
201C
RTC_DEC_SEC
RTC_INC_SEC
LC D D ispl ay Inter face:
LCDX
2020
LCD_BSTEN
LCD_NUM[4:0]
LCDY
2021
LCD_EN
LCD_MODE[2:0]
LCD_CLK[1:0]
LCDZ
2022
LCD_FS[4:0]
LCD0
2030
LCD_SEG0[3:0]
LCD1
2031
LCD_SEG1[3:0]
LCD2
2032
LCD_SEG2[3:0]
LCD3
2033
LCD_SEG3[3:0]
…
…
…
…
LCD39
2057
LCD_SEG39[3:0]
LCD40
2058
LCD_SEG40[3:0]
LCD41
2059
LCD_SEG41[3:0]
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Name Addr
Bi t 7 Bit 6 Bit 5 Bi t 4 Bit 3 Bit 2 Bi t 1 Bi t 0
RTM Pr obes:
RTM0
2060
RTM0[7:0]
RTM1
2061
RTM1[7:0]
RTM2
2062
RTM2[7:0]
RTM3
2063
RTM3[7:0]
Synchronous Serial Inter face:
SSI
2070
SSI_EN
SSI_10M
SSI_CKGATE
SSI_FSIZE[1:0]
SSI_FPOL
SSI_RDYEN
SSI_RDYPOL
SSI_BEG
2071
SSI_BEG[7:0]
SSI_END
2072
SSI_END[7:0]
Fuse Sel ection Regi sters:
TRIMSEL
20FD
TRIMSEL[7:0]
TRIM
20FF
TRIM[7:0]
SFR MAP (SFRs Specific to T eridian 80515) – In Numerical Order
‘Not Used’ bits are blacked out and contain no memory and are read by the MPU as zero. RESERVED bits are in use and
should not be changed. Thi s table lists onl y the SFR registers that ar e not generi c 8051 SFR registers.
Name
SFR
Addr
Bi t 7 Bit 6 Bit 5 Bi t 4 Bit 3 Bit 2 Bi t 1 Bi t 0
Digital I/O:
P0
80
DIO_0[7:0] (Port 0)
DIR0
A2
DIO_DIR0[7:0]
P1
90
DIO_1[7:0] (Port 1)
DIR1
91
DIO_DIR1[7:0]
P2
A0
DIO_2[5:0] (Port 2)
DIR2
A1
DIO_DIR2[5:0]
Int errupts and WD Timer:
INTBITS
F8
INT6
INT5
INT4
INT3
INT2
INT1
INT0
WDI
E8
WD_RST
IE_RTC
IE_XFER
Flash:
ERASE
94
FLSH_ERASE[7:0]
FLSHCTL
B2
PREBOOT
SECURE
FLSH_MEEN
FLSH_PWE
PGADR
B7
FLSH_PGADR[6:0]
Serial EEPROM:
EEDATA
9E
EEDATA[7:0]
EECTRL
9F
EECTRL[7:0]
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I/O RAM (Configuration RAM) – Alphabetical Order
Many functions of the chip can be controlled via the I/O RAM (Configuration RAM). The CE will also take some of its para-
meters from the I/O RAM.
Bits with a W (write) direction are written by the MPU into I/O RAM. Typically, they are initially stored in flash memory and
copied to the I/O RAM by the MPU. Some of the more frequently programmed bits are mapped to the MPU SFR memory
space. Th e rem ai ni ng bits are mapped to 2xxx. Bits with R (r ead) direction can only be read by the MPU. On power up, all
bits are cleared to zero unless otherwise st ated. Generic SFR registers are not listed.
Name Location
[Bit(s)] Dir Description
ADC_DIS 2005[3] R/W Disables ADC and r emoves bi as c urrent
CE_EN 2000[4] R/W CE enabl e.
CHOP_EN[1:0] 2002[5:4] R/W Chop enable f or the r eference band gap circuit.
00: enabled 01: disabl ed 10: disabled 11: enabled
RESERVED
2004[5]
R/W
Must b e 0.
CKOUT_DIS
2004[4] R/W CKOUT Di sable. When zero, CKTEST i s an active out put.
COMP_INT[1:0]
2003[4:3] R/W Tw o bit s establ ishi ng whet her a c omp ara tor s tate c hange should cr eat e
MP U i nterr upt s . 1: int errupt, 0: no int errupt. If 1 1, the comp ar ator out put s ar e
XOR’ed.
Bi t0 = com p2, Bit1 = comp 3
COMP_STAT[2:0] 2003[2:0] R Three bit s containing com parator output status.
Bit0 = c omp 1, Bit1 = com p2, B it 2 = com p3
DIO_R0[2:0]
DIO_R1[2:0]
DIO_R2[2:0]
DIO_R3[2:0]
DIO_R4[2:0]
DIO_R5[2:0]
DIO_R6[2:0]
DIO_R7[2:0]
DIO_R8[2:0]
DIO_R9[2:0]
DIO_R10[2:0]
DIO_R11[2:0]
2009[2:0]
2009[6:4]
200A[2:0]
200A[6:4]
200B[2:0]
200B[6:4]
200C[2:0]
200C[6:4]
200D[2:0]
200D[6:4]
200E[2:0]
200E[6:4]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Connects dedicated I/O pins 0 to 11 to selec t able internal resources. If more
than one input is connect ed to the same resource, the ‘Multiple’ column
below specifies how t hey are c omb ined. See So ftware User’s Guid e f or
details).
DIO_GP Resource Multiple
0
NONE
--
1
Reserved
OR
2
T0 (count er0 clock)
OR
3
T1 (count er1 clock)
OR
4
High priority I/O interrupt (int0 rising)
OR
5
Low priority I/O interrupt (int1 rising)
OR
6
High priority I/O interrupt (int0 falling)
OR
7
Low priority I/O interrupt (int1 falli ng)
OR
DIO_DIR0[7:0]
SFR A2 R/W
Programs t he direction of DIO pins 7 through 0. 1 indicates out put. Ignored if
the pin i s not confi gured as I/O. See DIO_PV and DIO_PW for special option
for D I O6 a nd DI O7 o utput s. S ee DIO_EEX for special opti on for DIO4 and
DIO5.
DIO_DIR1[7:0] SF R 9 1 R/W Progra ms the direction of DIO pins 15 through 8. 1 indicates output. Ignored
if the pin is not confi gur ed as I/O.
DIO_DIR2[5:0] SFR
A1[5:0] R/W Programs t he direction of DIO pins 21 through 16. 1 indicates output.
Ignored if the pin is not configured as I/O.
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Name Location
[Bit(s)] Dir Description
DIO_0[7:0]
DIO_1[7:0]
DIO_2[5:0]
SFR 80
SFR 90
SFR
A0[5:0]
R/W
R/W
R/W
Port 0
Port 1
Port 2
The value on the DIO pins. Pins configured
as LCD will read zer o. When wri tten,
changes dat a on pins configured as out-
puts. Pins configured as LCD or input will
ignor e w ri tes .
DIO_EEX 2008[4] R/W When set , co nver ts D I O4 a nd DI O5 to int erface wi th external EEP RO M .
DIO4 becomes S CK a nd DI O 5 becomes bi-direct ional SDA . LCD_NUM
must be less than 18 .
DIO_PV
2008[2] R/W Causes VARPULSE to be output on DIO7, if DIO7 is configured as output.
LCD_NUM must b e less t han 15.
DIO_PW 2008[3] R/W Causes WPULSE to be output on DIO6, if DIO6 is configur ed as output.
LCD_NUM must b e less t han 16.
EEDATA[7:0]
SFR 9E
R/W
Serial EEPROM interface data
EECTRL[7:0]
SFR 9F R/W Ser ia l EE P RO M inter f ace control
ECK_DIS 2005[5] R/W Emula tor clock disable. When one, the emulato r clock is disabl ed. This bit
is to be used wi t h caution! I nadvertently setting this bit will
inhibit access to the part with the ICE interface and thus
preclude flash erase and programming oper a tions. If ECK_DIS
is set, it should be done at least 1000ms after power-up t o give emulators
and programming devices enough time to complete an erase operation.
EQU[2:0] 2000[7:5] R/W Specifie s the power equation to the CE.
EX_XFR
EX_RTC 2002[0]
2002[1] R/W Interrupt enabl e bits. These bits enable the XFER_BUSY and the
RTC_1SE C interrupts to the MPU. Note that if either interrupt is to be
enabled, EX6 in the 80515 must also be set.
FIR_LEN 2005[4] R/W The length of the ADC decimation FI R filter.
1: 22 ADC bits/3 CK32 cy cles (384 CKFI R cycles),
0: 21 ADC bits/2 CK32 cy cles (288 CKFI R cycles)
FLASH66Z
2005[1]
R/W
Should be set t o 1 to m ini mize s upply cur rent .
FLSH_ERASE
SFR 94 W Flash Era se I nit iate
FLSH_ERASE is u sed to i nitiat e ei ther t he Flas h Mass Era se cycle or t he
Flash Page Erase cycl e. Speci fi c patterns are expec t ed for FLSH_ERASE in
order to i nit iate t he appropriat e Era se cycle.
(default = 0x00).
0x55 – Ini t iat e Fla sh Page Era se c ycle. M ust b e pr oceeded by a writ e t o
FLSH_PGADR @ SF R 0xB7.
0xAA – Initiat e Flash M ass E rase cycle. M ust be proceeded by a write to
FLSH_MEEN @ SFR 0xB2 and the debug (CC) por t must be
enabled.
Any other pattern w r it ten to FLSH_ERASE will have no effec t .
FLSH_MEEN
SFR B2[1]
W
Mass Er ase Enable
0 – M ass Erase disabled ( def ault ) .
1 – Mass Eras e enabled.
Must be r e-written f or each new Mass Erase cycle.
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Name Location
[Bit(s)] Dir Description
FLSH_PGADR SFR
B7[7:1] W Flash Page Erase Address
FLSH_PGADR[6:0] –
Flash Page Address (page 0 thru 127) that will be
erased dur ing the Page Erase cy cle. (default = 0x00).
Must be r e-written f or each new Page Erase cycle.
FLSH_PWE SFR B2[0] R/W Progra m Wri te Enab le
0 – MOVX commands refer to XRAM Space, normal oper ati on (default).
1 – MOVX @DPTR,A moves A to Program Space (Flash) @ DPTR.
This bit i s automatically reset after each byte written to flash. Writes to this
bit are inhibited w hen int errupts a re en abled.
IE_XFER
IE_RTC SFR E8[0]
SFR E8[1] R/W I nt errupt flags. These f lags ar e part of the WDI SFR re gister and monitor the
XFER_BUSY interrupt and the RTC_1SEC inter
rupt. The flags are set by
hardware and must be cl eared by the interrupt h andler. S ee al so WD_RST.
INTBITS SFR
F8[6:0] R Interrupt
inputs. The MPU may read these bits to see the input to external
interrupts INT0, INT1, up to INT6. These bits do not have any m em ory and
are primarily intended f or debug use.
LCD_BSTEN
2020[7]
R/W
Enables t he LCD voltage boost cir cuit.
LCD_CLK[1:0]
2021[1:0] R/W
Sets the LCD clock frequency for COM/SEG pins (not the fram e rate. Note:
fw = CKFIR/128
00: fw/29, 01: fw/28, 10: fw/27, 11: fw/26
LCD_EN
2021[5] R/W
Enables the LCD display. When disabled, VLC2, VLC1, and VLC0 are
ground as ar e the COM and SEG outputs.
LCD_FS[4:0] 2022[4:0] R/W Controls the LCD full scale vol tage, VLC2:
)
31
_
3.07.0(
2FSLCD
VLCDVLC +⋅=
LCD_MODE[2:0] 2021[4:2] R/W The LCD bias mode.
000: 4 states, 1/3 bias
001: 3 states, 1/3 bias
010: 2 states, ½ bias
011: 3 states, ½ bias
100: static display
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DATA SHEET
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A Maxim Integrated Products Brand
Name Location
[Bit(s)] Dir Description
LCD_NUM[4:0] 2020[4:0] R/W Number of dual-
purpose LCD/DIO pins to be configured as LCD. This
number can be bet ween 0 and 18. The first dual-purpose pi n to be us ed as
LCD is SEG41/DIO21. If LCD_NUM
= 2, SEG41 and SEG 40 will be
configured
as LCD. The remaining SEG39 to SEG24 will be configured as
DIO19 to DIO4.
LCD_NUM
SEG
DIO
0
None
DIO4-21
1
SEG41
DIO4-20
2
SEG40-41
DIO4-19
3
SEG39-41
DIO4-18
4
SEG38-41
DIO4-17
5
SEG37-41
DIO4-16
6
SEG36-41
DIO4-15
7
SEG35-41
DIO4-14
8
SEG34-41
DIO4-13
9
SEG33-41
DIO4-12
10
SEG32-41
DIO4-11
11
SEG31-41
DIO4-10
12
SEG30-41
DIO4-9
13
SEG29-41
DIO4-8
14
SEG28-41
DIO4-7
15
SEG27-41
DIO4-6
16
SEG26-41
DIO4-5
17
SEG25-41
DIO4
18
SEG24-41
None
LCD_SEG0[3:0]
…
LCD_SEG41[3:0]
2030[3:0]
…
2059[3:0]
R/W LCD Segmen t Data . Ea c h word contai ns inf ormatio n for fr om 1 to 4 time
divisions of ea ch s egment. In ea ch w ord, bit 0 c orrespo nds t o CO M 0, on up
to bit 3 for COM3.
MPU_DIV[2:0] 2004[2:0] R/W The M PU cl ock divid er ( from CK CE). T hes e bits may be pr ogr ammed by
the MPU without risk of losing control.
000 - CKCE, 001 - CKCE/2, …, 111 - CKCE/27
MPU_DIV is 000 on power-up.
MUX_ALT 2005[2] R/W The MPU asserts t his bit when it wi s hes the MUX to perform ADC
conversions on an alternate set of input s.
MUX_DIV[1:0] 2002[7:6] R/W The number of states in the input multiplexer.
00 - 6 states 01 - 4 st ates 10 - 3 states 11 - 2 states
MUX_E
2005[0]
R/W
MUX_SYNC enabl e. When hi gh, converts SEG7 i nto a MUX_SYNC output.
OPT_TXDIS
2008[5] R/W Tristates the OPT_TX output.
PREBOOT
SFR B2[7] R In dicat es that th e preb oot sequence is act ive.
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
SEPTEMBER 2011
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Name Location
[Bit(s)] Dir Description
PRE_SAMPS[1:0] 2001[7:6] R/W Together w/ SUM_CYCLES, this value det er mines the numb er of s amp les in
one s um c ycle betw een XF ER inter ru pts for the C E.
Number of sam ples = PRE_SAMPS*SUM_CYCLES.
00-42, 01-50, 10-84, 11-100
RTC_SEC[5:0]
RTC_MINI[5:0]
RTC_HR[4:0]
RTC_DAY[2:0]
RTC_DATE[4:0]
RTC_MO[3:0]
RTC_YR[7:0]
2015
2016
2017
2018
2019
201A
201B
R/W
The RTC interface. These are the ‘year’, ‘m onth’, ‘day’, ‘hour’, ‘minute’ and
‘second’ parameters for the RTC. The RTC is set by writing to these
registers. Year 00 is defined as a leap year.
SEC 00 to 59
MIN 00 to 59
HR 00 to 23 (00=Midnight)
DAY 01 to 07 (01=Sunday)
DATE 01 to 31
MO 01 to 12
YR 00 to 256
RTC_DEC_SEC
RTC_INC_SEC
201C[1]
201C[0]
W
RTC time correction bits. Only one bit may be pulsed at a time. When
pulsed, causes the RTC tim e value to be increm ented (or decrem ented) by
an additional second the next time the RTC_SEC
register is clocked. The
pulse width may be any value. If an additional correction is desired, the
MPU must wait 2 seconds before pulsing one of the bi ts again.
RTM_EN 2002[3] R/W
Real Time Monitor enable. When ‘0’, the RTM output is low. This bit
enables the two wire version of RTM
RTM0[7:0]
RTM1[7:0]
RTM2[7:0]
RTM3[7:0]
2060
2061
2062
2063
R/W Four RTM probes. Bef or e each CE code pass, the values of these registers
are serially output on the RTM pin. The RTM registers are ignored when
RTM_EN=0.
SECURE
SFR B2[6] R/W
Enables security provisions that prevent external reading of flash memory
and CE
program RAM. This bit is reset on chip reset and may only be set.
Attempts to wr i te zero are i gnored .
SSI_EN
2070[7]
R/W
Enables the Synchronous Serial Interface (SSI) on SEG3, SEG4, and
SE G 5 p ins. If SSI_RDYEN
is set, SEG6 i s enabled also. The pi ns take on t he
new functions SCLK, SSDATA, SFR, and SRDY, respectively. When
SSI_EN is high and LCD_EN
is low, these pins are converted to the SSI
function, regardless of LCDEN and LCD_NUM. For proper LCD operation,
SSI_EN must not be high when LCD_EN is high.
SSI_10M 2070[6] R/W SSI clock speed: 0: 5MHz, 1: 10MHz
SSI_CKGATE
2070[5]
R/W
SSI gated clock enable. When low, the SCLK is continuous. When high, the
clock is held low when data is not being tr ansferred.
SSI_FSIZE[1:0] 2070[4:3] R/W SSI frame pulse fo r mat:
0: once at beginning of SSI sequence (whole block of data),
1: ever y 8 bits , 2: ever y 16 bits, 3: ev ery 32 bits.
SSI_FPOL 2070[2] R/W SFR p ulse pola r it y: 0: posit ive, 1: negative
SSI_RDYEN 2070[1] R/W SRDY enable. If SSI_RDYEN and SSI_EN are high, the SEG6 pin is
configured as SRDY. Otherwise, it is an LCD driver.
SSI_RDYPOL 2070[0] R/W SRDY polarity: 0: positive, 1: negative
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
AUGUST 2011
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A Maxim Integrated Products Brand
Name Location
[Bit(s)] Dir Description
SSI_BEG[7:0]
SSI_END[7:0] 2071[7:0]
2072[7:0] R/W
The beginning and ending address of the transfer region of the CE data
memory. If the SSI is enabled, a block of words starting with SSI_BEG and
ending with SSI_END will be sent. SSI_END must be larger than SSI_BEG.
The maximum number of output words is limited by the number of SSI
clocks i n a CE code pass—see FIR_LEN, MUX_DIV, and SSI_10M.
SUM_CYCLES
[5:0] 2001[5:0] R/W Together w/ PRE_SAMPS, th is val ue d etermines (for the CE) th e numb er of
s amples in one sum cy c le b etw een XFE R in terr upt s .
Number of sam ples = PRE_SAMPS*SUM_CYCLES.
TMUX[3:0] 2000[3:0] R/W Selects one of 1 6 input s for TM UXO U T.
0 – DGND ( analog)
1 – IBIAS (ana log )
2 – PLL_2 .5V (ana log)
3 – VBIAS ( analog)
4 – RTM (Real time ou tpu t fr om CE)
5 – WDTR_EN (Comparator 1 O utput A ND V1LT3)
6 – V2_OK (Comparator 2 Output)
7 – V3_OK (Comparator 3 Output)
8 – RXD ( fro m Optical in ter fa ce)
9 – MUX_SYNC (fro m MUX_CTRL)
A – CK_10M
B – CK_MPU
C – reser ved for product ion test
D – RTCLK
E – CE_BUSY
F – XFER_BUSY
RESERVED 2005[7] R/W Must be zero.
TRIMSEL
20FD
W
Select s t he temp era ture trim fuse to b e rea d wi th the TRIM register
(TRIMM[2:0]: 4, TRIMBGA: 5, TRIMBGB: 6)
TRIM 20FF R Contains TRIMBGA, TRIMBGB, or TRIMM[2:0] depending on the value
writte n to TRIMSEL. If TRIMBGB = 0 then t he IC i s a 651 3 else the IC is a
6513H.
VERSION[7:0] 2006 R The sil i con rev i sion num ber. This data sheet does not appl y to revisions <
000 0100.
VREF_CAL 2004[7] R/W B rings VREF o ut to th e VRE F pin . This feature is di sa bled when
VREF_DIS=1.
VREF_DIS 2004[3] R/W Di sa bles the inter nal vol tage refer ence.
WD_RST SFR E8[7] W Reset s the WD ti mer. The WDT is r eset when a 1 i s wr i tten t o this bit. Onl y
byte oper ati ons on the whol e W DI register should be used.
WD_OVF 2002[2] R/W The WD ove r flow st atus bi t. Thi s bit i s set wh en the WD ti mer o verflows. It
is power ed by the VBAT pin and at boot-up will indicate if the part is
r eco ver ing from a WD overflow or a power faul t. T his b i t should be cleared
by the MPU on boot-up. I t i s also automat ically cleared when RESETZ is
low.
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
SEPTEMBER 2011
© 2005-2011 Teridian Semiconductor Corporation Page: 67 of 104
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CE Program and Environment
CE Program
The CE program is supplied by Teridian as a data image that can be merged with the MPU operational code for meter
applications . Typically, the CE progra m cove rs most applica tions and does not need to be modified.
Formats
All CE words are 4 bytes. Unless specified otherwise, they are in 32-bit two’s com plement (-1 = 0xFFFFFFFF). ‘Calibration’
parameters are defined in flash memory (or external EEPROM) and must be copied to CE memory by the MPU before
enabling the CE. ‘Internal’ variables are used in internal CE calculations. ‘Input’ variables allow the MPU to control the
behavior of the CE code. ‘Output’ variables are outputs of the CE calculations. The corr esponding MPU address for the most
signif i cant byte is gi ven by 0x1000 + 4 x CE_address and 0x1003 + 4 x CE_addr ess for the least significant byte.
Constants
Constants used i n the CE Data Memory t ables are:
Sampling freque ncy: FS = 32768Hz/13 = 2520.62Hz.
F0 is t he fundamental signal fr equency, typi cally 50 or 60 H z.
IMAX is the ex te rnal rms c ur re nt corresponding to 250 mV peak at the inputs IA, IB, IC .
VMAX is the external rms v oltage corresponding to 250mV peak at the input s VA, VB, VC.
NACC, the accumulation count for energy measurements is PRE_SAMPS*SUM_CYCLES. This value resides in
SUM_PRE (CE addres s 36).
Accumulation count time for energy measurements is PRE_SAMPS*SUM_CYCLES/FS.
In_8 is a gai n constant of c urrent channel n. Its val ue is 8 or 1 and is controlled by In_SHUNT.
X is a g ain const ant of t he puls e generat ors . I ts value i s d eterm ined by PULSE_FAST and PULSE_SLOW.
Voltage LSB = VMAX * 7.879810-9 V.
The system constants IMAX and VMAX are used by the MPU to convert internal digital quantities (as used by the CE) to
external, i.e. metering quantities. Their values are determined by the scaling of the voltage and current sensors used in an
actual meter. The LSB values used i n this document r elate digital quantities at the CE or MPU interface to ext ernal m eter input
quantities. For example, if a SAG threshold of 80V peak is desired at the meter input, the digital value that should be pro-
grammed in to SAG_THR would be 80V/SAG_THRLSB, where SAG_THRLSB is the LSB value in the des cr iption of SAG_THR.
The parameters EQU, CE_EN, PRE_SAMPS, and SUM_CYCLES are essential to the function of the CE and are stored in I/O
RA M (see I/O RA M s ectio n).
Environment
Before starti ng the CE usi ng the CE_EN bit, the MPU has to establis h the proper environm ent f or the CE by implem enti ng the
following st eps:
• Loading t he image for the CE code into CE PRAM.
• Loading t he CE data into CE DRAM.
• Establishing the equation to be applied in EQU.
• Establishing the accum ul ation period and number of samples in PRE_SAMPS and SUM_CYCLES.
• Es tabl ishin g the numb er of cycles per A D C m ux cycle.
There must be thirteen 32768Hz cycles per ADC mux cycle (see System Timing Diagram, Figure 13). This means that t he
product of the number of cycles per ADC conversion and the num ber of conversions per cycle m ust be 12 (al lowing for one
settling cycle). The defaul t configuration is FIR_LEN = 0 (two cycle s per conve rsion) and MUX_DIV = 0 (6 conver sions per mux
cycle).
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
AUGUST 2011
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A Maxim Integrated Products Brand
During operation, the MPU is in charge of controlling the m ulti plexer cycles, for example by inserting an alternate m ultiplexer
sequence at r egular intervals using MUX_ALT. This enables temperature measurement . The polarity of CHOP m ust be altered
for each sample. It must also alternate for each alternate multiplexer reading.
Th e MP U mu st pr o gr am CHOP_EN alternately between 01 and 10 on ev er y CE_BUSY interrupt except for the fir st CE_BUSY
after an XFER_BUSY interrupt. Note that when XFER_BUSY occurs, it will always be at the same time as a CE_BUSY
interrupt.
Operating CE codes with environment parameters deviating from the values specified by Teridian will lead to
unpredictable results.
CE Calcul at ions
The CE performs the precision computations necessary to accurately measure power. These computations include offset
cancellation, phase compensation, product smoothing, product summation, frequency detection, VAR calculation, sag
detect ion, peak det ecti on, and voltage phase m eas urem ent. Al l data com puted by t he C E i s dep en den t o n t he s el ec t ed met er
equation as given by EQU (in I/O RAM). As a function of EQU, the element components V0 through I2 take on different
meanings.
EQU Watt & VAR Formul a
(WSUM/VARSUM)
Element In put Mapping
W0SUM/
VAR0SUM W1SUM/
VAR1SUM W2SUM/
VAR2SUM I0SQ
SUM I1SQ
SUM I2SQ
SUM
0 VA IA ( 1 elemen t, 2W 1 φ) VA*IA - - IA - -
1 VA*(IA-IB)/2
(1 e lement, 3W 1 φ) VA*(IA-IB)/2 - (IA-IB) IB -
2 VA*IA + VB*IB
(2 e lement, 3W 3 φ Delta) VA*IA VB*IB - IA IB -
3
VA*(IA-IB) /2 + VC *IC
(2 element, 4W 3φ Delta) VA*(IA-IB)/2 - VC*IC IA-IB IB IC
4
VA*(IA-IB)/2 + VB* (IC-IB)/2
(2 e lement, 4W 3 φ Wye) VA*(IA-IB)/2 VB*(IC-IB)/2 - IA-IB IC-IB IC
5
VA*I A + VB*IB + VC* IC
(3 e lement, 4W 3 φ Wye) VA*IA VB*IB VC*IC IA IB IC
CE RAM Locat ions
The information gi v en in the following tables appl y to CE code Version CE13B09D.
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
SEPTEMBER 2011
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CE Fron t End Dat a (Raw Dat a)
Access to the raw data provided by t he AFE i s possible by reading addres ses 0 through 7, as listed bel ow.
Addr es s (HE X) Name Description
0x00
IA
Phase A cur ren t
0x01
VA
Phase A voltage
0x02
IB
Phase B cur ren t
0x03
VB
Phase B voltage
0x04
IC
Phase C cur ren t
0x05
VC
Phase C voltage
0x06
TEMP
Temperature
0x07 V3
V3 monitor/co mpara tor
input
CE Status Word
Since the CE_BUSY interrupt occurs at 2520. 6Hz, it is desirable to minimize the com putation required in the int errupt handler
of t he MPU. T he CE status w or d can be r ead by the M P U at every CE_ BUS Y i nterr upt.
CE
Address Name Description
0x51 CESTATUS See descr iption of CE status word b elo w
The CE Status Word is useful for generating early warnings to the MPU. It contains sag warnings for phase A, B, and C, as
well as F0, the deri ved clock operating at the fundamental input frequenc y. CESTATUS provides information about the status of
voltage and input AC signal frequency, which are usef ul for generating an early power fail warning to initiate necessary data
storage. CESTATUS represents the status flags fo r the prece ding CE code pass (CE_BUSY inte rrupt).
Note: The CE does not store sag alarms from one code pass to the next. CESTATUS is refreshed at every CE_BUSY
interrupt and remains valid for up to 100µs after the CE_BUSY interrupt occurs. Unsynchronized read operations of
CESTATUS will yield unrel iab le results.
The significance of the bits in CESTATUS is shown i n th e t able belo w:
CESTATUS Bit Name Description
31-29 Not Used These unused bits will always be zer o.
28 F0 F0 is a squar e wave at the exact fundamental input frequency.
27 SAG_C Normall y zero. Becom es one when |VC| remains bel ow SAG_THR for SAG_CNT
s amples. Will n ot retu rn t o zer o until |VC | ris es above SAG_THR.
26 SAG_B Nor mally zero . B ecomes one when |VB| r emains below
SAG_THR
for
SAG_CNT
s amples. Will n ot retu rn t o zer o until |VB| r ises above SAG_THR.
25 SAG_A Nor mally zero . B ecomes one when |VA| r emains below SAG_THR for SAG_CNT
s amples. Will n ot retu rn t o zer o until |VA} r ises above SAG_THR.
24-0 Not Us ed Thes e unused bits wi ll always be zero .
For generating proper status information, the CE is i nitialized by the MPU using SAG_THR (default of 80V RMS at the meter
input if VMAX=600V) and SAG_CNT (default 80 sam ples). Using the default value for SAG_CNT, the pe ak-to-peak signal has to
be below SAG_THR value for 32 m ill iseconds to activat e th e SAG_X status bits.
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
AUGUST 2011
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A Maxim Integrated Products Brand
CE
Address Name Default Description
0x31 SAG_THR +23,930,000
(0x16D23AA)
Met er vol tage inputs must be above t his threshold to prev ent sag al arms.
LSB = VMAX * 7.879810-9 V.
For ex ample, i f a s ag threshold of 80V RMS is desired,
9
108798.7 280
_
−
⋅⋅
=
VMAX
THRSAG
0x32 SAG_CNT 80 Numb er of cons ecut ive volt age sam ples below SAG_THR before a sag alarm
is declar ed (80*397µs = 31.8ms).
CE Transfer Variables
W h en t h e MPU r ec eiv es t h e XFER_BUSY int errupt, it knows that fresh data i s available in the transf er variables. CE transfer
variables are modified during the CE code pass that ends with an XFER_BUSY interrupt. They remain constant throughout
each accumul atio n i nt erval. In t his dat a s heet , t he names of CE t ra nsfer variables alw ays end with _X.
Fundame ntal Po w er Measur ement V ariable s
The tabl e below describes each transfer variable for f undamental power m easurement. All variables are signed 32 bit integers.
Accumulated variables such as WSUM are internally scaled so they have at least 2x margin before overflow when the
int egration time is 1 second. Additionally, the hardware will not permit output val ues to ‘f old back’ upon over fl ow.
CE
Address Name Description
0x42
WSUM_X
The signed sum: W0SUM_X+W1SUM_X+W2SUM_X
0x43
W0SUM_X
The s um o f Wa t t samples from ea ch w at tmeter element .
LSB = 9.4045*10-13 VMAX IMAX / In_8 Wh.
0x44 W1SUM_X
0x45 W2SUM_X
0x46 VARSUM_X The si gned sum: VAR0SUM_X+VAR1SUM_X+VAR2SUM_X
0x47 VAR0SUM_X Th e sum of V AR samples f rom each w at tmeter element .
LSB = 9.4045*10-13 VMAX I MAX / In_8 VARh.
0x48 VAR1SUM_X
0x49 VAR2SUM_X
WSUM_X and VARSUM_X are the signed sum of Phase-A, Phase-B and Phase-C Wh or VARh values according to the
metering equation specified in the I/O RAM register EQU. WxSUM_X is the Wh value accumulated for phase ‘x’ in the last
accumulation interval and can be computed based on th e s pecif ied LSB val ue.
For ex ample, w it h VMAX = 600V and IMAX = 208A, LSB (for WxSUM_X ) is 0.1173 µWh.
Inst antaneous Power Measurement Variables
The FREQSEL Register selects the input phase used for frequency measurement and for the MAIN_EDGE counter. The
frequency measurement is implemented using the fr equency locked loop of the CE for the selec t ed phase.
IxSQSUM_X and VxSQSUM are the squared current and voltage samples acquired during the last accumulation interval.
INSQSUM_X can be used for com puting the neutr al cur r ent.
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3-Phase Energy Meter IC
DATA SHEET
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A Maxim Integrated Products Brand
CE
Address Name Description
0x33 FREQSEL
Selected phase f or the frequency monitor, the phase-to-phase vol tage
m easurements, and voltage zero crossings:
Phase A: 0 (default)
Phase B: 1
Phase C: 2
0x41 FREQ_X Fundamental frequency. LSB
6
32 10587.0
2
−
⋅≈≡ S
F
Hz
0x4A I0SQSUM_X The sum o f squar ed cu r ren t s amples f rom each element .
LSB = 9.4045*10-13 IMAX2 / In_8 2 A2h
0x4B I1SQSUM_X
0x4C I2SQSUM_X
0x4D INSQSUM_X
The s um o f squar ed cu r ren t s amples f rom the calculated neutral:
∑++ 2
210 )( III
.
LSB = 1.2539*10-12 IMAX2 / In_ 8 2 A2h
0x4E
V0SQSUM_X
The s um o f squar ed vo l ta ge s amples fr om ea ch el emen t .
LSB= 9. 4045*10-13 VMAX2 V2h
0x4F V1SQSUM_X
0x50 V2SQSUM_X
0x5A V3SQSUM_X The sum of s qua red volta ge samples f rom the V 3 input . If CAL_V3 =
8192, then LSB = 9.4045*10-13 VMAX2 V2h or 9.4 045*1 0-13 IMAX2 I2h
The RMS values can be com put ed by the MPU from t he squared current and volt age samples as per the formulae:
Other Measure men t Para meters
PH_AtoB_X and PH_AtoC_X contain phase angle information between the phase voltages, depending on the setting of
FREQ_SEL, as shown in the table below. The phase angle inform ation can be used for phase sequencing and error det ection.
If the voltage at the selec t ed phase is missing, t he meter accuracy will be reduced.
To maintain accuracy, FREQ_SEL must be set to a phase with an active voltage. For example, in a system where
phase A is lost (which can be detected using the SAG bits or by comparing the voltage VA with a lower limit),
FREQ_SEL must b e set to an alter nat ive phase to maint ain accur acy .
MAINEDGE_X i s us efu l fo r im plem en ti ng a rea l-time clock based on the input AC signal. MAINEDGE_X is the number of half-
cycles account ed for in the las t accum ul ated interval f or the AC signal of the phase specified in the FREQ_SEL register.
ACC
S
RMS
NFLSBVxSQSUM
Vx ⋅⋅⋅
=3600
ACC
S
RMS NFLSBIxSQSUM
Ix ⋅⋅⋅
=3600
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
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A Maxim Integrated Products Brand
CE
Address Name
Description
FREQU_SEL = 0 FREQU_SEL = 1 FREQU_SEL = 2
0x52 PH_AtoB_X Phase lag from V A t o VB.
Phase lag from VB to VC.
Phase lag from VC to VA.
Angle in degrees PH_AtoB_X*360/NACC+2.4 PH_AtoB_X*360/NACC+2.4 PH_AtoB_X*360/NACC-4.8
0x53 PH_AtoC_X Phase lag from VA to VC.
Phase lag from VB to VA.
Phase lag from VC to VB.
Angle in degrees PH_AtoC_X*360/NACC+4.8 PH_AtoC_X *360/NACC-2.4 PH_AtoC_X *360/NACC-2.4
0x55 MAINEDGE_X
The number of zero
c ro ssings of V A in th e pre-
vious accumulation interval.
The number of zero
c ro ssings of V B in th e pre-
vious accumulation interval.
The number of zero
c ro ssings of V C in t he pr e-
vious accumulation interval.
Edge crossings ar e eit her direction and are debounced.
Temperature Measurement and Tem perature Compensat ion
Input variables: TEMP_NOM is the reference value for temperature measurement, i.e. when this value is set with
TEMP_RAW_X at known temperature. The 71M6513/6513H measur es temperature with refer ence to this val ue.
DEGSCALE is th e s lo pe or r ate of temp eratu re incr eas e or decrea se fr om the TEMP_NOM for TEMP_X measurement.
PPMC and PPMC2 are t emperature com pensati on coefficients. Thei r values should reflect the characteristics of the band gap
voltage re fe re nce of the chip. PPMC and PPMC2 follow the square law characte ristics to compensate for nonl inear tempe ra ture
behaviors, when the 71M6513/6513H is in internal temper ature compens ation mode.
EXT_TEMP al lows t he MPU t o select bet ween di rec t con trol of GAIN_ADJ or managem ent of GAIN_ADJ by the CE, based on
TEMP_X and the temperature c orrec t ion coeffici ents PPMC and PPMC2.
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
SEPTEMBER 2011
© 2005-2011 Teridian Semiconductor Corporation Page: 73 of 104
A Maxim Integrated Products Brand
CE
Address Name Default Description
0x11 TEMP_NOM 0
Dur ing c alibrat ion, t he value of TEMP_RAW_X should be pl aced in
TEMP_NOM.
0x30 DEGSCALE 22721 Scale factor for TEMP_X.
TEMP_X = -DEGSCALE*2-22*(TEMP_RAW_X-TEMP_NOM).
0x38 EXT_TEMP 0
Should be 15 or 0. When 15, causes the CE t o ignore internal tem perature
c ompens ation and permits the MPU to co nt ro l GAIN_ADJ. When internal
tem per at ure c omp ens atio n is sel ect ed, GAIN_ADJ will b e:
⋅
+
⋅
++=
23
2
14
22_
2
_
116384_ PPMCXTEMPPPMCXTEMP
floorADJGAIN
Default is 0 ( internal compens ation).
0x39 PPMC 0
Linear te mperature com pensat i on factor. Equals the li near temperature co-
eff icien t (PPM/° C) of V REF m ult iplied by 26 .84 , or T C 1 (expr essed in µV/ °C,
s ee E lect ric al Sp ecific at ions) mul tiplied by 22. 46 1. A positive value will cause
the meter to run faster when hot. The compensation factor affects both V and
I and wi ll therefore have a doubl e effect on products.
1 CE sca ling factor 22.46=221/(1.195*57)
0x3A PPMC2 0
Square-law temperat ure compensation factor. Equal s the square-law tem-
perature coeffici ent (PPM/°C2) of VREF m ultiplied by 1374, or TC2 (ex-
pressed in µV/° C 2, see Elect r ical Specif icat i on s) multiplied by 11502.1. A po-
s i tiv e value will cause the meter t o run f aster when hot. The compensation
factor affects both V and I and will therefore have a doubl e effect on prod-
ucts.
2 CE sca ling factor 1150=229/(1.195*58)
Output variables: TEMP_X is the temperature measurement from reference temperature of TEMP_NOM. TEMP_X is
computed using TEMP_RAW_X and DEGSCALE. Thi s qu ant ity is positi ve wh en t he t em per at ur e is a bo ve t he r efer ence a nd is
negative for cold temperatures.
TEMP_RAW_X is the raw processed value from ADC output and is the fundamental quantity for temperature measurement.
TEMP_RAW_X is less than TEMP_NOM at higher temperatures. TEMP_RAW_X is more than TEMP_NOM for cooler
tem per at ures than referen ce t emp erature.
GAIN_ADJ is a scaling factor for power measurements based on temperature (when in internal temperature compensation
mode). In general, for higher tem perat ures it is lower than 16384 and higher t han 16384 for lower tem peratures. GAIN_ADJ is
mainly dependent on the PPMC, PPMC2 and TEMP_X register values. This parameter is automati cally computed by the CE
and is used by the CE for temperature compensati on.
CE
Address
Name Description
0x40 TEMP_X Deviat i on from Cal ibrati on temp era ture. LSB = 0 . 1
0
C.
0x54 TEMP_RAW_X
Filtered, unscaled reading from tem perature sensor. This value should be
writte n to TEMP_NOM dur ing mete r calib ration.
0x2E GAIN_ADJ
Scales all voltage and current inputs. 16384 p rov ides unity ga in. Default is
16384. If EXT_TMP = 0 , GAIN_ADJ is updated by the CE.
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
AUGUST 2011
Page: 74 of 104 © 2005-2011 Teridian Semiconductor Corporation
A Maxim Integrated Products Brand
Pulse Generation
Input variables: The combination of the PULSE_SLOW and PULSE_FAST parameters control the speed of the pulse rat e. The
default values of 1 and 1 wil l maintai n the original pulse rate gi ven by th e Kh equatio n.
WRATE controls the number of pulses that are gen erated per measured W h and VARh quantities. The lower WRATE i t is the
slower is the pulse rate for measured power quantity. The metering constant Kh is derived from WRATE as the amount of
energy measured for each pulse. That is, if Kh = 1Wh/pulse, a power applied to the meter of 120V and 30A results in one
pulse per second. If the load is 240V at 150A, ten pulses per second will be generated.
Control is transferred to the MPU for pulse generation if EXT_PULSE > 0. In this case, the pulse rate is determined by
APULSEW and APULSER. The MPU has to load the sour ce for pulse generation in APULSEW and APULSER to gener ate puls es.
I rrespect ive o f the EXT_PULSE, status the out put pulse rate controlled by APULSEW and APULSER i s imp lem ent ed by t he CE
only. By setting EXT_PULSE > 0, the MPU is providi ng the source for pulse generation. If EXT_PULSE is negative, W0SUM_X
and VAR0SUM_X ar e the default pulse gener at ion sources. In this cas e, creep cannot be contr oll ed since it is an M P U fun ct ion.
The maximum pulse rate is 3*FS = 7.56kHz.
PULSE_WIDTH allows adjustment of the pulse width for compatibility with calibration and other external equipment. The
m ini mum p ulse width possible is 6 6.1 6µs .
The maximum time jitter is 1/ 6 of t he MUX cycle period (normally 67μs) and is independent of the number of pulses measured.
Thus, if the pulse gener ator is monitor ed for 1 second, the peak j itter is 67ppm. After 10 seconds, the peak jitter i s 7ppm . The
av er a g e j it ter i s al wa y s zer o . If i t i s at t empt ed t o dr i v e ei t her pu l s e g en er at o r f as t er t ha n i t s m a xim um rate, i t w il l sim p l y ou t p ut
at its max i mu m rate without ex hibiting any roll-over characteristics. The ac tu al pulse rate, using WSUM as an exampl e, is:
Hz
FWSUMWRATEX
RATE
S
46
2
⋅⋅⋅
=
Where FS = 2520.6Hz (sampling frequency), and X = pulse speed factor derived from CE variables PULSE_SLOW and
PULSE_FAST (see ta ble belo w).
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
SEPTEMBER 2011
© 2005-2011 Teridian Semiconductor Corporation Page: 75 of 104
A Maxim Integrated Products Brand
CE
Address Name Default Description
0x28
PULSE_SLOW
1
When PULSE_SLOW > 0, t he pulse generator i nput i s reduced 64x.
When PULSE_FAST > 0, the pulse generat or input is incr eased 16x.
Thes e two parameters c ont rol th e pul se g ain factor X ( see tabl e below ) .
Allow ed value s are either 1 or –1.
X
PULSE_SLOW
PULSE_FAST
1.5 * 2
2
= 6 -1 -1
1.5 * 2
6
= 96 -1 1
1.5 * 2
-4
= 0.09375 1 -1
1.5 1 (default) 1 (default)
0x29 PULSE_FAST 1
0x2D
WRATE
683
Kh =
VMAX
*
IMAX
*66 .1782 / (
In_8
*WRATE*N
ACC
*X) Wh/pulse.
0x36
SUM_PRE
2520
PRE_SAMPS
*
SUM_CYCLES
(NACC)
0x37 EXT_PULSE 15 Shoul d be 15 or 0. When zero, causes the pulse generators to respond to
WSUM_X and VARSUM_X. Oth erwise, the gener ators respond t o values the
MPU places in APULSEW and APULSER.
0x3C PULSE_WIDTH 50 The maximum pulse width (low-going pulse) is:
(2 * PULSE_WIDTH + 1) * 66µ s. 0 i s a legit i ma te val ue.
0x26 APULSEW 0
W h pulse generator input, to be updated by the MPU when using external pulse
generation (see DIO_PW b it). The outp ut puls e rate is:
APULSEW * FS * 2-32 * WRATE * 2-14
This input is buffered and can be updated by the MPU during a comput ati on
interval. The change will t ake effec t at the beginnin g of t he next inter val .
0x27 APULSER 0
VARh pul se generator input, to be updated by the MPU when using exter nal
pulse gene ration (see DIO_PV bi t). The output pul se r ate i s:
APULSER * FS*2-32 * WRATE * 2-14
This input is buffered and can be updated by the MPU during a comput ati on
interval. The change will t ake effec t at the beginnin g of t he next inter val .
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
AUGUST 2011
Page: 76 of 104 © 2005-2011 Teridian Semiconductor Corporation
A Maxim Integrated Products Brand
CE Cal ib ratio n Param et ers
The t able belo w li s ts the par ameters that are typi ca l ly ent ered to effect calib rat io n o f meter a cc ura cy.
CE
Address
Name Default Description
0x08 CAL_IA 16384
These constants contr ol the gain of t heir respect ive channels. The nominal
value for each param eter is 214 = 16384. The gain of ea ch channel is di rect l y
proportio nal to its C AL parameter. T hus, if the gai n of a channel is 1% slow,
CAL should be increased by 1%.
0x09 CAL_VA 16384
0x0A CAL_IB 16384
0x0B
CAL_VB
16384
0x0C
CAL_IC
16384
0x0D CAL_VC 16384
0x65
CAL_V3
8192
Gai n c ont rol for V3 chann el, us ed for n eut r al cur ren t mea surement.
0x0E PHADJ_A 0
These thr ee constants control the CT phase com pensation. No com pensation
occurs when PHADJ_X = 0. As PHADJ_X
is increased, more compensation
(l ag) i s introduced. Range: ±215 –
1. I f it is desired to delay the current by the
angle Φ:
Φ⋅−
Φ⋅
=TAN
TAN
XPHADJ 0131.01487.0 02229.0
2_
20
at 60Hz
Φ⋅−
Φ⋅
=TAN
TAN
XPHADJ 009695.01241.0 0155.0
2_ 20
at 50Hz
0x0F PHADJ_B 0
0x10 PHADJ_C 0
0x11 TEMP_NOM N/A
During calibration, the value of TEMP_RAW_X should be placed in
TEMP_NOM.
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
SEPTEMBER 2011
© 2005-2011 Teridian Semiconductor Corporation Page: 77 of 104
A Maxim Integrated Products Brand
Ot her CE Par ameters
Th e table b elow shows CE par am eter s us ed for s up pres si on of noi se d ue t o sc ali ng and t run cat i on ef fec ts as well as s cal ing
factors.
CE
Address Name Default Description
0x2F QUANT 0 This parameter is added to the Watt calculation to compensate for input noise
and truncation.
LSB=(VMAX*IMAX / In_8) *1.04173*10-9 W
0x34 QUANT_VAR 0 Thi s parameter is added to the VAR cal culation to compensate for input noise
and truncation.
LSB = (VMAX*IMAX/In_8) * 1.04173*10-9 W
0x35 QUANT_I 0
This parameter is added to compensate for input noise and truncation in t he
squaring calculations for I2 and V2.
LSB=VMAX2*1.04173*10-9 V2
LSB= (IMAX2/In_82)*1.04173*10-9 A2
0x3B KVAR 6448 Scale factor for t he VAR calculation. The default value of KVAR shoul d nev er
need to be changed.
0x64 QUANT_V3 0 Offs et fo r low-cur ren t mea sur emen t on V3.
LSB = = 9.4045*10-13 IMAX2 A2h
TYPICAL PERFORMANCE DATA
Wh Accuracy at Ro om Temperatu re
Figure 24: Wh Accuracy, 0.3A - 200A/240V
VARh Accuracy at Room Temperatu re
200
100
30
25
10
3
1
0.3
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
0.1 1 10 100 1000
%Error
A
0 Deg
60 Deg
-60 Deg
180 Deg
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
AUGUST 2011
Page: 78 of 104 © 2005-2011 Teridian Semiconductor Corporation
A Maxim Integrated Products Brand
Figure 25: VARh Accuracy for 0.3A to 200A/240V Performance
Harmon ic Performance
T est p erform ed at cu r r ent dis t or ti on am plitu d e of 40% and voltag e dist ort i on am pl itud e of 10% as p er IEC 62 0 53, part 22 .
Figure 26: Meter Accuracy over Harmonics at 240V, 30A
200
100
30
25
10
3
1
0.3
-0.2
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0.2
0.1 1 10 100 1000
% E rro r
A
90 De g
150 De g
270 De g
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
1357911 13 15 17 19 21 23 25
Harmonic
Error [%]
50Hz Harmonic Data 60Hz Harmonic Data
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
SEPTEMBER 2011
© 2005-2011 Teridian Semiconductor Corporation Page: 79 of 104
A Maxim Integrated Products Brand
AP P L ICATIO N IN FO R M ATION
Con ne c t io n of Se ns or s ( CT, R e s is tiv e S h unt, Rogows k i C oil)
Figures 27 thr ough 30 show how resistive di viders, current transformers, restive shunts, and Rogowski coils are connect ed to
the voltage and current inputs of the 71M6513.
The analog i nput pins of the 71M6511 are desi gned for sensors with low source impedance. RC filters with resistance
values higher than those implem ented in the Teridian Demo Boards should be avoided.
Figure 27: Resistive Voltage Divider (left), Current Transformer (right)
Figure 28: Resistive Shunt (left ), Rogowski Coil (right)
Distinction betw een 71M6513 and 71M 6513H P art s
71M6513H parts go through a process of trimming and characterization during production that make them suitable to high-
accuracy applications.
The first process applied to the 71M6513H is the trimming of the refer ence voltage, which i s guaranteed to have acc uracy over
tem per at ure o f bet ter that ±10PPM/°C.
The second process applied to the 71M6513H is the characterization of the reference voltage over temperature. The
coefficients for the reference vol tage are stored in so-c all ed trim f us es ( I/O RAM reg is ter s TRIMBGA, TRIMBGB, TRIMM[2:0].
The MPU progr am can read these trim fuses and calculat e the cor r ecti on coefficients PPM1 and PPM2 per the f ormulae given
in t he Performance Specificat ions sec t ion ( V REF, VBIAS). S ee the Temper atur e C omp ens ation sec t ion f or det ails.
The f us e TRIMBGB is non-zero for the 71M6513H par t and ze ro for the 71M6513 part.
Trim fuse information is not available for non-H parts. Thus, t he standar d set t ings are to be applied . Th ese s ettings are:
• PPMC = TC 1 * 22. 46 = –149
• PPMC2 = TC2 * 1150.1 = –392
VA = Vin * R
out
/(R
out
+ R
in
)
V
in
R
in
R
out
VA
Vout = dI
in
/dt
V
out
R
1/N
I
in
V
C
V3P3
IA
Vout = dI
in
/dt
V
out
R
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
AUGUST 2011
Page: 80 of 104 © 2005-2011 Teridian Semiconductor Corporation
A Maxim Integrated Products Brand
Temperature Compensation and Mains Frequency Stabilization for the RT C
The accuracy of the RTC depends on the stability of the ext er nal c r ystal. Crystals vary in terms of initial accuracy as well as in
terms of behavior over temperature. The flexibility provided by the MPU allows for compensation of the RTC using the sub-
strate tem perature. To achieve this, the crystal has to be characterized over temperature and the three coefficients Y_CAL,
Y_CALC, and Y_CAL_C2 have to be calculated. Provided the IC substrate t emperatures tracks the crystal t em perat ure, the
coefficients can be used in the MPU firmware to trigger occasional corrections of the RTC seconds count, using the
RTC_DEC_SEC or RTC_INC_SEC registers in I/O RAM.
It is not recommended to measure crystal frequency directly due to the error introduced by the measurement probes. A
practical method t o measur e t he cr y st al frequency (when installed on the PCB with the 71M6513) is to have a DIO pin t oggle
every second, based on the RTC interrupt, with all other interrupts disabled. When this signal is measured with a precision
timer, the cr ystal frequenc y can be obtained f r om the measured time period t (in µs):
tµs
f6
10
32768=
Example: Let us assume a crystal characterized by the measurements shown in Table 61. The values show that even at
nominal temperature (the temperature at which the chip was calibrated for energy), the deviation from the ideal crystal
frequency is 11.6 PPM, resul ti ng in about one second inaccuracy per day, i.e. more than som e standards allow.
Deviation from
Nominal
Temperature [°C]
Measured
Frequency [Hz] Deviation from
Nominal
Frequency [PPM]
+50
32767.98
-0.61
+25 32768.28 8.545
0 32768.38 11.597
-25 32768.08 2.441
-50 32767.58 -12.817
Table 61: Frequency over Tempe r ature
As Figure 29 shows, even a constant compensation woul d not bring much im provement, since the tem perature characteristics
of the crystal are a mi x of constant, linear , and quadratic ef fects (in commercially available crystals, the constant and quadrati c
eff ect s are dominant).
Figure 29: Crystal Frequency over Temperature
The tem per ature charact eristics of the crystal are obtained from t he curve in Figure 29 by curve-fitti ng the PPM deviations. A
fai r ly c los e cu r ve fit i s ac hieved w ith the coef fi cient s a = 10.8 9, b = 0 .122, and c = –0 .00 714 (see Figure 30).
32767.5
32767.6
32767.7
32767.8
32767.9
32768
32768.1
32768.2
32768.3
32768.4
32768.5
-50 -25 025 50
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
SEPTEMBER 2011
© 2005-2011 Teridian Semiconductor Corporation Page: 81 of 104
A Maxim Integrated Products Brand
When applying the inverted coefficients, a curve (see Figure 30) will result that effectively neutralizes the original crystal
characteristics. The frequencies were calculated using the fit coefficients as follows:
+++⋅= 6
2
66 101010
1c
T
b
T
a
ff nom
Figure 30: Crystal Compensation
The MPU Dem o Code supplied with the Teridian Dem o Kit s has a direc t interface f or these coeffi cients and it directly controls
the RTC_DEC_SEC or RTC_INC_SEC r egisters. The Demo Code uses t he coefficients in the following form:
1000 2_
100
_
10
_
)( 2CALCY
T
CALCY
T
CALY
ppmCORRECTION ⋅+⋅+=
No te t hat th e co effici ents a re scaled by 10, 100, and 1000 to provide more resolution. For our example case, t he coeffici ents
would then become ( after r ounding, since t he Demo Code accep ts only in tegers):
Y_CAL = 109, Y_CALC = 12, Y_CALC2 = 7
Alternatively, the mains frequency may be used to stabilize or check the function of the RTC. For this purpose, the CE
provides a count of the zero crossings detected for the selected line voltage in the MAIN_EDGE_X address. This count is
equivalent to twice the line frequency, and can be used to synchr onize and/or corr ect the RTC.
External Tem perature Compensat ion
In a production electricity meter, the 71M6513 or 71M6513H is not the only component contributing to temperature de-
pendency. In fact, a whole range of com ponents (e. g. curr ent transformers, resistor dividers, power sources, filter capacitors)
will exhibi t slight or pronounced temperature effects. Since the output of the on-chi p t em per at ure s ens or is acc essible t o t he
MPU, temperature-compensation mechanisms with great flexibility, i.e. beyond the capabilities implemented in the CE, are
possible.
Temperature Measuremen t
Temperature measure ment can be implemented with the following steps:
1) At a known tem perature TN, read the TEMP_RAW register of the CE and wri t e the value into TEMP_NOM.
2) Read the TEMP_X regi s ter at t he k now n t emp erat ure. The obt ai ned val ue s hould b e <±0.1°C.
3) The t emperature T (in °C) at any envir onm ent can be obtained by reading TEMP_X and applying t he following
formula:
32767.5
32767.6
32767.7
32767.8
32767.9
32768
32768.1
32768.2
32768.3
32768.4
32768.5
-50 -25 025 50
crystal
cur ve fit
inverse cur ve
10_XTEMP
TT
N
+=
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
AUGUST 2011
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Temperature Compen sation
For the 71M6513 (regular accuracy parts), the temperature coefficients T C1 and TC2 are given as const ants t hat represent
typical compone nt behavio r (in µV/°C2). TC1 and TC2 allow compensation for variations of the reference voltage to within ±40
PPM/°C.
For the high-accuracy parts, individualized c oefficients TC1 and TC2 can be r etrieved f rom the on-chip fuses via TRIMBGA,
TRIMBGB, TRIMM[2:0] (see Section ‘Distinction between 71M6513 and 71M6513H Parts’). For the 71M6513H, TC1 and TC2
allow compensation for variations of the reference voltage to within ±10 PPM/°C
Since TC1 a nd TC 2 ar e given in µV/ °C an d µV/ °C2, respectively, the value of t he VREF voltage (1.195V) has to be
taken into account when transi ti oning to PPM/°C and PPM/°C2. This means that PPMC = 26.84*TC1/1.195 and
PPMC2 = 1374*TC2/1 .195).
Clo se exa mination of the electrical specificat ion (s ee Table 62) for the 71M6513 r evea ls that the achievable d eviati on is not
strictly ±40 PPM/°C over the whole temperature range: Only for temperatures for which T-22 > 4 0 ( i.e. T > 62°C) or for which
T-22 < -4 0 ( i.e. T < -18°C), the dat a sheet s tates ±40 PPM/°C. For temperatures between -18°C and +62°C, the err or should
be consi dered constant at ±1,600 PPM, or ±0.16%.
Similar considerations apply to t he high-accuracy part 71M6513H (see Table 63) , w her e th e error a rou nd t he c al ibr at ion
temperat ure shoul d be considered constant at ±600 P PM, or ±0.06%.
Table 62: VREF Definition for the Re gul ar Accura cy Part s 71M6513
Parameter Min
T
yp
VREF(T) de viation fro m VNOM(T)
)40,22max( 10
)( )()(
6
−
−
TTVNOM TVNOMTVREF
-40 +40 PPM/ºC
Table 63: VREF Definition for the Hi gh-Accuracy Parts 71M6513H
Parameter
Min
Typ
VREF(T) de viation fro m VNOM(T)
)40,22max( 10
)( )()(
6
−
−
TTVNOM TVNOMTVREF
-10 +10 PPM/ºC
Figure 31 and Figure 32 show this concept grap hical ly. The “box ” from -18°C to +62°C reflect s the fact that it is impractical
to meas ur e t he t emp erat ure c oef f icient of high-qu al it y ref erenc es at small t emp era ture excursio ns. For example, at + 25°C,
the expect ed er ror would b e ±3°C * 40 PPM/°C, or just 0.012% for the regular-accuracy par ts.
The maximum deviation of ±2520 PPM (or 0.252%) for the regular-accuracy parts is reached at the temperature
extremes. If the ref erence volt age is used to m easure bot h voltage and current, the identi cal err ors of ±0. 252% add up t o
a maximum Wh r egistration er ror of ±0.504%.
The maximum deviation of ±630 PPM (or 0.063%) for the 71M6513H is reached at the temperature extremes. If the
reference volt age is used to m easure both voltage and curr ent, the ident ical errors of ±0.063% add up to a maximum Wh
r egist ration error o f ±0.126%.
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
SEPTEMBER 2011
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A Maxim Integrated Products Brand
Figure 31: Error Band for VREF over Temperature (Regular -Accuracy Parts)
Figure 32: Error Band for VREF over Temperature (High-Accuracy Parts)
Crystal Oscillator
The oscillator drives a standard 32.768 kHz watch crystal. The oscillator has been designed specifically to handle these
cr yst al s a nd i s c om pati ble wit h t h eir hig h im peda nc e a nd li m ited p o wer ha ndli n g c ap abil it y. The oscillator power dissipation is
very low to maximize t he lifetime of any battery bac kup dev i ce attached t o VBAT.
Board layouts with m inimum capacitance from XIN to XOUT will require less battery current. Good layouts will have XIN and
XOU T shiel ded from ea ch oth er.
-2800
-2400
-2000
-1600
-1200
-800
-400
0
400
800
1200
1600
2000
2400
2800
-40 -20 020 40 60 80
Error Band (PPM) over Temperature (°C)
±40 PPM/°C
±40 PPM/°C
-1000
-800
-600
-400
-200
0
200
400
600
800
1000
-40 -20 020 40 60 80
Error Band (PPM) over Temperature (°C)
-10 PPM/°C
+10 PPM/°C
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
AUGUST 2011
Page: 84 of 104 © 2005-2011 Teridian Semiconductor Corporation
A Maxim Integrated Products Brand
For best rejection of electromagnetic interference, connect the crystal body and the ground terminals of the two
crystal capacitors to GNDD through a ferrite bead. No external resistor should be connected across the crystal,
since the oscillator is self-biasing.
Con ne c t in g LCDs
The 71M6513 has a LCD controller on-chip capable of controlling static or multiplexed LCDs. Figure 33 shows the basic
connection f or a LCD.
Figure 33: Connecting LCDs
Figure 34 shows how 5V LCDs can be operated even when a 5V supply is not available. Setting the I/O RAM register
LCD_BSTEN to 1 starts the on-chip boost circuitry that will output an AC frequency on the VDRV pin. Using a small coupling
capacitor, two general-purpose diodes and a reservoir capacit or, a 5VDC voltage is generat ed which can be f ed back i nto the
VLCD pin of t he 71M6513. The LCD dri vers are enabled with the I/O register LCD_ON; I/O register LCD_FS is used to adjust
contrast, and LCD_MODE selects the operati on mode (LCD type).
segments
71M6513
LCD
commons
segments
71M6513
LCD
commons
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
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© 2005-2011 Teridian Semiconductor Corporation Page: 85 of 104
A Maxim Integrated Products Brand
Figure 34: LCD Boost Cir cuit
Connecting I2C EEPROMs
I2C EEPROMs or other I2C com pati ble dev ices shoul d be connected to the DIO pins DIO4 and DIO5, as shown in Figure 35.
Pull-up resistors of roughly 3kΩ to V3P3 should be used for both SCL and SDA signals. The DIO_EEX register in I/O RAM
must be set to 1 in order to convert the DIO pins DIO4 and DIO5 to I2C pins SCL and SDA.
Figure 35: EEPROM Connect ion
Connect ing 5V Devices
In gener al, all pins of the 71M6513 ar e compat ibl e with external 5V devices. The exc epti ons are the power supply pins and the
RX pin of t he UA RT (see s ect ion Elec t ri cal Sp ecif icat ions) .
LCD_BSTEN
segments
71M6513
5V LCD
commons
VLCD
V3P3
5VDC
VDRV
V3P3
LCD_FS
LCD_EN
LCD_MODE
Contrast
ON/OFF
L CD t ype
LCD_BSTEN
segments
71M6513
5V LCD
commons
VLCD
V3P3
5VDC
VDRV
V3P3
LCD_FS
LCD_EN
LCD_MODE
Contrast
ON/OFF
L CD t ype
DIO4
DIO5
71M6513
EEPROM
SCL
SDA
V3P3
3kΩ
3kΩ
DIO4
DIO5
71M6513
EEPROM
SCL
SDA
V3P3
3kΩ
3kΩ
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
AUGUST 2011
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A Maxim Integrated Products Brand
Figure 36: Interfacing RX to a 0-5V Signal
Figure 36 shows how a 5V signal from an exter nal dev ice can be safely i nt erfaced to the RX pin.
71M651X
V
IN
RX
R1 = 100kΩ
V3P3
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
SEPTEMBER 2011
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A Maxim Integrated Products Brand
Opt ical Interface
The pins O PT_TX and OPT_RX can be used for a regular seri al interface, e.g. by connecting a RS_232 tr ansceiver, or they
can be used to dir ectly operate optical com ponents, e.g. an infrared diode and phot otransistor implementi ng a FLAG interface.
Figure 37 shows the basic connect ions. The OPT_TX pin becomes active when t he I/O RAM register OPT_TXDIS is set to 0.
Figure 37: Connecti on f or Opti cal Component s
Connect ing V1 and Reset Pins
A voltage divider should be used to establish that V1 i s in a safe range when the m eter is in mission mode (V1 must be lower
than 2.9V in all cas es in order to keep t he hardware watchdog tim er enabled). For proper debuggi ng or loading code into the
71M6513 mounted on a PCB, it is necessary to have a provision like the header shown above R1 in Figure 38. A shorting
jumper on this header pulls V1 up to V3P3 disabling the har dware watchdog tim er.
Figure 38: Voltage Divider for V1
Even though a f unctional meter will not necessar il y need a r eset swit c h, it is useful to have a reset pushbutton f or prototyping.
When a circuit is used in an EMI environment, the RESETZ pin should be supported by the external components shown in
Figure 39. R1 should be in the r ange of 200Ω, R2 should be ar ound 10Ω. The capaci tor C1 should be 1nF. R1 and C1 should
be mounted as close as possible to the IC. In cases where the trace from the pushbutton switch to the RESTZ pin poses a
problem, R2 can be remove d.
OPT_TX R
2
R
1
OPT_RX
71M6513
V3P3SYS
Phototransistor
LED
100kΩ
100pF
V3P3SYS
OPT_TX R
2
R
1
OPT_RX
71M6513
V3P3SYS
Phototransistor
LED
100kΩ
100pF
V3P3SYS
V
in
R
2
V1
R
1
R
3
10kΩ
V
in
R
2
V1
R
1
R
3
10kΩ
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
AUGUST 2011
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A Maxim Integrated Products Brand
Figure 39: External Com ponents for RESETZ
Connecting the V3 Pin
The following shoul d be noted when connecting the V3 pin:
1) If t he V3 pin is unused it should be left f loating or terminated to the VREF pin.
2) If t he V3 pin is used as a c omp arator input the digital input voltage appl ied to V3 should be limited to VBIAS ±0.9V.
3) If t he V3 pin is used either as an auxiliary analog input, and tem perature measur em ents are made and evaluated
using the alternate multiplexer cycle, the V3 input voltage range must be restri cted to VBIAS ±0.9 V (i.e . 0 .6 V to 2. 4
V). Otherwise, t he TEMP or V3 m easurement c ould be inaccur ate. This precaution is particularly impo r tant for
customers who ar e using the TEMP samples for temper ature compensation, especially with the 71M6513H devices.
Connect ing a Battery
Many m eter manufacturers assem ble the meter PCB with the 71M6513 IC and the other electr onic components fi rst and t hen
join the meter PCB with the meter enclosure, sensors and other main components separately at a later production step.
Typ ically, pr ogr ammin g, final t est (ATE), and calib rat io n ar e perfor med a f ter this s econd step.
The following production sequence is strongly recommended:
1) During PCB assembly, when adding/inserting the bat t ery, the boar d supply voltage (V3P3A, V3P3D) should be ac tive
(i.e. at 3.3 VDC), which can be achieved by briefly connecting the battery to V3P3A/V3P3D through a jumper wire.
After the batt ery is i nserted with the boar d power active, the jumper wi r e should be removed.
2) Th e battery should t hen remai n co nnect ed thr ough f actor y test (A TE) , time on the shelf and shipment.
In cases wher e it is not feasible to power V3P3A/V3P3D while inserting the bat t ery, it is r ecommended to i solate the bat ter y i n
its holder using a rem ovable piece of Kapton t ape or ot her isolating materi al. This isolation should then be remov ed once the
meter i s ful ly powered duri ng the calibrat ion and test proce ss.
R
1
RESETZ
71M6513
DGND
V3P3
R
2
V3P3
Pushbutton C
1
200Ω
1nF
10ΩR
1
RESETZ
71M6513
DGND
V3P3
R
2
V3P3
Pushbutton C
1
200Ω
1nF
10Ω
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
SEPTEMBER 2011
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A Maxim Integrated Products Brand
Fl ash Prog ramming
Operational or test code can be programm ed i nto the flash memory using eit her an i n-circuit em ulator or the Flash Download
Board Module (FDBM) available from Teridian. The flash programming procedure uses the E_RTS, E_RXTX, and E_TCLK
pins.
MPU Firmware Library
All application-specific MPU functions mentioned above under “Application Information” are available from Teridian as a
standard ANSI C library and as ANSI “ C” source code. The code is available as part of the Dem onstr ation Kit for the 71M6513
and 71M6513H ICs. The Demonstration Kits come with the 71M6513 or 71M6513H IC preprogrammed with demo firmware
mounted on a functi onal sam ple m eter PCB (Demo Board). The D em o Boards al l ow for quick and effic ien t evalu at ion of the IC
without having to write firmware or having to supply an in-circui t em ul ator (I CE ).
A reference gui de for firmware development on the 71M6513 and 71M6513H is available as a separate doc um ent (Software
User ’s Guide, “SUG”) . T he User’s Manuals supplied with the Demo Kits contain MPU address m aps for the demo code as well
as other us efu l i nformation, such as sample c alibrat ion proc edures .
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
AUGUST 2011
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A Maxim Integrated Products Brand
SPECIFICATIONS
Elect rical Specificat ions
ABSOLUTE MAXIMUM RATINGS
Supplies and Ground Pins:
V3P3D, V3P3A
−
0.5V to 4.6V
| V3P3D - V3P3A |
0V t o 0.5 V
VLCD
-0.5V to 7V
VBAT
-0.5V to 4.6V
GNDD
-0.5V to +0.5V
Analog Output Pins:
VREF, VBIAS
-1mA to 1mA,
-0.5 to V3P3A+0. 5V
V2P5
-1mA to 1mA,
-0.5V to 3.0V
Analog Input Pins:
IA, VA, IB, VB, IC, VC, V2, V3
-0.5V to V3P3A+0. 5V
XIN, XOUT
-0.5V to 3.0V
RX
-0.5V to 3.6V
OPT_RX
-1mA to 1mA
-0.5 to V3P3A+0. 5V
Digital Input Pins:
DIO0-2 1, E_RXTX, E_RST, E_ISYNC/ BRKRQ -0.5 to 6V
TEST, RESETZ -0.5 to V3P3D+0.5V
All Other Pins:
Input pi ns -5mA to 5mA
-0.5V to V3P3D+0.5V
Output pins -30 mA to 30mA
-0.5 to V3P3D+0.5V
Temperature:
Operating junction tempe rature (peak, 100ms)
140 °C
Operating junction tempe rature (continuo us)
125 °C
Sto rag e temperat ure
−45 °C to 165 °C
Solder te mperature – 10 second duration
250 °C
ESD Stress:
Pins IA, VA, IB, VB, IC, VC, RX, TX, E_RST, E_TCLK, E_RXTX, E_TBUS[n]
4kV
All oth er pin s
2kV
Stresses beyond Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only and functional
operation at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions fo r extended periods may affect device reliability. All volt ag es ar e wi th resp ec t to GND A.
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
SEPTEMBER 2011
© 2005-2011 Teridian Semiconductor Corporation Page: 91 of 104
A Maxim Integrated Products Brand
RECOMMENDED OP ERATING CONDITIO NS
PARAMETER CONDITION MIN TYP MAX UNIT
3.3V Suppl y Voltage
(V3P3A, V3P3D) † Normal Ope ration 3.0 3.3 3.6 V
Battery Backup 0 3.45 V
VLCD 2.9 5.5 V
VBAT
No Battery
Externall y Connect to V3P3D
Battery Backup 2.0 3.8 V
Operating Temperature -40 85 ºC
†V3P3A and V3P3D should be shorted together on the circuit board. GNDA and GNDD should also be shorted on the circuit board.
LOGIC LEVELS
PARAMETER CONDITION MIN TYP MAX UNIT
Digital high-lev el input vol tage, VIH 2 V3P3D V
Digital low-le vel input voltage, VIL −0.3 0.8 V
Digital high-level output voltage VOH ILOAD = 1mA V3P3D
–0.4 V3P3D V
ILOAD = 15mA V3P3D-
0.61 V
Digital low-level outp ut voltage VOL ILOAD = 1mA 0 0.4 V
ILOAD = 15mA 0.8
1
V
Input pull-up current, I
IL
RESETZ
................................
.......
Other digital inputs
VIN=0V
10
10
-1
100
100
1
μA
μA
μA
Input pull down current, IIH
TEST
Other digital inputs
VIN=V3P3D
10
-1
100
1
μA
μA
1 Guaranteed by design; not produc tion te sted.
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
AUGUST 2011
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SUPPLY CURRENT
PARAMETER CONDITION MIN TYP MAX UNIT
V3P3A + V3P3D + VLCD current N or mal Ope ration,
V3P3A=V3P3D=VLCD=3.3V
CKMPU=614kHz
VBAT=3.6V
No flash memory write
6.4 9.5 mA
V3P3A current 3.7 4.3 mA
V3P3D current 2.5 4.8 mA
VLCD current
0.2
0.4
mA
VBAT current -300 300 nA
V3P3D current
Normal Ope ration,
V3P3A=V3P3D=VLCD=3.3V
VBAT=3. 6V, no flash memory
write
CKMPU=1,228kHz
CKMPU=2,456kHz
CKMPU=4,912kHz
2.9
3.6
5.1
mA
mA
mA
V3P3A + V3P3D current
Power sav e/sleep mode
V3P3A=V3P3D=VLCD=3.3V,
CE, ADC, E_TCLK, VREF dis-
abled
CKMPU=153.5kHz
CKMPU=38.4kHz
6
4.9
7
mA
mA
V3P3D current, Write Flash Norm al Oper ati on as above,
except write Flash at maximum
rate. 7 mA
VBAT current,
VBAT=3.6V
Battery backup,
≤
25°C
V3P3A=V3P3D=VLCD=0V
fOSC = 32kHz 85°C
2 4 μA
41 121 μA
1 Guaranteed by design; not production tested.
2.5V VOLTAGE REGULATOR
Unl ess oth erw is e sp ecif ied , l oad = 5mA
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
Voltage overhead V3P3-V2P5
Reduce V3P3 until V2P5
drops 200m V
440 mV
PSSR ∆V2P5/∆V3P3
RESETZ=1, iload=0
-3
+3
mV/V
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
SEPTEMBER 2011
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A Maxim Integrated Products Brand
VREF, VBIAS
Unl ess oth erw is e sp ecif ied , VREF_DIS=0
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
VREF output voltage, VNOM(25)
Ta = 22ºC
1.193
1.195
1.197
V
VREF chop st ep
40
mV
VREF output impe dance
VREF_CAL =1,
ILOAD = 10µA, -10µA
2.5 kΩ
VNOM definitionA
VNOM(T) = VREF(22) + (T–22)TC1 + (T–22)2TC2
V
-- If TRIMBGA and TRIMBGB avai labl e (6513H) --
VREF temp erature coef ficients
TC1 (linear)
TC2 (quad ratic)
TRIMBGA, TRIMBGB, TRIMM[2 : 0]: See
TRIMSEL, TRIM registers
x(33-0.28y ) + 0.33y + 7.9
x(0.02-0.0002y) – 0.46
where x = 0. 1TRIMBGB - 0.14(TRIMM[2:0]+0.5),
900
370000_500
2
_−−
=BGATRIM
NOMTEMP
y
µV/°C
µV/°C2
VREF(T) deviation from VNOM(T)
)40|,22max(| 10)()(
6
−
−
TVNOM TVNOMTVREF
-10 10 ppm/ºC
-- If TRIMBGA and TRIMBGB not a vaila ble (6513) --
VREF temp erature coef ficients
TC1 (linear)
TC2 (quad ratic)
7.0
-0.341
µV/ºC
µV/°C
2
VREF(T) deviation from VNOM(T)
)40|,22max(| 10)()( 6
−
−
TVNOM TVNOMTVREF
Ta = -40 ºC to +85ºC -401 +401 ppm/ºC
VREF aging Ta = 25ºC ±25
ppm/
year
VBIAS output vol tage
Ta = 25ºC
Ta = -40 ºC to 85ºC
(-1%)
(-2%)
1
1.5
1.5
1
(+1%)
(+2%)
1
V
V
VBIAS ou tpu t impe dance
ILOAD = 1mA, -1mA
240
500
Ω
A This relationship describes the nom inal behavior of VREF at different temperatures.
1 Guaranteed by design; not production tested.
CRYSTAL OSCILLATOR
Crystal is disconnecte d. Test load is series 200pF, 100kΩ connect ed between DGND and XOUT.
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
Maximum Output Power to Crystal4
Cry stal c onnected
1
μW
Xin to Xout Capacitanc e1
3
pF
Capacitance to DGND1
Xin
Xout
5
5
pF
pF
Watchdog RTC_OK threshold
25
kHz
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
AUGUST 2011
Page: 94 of 104 © 2005-2011 Teridian Semiconductor Corporation
A Maxim Integrated Products Brand
ADC CONVE RTER, VDD REFERENCED
FIR_LEN=0, VREF_DIS=0, VDDREFZ=0
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
Re commended Input Range
(Vin-V3P3A)
-250 250
mV
peak
Voltage to Current Crosstalk:
)cos(
*106VcrosstalkVin
Vin
Vcrosstalk ∠−∠
Vin = 200m V peak, 65Hz,
on VA, VB, or VC
Vcrosstalk = largest
measurement on IA, IB, o r
IC
-101 101 μV/V
THD (First 10 harmonics)
250mV- peak
20mV- peak
Vin=65Hz,
64kpts FFT, Blackman-
Harris window
-75
-90
dB
dB
Input Impedance
Vin=65Hz
40
90
kΩ
Temp erature c oefficient of Input
Impedance
Vin=65Hz 1.7 Ω/°C
LSB size
FIR_LEN=0
355
nV/LSB
Dig ital Full Scale
+884736
LSB
AD C G ain E r ro r v s
% Pow er S upply V ariation
3.3/33100 /357106
APV VnVNout INPK
∆
∆
Vin=200mV peak, 65Hz
V3P3A=3.0V , 3.6V 50 ppm/%
Inp ut Offs et (Vin-V3P3A)
-10
10
mV
1 Guaranteed by design; not production tested.
OPTICAL INTERFACE
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
OPT_TX VOH (V3P3D-OPT_TX)
ISOURCE=1mA
0.4
V
OPT_TX VOL
ISINK=20mA
0.7
V
OPT_RX Vin T hreshol d
(VinRISING+VinFALLING)/2
200 250 300 mV
OPT_RX Vin H ysteresis
(VinRISING-VinFALLING)
5 30 mV
OPT_RX input impedance
|Vin|≤300mV
1
MΩ
TEM PERAT URE SE NSOR
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
Nomi na l Sens itivity ( Sn)2
T
A
=25ºC, T
A
=75ºC
No minal relationship:
N(T)= Sn*T+Nn
-900
LSB/ºC
Nominal Offset (Nn) 2
40000
0
LSB
Temp erature E r ror1
n
SNTN
TERR ))25()((
)25( −
−−=
TA = -40ºC to +85ºC -31 31 ºC
1 Guaranteed by design; not production tested.
2 T hi s par amet er defines a nomi nal r elationsh i p ra ther than a mea sured par ameter. Corr ect circuit oper atio n i s v er if ied with
other specs t hat use t his nominal relati ons hip as a reference.
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
SEPTEMBER 2011
© 2005-2011 Teridian Semiconductor Corporation Page: 95 of 104
A Maxim Integrated Products Brand
LCD BOOST
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
VDRV Frequency
OSC/2
Hz
VDRV Si n k Curr ent
Vol=1.5V
1.2
2.75
mA
VD RV S ource Curr ent
Voh=1.5V
1.2
2.6
mA
VLCD Target Voltage
4.5
5.5
V
VLCD I nput Current
VLCD=5.0V,
LCD_FS=1F,
LCD_MODE=0,1,2,3
LCD_BSTEN=1
450 μA
LCD DRI V E RS
Appli es t o all COM and S EG pins. Unl ess oth erwise st ated, VL CD= 5. 0V, LCD_FS=1F
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
VLC0 Max Voltage (LCD_FS =1F)
With resp ect t o VLCD
-0.2
0
V
VLC0 Min Voltage (LCD_FS =00)
With resp ect t o VLCD*0. 7
-0.2
0.2
V
VLC1 Vol t age,
1/3 bias
½ bias
With resp ect t o 2* VLC D/3
With resp ect t o VLCD/2
-10
-10
+10
+10
%
%
VLC0 Vol t age,
1/3 bias
½ bias
With resp ect t o VLCD/3
With resp ect t o VLCD/2
-15
-10
+15
+10
%
%
Output Impe dance
∆ILOAD=10µA
30
kΩ
RTC
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
Range for date
2000
-
2255
year
RESETZ
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
Reset p ulse width
5
µs
Reset p ulse f all t ime
11
µs
1 Guaranteed by design; not production tested.
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
AUGUST 2011
Page: 96 of 104 © 2005-2011 Teridian Semiconductor Corporation
A Maxim Integrated Products Brand
COMPARATORS
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
Offset Voltage
V1-VBIAS
V2-VBIAS
V3-VBIAS
-20
-20
-20
15
15
15
mV
mV
mV
Hysteres is C urrent
V1
V2
V3
Vin = VBIAS - 100mV
0.8
0.8
0.8
1.2
1.2
1.2
μA
μA
μA
Response Tim e
V1
V2
V3
+100mV o ver drive
2
0.5
0.5
15
50
50
μs
μs
μs
WD Di sa ble T hr eshold (V1-V3P3A)
-400
-10
mV
RAM AND FLASH MEMORY
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
CE RAM wait states
CKMPU = 4.9MHz
5
Cycles
CKMPU = 1.25 MHz
2
Cycles
Flash w r it e cy cles
-40°C to +85°C
20,000
Cycles
Flash dat a retention
25°C
100
Years
Flash dat a retention
85°C
10
Years
Flash byte writes bet w een page or mas s
erase operations
2 Cycles
FLA S H MEM OR Y TIMING
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
Wri te Ti me per Byte
42
µs
Page Er ase (5 12 bytes)
20
ms
Mass Erase
200
ms
EEPROM INTERFACE
PARAMETER
CONDITION
MIN
TYP
MAX
UNIT
Wr i te C lock frequency
CKMPU=4.9MHz, Using
interrupts
78 kHz
CKMPU=4.9MHz, “bit -
banging” DIO4/5
150 kHz
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
SEPTEMBER 2011
© 2005-2011 Teridian Semiconductor Corporation Page: 97 of 104
A Maxim Integrated Products Brand
Recommen ded External Components
NAME FROM TO FUNCTION VALUE UNIT
C1 V3P3A AGND Bypass capaci tor for 3.3V supp ly ≥0.1±20% µF
C2 V3P3D DGND Bypass capaci tor for 3.3V supp ly ≥0.1±20% µF
XTAL XIN XOUT 32.7 6 8kHz cr yst al. Elect rically simil a r to ECS
ECX-3 TA series 32.768 kHz
CXS XIN AGND Load capaci tor for crystal (depends on crystal
specs and board parasit ics). 22±10% pF
CXL XOUT AGND 22±10% pF
CV1 V1 AGND Bypass capacitor for V1 ≥0.1±20% µF
CBIAS VBIAS AGND Bypass capacitor for VBIAS ≥1000±20% pF
CBST1 VDRV external Boost charging capac i tor 33±20% nF
CBST2 VLCD DGND B oost bypass capac i tor ≥0.22±20% µF
C2P5 V2P5 DGND Bypass capac itor for V2P5 ≥0.1±20% µF
RTST TEST DGND Resistor for TEST 10kΩ±10% µF
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
AUGUST 2011
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Packaging Informati on
100-Pin LQFP PACKAGE OUTLINE (Bottom View)
1
0.50(0.0197)TYP.
0.05(0.002)
0.15(0.006)
0.18(0.007)
0.27(0.011)
0.60(0.024) TYP.
13.8(0.543)
14.2(0.559)
15.7(0.618)
16.3(0.641)
15.7(0.618)
16.3(0.641)
1.40(0.055)
1.60(0.063)
Top View
Side View
Notes: Controlling dimensions are in mm.
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
SEPTEMBER 2011
© 2005-2011 Teridian Semiconductor Corporation Page: 99 of 104
A Maxim Integrated Products Brand
Pinout (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
63
62
61
60
59
58
57
56
55
54
53
52
51
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
VBIAS
E_TCLK
SEG33/DIO13
SEG32/DIO12
E_RST
VLCD
NC
XOUT
TEST
XIN
GNDA
NC
OPT_RX
V1
V2
V3
VREF
IA
IB
VA
VB
VC
V3P3A
GNDA
IC
GNDD
SEG14
SEG13
NC
SEG12
SEG11
NC
NC
NC
NC
SEG10
SEG9
SEG7/MUX_SYNC
SEG8
NC
SEG6/SRDY
SEG36/DIO16
NC
SEG35/DIO15
SEG34/DIO14
E_ISYNC/BRKRQ
SEG2
SEG1
SEG15
SEG0
GNDD
E_RXTX
OPT_TX
TMUXOUT
SEG37/DIO17
V3P3D
DIO_3
COM1
COM2
COM3
TX
SEG3/SCLK
VDRV
CKTEST
COM0
SEG4/SSDATA
SEG5/SFR
E_TBUS[3]
E_TBUS[2]
DIO_0
SEG38/DIO18
DIO_1
DIO_2
E_TBUS[0]
E_TBUS[1] SEG27/DIO7
SEG39/DIO19
SEG26/DIO6
SEG25/DIO5
SEG29/DIO9
RX
SEG31/DIO11
GNDD
RESETZ
V2P5
VBAT
SEG24/DIO4
SEG23
SEG22
SEG28/DIO8
SEG41/DIO21
SEG40/DIO20
NC
SEG19
SEG18
SEG17
SEG16
SEG30/DIO10
SEG20
SEG21
TERIDIAN
71M6513-IGT/71M6513H-IGT
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
AUGUST 2011
Page: 100 of 104 © 2005-2011 Teridian Semiconductor Corporation
A Maxim Integrated Products Brand
Pin Descri ptions
Power/Ground Pins
Name
Pin #
Type
Description
GNDA
76,91 P Analog ground: This pin should be connected dir ectly to the analog ground plane.
GNDD
1, 40, 75 P Digital ground: This pin should be connected directly to the digital ground plane.
V3P3A
77 P Analog power supply: A 3.3V analog power supply should be connected to this pi n.
V3P3D
9 P Digital power supply: A 3. 3V digital power supply should be connected to this pin.
VBAT 72 P
Battery backup power s upply. A battery or super -capacitor is to be connected between
VBAT and GNDD . If no batte ry is used, connect VBAT to V3P3D .
V2P5 73 O Outp ut of the 2. 5V regulato r . A 0.1µF c apacitor to G N DA s hould be connected t o thi s pin.
VLCD 96 P LCD power supply.
NC
32,33,36,
42,43,44,
47,55,90,95
-- No Connec t
Analog Pins
Name
Pin #
Type
Circuit
Description
IA
IB
IC
84
83
82
I 6
Line Current Sense Input s: These pins are voltage inputs to the internal A/ D con-
verter. Typically, they are connected to the out put of a curr ent transformer . Unused
pins m ust be connected to V3P3A.
VA
VB
VC
80
79
78
I 6
Line Vol tage Sense Inputs: These pins are volt age inputs to the internal A/ D con-
v erter . Ty picall y, they are c onnec ted t o th e output of a r esistor divider . Unused pins
must be connect e d to V3P3A.
V1
V2
V3
88
87
86 I 7
Com parator Inputs - voltage i nputs to the inter nal comparator: The vol tages applied
to t hese pins are c omp ar ed to VBIAS . If the voltage is above VBIAS, the corre-
sponding comparator output will be high (1). The out puts are maintained in the
COMP_STAT regist er. A typical application is to sense the v oltage on the DC supply
using an ex ternal resistor divider to sc al e the power supply voltage t o a level that
trigger s the comp arator at the desir ed v olta ge dr op.
V1: This pi n is part of t he r eset circ uitry. It also cont rols the hard ware watc hdog
timer. A 0.1µF capacitor to GNDA should be connecte d to this pin.
V2: Com par ator inpu t. If unused, t his pin m ust be connected to V3P3A or
ground.
V3: C o mpa ra tor inpu t, also available to the ADC during alternative multiplexer
cycles. If not used for measuring or sensing purposes, t he V3 pin should either
be left unconnect ed or be connected to the VREF pi n. See pr ecautions on page
88.
VBIAS 81 O 9
Reference volt age used by t he power fault detection cir cuit. A 1, 000pF capacitor to
GND shou ld be connecte d to this pin.
VREF 85 I/O 9
Volta ge Refer ence for t he AD C. A 0.1µF capacitor to GNDA should be connected to
thi s pin.
XIN,
XOUT 92
94 I 8
Crystal I nputs: A 32kHz style crystal should be connect ed ac ross these pins.
Typica l ly, a 22-27pF capacit or is also connec ted f r om ea ch pi n t o G NDA . See cry s ta l
manufacturer datasheet for details.
VDRV 7 O 4 Voltage boost output.
Pi n ty p es: P = Po wer, O = Output , I = I nput, I/ O = I nput/Output
The circuit num ber denotes the equivalent circuit, as specified under “I/O Equivalent Circuits”.
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
SEPTEMBER 2011
© 2005-2011 Teridian Semiconductor Corporation Page: 101 of 104
A Maxim Integrated Products Brand
Di gital Pins
Name
Pin #
Type
Circuit
Description
DIO_3,
DIO_2,
DIO_1,
DIO_0
21
20
19
18
I/O 3, 4 Di gital input/output pins 0 through 3. If unused, these DIO pins must be
configured as outputs or terminated to V3P3 or gr ound.
COM3,
COM2,
COM1,
COM0
25
24
23
22
O 5 LCD Common O utput s: T hese 4 pins provide the select signal s for the
LCD dis p lay .
SEG0…SEG2,
SEG8…SEG23
See
pinout O 5 Dedicated LCD Segm ent O utput.
SEG24/DIO4…
…….
SEG41/DIO21
See
pinout I/O 3 , 4, 5
Multi-use p ins, c onfig ura ble as ei th er L CD SEG dri ver or DIO (D IO 4 =
SCK, DI O5 = SDA when configured as EEPROM I/F, WPULSE = DIO6,
VARPULSE = DIO7 when configured as pulse out puts). If unused, these
pins m ust be configured as outputs or terminated t o V3P3 /ground.
SEG7/MUX_SYNC 37 O 4, 5
Multi-use-pin LCD Segment Out put/ MUX_SYNC i s output for Synchron-
ous serial interface
SEG6/SRDY 35 I/O 2, 5
Multi-use-pin, LCD Segment Outputs/ SRDY input for Synchronous ser ial
interface. If u nused, this pin must be t erminate d to ground.
SEG5/SFR
11
O
4, 5
Multi-use-pin, LCD Segment Output/ SFR output for SSI.
SEG4/SDATA
10
O
4, 5
Multi-use-pin, LCD Segment Output/ SDATA output for SSI.
SEG3/SCLK
6
O
4, 5
Multi-use-pin, LCD Segment Output/ SCLK output for SSI.
RESETZ 74 I 1
This pi n is used to reset th e chip into a k nown st ate. For n or m al oper atio n,
thi s pin is s et to 1. To r eset t he chip, this pin is dr iven t o 0. This p in has an
internal 30μA (nominal) current source pull-up but no Schmitt-trigger
circuitry. The minimum width of the pulse is 5μs. A 0.1µF capacitor to
GNDA s hould be connected to this pin. Since the chip resets its elf at
power-up, no other exter nal r eset circuitry is required.
RX 71 I 3
UART input. The voltage appli ed at t his input must be below 3.6V. I f u n -
used, the RX pi n must be terminated to V3P3 or gr ound.
TX
5
O
4
UART output.
OPT_RX 89 I 7
Opt ical Receive In put: T his p in r eceives a signal fr om an ext er nal phot o-
detect or used in an I R ser ial interfa ce. I f u nused, the OPT_R X pin must
be terminated to V3P3 or ground.
OPT_TX 3 O 4
Optical LED Transmit Output: This pin is designed to directly drive an LED
for t ra nsm itting data i n an I R ser ial inter face. C an b e t ristat ed with
OPT_TXDIS to be m ult iplex ed with ot her DIO pin s .
CKTEST
8
O
4
Clock PLL output. Can be enabled and disabled by CKOUT_EN.
TMUXOUT 4 O 4 Dig i tal ou tpu t t est mult iplex er. Co ntrolled by TMUX[3:0].
E_RXTX
2
I/O
1, 4
Emulator ser ial dat a.
E_TBUS[3]
E_TBUS[2]
E_TBUS[1]
E_TBUS[0]
12
13
14
15
O 4 Emulator tr ac e bus. These pins have int ernal pull-up res istors.
E_ISYNC/BRKRQ
29
I/O
1, 4
Em ulat or handshake. Th is pin h as an internal p ull-up resistor.
E_TCLK
100
O
4
Emulator clo ck. This pin h as a n inter nal pul l-up resistor.
E_RST
97
I/O
1, 4
Emulator res et. This pin h as a n inter nal pul l-up resistor.
TEST
93
I
7
For Teridian inter nal use. Must be c onnec t ed to G NDD via a 10kΩ resistor.
Pi n ty p es: P = Po wer, O = Output , I = I nput, I/ O = I nput/Output
The circuit num ber denotes the equivalent circuit, as specified under “I/O Equivalent Circuits”.
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
AUGUST 2011
Page: 102 of 104 © 2005-2011 Teridian Semiconductor Corporation
A Maxim Integrated Products Brand
I/O Equivalent Circuits:
Oscillator Equivalent Circuit
Type 8:
Oscillator I/O
Digital Input Equivalent Circuit
Type 1:
Standard Digital Input or
pin configured as DIO Input
with Internal Pull-Up
GNDD
110K
V3P3D
CMOS
Input
V3P3D
Digital
Input
Pin
Digital Input
Type 2:
Pin configured as DIO Input
with Internal Pull-Down
GNDD
110K
GNDD
CMOS
Input
V3P3D
Digital
Input
Pin
Digital Input Type 3:
Standard Digital Input or
pin configured as DIO Input
GNDD
CMOS
Input
V3P3D
Digital
Input
Pin
CMOS
Output
GNDD
V3P3D
GNDD
V3P3D
Digital Output Equivalent Circuit
Type 4:
Standard Digital Output or
pin configured as DIO Output
Digital
Output
Pin
LCD Output Equivalent Circuit
Type 5:
LCD SEG or
pin configured as LCD SEG
LCD
Driver
GNDD
LCD SEG
Output
Pin
To
MUX
GNDA
V3P3A
Analog Input Equivalent Circuit
Typ e 6:
ADC Input
Analog
Input
Pin
Comparator Input Equivalent
Circuit Type 7:
Comparator Input
GNDA
V3P3A
To
Comparator
Comparator
Input
Pin
To
Oscillator
GNDD
V3P3D
Oscillator
Pin
VREF Equivalent Circuit
Type 9:
VREF
from
internal
reference
GNDA
V3P3A
VREF
Pin
V2P5 Equi valent Circuit
Type 10:
V2P5
from
internal
reference
GNDD
V3P3D
V2P5
Pin
VLCD Equivalent Circuit
Type 11:
VLCD Power
GNDD
LCD
Drivers
VLCD
Pin
VBAT Equivalent Circuit
Type 12:
VBAT Power
GNDD
Power
Down
Circuits
VBAT
Pin
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
SEPTEMBER 2011
© 2005-2011 Teridian Semiconductor Corporation Page: 103 of 104
A Maxim Integrated Products Brand
ORDERING INFORMATION
PART DESCRI P TION ORDERING
NUMBER PACKAGE
MARKING
71M6513
100-pin lead-free LQFP, 0.5% accuracy 71M6513-IGT/F 71M6513-IGT
71M6513
100-pin l ead-free LQF P, 0.5% accuracy, T&R 71M6513-IGTR/F 71M6513-IGT
71M6513H
100-pin lead-free LQFP, 0.1% accuracy 71M6513H-IGT/F 71M6513H-IGT
71M6513H
100-pin lead-fr ee LQ FP, 0.1% ac cur ac y, T&R 71M6513H-IGTR/F 71M6513H-IGT
Revision History
Revision Date Description
2.0
11/23/2005
Initial release
2.1
11/30/2005
Updated Electrical Specification (TC1/TC2, fuse descriptions)
2.2 4/17/2006
Improved MPU register (SFR) descripti on. Added information in Electrical
Specifications (ADC resolution 355nV/LSB with FIR_LEN=0 , formula for
tem per at ure c oefficients , 38 kHz MPU cl ock, VREF aging information, current
consumption in low-power mode, rem oved note on ADC count [3.589, 461 * 600 *
7.8E-9 = 169V]). Improved CE d escri pti on ( adde d X to pulse rate formula,
TEMP_NOM default value, APULSER and APULSEW u pdate by MPU, rel ation
betw een ADC cy cles and MUX_DIV. Added not es and clarifications on flash
write oper ations. Added i nformation in Applications sect ion on connection of V3,
crystal freque ncy variations and frequency measurement . Improved figures 4 and
5. Added cauti on notes for timing re quire d for SW W DT and for conditions
blocking interrupt proce ssing. Added note in pin des cripti ons on connect i on of V3.
2.3 3/14/2007
Added I/O Equi v alent Ci rcuits and i nter rupt structure diagram. Added note in CE
Secti on stating that CE STATUS word must be r ead right after the CE_BUSY
interru pt. Del eted FL SH_TMR from lis t of pins i n Logic L evels. Updated Tabl e 51
(DIO pins) and Fi gur e 11. Changed capacit or value for XIN/XOUT in Pin
Descri ptions and i n Recommended Exter nal Components. Added items in
Electrical Specification (tem per atur e ra nge f or maximum wri te cycles, flash
r etent io n time f or +8 5°C , maximum number of writ es in betw een f lash era se
operations). Ad ded not e in P i n Descr iptions on external reset circuitry. Added
cautionary notes for ECK_DIS and SECURE bits. A dde d re quirements for termination
in pin tables fo r DI O_0-DIO_3, DIO/SEG, RX, OPT_RX pi ns. Added expl anat ion
of SRDY polarity.
71M6513/71M6513H
3-Phase Energy Meter IC
DATA SHEET
AUGUST 2011
Page: 104 of 104 © 2005-2011 Teridian Semiconductor Corporation
A Maxim Integrated Products Brand
Revisi on History (Contin ued)
Revision
Date
Description
2.4 8/17/2007
Removed all references to ROM versions. R emo ved refer ence to 3rd UART in
“ Hard w are O ver view” u sing bi t-bang te chnique. Added note stating that “bit-
banging” of DIO4/5 is discouraged. Added “A 1,000pF capacitor to GND should
be connected to this pin” f or VBIAS in Analog Pi n Desc r iptions. Added precauti on
regarding I /O RAM l ocations aff ected by flash write under “Flash Memory”. Added
remark in “MPU/CE Co mmunic ation ” on inaccuracy of accu mulation interval as
c ompared to R TC. M odified C E Inter face description. Changed in Electrical Spe-
cifications: TC1 to +7.0 (VREF section), recommended capacitor values for
XIN/XOUT and crystal type. Correcte d diagra m for Rogow ski coil (Figure 30) .
Fixed Table 56.
2.5 8/12/2008
Updated package information from IEL (exposed pad LQFP) to IGT/F package
type (title page, package drawing, and orderi ng information). Updated Teridian
street address information. Updat ed explanat ion for V3SQSUM register in CE
Interfa ce Descri ption.
Added r evision his tory table to repl ace sep ar ate revisio n notes.
2.6 12/10
Changed information on Wh accur acy on title page. Added section on del ay
c ompens ation i n C E Descr iption. Cor rec ted UAR T descr ipt ion i n M PU sect io n.
Added cautionary note in CE Progr am and Environm ent section stating that
operating CE code wi th en vironmental settings other than those specified in the
data sheet will lead to unpr edictable results. Deleted graphs showing ty pical
performance over temperature. Added crystal oscillator information in Application
Informa t ion sectio n. Added note in Applications section stating that high source
impedance sensor circuits should be avoided.
Clarified “gua ranteed by de sign” and “tested in production ” inf or mation in
Electrical Specifications section.
Changed font for all SFR and I /O RAM r egister v ariables to Times New R oman
Italic.
Corrected various typos.
3 9/11
Added the following:
- Changed “50ppm/°C” to “40ppm/°C” ( page 1).
- Explanation of scaling factors appli ed to PPMC and PPMC2 (page 73).
- Explanation of er r or bands for temperature compensat ion (page 82).
- Precautionary notes regarding t he voltage range of the V3 pin (page 88).
- Precautionary notes for connecti ng a battery (page 88).