1/40August 2005
M25P20
2 Mbit, Low Voltage, Serial Flash Memory
With 40MHz SPI Bus Interface
FEATURES SUMMARY
■2 Mbit of Flash Me m o ry
■Page Program (up to 256 Bytes) in 1.4ms
(typical)
■Sector Erase (512 Kbit) in 1s (typical)
■Bulk Erase (2 Mbit) in 3s (typ ical)
■2.7 to 3.6V Single Supply Voltage
■SPI Bus Compatible Serial Interface
■40MHz Clock Rate (maximum)
■Deep Power-down Mode 1µA (typical)
■Electronic Signature (11h)
Figure 1. Pack ag e s
SO8 (MN)
150 mil width
8
1
VDFPN8 (MP)
(MLP8)
M25P20
2/40
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Data Output (Q). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Data Input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Write Protect (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
SPI MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
OPERATING FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Page Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Polling During a Write, Program or Erase Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Active Power, Standby Power and Deep Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Hold Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
MEMORY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Write Disable (WRDI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Read Status Register (RDSR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
WIP bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
SRWD bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Read Data Bytes (READ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Read Data Bytes at Higher Speed (FAST_READ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Deep Power-down (DP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3/40
M25P20
Release from Deep Power-down and Read Electronic Signature (RES) . . . . . . . . . . . . . . . . . 23
POWER-UP AND POWER-DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
M25P20
4/40
SUMMARY DESCRIPTION
The M25P20 is a 2 Mbit (256K x 8) Serial Flash
Memory, with advanced write protection mecha-
nisms, accessed by a high speed SPI-compatible
bus.
The memory can be programmed 1 to 256 bytes at
a time, using the Page Program instruction.
The memory is organized as 4 sectors, each con-
taining 256 pages. Each page is 256 bytes wide.
Thus, the whole memory can be viewed as con-
sisting of 1024 pages, or 262,144 bytes.
The whole memory can be erased using the Bulk
Erase instruction, or a sector at a time, using the
Sector Erase instruction.
Figure 2. Logic Diagram
Figure 3. SO and VDFPN Connections
Note: 1. There is an exposed die pad dle on the undersi de of the
MLP8 package. This is pulled, internally, to VSS, and
must not be al lowed to be connecte d to any oth er voltage
or signal li ne on the PCB.
2. See PACKAGE MECHANICAL section for package di-
mensions, and how to identify pin-1.
Table 1. Signal Names
AI04080
S
VCC
M25P20
HOLD
VSS
W
Q
C
D
1
AI04081B
2
3
4
8
7
6
5DVSS C
HOLDQ
SV
CC
W
M25P20
C Serial Clock
D Serial Data Input
Q Serial Data Output
SChip Select
W Write Protect
HOLD Hold
VCC Supply Voltage
VSS Ground
5/40
M25P20
SIGNAL DESCRIPTION
Serial Data Output (Q). This output signal is
used to transfer data serially out of the device.
Data is shifted out on the falling edge of Serial
Clock (C).
Serial Data Input (D). This input signal is used to
transfer data ser ially into the device. It rece ives in-
structions, addresses, and the data to be pro-
grammed. Values a re latched on the rising e dge of
Serial Clock (C).
Serial Clock (C). This input signal provides the
timing of the serial interface. Instructions, address-
es, or data present at Serial Data Input (D) are
latched on the rising edge of Serial Clock (C). Data
on Serial Data Output (Q) changes after the falling
edge of Serial Clock (C).
Chip Select (S). When this input signal is High,
the device is deselected and Serial Data Output
(Q) is at high impedance. Unless an internal Pro-
gram, Erase or Write Status Register cycle is in
progress, the device will be in the Standby mode
(this is not the Deep Power-down mode). Driving
Chip Select (S) Low selects the device, placing it
in the Active Power mode.
After Power-up, a falling edge on Chip Select (S)
is required prior to the start of any instruction.
Hold (HOLD). The Hold (HOLD) signal is used to
pause any serial communications with the device
without deselectin g the device.
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be se-
lected, with Chip Select (S) driven Low.
Write Protect (W). The main purpose of this in-
put signal is to fr eeze the size of the a rea of mem-
ory that is protected against program or erase
instructions (as specified by the values in the BP1
and BP0 bits of th e Status Register ).
M25P20
6/40
SPI MODES
These de vices can be driv en by a micro controller
with its SPI peripheral running in either of the two
following modes:
– CPOL=0, CPHA=0
– CPOL=1, CPHA=1
For these two modes, input data is latched in on
the rising edge of Serial Clock (C), and output data
is available from the falling edge of Serial Clock
(C).
The difference bet ween th e two mod es, as shown
in Figure 5., is the clock polarity when the bus
master is in Stand-by mode and not transferring
data:
– C remains at 0 for (CPOL=0, CPHA=0)
– C remains at 1 for (CPOL=1, CPHA=1)
Figure 4. Bus Master and Memory Device s on the SPI Bus
Note: The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
Figure 5. SPI Modes Supported
AI03746D
Bus Master
(ST6, ST7, ST9,
ST10, Others) SPI Memory
Device
SDO
SDI
SCK
CQD
S
SPI Memory
Device
CQD
S
SPI Memory
Device
CQD
S
CS3 CS2 CS1
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
WHOLD WHOLD WHOLD
AI01438B
C
MSB
CPHA
D
0
1
CPOL
0
1
Q
C
MSB
7/40
M25P20
OPERATING FEATURES
Page Programming
To program one data byte , two instructions are re -
quired: Write Enable (WREN), which is one byte,
and a Page Program (PP) sequence, which con-
sists of four bytes plus data. This is followed by the
internal Program cycle (of duration tPP).
To spread this overhead, the Page Program (PP)
instruction allows up to 256 bytes to be pro-
grammed at a time (changing bits from 1 to 0), pro-
vided that they lie in consecutive addresses on the
same page of memory.
For optimized timings, it is recommended to use
the Page Program (PP) instruction to program all
consecutive targeted Bytes in a single sequence
versus using several Page Program (PP) se-
quences with each containing only a few Bytes
(see Page Program (PP), Instruction Times (De-
vice Grade 6) and Instruction Times (Device
Grade 3)).
Sector Erase and Bulk Erase
The Page Program (PP) instruction allows bits to
be reset from 1 to 0. Before this can be applied, the
bytes of memory need to have been erased to all
1s (FFh). This can be achieved eit her a sector at a
time, using the Sector Erase (SE) instruction, or
throughout the entire memory, using the Bulk
Erase (BE) instruction. This starts an internal
Erase cycle (of duration tSE or tBE).
The Erase instruction must be preceded by a Write
Enable (WREN) instruction.
Polling During a Write, Progra m or Erase Cycle
A further imp rovement in the time to Write Status
Register (WRSR), Program (PP) or Erase (SE or
BE) can be achieved by not waiting for the worst
case delay (tW, tPP, tSE, or tBE). The Write In
Progress (WIP) b it is provided in the Status Re gis-
ter so that the application program can monitor its
value, polling it to establish when the previous
Write cycle, Program cycle or Erase cycle is com-
plete.
Active Power, Standby Power and Deep
Power-Down Modes
When Chip Select (S) is Low, the device is select-
ed, and in the Active Power mode.
When Chip Select (S) is High, the device is dese-
lected, but could r emain in the Active Power mode
until all internal cycles have completed (Program,
Erase, Write Status Register). The device then
goes in to the Standby Power mode. The device
consumption drops t o ICC1.
The Deep Power-down mode is entered whe n the
specific instruction (the Deep Power-down (DP) in-
struction) is executed. The device consumption
drops further to ICC2. The device remains in this
mode until another specific instruction (the Re-
lease from De ep Powe r-down a nd Re ad Electro n-
ic Signature (RES) instruction ) is executed.
All other instructions are ignored while the device
is in the Deep Power-down mode. This can be
used as an extra software protection mechanism,
when the device is not in a ctive use , to pro tect the
device from inadvertent Write, Program or Erase
instructions.
Status Regist er
The Status Register contains a number of status
and control bits, as shown in Table 5., that can be
read or set (as appropriate) by specific instruc-
tions.
WIP bit. The Write In Progress (WIP) bit indicat es
whether the memory is busy with a Write Status
Register, Program or Erase cycle.
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status o f the internal Write Enable Lat ch.
BP1, BP0 bits. The Block Protect (BP1, BP0) bits
are non-volatile. They define the size of the area to
be software p rotected against Prog ram and Erase
instructions.
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected mode. In this mode, the non-volatile bit s
of the Status Register (SRWD, BP1, BP0) become
read-only bits.
M25P20
8/40
Protection Modes
The environments where non-vola tile memory de-
vices are used can be very noisy. No SPI device
can operate correc tly in the presence of excessive
noise. To help combat this, the M25P20 features
the following data protection mechanisms:
■Power On Reset and an internal timer (tPUW)
can provide protection ag ainst inadvertant
changes while the power supply is outside the
operating specification.
■Program, Erase and Write Status Register
instructions are checked t hat they consist of a
number of clock pulses that is a multiple of
eight, before they are accepted for execution.
■All instructions that modify data must be
preceded by a Write Enable (WREN)
instruction to set t he Write Enable Latch
(WEL) bit. This bit is returned to its reset state
by the following events:
– Power-up
– Write Disable (WRDI) instruction
completion
– Write Status Register ( WRSR) instru ction
completion
– Page Program (PP) instruction completion
– Sector Erase (SE) instruction completion
– Bulk Erase (BE) instruction completion
■The Block Protect (BP1, BP0) bits allow part of
the memory to be configured as read-only.
This is the Software Protected Mode (SPM).
■The Write Protect (W) signal, in co-operation
with the Status Register Write Disable
(SRWD) bit, allows the Block Protect (BP1,
BP0) bits and Status Register Write Disable
(SRWD) bit to be write-protected. This is the
Hardware Protected Mode (HPM).
■In addition to the low power consumption
feature, the Deep Power-down mode offers
extra software prot ection from inadvertant
Write, Program and Erase instructions, as all
instructions are ignored except one par ticular
instruction (the Release from Deep Power-
down instruction).
Table 2. Protected Area Sizes
Note: 1. The device is ready to accept a Bulk Erase instruction if, and only if, both Block Protect (BP1, BP0) are 0.
Status Register
Content Memory Content
BP1 Bit BP0 Bit Protected Area Unprotected Area
0 0 none All sectors1 (four sectors: 0, 1, 2 and 3)
0 1 Upper quarter (Sector 3) Lower three-quarters (three sectors: 0 to 2)
1 0 Upper half (two sectors: 2 and 3) Lower half (Sectors 0 and 1)
1 1 All sectors (four sectors: 0, 1, 2 and 3) none
9/40
M25P20
Hold Condition
The Hold (HOLD) signal is used to pause any se-
rial communications with the device without reset-
ting the clocking sequence. However, taking this
signal Low does not terminate any Write Status
Register, Pr ogram or Erase cycle that is cu rrently
in progress.
To enter the Hold condition, the device must be
selected, with Chip Select (S) Lo w.
The Hold condition star ts on the fall ing edge of the
Hold (HOLD) signal, provided that this coincides
with Serial C lock (C) b eing Low (as shown in Fig-
ure 6.).
The Hold condition ends on the rising edge of the
Hold (HOLD) signal, provided that this coincides
with Serial Clock (C) being Low.
If the falling edge does not coincide with Serial
Clock (C) being Low, the Hold condition starts af-
ter Serial Clock (C) next goes Low. Similarly, if the
rising edge does not coincide with Serial Clock (C)
being Low, the Hold condition ends after Serial
Clock (C) next goes Low. (T his is shown in Figure
6.).
During the Hold condition, the Serial Data Output
(Q) is high impedance, and Serial Data Input (D)
and Serial Clock (C) are Don’t Care.
Normally, the device is kept selected, with Chip
Select (S) driven Low, f or the whole duration of t he
Hold condition. This is to ensure that the state of
the internal log ic remains unchanged from t he mo-
ment of entering the Hold condition.
If Chip Select (S) goes H igh while the devic e is in
the Hold condition, this has the effect of resetting
the internal logic of the device. To restart commu-
nication with the device, it is necessary to drive
Hold (HOLD) High, and then to drive Chip Select
(S) Low. This prevents the d evice from going back
to the Hold condition.
Figure 6. Hold Condit ion Activation
AI02029D
HOLD
C
Hold
Condition
(standard use)
Hold
Condition
(non-standard use)
M25P20
10/40
MEMORY ORGANIZATION
The memory is organized as:
■262,144 bytes (8 bits each)
■4 sectors (512 Kbits, 65536 bytes each)
■1024 pages (256 bytes each).
Each page can be individually programmed (bits
are programmed from 1 to 0). The device is Sector
or Bulk Erasable (bits are erased from 0 to 1) but
not Page Erasable.
Table 3. Memory Organizatio n
Figure 7. Block Diagram
Sector Address Range
3 30000h 3FFFFh
2 20000h 2FFFFh
1 10000h 1FFFFh
0 00000h 0FFFFh
AI04079
HOLD
S
WControl Logic High Voltage
Generator
I/O Shift Register
Address Register
and Counter 256 Byte
Data Buffer
256 Bytes (Page Size)
X Decoder
Y Decoder
C
D
Q
Status
Register
00000h
10000h
20000h
30000h
3FFFFh
000FFh
Size of the
read-only
memory area
11/40
M25P20
INSTRUCTIONS
All instructions, addresses and data are shifted in
and out of the device, most significa n t bit first.
Serial Data Input (D) is sampled on the first rising
edge of Serial Clock (C) after Chip Select (S) is
driven Low. Then, the one-byte instruction code
must be shifted in to the device, most significant bit
first, on Serial Data Input (D), each bit being
latched on the rising edges of Serial Clock (C).
The instruction set is listed in Table 4..
Every instruc tion sequence star ts with a one-byte
instruction code. Depending on the instruction,
this might be followed by address bytes, or by data
bytes, or by both or none. Ch ip Select ( S) must be
driven High after the last bit of the instruction se-
quence has been shifted in.
In the case of a Read Data Bytes (READ), Read
Data Bytes at Higher Speed (Fast_Read), Read
Status Register (RDSR) or Release from Deep
Power-down, and Read Electronic Signature
(RES) instruction, the shifted-in instruction se-
quence is followed by a data-out sequence. Chip
Select (S) can be driven High after any bit of the
data-out sequence is being shifted out.
In the case of a Page Program (PP), Sector Erase
(SE), Bulk Erase (BE), Write Status Register
(WRSR), Write Enable (WREN), Write Disable
(WRDI) or Deep Power-down (DP) instruction,
Chip Select (S) must be driven High exactly at a
byte boundary, otherwise the instruction is reject-
ed, and is not executed. That is, Chip Select (S)
must driven High when the number of clock pulses
after Chip Select (S) being driven Low is an exact
multiple of eight.
All attempts to ac cess the memory arr ay during a
Write Status Register cycle, Program cycle or
Erase cycle are ignored, and the internal Write
Status Register cycle, Program cycle or Erase cy-
cle continues unaffected.
Table 4. Instruction Set
Instruction Description One-byte Instruction Code Address
Bytes Dummy
Bytes Data
Bytes
WREN Write Enable 0000 0110 06h 0 0 0
WRDI Write Disable 0000 0100 04h 0 0 0
RDSR Read Status Register 0000 0101 05h 0 0 1 to ∞
WRSR Write Status Register 0000 0001 01h 0 0 1
READ Read Data Bytes 0000 0011 03h 3 0 1 to ∞
FAST_READ Read Data Bytes at Higher Speed 0000 1011 0Bh 3 1 1 to ∞
PP Page Program 0000 0010 02h 3 0 1 to 256
SE Sector Erase 1101 1000 D8h 3 0 0
BE Bulk Erase 1100 0111 C7h 0 0 0
DP Deep Power-down 1011 1001 B9h 0 0 0
RES Release from Deep Power-down,
and Read Electronic Signature 1010 1011 ABh 0 3 1 to ∞
Release from Deep Power-down 0 0 0
M25P20
12/40
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 8.)
sets the Write Enable La tch (WEL) bit.
The Write Enable La tch ( WEL) bit must be set pri-
or to every Page Program (PP), Sector Erase
(SE), Bulk Erase (BE) and Write Status Register
(WRSR) instruction.
The Write Enable (WREN) instruction is entered
by driving Chip Select (S) Low, sending the in-
struction code, and then driving Chip Select (S)
High.
Figure 8. Write Enable (WREN) Instruction Sequence
Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 9.)
resets the Write Enable Latch (WEL) bit.
The Write Disable (WRDI) instruction is entered by
driving Chip Select (S) Low, sending the instruc-
tion code, and th en driving Chip Select (S) High.
The Write Enable Latch (WEL) bit is reset under
the following conditions:
–Power-up
– Write Disable (WRDI) instruction completion
– Write Status Register (WRSR) instruction
completion
– Page Program (PP) instruction completion
– Sector Erase (SE) instruction completion
– Bulk Erase (BE) instruction completion
Figure 9. Write Disable (WRDI) Instruction Sequence
C
D
AI02281E
S
Q
21 34567
High Impedance
0
Instruction
C
D
AI03750D
S
Q
21 34567
High Impedance
0
Instruction
13/40
M25P20
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction al-
lows the Status Register to be read. The Status
Register may be read at any time, even while a
Program, Erase or Write Status Register cycle is in
progress. When one of these cycles is in progress,
it is recommended to check the Write In Progress
(WIP) bit before sending a new instruction to the
device. It is also possible to read the Status Reg-
ister continuously, as shown in Figure 10..
Table 5. Status Register Format
The status and control bits of the St atus Register
are as follows:
WIP bit. The Write In Progress (WIP) bit indicates
whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1,
such a cycle is in progress, when reset to 0 no
such cycle is in progress.
WEL bit. The Write Enable Latch (WEL) bit indi-
cates the status o f the internal Write Enable Lat ch.
When set to 1 the internal Write Enable Latch is
set, when set to 0 the internal Write Enable Latch
is reset and no Write Status Register, Program or
Erase instruct ion is acce pt ed .
BP1, BP0 bits. The Block Protect (BP1, BP0) bits
are non-volatile. They define the size of the area to
be software p rotected against Prog ram and Erase
instructions. These bits are written with the Write
Status Register (WRSR) instruction. When one or
both of the Block Protect (BP1, BP0) bits is set to
1, the relevant memory area (as defined in Table
2.) becomes protected against Page Program
(PP) and Sector Erase (SE) instructions. The
Block Protect (BP1, BP0) bits can be written pro-
vided that the Hardware Protected mode has not
been set. The Bulk Erase (BE) instruction is exe-
cuted if, and only if, both Block Pro tect (BP1, BP0)
bits are 0.
SRWD bit. The Status Register Write Disable
(SRWD) bit is operated in conjunction with the
Write Protect (W) signal. The Status Register
Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware
Protected mode (when the Status Register Write
Disable (SRWD) bit is set to 1, and Write P rotect
(W) is driven Low). In this mode, the non-volatile
bits of the Stat us Re gister (SRWD, BP1, BP0 ) b e-
come read-only bits and th e Write Sta tus Register
(WRSR) instruction is no longer accept ed for exe-
cution.
Figure 10. Read Status Register (RDSR) Instruction Se quence and Data-Out Sequence
b7 b0
SRWD 0 0 0 BP1 BP0 WEL WIP
Status Register Write Protect
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit
C
D
S
21 3456789101112131415
Instruction
0
AI02031E
Q76543210
Status Register Out
High Impedance
MSB
76543210
Status Register Out
MSB
7
M25P20
14/40
Write Status Regi st e r (WR SR)
The Write Status Register (WRSR) instruction al-
lows new values to be written to the Status Regis-
ter. Before it can be accepted, a Write Enable
(WREN) instruction must previously have been ex-
ecuted. After the Write Enable (WREN) instruction
has been decoded and executed, the device sets
the Write Enable Lat ch (WEL).
The Write Status Register (WRSR) instruction is
entered by driving Chip Select (S) Low, followed
by the instruction code and th e data byte on Serial
Data Input (D ) .
The instruction sequence is shown in Figure 11..
The Write Status Register (WRSR) instruction has
no effect on b6, b5, b4, b1 and b0 of the Status
Register. b6, b5 and b4 are always read as 0.
Chip Select (S) must be driven High after the
eighth bit of the data byte has been latched in. If
not, the Write Status Register (WRSR) instruction
is not executed. As soon as Chip Select (S ) is driv-
en High, the self-timed Write Status Register cycle
(whose du ration is tW) is initiated. While the Write
Status Register cycle is in progress, the Status
Register may still be read to check the value of the
Write In Progress (WIP) bit . The Write In Progr ess
(WIP) bit is 1 during the self-timed Write Status
Register cycle, and is 0 when it is completed. At
some unspecified time before the cycle is complet-
ed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction al-
lows the user to change the values of the Block
Protect (BP1, BP0) bits, to define the size of the
area that is to be treated as read-only, as defined
in Table 2.. The Write St at us Regi ster ( WRSR) in-
struction also allows the user to set or reset the
Status Register Write Disable (SRWD) bit in ac-
cordance with the Write Protect (W) signal. The
Status Register Write Disable (SRWD) bit and
Write Protect (W) signal allow the d evice to be p ut
in the Hardware Protected Mode (HPM). The Write
Status Register (WRSR) instruction is not execut-
ed once the Hardware Protected Mode (HPM) is
entered.
Figure 11. Write Status Register (WRSR) Instruction Sequence
C
D
AI02282D
S
Q
21 3456789101112131415
High Impedance
Instruction Status
Register In
0
765432 0
1
MSB
15/40
M25P20
Table 6. Protection Modes
Note: 1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 2..
The protection features of the device are summa-
rized in Table 6..
When the Status Register Write Disable (SRWD)
bit of the Status Register is 0 (its initial delivery
state), it is possible to write to the Status Register
provided that the Write Enable Latch (WEL) bit has
previously been set by a Write Enable (WREN) in-
struction, regardless of the whether Write Protect
(W) is driven High or Low.
When the Status Register Write Disable (SRWD)
bit of the Status Register is set to 1, two cases
need to be considered, depending on the state of
Write Protect (W):
– If Write Protect (W) is driven High, it is
possible to write to the Status Register
provided that the Write Enable Latch (WEL) bit
has previously bee n se t by a Writ e Ena b le
(WREN) instruction.
– If Write Protect (W) is driven Low, it is not
possible to writ e to the Status Regist er even if
the Write Enable La tc h (WEL ) bit has
previously been set by a Write Enable
(WREN) instruction. (Attempts to write to the
Status Register are rejected, and are not
accepted for execution). As a consequence,
all the data bytes in the memor y area that are
software protected (SPM) by the Block Protect
(BP1, BP0) bits of the Status Register, are
also hardware protected against data
modification.
Regardless of the order of the two events, the
Hardware Protected Mode (HPM) can be entered:
– by setting the Status Register Write Disable
(SRWD) bit after driving Write Protect (W) Low
– or by driving Write Protect ( W) Low after
setting the Status Register Write Disable
(SRWD) bit.
The only way to exit the Hardware Protected Mode
(HPM) once entered is to pull Write Protect (W)
High.
If Write Protect (W) is permanently tied High, the
Hardware Protected Mode (HPM) can never be
activated, and only the Software Protected Mode
(SPM), using the Block Protect (BP1, BP0) bits of
the Status Register, can be used .
W
Signal SRWD
Bit Mode Write Protection of the
Status Register
Memory Content
Protected Area1Unprotected Area1
10
Software
Protected
(SPM)
Status Register is Writable
(if the WREN instruction
has set the WEL bit)
The values in the SRWD,
BP1 and BP0 bits can be
changed
Protected against Page
Program, Sector Erase
and Bulk Erase
Ready to accept Page
Program and Sector Er ase
instructions
00
11
01
Hardware
Protected
(HPM)
Status Register is
Hardware write protected
The values in the SRWD,
BP1 and BP0 bits cannot
be changed
Protected against Page
Program, Sector Erase
and Bulk Erase
Ready to accept Page
Program and Sector Er ase
instructions
M25P20
16/40
Read Data Bytes (READ)
The device is first selec ted by driving Chip Select
(S) Low. The instruction code for the Read Data
Bytes (READ) instruction is followed by a 3-byte
address (A23-A0) , each bit being latched-in d uring
the rising edge o f Serial Clock (C). Then t he mem-
ory contents, at that addr ess, is sh ift ed out on Se -
rial Data Output (Q), each bit being shifted out, at
a maximum frequency fR, during the falling edge of
Serial Clock (C).
The instruction sequence is shown in Figure 12..
The first byte addressed can be at any location.
The address is automatically incremented to the
next higher address after each byte of data is shift-
ed out. The wh ole memory can, therefore, be r ead
with a single Read Data Bytes (READ) instruction.
When the highe st address is reached, the addr ess
counter rolls over to 000000h, allowing the read
sequence to be continued indefinitely.
The Read Data Bytes (READ) instruction is termi-
nated by driving Chip Select (S) High. Chip Select
(S) can be driven High at any time dur ing data out-
put. Any Read Data Bytes (READ) instruction,
while an Erase, Program or Write cycle is in
progress, is rejected without having any e ffects on
the cycle that is in prog re ss .
Figure 12. Read Data Bytes (READ) Instruction Sequence and Data-Out Sequence
Note: Address bits A23 to A18 are Don’t Care.
C
D
AI03748D
S
Q
23
21 345678910 2829303132333435
2221 3210
36 37 38
76543 1 7
0
High Impedance Data Out 1
Instruction 24-Bit Address
0
MSB
MSB
2
39
Data Out 2
17/40
M25P20
Read Data Bytes at Higher Speed
(FAST_READ)
The device is first selec ted by driving Chip Select
(S) Low. The instruction code for the Read Data
Bytes at Higher Speed (FAST_READ) instruction
is followed by a 3-byte address (A23-A0) and a
dummy byte, each bit being latched-in during the
rising edge of Serial Clock (C). Then the memory
contents, at that address, is shifted out on Serial
Data Output (Q), each bit being shifted out, at a
maximum frequency fC, during the falling edge of
Serial Clock (C).
The instruction sequence is shown in Figure 13..
The first byte addressed can be at any location.
The address is automatically incremented to the
next higher address after each byte of data is shift-
ed out. The wh ole memory can, therefore, be r ead
with a single Read Data Bytes at Higher Speed
(FAST_READ) instruction. When the highest ad-
dress is reached, the address counter rolls over to
000000h, allowing the read sequence to be contin-
ued indefinitely.
The Read Data Bytes at Higher Speed
(FAST_READ) instruction is termin at ed b y driving
Chip Select (S) High. Chip Select (S) can be driv-
en High at any time during data output. Any Read
Data Bytes at Higher Speed (FAST_READ) in-
struction, while an Erase, Program or Write cycle
is in progress, is rejected without having any ef-
fects on the cycle that is in progress.
Figure 13. Read Data Bytes at Higher Speed (FAST_READ) Instruction Sequen ce
and Data-Out Sequence
Note: Address bits A23 to A18 are Don’t Care.
C
D
AI04006
S
Q
23
21 345678910 28293031
2221 3210
High Impedance
Instruction 24 BIT ADDRESS
0
C
D
S
Q
32 33 34 36 37 38 39 40 41 42 43 44 45 46
765432 0
1
DATA OUT 1
Dummy Byte
MSB
76543210
DATA OUT 2
MSB MSB
7
47
765432 0
1
35
M25P20
18/40
Page Program (PP)
The Page Program (PP) instruction allows bytes to
be programmed in the memory (changing bits from
1 to 0). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been ex-
ecuted. After the Write Enable (WREN) instruction
has been decoded, the device sets the Write En-
able Latch (WEL).
The Page Program (PP) instruction is entered by
driving Chip Select (S) Low, followed by the in-
struction code, three address bytes and at least
one data byte on Serial Data Input (D). If the 8
least significant address bits (A7-A0) are not all
zero, all transmitted data that goes beyond the end
of the current p age are program med from the start
address of the same page (from the address
whose 8 least significant bi ts (A7-A0) are all zero).
Chip Select (S) must be driven Low for the entire
duration of the seq uence.
The instruction sequence is shown in Figure 14..
If more than 2 56 byte s are sent t o the d evice, pre-
viously latched data are discarded and the last 256
data bytes a re guara nteed to be programm ed cor-
rectly within the same page. If less than 256 Data
bytes are sent to device, they are correctly pro-
grammed at the r equested addresses without hav-
ing any effects on the other bytes of the same
page.
For optimized timings, it is recommended to use
the Page Program (PP) instruction to program all
consecutive targeted Bytes in a single sequence
versus using several Page Program (PP) se-
quences with each containing only a few Bytes
(see Instruction Times (Device Grade 6) and In-
struction Times (Device Grade 3)).
Chip Select (S) must be driven High after the
eighth bit of the last dat a byte has been latched in,
otherwise the Page Program (PP) instruction is not
executed.
As soon as Chip Select (S) is driven High, the self-
timed Page Program cycle (whose duration is tPP)
is initiated. While the Page Program cycle is in
progress, the Status Register may be read to
check the value of t he Write In Progress (WIP) bit.
The Write In Progress (WIP) bit is 1 during the self-
timed Page Program cycle, and is 0 when it is
completed. At some unspecified time before the
cycle is complete d, th e W rite En ab le La tc h ( WEL )
bit is reset.
A Page Program (PP) instruction applied to a page
which is protected by the Block Protect (BP1, BP0)
bits (see Table 3. and Table 2.) is not executed.
19/40
M25P20
Figure 14. Page Program (PP) Instruction Sequence
Note: Address bits A23 to A18 are Don’t Care.
C
D
AI04082B
S
4241 43 44 45 46 47 48 49 50 52 53 54 5540
C
D
S
23
21 345678910 2829303132333435
2221 3210
36 37 38
Instruction 24-Bit Address
0
765432 0
1
Data Byte 1
39
51
765432 0
1
Data Byte 2
765432 0
1
Data Byte 3 Data Byte 256
2079
2078
2077
2076
2075
2074
2073
765432 0
1
2072
MSB MSB
MSB MSB MSB
M25P20
20/40
Sector Erase (SE)
The Sector Erase (SE) instruction sets to 1 (FFh)
all bits inside the chosen sector. Before it can be
accepted, a Write Enable (WREN) instruction
must previously have been executed. After the
Write Enable (WREN) instr uction has been decod-
ed, the device sets the Write Enab le Latch (WEL).
The Sector Erase (SE) instruction is entered by
driving Chip Select (S) Low, followed by the in-
struction code, and three address bytes on Serial
Data Input (D). Any address inside the Sector ( see
Table 3.) is a valid address for the Sector Erase
(SE) instruction. Chip Select (S) must be driven
Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 15..
Chip Select (S) must be driven High after the
eighth bit of the last address byte has been latched
in, otherwise the Sector Erase (SE) instruction is
not executed. As soon as Chip Select (S) is driven
High, the self-timed Sector Erase cycle (whose du-
ration is tSE) is initiated. While the Sector Erase cy-
cle is in progress, t he Status Register may be r ead
to check the value of the Write In Progress (WIP)
bit. The Write I n Progr ess (WIP) bit is 1 d uri ng the
self-timed Sector Erase cycle, and is 0 when it is
completed. At some unspecified time before the
cycle is complete d, th e W rite En ab le La tc h ( WEL )
bit is reset.
A Sector Erase (SE) instruction applied to a page
which is protected by the Block Protect (BP1, BP0)
bits (see Table 3. and Table 2.) is not executed.
Figure 15. Sector Erase (SE) Instruction Sequence
Note: Address bits A23 to A18 are Don’t Care.
24 Bit Address
C
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AI03751D
S
21 3456789 293031
Instruction
0
23 22 2 0
1
MSB
21/40
M25P20
Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to 1
(FFh). Before it can be accepted, a Write Enable
(WREN) instruction must previously have been ex-
ecuted. After the Write Enable (WREN) instruction
has been decoded, the device sets the Write En-
able Latch (WEL).
The Bulk Erase (BE) instruction is entered by driv-
ing Chip Select (S) Low, followed by the instruction
code on Serial Data Input (D). Chip Select (S)
must be driven Low for the entire duration of the
sequence.
The instruction sequence is shown in Figure 16..
Chip Select (S) must be driven High after the
eighth bit of the instruct ion code has bee n lat ched
in, otherwise the Bulk Erase instruction is not exe-
cuted. As soon as Chip Select (S) is driven High,
the self-timed Bulk Er ase cycle (whose dur ation is
tBE) is initiated. While the Bulk Erase cycle is in
progress, the Status Register may be read to
check the value of t he Write In Progress (WIP) bit.
The Write In Progress (WIP) bit is 1 during the self-
timed Bulk Erase cycle, and is 0 when it is com-
pleted. At some unspecified time before the cycle
is completed, the Write Enable Latch (W EL) bit is
reset.
The Bulk Erase (BE) instruction is executed only if
both Block Protect (BP1, BP0) bits are 0. The Bulk
Erase (BE) instruction is ignored if one, or more,
sectors are protecte d.
Figure 16. Bulk Erase (BE) Instruction Sequence
C
D
AI03752D
S
21 345670
Instruction
M25P20
22/40
Deep Power-down (DP)
Executing the Deep Power-down (DP) instruction
is the only wa y to put the device in the lowe st con-
sumption mode (the Deep Power-down mode). It
can also be used as an extra software protection
mechanism, w hile the device is not in active us e,
since in this mode, the device ignores all Write,
Program and Erase instructions.
Driving Chip Select (S) High deselects the device,
and puts the device in the Standby mode (if there
is no internal cycle currently in progress). But this
mode is not the Deep Power-down mode. The
Deep Power-down mode can only be entered by
executing the Deep Power-down (DP) instruction,
subsequently reducing the standby current (from
ICC1 to ICC2, as specified in Tabl e 12.).
Once the device has entered the Deep Power-
down mode, all instruction s are ignored except the
Release from Deep Power-down and Read Elec-
tronic Signature (RES) instruction. This releases
the device from this mode. The Release from
Deep Power-down and Read Ele ctronic Signat ure
(RES) instruction also allows the Electron ic Signa-
ture of the device t o be o utpu t o n Ser ial Da ta Out-
put (Q).
The Deep Power-down mode automatically stops
at Power-do wn, and the device always Power s-up
in the Standby mode.
The Deep Power-do wn (DP) in structio n is entered
by driving Chip Select (S) Low, followed by the in-
struction code on Serial Data Input (D). Chip Se-
lect (S) must be driven Low for the entire duration
of the sequence.
The instruction sequence is shown in Figure 17..
Chip Select (S) must be driven High after the
eighth bit of the instruction code has been latched
in, otherwise th e Deep Power-down (DP) instruc-
tion is not executed. As so on as Ch ip Select ( S ) is
driven High, it requires a delay of tDP before the
supply current is reduced to ICC2 and the Deep
Power-down mode is entered.
Any Deep Power-down (DP) instruction, while an
Erase, Program or Write cycle is in progress, is re-
jected without having any effe cts on the cycle th at
is in progress.
Figure 17. Deep Power-down (DP) Instruction Sequence
C
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AI03753D
S
21 345670t
DP
Deep Power-down Mode
Stand-by Mode
Instruction
23/40
M25P20
Release from Deep Power-down and Read
Electronic Signature (RES)
Once the device has entered the Deep Power-
down mode, all instruction s are ignored except the
Release from Deep Power-down and Read Elec-
tronic Signature (RES) instruction. Executing this
instruction takes the device out of the Deep Pow-
er-down mode.
The instruction can also be used to rea d, on Serial
Data Output (Q), the 8-bit Electronic Signature,
whose value for the M25P20 is 11h.
Except while an Erase, Program or Write Status
Register cycle is in progress, the Release from
Deep Power-down and Read Ele ctronic Signat ure
(RES) instruction always provides access to the 8-
bit Electronic Signature of the device, and can be
applied even if the Deep Power-down mode has
not been entered.
Any Release from Deep Power-down and Read
Electronic Signature (RES) instruction while an
Erase, Program or Write Status Register cycle is in
progress, is not decoded, and has no effect on the
cycle that is in progress.
The device is first selec ted by driving Chip Select
(S) Low. The instruction code is followed by 3
dummy bytes, each bit being latched-in on Serial
Data Input (D) during the rising edge of Serial
Clock (C). Then, the 8-bit Electronic Signature,
stored in the memo ry, is shifted o ut on Serial Data
Output (Q), each bit being shifted out during the
falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 18..
The Release from Deep Power-down and Read
Electronic Signature (RES) instruction is terminat-
ed by driving Chip Select (S) High after the Elec-
tronic Signature has been read at least once.
Sending additional clock cycles on Serial Clock
(C), while Chip Select (S) is driven Low, cause the
Electronic Signature to be output repeatedly.
When Chip Select (S) is driven High, the device is
put in the Stand by Powe r m o de . If the de vic e wa s
not previously in t he Deep Power-down mode, the
transition to the Standby Power mode is immedi-
ate. If the device wa s previo usly in the Dee p Pow-
er-down mode, though, the transition to the
Standby Power mode is delayed by tRES2, and
Chip Select (S) must remain High for at least
tRES2(max), as specified in Table 17.. Once in the
Standby Power mode, the device waits to be se-
lected, so that it can receive, decode and execute
instructions.
Figure 18. Release from Deep Power-down and Read Electronic Signature (RES) Instruction
Sequence and Data-Out Sequence
Note: The value of the 8- bit Electronic Signature, for the M25P20, is 11h.
C
D
AI04047C
S
Q
23
21 345678910 2829303132333435
2221 3210
36 37 38
765432 0
1
High Impedance Electronic Signature Out
Instruction 3 Dummy Bytes
0
MSB
Stand-by Mode
Deep Power-down Mode
MSB
t
RES2
M25P20
24/40
Figure 19. Release from Deep Power-down (RES) Instruction Sequence
Driving Chip Select (S) High after the 8-bit instruc-
tion byte has been received by the device, but be-
fore the whole of the 8-bit Electronic Signature has
been transmitted for the first time (as shown in Fig-
ure 19.), still ensures that the device is put into
Standby Power mode. If the device was not previ-
ously in the Deep Power-down mode, the transi-
tion to the Standby Power mode is immediate. If
the device was previously in the Deep Power-
down mode, though, the transition to the Standby
Power mode is delayed by tRES1, and Chip Select
(S) must remain High for at least tRES1(max), as
specified in Table 17.. Once in the Standby Power
mode, the device waits to be selected, so that it
can receive, decode and execute instructions.
C
D
AI04078B
S
21 345670tRES1
Stand-by Mode
Deep Power-down Mode
QHigh Impedance
Instruction
25/40
M25P20
POWER-UP AND POWER-DOWN
At Power-up and Power-down, the device must
not be selecte d (that is Chip Select (S) must follow
the voltage applied on VCC) until VCC reaches the
correct value:
–V
CC(min) at Power-up, and t hen for a further
delay of tVSL
–V
SS at Power-down
Usually a simple pull-up resistor on Chip Select (S)
can be used to ensure safe and proper Power-up
and Power-down.
To avoid data corruption an d inadve rtent writ e op-
erations during power up, a Power On Reset
(POR) circuit is included. The logic inside the de-
vice is held reset while VCC is less than the Power
On Reset (POR) thre shold volta ge, VWI – all oper-
ations are disabled, and the device does not re-
spond to any instruction.
Moreover, the device ignores all Write Enable
(WREN), Page Program (PP), Sector Erase (SE),
Bulk Erase (BE) and Write Status Register
(WRSR) instructions until a time delay of tPUW has
elapsed afte r the moment that VCC rises above the
VWI threshold. However, the correct operation of
the device is not guarant eed if, by this time, VCC is
still below VCC(min). No Write Status Register,
Program or Erase instructions should be sent until
the later of:
–t
PUW after VCC passed the VWI threshold
–t
VSL after VCC passed the VCC(min) level
These values are specified in Table 7..
If the delay, tVSL, has elapsed, aft er VCC has risen
above VCC(min), the device can be selected for
READ instructions even if the tPUW delay is not yet
fully elapsed.
At Power-up, the device is in the following state:
– The device is in the Standby mode (not the
Deep Power-down mode).
– The Write Enable La tc h (WEL) bit is reset.
Normal precautions must be taken for supply rail
decoupling, to stabilize the VCC supply. Eac h de-
vice in a system should have the VCC rail decou-
pled by a suitable capacitor close to the package
pins. (Generally, this capacitor is of the order of
0.1µF).
At Power-down, when VCC drops f rom the opera t-
ing voltage, to below the Power On Reset (POR)
threshold voltage, V WI, all operations are di sabled
and the device does not respond to any instruc-
tion. (The designer needs to be aware that if a
Power-down occurs while a Write, Program or
Erase cycle is in progress, some data corruption
can result.)
Figure 20. Power-up Timing
VCC
AI04009C
VCC(min)
VWI
Reset State
of the
Device
Chip Selection Not Allowed
Program, Erase and Write Commands are Rejected by the Device
tVSL
tPUW
time
Read Access allowed Device fully
accessible
VCC(max)
M25P20
26/40
Table 7. Power-Up Timing and VWI Threshold
Note: 1. These par ameters are characterized only.
INITIAL DELIVERY STATE
The device is delivered with the memory array
erased: all bits are set to 1 (each byte contains FFh). The Stat us Register cont ains 00h (all Stat us
Register bits are 0).
Symbol Parameter Min. Max. Unit
tVSL1VCC(min) to S low 10 µs
tPUW1Time delay to Write instruction 1 10 ms
VWI1Write Inhibit Voltage 1 2 V
27/40
M25P20
MAXIMUM RATING
Stressing the device above the rating listed in the
Absolute Maximum Ratings" table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at these or
any other conditions above those indicated in the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 8. Absolute Maximum Rat ings
Note: 1. Compliant wi th JED EC St d J-STD -020 C (for smal l body , Sn- Pb or Pb as sembl y), the ST E COPACK® 7191395 specification, and
the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU.
2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 Ω, R2=500 Ω).
Symbol Parameter Min. Max. Unit
TSTG Storage Temperature –65 150 °C
TLEAD Lead Temperature during Soldering See note 1°C
VIO Input and Output Voltage (with respect to Ground) –0.6 4.0 V
VCC Supply Voltage –0.6 4.0 V
VESD Electrostatic Discharge Voltage (Human Body model) 2–2000 2000 V
M25P20
28/40
DC AND AC PARAMETERS
This section summarizes the operating and mea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Designers should check that the operating
conditions in their circuit match the measurement
conditions when relying on the quoted parame-
ters.
Table 9. Operating Conditions
Table 10. Data Retention and Endurance
Note: 1. This is preliminary data
Table 11. Capacitance
Note: Sampled only, not 100% tested, at TA=25°C and a frequency of 20MHz.
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 2.7 3.6 V
TAAmbient Operating Temperature (Device Grade 6) –40 85 °C
Ambient Operating Temperature (Device Grade 3) –40 125
Parameter Condition Min. Max. Unit
Erase/Program Cycles Device Grade 6 100 000 cycles per
sector
Device Grade 3 1 10 000
Data Retention Device Grade 6 20 years
Device Grade 3 1 (at 85°C) 20
Symbol Parameter Test Condition Min.Max.Unit
COUT Output Capacitance (Q) VOUT = 0V 8 pF
CIN Input Capacitance (other pins) VIN = 0V 6 pF
29/40
M25P20
Table 12. DC Characteristics
Table 13. DC Characteristics (Device Grade 3)
Note: 1. This is preliminary data
Symbol Parameter Test Condition
(in addition to those in Table 9.)Min. Max. Unit
ILI Input Leakage Current ± 2 µA
ILO Output Leakage Current ± 2 µA
ICC1 Standby Current S = VCC, VIN = VSS or VCC 50 µA
ICC2 Deep Power-down Current S = VCC, VIN = VSS or VCC 5µA
ICC3 Operating Current (READ)
C = 0.1VCC / 0.9.VCC at 40MHz,
Q = open 8mA
C = 0.1VCC / 0.9.VCC at 20MHz,
Q = open 4mA
ICC4 Operating Current (PP) S = VCC 15 mA
ICC5 Operating Current (WRSR) S = VCC 15 mA
ICC6 Operating Current (SE) S = VCC 15 mA
ICC7 Operating Current (BE) S = VCC 15 mA
VIL Input Low Voltage – 0.5 0.3VCC V
VIH Input High Voltage 0.7VCC VCC+0.4 V
VOL Output Low Voltage IOL = 1.6 mA 0.4 V
VOH Output High Voltage IOH = –100 µAV
CC–0.2 V
Symbol Parameter Test Condition
(in addition to those in Table 9.)Min.1Max.1Unit
ILI Input Leakage Current ± 2 µA
ILO Output Leakage Current ± 2 µA
ICC1 Standby Current S = VCC, VIN = VSS or VCC 100 µA
ICC2 Deep Power-down Current S = VCC, VIN = VSS or VCC 50 µA
ICC3 Operating Current (READ)
C = 0.1VCC / 0.9.VCC at 40MHz,
Q = open 8mA
C = 0.1VCC / 0.9.VCC at 20MHz,
Q = open 4mA
ICC4 Operating Current (PP) S = VCC 15 mA
ICC5 Operating Current (WRSR) S = VCC 15 mA
ICC6 Operating Current (SE) S = VCC 15 mA
ICC7 Operating Current (BE) S = VCC 15 mA
VIL Input Low Voltage – 0.5 0.3VCC V
VIH Input High Voltage 0.7VCC VCC+0.4 V
VOL Output Low Voltage IOL = 1.6 mA 0.4 V
VOH Output High Voltage IOH = –100 µAV
CC–0.2 V
M25P20
30/40
Table 14. Instruction Times (Device Grade 6)
Table 15. Instruction Times (Device Grade 3)
Note: 1. At 85°C
2. This is preliminary data
3. When using the Page Program (PP) instruction to program consecutive Bytes, optimized timings are obtained with one sequence
including all the Bytes versus several sequences of only a few Bytes. (1 ≤ n ≤ 256)
Table 16. AC Measurement Conditions
Note: Output Hi-Z is defined as the point where data out is no longer driven.
Test conditions specified in Table 9. and Table 16.
Symbol Alt. Parameter Min. Typ. Max. Unit
tWWrite Status Register Cycle Time 5 15 ms
tPP (1)
1. When using the Page Progr am (P P) in st ructi on to progr am co nsec ut ive By tes, optimiz ed t imin gs a re ob tain ed with one se-
quence including all the Bytes ve rsus several sequence s of only a few Bytes. (1 ≤ n ≤ 256)
Page Program Cycle Time (256 Bytes) 1.4 5ms
Page Program Cycle Time (n Bytes) 0.4+
n*1/256
tSE Sector Erase Cycle Time 0.8 3 s
tBE Bulk Erase Cycle Time 2.5 6 s
Test conditions specified in Table 9. and Table 16.
Symbol Alt. Parameter Min. Typ.1,2 Max.2Unit
tWWrite Status Register Cycle Time 8 15 ms
tPP 3
Page Program Cycle Time (256 Bytes) 1.5
5ms
Page Program Cycle Time (n Bytes) 0.4+
n*1.1/
256
tSE Sector Erase Cycle Time 1 3 s
tBE Bulk Erase Cycle Time 2.8 6 s
Symbol Parameter Min. Max. Unit
CLLoad Capacitance 30 pF
Input Rise and Fall Times 5 ns
Input Pulse Voltages 0.2VCC to 0.8VCC V
Input Timing Reference Voltages 0.3VCC to 0.7VCC V
Output Timing Reference Voltages VCC / 2 V
31/40
M25P20
Figure 21. AC Measurement I/O Waveform
Table 17. AC Characteristics (25MHz Operation, Device Grade 6 or 3)
Test conditions specified in Table 9. and Table 16.
Symbol Alt. Parameter Min. Typ. Max. Unit
fCfCClock Frequency for the following instructions:
FAST_READ, PP, SE, BE, DP, RES,
WREN, WRDI, RDSR, WRSR D.C. 25 MHz
fRClock Frequency for READ instructions D.C. 20 MHz
tCH 1tCLH Clock High Time 18 ns
tCL 1tCLL Clock Low Time 18 ns
tCLCH 2Clock Rise Time3 (peak to peak) 0.1 V/ns
tCHCL 2Clock Fall Time3 (peak to peak) 0.1 V/ns
tSLCH tCSS S Active Setup Time (relative to C) 10 ns
tCHSL S Not Active Hold Time (relative to C) 10 ns
tDVCH tDSU Data In Setup Time 5 ns
tCHDX tDH Data In Hold Time 5 ns
tCHSH S Active Hold Time (relative to C) 10 ns
tSHCH S Not Active Setup Time (relative to C) 10 ns
tSHSL tCSH S Deselect Time 100 ns
tSHQZ 2tDIS Output Disable Time 15 ns
tCLQV tVClock Low to Output Valid 15 ns
tCLQX tHO Output Hold Time 0 ns
tHLCH HOLD Setup Time (relative to C) 10 ns
tCHHH HOLD Hold Time (relative to C) 10 ns
tHHCH HOLD Setup Time (relative to C) 10 ns
tCHHL HOLD Hold Time (relative to C) 10 ns
tHHQX 2tLZ HOLD to Output Low-Z 15 ns
AI07455
0.8VCC
0.2VCC
0.7VCC
0.3VCC
Input and Output
Timing Reference Levels
Input Levels
0.5VCC
M25P20
32/40
Note: 1. tCH + tCL must be greater than or equal to 1/ fC
2. Value guaranteed by characterization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicable as a constraint for a WRSR instr uction when S R WD is set at 1.
Table 18. AC Characteristics (40MHz Operation, Device Grade 6)
tHLQZ 2tHZ HOLD to Output High-Z 20 ns
tWHSL 4Write Protect Setup Time 20 ns
tSHWL 4Write Protect Hold Time 100 ns
tDP 2S High to Deep Power-down Mode 3 µs
tRES1 2S High to Standby Mode without Electronic
Signature Read 3µs
tRES2 2S High to Standby Mode with Electronic
Signature Read 1.8 µs
40MHz available for products marked since week 20 of 2004, only5
Test conditions specified in Table 9. and Table 16.
Symbol Alt. Parameter Min. Typ. Max. Unit
fCfCClock Frequency for the following instructions:
FAST_READ, PP, SE, BE, DP, RES,
WREN, WRDI, RDSR, WRSR D.C. 40 MHz
fRClock Frequency for READ instructions D.C. 20 MHz
tCH 1tCLH Clock High Time 11 ns
tCL 1tCLL Clock Low Time 11 ns
tCLCH 2Clock Rise Time3 (peak to peak) 0.1 V/ns
tCHCL 2Clock Fall Time3 (peak to peak) 0.1 V/ns
tSLCH tCSS S Active Setup Time (relative to C) 5 ns
tCHSL S Not Active Hold Time (relative to C) 5 ns
tDVCH tDSU Data In Setup Time 2 ns
tCHDX tDH Data In Hold Time 5 ns
tCHSH S Active Hold Time (relative to C) 5 ns
tSHCH S Not Active Setup Time (relative to C) 5 ns
tSHSL tCSH S Deselect Time 100 ns
tSHQZ 2tDIS Output Disable Time 9 ns
tCLQV tVClock Low to Output Valid 9 ns
tCLQX tHO Output Hold Time 0 ns
tHLCH HOLD Setup Time (relative to C) 5 ns
tCHHH HOLD Hold Time (relative to C) 5 ns
tHHCH HOLD Setup Time (relative to C) 5 ns
Test conditions specified in Table 9. and Table 16.
Symbol Alt. Parameter Min. Typ. Max. Unit
33/40
M25P20
Note: 1. tCH + tCL must be greater than or equal to 1/ fC
2. Value guaranteed by characterization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicable as a constraint for a WRSR instr uction when S R WD is set at 1.
5. Details of how to find the date of marking are given in Application Note, AN1995.
Figure 22. Serial Input Timing
tCHHL HOLD Hold Time (relative to C) 5 ns
tHHQX 2tLZ HOLD to Output Low-Z 9 ns
tHLQZ 2tHZ HOLD to Output High-Z 9 ns
tWHSL 4Write Protect Setup Time 20 ns
tSHWL 4Write Protect Hold Time 100 ns
tDP 2S High to Deep Power-down Mode 3 µs
tRES1 2S High to Standby Mode without Electronic
Signature Read 3µs
tRES2 2S High to Standby Mode with Electronic
Signature Read 1.8 µs
40MHz available for products marked since week 20 of 2004, only5
Test conditions specified in Table 9. and Table 16.
Symbol Alt. Parameter Min. Typ. Max. Unit
C
D
AI01447C
S
MSB IN
Q
tDVCH
High Impedance
LSB IN
tSLCH
tCHDX
tCHCL
tCLCH
tSHCH
tSHSL
tCHSHtCHSL
M25P20
34/40
Figure 23. Write Protect Setup and Hold Timing during WRSR when SRWD=1
Figure 24. Hold Timing
C
D
S
Q
High Impedance
W
tWHSL tSHWL
AI07439
C
Q
AI02032
S
D
HOLD
tCHHL
tHLCH
tHHCH
tCHHH
tHHQXtHLQZ
35/40
M25P20
Figure 25. Output Timing
C
Q
AI01449e
S
LSB OUT
DADDR.LSB IN
tSHQZ
tCH
tCL
tQLQH
tQHQL
tCLQX
tCLQV
tCLQX
tCLQV
M25P20
36/40
PACKAGE MECHANICAL
Figure 26. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width, Package Outline
Note: Drawing is not to scale.
Table 19. SO8 narrow – 8 lead Plastic Small Outline, 150 mils body width,
Package Mechanical Data
Symbol millimeters inches
Typ. Min. Max. Typ. Min. Max.
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
E 3.80 4.00 0.150 0.157
e1.27––0.050––
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.40 0.90 0.016 0.035
α0° 8° 0° 8°
N8 8
CP 0.10 0.004
SO-a
E
N
CP
Be
A
D
C
LA1 α
1
H
h x 45˚
37/40
M25P20
Figure 27. MLP8, 8-lead Very thin Dual Flat Package No lead, 6x5mm, Package Outline
Note: Drawing is not to scale.
Table 20. MLP8, 8-lead Very thin Dual Flat Package No lead, 6x5mm, Package Mechanical Data
Symbol millimeters inches
Typ. Min. Max. Typ. Min. Max.
A 0.85 1.00 0.0335 0.0394
A1 0.00 0.05 0.0000 0.0020
A2 0.65 0.0256
A3 0.20 0.0079
b 0.40 0.35 0.48 0.0157 0.0138 0.0189
D 6.00 0.2362
D1 5.75 0.2264
D2 3.40 3.20 3.60 0.1339 0.1260 0.1417
E 5.00 0.1969
E1 4.75 0.1870
E2 4.00 3.80 4.20 0.1575 0.1496 0.1654
e 1.27 0.0500
L 0.60 0.50 0.75 0.0236 0.0197 0.0295
θ12° 12°
D
E
VDFPN-01
A2
A
A3
A1
E1
D1
eE2
D2
L
b
θ
M25P20
38/40
PART NUMBERING
Table 21. Ordering Information Scheme
Note: 1. ST strongly recommends the use of the Automotive Grade devices for use in an automotive environment. The High Reliability Cer-
tified Flow (HRCF) is described in the quality note QNEE9801. Please ask your nearest ST sales office for a copy.
2. Device grad e 3 available in SO8 Lead-free and RoHS comp liant package
For a list of available optio ns (speed, package, etc.) or for fu rther information on any aspect of this device,
please contact your nea rest ST Sales Office.
Example: M25P20 – V MN 6 T P
Device Type
M25P = Serial Flash Memory for Code Storage
Device Function
20 = 2 Mbit (256K x 8)
Operating Voltage
V = VCC = 2.7 to 3.6V
Package
MN = SO8 (150 mil width)
MP = VDFPN8 6x5mm (MLP8)
Device Grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
3 (2) = Device tested with High Reliability Certified Flow1.
Automotive temperature range (–40 to 125 °C)
Option
blank = Standard Packing
T = Tape and Reel Packing
Plating Technology
blank = Standard SnPb plating
P or G = RoHS compliant
39/40
M25P20
REVISION HISTORY
Table 22. Document Revision History
Date Rev. Description of Revision
12-Apr-2001 1.0 Document written
25-May-2001 1.1 Serial Paged Flash Memory renamed as Serial Flash Memory
11-Sep-2001 1.2
Changes to text: Signal Description/Chip Select; Hold Condition/1st para; Protection modes;
Release from Power-down and Read Electronic Signature (RES); Power-up
Repositioning of several tables and illustrations without changing their contents
Power-up timing illustration; SO8W package removed
Changes to tables: Abs Max Ratings/VIO; DC Characteristics/VIL
16-Jan-2002 1.3 FAST_READ instr uction added. Document revised with new timings, VWI, ICC3 and clock slew
rate. Descriptions of Polling, Hold Condition, Page Programming, Release for Deep Po wer-
down made more precise. Value of tW(max) modified.
16-May-2002 1.4 Clarification of descriptions of entering Standby Power mode from Deep Power-down mode,
and of terminating an instruction sequence or data-out sequence.
12-Sep-2002 1.5 VFQFPN8 package (MLP8) added. Document promoted to full datasheet.
13-Dec-2002 1.6 Typical Page Program time improv ed. Write Protect setup and hold times specified, for
applications that s witch Write Protect to exit the Hardw are Protection mode immediately bef ore
a WRSR, and to enter the Hardware Protection mode again immediately after.
24-Nov-2003 2.0 Table of contents, w arning about e xposed paddle on MLP8, and Pb-free options added.
40MHz AC Characteristics table included as well as 25MHz. ICC3(max), tSE(typ) and tBE(typ)
values improved. Change of naming for VDFPN8 package
26-Apr-2004 3.0 Automotive range added. Soldering temperature information clarified for RoHS compliant
devices. Device Grade clarified
05-Aug-2004 4.0 Device Gr ade information clarified. Data-retention measurement temperature corrected.
Details of how to find the date of marking added.
21-Dec-2004 5.0 2 Notes removed from Table 21., Ordering Information Scheme. Small text changes. End
timing line of tSHQZ modified in Figure 25., Output Timing.
01-Aug-2005 6.0 Updated Page Program (PP) instructions in Page Programming, Page Program (PP),
Instruction Times (Device Grade 6) and Instruction Times (Device Grade 3).
M25P20
40/40
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by implicatio n o r otherwise u nd er an y pa ten t o r pa ten t rights of STMicroelectronics . Sp ec ific ations mentione d in this public ation are subject
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