4-Channel/8-Channel
Fault-Protected Analog Multiplexers
ADG508F/ADG509F/ADG528F
Rev. E
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FEATURES
Low on resistance (300 Ω typical)
Fast switching times
tON 250 ns maximum
tOFF 250 ns maximum
Low power dissipation (3.3 mW maximum)
Fault and overvoltage protection (−40 V to +55 V)
All switches off with power supply off
Analog output of on channel clamped within power
supplies if an overvoltage occurs
Latch-up proof construction
Break-before-make construction
TTL and CMOS compatible inputs
APPLICATIONS
Existing multiplexer applications (both fault-protected and
nonfault-protected)
New designs requiring multiplexer functions
FUNCTIONAL BLOCK DIAGRAMS
S1
S8
A0
D
ADG508F/
ADG528F
A1 A2 EN
1 OF 8
DECODER
ADG528F
ONLY WR
RS
00035-001
S1A
A0
DA
ADG509F
A1
S4A
S1B
S4B DB
EN
1 OF 4
DECODER
00035-101
Figure 1.
GENERAL DESCRIPTION
The ADG508F, ADG509F, and ADG528F are CMOS analog
multiplexers, with the ADG508F and ADG528F comprising
eight single channels and the ADG509F comprising four
differential channels. These multiplexers provide fault protec-
tion. Using a series n-channel, p-channel, n-channel MOSFET
structure, both device and signal source protection is provided
in the event of an overvoltage or power loss. The multiplexer
can withstand continuous overvoltage inputs from −40 V to
+55 V. During fault conditions, the multiplexer input (or out-
put) appears as an open circuit and only a few nanoamperes of
leakage current will flow. This protects not only the multiplexer
and the circuitry driven by the multiplexer, but also protects
the sensors or signal sources that drive the multiplexer.
The ADG508F and ADG528F switch one of eight inputs to a
common output as determined by the 3-bit binary address lines
A0, A1, and A2. The ADG509F switches one of four differential
inputs to a common differential output as determined by the
2-bit binary address lines A0 and A1. The ADG528F has on-
chip address and control latches that facilitate microprocessor
interfacing. An EN input on each device is used to enable or
disable the device. When disabled, all channels are switched off.
PRODUCT HIGHLIGHTS
1. Fault Protection.
The ADG508F/ADG509F/ADG528F can withstand
continuous voltage inputs from −40 V to +55 V. When a
fault occurs due to the power supplies being turned off, all
the channels are turned off and only a leakage current of a
few nanoamperes flows.
2. On channel turns off while fault exists.
3. Low RON.
4. Fast switching times.
5. Break-before-make switching.
Switches are guaranteed break-before-make so that input
signals are protected against momentary shorting.
6. Trench isolation eliminates latch-up.
A dielectric trench separates the p and n-channel
MOSFETs thereby preventing latch-up.
ADG508F/ADG509F/ADG528F
Rev. E | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagrams ............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Dual Supply ................................................................................... 3
Truth Tables ................................................................................... 4
Timing Diagrams .......................................................................... 5
Absolute Maximum Ratings ............................................................6
ESD Caution...................................................................................6
Pin Configuration and Function Descriptions ..............................7
Typical Performance Characteristics ..............................................8
Terminology .................................................................................... 10
Theory of Operation ...................................................................... 11
Test Circuits ..................................................................................... 12
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 18
REVISION HISTORY
7/09—Rev. D: Rev. E
Updated Format .................................................................. Universal
Added TSSOP ..................................................................... Universal
Updated Outline Dimensions ....................................................... 15
Changes to Ordering Guide .......................................................... 18
4/01—Data Sheet Changed from Rev. C to Rev. D.
Changes to Ordering Guide ............................................................ 1
Changes to Specifications Table ...................................................... 2
Max Ratings Changed ...................................................................... 4
Deleted 16-Lead Cerdip from Outline Dimensions .................. 11
Deleted 18-Lead Cerdip from Outline Dimensions .................. 12
ADG508F/ADG509F/ADG528F
Rev. E | Page 3 of 20
SPECIFICATIONS
DUAL SUPPLY
VDD = +15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
B Version
Parameter +25°C −40°C to +85°C Unit Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range VSS + 3 V min
V
DD − 1.5 V max
RON 300 350 Ω typ −10 V ≤ VS ≤ +10 V, IS = 1 mA;
V
DD = +15 V ± 10%, VSS = −15 V ± 10%
400 Ω max −10 V ≤ VS ≤ +10 V, IS = 1 mA;
V
DD = +15 V ± 5%, VSS = −15 V ± 5%
RON Drift 0.6 %/°C typ VS = 0 V, IS = 1 mA
RON Match 5 % max VS = 0 V, IS = 1 mA
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF) ±0.02 nA typ VD = ±10 V, VS = +10 V;
±1 ±50 nA max See Figure 22
Drain OFF Leakage ID (OFF) ±0.04 nA typ VD = ±10 V, VS = +10 V;
ADG508F/ADG528F ±1 ±60 nA max See Figure 23
ADG509F ±1 ±30 nA max
Channel ON Leakage ID, IS (ON) ±0.04 nA typ VS = VD = ± 10 V;
ADG508F/ADG528F ±1 ±60 nA max See Figure 24
ADG509F ±1 ±30 nA max
FAULT
Output Leakage Current ±0.02 nA typ VS = ±33 V, VD = 0 V, see Figure 23
(With Overvoltage) ±2 ±2 μA max
Input Leakage Current ±0.005 μA typ VS = ±25 V, VD = +10 V, see Figure 25
(With Overvoltage) ±2 μA max
Input Leakage Current ±0.001 μA typ VS = ±25 V, VD = VEN = A0, A1, A2 = 0 V
(With Power Supplies OFF) ±2 μA max See Figure 26
DIGITAL INPUTS
Input High Voltage, VINH 2.4 V min
Input Low Voltage, VINL 0.8 V max
Input Current, IINL or IINH ±1 μA max VIN = 0 or VDD
CIN, Digital Input Capacitance 5 pF typ
DYNAMIC CHARACTERISTICS1
tTRANSITION 200 ns typ RL = 1 MΩ, CL = 35 pF;
300 400 ns max VS1 = ±10 V, VS8 = +10 V; see Figure 27
tOPEN 50 ns typ RL = 1 kΩ, CL = 35 pF;
25 10 ns min VS = 5 V; see Figure 28
tON (EN, WR) 200 ns typ RL = 1 kΩ, CL = 35 pF;
250 400 ns max VS = 5 V; see Figure 29
tOFF (EN, RS) 200 ns typ RL = 1 kΩ, CL = 35 pF;
tSETT, Settling Time 250 400 ns max VS = 5 V; see Figure 29
0.1% 1 μs typ RL = 1 kΩ, CL = 35 pF;
0.01% 2.5 μs typ VS = 5 V
ADG528F Only
tW, Write Pulse Width 100 120 ns min
tS, Address, Enable Setup Time 100 ns min
tH, Address, Enable Hold Time 10 ns min
tRS, Reset Pulse Width 100 ns min
ADG508F/ADG509F/ADG528F
Rev. E | Page 4 of 20
B Version
Parameter +25°C −40°C to +85°C Unit Test Conditions/Comments
Charge Injection 4 pC typ VS = 0 V, RS = 0 Ω,CL= 1 nF; see Figure 32
OFF Isolation 68 dB typ RL = 1 kΩ, CL = 15 pF, f = 100 kHz;
50 dB min VS = 7 V rms; see Figure 33
CS (OFF) 5 pF typ
CD (OFF)
ADG508F/ADG528F 50 pF typ
ADG509F 25 pF typ
POWER REQUIREMENTS
IDD 0.1 0.2 mA max VIN = 0 V or 5 V
ISS 0.1 0.1 mA max
1 Guaranteed by design, not subject to production test.
TRUTH TABLES
Table 2. ADG508F Truth Table
A2 A1 A0 EN ON Switch
X X X 0 None
0 0 0 1 1
0 0 1 1 2
0 1 0 1 3
0 1 1 1 4
1 0 0 1 5
1 0 1 1 6
1 1 0 1 7
1 1 1 1 8
X = Don’t Care
Table 3. ADG509F Truth Table
A1 A0 EN ON Switch Pair
X X 0 None
0 0 1 1
0 1 1 2
1 0 1 3
1 1 1 4
X = Don’t Care
Table 4. ADG528F Truth Table
A2 A1 A0 EN WR RS
ON Switch
X X X X 1 Retains previous switch condition
X X X X X 0 None (address and enable latches cleared)
X X X 0 0 1 None
0 0 0 1 0 1 1
0 0 1 1 0 1 2
0 1 0 1 0 1 3
0 1 1 1 0 1 4
1 0 0 1 0 1 5
1 0 1 1 0 1 6
1 1 0 1 0 1 7
1 1 1 1 0 1 8
X = Don’t Care
ADG508F/ADG509F/ADG528F
Rev. E | Page 5 of 20
TIMING DIAGRAMS
Figure 2 shows the timing sequence for latching the switch address and enable inputs. The latches are level sensitive; therefore, while WR
is held low, the latches are transparent and the switches respond to the address and enable inputs. This input data is latched on the rising
edge of WR.
.
t
W
50% 50%
t
S
t
H
0.8V
2V
3
V
WR
0V
3V
0V
A
0, A1, A2
EN
0
0035-002
Figure 2. ADG528F Timing Sequence for Latching the Switch Address and Enable Inputs
Figure 3 shows the reset pulsewidth, tRS, and the reset turnoff time, tOFF (RS). Note that all digital input signals rise and fall times are
measured from 10% to 90% of 3 V. tR = tF = 20 ns.
t
RS
50% 50%
0.8V
O
3
V
RS
0V
V
O
SWITCH
OUTPUT
t
OFF
(RS)
0V
00035-003
Figure 3. ADG528F Reset Pulse Width
ADG508F/ADG509F/ADG528F
Rev. E | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS
TA = +25°C unless otherwise noted.
Table 5.
Parameter Rating
VDD to VSS 44 V
VDD to GND −0.3 V to +25 V
VSS to GND +0.3 V to −25 V
Digital Input, EN, Ax −0.3 V to VDD + 2 V or 20 mA,
whichever occurs first
VS, Analog Input Overvoltage with
Power On
VSS − 25 V to VDD + 40 V
VS, Analog Input Overvoltage with
Power Off
−40 V to +55 V
Continuous Current, S or D 20 mA
Peak Current, S or D
(Pulsed at 1 ms, 10% Duty Cycle Max) 40 mA
Operating Temperature Range
Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
TSSOP
θJA, Thermal Impedance 112°C/W
Plastic Package
θJA, Thermal Impedance
16-Lead 117°C/W
18-Lead 110°C/W
Lead Temperature, Soldering (10 sec) 260°C
SOIC Package
θJA, Thermal Impedance
Narrow Body 77°C/W
Wide Body 75°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
PLCC Package
θJA, Thermal Impedance 90°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ADG508F/ADG509F/ADG528F
Rev. E | Page 7 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
A0 1
EN 2
VSS 3
S1 4
A116
A215
GND14
VDD
13
S2 5
S3 6
S4 7
S5
12
S6
11
S710
D8S89
ADG508F
TOP VIEW
(Not to Scale)
00035-004
Figure 4. ADG508F Pin Configuration
TSSOP/DIP/SOIC
A0
1
EN
2
V
SS 3
S1A
4
A1
16
GND
15
V
DD
14
S1B
13
S2A
5
S3A
6
S4A
7
S2B
12
S3B
11
S4B
10
DA
8
DB
9
ADG509F
TOP VIEW
(Not to Scale)
00035-005
Figure 5. ADG509F Pin Configuration
TSSOP/DIP/SOIC
WR
1
A0
2
EN
3
V
SS 4
RS
18
A1
17
A2
16
GND
15
S1
5
S2
6
S3
7
V
DD
14
S5
13
S6
12
S4
8
S7
11
D
9
S8
10
ADG528F
TOP VIEW
(Not to Scale)
00035-006
Figure 6. ADG528F Pin Configuration
DIP
1201923
4
5
6
7
8
18
17
16
15
14
910 11 12 13
NC = NO CONNECT
EN
V
SS
S1
S2
S3
A2
GND
V
DD
S5
S6
A0
WR
NC
RS
A1
S4
D
NC
S8
S7
PIN 1
INDENTFIER
ADG528F
TOP VIEW
(Not to Scale)
00035-007
Figure 7. ADG528F Pin Configuration
PLCC
ADG508F/ADG509F/ADG528F
Rev. E | Page 8 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
2000
1000
0
15–15 –10 –5 0 5 10
500
1750
1500
1250
750
250
V
D
, V
S
(V)
R
ON
(Ω)
T
A
= 25°C
V
DD
= +5V
V
SS
= –5V
V
DD
= +10V
V
SS
= –10V
00035-008
Figure 8. On Resistance as a Function of VD (VS)
1m
1µ
1p
–50 –30 –20 –10 0 10 20 30 40 50 60
–40
1n
100µ
10µ
10n
100n
10p
100p
VIN INPUT VOLTAGE (V)
ISINPUT LEAKAGE (A)
OPERATING RANGE
VDD = 0V
VSS = 0V
VD = 0V
00035-009
Figure 9. Input Leakage Current as a Function of VS (Power Supplies Off)
During Overvoltage Conditions
1m
1µ
1p
–50 –30 –20 –10 0 10 20 30 40 50 60
–40
1n
100µ
10µ
10n
100n
10p
100p
V
IN
INPUT VOLTAGE (V)
I
D
INPUT LEAKAGE (A)
OPERATING RANGE
V
DD
= +15V
V
SS
= –15V
V
D
= 0V
00035-010
Figure 10. Output Leakage Current as a Function of VS (Power Supplies On)
During Overvoltage Conditions
2000
1000
0
15–15 –10 –5 0 5 10
500
1750
1500
1250
750
250
V
D
, V
S
(V)
R
ON
(Ω)
V
DD
= +15V
V
SS
= –15V
T
A
= 125°C
T
A
= 85°C
T
A
= 25°C
00035-011
Figure 11. On Resistance as a Function of VD (VS) for Different Temperatures
1m
1µ
1p
–50 –30 –20 –10 0 10 20 30 40 50 60
–40
1n
100µ
10µ
10n
100n
10p
100p
INPUT VOLTAGE (V)
I
S
INPUT LEAKAGE (A)
OPERATING RANGE
V
DD
= +15V
V
SS
= –15V
V
D
= 0V
00035-012
Figure 12. Input Leakage Current as a Function of VS (Power Supplies On)
During Overvoltage Conditions
0.3
0.2
–0.2
–14 –10 –6 –2 2 6 10 14
0.1
0.0
–0.1
V
S,
V
D
(V)
LEAKAGE CURRENTS (nA)
I
S
(OFF)
I
S
(OFF)
I
S
(ON)
V
DD
= +15V
V
SS
= –15V
T
A
= 25°C
00035-013
Figure 13. Leakage Currents as a Function of VD (VS)
ADG508F/ADG509F/ADG528F
Rev. E | Page 9 of 20
100
10
0.01
45 5525 65 75 85 95 10535
1
115 125
0.1
TEMPERATURE (°C)
LEAKAGE CURRENTS (nA)
V
DD
= +15V
V
SS
= –15V
V
D
= +10V
V
S
= –10V
I
S
(OFF)
I
D
(ON)
I
D
(OFF)
00035-014
Figure 14. Leakage Currents as a Function of Temperature
260
240
100
10 11 12 13 14 15
120
t
ON
(EN)
220
200
180
160
140
SWITCHING TIME (ns)
POWER SUPPLY (V)
V
IN
= 2V
t
TRANSITION
t
OFF
(EN)
00035-015
Figure 15. Switching Time vs. Power Supply
280
240
100
25 45 65 85 105 125
120
220
200
180
160
140
TEMPERATURE (°C)
SWITCHING TIME (ns)
260
V
DD
= +15V
V
SS
= –15V
V
IN
= +5V
t
ON
(EN)
t
TRANSITION
t
OFF
(EN)
00035-016
Figure 16. Switching Time vs. Temperature
ADG508F/ADG509F/ADG528F
Rev. E | Page 10 of 20
TERMINOLOGY
VDD
Most Positive Power Supply Potential.
VSS
Most Negative Power Supply Potential.
GND
Ground (0 V) Reference.
RON
Ohmic Resistance between D and S.
RON Drift
Change in RON when temperature changes by one degree
Celsius.
RON Match
Difference between the RON of any two channels.
IS (OFF)
Source leakage current when the switch is off.
ID (OFF)
Drain leakage current when the switch is off.
ID, IS (ON)
Channel leakage current when the switch is on.
VD (VS)
Analog Voltage on Terminals D, S.
CS (OFF)
Channel input capacitance for off condition.
CD (OFF)
Channel output capacitance for off condition.
CD, CS (ON)
On Switch Capacitance.
CIN
Digital Input Capacitance.
tON (EN)
Delay time between the 50% and 90% points of the digital input
and switch on condition.
tOFF (EN)
Delay time between the 50% and 90% points of the digital input
and switch off condition.
tTRANSITION
Delay time between the 50% and 90% points of the digital
inputs and the switch on condition when switching from one
address state to another.
tOPEN
“OFF” time measured between 80% points of both switches
when switching from one address state to another.
VINL
Maximum input voltage for Logic 0.
VINH
Minimum input voltage for Logic 1.
IINL (IINH)
Input current of the digital input.
Off Isolation
A measure of unwanted signal coupling through an off channel.
Charge Injection
A measure of the glitch impulse transferred from the digital
input to the analog output during switching.
IDD
Positive Supply Current.
ISS
Negative Supply Current.
ADG508F/ADG509F/ADG528F
Rev. E | Page 11 of 20
THEORY OF OPERATION
The ADG508F/ADG509F/ADG528F multiplexers are capable of
withstanding overvoltages from −40 V to +55 V, irrespective of
whether the power supplies are present or not. Each channel of
the multiplexer consists of an n-channel MOSFET, a p-channel
MOSFET, and an n-channel MOSFET, connected in series. When
the analog input exceeds the power supplies, one of the MOSFETs
will switch off, limiting the current to submicroamp levels, thereby
preventing the overvoltage from damaging any circuitry following
the multiplexer. Figure 17 illustrates the channel architecture that
enables these multiplexers to withstand continuous overvoltages.
When an analog input of VSS + 3 V to VDD − 1.5 V is applied to
the ADG508F/ADG509F/ADG528F, the multiplexer behaves as
a standard multiplexer, with specifications similar to a standard
multiplexer, for example, the on-resistance is 400 Ω maximum.
However, when an overvoltage is applied to the device, one of
the three MOSFETs will turn off.
Figure 17 to Figure 20 show the conditions of the three MOSFETs
for the various overvoltage situations. When the analog input
applied to an ON channel approaches the positive power supply
line, the n-channel MOSFET turns OFF since the voltage on
the analog input exceeds the difference between VDD and the
n-channel threshold voltage (VTN). When a voltage more nega-
tive than VSS is applied to the multiplexer, the p-channel
MOSFET will turn off since the analog input is more negative
than the difference between VSS and the p-channel threshold
voltage (VTP). Since VTN is nominally 1.5 V and VTP is typically
3 V, the analog input range to the multiplexer is limited to
−12 V to +13.5 V when a ±15 V power supply is used.
When the power supplies are present but the channel is off,
again either the p-channel MOSFET or one of the n-channel
MOSFETs will turn off when an overvoltage occurs.
Finally, when the power supplies are off, the gate of each
MOSFET will be at ground. A negative overvoltage switches
on the first n-channel MOSFET but the bias produced by the
overvoltage causes the p-channel MOSFET to remain turned
off. With a positive overvoltage, the first MOSFET in the series
will remain off since the gate to source voltage applied to this
MOSFET is negative.
During fault conditions, the leakage current into and out of the
ADG508F/ADG509F/ADG528F is limited to a few microamps.
This protects the multiplexer and succeeding circuitry from
over stresses as well as protecting the signal sources which drive
the multiplexer. Also, the other channels of the multiplexer will
be undisturbed by the overvoltage and will continue to operate
normally.
Q1 Q2 Q3
+55V
OVERVOLTAGE
n-CHANNEL
MOSFET IS
OFF
VDD VSS
00035-017
Figure 17. +55 V Overvoltage Input to the On Channel
Q1 Q2 Q3
–40V
OVERVOLTAGE
n-CHANNEL
MOSFET IS
ON p-CHANNEL
MOSFET IS
OFF
VSS VDD
00035-018
Figure 18. −40 V Overvoltage on an Off Channel with
Multiplexer Power On
Q1 Q2 Q3
+55V
OVERVOLTAGE
n-CHANNEL
MOSFET IS
OFF
00035-019
Figure 19. +55 V Overvoltage with Power Off
Q1 Q2 Q3
–40V
OVERVOLTAGE
n-CHANNEL
MOSFET IS
ON p-CHANNEL
MOSFET IS
OFF
00035-020
Figure 20. −40 V Overvoltage with Power Off
ADG508F/ADG509F/ADG528F
Rev. E | Page 12 of 20
TEST CIRCUITS
IDS
S
RON = V1/IDS
V1
V
S
D
0
0035-021
Figure 21. On Resistance
S1
S2
S8
V
D
I
S
(OFF)
V
S
V
DD
V
SS
V
DD
V
SS
D
0.8VEN
A
00035-022
Figure 22. IS (Off)
S1
S2
S8
V
S
I
D
(OFF)
V
D
V
DD
V
SS
V
DD
V
SS
D
0.8VEN
A
00035-023
Figure 23. ID (Off)
S1
S2
S8
V
S
I
D
(ON)
V
D
V
DD
V
SS
V
DD
V
SS
D
2.4VEN
A
00035-025
Figure 24. ID (On)
S1
S2
S8
V
S
V
DD
V
SS
V
DD
V
SS
D
0.8VEN
A
00035-026
Figure 25. Input Leakage Current (with Overvoltage)
A2
0V
0
V
V
DD
V
SS
V
S
D
0
V
A1
A0
EN
RS
GND WR
ADG528F*
S1
S8
A
00035-027
Figure 26. Input Leakage Current (with Power Supplies Off)
ADG508F/ADG509F/ADG528F
Rev. E | Page 13 of 20
A2
V
SS
V
DD
D
V
S1
V
IN
V
S8
V
OUT
A1
A0
EN
RS
GND WR
ADG528F*
S1
S8
S2 TO S7
2.4V
50Ω
R
L
1MΩ
C
L
35pF
V
SS
V
DD
*SIMILAR CONNECTION FOR ADG508F/ADG509F.
3V
50%
V
OUT
t
TRANSITION
90%
90%
t
TRANSITION
ADDRESS
DRIVE (V
IN
)50%
00035-024
Figure 27. Switching Time of Multiplexer, tTRANSITION
A2
V
SS
V
DD
D
V
S
V
IN
V
OUT
A1
A0
EN
RS
GND WR
ADG528F*
S1
S8
S2 TO S7
2.4V
50Ω
R
L
1kΩ
C
L
35pF
V
SS
V
DD
ADDRESS
DRIVE (V
IN
)
3V
V
OUT
t
OPEN
80% 80%
*SIMILAR CONNECTION FOR ADG508F/ADG509F.
00035-029
Figure 28. Break-Before-Make Delay, tOPEN
A2
V
SS
V
DD
D
V
S
IN
V
OUT
A1
A0
EN
RS
GND WR
ADG528F*
S1
S2 TO S8
R
L
1kΩ
C
L
35pF
V
SS
V
DD
ENABLE
DRIVE (V
IN
)
3V
0V
0V
V
O
OUTPUT
t
ON
(EN)
t
OFF
(EN)
50%50%
0.9V
O
V
RS
*SIMILAR CONNECTION FOR ADG508F/ADG509F.
00035-030
Figure 29. Enable Delay, tON (EN), tOFF (EN)
A2
VSS
VDD
D
VS
VRS
VOUT
A1
A0
EN
2.4V
RS
GND
WR
ADG528F
S1
S2 TO S8
RL
1kΩ
CL
35pF
V
SS
V
DD
WR
3V
50%
0V
0V
V
O
OUTPUT
VWR
t
ON (WR)
0.2VO
00035-031
Figure 30. Write Turn-On Time, tON (WR)
ADG508F/ADG509F/ADG528F
Rev. E | Page 14 of 20
A2
VDD
V
DD
VSS
V
SS
D
VS
VIN
VOUT
A1
A0
EN2.4V
RS
GND WR
ADG528F*
*
SIMILAR CONNECTION FOR ADG508F/ADG509F.
S1
S2 TO S8
RL
1kΩ
CL
35pF
RS
3V
0V
50% 50%
0V
V
O
SWITCH
OUTPUT
t
RS
t
OFF
(RS)
0.8V
O
00035-032
Figure 31. Reset Turn-Off Time, tOFF (RS)
3V
V
OUT
LOGIC
INPUT (V
IN
)
Q
INJ
= C
L
× ΔV
OUT
0V
A2
V
OUT
D
*SIMILAR CONNECTION FOR ADG508F/ADG509F.
A1
A0
EN
RS
GND WR
ADG528F*
2.4V
S
C
L
1nF
V
S
V
SS
V
SS
V
DD
V
DD
V
IN
R
S
ΔV
OUT
00035-033
Figure 32. Charge Injection
A2
V
DD
V
DD
V
SS
V
SS
V
IN
DV
OUT
A1
A0
EN
2.4V RS
GND WR
S1
S8
R
L
1kΩ
0
0035-034
ADG528F*
*SIMILAR CONNECTION FOR ADG508F/ADG509F.
Figure 33. Off Isolation
ADG508F/ADG509F/ADG528F
Rev. E | Page 15 of 20
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
COMPLIANT TO JEDEC STANDARDS MS-001-AB
073106-B
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
OUTLINE DIMENSIONS
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
16
18
9
0.100 (2.54)
BSC
0.800 (20.32)
0.790 (20.07)
0.780 (19.81)
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.060 (1.52)
MAX
0.430 (10.92)
MAX
0.210 (5.33)
MAX
SEATING
PLANE
0.015
(0.38)
MIN
0.005 (0.13)
MIN
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
Figure 34. 16-Lead Plastic Dual In-Line Package [PDIP] Narrow Body
(N-16)
Dimensions shown in inches and (millimeters)
COMPLIANT TO JEDEC STANDARDS MS-012-AC
10.00 (0.3937)
9.80 (0.3858)
16 9
8
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
1.27 (0.0500)
BSC
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0039)
0.51 (0.0201)
0.31 (0.0122)
1.75 (0.0689)
1.35 (0.0531)
0.50 (0.0197)
0.25 (0.0098)
1.27 (0.0500)
0.40 (0.0157)
0.25 (0.0098)
0.17 (0.0067)
COPLANARITY
0.10
8°
0°
060606-A
45°
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 35. 16-Lead Standard Small Outline Package [SOIC-N] Narrow Body
(R-16)
Dimensions shown in millimeters and (inches)
ADG508F/ADG509F/ADG528F
Rev. E | Page 16 of 20
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013- AA
032707-B
10.50 (0.4134)
10.10 (0.3976)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75 (0.0295)
0.25 (0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
C
OPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
16 9
8
1
1.27 (0.0500)
BSC
Figure 36. 16-Lead Standard Small Outline Package [SOIC-W] Wide Body
(RW-16)
Dimensions shown in millimeters and (inches)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
COMPLIANT TO JEDEC STANDARDS MS-001
070706-A
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
18
19
10
0.100 (2.54)
BSC
0.920 (23.37)
0.900 (22.86)
0.880 (22.35)
0.210 (5.33)
MAX
SEATING
PLANE
0.015
(0.38)
MIN
0.005 (0.13)
MIN
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.060 (1.52)
MAX
0.430 (10.92)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.015 (0.38)
GAUGE
PLANE
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
Figure 37. 18-Lead Plastic Dual In-Line Package [PDIP] Narrow Body
(N-18)
Dimensions shown in inches and (millimeters)
ADG508F/ADG509F/ADG528F
Rev. E | Page 17 of 20
COMPLIANT TO JEDEC STANDARDS MO-047-AA
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
0.020 (0.50)
R
BOTTOM
VIEW
(PINS UP)
0.021 (0.53)
0.013 (0.33) 0.330 (8.38)
0.290 (7.37)
0.032 (0.81)
0.026 (0.66)
0.056 (1.42)
0.042 (1.07) 0.20 (0.51)
MIN
0.120 (3.04)
0.090 (2.29)
3
4
19
18
8
9
14
13
TOP VIEW
(PINS DOWN)
0.395 (10.03)
0.385 (9.78) SQ
0.356 (9.04)
0.350 (8.89) SQ
0.048 (1.22 )
0.042 (1.07)
0.048 (1.22)
0.042 (1.07)
0.020
(0.51)
R
0.050
(1.27)
BSC
0.180 (4.57)
0.165 (4.19)
0.045 (1.14)
0.025 (0.64) R
PIN 1
IDENTIFIER
Figure 38. 20-Lead Plastic Leaded Chip Carrier [PLCC]
(P-20)
Dimensions shown in inches and (millimeters)
16 9
81
PIN 1
SEATING
PLANE
8°
0°
4.50
4.40
4.30
6.40
BSC
5.10
5.00
4.90
0.15
0.05
0.65
BSC
1.20
MAX
0.20
0.09 0.75
0.60
0.45
0.30
0.19
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 39. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
ADG508F/ADG509F/ADG528F
Rev. E | Page 18 of 20
ORDERING GUIDE
Model Temperature Range Package Description Package Option
ADG508FBN −40°C to +85°C 16-Lead PDIP N-16
ADG508FBNZ −40°C to +85°C 16-Lead PDIP N-16
ADG508FBRN −40°C to +85°C 16-Lead SOIC_N R-16
ADG508FBRN–REEL7 −40°C to +85°C 16-Lead SOIC_N R-16
ADG508FBRNZ −40°C to +85°C 16-Lead SOIC_N R-16
ADG508FBRNZ–REEL7 −40°C to +85°C 16-Lead SOIC_N R-16
ADG508FBRW −40°C to +85°C 16-Lead SOIC_W RW-16
ADG508FBRWZ −40°C to +85°C 16-Lead SOIC_W RW-16
ADG508FBRWZ-REEL −40°C to +85°C 16-Lead SOIC_W RW-16
ADG508FBRUZ −40°C to +85°C 16-Lead TSSOP RU-16
ADG508FBRUZ-REEL7 −40°C to +85°C 16-Lead TSSOP RU-16
ADG509FBN −40°C to +85°C 16-Lead PDIP N-16
ADG509FBNZ −40°C to +85°C 16-Lead PDIP N-16
ADG509FBRN −40°C to +85°C 16-Lead SOIC_N R-16
ADG509FBRN–REEL7 −40°C to +85°C 16-Lead SOIC_N R-16
ADG509FBRNZ −40°C to +85°C 16-Lead SOIC_N R-16
ADG509FBRNZ–REEL7 −40°C to +85°C 16-Lead SOIC_N R-16
ADG509FBRW −40°C to +85°C 16-Lead SOIC_W RW-16
ADG509FBRW-REEL −40°C to +85°C 16-Lead SOIC_W RW-16
ADG509FBRWZ −40°C to +85°C 16-Lead SOIC_W RW-16
ADG509FBRWZ-REEL −40°C to +85°C 16-Lead SOIC_W RW-16
ADG509FBRUZ −40°C to +85°C 16-Lead TSSOP RU-16
ADG509FBRUZ-REEL7 −40°C to +85°C 16-Lead TSSOP RU-16
ADG528FBN −40°C to +85°C 18-Lead PDIP N-18
ADG528FBNZ −40°C to +85°C 18-Lead PDIP N-18
ADG528FBP −40°C to +85°C 20-Lead PLCC P-20
ADG528FBP-REEL −40°C to +85°C 20-Lead PLCC P-20
ADG528FBPZ −40°C to +85°C 20-Lead PLCC P-20
ADG508F/ADG509F/ADG528F
Rev. E | Page 19 of 20
NOTES
ADG508F/ADG509F/ADG528F
Rev. E | Page 20 of 20
NOTES
©2001–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00035-0-7/09(E)