September 2010 Doc ID 13317 Rev 5 1/34
34
RHF1401
Rad-hard 14-bit 30 Msps A/D converter
Features
■Qml-V qualified, smd 5962-06260
■Rad hard: 300 kRad(Si) TID
■Failure immune (SEFI) and latchup immune
(SEL) up to 120 MeV-cm2/mg at 2.7 V and
125° C
■Hermetic package
■Tested at Fs=20Msps
■Low power: 85 mW at 20 Msps
■Optimized for 2 Vpp differential input
■High linearity and dynamic performances
■2.5 V/3.3 V compatible digital I/O
■Internal reference voltage with external
reference option
Applications
■Digital communication satellites
■Space data acquisition systems
■Aerospace instrumentation
■Nuclear and high-energy physics
Description
The RHF1401 is a 14-bit analog-to-digital
converter that uses pure (ELDRS-free) CMOS
0.25 µm technology combining high performance,
radiation robustness and very low power
consumption. The RHF1401 is based on a
pipeline structure and digital error correction to
provide excellent static linearity.
Specifically designed to optimize power
consumption, the RHF1401 only dissipates
85 mW at 20 Msps, while maintaining a high level
of performance.
The device integrates a proprietary track-and-hold
structure to ensure a large effective resolution
bandwidth.
Voltage references are integrated in the circuit to
simplify the design and minimize external
components. A tri-state capability is available on
the outputs to allow common bus sharing. A data-
ready signal, which is raised when the data is
valid on the output, can be used for
synchronization purposes.
The RHF1401 has an operating temperature
range of -55° C to +125° C and is available in a
small 48-pin ceramic SO-48 package.
Ceramic SO-48 package
www.st.com
Contents RHF1401
2/34 Doc ID 13317 Rev 5
Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4 Equivalent circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5 Timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
5.1 Digital output load considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
6 Absolute maximum ratings and operating conditions . . . . . . . . . . . . 10
7 Electrical characteristics (after 300 kRad) . . . . . . . . . . . . . . . . . . . . . . 11
7.1 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1.1 Digital inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.1.2 Digital outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.2 Driving the analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.3 Reference connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.3.1 Internal reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.3.2 External reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.4 Clock input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.5 Power consumption optimization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
7.6 PCB layout precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
8 Definitions of specified parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.1 Static parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.2 Dynamic parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
9 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
10 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
RHF1401 Block diagram
Doc ID 13317 Rev 5 3/34
1 Block diagram
Figure 1. RHF1401 block diagram
AM04556
VIN
INCM
VINB
CLK
GND
OR
D13
D0
DR
OEB
DFSB
VREFM
IPOL
GNDA
VREFP
stage
1
stage
2
stage
n
Digital data correction
Buffers
Reference
circuits
Sequencer-phase shifting
Timing
VCCBI VCCBE
INCM
REFMODE
Pin connections RHF1401
4/34 Doc ID 13317 Rev 5
2 Pin connections
Figure 2. pin connections (top view)
GNDBI
GNDBE
VCCBE
NC
NC
OR
(MSB)D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
(LSB)D0
DR
VCCBE
GNDBE
VCCBI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
DGND
DGND
CLK
DGND
DVCC
DVCC
AVCC
AVCC
AGND
INCM
AGND
VINB
AGND
VIN
AGND
VREFM
VREFP
IPOL
AGND
AVCC
AVCC
DFSB
OEB
REFMODE
RHF1401 Pin descriptions
Doc ID 13317 Rev 5 5/34
3 Pin descriptions
Table 1. Pin descriptions
Pin Name Description Observations Pin Name Description Observations
1 GNDBI Digital buffer ground 0 V 25 REFMODE Ref. mode control input 2.5 V/3.3 V CMOS
input
2 GNDBE Digital buffer ground 0 V 26 OEB Output enable input 2.5 V/3.3 V CMOS
input
3VCCBE
Digital buffer power
supply 2.5 V/3.3 V 27 DFSB Data format select input 2.5 V/3.3 V CMOS
input
4NC Not connected to the
dice 28 AVCC Analog power supply 2.5 V
5NC Not connected to the
dice 29 AVCC Analog power supply 2.5 V
6 OR Out of range output CMOS output
(2.5 V/3.3 V) 30 AGND Analog ground 0 V
7 D13(MSB) Most significant bit
output
CMOS output
(2.5 V/3.3 V) 31 IPOL Analog bias current input
8 D12 Digital output CMOS output
(2.5 V/3.3 V) 32 VREFP Top voltage reference Can be external or
internal
9 D11 Digital output CMOS output
(2.5 V/3.3 V) 33 VREFM Bottom voltage reference 0 V
10 D10 Digital output CMOS output
(2.5 V/3.3 V) 34 AGND Analog ground 0 V
11 D9 Digital output CMOS output
(2.5 V/3.3 V) 35 VIN Analog input 1 Vpp
12 D8 Digital output CMOS output
(2.5 V/3.3 V) 36 AGND Analog ground 0 V
13 D7 Digital output CMOS output
(2.5 V/3.3 V) 37 VINB Inverted analog input 1 Vpp
14 D6 Digital output CMOS output
(2.5 V/3.3 V) 38 AGND Analog ground 0 V
15 D5 Digital output CMOS output
(2.5 V/3.3 V) 39 INCM Input common mode Can be external or
internal
16 D4 Digital output CMOS output
(2.5 V/3.3 V) 40 AGND Analog ground 0 V
17 D3 Digital output CMOS output
(2.5V /3.3 V) 41 AVCC Analog power supply 2.5 V
18 D2 Digital output CMOS output
(2.5 V/3.3 V) 42 AVCC Analog power supply 2.5 V
19 D1 Digital output CMOS output
(2.5 V/3.3 V) 43 DVCC Digital power supply 2.5 V
20 D0(LSB) Digital output LSB CMOS output
(2.5 V/3.3 V) 44 DVCC Digital power supply 2.5 V
21 DR Data ready output(1) CMOS output
(2.5 V/3.3 V) 45 DGND Digital ground 0 V
22 VCCBE Digital buffer power
supply 2.5 V/3.3 V 46 CLK Clock input 2.5 V compatible
CMOS input
23 GNDBE Digital buffer ground 0 V 47 DGND Digital ground 0 V
24 VCCBI Digital buffer power
supply 2.5 V 48 DGND Digital ground 0 V
1. See load considerations in Chapter 5: Timing characteristics.
Equivalent circuits RHF1401
6/34 Doc ID 13317 Rev 5
4 Equivalent circuits
Figure 3. Analog inputs Figure 4. Output buffers
AM04557
VIN or VINB
(pad)
AVCC
AGND
7 pF
AM04558
D0 …D13
7 pF
(pad)
VCCBE
GNDBE
AGND
OEB
Data
AVCC
Figure 5. Clock input Figure 6. Data format input
AM04559
CLK
7 pF
(pad)
DVCC
DGND
AM04560
DFSB
7 pF
(pad)
VCCBE
GNDBE
Figure 7. Reference mode control input Figure 8. Output enable input
AM04561
REFMODE
7 pF
(pad)
VCCBE
GNDBE
AM04562
OEB
7 pF
(pad)
VCCBE
GNDBE
RHF1401 Equivalent circuits
Doc ID 13317 Rev 5 7/34
Figure 9. VREFP and INCM input
Figure 10. VREFM input
AM04563
VREFP
7 pF
(pad)
AVCC
AGND
INCM
7 pF
(pad)
AVCC
AGND
REFMODE REFMODE
AM04564
VREFM
AVCC
AGND
7 pF
(pad)
High input impedance
Timing characteristics RHF1401
8/34 Doc ID 13317 Rev 5
5 Timing characteristics
Figure 11. Timing diagram
The input signal is sampled on the rising edge of the clock while the digital outputs are
synchronized on the falling edge of the clock. The duty cycles on DR and CLK are the same.
Table 2. Timing characteristics
Symbol Parameter Test conditions Min Typ Max Unit
DC Clock duty cycle Fs = 20 Msps 45 50 65 %
Tod
Data output delay (fall of
clock to data valid) (1)
1. As per Figure 11.
10 pF load capacitance 5 7.5 13 ns
Tpd Data pipeline delay(2)
2. If the duty cycle does not equal 50%: Tpd = 7 cycles + CLK pulse width.
Duty cycle = 50% 7.5 7.5 7.5 cycles
Ton
Falling edge of OEB to
digital output valid data 1ns
Toff
Rising edge of OEB to
digital output tri-state 1ns
TrD Data rising time 10 pF load capacitance 6 ns
TfD Data falling time 10 pF load capacitance 3 ns
N-2
N-1
NN+1
N+2
N+3
N+4
N+5 N+6
N+7
N+8
N-8N-7 N-6 NN-5 N -4 N+1N-3N-1
HZ state
Analog
input
CLK
OEB
Data
output
DR
Toff Ton
Tpd + Tod
Tod
AM06120
OR
Tod
RHF1401 Timing characteristics
Doc ID 13317 Rev 5 9/34
The rising and falling edges of the OR pin are synchronized with the falling edge of the DR
pin.
5.1 Digital output load considerations
The features of the internal output buffers limit the maximum load on the digital data output.
In particular, the shape and amplitude of the Data Ready signal, toggling at the clock
frequency, can be weakened by a higher equivalent load.
In applications that impose higher load conditions, it is recommended to use the falling edge
of the master clock instead of the Data Ready signal. This is possible because the output
transitions are internally synchronized with the falling edge of the clock.
Figure 12. Output buffer fall time Figure 13. Output buffer rise time
0 5 10 15 20 25 30 35 40 45 50
0
5
10
15
20
fall time (ns)
capa-load (pF)
0 5 10 15 20 25 30 35 40 45 50
0
5
10
15
20
rise time (ns)
capa-load (pF)
Absolute maximum ratings and operating conditions RHF1401
10/34 Doc ID 13317 Rev 5
6 Absolute maximum ratings and operating conditions
Table 3. Absolute maximum ratings
Symbol Parameter Values Unit
AVCC Analog supply voltage 3.3 V
DVCC Digital supply voltage 3.3 V
VCCBI Digital buffer supply voltage 3.3 V
VCCBE Digital buffer supply voltage 3.6 V
VIN
VINB
Analog inputs: bottom limit −> top limit -0.6 V −> AVCC+0.6 V V
VREFP
VINCM
External references: bottom limit −> top limit -0.6 V −> AVCC+0.6 V V
IDout Digital output current -100 to 100 mA
Tstg Storage temperature -65 to +150 °C
Rthjc Thermal resistance junction to case 22 °C/W
Rthja Thermal resistance junction to ambient 125 °C/W
ESD HBM (human body model)(1)
1. Human body model: a 100 pF capacitor is charged to the specified voltage, then discharged through a
1.5 kΩ resistor between two pins of the device. This is done for all couples of connected pin combinations
while the other pins are floating.
2kV
Table 4. Operating conditions
Symbol Parameter Min Typ Max Unit
AVCC Analog supply voltage 2.3 2.5 2.7 V
DVCC Digital supply voltage 2.3 2.5 2.7 V
VCCBI Digital internal buffer supply 2.3 2.5 2.7 V
VCCBE Digital output buffer supply 2.3 2.5 3.4 V
VREFP Forced top voltage reference 0.8 1.4 V
VREFM Bottom internal reference voltage 0 0 0.5 V
VINCM Forced common mode voltage 0.2 1.1 V
VIN
VIN max. voltage versus GND 1.6 V
VIN min. voltage versus GND -0.2 V
VINB
VINB max. voltage versus GND 1.6 V
VINB min. voltage versus GND -0.2 V
DFSB
Digital inputs (see Ta bl e 9 for thresholds) 0 VCCBE VREFMODE
OEB
RHF1401 Electrical characteristics (after 300 kRad)
Doc ID 13317 Rev 5 11/34
7 Electrical characteristics (after 300 kRad)
Unless otherwise specified, the test conditions in the following tables are:
AVCC = DVCC = VCCBI =VCCBE = 2.5 V, Fs=20 Msps, FIN= 15 MHz, VIN at -1 dBFS,
VREFM = 0 V, Tamb = 25°C.
Table 5. Analog inputs
Symbol Parameter Test conditions Min Typ Max Unit
VIN-VINB
Full-scale reference voltage
(FS)(1)
1. See Chapter 8: Definitions of specified parameters on page 29 for more information.
VREFP = 1 V
(forced) 2V
pp
CIN Input capacitance 7 pF
ZIN Input impedance Fs = 20 Msps 3.3 kΩ
ERB Effective resolution bandwidth(1) 70 MHz
Table 6. Internal reference voltage
Symbol Parameter Test conditions Min Typ Max Unit
Rout
Output resistance of internal
reference
REFMODE = 0
internal reference
on
30 Ω
REFMODE = 1
internal reference
off
7.5 kΩ
VREFP Top internal reference voltage(1)
1. VREFM connected to GND.
REFMODE = 0 0.76 0.84 0.95 V
VINCM Input common mode voltage REFMODE = 0 0.40 0.44 0.50 V
Table 7. External reference voltage(1)
1. See Figure 14.
Symbol Parameter Test conditions Min Typ Max Unit
VREFP Forced top reference voltage REFMODE = 1 0.8 1.4 V
VREFM Forced bottom ref voltage REFMODE = 1 0 0.5 V
VINCM Forced common mode voltage REFMODE = 1 0.2 1.1 V
Table 8. Static accuracy
Symbol Parameter Test conditions Min Typ Max Unit
DNL Differential non-linearity(1)
1. See Figure 33 and Chapter 8 for more information. This parameter is not tested.
Fin = 1.5 Msps
Vin at -1 dBFS
Fs=1.5 Msps
±0.4 LSB
INL Integral non-linearity(2)
2. See Figure 34 and Chapter 8 for more information. This parameter is not tested.
±3 LSB
Monotonicity and no missing
codes Guaranteed
Electrical characteristics (after 300 kRad) RHF1401
12/34 Doc ID 13317 Rev 5
Higher values of SNR, SINAD and ENOB can be obtained by increasing the full-scale range
of the analog input. This is illustrated in Figure 51 and Figure 52 with VREFP =1.25V.
Table 9. Digital inputs and outputs
Symbol Parameter Test conditions Min Typ Max Unit
Clock input
CT Clock threshold DVCC = 2.5 V 1.25 V
CA Square clock amplitude
(DC component = 1.25 V) DVCC = 2.5 V 0.8 2.5 Vp-p
Digital inputs
VIL Logic "0" voltage VCCBE = 2.5 V 0 0.25 x
VCCBE
V
VIH Logic "1" voltage VCCBE = 2.5 V 0.75 x
VCCBE
VCCBE V
Digital outputs
VOL Logic "0" voltage IOL = -10 µA 0 0.25 V
VOH Logic "1" voltage IOH = 10 µA VCCBE
-0.25 V
IOZ
High impedance leakage
current OEB set to VIH -15 15 µA
CLOutput load capacitance High CLK
frequencies 15 pF
Table 10. Dynamic characteristics
Symbol Parameter Test conditions Min Typ Max Unit
SFDR Spurious free dynamic range
Fin = 15 MHz
Fs = 20 Msps
Vin at -1 dBFS
internal references
CL = 6 pF
70 91 dBFS
SNR Signal to noise ratio 66 70 dB
THD Total harmonic distortion 70 86 dB
SINAD Signal to noise and distortion
ratio 65 70 dB
ENOB Effective number of bits 10.6 11.5 bits
RHF1401 Electrical characteristics (after 300 kRad)
Doc ID 13317 Rev 5 13/34
Figure 14. Differential input configuration
AM04565
Differential
input signal
VIN
VINB
INCM
REFM
REFP
Ground
External or internal
External or
internal
2.5 V
VCCBE
VCCBI
AVCC
DVCC
Figure 15. ENOB vs. input freq., square clock Figure 16. SINAD vs. input freq., square clock
1k 10k 100k 1M 10M 100M
8
9
10
11
12
Ω
Ω
Ω
Ω
ENOB (#bit)
Input Frequency (Hz)
1k 10k 100k 1M 10M 100M
-80
-70
-60
-50
-40
Ω
Ω
Ω
Ω
SINAD (dB)
Input Frequency (Hz)
Figure 17. THD vs. input freq., square clock Figure 18. SNR vs. input freq., square clock
1k 10k 100k 1M 10M 100M
-100
-90
-80
-70
-60
-50
-40
-30
Ω
Ω
Ω
Ω
THD (dB)
Input Frequency (Hz)
1k 10k 100k 1M 10M 100M
-80
-70
-60
-50
-40
Ω
Ω
Ω
Ω
SNR (dB)
Input Frequency (Hz)
Electrical characteristics (after 300 kRad) RHF1401
14/34 Doc ID 13317 Rev 5
Figure 19. SFDR vs. input freq., square clock Figure 20. ENOB vs. VCCBE
1k 10k 100k 1M 10M 100M
-100
-90
-80
-70
-60
-50
-40
-30
Ω
Ω
Ω
Ω
SFDR (dB)
Input Frequency (Hz)
9.5
10
10.5
11
11.5
1.E+07 2.E+07 3.E+07 4.E+07
ENOB (bits)
Sampling Frequency (Hz)
Fin = 15MHz - square clock
VccBE=2.5V
VccBE=3.3V
Figure 21. ENOB vs. input freq., ext. ref. Figure 22. ENOB vs. REFP
1k 10k 100k 1M 10M 100M
8
9
10
11
12
Ω
Ω
ENOB (#bit)
Input Frequency (Hz)
1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4
8
9
10
11
12
Ω
Ω
ENOB (#bit)
REFP (V)
Figure 23. ENOB vs. clock duty cycle Figure 24. ENOB vs. INCM
0 102030405060708090100
7
8
9
10
11
12
Ω
Ω
ENOB (#bit)
Clock duty cycle (%)
0.30.4 0.5 0.6 0.7 0.80.9 1.0
8
9
10
11
12
Ω
ENOB (#bit)
INCM (V)
Differential sine wave input
RHF1401 Electrical characteristics (after 300 kRad)
Doc ID 13317 Rev 5 15/34
Figure 25. ENOB vs. Vin Figure 26. ENOB vs. square clock, diff. input
0.0 0.5 1.0 1.5 2.0 2.5
8
9
10
11
12
ENOB (#bit)
Vin (Vp-p)
110
8
9
10
11
12
ENOB (#bit)
Clock Frequency (Msps)
Figure 27. SFDR vs. square clock, diff. input Figure 28. SINAD vs. square clock, diff. input
110
50
55
60
65
70
75
80
85
90
95
SFDR (dB)
Clock Frequency (Msps)
110
-75
-70
-65
-60
-55
-50
-45
SINAD (dB)
Clock Frequency (Msps)
Figure 29. THD vs. square clock, diff. input Figure 30. SNR vs. square clock, diff. input
110
50
55
60
65
70
75
80
85
90
THD (dB)
Clock Frequency (Msps)
110
-75
-70
-65
-60
-55
-50
SNR (dB)
Clock Frequency (Msps)
Electrical characteristics (after 300 kRad) RHF1401
16/34 Doc ID 13317 Rev 5
Figure 31. ENOB vs. sine clock, diff. input Figure 32. Clock threshold vs. temperature
1M 10M 100M
8
9
10
11
12
ENOB (#bit)
Clock Frequency (Msps)
-60 -40 -20 0 20 40 60 80 100 120 140
1.22
1.23
1.24
1.25
1.26
1.27
1.28
Clock threshold (V)
Temperature (°C)
Figure 33. DNL, differential input Figure 34. INL, differential input
DNL (LSB)
INL (LSB)
RHF1401 Electrical characteristics (after 300 kRad)
Doc ID 13317 Rev 5 17/34
Figure 35. Single-ended input configuration
AM04566
Single-ended
input signal
Ground
External or internal
External or
internal
2.5 V
VIN
VINB
INCM
REFM
REFP
VCCBE
VCCBI
AVCC
DVCC
Figure 36. ENOB vs. Fin, single-ended Figure 37. SINAD vs. Fin, single-ended
100k 1M 10M
7
8
9
10
11
12
Ω
ENOB (#bit)
Input Frequency (Hz)
100k 1M 10M
-80
-70
-60
-50
-40
Ω
SINAD (dBc)
Input Frequency (Hz)
Figure 38. THD vs. Fin, single-ended Figure 39. SNR vs. Fin, single-ended
100k 1M 10M
50
60
70
80
90
Ω
THD (dB)
Input Frequency (Hz)
100k 1M 10M
-80
-70
-60
-50
-40
Ω
SNR (dB)
Input Frequency (Hz)
Electrical characteristics (after 300 kRad) RHF1401
18/34 Doc ID 13317 Rev 5
Figure 40. SFDR vs. Fin, single-ended
100k 1M 10M
50
60
70
80
90
Ω
SFDR (dB)
Input Frequency (Hz)
RHF1401 Electrical characteristics (after 300 kRad)
Doc ID 13317 Rev 5 19/34
7.1 Operating modes
Extra functionalities are provided to simplify the application board as much as possible. The
operating modes offered by the RHF1401 are described in Ta bl e 1 1 .
7.1.1 Digital inputs
Data format select bit (DFSB): when set to low level (VIL), the digital input DFSB provides
a two’s complement digital output MSB. This can be of interest when performing some
further signal processing. When set to high level (VIH), DFSB provides standard binary
output coding.
Output enable bit (OEB): when set to low level (VIL), all digital outputs remain active. When
set to high level (VIH), all digital output buffers are in a high impedance state while the
converter goes on sampling. When OEB is set to a low level again, the data arrives on the
output with a very short Ton delay. This feature enables the chip select of the device.
Figure 11 on page 8 summarizes this functionality.
Reference mode control (REFMODE): this allows the internal or external settings of the
voltage references VREFP and INCM. REFMODE = 0 for internal references,
REFMODE = 1 for external references (and disables both references VREFP and INCM).
7.1.2 Digital outputs
Out of range (OR): this function is implemented on the output stage in order to set an "out-
of-range" flag whenever the digital data is over the full-scale range. Typically, there is a
detection of all data at ‘0’ or all data at ‘1’. It sets an output signal OR, which is in a low level
state (VOL) when the data stays within the range, or in a high-level state (VOH) when the
data is out of range.
Data ready (DR): the Data Ready output is an image of the clock being synchronized on the
output data (D0 to D13). This is a very helpful signal that simplifies the synchronization of
the measurement equipment or of the controlling DSP. Like all other digital outputs, DR goes
into high impedance when OEB is set to a high level, as shown in Figure 11 on page 8.
Table 11. RHF1401 operating modes
Inputs Outputs
Analog input differential
amplitude DFSB OEB OR DR Most significant bit (MSB)
(VIN-VINB) above maximum range HLHCLKD13
L L H CLK D13 complemented
(VIN-VINB) below minimum range HLHCLKD13
L L H CLK D13 complemented
(VIN-VINB) within range HLLCLKD13
L L L CLK D13 complemented
XXH
HZ
(1)
1. High impedance.
HZ HZ (all digital outputs are in high
impedance)
Electrical characteristics (after 300 kRad) RHF1401
20/34 Doc ID 13317 Rev 5
7.2 Driving the analog input
Figure 41. Equivalent VIN - VINB (differential input)
Figure 42. Maximum input swing on each VIN or VINB input
Figure 43. Optimized single-ended configuration (DC coupling), external REFP
AM04567
INCM (level 0, code 8191)
(level - FS, code 0)
(level + FS, code 16383)
FS (full-scale)
= 2(VREFP - VREFM)
VIN
VINB
VIN -VINB
AM04568
+1.6 V (high input rail)
0 V (ground)
- 0.2 V (low input rail)
AM04569
VIN
VINB
External
VIN
INCM
Ground
INCM
VIN -VINB
REFM
+1.6 V (high input rail)
INCM
0 V (ground)
- 0.2 V (low input rail)
Vp -p
REFP
External
RHF1401 Electrical characteristics (after 300 kRad)
Doc ID 13317 Rev 5 21/34
The RHF1401 is designed for use in a differential input configuration. Nevertheless, it can
achieve good performance in a single-ended input configuration. In single-ended, a good
quality conversion can be achieved by using an input amplitude up to 1.4 Vp-p by using the
external references INCM and VREFP at 0.7 V and 1 V respectively (see Figure 35 on
page 17).
Figure 44. 2 Vp-p differential input
The RHF1401 is designed to obtain optimum performance when driven on differential inputs
with a differential amplitude of two volts peak-to-peak (2 Vp-p). This is the result of 1 Vp-p on
the VIN and VINB inputs in phase opposition.
The RHF1401 is specifically designed to meet sampling requirements for intermediate
frequency (IF) input signals. In particular, the track-and-hold in the first stage of the pipeline
is designed to minimize the linearity limitations as the analog frequency increases. This is
achieved by making the input impedance independent of the input frequency.
Figure 45 on page 22 shows a differential input solution. The input signal is fed to the
transformer’s primary, while the secondary drives both ADC inputs. The transformer must be
50 Ω matched (for proper matching with a 50 Ω generator). Tracks between the secondary
and VIN and VINB pins must be as short as possible.
The common-mode voltage of the ADC (INCM) is connected to the center tap of the
transformer’s secondary in order to bias the input signal around the common voltage (see
Table 6 on page 11).The INCM is decoupled to maintain a low noise level on this node.
Ceramic technology for decoupling provides good capacitor stability across a wide
bandwidth.
Table 12. Output codes for DFSB = 1
Vin - Vinb Output code
+ range/2 16383
0 8191
- range/2 0
AM04570
VIN
VINB
1 Vp -p
INCM
(Internal
or external)
1 Vp -p
Ground
REFP
REFM
VIN -VINB (2 Vp-p)
1 V
INCM
INCM
Electrical characteristics (after 300 kRad) RHF1401
22/34 Doc ID 13317 Rev 5
Figure 45. Differential implementation using a balun
Some applications may require a single-ended input, which can easily be achieved with the
configuration shown in Figure 46. However, with this type of configuration, a degradation in
the rated performance of the RHF1401 may occur, compared with a differential
configuration. A sufficiently decoupled DC reference should be used to bias the RHF1401
inputs. An AC-coupled analog input can also be used and the DC analog level set with a
high value resistor R (10 kΩ to 100 kΩ) connected to a proper DC source. Cin and R behave
like a high-pass filter and are calculated to set the lowest-possible cut-off frequency.
Figure 46. AC-coupling single-ended input configuration
AM04571
100 nF* ceramic
(as close as
possible to
INCM pin)
50 Ω
100 pF
ADT1 -1
1:1
Analog input signal
50 Ω track Short track
470 nF* ceramic
(as close as possible
to the transformer)
External
INCM
(optional)
*the use of a ceramic technology is
preferable for a large bandwidth
stability of the capacitor
VIN
VINB
INCM
(50 Ω output)
AM04572
100 nF ceramic*
(as close as possible
to INCM pin)
R
Cin
Short track
50 Ω
External INCM
(optional)
R
VIN
VINB
INCM
Short track
470 pF
ceramic*
100 nF
ceramic*
*the use of a ceramic technology is
preferable for a large bandwidth
stability of the capacitor
Analog input signal
(50 Ω output)
50 Ω track
RHF1401 Electrical characteristics (after 300 kRad)
Doc ID 13317 Rev 5 23/34
Figure 47. AC-coupling single-ended input configuration for low frequencies
The C capacitor (in the range of 33 pF for example) is dedicated to a low input frequency
range. This capacitor is efficient in reducing noise in the higher frequencies. When coupled
with the resistors, R and C together behave like a high-pass filter. For example, if R = 10 k
and C = 33 pF, the cut-off frequency of this filter equals 482 kHz.
AM04573
100 nF ceramic*
(as close as possible
to INCM pin)
R
Short track
50 Ω
External INCM
(optional)
*ceramic technology for a large
bandwidth stability of the capacitor
R
VIN
VINB
INCM
Short track
C
Analog input signal
(50 Ω output)
50 Ω track
Cin
Electrical characteristics (after 300 kRad) RHF1401
24/34 Doc ID 13317 Rev 5
7.3 Reference connection
7.3.1 Internal reference
In the standard configuration, the ADC is biased with the internal reference voltage. The
VREFM pin is connected to the analog ground while VREFP is internally set to a voltage close
to 1.0 V. VREFP should be decoupled so as to minimize low and high frequency noise. Like
VREFP
, INCN is internal and can be fixed externally. Figure 48 shows the schematic.
Figure 48. Internal reference setting
7.3.2 External reference
An external reference voltage can be used for specific applications requiring even better
linearity or enhanced temperature behavior (see Table 6: Internal reference voltage on
page 11). An external voltage reference with the configuration shown in Figure 49 and
Figure 50 can be used to obtain optimum performance. Decoupling is achieved by using
ceramic capacitors, which provide optimum linearity versus frequency.
Note: * The use of ceramic technology is preferable to ensure large bandwidth stability of the
capacitor.
AM04574
470 nF*
100 nF*
VIN
VINB
VREFM
VREFP
As close as possible
the ADC pins
*the use of a ceramic technology is
preferable for a large bandwidth
stability of the capacitor.
Figure 49. External reference setting Figure 50. Example with a zener
AM04575
470 nF*
100 nF*
VIN
VINB
VREFM
VCCA VREFP
As close as possible
the ADC pins
DC
source
AM04576
470 nF*
100 nF*
VIN
VINB
VREFM
VCCA VREFP
R
As close as possible
the ADC pins
RHF1401 Electrical characteristics (after 300 kRad)
Doc ID 13317 Rev 5 25/34
In multi-channel applications, the high impedance input of the references allows you to drive
several ADCs with only one voltage reference device.
In the case of a 1.25 V external reference, the full scale is increased to 2.5 Vpp differential.
The improved dynamic performance is shown in Figure 51 and Figure 52.
The magnitude of the analog input common mode should stay close to VREFP/2. Higher
levels will introduce more distortion.
Figure 51. ENOB at REFP = 1.25 V Figure 52. Dynamic performance at REFP = 1.25 V
345678910 20
11.3
11.4
11.5
11.6
11.7
11.8
11.9
12.0
12.1
12.2
12.3
ENOB (#bit)
Clock frequency (Msps)
345678910 20
-100
-95
-90
-85
-80
-75
-70
Dynamic perf. (dB)
Clock frequency (Msps)
Electrical characteristics (after 300 kRad) RHF1401
26/34 Doc ID 13317 Rev 5
7.4 Clock input
The quality of the converter very much depends on the accuracy of the clock input in terms
of jitter. The use of a low jitter crystal-controlled oscillator is recommended.
The following points should also be considered.
●The clock’s power supplies must be independent of the ADC’s output supplies to avoid
digital noise modulation on the output.
●When powered-on, the circuit needs several clock periods to reach its normal operating
conditions.
Figure 53. Clock input schematic
The signal applied to the CLK pin is critical to obtain full performance from the RHF1401.
Below 10 MHz, the sine clock does not have transition times fast enough to achieve good
performances. It is recommended to use a square signal with fast transition times and to
place proper termination resistors as close as possible to the device.
The sampling instant is determined by the clock signal’s rising edge. The jitter associated
with this instant must be as low as possible to avoid SNR degradation on fast moving input
signals. To make sure any error is less than 0.5 LSB, the total jitter Tj must satisfy the
following condition for a full-scale input signal.
For example, the total jitter with a 14-bit resolution for a 10 MHz full-scale input should be no
more than 1 picosecond (rms).
In most cases, the clock signal jitter is responsible for noise. Therefore, you must pay
attention to the clock signal when fast signals are acquired with a low frequency clock.
AM04577
50 Ω
CLK
DVcc/2
DVcc/2
Square clock
Sine clock Short track
CLK
Short track
50 Ω
50 Ω clock generator
Tj
1
πFin 2n1+
⋅⋅
---------------------------------------
<
RHF1401 Electrical characteristics (after 300 kRad)
Doc ID 13317 Rev 5 27/34
7.5 Power consumption optimization
The internal architecture of the RHF1401 makes it possible to optimize the power
consumption according to the sampling frequency of the application. For this purpose, an
external Rpol resistor is placed between the IPOL pin and the analog ground. Therefore, the
total dissipation can be adjusted across the entire sampling range to fulfill the requirements
of applications where power saving is critical.
For low sampling frequencies, the resistor value may be adjusted to decrease the analog
current without any deterioration of the dynamic performance.
The current consumption Icca, depending on the value of Rpol, is as shown in Figure 54 for
two different configurations.
●REFMODE = 0
●REFMODE = 1
Figure 54. Analog current consumption vs. Fs according to value of Rpol
0 5 10 15 20 25 30
10
100
Rpol (k ) - Icca (mA)
Sampling Frequency, Fs (Msps)
Electrical characteristics (after 300 kRad) RHF1401
28/34 Doc ID 13317 Rev 5
7.6 PCB layout precautions
●Use of dedicated analog and digital ground planes on the PCB is recommended for
high-speed circuit applications to provide low parasitic inductance and resistance.
Ground planes under the digital pins and layers should be avoided to minimize parasitic
capacitances.
●The separation of the analog signal from clock signal and digital outputs is mandatory
to prevent noise from coupling onto the input signal.
●Power supply bypass capacitors must be placed as close as possible to the IC pins to
improve high-frequency bypassing and reduce harmonic distortion.
●All leads must be as short as possible, especially for the analog input, so as to
decrease parasitic capacitance and inductance.
●To minimize the transition current when the output changes, the capacitive load at the
digital outputs must be reduced as much as possible by using the shortest-possible
routing tracks.
●Choose the smallest-possible component sizes (SMD).
RHF1401 Definitions of specified parameters
Doc ID 13317 Rev 5 29/34
8 Definitions of specified parameters
8.1 Static parameters
Differential non-linearity (DNL)
The average deviation of any output code width from the ideal code width of 1 LSB.
Integral non-linearity (INL)
An ideal converter exhibits a transfer function that is a straight line from the starting code to
the ending code. The INL is the deviation from this ideal line for each transition.
8.2 Dynamic parameters
Spurious free dynamic range (SFDR)
The ratio between the power of the worst spurious signal (not always a harmonic) and the
amplitude of the fundamental tone (signal power) over the full Nyquist band. Expressed in
dBc.
Total harmonic distortion (THD)
The ratio of the rms sum of the first five harmonic distortion components to the rms value of
the fundamental line. Expressed in dB.
Signal to noise ratio (SNR)
The ratio of the rms value of the fundamental component to the rms sum of all other spectral
components in the Nyquist band (Fs/2) excluding DC, fundamental and the first five
harmonics. Reported in dB.
Signal-to-noise and distortion ratio (SINAD)
A similar ratio to the SNR but that includes the harmonic distortion components in the noise
figure (not the DC signal). Expressed in dB. From SINAD, the effective number of bits
(ENOB) can easily be deduced using the formula:
SINAD = 6.02
×
ENOB + 1.76 dB
When the analog input signal is not full-scale (FS) but has an A0 amplitude, the SINAD
expression becomes:
SINAD = 6.02
×
ENOB + 1.76 dB + 20 log (A0 / FS)
Analog input bandwidth
The maximum analog input frequency at which the spectral response of a full power signal
is reduced by 3 dB. Higher values can be achieved with smaller input levels.
Pipeline delay
The delay between the initial sample of the analog input and the availability of the
corresponding digital data output on the output bus. Also called data latency. Expressed as
a number of clock cycles.
Package information RHF1401
30/34 Doc ID 13317 Rev 5
9 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
RHF1401 Package information
Doc ID 13317 Rev 5 31/34
Figure 55. Ceramic SO-48 package mechanical drawing
Table 13. Ceramic SO-48 package mechanical data
Ref.
Dimensions
Millimeters Inches
Min. Typ. Max. Min. Typ. Max.
A 2.18 2.47 2.72 0.086 0.097 0.107
b 0.20 0.254 0.30 0.008 0.010 0.012
c 0.12 0.15 0.18 0.005 0.006 0.007
D 15.57 15.75 15.92 0.613 0.620 0.627
E 9.52 9.65 9.78 0.375 0.380 0.385
E1 10.90 0.429
E2 6.22 6.35 6.48 0.245 0.250 0.255
E3 1.52 1.65 1.78 0.060 0.065 0.070
e 0.635 0.025
f 0.20 0.008
L 12.28 12.58 12.88 0.483 0.495 0.507
P 1.30 1.45 1.60 0.051 0.057 0.063
Q 0.66 0.79 0.92 0.026 0.031 0.036
S1 0.25 0.43 0.61 0.010 0.017 0.024
Ordering information RHF1401
32/34 Doc ID 13317 Rev 5
10 Ordering information
Table 14. Order codes
Note: Contact your local ST sales office for information regarding the specific conditions for
products in die form and QML-Q versions.
Order code SMD pin Quality
level Package Lead
finish Packing Marking EPPL
RHF1401KSO1 - Engineering
model SO-48 Gold Strip
pack RHF1401KSO1 -
RHF1401KSO-01V 5962F0626001VXC QMLV-Flight SO-48 Gold Strip
pack 5962F0626001VXC -
RHF1401 Revision history
Doc ID 13317 Rev 5 33/34
11 Revision history
Table 15. Document revision history
Date Revision Changes
29-Jun-2007 1
First public release.
Failure immune and latchup immune value increased to
120 MeV-cm2/mg.
Updated package mechanical information.
Removed reference to non rad-hard components from External
references, common mode: on page 16.
29-Oct-2007 2
Updated Figure 1: RHF1401 block diagram.
Added explanation on Figure 3: Timing diagram.
Added introduction to Section 6: Typical performance characteristics.
Updated Section 7.2: Clock signal requirements and Section 7.3:
Power consumption optimization.
Added Section 7.4: Low sampling rate recommendations.
Updated information on Data Ready signal in Section 7.5: Digital
inputs/outputs.
Added Figure 24: Impact of clock frequency on RHF1401
performance and Figure 25: CLK signal derivation.
09-Nov-2009 3
Changed input clock features in Table 9 .
Modified Ta b l e 1 3 .
Added Figure 12 to Figure 42.
26-Feb-2010 4
Modified Figure 1: RHF1401 block diagram.
Added details for Tdr and changed values for Tpd in Table 2: Timing
characteristics.
Modified Figure 11: Timing diagram.
Changed values for VREFP in Ta bl e 4 .
Changed Vin operating conditions in Ta b l e 4 , Figure 42 and
Figure 43.
Changed values for DNL in Ta bl e 8 .
13-Sep-2010 5
Modified Figure 1 on page 3 and Figure 9 on page 7.
Added note 2. on page 8.
Modified CIN typ value in Table 5: Analog inputs as per Figure 3.
Modified Figure 11: Timing diagram.
Replaced Figure 20.
Added Table 12: Output codes for DFSB = 1.
Modified Figure44: 2V
p-p differential input.
RHF1401
34/34 Doc ID 13317 Rev 5
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