8K/16K x 9
Synchronous Dual-Port St atic RAM
CY7C09159A
CY7C09169A
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-06047 Rev. *A Revised December 27, 2002
25/0251
Features
• True dual-ported memory cells which allow simulta-
neous access of the same memory location
• Two Flow-Through/Pipelined devices
—8K x 9 organization (CY7C09159A)
—16K x 9 organization (CY7C09169A)
• Three Modes
—Flow-Through
—Pipelined
—Burst
• Pipelined output mode on both ports allows fast
100-MH z cyc le time
• 0.35-micron CMOS for optimum speed/power
• High-speed clock to data access 6.5[1]/7.5/9/12 ns (max.)
• Low operating power
—Active = 200 mA (typical)
—Standby = 0.05 mA (typical)
• Fully synchronous interface for easier operation
• Burst counters increment addresses internally
—Shorten cycle times
—Minimize bus noise
—Supported in Flow-Through and Pipelined modes
• Dual Chip Enables for easy depth expansion
• Automatic power-down
• Commercial and Indus trial tem peratu re ranges
•Available in 100-pin TQFP
Notes:
1. See page 6 for Load Conditions.
2. A0–A12 for 8K; A0–A13 for 16K.
v
Logic Block Diagram
R/WL
CE0L
CE1L
OEL
FT/PipeL
I/O0L–I/O8L
Control
A0–A12/13L
CLKL
ADSL
CNTENL
CNTRSTL
R/WR
1
0
0/1
CE0R
CE1R
OER
10/1
0FT/PipeR
I/O0R–I/O8R
I/O
Control
A0–A12/13R
CLKR
ADSR
CNTENR
CNTRSTR
1
0
0/1
1
0/1 0
I/O
Counter/
Address
Register
Decode
True Dual-Ported
RAM Array
Counter/
Address
Register
Decode
9 9
[2] [2]
13/14 13/14
For the most recent information, visit the Cypress web site at www.cypress.com
CY7C09159A
CY7C09169A
Document #: 38-06047 Rev. *A Page 2 of 17
Functional Description
The CY7C09159A and CY7C09169A are high-speed synchro-
nous CMO S 8K and 16K x 9 d ual-port stat ic RAM s. Two ports
are provided, permitting independent, simultaneous access for
reads and writes to any location in memory[3]. Registers on
control, address, and data lines allow for minimal set-up and
hold times. In pipelined output mode, data is registered for
decreased cycle time. Clock to data valid tCD2 = 6.5 ns[1] (pipe-
lined). Flow-through mode can also be used to bypass the
pipelined output register to eliminate access latency. In flow-
through mode data will be available tCD1 = 15 ns after the
address is clocked into the device. Pipelined output or flow-
through mode is selected via the FT/Pipe pin.
Each po rt con tain s a burst c ounte r on th e inpu t addr ess re gis-
ter. The internal write pulse width is independent of the LOW-
to-HIGH trans ition of the cl ock si gn al. T he in ternal write p uls e
is self-timed to allow the shortest possible cycle times.
A HIGH on CE0 or LOW on CE1 for one clo ck cy cle wil l po wer
down the internal circuitry to reduce the static power consump-
tion. The use of multiple Chip Enables allows easier banking
of multiple chips for depth expansion configurations. In the
pipelin ed mod e, one c ycl e is require d wi th CE0 LO W and CE 1
HIGH to reactivate the outputs.
Counter enable inputs are provided to st all the operation of the
address input and utilize the internal add ress generated by the
internal counter for fast interleaved memory applications. A
port’s burst counter is loaded with the port’s Address Strobe
(ADS). When the port’s Count Enable (CNTEN) is asserted,
the address counter will increment on each LOW-to-HIGH
transition of that port’s clock signal. This will read/write one
word from/into each successive address location until CNTEN
is deasserted. The counter can address the entire memory
array and will l oop back to the st art. Co unter Reset (CNTRST)
is used to reset the burst counter.
All parts are available in 100-pin Thin Quad Plastic Flatpack
(TQFP) packages.
Note:
3. When simultaneously writing to the same location, final value cannot be guaranteed.
CY7C09159A
CY7C09169A
Document #: 38-06047 Rev. *A Page 3 of 17
Pin Configuration
Note:
4. This pin is NC for CY7C09159A.
1
3
2
92 91 90 848587 868889 83 82 81 7678 77798093949596979899100
59
60
61
67
66
64
65
63
62
68
69
70
75
73
74
72
71
NC
NC
A7R
A8R
A9R
A10R
NC
A12R
NC
GND
NC
NC
CE0R
A13R
A11R
NC
NC
CE1R
CNTRSTR
R/WR
OER
FT/PIPER
GND
NC
NC
58
57
56
55
54
53
52
51
CY7C09159A (8K x 9)
NC
NC
A7L
A8L
A9L
A10L
NC
A12L
NC
VCC
NC
NC
CE0L
A13L
A11L
NC
NC
CE1L
CNTRSTL
R/WL
OEL
FT/PIPEL
NC
NC
NC
17
16
15
9
10
12
11
13
14
8
7
6
4
5
18
19
20
21
22
23
24
25
NC
NC
A6L
A5L
A4L
A3L
CLKL
A1L
CNTENL
GND
GND
CNTENR
A0R
A0L
A2L
ADSR
CLKR
A1R
A2R
A3R
A4R
A5R
A6R
NC
ADSL
34 35 36 424139 403837 43 44 45 5048 494746
NC
NC
I/O8R
I/O7R
I/O6R
I/O5R
I/01R
I/O3R
I/O2R
GND
VCC
GND
I/O2L
VCC
I/O4R
I/O0L
I/O1L
I/O3L
I/O4L
I/O5L
I/O6L
I/O7L
I/O8L
GND
I/O0R
3332313029282726
CY7C09169A (16K x 9)
100-Pi n TQFP
(Top View)
[4] [4]
CY7C09159A
CY7C09169A
Document #: 38-06047 Rev. *A Page 4 of 17
Maximum Ratings[5]
(Above which the useful life may be impaired. For user guide-
lines, not tes ted .)
Storage Temperature................................. –65°C to +150°C
Ambient Temperature with Power Applied..–55°C to +125°C
Supply Voltage to Ground Potential...............–0.3V to +7.0V
DC Voltage Applied to
Outputs in High Z State..................................–0.5V to +7.0V
DC Input Voltage............................................–0.5V to +7.0V
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage..... ...... ..... ...... ................. .....> 200 1V
Latch-Up Current.....................................................>200 mA
Note:
5. The Voltage on any input or I/O pin cannot exceed the power pin during
power-up. 6. Industrial Parts are available in CY7C09169A only.
Selection Guide
CY7C09159A
CY7C09169A
-6[1]
CY7C09159A
CY7C09169A
-7
CY7C09159A
CY7C09169A
-9
CY7C09159A
CY7C09169A
-12
fMAX2 (MHz) (Pipelined) 100 83 67 50
Max. Access Time (ns) (Clock to Data, Pipelined) 6.5 7.5 9 12
Typical Operating Current ICC (mA) 250 235 215 195
Typical Standby Current for ISB1 (mA)
(Both Ports TTL Level) 45 40 35 30
Typical Standby Current for ISB3 (mA)
(Both Ports CMOS Level) 0.05 0.05 0.05 0.05
Pin Definitions
Left Port Right Port Description
A0L–A13L A0R–A13R Address Inputs (A0−A12 for 8K; A0−A13 for 16K devices).
ADSLADSRAddress Strobe Input . Used as an address qu alifier. This sig nal shoul d be assert ed LOW duri ng
normal read or write transactions. Asserting this signal LOW also loads the burst address counter
with data present on the I/O pins.
CE0L,CE1L CE0R,CE1R Chip Enable Input. To select e ither the left or rig ht port, bo th CE0 AND CE1 must be asserted to
their active states (CE0 ≤ VIL and CE1 ≥ VIH).
CLKLCLKRClock Signal. This input can be free running or strobed. Maximum clock input rate is fMAX.
CNTENLCNTENRCounter Enable Input. Asserting this signal LOW increments the burst address counter of its
respecti ve port o n each risi ng edge o f CLK. CN TEN is dis abled if ADS or CNTRST are asserted
LOW.
CNTRSTLCNTRSTRCounter Reset Input. Asserting this signal LOW resets the burst address counter of its respective
port to zero. CNTRST is not disable d by asserting ADS or CNTEN.
I/O0L–I/O8L I/O0R–I/O8R Data Bus Input/Output (I/O0–I/O7 for x8 devices; I/O0–I/O8 for x9 dev ic es ).
OELOEROutput Enabl e Input . This s ignal must b e asserte d LOW t o enabl e the I/ O dat a pins durin g read
operations.
R/WLR/WRRead/Write Enable Input. This signal is asserted LOW to write to the dual port memory array.
For read operations, assert this pin HIGH.
FT/PIPELFT/PIPERFlow-Through/Pipelined Se lect Input. For f low-through mode operation, assert this pin L OW. For
pipelined mode operation, assert this pin HIGH.
GND Ground Input.
NC No Connect.
VCC Power Input.
Operating Range
Range Ambient
Temperature VCC
Commercial 0°C to +70°C 5V ± 10%
Industrial[6] −40°C to +85°C 5V ± 10%
CY7C09159A
CY7C09169A
Document #: 38-06047 Rev. *A Page 5 of 17
Note:
7. CEL and CER are internal signals. To select either the left or right port, both CE0 AND CE1 must be asserted to their active states (CE0 ≤ VIL and CE1 ≥ VIH).
Electrical Characteristics Ov er the Op erating Rang e
Parameter Description
CY7C09159A
CY7C09169A
Unit
-6[1] -7 -9 -12
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
VOH Output HIGH Voltage
(VCC = Min., IOH = –4.0 mA) 2.4 2.4 2.4 2.4 V
VOL Output LOW Voltage
(VCC = Min., IOH = +4.0 mA) 0.4 0.4 0.4 0.4 V
VIH Input HIGH Voltage 2.2 2.2 2.2 2.2 V
VIL Input LOW Voltage 0.8 0.8 0.8 0.8 V
IOZ Output Leakage Current −10 10 −10 10 −10 10 −10 10 µA
ICC Operating Current
(VCC = Max.,
IOUT = 0 mA)
Outputs Disabled
Com’l. 250 450 235 420 210 350 200 305 mA
Ind.[6] 245 410 mA
ISB1 Standby Current (Both
Ports TTL Level)[7]
CEL & CER ≥ VIH,
f = fMAX
Com’l. 45 115 40 105 35 95 30 85 mA
Ind.[6] 50 110 mA
ISB2 Standby Current (One
Port TTL Level)[7]
CEL | CER ≥ VIH,
f = fMAX
Com’l. 175 235 160 220 145 205 125 190 mA
Ind.[6] 160 220 mA
ISB3 Standby Current (Both
Ports CM OS Level)[7]
CEL & CER ≥
VCC – 0.2V, f = 0
Com’l. 0.05 0.5 0.05 0.5 0.05 0.5 0.05 0.5 mA
Ind.[6] 0.05 0.5 mA
ISB4 Standby Current (One
Port CMOS Level)[7]
CEL | CER ≥ VIH,
f = fMAX
Com’l. 160 200 145 185 130 170 110 150 mA
Ind.[6] 145 185 mA
Capacitance
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 2 5°C, f = 1 MHz,
VCC = 5.0V 10 pF
COUT Output Capacitance 10 pF
CY7C09159A
CY7C09169A
Document #: 38-06047 Rev. *A Page 6 of 17
AC Test Loads (Applicabl e to -6 only)[8]
Note:
8. Test Conditions: C = 10 pF.
AC Test Loads
(a) Normal Load (Load 1)
R1 = 893Ω
5V
OUTPUT
R2 = 347Ω
C= 30pF
VTH =1.4V
OUTPUT
C= 30 pF
(b) Thévenin Equivalent (Load 1) (c) Three-State Delay(Load 2)
R1 = 893Ω
R2 = 347Ω
5V
OUTPUT
C= 5pF
RTH = 250Ω
(Used for tCKLZ, tOLZ, & t OHZ
including scope and jig)
V
TH
=1.4V
OUTPUT
C
(a) Load 1 (-6 only)
R = 50
Ω
Z
0
= 50
Ω
3.0V
GND 90% 90%
10%
3ns 3ns
10%
ALL INPUTPULSES
≤≤
0.00
0.10
0.20
0.30
0.40
0.50
0.60
0.70
0.80
0.90
1.00
1 0 15 20 25 30 35
(b) Load Derating Curve
Capacitance (pF)
∆
(ns) for all -6 access times
CY7C09159A
CY7C09169A
Document #: 38-06047 Rev. *A Page 7 of 17
Switching Characteristics Over the Operating Range
Parameter Description
CY7C09159A
CY7C09169A
Unit
-6[1] -7 -9 -12
Min. Max. Min. Max. Min. Max. Min. Max.
fMAX1 fMax Flow-Through 53 45 40 33 MHz
fMAX2 fMax Pipelined 100 83 67 50 MHz
tCYC1 Clock Cycle Time - Flow-Through 19 22 25 30 ns
tCYC2 Clock Cycle Time - Pipelined 10 12 15 20 ns
tCH1 Clock HIGH Time - Flow-Through 6.5 7.5 12 12 ns
tCL1 Clock LOW Time - Flow-Through 6.5 7.5 12 12 ns
tCH2 Clock HIGH Time - Pipelined 4 5 6 8 ns
tCL2 Clock LOW Time - Pipelined 4 5 6 8 ns
tRClock Rise Time 3 3 3 3 ns
tFClock Fall Time 3333ns
tSA Address Set-u p Time 3.5 4 4 4 n s
tHA Address H old Time 0 0 1 1 ns
tSC Chip Enable Set-up Time 3.5 4 4 4 ns
tHC Chip Enable Hold Time 0 0 1 1 ns
tSW R/W Set-up Time 3.5 4 4 4 ns
tHW R/W Hold Time 0011ns
tSD Input Data Set-up Time 3.5 4 4 4 ns
tHD Input Data Hold Time 0 0 1 1 ns
tSAD ADS Set-up Time 3.5 4 4 4 ns
tHAD ADS Hold Time 0011ns
tSCN CNTEN Set-up Time 3.5 4 4 4 ns
tHCN CNTEN Hold Time 0011ns
tSRST CNTRST Set-up T ime 3.5 4 4 4 ns
tHRST CNTRST Hold Time 0011ns
tOE Output Enab le to Dat a Valid 8 9 10 12 ns
tOLZ OE to Low Z 2 2 2 2 ns
tOHZ OE to High Z 17171717ns
tCD1 Clock to Data Valid - Flow-Through 15 18 20 25 ns
tCD2 Clock to Data Valid - Pipelined 6.5 7.5 9 12 ns
tDC Data Output Hold After Clock HIGH 2 2 2 2 ns
tCKHZ Clock HIGH to Output High Z 29292929ns
tCKLZ Clock HIGH to Output Low Z 2 2 2 2 ns
Port to Port Delays
tCWDD Write Port Clock HIGH to Read Data De-
lay 30 35 40 40 ns
tCCS Clock to Clock Set-up Time 9 10 15 15 ns
CY7C09159A
CY7C09169A
Document #: 38-06047 Rev. *A Page 8 of 17
Switching Waveforms
Read Cycle for Flow-Through Output (FT/PIPE = VIL)[9, 10, 11, 12]
Read Cycle for Pipelined Operation (FT/PIPE = VIH)[9, 10, 11, 12]
Notes:
9. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
10. ADS = VIL, CNTEN and CNTRST = VIH.
11 . The output is disabled (high- impedance state) by CE0=VIH or CE1 = VIL following the next rising edge of the clock.
12. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK. Numbers are for reference only .
tCH1 tCL1
tCYC1
tSC tHC
tDC
tOHZ
tOE
tSC tHC
tSW tHW
tSA tHA
tCD1 tCKHZ
tDC
tOLZ
tCKLZ
AnAn+1 An+2 An+3
QnQn+1 Qn+2
CLK
CE0
CE1
R/W
ADDRESS
DATAOUT
OE
tCH2 tCL2
tCYC2
tSC tHC
tSW tHW
tSA tHA
AnAn+1
CLK
CE0
CE1
R/W
ADDRESS
DATAOUT
OE
An+2 An+3
tSC tHC
tOHZ
tOE
tOLZ
tDC
tCD2
tCKLZ
QnQn+1 Qn+2
1 Latency
CY7C09159A
CY7C09169A
Document #: 38-06047 Rev. *A Page 9 of 17
Bank Select Pipelined Read[13, 14]
Left Port Write to Flow-Through Right Port Read[15, 16, 17, 18]
Notes:
13. In this depth expansion example, B1 represents Bank #1 and B2 is Bank #2. Each Bank consists of one Cypress dual-port device from this data sheet.
ADDRESS(B1) = ADDRESS(B2).
14. OE and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.
15. The same waveforms apply for a right port write to flow-through left port read.
16. CE0 and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
17. OE = VIL for the right port, which is being read from. OE = VIH for the left port, which is being written to.
18. It tCCS ≤ maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD. If tCCS>maximum spe cifie d, then data is not
valid until tCCS + tCD1. tCWDD does not apply in this case.
Switching Waveforms (continued)
D3
D1
D0
D2
A0A1A2A3A4A5
D4
A0A1A2A3A4A5
tSA tHA
tSC tHC
tSA tHA
tSC tHC
tSC tHC
tSC tHC tCKHZ
tDC
tDC
tCD2
tCKLZ
tCD2 tCD2 tCKHZ
tCKLZ
tCD2 tCKHZ
tCKLZ
tCD2
tCH2 tCL2
tCYC2
CLKL
ADDRESS(B1)
CE0(B1)
DATAOUT(B2)
DATAOUT(B1)
ADDRESS(B2)
CE0(B2)
tSA tHA
tSW tHW
tSD tHD
MATCH
VALID
tCCS
tSW tHW
tDC
tCWDD
tCD1
MATCH
tSA tHA
MATCH
NO
MATCH
NO
VALID VALID
tDC
tCD1
CLKL
R/WL
ADDRESSL
DATAINL
ADDRESSR
DATAOUTR
CLKR
R/WR
CY7C09159A
CY7C09169A
Document #: 38-06047 Rev. *A Page 10 of 17
Pipelined Read-to-Write-to-Read (OE = VIL)[12 , 16, 19, 20]
Pipelined Read-to-Write-to-Read (OE Controlled)[12, 16, 19, 20]
Notes:
19. Output state (HIGH, LOW, or High-Impedance) is determined by the previous cycle control signals.
20. During “No operation,” data in memory at the selected address may be corrupted and should be rewritten to ensure data integrity.
Switching Waveforms (continued)
tCYC2tCL2
tCH2
tHC
tSC
tHW
tSW
tHA
tSA
tHW
tSW
tCD2 tCKHZ
tSD tHD
tCKLZ tCD2
NO OPERATIO N WRITEREAD READ
CLK
CE0
CE1
R/W
ADDRESS
DATAIN
DATAOUT
AnAn+1 An+2 An+2
Dn+2
An+3 An+4
QnQn+3
tCYC2tCL2
tCH2
tHC
tSC
tHW
tSW
tHA
tSA
AnAn+1 An+2 An+3 An+4 An+5
tHW
tSW
tSD tHD
Dn+2
tCD2
tOHZ
READ READWRITE
Dn+3 tCKLZ tCD2
QnQn+4
CLK
CE0
CE1
R/W
ADDRESS
DATAOUT
DATAIN
OE
CY7C09159A
CY7C09169A
Document #: 38-06047 Rev. *A Page 11 of 17
Flow-Through Read-to-Write-to-Read (OE = VIL)[10, 12, 16, 19]
Flow-Through Read-to-Write-to-Read (OE Controlled)[10, 12, 16, 19]
Switching Waveforms (continued)
tCH1 tCL1
tCYC1
tSC tHC
tSW tHW
tSA tHA
tSW tHW
tSD tHD
AnAn+1 An+2 An+2 An+3 An+4
Dn+2
QnQn+1 Qn+3
tCD1 tCD1
tDC tCKHZ
tCD1 tCD1
tCKLZ tDC
READ NO
OPERATION WRITE READ
CLK
CE0
CE1
ADDRESS
R/W
DATAIN
DATAOUT
Qn
tCH1 tCL1
tCYC1
tSC tHC
tSW tHW
tSA tHA
tCD1 tDC
tOHZ
READ
AnAn+1 An+2 An+3 An+4 An+5
Dn+2 Dn+3
tSW tHW
tSD tHD
tCD1 tCD1
tCKLZ tDC
Qn+4
tOE
WRITE READ
CLK
CE0
CE1
ADDRESS
R/W
DATAIN
DATAOUT
OE
CY7C09159A
CY7C09169A
Document #: 38-06047 Rev. *A Page 12 of 17
Pipelined Read with Address Counter Advance[21]
Flow-Through Read with Address Counter Advance[21]
Note:
21. CE0 and O E = VIL; CE1, R/W and CNTRST = VIH.
Switching Waveforms (continued)
COUNTER HOLD
READ WITH COUNTER
tSA tHA
tSAD tHAD
tSCN tHCN
tCH2 tCL2
tCYC2
tSAD tHAD
tSCN tHCN
Qx-1 QxQnQn+1 Qn+2 Qn+3
tDC
tCD2
READ WITH COUNTER
READ
EXTERNAL
ADDRESS
CLK
ADDRESS
ADS
DATAOUT
CNTEN
An
tCH1 tCL1
tCYC1
tSA tHA
tSAD tHAD
tSCN tHCN
An
tSAD tHAD
tSCN tHCN
tCD1
CLK
ADDRESS
ADS
CNTEN
QxQnQn+1
tDC COUNTE R HOLD
READ WITH COUNTER
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
Qn+3
Qn+2
DATAOUT
CY7C09159A
CY7C09169A
Document #: 38-06047 Rev. *A Page 13 of 17
Write with Address Counter Advance (Flow-Through or Pipelined Outputs)[22, 23]
Notes:
22. CE0 and R/W = VIL; CE1 and CNTRST = VIH.
23. The “Internal Address” is equal to the “External Address” when ADS = VIL and equals the counter output when ADS = VIH.
Switching Waveforms (continued)
tCH2 tCL2
tCYC2
AnAn+1 An+2 An+3 An+4
Dn+1 Dn+1 Dn+2 Dn+3 Dn+4
An
Dn
tSAD tHAD
tSCN tHCN
tSD tHD
WRIT E EX T E RN AL WRITE WITH COUNTER
ADDRESS WRITE WITH
COUNTER WRITE COUNTER
HOLD
CLK
ADDRESS
INTERNAL
CNTEN
ADS
DATAIN
ADDRESS
tSA tHA
CY7C09159A
CY7C09169A
Document #: 38-06047 Rev. *A Page 14 of 17
Notes:
24. CE0 = VIL; CE1 = VIH.
25. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset.
Counter Reset (Pipelined Outputs)[12, 19, 24, 25]
Switching Waveforms (continued)
tCH2 tCL2
tCYC2
CLK
ADDRESS
INTERNAL
CNTEN
ADS
DATAIN
ADDRESS
CNTRST
R/W
DATAOUT Q0Q1Qn
D0
AX01A
nAn+1
tSAD tHAD
tSCN tHCN
tSRST tHRST
tSD tHD
tSW tHW
AnAn+1
tSA tHA
COUNTER
RESET WRITE
ADDRESS 0 READ
ADDRESS 0 READ
ADDR ES S 1 READ
ADDRESS n
CY7C09159A
CY7C09169A
Document #: 38-06047 Rev. *A Page 15 of 17
Notes:
26. “X” = “Don’t Care,” “H” = VIH, “L” = VIL.
27. ADS, CNTEN, CNTRST = “Don’t Care.”
28. OE is an asynchronous input signal.
29. Whe n C E changes state in the pipelined mode, deselection and read happen in the following clock cycle.
30. CE0 and O E = VIL; CE1 and R/W = VIH.
31. Data shown for flow-through mode; pipelined mode output will be delayed by one cycle.
32. Counter operation is independent of CE0 an d CE1.
Read/Write and Enable Operation[26, 27, 28]
Inputs Outputs
OE CLK CE0CE1R/W I/O0–I/O8Operation
X H X X High-Z Deselected[29]
X X L X High-Z Deselected[29]
X L H L DIN Write
L L H H DOUT Read[29]
H X L H X High-Z Outpu ts Disa bled
Address Counter Control Operation[26, 30, 31, 32]
Address Previous
Address CLK ADS CNTEN CNTRST I/O Mode Operation
X X X X L Dout(0) Reset Counter Reset to Address 0
AnX L X H Dout(n) Load Address Load into Counter
X AnH H H Dout(n) Hold External Address Blocked—Counter
Disabled
X AnH L H Dout(n+1) Increment Counter Enabled —Internal Address
Generation
CY7C09159A
CY7C09169A
Document #: 38-06047 Rev. *A Page 16 of 17
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any ci rcuitry other th an circuitry embod ied in a Cypr ess Semiconductor pr oduct. Nor does it convey or imply any licen se under p atent or other rights. Cy press Semiconductor does not autho rize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
Ordering Information
8K x9 Synchronous Dual-Port SRAM
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
6.5[1] CY7C09159A-6AC A100 100-Pin Thin Quad Flat Pack Commercial
7.5 CY7C09159A-7AC A100 100-Pin Thin Quad Flat Pack Commercial
9CY7C09159A-9AC A100 100-Pin Thin Quad Flat Pack Commercial
12 CY7C09159A-12AC A100 100-Pin Thin Quad Flat Pack Commercial
16K x9 Synchronous Dual-Port SRAM
Speed
(ns) Ordering Code Package
Name Package Type Operating
Range
6.5[1] CY7C09169A-6AC A100 100-Pin Thin Quad Flat Pack Commercial
7.5 CY7C09169A-7AC A100 100-Pin Thin Quad Flat Pack Commercial
9 CY7C09169A-9AC A100 100-Pin Thin Quad Flat Pack Commercial
CY7C09169A-9AI A100 100-Pin Thin Quad Flat Pack Industrial
12 CY7C09169A-12AC A100 100-Pin Thin Quad Flat Pack Commercial
Package Diagram
100-Pin Thin Plastic Quad Flat Pack (TQFP) A100
51-85048-B
CY7C09159A
CY7C09169A
Document #: 38-06047 Rev. *A Page 17 of 17
Document Title: CY7C09159A/CY7C09169A 8K/16K x 9 Synchronous Dual-Port Static RAM
Document Number: 38-06047
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 110199 09/29/01 SZV Change from Spec number: 38-00833 to 38-06047
*A 122297 12/27/02 RBI Power up requirements added to Maximum Ratings Information
