DS-25SF081–045I–8/2017
Features
Single 2.3V - 3.6V Supply
Serial Peripheral Interface (SPI) Compatible
Supports SPI Modes 0 and 3
Supports Dual and Quad Output Read
104MHz Maximum Operating Frequency
Clock-to-Output (tV) of 6 ns
Flexible, Optimized Erase Architecture for Code + Data Storage Applications
Uniform 4-Kbyte Block Erase
Uniform 32-Kbyte Block Erase
Uniform 64-Kbyte Block Erase
Full Chip Erase
Hardware Controlled Locking of Protected Blocks via WP Pin
3 Protected Programmable Security Register Pages
Flexible Programming
Byte/Page Program (1 to 256 Bytes)
Fast Program and Erase Times
0.7ms Typical Page Program (256 Bytes) Time
70ms Typical 4-Kbyte Block Erase Time
300ms Typical 32-Kbyte Block Erase Time
600ms Typical 64-Kbyte Block Erase Time
JEDEC Standard Manufacturer and Device ID Read Methodology
Low Power Dissipation
2µA Deep Power-Down Current (Typical)
10µA Standby current (Typical)
4mA Active Read Current (Typical)
Endurance: 100,000 Program/Erase Cycles
Data Retention: 20 Years
Complies with Full Industrial Temperature Range
Industry Standard Green (Pb/Halide-free/RoHS Compliant) Package Options
8-lead SOIC (150-mil and 208-mil)
8-pad Ultra Thin DFN (5 x 6 x 0.6 mm and 2 x 3 x 0.6 mm)
8-lead TSSOP (4 x 4 mm)
Die in Wafer Form
AT25SF081
8-Mbit, 2.3V Minimum
SPI Serial Flash Memory with Dual-I/O and Quad-IO Support
2
AT25SF081
DS-25SF081–045I–8/2017
Description
The Adesto® AT25SF081 is a serial interface Flash memory device designed for use in a wide variety of high-volume
consumer based applications in which program code is shadowed from Flash memory into embedded or external RAM
for execution. The flexible erase architecture of the AT25SF081 is ideal for data storage as well, eliminating the need for
additional data storage devices.
The erase block sizes of the AT25SF081 have been optimized to meet the needs of today's code and data storage
applications. By optimizing the size of the erase blocks, the memory space can be used much more efficiently. Because
certain code modules and data storage segments must reside by themselves in their own erase regions, the wasted and
unused memory space that occurs with large block erase Flash memory devices can be greatly reduced. This increased
memory space efficiency allows additional code routines and data storage segments to be added while still maintaining
the same overall device density.
The device also contains three pages of Security Register that can be used for purposes such as unique device
serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc. These Security Register
pages can be individually locked.
1. Pin Descriptions and Pinouts
Table 1-1. Pin Descriptions
Symbol Name and Function
Asserted
State Type
CS
CHIP SELECT: Asserting the CS pin selects the device. When the CS pin is deasserted, the
device will be deselected and normally be placed in standby mode (not Deep Power-Down
mode), and the SO pin will be in a high-impedance state. When the device is deselected,
data will not be accepted on the SI pin.
A high-to-low transition on the CS pin is required to start an operation, and a low-to-high
transition is required to end an operation. When ending an internally self-timed operation
such as a program or erase cycle, the device will not enter the standby mode until the
completion of the operation.
Low Input
SCK
SERIAL CLOCK: This pin is used to provide a clock to the device and is used to control the
flow of data to and from the device. Command, address, and input data present on the SI pin
is always latched in on the rising edge of SCK, while output data on the SO pin is always
clocked out on the falling edge of SCK.
-Input
SI (I/O0)
SERIAL INPUT: The SI pin is used to shift data into the device. The SI pin is used for all data
input including command and address sequences. Data on the SI pin is always latched in on
the rising edge of SCK.
With the Dual-Output and Quad-Output Read commands, the SI Pin becomes an output pin
(I/O0) in conjunction with other pins to allow two or four bits of data on (I/O3-0) to be clocked
in on every falling edge of SCK
To maintain consistency with the SPI nomenclature, the SI (I/O0) pin will be referenced as
the SI pin unless specifically addressing the Dual-I/O and Quad-I/O modes in which case it
will be referenced as I/O0
Data present on the SI pin will be ignored whenever the device is deselected (CS is
deasserted).
-Input/Output
3
AT25SF081
DS-25SF081–045I–8/2017
SO (I/O1)
SERIAL OUTPUT: The SO pin is used to shift data out from the device. Data on the SO pin
is always clocked out on the falling edge of SCK.
With the Dual-Output Read commands, the SO Pin remains an output pin (I/O0) in
conjunction with other pins to allow two bits of data on (I/O1-0) to be clocked in on every
falling edge of SCK
To maintain consistency with the SPI nomenclature, the SO (I/O1) pin will be referenced as
the SO pin unless specifically addressing the Dual-I/O modes in which case it will be
referenced as I/O1
The SO pin will be in a high-impedance state whenever the device is deselected (CS is
deasserted).
-Input/Output
WP
(I/O2)
WRITE PROTECT: The WP pin controls the hardware locking feature of the device. With the
Quad-Output Read commands, the WP Pin becomes an output pin (I/O2) in conjunction with
other pins to allow four bits of data on (I/O33-0) to be clocked in on every falling edge of SCK.
To maintain consistency with the SPI nomenclature, the WP (I/O2) pin will be referenced as
the WP pin unless specifically addressing the Quad-I/O modes in which case it will be
referenced as I/O2
The WP pin is internally pulled-high and may be left floating if hardware controlled protection
will not be used. However, it is recommended that the WP pin also be externally connected
to VCC whenever possible.
-Input/Output
HOLD
(I/O3)
HOLD: The HOLD pin is used to temporarily pause serial communication without
deselecting or resetting the device. While the HOLD pin is asserted, transitions on the SCK
pin and data on the SI pin will be ignored, and the SO pin will be in a high-impedance state.
The CS pin must be asserted, and the SCK pin must be in the low state in order for a Hold
condition to start. A Hold condition pauses serial communication only and does not have an
effect on internally self-timed operations such as a program or erase cycle. Please refer to
“Hold Function” on page 31 for additional details on the Hold operation.
With the Quad-Output Read commands, the HOLD Pin becomes an output pin (I/O3) in
conjunction with other pins to allow four bits of data on (I/O33-0) to be clocked in on every
falling edge of SCK.
To maintain consistency with the SPI nomenclature, the HOLD (I/O3) pin will be referenced
as the HOLD pin unless specifically addressing the Quad-I/O modes in which case it will be
referenced as I/O3
The HOLD pin is internally pulled-high and may be left floating if the Hold function will not be
used. However, it is recommended that the HOLD pin also be externally connected to VCC
whenever possible.
-Input/Output
VCC
DEVICE POWER SUPPLY: The VCC pin is used to supply the source voltage to the device.
Operations at invalid VCC voltages may produce spurious results and should not be
attempted.
-Power
GND GROUND: The ground reference for the power supply. GND should be connected to the
system ground. -Power
Table 1-1. Pin Descriptions (Continued)
Symbol Name and Function
Asserted
State Type
4
AT25SF081
DS-25SF081–045I–8/2017
2. Block Diagram
Figure 2-1. Block Diagram
3. Memory Array
To provide the greatest flexibility, the memory array of the AT25SF081 can be erased in four levels of granularity
including a full chip erase. The size of the erase blocks is optimized for both code and data storage applications, allowing
both code and data segments to reside in their own erase regions. The Memory Architecture Diagram illustrates the
breakdown of each erase level.
Figure 1-1. 8-SOIC, 8-TSSOP (Top View) Figure 1-2. 8-UDFN (Top View)
1
2
3
4
8
7
6
5
CS
SO
WP
GND
VCC
HOLD
SCK
SI
CS
SO
WP
GND
1
2
3
4
8
7
6
5
VCC
HOLD
SCK
SI
Flash
Memory
Array
Y-Gating
CS
SCK
Note: I/O3-0 pin naming convention is used for Dual-I/O and Quad-I/O commands.
SO (I/O1)
SI (I/O0)
Y-Decoder
Address Latch
X-Decoder
I/O Buffers
and Latches
Control and
Protection Logic
SRAM
Data Buffer
WP (I/O2)
Interface
Control
And
Logic
HOLD (I/O3)
5
AT25SF081
DS-25SF081–045I–8/2017
Figure 3-1. Memory Architecture Diagram
64KB 32KB 4KB 1-256 Byte
4KB 0FFFFFh–0FF000h 256 Bytes 0FFFFFh–0FFF00h
4KB 0FEFFFh–0FE000h 256 Bytes 0FFEFFh–0FFE00h
4KB 0FDFFFh–0FD000h 256 Bytes 0FFDFFh–0FFD00h
4KB 0FCFFFh–0FC000h 256 Bytes 0FFCFFh–0FFC00h
4KB 0FBFFFh–0FB000h 256 Bytes 0FFBFFh–0FFB00h
4KB 0FAFFFh–0FA000h 256 Bytes 0FFAFFh–0FFA00h
4KB 0F9FFFh–0F9000h 256 Bytes 0FF9FFh–0FF900h
4KB 0F8FFFh–0F8000h 256 Bytes 0FF8FFh–0FF800h
4KB 0F7FFFh–0F7000h 256 Bytes 0FF7FFh–0FF700h
4KB 0F6FFFh–0F6000h 256 Bytes 0FF6FFh–0FF600h
4KB 0F5FFFh–0F5000h 256 Bytes 0FF5FFh–0FF500h
4KB 0F4FFFh–0F4000h 256 Bytes 0FF4FFh–0FF400h
4KB 0F3FFFh–0F3000h 256 Bytes 0FF3FFh–0FF300h
4KB 0F2FFFh–0F2000h 256 Bytes 0FF2FFh–0FF200h
4KB 0F1FFFh–0F1000h 256 Bytes 0FF1FFh–0FF100h
4KB 0F0FFFh–0F0000h 256 Bytes 0FF0FFh–0FF000h
4KB 0EFFFFh–0EF000h 256 Bytes 0FEFFFh–0FEF00h
4KB 0EEFFFh–0EE000h 256 Bytes 0FEEFFh–0FEE00h
4KB 0EDFFFh–0ED000h 256 Bytes 0FEDFFh–0FED00h
4KB 0ECFFFh–0EC000h 256 Bytes 0FECFFh–0FEC00h
4KB 0EBFFFh–0EB000h 256 Bytes 0FEBFFh–0FEB00h
4KB 0EAFFFh–0EA000h 256 Bytes 0FEAFFh–0FEA00h
4KB 0E9FFFh–0E9000h 256 Bytes 0FE9FFh–0FE900h
4KB 0E8FFFh–0E8000h 256 Bytes 0FE8FFh–0FE800h
4KB 0E7FFFh–0E7000h
4KB 0E6FFFh–0E6000h
4KB 0E5FFFh–0E5000h
4KB 0E4FFFh–0E4000h 256 Bytes 0017FFh–001700h
4KB 0E3FFFh–0E3000h 256 Bytes 0016FFh–001600h
4KB 0E2FFFh–0E2000h 256 Bytes 0015FFh–001500h
4KB 0E1FFFh–0E1000h 256 Bytes 0014FFh–001400h
4KB 0E0FFFh–0E0000h 256 Bytes 0013FFh–001300h
256 Bytes 0012FFh–001200h
256 Bytes 0011FFh–001100h
256 Bytes 0010FFh–001000h
4KB 00FFFFh–00F000h 256 Bytes 000FFFh–000F00h
4KB 00EFFFh–00E000h 256 Bytes 000EFFh–000E00h
4KB 00DFFFh–00D000h 256 Bytes 000DFFh–000D00h
4KB 00CFFFh–00C000h 256 Bytes 000CFFh–000C00h
4KB 00BFFFh–00B000h 256 Bytes 000BFFh–000B00h
4KB 00AFFFh–00A000h 256 Bytes 000AFFh–000A00h
4KB 009FFFh–009000h 256 Bytes 0009FFh–000900h
4KB 008FFFh–008000h 256 Bytes 0008FFh–000800h
4KB 007FFFh–007000h 256 Bytes 0007FFh–000700h
4KB 006FFFh–006000h 256 Bytes 0006FFh–000600h
4KB 005FFFh–005000h 256 Bytes 0005FFh–000500h
4KB 004FFFh–004000h 256 Bytes 0004FFh–000400h
4KB 003FFFh–003000h 256 Bytes 0003FFh–000300h
4KB 002FFFh–002000h 256 Bytes 0002FFh–000200h
4KB 001FFFh–001000h 256 Bytes 0001FFh–000100h
4KB 000FFFh–000000h 256 Bytes 0000FFh–000000h
• • •
64KB
Sector 0
Block Erase Detail Page Program Detail
Page AddressBlock Address
32KB
32KB
Range
•
• •
• • •
Range
32KB
32KB
• •
•
64KB
Sector 15
32KB
32KB
64KB
Sector 14
6
AT25SF081
DS-25SF081–045I–8/2017
4. Device Operation
The AT25SF081 is controlled by a set of instructions that are sent from a host controller, commonly referred to as the SPI
Master. The SPI Master communicates with the AT25SF081 via the SPI bus which is comprised of four signal lines: Chip
Select (CS), Serial Clock (SCK), Serial Input (SI), and Serial Output (SO).
The SPI protocol defines a total of four modes of operation (mode 0, 1, 2, or 3) with each mode differing in respect to the
SCK polarity and phase and how the polarity and phase control the flow of data on the SPI bus. The AT25SF081
supports the two most common modes, SPI Modes 0 and 3. The only difference between SPI Modes 0 and 3 is the
polarity of the SCK signal when in the inactive state (when the SPI Master is in standby mode and not transferring any
data). With SPI Modes 0 and 3, data is always latched in on the rising edge of SCK and always output on the falling edge
of SCK.
Figure 4-1. SPI Mode 0 and 3
4.1 Dual Output Read
The AT25SF081 features a Dual-Output Read mode that allow two bits of data to be clocked out of the device every
clock cycle to improve throughput. To accomplish this, both the SI and SO pins are utilized as outputs for the transfer of
data bytes. With the Dual-Output Read Array command, the SI pin becomes an output along with the SO pin.
4.2 Quad Output Read
The AT25SF081 features a Quad-Output Read mode that allow four bits of data to be clocked out of the device every
clock cycle to improve throughput. To accomplish this, the SI, SO, WP, HOLD pins are utilized as outputs for the transfer
of data bytes. With the Quad-Output Read Array command, the SI, WP, HOLD pins become outputs along with the SO
pin.
5. Commands and Addressing
A valid instruction or operation must always be started by first asserting the CS pin. After the CS pin has been asserted,
the host controller must then clock out a valid 8-bit opcode on the SPI bus. Following the opcode, instruction dependent
information such as address and data bytes would then be clocked out by the host controller. All opcode, address, and
data bytes are transferred with the most-significant bit (MSB) first. An operation is ended by deasserting the CS pin.
Opcodes not supported by the AT25SF081 will be ignored by the device and no operation will be started. The device will
continue to ignore any data presented on the SI pin until the start of the next operation (CS pin being deasserted and
then reasserted). In addition, if the CS pin is deasserted before complete opcode and address information is sent to the
device, then no operation will be performed and the device will simply return to the idle state and wait for the next
operation.
Addressing of the device requires a total of three bytes of information to be sent, representing address bits A23-A0.
Since the upper address limit of the AT25SF081 memory array is 0FFFFFh, address bits A23-A20 are always ignored by
the device.
SCK
CS
SI
SO
MSB LSB
MSB LSB
7
AT25SF081
DS-25SF081–045I–8/2017
Table 5-1. Command Listing
Command Opcode
Clock
Frequency
Address
Bytes
Dummy
Bytes
Data
Bytes
Section
Link
Read Commands
Read Array
0Bh 0000 1011 Up to 85 MHz 3 1 1+
6.1
03h 0000 0011 Up to 50 MHz 3 0 1+
Dual Output Read 3Bh 0011 1011 Up to 85 MHz 3 1 1+ 6.2
Dual I/O Read BBh 1011 1011 Up to 85 MHz 3 0 1+ 6.3
Quad Output Read 6Bh 0110 1011 Up to 85 MHz 3 1 1+ 6.4
Quad I/O Read EBh 1110 1011 Up to 85 MHz 3 1 1+ 6.5
Continuous Read Mode Reset - Dual FFFFh 1111 1111
1111 1111 Up to 104 MHz 0 0 0 6.6
Continuous Read Mode Reset - Quad FFh 1111 1111 Up to 104 MHz 0 0 0 6.6
Program and Erase Commands
Block Erase (4 Kbytes) 20h 0010 0000 Up to 104 MHz 3 0 0
7.2Block Erase (32 Kbytes) 52h 0101 0010 Up to 104 MHz 3 0 0
Block Erase (64 Kbytes) D8h 1101 1000 Up to 104MHz 3 0 0
Chip Erase
60h 0110 0000 Up to 104 MHz 0 0 0
7.3
C7h 1100 0111 Up to 104 MHz 0 0 0
Byte/Page Program (1 to 256 Bytes) 02h 0000 0010 Up to 104 MHz 3 0 1+ 7.1
Protection Commands
Write Enable 06h 0000 0110 Up to 104 MHz 0 0 0 8.1
Write Disable 04h 0000 0100 Up to 104 MHz 0 0 0 8.2
Security Commands
Erase Security Register Page 44h 0100 0100 Up to 104 MHz 3 0 0 9.1
Program Security Register Page 42h 0100 0010 Up to 104 MHz 3 0 1+ 9.2
Read Security Register Page 48h 0100 1000 Up to 85MHz 3 1 1+ 9.3
Status Register Commands
Read Status Register Byte 1 05h 0000 0101 Up to 104 MHz 0 0 1
10.1
Read Status Register Byte 2 35h 0011 0101 Up to 104 MHz 0 0 1
Write Status Register 01h 0000 0001 Up to 104 MHz 0 0 1 or 2 10.2
Write Enable for Volatile Status
Register 50h 0101 0000 Up to 104MHz 0 0 0 10.3
Miscellaneous Commands
Read Manufacturer and Device ID 9Fh 1001 1111 Up to 104MHz 0 0 3 11.1
Read ID 90h 1001 0000 Up to 104 MHz 0 3 2 11.2
8
AT25SF081
DS-25SF081–045I–8/2017
6. Read Commands
6.1 Read Array (0Bh and 03h)
The Read Array command can be used to sequentially read a continuous stream of data from the device by simply
providing the clock signal once the initial starting address is specified. The device incorporates an internal address
counter that automatically increments every clock cycle.
Two opcodes (0Bh and 03h) can be used for the Read Array command. The use of each opcode depends on the
maximum clock frequency that will be used to read data from the device. The 0Bh opcode can be used at any clock
frequency up to the maximum specified by fRDHF, and the 03h opcode can be used for lower frequency read operations
up to the maximum specified by fRDLF.
To perform the Read Array operation, the CS pin must first be asserted and the appropriate opcode (0Bh or 03h) must be
clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the
starting address location of the first byte to read within the memory array. Following the three address bytes, an
additional dummy byte needs to be clocked into the device if the 0Bh opcode is used for the Read Array operation.
After the three address bytes (and the dummy byte if using opcode 0Bh) have been clocked in, additional clock cycles
will result in data being output on the SO pin. The data is always output with the MSB of a byte first. When the last byte
(0FFFFFh) of the memory array has been read, the device will continue reading back at the beginning of the array
(000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the array.
Deasserting the CS pin will terminate the read operation and put the SO pin into high-impedance state. The CS pin can
be deasserted at any time and does not require a full byte of data be read.
Figure 6-1. Read Array - 03h Opcode
Deep Power-Down B9h 1011 1001 Up to 104 MHz 0 0 0 11.3
Resume from Deep Power-Down ABh 1010 1011 Up to 104 MHz 0 0 0 11.4
Resume from Deep Power-Down and
Read ID ABh 1010 1011 Up to 104 MHz 0 3 1 11.4
Table 5-1. Command Listing
Command Opcode
Clock
Frequency
Address
Bytes
Dummy
Bytes
Data
Bytes
Section
Link
6&.
&6
6,
62
06% 06%
23&2'(
$$$$ $$$$$
06% 06%
''''''''''
$''5(66%,76$$
'$7$%<7(
+,*+,03('$1&(
9
AT25SF081
DS-25SF081–045I–8/2017
Figure 6-2. Read Array - 0Bh Opcode
6.2 Dual-Output Read Array (3Bh)
The Dual-Output Read Array command is similar to the standard Read Array command and can be used to sequentially
read a continuous stream of data from the device by simply providing the clock signal once the initial starting address has
been specified. Unlike the standard Read Array command, however, the Dual-Output Read Array command allows two
bits of data to be clocked out of the device on every clock cycle, rather than just one.
The Dual-Output Read Array command can be used at any clock frequency, up to the maximum specified by fRDDO. To
perform the Dual-Output Read Array operation, the CS pin must first be asserted and then the opcode 3Bh must be
clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the
location of the first byte to read within the memory array. Following the three address bytes, a single dummy byte must
also be clocked into the device.
After the three address bytes and the dummy byte have been clocked in, additional clock cycles will result in data being
output on both the SO and SI pins. The data is always output with the MSB of a byte first and the MSB is always output
on the SO pin. During the first clock cycle, bit seven of the first data byte is output on the SO pin, while bit six of the same
data byte is output on the SI pin. During the next clock cycle, bits five and four of the first data byte are output on the SO
and SI pins, respectively. The sequence continues with each byte of data being output after every four clock cycles.
When the last byte (0FFFFFh) of the memory array has been read, the device will continue reading from the beginning of
the array (000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the
array.Deasserting the CS pin will terminate the read operation and put the SO and SI pins into a high-impedance state.
The CS pin can be deasserted at any time and does not require that a full byte of data be read.
Figure 6-3. Dual-Output Read Array
6&.
&6
6,
62
06% 06%
23&2'(
$$$$ $$$$$
06%
;;;;;;;;
06% 06%
''''''''''
$''5(66%,76$$ '217&$5(
'$7$%<7(
+,*+,03('$1&(
SCK
CS
6,6,2
SO
MSB MSB
2310
00111011
6754101198123942434140373833363534313229304447484645
23&2'(
AAAA AAAAA
MSB
XXXXXXXX
MSB MSB MSB
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
$''5(66%,76$$ DON'T &$5( OUTPUT
DAT$%<7( OUTPUT
DAT$%<7(
HIGH-IMPEDANCE
1 0
AT25SF081
DS-25SF081–045I–8/2017
6.3 Dual-I/O Read Array (BBh)
The Dual-I/O Read Array command is similar to the Dual-Output Read Array command and can be used to sequentially
read a continuous stream of data from the device by simply providing the clock signal once the initial starting address
with two bits of address on each clock and two bits of data on every clock cycle.
The Dual-I/O Read Array command can be used at any clock frequency, up to the maximum specified by fRDDO. To
perform the Dual-I/O Read Array operation, the CS pin must first be asserted and then the opcode BBh must be clocked
into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the location
of the first byte to read within the memory array. Following the three address bytes, a single mode byte must also be
clocked into the device.
After the three address bytes and the mode byte have been clocked in, additional clock cycles will result in data being
output on both the SO and SI pins. The data is always output with the MSB of a byte first and the MSB is always output
on the SO pin. During the first clock cycle, bit seven of the first data byte is output on the SO pin, while bit six of the same
data byte is output on the SI pin. During the next clock cycle, bits five and four of the first data byte are output on the SO
and SI pins, respectively. The sequence continues with each byte of data being output after every four clock cycles.
When the last byte (0FFFFFh) of the memory array has been read, the device will continue reading from the beginning of
the array (000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the
array.Deasserting the CS pin will terminate the read operation and put the SO and SI pins into a high-impedance state.
The CS pin can be deasserted at any time and does not require that a full byte of data be read.
Figure 6-4. Dual I/O Read Array (Initial command or previous M5, M4≠1,0)
6.3.1 Dual-I/O Read Array (BBh) with Continuous Read Mode
The Fast Read Dual I/O command can further reduce instruction overhead through setting the Continuous Read Mode
bits (M7-0) after the input Address bits (A23-0), as shown in Figure 6-5. The upper nibble of the (M7-4) controls the
length of the next Fast Read Dual I/O command through the inclusion or exclusion of the first byte instruction code. The
lower nibble bits of the (M3-0) are don't care ("x"). However, the IO pins should be high-impedance prior to the falling
edge of the first data out clock. If the "Continuous Read Mode" bits M5-4 = (1,0), then the next Fast Read Dual I/O
command (after CS is raised and then lowered) does not require the BBH instruction code, as shown in Figure 15. This
reduces the command sequence by eight clocks and allows the Read address to be immediately entered after CS is
asserted low. If the "Continuous Read Mode" bits M5-4 do not equal to (1,0), the next command (after CS is raised and
then lowered) requires the first byte instruction code, thus returning to normal operation. A Continuous Read Mode Reset
command can also be used to reset (M7-0) before issuing normal commands.
I/O0
(SI)
SCK
I/O1
(SO)
CS
MSB
MSB
2310
10111011
675410119812 2321 2219 20
Opcode
A
22
A
20
A
18
A
16
A
0
M
6
M
4
A
14
A
Address Bits
A23-A16
M
3
M
2
M
1
M
0
Address Bits
A15-A8 A7-A0 M7-M0
MSB
A
23
A
21
A
19
A
17
A
1
M
7
M
5
A
15
A
2725 2624
D
6
D
4
D
3
D
2
D
1
D
0
Byte 1
D
7
D
5
D
6
D
7
Byte 2
1 1
AT25SF081
DS-25SF081–045I–8/2017
Figure 6-5. Dual-I/O Read Array (Previous command set M5, M4 = 1,0)
6.4 Quad-Output Read Array (6Bh)
The Quad-Output Read Array command is similar to the Dual-Output Read Array command. The Quad-Output Read
Array command allows four bits of data to be clocked out of the device on every clock cycle, rather than just one or two.
The Quad Enable bit (QE) of the Status Register must be set to enable for the Quad-Output Read Array instruction.
The Quad-Output Read Array command can be used at any clock frequency, up to the maximum specified by fRDQO. To
perform the Quad-Output Read Array operation, the CS pin must first be asserted and then the opcode 6Bh must be
clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the
location of the first byte to read within the memory array. Following the three address bytes, a single dummy byte must
also be clocked into the device.
After the three address bytes and the dummy byte have been clocked in, additional clock cycles will result in data being
output on the I/O3-0 pins. The data is always output with the MSB of a byte first and the MSB is always output on the I/O3
pin. During the first clock cycle, bit 7 of the first data byte will be output on the I/O3 pin while bits 6, 5, and 4 of the same
data byte will be output on the I/O2, I/O1, and I/O0 pins, respectively. During the next clock cycle, bits 3, 2, 1, and 0 of the
first data byte will be output on the I/O3, I/O2, I/O1 and I/O0 pins, respectively.
The sequence continues with each byte of data being output after every two clock cycles. When the last byte (0FFFFFh)
of the memory array has been read, the device will continue reading from the beginning of the array (000000h). No
delays will be incurred when wrapping around from the end of the array to the beginning of the array.Deasserting the CS
pin will terminate the read operation and put the WP, HOLD, SO, SI pins into a high-impedance state. The CS pin can be
deasserted at any time and does not require that a full byte of data be read.
I/O0
(SI)
SCK
I/O1
(SO)
CS
MSB
2310675410119812 1715 1613 14
A
22
A
20
A
18
A
16
A
0
M
6
M
4
A
14
A
Address Bits
A23-A16
M
3
M
2
M
1
M
0
Address Bits
A15-A8 A7-A0
M7-M0
MSB
A
23
A
21
A
19
A
17
A
1
M
7
M
5
A
15
A
2119 2018
D
6
D
4
D
3
D
2
D
1
D
0
Byte 1
D
7
D
5
D
6
D
7
Byte 2
1 2
AT25SF081
DS-25SF081–045I–8/2017
Figure 6-6. Quad-Output Read Array
6.5 Quad-I/O Read Array(EBh)
The Quad-I/O Read Array command is similar to the Quad-Output Read Array command. The Quad-I/O Read Array
command allows four bits of address to be clocked into the device on every clock cycle, rather than just one.
The Quad-I/O Read Array command can be used at any clock frequency, up to the maximum specified by fRDQO. To
perform the Quad-I/O Read Array operation, the CS pin must first be asserted and then the opcode EBh must be clocked
into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify the location
of the first byte to read within the memory array. Following the three address bytes, a single mode byte must also be
clocked into the device.
After the three address bytes, the mode byte and two dummy bytes have been clocked in, additional clock cycles will
result in data being output on the I/O3-0 pins. The data is always output with the MSB of a byte first and the MSB is always
output on the I/O3 pin. During the first clock cycle, bit 7 of the first data byte will be output on the I/O3 pin while bits 6, 5,
and 4 of the same data byte will be output on the I/O2, I/O1 and I/O0 pins, respectively. During the next clock cycle, bits 3,
2, 1, and 0 of the first data byte will be output on the I/O3, I/O2, I/O1 and I/O0 pins, respectively. The sequence continues
with each byte of data being output after every two clock cycles.
When the last byte (0FFFFFh) of the memory array has been read, the device will continue reading from the beginning of
the array (000000h). No delays will be incurred when wrapping around from the end of the array to the beginning of the
array.Deasserting the CS pin will terminate the read operation and put the I/O3, I/O2, I/O1 and I/O0 pins into a high-
impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be read.The
Quad Enable bit (QE) of the Status Register must be set to enable for the Quad-I/O Read Array instruction.
I/O0
(SI)
SCK
06% 06%
2310
01101011
675410119812 394243414037 3833 36353431 3229 30 44 47 484645
Opcode
AAAA AAAAA
06%
XXXXXXXX
Address Bits A23-A0 Don't Care
Byte 1
OUT
Byte 2
OUT
Byte 3
OUT
Byte 4
OUT
Byte 5
OUT
I/O1
(SO)
High-impedance
D
5
D
1
D
5
D
1
D
5
D
1
D
5
D
1
D
5
D
1
I/O2
(WP)
High-impedance
D
6
D
2
D
6
D
2
D
6
D
2
D
6
D
2
D
6
D
2
I/O3
(HOLD) MSB MSB MSB MSB MSB
High-impedance
D
7
D
3
D
7
D
3
D
7
D
3
D
7
D
3
D
7
D
3
D
4
D
0
D
4
D
0
D
4
D
0
D
4
D
0
D
4
D
0
CS
1 3
AT25SF081
DS-25SF081–045I–8/2017
Figure 6-7. Quad-I/O Read Array (Initial command or previous M5, M4 ≠ 1,0)
6.5.1 Quad-I/O Read Array (EBh) with Continuous Read Mode
The Fast Read Quad I/O command can further reduce instruction overhead through setting the Continuous Read Mode
bits (M7-0) after the input Address bits (A23-0), as shown in Figure 6-6. The upper nibble (M7-4) of the Continuous Read
Mode bits controls the length of the next Fast Read Quad I/O command through the inclusion or exclusion of the first byte
instruction code. The lower nibble bits (M3-0) of the Continuous Read Mode bits are don't care. However, the IO pins
should be high-impedance prior to the falling edge of the first data out clock. If the Continuous Read Mode bits M5-4 =
(1,0), then the next Quad-I/O Read Array command (after CS is raised and then lowered) does not require the EBh
instruction code, as shown in Fig 6-8. This reduces the command sequence by eight clocks and allows the Read address
to be immediately entered after CS is asserted low. If the "Continuous Read Mode" bits M5-4 do not equal to (1,0), the
next command (after CS is raised and then lowered) requires the first byte instruction code, thus returning to normal
operation. A Continuous Read Mode Reset command can also be used to reset (M7-0) before issuing normal
commands.
Figure 6-8. Quad I/O Read Array with Continuous Read Mode (Previous Command Set M5-4 =1,0)
6.6 Continuous Read Mode Reset (FFh or FFFFh)
The Continuous Read Mode bits are used in conjunction with the Dual I/O Read Array and the Quad I/O Read Array
commands to provide the highest random Flash memory access rate with minimum SPI instruction overhead, thus
allowing more efficient XIP (execute in place) with this device family.
I/O
0
(SI)
SCK
I/O
1
(SO)
CS
MSB
2310
11101011
67541011981917 1816
Opcode
A
20
A
16
A
12
A
8
A23-A16 A15-A8
A
21
A
17
A
13
A
9
2321 2220
D
4
D
1
D
0
D
5
D
4
Byte 1
D
5
D
0
D
1
Byte 2
I/O
2
(WP)
A
22
A
18
A
14
A
10
D
2
D
6
D
6
D
2
I/O
3
(HOLD)
A
23
A
19
A
15
A
11
D
3
D
7
D
7
D
3
14 151312
A
4
A
0
M
4
M
0
A7-A0 M7-M0
A
6
A
2
M
6
M
2
A
7
A
3
M
7
M
3
A
5
A
1
M
5
M
1
Dummy
I/O0
(SI)
SCK
I/O1
(SO)
CS
23106754101198
A
20
A
16
A
12
A
8
A23-A16 A15-A8
A
21
A
17
A
13
A
9
D
4
D
1
D
0
D
5
D
4
Byte 1
D
5
D
0
D
1
Byte 2
I/O2
(WP)
A
22
A
18
A
14
A
10
D
2
D
6
D
6
D
2
I/O3
(HOLD)
A
23
A
19
A
15
A
11
D
3
D
7
D
7
D
3
14 151312
A
4
A
0
M
4
M
0
A7-A0 M7-M0
A
6
A
2
M
6
M
2
A
7
A
3
M
7
M
3
A
5
A
1
M
5
M
1
Dummy
1 4
AT25SF081
DS-25SF081–045I–8/2017
The "Continuous Read Mode" bits M7-0 are set by the Dual/Quad I/O Read Array commands. M5-4 are used to control
whether the 8-bit SPI instruction code (BBh or EBh) is needed or not for the next instruction. When M5-4 = (1,0), the next
instruction will be treated the same as the current Dual/Quad I/O Read Array command without needing the 8-bit
instruction code. When M5-4 do not equal (1,0), the device returns to normal SPI instruction mode, in which all
instructions can be accepted. M7-6 and M3-0 are reserved bits for future use; either 0 or 1 values can be used.
See Figure 6-9, the Continuous Read Mode Reset instruction (FFh or FFFFh) can be used to set M4 = 1, thus the device
will release the Continuous Read Mode and return to normal SPI operation.
To reset Continuous Read Mode during Quad I/O operation, only eight clocks are needed to shift in instruction FFh. To
reset Continuous Read Mode during Dual I/O operation, sixteen clocks are needed to shift in instruction FFFFh.
Figure 6-9. Continuous Read Mode Reset (Quad)
Figure 6-10. Continuous Read Mode Reset (Dual)
7. Program and Erase Commands
7.1 Byte/Page Program (02h)
The Byte/Page Program command allows anywhere from a single byte of data to 256 bytes of data to be programmed
into previously erased memory locations. An erased memory location is one that has all eight bits set to the logical “1”
state (a byte value of FFh). Before a Byte/Page Program command can be started, the Write Enable command must
have been previously issued to the device (see “Write Enable (06h)” on page 17) to set the Write Enable Latch (WEL) bit
of the Status Register to a logical “1” state.
To perform a Byte/Page Program command, an opcode of 02h must be clocked into the device followed by the three
address bytes denoting the first byte location of the memory array to begin programming at. After the address bytes have
been clocked in, data can then be clocked into the device and will be stored in an internal buffer.
If the starting memory address denoted by A23-A0 does not fall on an even 256-byte page boundary (A7-A0 are not all
0), then special circumstances regarding which memory locations to be programmed will apply. In this situation, any data
S
CK
CS
SI
SO
MSB
2310
11111111
6754
OPCODE
DON’T CARE
10 119814151312
11111111
S
CK
CS
SI
SO
MSB
2310
11111111
6754
OPCODE
DON’T CARE
1 5
AT25SF081
DS-25SF081–045I–8/2017
that is sent to the device that goes beyond the end of the page will wrap around back to the beginning of the same page.
For example, if the starting address denoted by A23-A0 is 0000FEh, and three bytes of data are sent to the device, then
the first two bytes of data will be programmed at addresses 0000FEh and 0000FFh while the last byte of data will be
programmed at address 000000h. The remaining bytes in the page (addresses 000001h through 0000FDh) will not be
programmed and will remain in the erased state (FFh). In addition, if more than 256 bytes of data are sent to the device,
then only the last 256 bytes sent will be latched into the internal buffer.
When the CS pin is deasserted, the device will take the data stored in the internal buffer and program it into the
appropriate memory array locations based on the starting address specified by A23-A0 and the number of data bytes
sent to the device. If less than 256 bytes of data were sent to the device, then the remaining bytes within the page will not
be programmed and will remain in the erased state (FFh). The programming of the data bytes is internally self-timed and
should take place in a time of tPP or tBP if only programming a single byte.
The three address bytes and at least one complete byte of data must be clocked into the device before the CS pin is
deasserted, and the CS pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device
will abort the operation and no data will be programmed into the memory array. In addition, if the memory is in the
protected state (see “Non-Volatile Protection” on page 18), then the Byte/Page Program command will not be executed,
and the device will return to the idle state once the CS pin has been deasserted. The WEL bit in the Status Register will
be reset back to the logical “0” state if the program cycle aborts due to an incomplete address being sent, an incomplete
byte of data being sent, the CS pin being deasserted on uneven byte boundaries, or because the memory location to be
programmed is protected.
While the device is programming, the Status Register can be read and will indicate that the device is busy. For faster
throughput, it is recommended that the Status Register be polled rather than waiting the tBP or tPP time to determine if the
data bytes have finished programming. At some point before the program cycle completes, the WEL bit in the Status
Register will be reset back to the logical “0” state.
Figure 7-1. Byte Program
Figure 7-2. Page Program
6&.
&6
6,
62
06% 06%
23&2'(
+,*+,03('$1&(
$$$$ $$$$$
06%
''''''''
$''5(66%,76$$ '$7$,1
6&.
&6
6,
62
06% 06%
23&2'(
+,*+,03('$1&(
$$ $$$$
06%
''''''''
$''5(66%,76$$ '$7$,1%<7(
06%
''''''''
'$7$,1%<7(Q
1 6
AT25SF081
DS-25SF081–045I–8/2017
7.2 Block Erase (20h, 52h, or D8h)
A block of 4, 32, or 64 Kbytes can be erased (all bits set to the logical “1” state) in a single operation by using one of three
different opcodes for the Block Erase command. An opcode of 20h is used for a 4-Kbyte erase, an opcode of 52h is used
for a 32-Kbyte erase, or D8h is used for a 64-Kbyte erase. Before a Block Erase command can be started, the Write
Enable command must have been previously issued to the device to set the WEL bit of the Status Register to a logical “1”
state.
To perform a Block Erase, the CS pin must first be asserted and the appropriate opcode (20h, 52h, or D8h) must be
clocked into the device. After the opcode has been clocked in, the three address bytes specifying an address within the
4- or 32- or 64-Kbyte block to be erased must be clocked in. Any additional data clocked into the device will be ignored.
When the CS pin is deasserted, the device will erase the appropriate block. The erasing of the block is internally self-
timed and should take place in a time of tBLKE.
Since the Block Erase command erases a region of bytes, the lower order address bits do not need to be decoded by the
device. Therefore, for a 4-Kbyte erase, address bits A11-A0 will be ignored by the device and their values can be either a
logical “1” or “0”. For a 32-Kbyte erase, address bits A14-A0 will be ignored by the device. For a 64-Kbyte erase, address
bits A15-A0 will be ignored by the device. Despite the lower order address bits not being decoded by the device, the
complete three address bytes must still be clocked into the device before the CS pin is deasserted, and the CS pin must
be deasserted on an byte boundary (multiples of eight bits); otherwise, the device will abort the operation and no erase
operation will be performed.
If the memory is in the protected state, then the Block Erase command will not be executed, and the device will return to
the idle state once the CS pin has been deasserted.
The WEL bit in the Status Register will be reset back to the logical “0” state if the erase cycle aborts due to an incomplete
address being sent, the CS pin being deasserted on uneven byte boundaries, or because a memory location within the
region to be erased is protected.
While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the device
is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the tBLKE time to
determine if the device has finished erasing. At some point before the erase cycle completes, the WEL bit in the Status
Register will be reset back to the logical “0” state.
Figure 7-3. Block Erase
7.3 Chip Erase (60h or C7h)
The entire memory array can be erased in a single operation by using the Chip Erase command. Before a Chip Erase
command can be started, the Write Enable command must have been previously issued to the device to set the WEL bit
of the Status Register to a logical “1” state.
Two opcodes (60h and C7h) can be used for the Chip Erase command. There is no difference in device functionality
when utilizing the two opcodes, so they can be used interchangeably. To perform a Chip Erase, one of the two opcodes
must be clocked into the device. Since the entire memory array is to be erased, no address bytes need to be clocked into
6&.
&6
6,
62
06% 06%
&&&&&&&&
23&2'(
$$$$ $$$$$ $ $ $
$''5(66%,76$$
+,*+,03('$1&(
1 7
AT25SF081
DS-25SF081–045I–8/2017
the device, and any data clocked in after the opcode will be ignored. When the CS pin is deasserted, the device will erase
the entire memory array. The erasing of the device is internally self-timed and should take place in a time of tCHPE.
The complete opcode must be clocked into the device before the CS pin is deasserted, and the CS pin must be
deasserted on an byte boundary (multiples of eight bits); otherwise, no erase will be performed. In addition, if the memory
array is in the protected state, then the Chip Erase command will not be executed, and the device will return to the idle
state once the CS pin has been deasserted. The WEL bit in the Status Register will be reset back to the logical “0” state
if the CS pin is deasserted on uneven byte boundaries or if the memory is in the protected state.
While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the device
is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the tCHPE time to
determine if the device has finished erasing. At some point before the erase cycle completes, the WEL bit in the Status
Register will be reset back to the logical “0” state.
Figure 7-4. Chip Erase
8. Protection Commands and Features
8.1 Write Enable (06h)
The Write Enable command is used to set the Write Enable Latch (WEL) bit in the Status Register to a logical “1” state.
The WEL bit must be set before a Byte/Page Program, Erase, Program Security Register Pages, Erase Security Register
Pages or Write Status Register command can be executed. This makes the issuance of these commands a two step
process, thereby reducing the chances of a command being accidentally or erroneously executed. If the WEL bit in the
Status Register is not set prior to the issuance of one of these commands, then the command will not be executed.
To issue the Write Enable command, the CS pin must first be asserted and the opcode of 06h must be clocked into the
device. No address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored.
When the CS pin is deasserted, the WEL bit in the Status Register will be set to a logical “1”. The complete opcode must
be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an byte boundary
(multiples of eight bits); otherwise, the device will abort the operation and the WEL bit state will not change.
Figure 8-1. Write Enable
6&.
&6
6,
62
06%
&&&&&&&&
23&2'(
+,*+,03('$1&(
6&.
&6
6,
62
06%
23&2'(
+,*+,03('$1&(
1 8
AT25SF081
DS-25SF081–045I–8/2017
8.2 Write Disable (04h)
The Write Disable command is used to reset the Write Enable Latch (WEL) bit in the Status Register to the logical “0”
state. With the WEL bit reset, all Byte/Page Program, Erase, Program Security Register Page, and Write Status Register
commands will not be executed. Other conditions can also cause the WEL bit to be reset; for more details, refer to the
WEL bit section of the Status Register description.
To issue the Write Disable command, the CS pin must first be asserted and the opcode of 04h must be clocked into the
device. No address bytes need to be clocked into the device, and any data clocked in after the opcode will be ignored.
When the CS pin is deasserted, the WEL bit in the Status Register will be reset to a logical “0”. The complete opcode
must be clocked into the device before the CS pin is deasserted, and the CS pin must be deasserted on an byte
boundary (multiples of eight bits); otherwise, the device will abort the operation and the WEL bit state will not change.
Figure 8-2. Write Disable
8.3 Non-Volatile Protection
The device can be software protected against erroneous or malicious program or erase operations by utilizing the Non-
Volatile Protection feature of the device. Non-Volatile Protection can be enabled or disabled by using the Write Status
Register command to change the value of the Protection (CMP, SEC, TB, BP2, BP1, BP0) bits in the Status Register.
The following table outlines the states of the Protection bits and the associated protection area
.
6&.
&6
6,
62
06%
23&2'(
+,*+,03('$1&(
Table 8-1. Memory Array with CMP=0
Protection Bits Memory Content
SEC TB BP2 BP1 BP0 Address Range Portion
X X 0 0 0 None None
00001 0F0000h-0FFFFFh Upper 1/16
00010 0E0000h-0FFFFFh Upper 1/8
00011 0C0000h-0FFFFFh Upper 1/4
00100 080000h-0FFFFFh Upper 1/2
01001 000000h-00FFFFh Lower 1/16
01010 000000h-01FFFFh Lower 1/8
01011 000000h-03FFFFh Lower 1/4
01100 000000h-0FFFFFh Lower 1/2
0 X 1 0 1 000000h-0FFFFFh ALL
X X 1 1 X 000000h-0FFFFFh ALL
1 9
AT25SF081
DS-25SF081–045I–8/2017
Table 8-2. Memory Array Protection with CMP=1
10001 0FF000h-0FFFFFh Upper 1/256
10010 0FE000h-0FFFFFh Upper 1/128
10011 0FC000h-0FFFFFh Upper 1/64
1010X 0F8000h-0FFFFFh Upper 1/32
11001 000000h-000FFFh Lower 1/256
11010 000000h-001FFFh Lower 1/128
11011 000000h-003FFFh Lower 1/64
1110X 000000h-007FFFh Lower 1/32
Protection Bits Memory Content
SEC TB BP2 BP1 BP0 Address Range Portion
X X 0 0 0 000000h-0FFFFFh All
00001 000000h-0EFFFFh Lower 15/16
00010 000000h-0DFFFFh Lower 7/8
00011 000000h-0BFFFFh Lower 3/4
00100 000000h-07FFFFh Lower 1/2
01001 010000h-0FFFFFh Upper 15/16
01010 020000h-0FFFFFh Upper 7/8
01011 040000h-0FFFFFh Upper 3/4
01100 080000H-0FFFFFH Upper 1/2
0 X 1 0 1 NONE NONE
X X 1 1 X NONE NONE
10001 000000h-0FEFFFh Lower 255/256
10010 000000h-0FDFFFh Lower 127/128
10011 000000h-0FBFFFh Lower 63/64
1010X 000000h-0F7FFFh Lower 31/32
11001 001000h-0FFFFFh Upper 255/256
11010 002000h-0FFFFFh Upper 127/128
11011 004000h-0FFFFFh Upper 63/64
1110X 008000h-0FFFFFh Upper 31/32
Table 8-1. Memory Array with CMP=0
Protection Bits Memory Content
2 0
AT25SF081
DS-25SF081–045I–8/2017
As a safeguard against accidental or erroneous protecting or unprotecting of the memory array, the Protection can be
locked from updates by using the WP pin (see “Protected States and the Write Protect Pin” on page 20 for more details).
8.4 Protected States and the Write Protect Pin
The WP pin is not linked to the memory array itself and has no direct effect on the protection status of the memory array.
Instead, the WP pin, is used to control the hardware locking mechanism of the device.
If the WP pin is permanently connected to GND, then the protection bits cannot be changed.
9. Security Register Commands
The device contains three extra pages called Security Registers that can be used for purposes such as unique device
serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc. The Security Registers are
independent of the main Flash memory.
Each page of the Security Register can be erased and programmed independently. Each page can also be
independently locked to prevent further changes.
9.1 Erase Security Registers (44h)
Before an erase Security Register Page command can be started, the Write Enable command must have been
previously issued to the device to set the WEL bit of the Status Register to a logical "1" state.
To perform an Erase Security Register Page command, the CS pin must first be asserted and the opcode 44h must be
clocked into the device. After the opcode has been clocked in, the three address bytes specifying the Security Register
Page to be erased must be clocked in. When the CS pin is deasserted, the device will erase the appropriate block. The
erasing of the block is internally self-timed and should take place in a time of tBE.
Since the Erase Security Register Page command erases a region of bytes, the lower order address bits do not need to
be decoded by the device. Therefore address bits A7-A0 will be ignored by the device. Despite the lower order address
bits not being decoded by the device, the complete three address bytes must still be clocked into the device before the
CS pin is deasserted, and the CS pin must be deasserted right after the last address bit (A0); otherwise, the device will
abort the operation and no erase operation will be performed.
While the device is executing a successful erase cycle, the Status Register can be read and will indicate that the device
is busy. For faster throughput, it is recommended that the Status Register be polled rather than waiting the tBE time to
determine if the device has finished erasing. At some point before the erase cycle completes, the RDY/BSY bit in the
Status Register will be reset back to the logical "0" state.
The WEL bit in the Status Register will be reset back to the logical "0" state if the erase cycle aborts due to an incomplete
address being sent, the CS pin being deasserted on uneven byte boundaries, or because a memory location within the
region to be erased is protected.
The Security Registers Lock Bits (LB3-LB1) in the Status Register can be used to OTP protect the security registers.
Once a Lock Bit is set to 1, the corresponding Security Register will be permanently locked. The Erase Security Register
Page instruction will be ignored for Security Registers which have their Lock Bit set.
Table 9-1. Security Register Addresses for Erase Security Register Page Command
Address A23-A16 A15-A8 A7-A0
Security Register 1 00H 01H Don’t Care
Security Register 2 00H 02H Don’t Care
Security Register 3 00H 03H Don’t Care
2 1
AT25SF081
DS-25SF081–045I–8/2017
Figure 9-1. Erase Security Register Page
9.2 Program Security Registers (42h)
The Program Security Registers command utilizes the internal 256-byte buffer for processing. Therefore, the contents of
the buffer will be altered from its previous state when this command is issued.
The Security Registers can be programmed in a similar fashion to the Program Array operation up to the maximum clock
frequency specified by fCLK. Before a Program Security Registers command can be started, the Write Enable command
must have been previously issued to the device (see “Write Enable (06h)” on page 17) to set the Write Enable Latch
(WEL) bit of the Status Register to a logical “1” state. To program the Security Registers, the CS pin must first be
asserted and the opcode of 42h must be clocked into the device. After the opcode has been clocked in, the three address
bytes must be clocked in to specify the starting address location of the first byte to program within the Security Register.
Table 9-2. Security Register Addresses for Program Security Registers Command
Figure 9-2. Program Security Registers
9.3 Read Security Registers (48h)
The Security Register can be sequentially read in a similar fashion to the Read Array operation up to the maximum clock
frequency specified by fCLK. To read the Security Register, the CS pin must first be asserted and the opcode of 48h must
be clocked into the device. After the opcode has been clocked in, the three address bytes must be clocked in to specify
the starting address location of the first byte to read within the Security Register. Following the three address bytes, one
dummy byte must be clocked into the device before data can be output.
After the three address bytes and the dummy byte have been clocked in, additional clock cycles will result in Security
Register data being output on the SO pin. When the last byte (0003FFh) of the Security Register has been read, the
6&.
&6
6,
MSB
2310
6754
OPCODE
$$ $$$
%,7$''5(66
Address A23-A16 A15-A8 A7-A0
Security Register 1 00H 01H Byte Address
Security Register 2 00H 02H Byte Address
Security Register 3 00H 03H Byte Address
6&.
&6
6,
62
MSB MS B
2310
001
6754983937383336353431322930
OPCODE
HIGH-IMPEDANCE
AA AAAA
MSB
DDDDDDDD
ADDRESS BITS A23-A0 DATA IN BYTE 1
MSB
DDDDDDDD
DATA IN BYTE n
2 2
AT25SF081
DS-25SF081–045I–8/2017
device will continue reading back at the beginning of the register (000000h). No delays will be incurred when wrapping
around from the end of the register to the beginning of the register.
Deasserting the CS pin will terminate the read operation and put the SO pin into a high-impedance state. The CS pin can
be deasserted at any time and does not require that a full byte of data be read.
Figure 9-3. Read Security Registers
10. Status Register Commands
10.1 Read Status Register (05h and 35h)
The Status Register can be read to determine the device's ready/busy status, as well as the status of many other
functions such as Block Protection. The Status Register can be read at any time, including during an internally self-timed
program or erase operation.
To read Status Register Byte 1, the CS pin must first be asserted and the opcode of 05h must be clocked into the device.
After the opcode has been clocked in, the device will begin outputting Status Register Byte 1 data on the SO pin during
every subsequent clock cycle. After the last bit (bit 0) of Status Register Byte 1 has been clocked out, the sequence will
repeat itself starting again with bit 7 as long as the CS pin remains asserted and the clock pin is being pulsed. The data
in the Status Register is constantly being updated, so each repeating sequence will output new data. Deasserting the CS
pin will terminate the Read Status Register operation and put the SO pin into a high-impedance state. The CS pin can be
deasserted at any time and does not require that a full byte of data be read.
To read Status Register Byte 2, the CS pin must first be asserted and the opcode of 35h must be clocked into the device.
After the opcode has been clocked in, the device will begin outputting Status Register Byte 2 data on the SO pin during
every subsequent clock cycle. After the last bit (bit 0) of Status Register Byte 2 has been clocked out, the sequence will
repeat itself starting again with bit 7 as long as the CS pin remains asserted and the clock pin is being pulsed. The data
in the Status Register is constantly being updated, so each repeating sequence will output new data. Deasserting the CS
pin will terminate the Read Status Register operation and put the SO pin into a high-impedance state. The CS pin can be
deasserted at any time and does not require that a full byte of data be read.
Table 9-3. Security Register Addresses for Read Security Registers Command
Address A23-A16 A15-A8 A7-A0
Security Register 1 00H 01H Byte Address
Security Register 2 00H 02H Byte Address
Security Register 3 00H 03H Byte Address
6&.
&6
6,
62
MSB MSB
2310
01
6754101198123336353431322930
OPCODE
AAAA AAAAA XXX
MSB MSB
DDDDDDDDDD
ADDRESS BITS A23-A0
MSB
XXXXXX
DON'T CARE
DATA BYTE 1
HIGH-IMPEDANCE
2 3
AT25SF081
DS-25SF081–045I–8/2017
Notes: 1. Only bits 7 through 2 of the Status Register can be modified when using the Write Status Register command.
2. R/W = Readable and writable
R = Readable only
Figure 10-1. Read Status Register Byte 1
Table 10-1. Status Register Format - Byte 1
Bit(1) Name Type(2) Description
7SRP0 Status Register Protection bit-0 R/W See Table 10-3 on Status Register Protection
6SEC Block Protection R/W See Table 8-1 and 8-2 on Non-Volatile Protection
5TB Top or Bottom Protection R/W See Table 8-1 and 8-2 on Non-Volatile Protection
4BP2 Block Protection bit-2 R/W See Table 8-1 and 8-2 on Non-Volatile Protection
3BP1 Block Protection bit-1 R/W See Table 8-1 and 8-2 on Non-Volatile Protection
2BP0 Block Protection bit-0 R/W See Table 8-1 and 8-2 on Non-Volatile Protection
1WEL Write Enable Latch Status R0Device is not Write Enabled (default)
1Device is Write Enabled
0RDY/BSY Ready/Busy Status R0Device is ready
1Device is busy with an internal operation
SCK
CS
SI
SO
MSB
2310
00000101
675410119812212217201918151613142324282927262530
23&2'(
MSB MSB
DDDDDD DDDD
MSB
DDDDDDDD D DDD D D
67$7865(*,67(5
BYTE 1
HIGH-IMPEDANCE
67$7865(*,67(5 67$7865(*,67(5
BYTE 1 BYTE 1
Table 10-2. Status Register Format – Byte 2
Bit(1) Name Type(2) Description
7RES Reserve for future use R 0 Reserve for future use
6CMP Complement Block Protection R/W 0 See table on Block Protection
5LB3 Lock Security Register 3 R/W
0Security Register page-3 is not locked (default)
1Security Register page-3 cannot be erased/programmed
4LB2 Lock Security Register 2 R/W
0Security Register page-2 is not locked (default)
1Security Register page-2 cannot be erased/programmed
3LB1 Lock Security Register 1 R/W
0Security Register page-1 is not locked (default)
1Security Register page-1 cannot be erased/programmed
2RES Reserved for future use R 0 Reserved for future use
1QE Quad Enable R/W
0HOLD and WP function normally (default)
1HOLD and WP are I/O pins
0SRP1 Status Register Protect bit-1 R/W See table on Status Register Protection
2 4
AT25SF081
DS-25SF081–045I–8/2017
Notes: 1. Only bits 6 through 3, 1, and 0 of the Status Register can be modified when using the Write Status Register command
2. R/W = Readable and writable
R = Readable only.
Figure 10-2. Read Status Register Byte 2
10.1.1 SRP1, SRP0 Bits
The SRP1 and SRP0 bits control whether the Status Register can be modified. The state of the WP pin along with the
values of the SRP1 and SRP0 determine if the device is software protected, hardware protected, or permanently
protected (see Table 10-3).
10.1.2 CMP, SEC, TB, BP2, BP1, BP0 Bits
The CMP, SEC, TB, BP2, BP1, and BP0 bits control which portions of the array are protected from erase and program
operations (see Tables 8-1 and 8-2).
The CMP bit complements the effect of the other bits.
The SEC bit selects between large and small block size protection.
The TB bit selects between top of the array or bottom of the array protection.
The BP2, BP1, and BP0 bits determine how much of the array is protected.
SCK
CS
SI
SO
MSB
2310
000101
675410119812212217201918151613142324282927262530
23&2'(
MSB MSB
DDDDDD DDDD
MSB
DDDDDDDD D DDD D D
67$7865(*,67(5
BYTE 2
HIGH-IMPEDANCE
67$7865(*,67(5 67$7865(*,67(5
BYTE 2 BYTE 2
Table 10-3. Status Register Protection Table
SRP1 SRP0 WP Status Register Description
0 0 X Software Protected The Status Register can be written to after a Write Enable
instruction, WEL=1.(Factory Default)
0 1 0 Hardware Protected WP=0, the Status Register is locked and cannot be written.
0 1 1 Hardware
Unprotected
WP =1, the Status Register is unlocked and can be written to
after a Write Enable instruction, WEL=1.
1 0 X Power Supply Lock-
Down (1)
1. When SRP1, SRP0 = (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to the (0, 0) state.
Status Register is protected and cannot be written to again
until the next Power-Down, Power-Up cycle.
1 1 X One Time Program Status Register is permanently protected and cannot be
written to.
2 5
AT25SF081
DS-25SF081–045I–8/2017
10.1.3 WEL Bit
The WEL bit indicates the current status of the internal Write Enable Latch. When the WEL bit is in the logical “0” state,
the device will not accept any Byte/Page Program, erase, Program Security Register, Erase Security Register, or Write
Status Register commands. The WEL bit defaults to the logical “0” state after a device power-up or reset operation. In
addition, the WEL bit will be reset to the logical “0” state automatically under the following conditions:
Write Disable operation completes successfully
Write Status Register operation completes successfully or aborts
Program Security Register operation completes successfully or aborts
Erase Security Register operation completes successfully or aborts
Byte/Page Program operation completes successfully or aborts
Block Erase operation completes successfully or aborts
Chip Erase operation completes successfully or aborts
If the WEL bit is in the logical “1” state, it will not be reset to a logical “0” if an operation aborts due to an incomplete or
unrecognized opcode being clocked into the device before the CS pin is deasserted. In order for the WEL bit to be reset
when an operation aborts prematurely, the entire opcode for a Byte/Page Program, erase, Program Security Register,
Erase Security Register, or Write Status Register command must have been clocked into the device.
10.1.4 RDY/BSY Bit
The RDY/BSY bit is used to determine whether or not an internal operation, such as a program or erase, is in progress.
To poll the RDY/BSY bit to detect the completion of a program or erase cycle, new Status Register data must be
continually clocked out of the device until the state of the RDY/BSY bit changes from a logical “1” to a logical “0”.
10.1.5 LB3, LB2, LB1 Bits
The LB3, LB2, and LB1 bits are used to determine if any of the three Security Register pages are locked.
The LB3 bit is in the logical “1” state if Security Register page-2 is locked and cannot be erased or programmed.
The LB2 bit is in the logical “1” state if Security Register page-1 is locked and cannot be erased or programmed.
The LB1 bit is in the logical “1” state if Security Register page-0 is locked and cannot be erased or programmed.
10.1.6 QE Bit
The QE bit is used to determine if the device is in the Quad Enabled mode. If the QE bit is in the logical “1” state, then the
HOLD and WP pins functions as input/output pins similar to the SI and SO. If the QE bit is in the logical “0” state, then the
HOLD pin functions as an input only and the WP pin functions as an input only.
10.2 Write Status Register (01h)
The Write Status Register command is used to modify the Block Protection, Security Register Lock-down, Quad Enable,
and Status Register Protection. Before the Write Status Register command can be issued, the Write Enable command
must have been previously issued to set the WEL bit in the Status Register to a logical “1”.
To issue the Write Status Register command, the CS pin must first be asserted and the opcode of 01h must be clocked
into the device followed by one or two bytes of data. The first byte of data consists of the SRP0, SEC, TB, BP2, BP1, BP0
bit values and 2 dummy bits. The second byte is optional and consists of 1 dummy bit, the CMP, LB3, LB2, LB1, 1
dummy bit, the QE, and 1 dummy bit. When the CS pin is deasserted, the bit values in the Status Register will be
modified, and the WEL bit in the Status Register will be reset back to a logical “0”.
The complete one byte or two bytes of data must be clocked into the device before the CS pin is deasserted, and the CS
pin must be deasserted on even byte boundaries (multiples of eight bits); otherwise, the device will abort the operation,
the state of the Status Register bits will not change, memory protection status will not change, and the WEL bit in the
Status Register will be reset back to the logical “0” state
2 6
AT25SF081
DS-25SF081–045I–8/2017
Table 10-4. Write Status Register Format.
Figure 10-3. Write Status Register
10.3 Write Enable for Volatile Status Register (50h)
The non-volatile Status Register bits described in Table 10-1 and Table 10-2 can also be written to as volatile bits. During
power up reset, the non-volatile Status Register bits are copied to a volatile version of the Status Register that is used
during device operation. This gives more flexibility to change the system configuration and memory protection schemes
quickly without waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register non-
volatile bits.
To write the volatile version of the Status Register bits, the Write Enable for Volatile Status Register (50h) instruction
must be issued prior to each Write Status Registers (01h) instruction. Write Enable for Volatile Status Register instruction
will not set the Write Enable Latch bit. It is only valid for the next following Write Status Registers instruction, to change
the volatile Status Register bit values.
Figure 10-4. Write Enable for Volatile Status Register
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SRPO SEC TB BP2 BP1 BP0 WEL WIP
SI
SCK
SO
CS
MSB
2310
00000001
67541011981917 1816
Opcode
DDDD
Status Register In - Byte 1
MSB
2321 222014 151312
DDDDDDDD
Status Register In - Byte 2
DDDD
High-Impedance
Table 10-5. Write Status Register Byte 2
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
reserved CMP LB3 LB2 LB1 reserved QE SRP1
6&.
&6
6,
62
MSB
2310
6754
OPCODE
HIGH-IMPEDANCE
2 7
AT25SF081
DS-25SF081–045I–8/2017
11. Other Commands and Functions
The AT25SF081 supports three different commands to access device identification that indicates the manufacturer,
device type, and memory density. The returned data bytes provide information as shown in Table 11-1.
11.1 Read Manufacturer and Device ID (9Fh)
Identification information can be read from the device to enable systems to electronically query and identify the device
while it is in system.
Since not all Flash devices are capable of operating at very high clock frequencies, applications should be designed to
read the identification information from the devices at a reasonably low clock frequency to ensure all devices used in the
application can be identified properly. Once the identification process is complete, the application can increase the clock
frequency to accommodate specific Flash devices that are capable of operating at the higher clock frequencies.
To read the identification information, the CS pin must first be asserted and the opcode of 9Fh must be clocked into the
device. After the opcode has been clocked in, the device will begin outputting the identification data on the SO pin during
the subsequent clock cycles. The first byte that will be output will be the Manufacturer ID followed by two bytes of Device
ID information. Deasserting the CS pin will terminate the Manufacturer and Device ID read operation and put the SO pin
into a high-impedance state. The CS pin can be deasserted at any time and does not require that a full byte of data be
read.
Table 11-2. Manufacturer and Device ID Information
Table 11-1. Manufacturer and Device ID Information
Instruction Opcode
Dummy
Bytes
Manufacturer
ID (Byte #1)
Device ID
(Byte #2)
Device ID
(Byte #3)
Read Manufacturer and Device ID 9Fh 01Fh 85h 01h
Read ID (Legacy Command) 90h 31Fh 13h
Resume from Deep Power-Down and
Read Device ID ABh 313h
Byte No. Data Type Value
1Manufacturer ID 1Fh
2Device ID (Part 1) 85h
3Device ID (Part 2) 01h
Table 11-3. Manufacturer and Device ID Details
Data Type Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Hex
Value Details
Manufacturer ID
JEDEC Assigned Code
1Fh JEDEC Code: 0001 1111 (1Fh for Adesto)
00011111
Device ID (Part 1)
Family Code Density Code
85h Family Code:100 (AT25SFxxx series)
Density Code: 00101 (8-Mbit)
10000101
Device ID (Part 2)
Sub Code Product Version Code
01h Sub Code: 000 (Standard series)
Product Version: 00001
00000001
2 8
AT25SF081
DS-25SF081–045I–8/2017
Figure 11-1. Read Manufacturer and Device ID
11.2 Read ID (Legacy Command) (90h)
Identification information can be read from the device to enable systems to electronically query and identify the device
while it is in system. The preferred method for doing so is the JEDEC standard “Read Manufacturer and Device ID (9Fh)”
method described in Section 11.1 on page 27; however, the legacy Read ID command is supported on the AT25SF081
to enable backwards compatibility to previous generation devices.
To read the identification information, the CS pin must first be asserted and the opcode of 90h must be clocked into the
device, followed by three dummy bytes. After the opcode has been clocked in followed by three dummy bytes, the device
will begin outputting the identification data on the SO pin during the subsequent clock cycles. The first byte that will be
output will be the Manufacturer ID of 1Fh followed by a single byte of data representing a device code of 13h. After the
device code is output, the sequence of bytes will repeat.
Deasserting the CS pin will terminate the Read ID operation and put the SO pin into a high-impedance state. The CS pin
can be deasserted at any time and does not require that a full byte of data read.
Figure 11-2. Read ID (Legacy Command)
11.3 Deep Power-Down (B9h)
During normal operation, the device will be placed in the standby mode to consume less power as long as the CS pin
remains deasserted and no internal operation is in progress. The Deep Power-Down command offers the ability to place
the device into an even lower power consumption state called the Deep Power-Down mode.
SCK
CS
SI
SO
60
9Fh
87
OPCODE
1Fh 85h 01h
MANUFACTURER ID DEVICE ID
BYTE1
DEVICE ID
BYTE2
HIGH-IMPEDANCE
14 1615 22 2423 30 3231
Note: Each transition shown for SI and SO represents one byte (8 bits)
6&.
&6
6,
62
MSB
2310
100
6754
OPCODE
HIGH-IMPEDANCE
31 323029 38 3937
35 363433
XX XXX
'800<%<7(6
MSB
DDDDDDDD
'(9,&(,'
2 9
AT25SF081
DS-25SF081–045I–8/2017
When the device is in the Deep Power-Down mode, all commands including the Read Status Register command will be
ignored with the exception of the Resume from Deep Power-Down command. Since all commands will be ignored, the
mode can be used as an extra protection mechanism against program and erase operations.
Entering the Deep Power-Down mode is accomplished by simply asserting the CS pin, clocking in the opcode of B9h,
and then deasserting the CS pin. Any additional data clocked into the device after the opcode will be ignored. When the
CS pin is deasserted, the device will enter the Deep Power-Down mode within the maximum time of tEDPD.
The complete opcode must be clocked in before the CS pin is deasserted, and the CS pin must be deasserted on an byte
boundary (multiples of eight bits); otherwise, the device will abort the operation and return to the standby mode once the
CS pin is deasserted. In addition, the device will default to the standby mode after a power-cycle.
The Deep Power-Down command will be ignored if an internally self-timed operation such as a program or erase cycle is
in progress. The Deep Power-Down command must be reissued after the internally self-timed operation has been
completed in order for the device to enter the Deep Power-Down mode.
Figure 11-3. Deep Power-Down
11.4 Resume from Deep Power-Down (ABh)
In order to exit the Deep Power-Down mode and resume normal device operation, the Resume from Deep Power-Down
command must be issued. The Resume from Deep Power-Down command is the only command that the device will
recognize while in the Deep Power-Down mode.
To resume from the Deep Power-Down mode, the CS pin must first be asserted and the opcode of ABh must be clocked
into the device. Any additional data clocked into the device after the opcode will be ignored. When the CS pin is
deasserted, the device will exit the Deep Power-Down mode within the maximum time of tRDPD and return to the standby
mode. After the device has returned to the standby mode, normal command operations such as Read Array can be
resumed.
If the complete opcode is not clocked in before the CS pin is deasserted, or if the CS pin is not deasserted on an byte
boundary (multiples of eight bits), then the device will abort the operation and return to the Deep Power-Down mode.
6&.
&6
6,
62
06%
,
&&
23&2'(
+,*+,03('$1&(
6WDQGE\0RGH&XUUHQW
$FWLYH&XUUHQW
'HHS3RZHU'RZQ0RGH&XUUHQW
W
('3'
3 0
AT25SF081
DS-25SF081–045I–8/2017
Figure 11-4. Resume from Deep Power-Down
11.4.1 Resume from Deep Power-Down and Read Device ID (ABh)
The Resume from Deep Power-Down command can also be used to read the Device ID.
When used to release the device from the Power-Down state and obtain the Device ID, the CS pin must first be asserted
and opcode of ABh must be clocked into the device, followed by 3 dummy bytes. The Device ID bits are then shifted out
on the falling edge of SCLK with most significant bit (MSB) first as shown in Figure 11-4. This command only outputs a
single byte Device ID. The Device ID value for the AT25SF081 is listed in Table 11-1.
After the last bit (bit 0) of the Device ID has been clocked out, the sequence will repeat itself starting again with bit 7 as
long as the CS pin remains asserted and the SCK pin is being pulsed. After CS is deasserted it must remain high for a
time duration of tRDPO before new commands can be received.
The same instruction may be used to read device ID when not in power down. In that case, /CS does not have to remain
high remain after it is deasserted.
Figure 11-5. Resume from Deep Power-Down and Read Device ID
6&.
&6
6,
62
MSB
,
&&
2310
10101011
6754
OPCODE
HIGH-IMPEDANCE
Deep Power-Down Mode Current
Active Current
Standby Mode Current
t
RDPD
6&.
&6
6,
62
MSB
,&&
2310
10101011
6754
OPCODE
HIGH-IMPEDANCE
'HHS3RZHU'RZQ0RGH&XUUHQW
Active Current
31 323029 38 3937
35 363433
XX XXX
'800<%<7(6 W5'32
MSB
DDDDDDDD
'(9,&(,'
6WDQGE\0RGH&XUUHQW
3 1
AT25SF081
DS-25SF081–045I–8/2017
11.5 Hold Function
The HOLD pin is used to pause the serial communication with the device without having to stop or reset the clock
sequence. The Hold mode, however, does not have an affect on any internally self-timed operations such as a program
or erase cycle. Therefore, if an erase cycle is in progress, asserting the HOLD pin will not pause the operation, and the
erase cycle will continue until it is finished.
If the QE bit value in the Status Register has been set to logical “1”, then the HOLD pin does not function as a control pin.
The HOLD pin will function as an output for Quad-Output Read and input/output for Quad-I/O Read.
The Hold mode can only be entered while the CS pin is asserted. The Hold mode is activated simply by asserting the
HOLD pin during the SCK low pulse. If the HOLD pin is asserted during the SCK high pulse, then the Hold mode won’t be
started until the beginning of the next SCK low pulse. The device will remain in the Hold mode as long as the HOLD pin
and CS pin are asserted.
While in the Hold mode, the SO pin will be in a high-impedance state. In addition, both the SI pin and the SCK pin will be
ignored. The WP pin, however, can still be asserted or deasserted while in the Hold mode.
To end the Hold mode and resume serial communication, the HOLD pin must be deasserted during the SCK low pulse. If
the HOLD pin is deasserted during the SCK high pulse, then the Hold mode won’t end until the beginning of the next SCK
low pulse.
If the CS pin is deasserted while the HOLD pin is still asserted, then any operation that may have been started will be
aborted, and the device will reset the WEL bit in the Status Register back to the logical “0” state.
Figure 11-6. Hold Mode
SCK
CS
HOLD
Hold HoldHold
3 2
AT25SF081
DS-25SF081–045I–8/2017
12. Electrical Specifications
12.3 DC Characteristics
12.1 Absolute Maximum Ratings*
Temperature under Bias. . . . . . . . . . . . . -55°C to +125°C*Notice: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional
operation of the device at these or any other
conditions beyond those indicated in the operational
sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended
periods may affect device reliability.
Storage Temperature . . . . . . . . . . . . . . . -65°C to +150°C
All Input Voltages (including NC Pins)
with Respect to Ground . . . . . . . . . . . . . . -0.6V to +4.1V
All Output Voltages
with Respect to Ground . . . . . . . . . . -0.6V to VCC + 0.5V
12.2 DC and AC Operating Range
AT25SF081
Operating Temperature (Case) Industrial -40°C to 85°C
VCC Power Supply 2.3V to 3.6V
Symbol Parameter Condition
2.3V to 3.6V
UnitsMin Typ Max
IDPD Deep Power-Down Current CS, HOLD, WP = VIH
All inputs at CMOS levels 2 5 µA
ISB Standby Current CS, HOLD, WP = VIH
All inputs at CMOS levels 13 25 µA
ICC1 (1) Active Current, Read (03h,
0Bh) Operation
f = 20MHz; IOUT = 0mA 3 6 mA
f = 50MHz; IOUT = 0mA 4 7 mA
f = 85MHz; IOUT = 0mA 5 8 mA
ICC2(1) Active Current,(3Bh, BBh
Read Operation (Dual)
f = 50MHz; IOUT = 0mA 5 8 mA
f = 85MHz; IOUT = 0mA 610 mA
ICC3(1) Active Current,(6Bh, EBh
Read Operation (Quad)
f = 50MHz; IOUT = 0mA 610 mA
f = 85MHz; IOUT = 0mA 812 mA
ICC4(1) Active Current,
Program Operation CS = VCC 10 16 mA
ICC5(1) Active Current,
Erase Operation CS = VCC 10 16 mA
3 3
AT25SF081
DS-25SF081–045I–8/2017
ILI Input Load Current All inputs at CMOS levels 1 1 µA
ILO Output Leakage Current All inputs at CMOS levels 1 1 µA
VIL Input Low Voltage VCC x 0.3 V
VIH Input High Voltage VCC x 0.7 V
VOL Output Low Voltage IOL = 1.6mA; VCC = 2.3V 0.4 V
VOH Output High Voltage IOH = -100µA VCC - 0.2V V
1. Typical values measured at 3.0V @ 25°C for the 2.3V to 3.6V range
12.4 AC Characteristics - Maximum Clock Frequencies
Symbol Parameter
2.3V to 3.6V 2.5V to 3.6V
UnitsMin Typ Max Min Typ Max
fCLK Maximum Clock Frequency for All Operations 104 104 MHz
fRDLF Maximum Clock Frequency for 03h Opcode 50 50 MHz
fRDHF Maximum Clock Frequency for 0Bh Opcode 70 70 MHz
fRDDO Maximum Clock Frequency for 3B, BBh
Opcode 50 70 MHz
fRDQO Maximum Clock Frequency for 6B, EBh
Opcode 33 70 MHz
12.5 AC Characteristics - All Other Parameters
Symbol Parameter
2.3V to 3.6V 2.5V to 3.6V
Units
Min Typ Max Min Typ Max
tCLKH Clock High Time 5 5 ns
tCLKL Clock Low Time 5 5 ns
tCLKR(1) Clock Rise Time, Peak-to-Peak (Slew Rate) 0.1 0.1 V/ns
tCLKF(1) Clock Fall Time, Peak-to-Peak (Slew Rate) 0.1 0.1 V/ns
tCSH Chip Select High Time 10 10 ns
tCSLS Chip Select Low Setup Time (relative to Clock) 5 5 ns
tCSLH Chip Select Low Hold Time (relative to Clock) 5 5 ns
tCSHS Chip Select High Setup Time (relative to Clock) 5 5 ns
Symbol Parameter Condition
2.3V to 3.6V
UnitsMin Typ Max
3 4
AT25SF081
DS-25SF081–045I–8/2017
tCSHH Chip Select High Hold Time (relative to Clock) 5 5 ns
tDS Data In Setup Time 2 2 ns
tDH Data In Hold Time 2 2 ns
tDIS(1) Output Disable Time 8 7 ns
tV
Output Valid Time (03h, 0Bh) 8 7 ns
Output Valid Time (3Bh, BBh - Dual) 8 7
Output Valid Time (6Bh, EBh - Quad) 9 8
tOH Output Hold Time 0 0 ns
tHLS HOLD Low Setup Time (relative to Clock) 5 5 ns
tHLH HOLD Low Hold Time (relative to Clock) 5 5 ns
tHHS HOLD High Setup Time (relative to Clock) 5 5 ns
tHHH HOLD High Hold Time (relative to Clock) 5 5 ns
tHLQZ (1) HOLD Low to Output High-Z 6 6 ns
tHHQZ(1) HOLD High to Output High-Z 6 6 ns
tWPS(1) (2) Write Protect Setup Time 20 20 ns
tWPH(1)(2) Write Protect Hold Time 100 100 ns
tEDPD(1) Chip Select High to Deep Power-Down 1 1 µs
tRDPD(1) Chip Select High to Standby Mode 5 5 µs
tRDPO(1) Resume Deep Power-Down, CS High to ID 5 5 µs
1. Not 100% tested (value guaranteed by design and characterization).
2. Only applicable as a constraint for the Write Status Register command when BPL = 1.
12.6 Program and Erase Characteristics
Symbol Parameter
2.3 to 3.6V 2.5V to 3.6V
Min Typ Max Min Typ Max Units
tPP (1) Page Program Time (256 Bytes) 0.7 50.7 5ms
tBP Byte Program Time 5 5 µs
tBLKE(1) Block Erase Time
4 Kbytes 60 300 60 300
ms32 Kbytes 300 1300 300 1300
64 K bytes 500 3000 500 3000
tCHPE(1) (2) Chip Erase Time 12 30 12 20 sec
12.5 AC Characteristics - All Other Parameters
Symbol Parameter
2.3V to 3.6V 2.5V to 3.6V
Units
Min Typ Max Min Typ Max
3 5
AT25SF081
DS-25SF081–045I–8/2017
tSRP(1) Security Register Program Time 2.5 2.5 ms
tSRP(1) Security Register Erase Time 15 15 ms
tWRSR(2) Write Status Register Time 15 15 ms
1. Maximum values indicate worst-case performance after 100,000 erase/program cycles.
2. Not 100% tested (value guaranteed by design and characterization).
12.7 Power-Up Conditions
2.3V to 3.6V 2.5V to 3.6V
Symbol Parameter Min Max Min Max Units
tVCSL Minimum VCC to Chip Select Low Time 25 20 µs
tPUW Power-up Device Delay Before Program or Erase Allowed 20 10 ms
VPOR Power-on Reset Voltage 2.3 2.3 V
12.6 Program and Erase Characteristics
Symbol Parameter
2.3 to 3.6V 2.5V to 3.6V
Min Typ Max Min Typ Max Units
3 6
AT25SF081
DS-25SF081–045I–8/2017
12.8 Input Test Waveforms and Measurement Levels
12.9 Output Test Load
13. AC Waveforms
Figure 13-1. Serial Input Timing
Figure 13-2. Serial Output Timing
AC
DRIVING
LEVELS
AC
MEASUREMENT
LEVEL
0.1V
CC
V
CC
/2
0.9V
CC
t
R
, t
F
< 2 ns (10% to 90%)
Device
Under
Test
30pF
&6
6,
6&.
62
06%
+,*+,03('$1&(
06%/6%
W&6/6
W&/.+ W&/./ W&6+6
W&6++
W'6 W'+
W&6/+
W&6+
&6
6,
6&.
62
W9
W&/.+ W&/./ W',6
W9
W2+
3 7
AT25SF081
DS-25SF081–045I–8/2017
Figure 13-3. WP Timing for Write Status Register Command When BPL = 1
Figure 13-4. HOLD Timing – Serial Input
Figure 13-5. HOLD Timing – Serial Output
WP
SI
SCK
SO
000
HIGH-IMPEDANCE
MSBX
t
WPS
t
WPH
CS
LSB OF
WRITE STATUS REGISTER
DATA BYTE
MSB OF
WRITE STATUS REGISTER
OPCODE
MSB OF
NEXT OPCODE
CS
SI
SCK
SO
tHHH tHLS
tHLH tHHS
HOLD
HIGH-IMPEDANCE
CS
SI
SCK
SO
tHHH tHLS
tHLQZ
tHLH tHHS
HOLD
tHHQX
3 8
AT25SF081
DS-25SF081–045I–8/2017
14. Ordering Information
14.1 Ordering Code Detail
AT25S 08 SS DHB1– –F
Designator
Product Family
Device Density
08 = 8-megabit
Interface
1 = Serial
Package Option
M = 8-pad, 5 x 6 x 0.6 mm UDFN
MA = 8-pad, 2 x 3 x 0.6 mm UDFN
SS = 8-lead, 0.150" wide SOIC
S = 8-lead, 0.208" wide SOIC
XM = 8-lead TSSOP
DWF = Die in Wafer Form
Device Grade
H = Green, NiPdAu lead finish,
Industrial temperature range
(–40°C to +85°C)
Shipping Carrier Option
B = Bulk (tubes)
T = Tape and reel
Operating Voltage
D = 2.5V to 3.6V
F = 2.3V to 3.6V
Ordering Code (1) Package Operating Voltage
Max. Freq.
(MHz) Operation Range
AT25SF081-SSHD-B
8S1
2.5V to 3.6V 70MHz Industrial
(-40°C to +85°C)
AT25SF081-SSHD-T
AT25SF081-SHD-B
8S2
AT25SF081-SHD-T
AT25SF081-MHD-T 8MA1
AT25SF081-MAHD-T 8MA3
AT25SF081-XMHD-T 8X
AT25SF081-DWF (2) DWF
AT25SF081-SSHF-B
8S1
2.3V to 3.6V 70MHz Industrial
(-40°C to +85°C)
AT25SF081-SSHF-T
AT25SF081-SHF-B
8S2
AT25SF081-SHF-T
AT25SF081-MHF-T 8MA1
AT25SF081-MAHF-T 8MA3
1. The shipping carrier option code is not marked on the devices.
3 9
AT25SF081
DS-25SF081–045I–8/2017
2. Contact Adesto for mechanical drawing or Die Sales information.
Package Type
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline Package (JEDEC SOIC)
8S2 8-lead, 0.208" Wide, Plastic Gull Wing Small Outline Package (EIAJ SOIC)
8MA1 8-pad (5 x 6 x 0.6mm body), Thermally Enhanced Plastic Ultra Thin Dual Flat No-lead (UDFN)
8MA3 8-pad (2 x 3 x 0.6mm body), Thermally Enhanced Plastic Ultra Thin Dual Flat No-lead (UDFN)
8X 8-lead (4 x 4 mm body), Thin Shrink Small Outline Package (TSSOP)
DWF Die in Wafer Form
4 0
AT25SF081
DS-25SF081–045I–8/2017
15. Packaging Information
15.1 8S1 – 8-lead, .150” JEDEC SOIC
DRAWING NO. REV. TITLE GPC
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A1 0.10 – 0.25
A 1.35 – 1.75
b 0.31 – 0.51
C 0.17 – 0.25
D 4.80 – 5.05
E1 3.81 – 3.99
E 5.79 – 6.20
e 1.27 BSC
L 0.40 – 1.27
ØØ 0° – 8°
ØØ
EE
11
NN
TOP VIEWTOP VIEW
CC
E1E1
END VIEW
AA
bb
LL
A1A1
ee
DD
SIDE VIEWSIDE VIEW
Package Drawing Contact:
contact@adestotech.com
8S1 G
8/20/14
Notes: This drawing is for general information only.
Refer to JEDEC Drawing MS-012, Variation AA
for proper dimensions, tolerances, datums, etc.
8S1, 8-lead (0.150” Wide Body), Plastic Gull
Wing Small Outline (JEDEC SOIC) SWB
4 1
AT25SF081
DS-25SF081–045I–8/2017
15.2 8S2 – 8-lead, .208” EIAJ SOIC
TITLE DRAWING NO. GPC REV.
Package Drawing Contact:
contact@adestotech.com
®
8S2STN F
8S2, 8-lead, 0.208” Body, Plastic Small
Outline Package (EIAJ)
4/15/08
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
2. Mismatch of the upper and lower dies and resin burrs aren't included.
3. Determines the true geometric position.
4. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm.
A 1.70 2.16
A1 0.05 0.25
b 0.35 0.48 4
C 0.15 0.35 4
D 5.13 5.35
E1 5.18 5.40 2
E 7.70 8.26
L 0.51 0.85
θ 0° 8°
e 1.27 BSC 3
θθ
11
NN
EE
TOP VIEWTOP VIEW
CC
E1E1
END VIEWEND VIEW
AA
bb
LL
A1A1
ee
DD
SIDE VIEWSIDE VIEW
4 2
AT25SF081
DS-25SF081–045I–8/2017
15.3 8MA1 – UDFN
Note: Subject to change.
TITLE DRAWING NO.GPC REV.
Package Drawing Contact:
contact@adestotech.com
®
8MA1YFG GT
8MA1, 8-pad (5 x 6 x 0.6 mm Body), Thermally
Enhanced Plastic Ultra Thin Dual Flat No Lead
Package (UDFN)
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A 0.50 0.55 0.60
A1 0.00 0.02 0.05
b 0.35 0.40 0.48
C 0.150 REF
D 4.90 5.00 5.10
D2 3.90 4.00 4.05
E 5.90 6.00 6.10
E2 3.30 3.40 3.45
e 1.27 BSC
L 0.55 0.60 0.65
y 0.00 – 0.08
K 0.20 – –
1. All dimensions are in mm. Angles in degrees.
2. Bilateral coplanarity zone applies to the exposed heat
sink slug as well as the terminals.
8/26/14
Pin 1 ID
TOP VIEW
E
D
A1
A
SIDE VIEW
y
C
BOTTOM VIEW
E2
D2
L
b
e
1
2
3
4
8
7
6
5
K
Pin #1
Chamfer
(C 0.35
x 45°)
4 3
AT25SF081
DS-25SF081–045I–8/2017
15.4 8MA3 – UDFN
Note: Subject to change.
TITLE DRAWING NO.GPC REV.
Package Drawing Contact:
contact@adestotech.com
®
8MA3YCQ GT
8MA3, 8-pad, 2 x 3 x 0.6 mm Body, 0.5 mm Pitch,
1.6 x 0.2 mm Exposed Pad, Saw Singulated
Thermally Enhanced Plastic Ultra Thin Dual
Flat No Lead Package (UDFN/USON)
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A 0.50 0.55 0.60
A1 0.00 0.02 0.05
A3 0.150 REF
b 0.20 0.25 0.30
D 2.00 BSC
D2 1.55 1.60 1.65
E 3.00 BSC
E2 0.15 0.20 0.25
e 0.50 BSC
L 0.40 0.45 0.50
eee – – 0.08
8/26/14
Notes: 1. All dimensions are in mm. Angles in degrees.
2. Bilateral coplanarity zone applies to the exposed heat
sink slug as well as the terminals.
D
14
PIN 1 ID
E
5
23
678
eee
4 4
AT25SF081
DS-25SF081–045I–8/2017
15.5 8X – TSSOP
DRAWING NO. REV. TITLE GPC
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A - - 1.20
A1 0.05 - 0.15
A2 0.80 1.00 1.05
D 2.90 3.00 3.10 2, 5
E 6.40 BSC
E1 4.30 4.40 4.50 3, 5
b 0.19 – 0.30 4
e 0.65 BSC
L 0.45 0.60 0.75
L1 1.00 REF
C 0.09 - 0.20
Side View
End View
Top View
A2
A
L
L1
D
1
E1
N
b
Pin 1 indicator
this corner
E
e
Notes: 1. This drawing is for general information only. Refer to JEDEC
Drawing MO-153, Variation AA, for proper dimensions,
tolerances, datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate
burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15mm (0.006in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions.
Inter-lead Flash and protrusions shall not exceed 0.25mm
(0.010in) per side.
4. Dimension b does not include Dambar protrusion. Allowable
Dambar protrusion shall be 0.08mm total in excess of the b
dimension at maximum material condition. Dambar cannot be
located on the lower radius of the foot. Minimum space between
protrusion and adjacent lead is 0.07mm.
5. Dimension D and E1 to be determined at Datum Plane H.
H
8X E
12/8/11
8X, 8-lead 4.4mm Body, Plastic Thin
Shrink Small Outline Package (TSSOP) TNR
C
A1
Package Drawing Contact:
contact@adestotech.com
®
4 5
AT25SF081
DS-25SF081–045I–8/2017
16. Revision History
Revision Level – Release Date History
A – April 2014 Initial release
B – May 2014 Removed tray shipping carrier option from DFN packages (-Y). Removed
Program/Erase Suspend and Resume features.
C – July 2014
Removed quad input references on pin descriptions. Corrected ignored address
bits in Section 5. Corrected Opcode reference for Read Array; OBh uses fRDHF
.
Corrected various address range references in Table 8-2. Updated doc control
number. Removed TSSOP bulk shipping option. Removed Preliminary status.
D – August 2014 Updated Chip Erase time specifications. Corrected 8S1, 8MA1 and 8MA3
package outline drawing.
E – January 2015 Removed DFN (not in production) footnote.
F – August 2015 Removed mention of Suspend/Resume in WP pin description.Added Die in Wafer
Form ordering option.Removed footnote on DFN and TSSOP packages.
G – April 2016 Updated 90h opcode description (added 3 dummy bytes).
H – May 2016 Added 2.3V selection.Updated AC and Program and Erase Characteristics.
Corrected maximum frequency for ordering table.
I – August 2017 Updated corporate address.
Corporate Office
California | USA
Adesto Headquarters
3600 Peterson Way
Santa Clara, CA 95054
Phone: (+1) 408.400.0578
Email: contact@adestotech.com
© 2017 Adesto Technologies. All rights reserved. / Rev.: DS-25SF081–045I–8/2017
Disclaimer: Adesto Technologies Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Adesto's Terms
and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications
detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Adesto are granted by the
Company in connection with the sale of Adesto products, expressly or by implication. Adesto's products are not authorized for use as critical components in life support devices or systems.
Adesto®, the Adesto logo, CBRAM®, and DataFlash® are registered trademarks or trademarks of Adesto Technologies. All other marks are the property of their respective
owners.
