109101907 - Agere Systems, Inc.

Advisory

July 2002

TSI-8 Time-Slot Interchanger

Introduction

This document describes technical issues that are

known to exist with the device and/or the

documentation of the device.

Issues

TXD Buffer Strength

The TXD[31:00] output buffers are capable of

excessive output drive, resulting in excessive

overshoot and undershoot.

Workaround

Series source and termination resistors may be

required for TXD[31:00] to achieve acceptable signal

integrity.

Corrective Action

This will be corrected in a future respin.

TXD Precharge Resistors

TXD[23:00] are not properly equipped with precharge

resistors.

Workaround

External precharge resistors for TXD[23:00] must be

provided if hot insertion is required by the application.

Corrective Action

This will be corrected in a future respin.

July 2002

AY02-027SWCH (Must accompany DS02-121SWCH, DS02-122SWCH, and DS02-123SWCH)

Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.

Agere, Agere Systems, and the Agere logo are trademarks of Agere Systems Inc.

For additional information, contact your Agere Systems Account Manager or the following:

INTERNET: http://www.agere.com

E-MAIL: docmaster@agere.com

N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286

1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106)

ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon

Tel. (852) 3129-2000, FAX (852) 3129-2020

CHINA: (86) 21-5047-1212 (Shanghai), (86) 755-25881122 (Shenzhen)

JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei)

EUROPE: Tel. (44) 7000 624624, FAX (44) 1344 488 045

Advance Information

May 2002

TSI-8 Time-Slot Interchanger

Product Description

Introduction

This document is a high-level description for the

TSI-8 time- slot inte r cha nge r devic e. The featu re s

and functions of the device are listed and explained

at a level intended to meet the needs of the system

design and component selection processes. Any

standards governing the operation of the device are

referenced, and the level of compliance is stated as

appropriate. Broad definitions of its intended

applications are given.

Relat ed Docume nts

More information on the TSI-8 is contained in the fol-

lowing documents:

■The hardware design guide contains all information

relevant to the use of the device in a board design.

Pin descriptions, dc electrical characteristics, tim-

ing diagrams, ac timing parameters, packaging,

and operating conditions are included.

■The register description defines the address map

for the TSI-8, and describes the purpose and oper-

ation of each register bit, its dependencies and ini-

tial state.

■The systems design guide describes how to design

software and hardware to support the device in

various applications. The initialization procedure

as well as some fundamental test setups for loop-

backs and pattern generation are also described.

Features

■8,192 input channels x 8,192 output channels non-

blocking DS0 time-slot interchange fabric.

■32 full-dup le x, seri al tim e -div i si on mult ip lex er

(TDM) concentration highway interfaces.

■Compatible with GCI, SLD interfaces, and H.110.

■Data rate selection of 2.048 Mbits/s,

4.096 Mbits/s, 8.192 Mbits/s, or 16.384 Mbits/s per

highway.

■Bit and byte offset to 1/4 bit resolution per highway.

■Frame integrity mode to ensure intact transfer of

wideband data (N x DS0, ISDN H-channels).

■Low-latency mode for minimum delay on voice

channels.

■16-bit synchronous microprocessor interface for

access to connection data and device registers.

■16 programmable time-slot translation tables allow

for real-time digital transform of TDM data. These

are selected per connection to provide fixed gain/

loss, A-law to µ-law conversion, etc.

■IEEE® 1149.1 boundary-scan test port (JTAG).

■Pattern generation and checking for on-line system

testing (pseudorandom bit sequence (PRBS),

quasirandom signal sequence (QRSS), or user-

defined byte).

■Low-power 1.5 V core power supply with 3.3 V

digital I/O compatibility.

■240-pin ball grid array (PBGA) package, 19 mm

square with 1.0 mm ball pitch.

■–40 °C to +85 °C industrial temperature range.

22 Agere Systems Inc.

Advance Information

May 2002

Product Description

TSI-8 Time-Slot Interchanger

Applications

The TSI-8 is suited to a wide variety of small-to-

medium si zed DS0 TDM switch applications . It has

sufficient capacity to support up to an OC-12 link

containing 64 kbits/s channels; it can provide useful

grooming, first-stage switching, loopback, and test

access on high-density transmission port cards (e.g.,

OC-12, OC-3, and DS3). For lower-density systems,

with several T1 ports for example, it can support all the

DS0 switching needs for the entire system. Typical

applications include:

■Central office TDM switch.

■Integrated access devices.

■Next-generation digital loop carriers.

■Digital cross connects.

■Remote access concentrators.

■Remote access servers.

■Voice/IP gateways.

■Multiservi ce access plat forms.

■Wireless base stations.

■Terminal multiplexer.

Description

The TSI-8 time-slot interchanger (TSI) is a time/space

switch with DS0 granularity . The fabric is a nonblocking

structure with 8,192 input channels that may be

interchanged to any of 8,192 output channels. The

input and output channels are arranged on time-

division multiplexed serial highways. The timing and

structu r e of these hig hway s compl ie s with Ager e

Systems Inc. concentration highway interface (CHI)

standard. Each CHI is independently programmed, and

the output CHIs support multidriver busing. The CHIs

have a programmable data rate (up to 16.384 Mbits/s)

and frame offset. Transm it and receive configuratio ns

are also independently programmable. The TSI-8 is

configured via a 16-bit synchronous microprocessor

interface, which is used to control the connection data

and to access the device’s registers.

The TSI-8 supports a number of additional time-slot

test and code substitution functions in addition to its pri-

mar y switchi n g ro le . Th es e o pt i on s ar e pro g ra mm ed i n

a similar fashion to normal connections, by setting spe-

cial bits in the connection control store. A frame integ-

rity mode ensures constant delay for bonded DS0

channels in applications that switch wideband data

(i.e., N x DS0 or ISDN H-channels). Low latency mode

ensures minimal delay for voice circuits.

Figure 1 represents a high-level block diagram of the

TSI-8.

Agere Systems Inc. 3

Advance Information

May 2002 Product Description

TSI-8 Time-Slot Interchanger

Description (c on tin ued)

Block Diagram

Figure 1. TSI-8 Block Diagram

TEST ACCESS

PORT

READ ADDRESS

COUNTER

CONNECTION

STORE

WRITE ADDRESS

COUNTER

DATA

STORE

MICROPROCESSOR

INTERFACE

TRANSMIT

CHI

TEST PATTERN

GENERATOR

TEST PATTERN

MONITOR

SWITCH

FABRIC

CLOCK

GENERATOR

RECEIVE

CHI

TRANSLATION

TABLE LOOKUP

32 32

44 Agere Systems Inc.

Advance Information

May 2002

Product Description

TSI-8 Time-Slot Interchanger

Switch Fabric

The switch fabric performs the nonblocking switching

function. It can switch any of the 8,192 possible incom-

ing time slots to any of the 8,192 possible outgoing

time slots. It uses the classic configuration of two mem-

ories, one co ntaini ng the traffic data and the seco nd

containing the switching configuration. The switch fab-

ric performs this switching function without regard to

the physical link from which the time slot was taken;

hence, the TSI-8 TSI is a time-space switch. T ime slots

are rearranged in order within a frame (time) and

among physi c al por ts (space).

Time-slot data from the input TDM highways is con-

verted to a common-rate parallel format by the CHI

blocks. These data are written into the data store

sequentially. The write address for the address for the

data store is generated from the system clock (CHI-

CLK) and frame synchronization (FSYNC) pulse; the

clock is multiplied up to 164 MHz by a PLL in the clock

generator block so that all 8,192 input time slots can be

written into the data store during a 125 µs frame. The

entire switching operation from the input to output CHIs

is synchronous to the CHICLK and frame locked to

FSYNC.

Connections are established by programming the con-

nection store. Each time slot on the output highways

has an associated address in the connection store;

each of those locations may be programmed with the

input highway and time slot to which a connection is

required. The connection store is also used to program

all other per-time-slot options, such as frame integrity,

translation table look-up, and test pattern insertion.

The switch fabric has the ability to select one of the fol-

lowing two latency modes for each connection:

■Frame integrity. Frame integrity mode ensures

proper operation with wideband data by getting all of

the time slots in an output frame from the same input

frame.

■Low latency. Low latency mode minimizes delay for

voice applications.

The time-slot interchanger core is a memory-based

implementation consisting of a data store and a

connection store. The data store provides temporary

storage for each of the 8,192 input TDM time slots.

Received serial data is converted to parallel format,

stored sequentially in the data store, and read to output

time slots under control of data in the connection store.

The connection store contains setup information for

each of the 8,192 output time slots.

Expansion

To interconnect more DS0 traffic than the 8,192 input

and 8,192 output time slots, which a single TSI-8

allows, a geometric expansion of TSIs will be needed.

The best alternative would be to use the TSI-16 or

STSI-144 device, which allows a linear growth in 16k

increments by adding a single device at each growth

stage up to a maximum of 144k time slots with as few

as nine devices. See the TSI-16 and/or STSI-144 doc-

umentation for more details.

Microprocessor Interface

The TSI-8 has a versatile 16-bit microprocessor

interface that provides access to its registers and

connection store. It is designed to connect directly to

the address and data buses of a synchronous general-

purpose microprocessor and is compatible with

Motorola ®, Intel ®, and other nonmultiplexed bus

structures. The required microprocessor signals are as

follows:

■16-bit data bus (DATA[15:00]).

■16-bit address bus (ADDR[15:00]).

■Four control lines (chip select (CS), address strobe

(AS), read/write (R/W), and data transfer

acknowledge (DT)).

■A proces sor clock (MPUCLK).

■Interrupt output (INT).

The connection store and device configuration

registers are directly addressed.

The TSI-8 generates interrupts on certain error condi-

tions—illegal address, CHI timings errors, for example.

These may all be masked individually.

Concentration Highway Interface (CHI)

The TSI-8 transmits and receives time-slot data via

32 transmit CHIs and 32 receive CHIs, which are

single-ended serial TDM links. A programmable clock

signal and a glob al fra me sy nc hroni z ati on puls e si gna l

provide the required timing references to the CHI

interface. The TSI-8 supports CHIs with unaligned

framing; that is, each CHI's offset from the frame

synchronization signal is independently programmable.

Although the frame offsets can be different, they must

be locked to a common frame reference. The transmit

CHIs may be placed into the high-impedance (Hi-Z)

state to allow busing of multiple drivers. Each CHI may

be independently configured for direct connection to a

variety of serial TDM interfaces operating at a

Agere Systems Inc. 5

Advance Information

May 2002 Product Description

TSI-8 Time-Slot Interchanger

Concentration Highway Interface (CHI)

(continued)

variety of data rates, including GCI, SLD, and H.110.

Each CHI supports data rates of 2.048 Mbits/s (32 time

slots), 4.096 Mbits/s, 8.192 Mbits/s, and 16.384 Mbits/s

(256 time slo ts).

The receive CHI block reformats the serial CHI input

data into a parallel format so that it can be written as

8-bit words into the data store. A 164 MHz clock is used

for those transfers. This clock is derived using an inter-

nal phase-locked loop.

The transmit CHIs are similar in number, format, and

flexibility to the receive CHIs. A parallel-serial conver-

sion process is performed, and the time-slot data are

slowed down from the 164 MHz internal clock rate to

the required CHI output rate (2.048 Mbits/s,

4.096 Mbits/s, 8.192 Mbits/s, or 16.384 Mbits/s). The

output CHI block also makes any time slot or bit offset

adjustments that have been programmed.

The receive CHIs are single-ended serial TDM

interfaces. The transmit CHIs can be configured as

bidirectional. In this case, the CHI receive (Rx) input is

disabled and the input CHI data comes from the

bidirectional TXD signal. The transmit drivers can be

set to a high-impedance state, and the device output

pin can be driven with input CHI data. This output

enable can be configured independently for each time

slot to support multiplexed TDM bus architectures such

as H.110. Thirty-two hot-swapable bidirectional TDM

ports can be configured for compatibility with H.110.

CHI Frame Offset Selection

TSI-8 supports unaligned (but synchronous) TDM data

streams. Each input CHI and each output CHI has a

programmable offset (see Table 1) ranging from 0 to

virtually a full frame. The TDM streams can be timed to

align with the connecting device rather than having to

be absolutely aligned with the TSI-8 frame synchroni-

zation inp ut.

Test Pattern Generator and Monitor

The test pattern generator (TPG) and test pattern mon-

itor (TPM) are a set of selectable test logic for support

of transmission facility testing and maintenance. This

block can supply and check any one of the test pat-

terns defined in ITU-T O.150, O.151, or O.152, as well

as user-defined patterns. Any combination of DS0s

can be concatenated as a single broadband stream to

test high-speed facilities. Additionally, the TPG/TPM

provides the ability to perform diagnostic tests at both

the system and device levels of operation.

System-level troubleshooting is facilitated with full

narrowband/wideband test pattern generation and

detection. Extensive device-level testing can quickly be

performed with specialized test pattern generation and

monitoring functions targeted at the CHI interface as

well as the switch fabric itself. An effective self-test can

be performed by configuring a test path and using the

TPG/TPM and the internal loopback capabilities of the

CHIs.

Test pattern generation and monitoring options are

configured using the connection store. Only one type

of test p attern can be transmitted at once, but it may be

concatenated on any number of channels. The test

pattern monitor may only check a single pattern on one

time slot or wideband channel.

Table 1. Fractional Bit Offset Resolution

CHI Data Rate CHICLK Receive Offse t Resolutio n Trans mit Offse t Resolut ion

2.048 Mbits/s 8.192 MHz 1/4 bit (122.1 ns) 1/4 bit (122.1 ns)

2.048 Mbits/s 16.384 MHz 1/4 bit (122.1 ns) 1/4 bit (122.1 ns)

4.096 Mbits/s 8.192 MHz 1/4 bit (61.0 ns) 1/4 bit (61.0 ns)

4.096 Mbits/s 16.384 MHz 1/4 bit (61.0 ns) 1/4 bit (61.0 ns)

8.192 Mbits/s 8.192 MHz 1/4 bit (30.5 ns) 1/2 bit (61.0 ns)

8.192 Mbits/s 16.384 MHz 1/4 bit (30.5 ns) 1/4 bit (30.5 ns)

16.384 Mbits/s 16.384 MHz 1/4 bit (15.25 ns) 1/2 bit (30.5 ns)

66 Agere Systems Inc.

Advance Information

May 2002

Product Description

TSI-8 Time-Slot Interchanger

Translation Table Look-Up Logic

The translation table look-up (TTL) logic is a set of 16

look-up tables that can optionally be inserted in the

TDM path at the output of the switch fabric. This allows

the end user to perform real-time digital transforms on

the outgoing TDM data. These look-up tables are user

programmable and are useful for various TDM related

transform functions such as µ-law to A-law conversion,

gain adjustment, or message conversion for static (i.e.,

robbed bit) signaling schemes. The various transforms

can be selected on a per-time-slot basis by program-

ming the connection store.

Delay Through the TSI-8

For each connec tion wri tte n to the connecti on sto re ,

the switch fabric is set to operate in low latency mode

or frame integrity mode. Low latency mode operates

with minimum delay of a DS0 byte from an input to out-

put time slot and is typically selected for voice applica-

tions. Frame integrity mode ensures intact switching of

wideband data so that all the bonded time slots in one

125 µs input frame are switched to the same 125 µs

output frame. Assuming the most favorable conditions,

the minimum switch time (first bit in to first bit out) is

two time-slot periods. The longest delay in low latency

mode is about one frame plus three time slots. The

longest delay in frame integrity mode is about three

frames plus three time slots.

Clocks

The TSI-8 has two clock domains: one used for TDM

data and the second used for the microprocessor

interface.

The input and output CHIs are in the TDM timing

domain. The CHICLK input, which may be 16.384 MHz

or 8.192 MHz, is the reference source for the TDM

timing. Internally, this clock is multiplied up to 164 MHz

for internal data transfer. An on-chip PLL is used for

this purpose. An 8 kHz frame synchronization pulse is

also required that must be synchronous with CHICLK.

This is used as a reference for all the time-slot

locations in the transmit and receive CHIs.

The second timing domain is used for the microproces-

sor interface. The MPUCLK input should be supplied

along with the microprocessor data, address, and con-

trol signals. Typically, this is available as an output on

most microprocessors, and is often referred to as the

peripheral clock.

Reset

The TSI-8 has a hardware reset input that is used to

initialize various internal logic functions. This may be

used during initialization and for device and board-level

testing. A similar reset is available as a register bit to

allow hardware reset under software control.

Note: Neither of these resets affects the contents of

the data store, or more importantly, the

connection store. However, the reset does put

the device into a benign state (outputs high

impedance or inactive).

Agere Systems Inc. 7

Advance Information

May 2002 Product Description

TSI-8 Time-Slot Interchanger

Ordering Information

Device Part Number Ball Count Package Comcode

TSI-8 TTSI008321BL-1 240 PBGAM1 109101907

IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc.

Motorola is a registered trademark of Motorola, Inc.

Intel is a registered trademark of Intel Corporation.

May 2002

DS02-121SWCH

Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application.

Agere, Agere Systems, and the Agere logo are trademarks of Agere Systems Inc.

For additional information, contact your Agere Systems Account Manager or the following:

INTERNET: http://www.agere.com

E-MAIL: docmaster@agere.com

N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286

1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-41 06)

ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gateway, Harbour City, Kowloon

Tel. (852) 3129-2000, FAX (852) 3129-2020

CHINA: (86) 21-5 04 7- 1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Sh enz h en)

JAPAN: (81) 3-5421-1600 (Tokyo ), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6778-8833, TAIWAN: (886) 2-2725-5858 (Taipei)

EUROPE: Tel. (44 ) 700 0 624 624, FAX (44) 1344 488 045