ICS580-01 Glitch-Free Clock Multiplexer Description Features The ICS580-01 is a clock multiplexer (mux) designed to switch between two clock sources with no glitches or short pulses. The operation of the mux is controlled by an input pin but the part can also be configured to switch automatically if one of the input clocks stops. The part also provides clock detection by reporting when an input clock has stopped. * * * * * * * * * For a clock mux with zero delay and smooth switching, see either the ICS581-01 or the ICS581-02. * 16-pin SOIC package Available in Pb (lead) free package No short pulses or glitches on output Operates from 2 to 220 MHz Low skew outputs Clock detect feature Ideal for systems with back-up or redundant clocks Selectable timeouts for clock detection Separate supply voltages allow power supply voltage translation Operates from 2.5 V to 5 V Block Diagram VDDC VDDI CLK1 INB 1 OE1 0 INA CLK2 OE2 SELB Transition Detector NO_INA OE3 Transition Detector NO_INB OE4 DIV Timer GND MDS 580-01 D 1 Revision 021605 Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com ICS580-01 Glitch-Free Clock Multiplexer Pin Assignment Timeout Selection SELB 1 16 OE1 DIV 2 15 VDDC VDDI 3 14 CLK1 INA 4 13 CLK2 INB 5 12 NO_INA GND 6 11 NO_INB OE4 7 10 GND OE3 8 9 OE2 DIV Nominal Timeout 0 600 ns 1 75 ns 16 pin (150 mil) SOIC Pin Descriptions Pin Number Pin Name Pin Type 1 SELB Input Mux select. Selects INB when high. Internal pull-up. 2 DIV Input Time out select. See table above. Internal pull-up. 3 VDDI Power Supply for input clocks only. Can be higher than VDDC. 4 INA Input Input Clock A. 5 INB Input Input Clock B. 6 GND Power Connect to ground. 7 OE4 Input Output enable. Tri-states NO_INB when low. Internal pull-up. 8 OE3 Input Output enable. Tri-states NO_INA when low. Internal pull-up. 9 OE2 Input Output enable. Tri-states CLK2 when low. Internal pull-up. 10 GND Power Connect to ground. 11 NO_INB Output Goes high when clock on INB stops. 12 NO_INA Output Goes high when clock on INA stops. 13 CLK2 Output Clock 2 output. Low skew compared to CLK1. 14 CLK1 Output Clock 1 output. Low skew compared to CLK2. 15 VDDC Power Main chip supply. Output clocks amplitude will match this VDD. 16 OE1 Input Output enable. Tri-states CLK1 when low. Internal pull-up. MDS 580-01 D Pin Description 2 Revision 021605 Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com ICS580-01 Glitch-Free Clock Multiplexer Device Operation The ICS580-01 consists of a glitch free mux between INA and INB controlled by SELB. The device is designed to switch between two clocks, whether running or not. In the first example, clocks are running on both INA and INB. When SELB changes, the output clock goes low after three cycles of the output clock (nominally). The output then stays low for three cycles of the new input clock (nominally) and then starts with the new input clock. This is shown in Figure 1. Figure 1 INA INB SELB CLK1, 2 In the second example, one of the inputs was selected and running but has since stopped (either high or low). This is indicated by either NO_INA or NO_INB going high depending on whether INA or INB has stopped. These signals go high following a selectable time-out period after the clock has stopped. The timeout period is determined by the DIV input in. The SELB pin is now changed to select the new input clock which is running. The output clock immediately goes low and stays low for three cycles of the new input clock and then starts with the new input clock. Figure 2 shows an example of this Figure 2 INA INB SELB Timeout NO_INA CLK1, 2 MDS 580-01 D 3 Revision 021605 Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com ICS580-01 Glitch-Free Clock Multiplexer Application Example In the third example, the ICS580-01 is configured to automatically switch clocks when an input stops. The clock that could stop is connected to INA while the backup clock (always running) is connected to INB. The output NO_INA is connected to SELB. This means that when the clock on INA stops, NO_INA goes high selecting the clock on INB which is muxed to the output after three cycles. When the clock on INA restarts, NO_INA immediately goes low, selecting the clock on INA. The output then switches in the manner described in the first example. The circuit diagram in Figure 3 shows a typical connection for this example. Note that CLK2 and NO_INB are unused and are disabled by grounding OE2 and OE4. A 33 series termination resistor is used on the clock output and two decoupling capacitors of 0.01F are used. All other inputs are left floating and are therefore pulled high by the on-chip pull-ups. VDD SELB OE1 VDDC DIV 0.01F VDDI CLK1 Normal Clock INA CLK2 Backup Clock INB NO_INA GND NO_INB OE4 GND OE3 OE2 0.01F Output Clock 33 Output Enable Each output has a dedicated output enable pin. If an output is unused, it should be tri-stated by tying the appropriate output enable pin to ground. External Components The ICS580-01 requires two 0.01F decoupling capacitors, one between VDDI and GND and one between VDDC and GND. Series termination resistors of 33 can be used on CLK1 and CLK2. MDS 580-01 D 4 Revision 021605 Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com ICS580-01 Glitch-Free Clock Multiplexer Split Power Supplies The VDDI pin provides the power for the INA and INB input buffers only. All the other inputs and the rest of the chip are connected to VDDC. This allows for supply voltage translation. For example, INA and INB could be 5V clocks (VDDI = 5V) and the rest of the chip could use a 3.3V supply on VDDC giving 3.3V output clocks. For correct operation VDDI must always be greater than or equal to VDDC. Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS580-01. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7V All Inputs and Outputs -0.5V to VDD+0.5V Ambient Operating Temperature 0 to +70C Ambient Operating Temperature -40 to +85C Storage Temperature -65 to +150C Junction Temperature 175C Soldering Temperature 260C Recommended Operation Conditions Parameter Min. Typ. Max. Units Ambient Operating Temperature 0 +70 C Ambient Operating Temperature -40 +85 C Power Supply Voltage (measured in respect to GND) +2.5 +5.5 V DC Electrical Characteristics Unless stated otherwise, VDD = 3.3V 5%, Ambient Temperature -40 to +85C Parameter Operating Voltage Symbol Conditions Typ. Max. Units VDDC 2.5 5.5 V VDDI VDDC 5.5 V Supply Current IDD 50 MHz, no load Input High Voltage VIH Non-clock inputs Input Low Voltage VIL Non-clock inputs Input High Voltage VIH INA and INB only Note 3 MDS 580-01 D Min. 5 6 2 (VDDC/2)+1 VDDC/2 mA VDDC V 0.8 V VDDI V Revision 021605 Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com ICS580-01 Glitch-Free Clock Multiplexer Parameter Symbol Conditions Input Low Voltage VIL INA and INB only Note 3 Input Capacitance CIN Output High Voltage VOH IOH = -12 mA Output Low Voltage VOL IOL = 12 mA Short Circuit Current IOS On-chip pull-up Resistor RPU Min. Typ. Max. Units VDDC/2 (VDDC/2)-1 V 4 pF VDDC-0.5 V 0.5 Non-clock inputs Pull-up to VDDC V 70 mA 250 k AC Electrical Characteristics Unless stated otherwise, VDD = 3.3V 5%, Ambient Temperature -40 to +85 C Parameter Input Frequency INA and INB, Note 1 Propagation Delay INA or INB to output Symbol fIN Conditions Min. Typ. Max. Units VDDC = 5V 1/timeout 270 MHz VDDC = 3.3V 1/timeout 220 MHz VDDC = 2.7V 1/timeout 180 MHz VDDC = 5V 4 8 ns VDDC = 3.3V 5 10 ns VDDC = 2.7V 6 12 ns VDDI = 5V 175 350 750 ns VDDI = 3.3V 500 1000 2000 ns VDDI = 2.7V 750 1500 3000 ns VDDI = 5V 20 40 80 ns VDDI = 3.3V 55 110 210 ns VDDI = 2.7V 100 200 400 ns Output Clock Rise Time 1.5 ns Output Clock Fall Time 1.5 ns 250 ps Transition Detector Timeout, DIV = 0 Transition Detector Timeout, DIV = 1 Output Clock Skew CLK1 to CLK2 Note 2 -250 0 Note 1. Frequencies less than the minimum may cause a timeout which will not guarantee glitch-free switching unless the clock is actually stopped. Note 2: Assumes identically loaded outputs with identical rise times, measured at VDD/2. Note 3: Output duty cycle is set by duty cycle of input clock at VDDC/2. MDS 580-01 D 6 Revision 021605 Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com ICS580-01 Glitch-Free Clock Multiplexer Thermal Characteristics Parameter Symbol Thermal Resistance Junction to Ambient Thermal Resistance Junction to Case Min. 120 C/W JA 1 m/s air flow 115 C/W JA 3 m/s air flow 105 C/W 58 C/W JC Marking Diagram (ICS580M-01LF) 16 1 8 Marking Diagram (ICS580M-01I) 8 Marking Diagram (ICS580M-01ILF) 16 9 9 580M01ILF ###### YYWW ICS580M-01I ###### YYWW 1 9 580M01LF ###### YYWW ICS580M-01 ###### YYWW 16 Max. Units Still air 9 1 Typ. JA Marking Diagram (ICS580M-01) 16 Conditions 1 8 8 Notes: 1. ###### is the lot number. 2. YYWW is the last two digits of the year and week that the part was assembled. 3. "LF" denotes Pb (lead) free package. MDS 580-01 D 7 Revision 021605 Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com ICS580-01 Glitch-Free Clock Multiplexer Package Outline and Package Dimensions (16 pin SOIC, 150 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95 16 Millimeters Symbol E Min A A1 B C D E e H h L H INDEX AREA 1 2 D A Inches Max Min 1.35 1.75 0.10 0.25 0.33 0.51 0.19 0.25 9.80 10.00 3.80 4.00 1.27 BASIC 5.80 6.20 0.25 0.50 0.40 1.27 0 8 Max .0532 .0688 .0040 .0098 .013 .020 .0075 .0098 .3859 .3937 .1497 .1574 0.050 BASIC .2284 .2440 .010 .020 .016 .050 0 8 h x 45 A1 C -Ce SEATING PLANE B L .10 (.004) C Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature ICS580M-01 Tubes 16-pin SOIC 0 to +70 C ICS580M-01T Tape and Reel 16-pin SOIC 0 to +70 C ICS580M-01LF Tubes 16-pin SOIC 0 to +70 C ICS580M-01LFT Tape and Reel 16-pin SOIC 0 to +70 C Tubes 16-pin SOIC -40 to +85 C Tape and Reel 16-pin SOIC -40 to +85 C ICS580M-01I ICS580M-01IT see page 7 ICS580M-01ILF Tubes 16-pin SOIC -40 to +85 C ICS580M-01ILFT Tape and Reel 16-pin SOIC -40 to +85 C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. MDS 580-01 D 8 Revision 021605 Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA 95126 tel (408) 297-1201 www.icst.com