Rev.1.00, Sep.21.2005, page 1 of 13
R1LV1616HBG-I Series
Wide Temperature Range Version
16 M SRAM (1-Mword × 16-bit) REJ03C0263-0100
Rev.1.00
Sep.21.2005
Description
The R1LV1616HBG-I Series is 16-Mbit static RAM organized 1-Mword × 16-bit. R1LV1616HBG-I Series has
realized higher density, higher performance and low power consumption by employing CMOS process technology (6-
transistor memory cell). It offers low power standby power dissipation; therefore, it is suitable for battery backup
systems. It is packaged in 48-ball plastic FBGA for high density surface mounting.
Features
• Single 3.0 V supply: 2.7 V to 3.6 V
• Fast access time: 45/55 ns (max)
• Power dissipation:
Active: 9 mW/MHz (typ)
Standby: 1.5 µW (typ)
• Completely static memory.
No clock or timing strobe required
• Equal access and cycle times
• Common data input and output.
Three state output
• Battery backup operation.
2 chip selection for battery backup
• Temperature range: −40 to +85°C
Ordering Information
Type No. Access time Package
R1LV1616HBG-4SI 45 ns 48-ball plastic FBGA with 0.75 mm ball pitch
R1LV1616HBG-5SI 55 ns PTBG0048HF (48FHJ)
R1LV1616HBG-I Series
Rev.1.00, Sep.21.2005, page 2 of 13
Pin Arrangement
(Top view)
48-ball FBGA
A
B
C
D
E
F
G
H
1 2 3 4 5 6
LB#
I/O8
I/O9
VSS
VCC
I/O14
I/O15
A18
OE#
UB#
I/O10
I/O11
I/O12
I/O13
A19
A8
A3
A5
A17
VSS
A14
A0
A12
A9
A1
A4
A6
A7
A16
A15
A13
A10
A2
CS1#
I/O1
I/O3
I/O4
I/O5
WE#
A11
CS2
I/O0
I/O2
VCC
VSS
I/O6
I/O7
NU
Pin Description
Pin name Function
A0 to A19 Address input
I/O0 to I/O15 Data input/output
CS1# (CS1) Chip select 1
CS2 Chip select 2
WE# (WE) Write enable
OE# (OE) Output enable
LB# (LB) Lower byte select
UB# (UB) Upper byte select
VCC Power supply
VSS Ground
NU*1 Not used (test mode pin)
Note: 1. This pin should be connected to a ground (VSS), or not be connected (open).
R1LV1616HBG-I Series
Rev.1.00, Sep.21.2005, page 3 of 13
Block Diagram
•
•
•
•
•
•
••
•
•
•
I/O0
I/O15
CS2
WE#
OE#
A17 A7 A5 A2
V
V
CC
SS
Row
decoder Memory matrix
8,192 x 128 x 16
Column I/O
Column decoder
Input
data
control
Control logic
A1
A19
A8
A9
A10
A11
A12
A13
A14
A16
A18
A15
A3
A6
LB#
UB#
A4
LSB
MSB
MSB LSB
A0
CS1#
R1LV1616HBG-I Series
Rev.1.00, Sep.21.2005, page 4 of 13
Operation Table
CS1# CS2 WE# OE# UB# LB# I/O0 to I/O7 I/O8 to I/O15 Operation
H × × × × × High-Z High-Z Standby
× L × × × × High-Z High-Z Standby
× × × × H H High-Z High-Z Standby
L H H L L L Dout Dout Read
L H H L H L Dout High-Z Lower byte read
L H H L L H High-Z Dout Upper byte read
L H L × L L Din Din Write
L H L × H L Din High-Z Lower byte write
L H L × L H High-Z Din Upper byte write
L H H H × × High-Z High-Z Output disable
Note: H: VIH, L: VIL, ×: VIH or VIL
Absolute Maximum Ratings
Parameter Symbol Value Unit
Power supply voltage relative to VSS V
CC −0.5 to +4.6 V
Terminal voltage on any pin relative to VSS VT −0.5*1 to VCC + 0.3*2 V
Power dissipation PT 1.0 W
Storage temperature range Tstg −55 to +125 °C
Storage temperature range under bias Tbias −40 to +85 °C
Notes: 1. VT min: −2.0 V for pulse half-width ≤ 10 ns.
2. Maximum voltage is +4.6 V.
DC Operating Conditions
Parameter Symbol Min Typ Max Unit Note
Supply voltage VCC 2.7 3.0 3.6 V
V
SS 0 0 0 V
Input high voltage VIH 2.2 VCC + 0.3 V
Input low voltage VIL −0.3 0.6 V 1
Ambient temperature range Ta −40 +85 °C
Note: 1. VIL min: −2.0 V for pulse half-width ≤ 10 ns.
R1LV1616HBG-I Series
Rev.1.00, Sep.21.2005, page 5 of 13
DC Characteristics
Parameter Symbol Min Typ Max Unit Test conditions
Input leakage current |ILI| 1 µA Vin = VSS to VCC
Output leakage current |ILO| 1 µA CS1# = VIH or CS2 = VIL or
OE# = VIH or WE# = VIL or
LB# = UB# = VIH, VI/O = VSS to VCC
Operating current ICC 20 mA CS1# = VIL, CS2 = VIH,
Others = VIH/ VIL, II/O = 0 mA
Average operating current ICC1
(READ) 22*1 35 mA Min. cycle, duty = 100%,
II/O = 0 mA, CS1# = VIL, CS2 = VIH,
WE# = VIH, Others = VIH/VIL
I
CC1 30*1 50 mA Min. cycle, duty = 100%,
II/O = 0 mA, CS1# = VIL, CS2 = VIH,
Others = VIH/VIL
I
CC2
(READ) 3*1 8 mA Cycle time = 70 ns, duty = 100%,
II/O = 0 mA, CS1# = VIL, CS2 = VIH,
WE# = VIH, Others = VIH/VIL
Address increment scan or decrement
scan
I
CC2 20*1 30 mA Cycle time = 70 ns, duty = 100%,
II/O = 0 mA, CS1# = VIL, CS2 = VIH,
Others = VIH/VIL
Address increment scan or decrement
scan
I
CC3 3*1 8 mA Cycle time = 1 µs, duty = 100%,
II/O = 0 mA, CS1# ≤ 0.2 V,
CS2 ≥ VCC − 0.2 V
VIH ≥ VCC − 0.2 V, VIL ≤ 0.2 V
ISB 0.1*1 0.5 mA CS2 = VIL Standby current
ISB1
0.5*1
8
µA
0 V ≤ Vin
(1) 0 V ≤ CS2 ≤ 0.2 V or
(2) CS1# ≥ VCC − 0.2 V,
CS2 ≥ VCC − 0.2 V or
(3) LB# = UB# ≥ VCC − 0.2 V,
CS2 ≥ VCC − 0.2 V,
CS1# ≤ 0.2 V
Average value
Output high voltage VOH 2.4 V IOH = −1 mA
V
OH V
CC − 0.2 V IOH = −100 µA
Output low voltage VOL 0.4 V IOL = 2 mA
V
OL 0.2 V IOL = 100 µA
Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25°C and not guaranteed.
R1LV1616HBG-I Series
Rev.1.00, Sep.21.2005, page 6 of 13
Capacitance
(Ta = +25°C, f = 1.0 MHz)
Parameter Symbol Min Typ Max Unit Test conditions Note
Input capacitance Cin 8 pF Vin = 0 V 1
Input/output capacitance CI/O 10 pF VI/O = 0 V 1
Note: 1. This parameter is sampled and not 100% tested.
AC Characteristics
(Ta = −40 to +85°C, VCC = 2.7 V to 3.6 V)
Test Conditions
• Input pulse levels: VIL = 0.4 V, VIH = 2.4 V
• Input rise and fall time: 5 ns
• Input and output timing reference levels: 1.4 V
• Output load: See figures (Including scope and jig)
50pF
Dout
RL=500 Ω
1.4 V
R1LV1616HBG-I Series
Rev.1.00, Sep.21.2005, page 7 of 13
Read Cycle
R1LV1616HBG-I
-4SI -5SI
Parameter Symbol Min Max Min Max Unit Notes
Read cycle time tRC 45 55 ns
Address access time tAA 45 55 ns
Chip select access time tACS1 45 55 ns
t
ACS2 45 55 ns
Output enable to output valid tOE 30 35 ns
Output hold from address change tOH 10 10 ns
LB#, UB# access time tBA 45 55 ns
Chip select to output in low-Z tCLZ1 10 10 ns 2, 3
t
CLZ2 10 10 ns 2, 3
LB#, UB# enable to low-Z tBLZ 5 5 ns 2, 3
Output enable to output in low-Z tOLZ 5 5 ns 2, 3
Chip deselect to output in high-Z tCHZ1 0 20 0 20 ns 1, 2, 3
t
CHZ2 0 20 0 20 ns 1, 2, 3
LB#, UB# disable to high-Z tBHZ 0 15 0 20 ns 1, 2, 3
Output disable to output in high-Z tOHZ 0 15 0 20 ns 1, 2, 3
Write Cycle
R1LV1616HBG-I
-4SI -5SI
Parameter Symbol Min Max Min Max Unit Notes
Write cycle time tWC 45 55 ns
Address valid to end of write tAW 45 50 ns
Chip selection to end of write tCW 45 50 ns 5
Write pulse width tWP 35 40 ns 4
LB#, UB# valid to end of write tBW 45 50 ns
Address setup time tAS 0 0 ns 6
Write recovery time tWR 0 0 ns 7
Data to write time overlap tDW 25 25 ns
Data hold from write time tDH 0 0 ns
Output active from end of write tOW 5 5 ns 2
Output disable to output in high-Z tOHZ 0 15 0 20 ns 1, 2
Write to output in high-Z tWHZ 0 15 0 20 ns 1, 2
Notes: 1. tCHZ, tOHZ, tWHZ and t BHZ are defined as the time at which the outputs achieve the open circuit conditions and
are not referred to output voltage levels.
2. This parameter is sampled and not 100% tested.
3. At any given temperature and voltage condition, tHZ max is less than tLZ min both for a given device and from
device to device.
4. A write occurs during the overlap of a low CS1#, a high CS2, a low WE# and a low LB# or a low UB#. A write
begins at the latest transition among CS1# going low, CS2 going high, WE# going low and LB# going low or
UB# going low. A write ends at the earliest transition among CS1# going high, CS2 going low, WE# going
high and LB# going high or UB# going high. tWP is measured from the beginning of write to the end of write.
5. tCW is measured from the later of CS1# going low or CS2 going high to the end of write.
6. tAS is measured from the address valid to the beginning of write.
7. tWR is measured from the earliest of CS1# or WE# going high or CS2 going low to the end of write cycle.
R1LV1616HBG-I Series
Rev.1.00, Sep.21.2005, page 8 of 13
Timing Waveform
Read Cycle
tAA tACS1
tACS2
tCLZ2
tCLZ1
tBLZ
tBA
tOH
tRC
Valid data
Valid address
High impedance
CS1#
CS2
LB#, UB#
OE#
tOLZ
tOE
tCHZ1
tCHZ2
tBHZ
tOHZ
Address
Dout
R1LV1616HBG-I Series
Rev.1.00, Sep.21.2005, page 9 of 13
Write Cycle (1) (WE# Clock)
WE#
tWC
tAW
tWP
tWR
tCW
tCW
tBW
tAS
tOW
tWHZ
tDW tDH
Valid address
Valid data
CS1#
LB#, UB#
High impedance
CS2
Address
Dout
Din
R1LV1616HBG-I Series
Rev.1.00, Sep.21.2005, page 10 of 13
Write Cycle (2) (CS1#, CS2 Clock, OE# = VIH)
Address
WE#
t
WC
t
AW
t
WP
t
WR
t
CW
t
CW
t
BW
t
AS
t
DW
t
DH
Valid address
Valid data
LB#, UB#
Dout
Din
High impedance
CS2
CS1#
t
AS
R1LV1616HBG-I Series
Rev.1.00, Sep.21.2005, page 11 of 13
Write Cycle (3) (LB#, UB# Clock, OE# = VIH)
Address
WE#
t
WC
t
AW
t
WP
t
CW
t
CW
t
BW
t
BW
t
WR
t
DW
t
DH
Valid address
UB# (LB#)
High impedance
CS2
CS1#
t
AS
LB# (UB#)
Dout
Din-UB
(Din-LB)
Din-LB
(Din-UB)
Valid data
t
DW
t
DH
Valid data
R1LV1616HBG-I Series
Rev.1.00, Sep.21.2005, page 12 of 13
Low VCC Data Retention Characteristics
(Ta = −40 to +85°C)
Parameter Symbol Min Typ Max Unit Test conditions*2
VCC for data retention VDR 1.5 3.6 V Vin ≥ 0 V
(1) 0 V ≤ CS2 ≤ 0.2 V or
(2) CS2 ≥ VCC − 0.2 V,
CS1# ≥ VCC − 0.2 V or
(3) LB# = UB# ≥ VCC − 0.2 V,
CS2 ≥ VCC − 0.2 V,
CS1# ≤ 0.2 V
Data retention current
ICCDR
0.5*1
8
µA
VCC = 3.0 V, Vin ≥ 0 V
(1) 0 V ≤ CS2 ≤ 0.2 V or
(2) CS2 ≥ VCC − 0.2 V,
CS1# ≥ VCC − 0.2 V or
(3) LB# = UB# ≥ VCC − 0.2 V,
CS2 ≥ VCC − 0.2 V,
CS1# ≤ 0.2 V
Average value
Chip deselect to data
retention time tCDR 0 ns See retention waveforms
Operation recovery time tR 5 ms
Notes: 1. Typical values are at VCC = 3.0 V, Ta = +25°C and not guaranteed.
2. CS2 controls address buffer, WE# buffer, CS1# buffer, OE# buffer, LB#, UB# buffer and Din buffer. If CS2
controls data retention mode, Vin levels (address, WE#, OE#, CS1#, LB#, UB#, I/O) can be in the high
impedance state. If CS1# controls data retention mode, CS2 must be CS2 ≥ VCC − 0.2 V or 0 V ≤ CS2 ≤ 0.2
V. The other input levels (address, WE#, OE#, LB#, UB#, I/O) can be in the high impedance state.
R1LV1616HBG-I Series
Rev.1.00, Sep.21.2005, page 13 of 13
Low VCC Data Retention Timing Waveform (1) (CS1# Controlled)
CC
V
2.7 V
2.2 V
0 V
CS1#
t
CDR
t
R
CS1# V – 0.2 V
CC
DR
V
Data retention mode
≥
Low VCC Data Retention Timing Waveform (2) (CS2 Controlled)
CC
V
2.7 V
0.6 V
0 V
CS2
CDR
t
R
0 V CS2 0.2 V
DR
V
Data retention modet
< <
Low VCC Data Retention Timing Waveform (3) (LB#, UB# Controlled)
CC
V
2.7 V
2.2 V
0 V
LB#, UB#
tCDR tR
LB#, UB# V – 0.2 V
CC
≥
DR
V
Data retention mode
Revision History R1LV1616HBG-I Series Data Sheet
Contents of Modification Rev. Date Page Description
0.01 Apr. 29. 2005 Initial issue
1.00 Sep. 21. 2005 Deletion of Preliminary
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