– 1 – E01656A34
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
ICX412AQ
20 pin DIP (Plastic)
2
8
V
H
Pin 1
Pin 11 48
4
Diagonal 8.933mm (Type 1/1.8) Frame Readout CCD Image Sensor with a Square Pixel for Color Cameras
Description
The ICX412AQ is a diagonal 8.933mm (Type 1/1.8)
interline CCD solid-state image sensor with a square
pixel array and 3.24M effective pixels. Sensitivity,
saturation signal, smear and frame rate have been
improved compared to the ICX252AQ.
This chip features an electronic shutter with variable
charge-storage time.
R, G, B primary color mosaic filters are used as the
color filters, and at the same time high sensitivity and
low dark current are achieved through the adoption
of Super HAD CCD technology.
This chip is suitable for applications such as
electronic still cameras, etc.
Features
•Suppor ts frame readout
•High horizontal and vertical resolution
•Suppor ts high frame rate readout mode: 30 frames/s,
AF1 mode: 60 frames/s, 50 frames/s,
AF2 mode: 120 frames/s, 100 frames/s
•Square pixel
•Horizontal drive frequency: 22.5MHz
•No voltage adjustments (reset gate and substrate bias are not adjusted.)
•R, G, B primar y color mosaic filters on chip
•High sensitivity, low dar k current
•Continuous variable-speed shutter
•Excellent anti-blooming characteristics
•Exit pupil distance recommended range –20 to –100mm
•20-pin high-precision plastic package
Device Structure
•Interline CCD image sensor
•Total number of pixels: 2140 (H) × 1560 (V) approx . 3.34M pixels
•Number of effective pixels: 2088 (H) × 1550 (V) approx. 3.24M pixels
•Number of active pixels: 2080 (H) × 1542 (V) approx. 3.21M pixels diagonal 8.933mm
•Number of recommended recording pixels:
2048 (H) × 1536 (V) approx. 3.15M pixels diagonal 8.832mm aspect ratio 4:3
•Chip size: 8.10mm (H) × 6.64mm (V)
•Unit cell size: 3.45µm (H) × 3.45µm (V)
•Optical black: Horizontal (H) direction: Front 4 pixels, rear 48 pixels
Ver tical (V) direction: Front 8 pixels, rear 2 pixels
•Number of dummy bits: Horizontal 28
Ver tical 1 (even fields only)
•Substrate material: Silicon
Optical black position
(T op Vie w)
∗Super HAD CCD is a trademark of Sony Corporation. The Super HAD CCD is a version of Sony's high performance CCD HAD (Hole-
Accumulation Diode) sensor with sharply improved sensitivity by the incor poration of a new semiconductor technology developed by
Sony Corporation.
– 2 –
ICX412AQ
11 12 13 14 15 16 17 18 19 20
Note)
Note) : Photo sensor
Horizontal register
Vertical register
V
DD
φRG
Hφ
2
Hφ
1
GND
φSUB
C
SUB
V
L
Hφ
1
Hφ
2
10 9 8 7 6 5 4 3 2 1
V
OUT
GND
TEST
TEST
Vφ
1B
Vφ
1A
Vφ
2
Vφ
3B
Vφ
3A
Vφ
4
B
Gr
B
Gr
B
Gb
R
Gb
R
Gb
B
Gr
B
Gr
B
Gb
R
Gb
R
Gb
GrRGrR
Block Diagram and Pin Configuration
(Top View)
Pin Description
Pin No. Description Pin No. Symbol Description
1
2
3
4
5
6
7
8
9
10
Vφ4
Vφ3A
Vφ3B
Vφ2
Vφ1A
Vφ1B
TEST
TEST
GND
VOUT
Ver tical register transfer clock
Ver tical register transfer clock
Ver tical register transfer clock
Ver tical register transfer clock
Ver tical register transfer clock
Ver tical register transfer clock
Test pin∗1
Test pin∗1
GND
Signal output
11
12
13
14
15
16
17
18
19
20
VDD
φRG
Hφ2
Hφ1
GND
φSUB
CSUB
VL
Hφ1
Hφ2
∗1Leave this pin open
∗2DC bias is generated within the CCD, so that this pin should be grounded externally through a capacitance
of 0.1µF.
Supply voltage
Reset gate clock
Horizontal register transfer clock
Horizontal register transfer clock
GND
Substrate clock
Substrate bias∗2
Protective transistor bias
Horizontal register transfer clock
Horizontal register transfer clock
Symbol
– 3 –
ICX412AQ
Absolute Maximum Ratings
Item
VDD, VOUT, φRG – φSUB
Vφ1A, Vφ1B, Vφ3A, Vφ3B – φSUB
Vφ2, Vφ4, VL – φSUB
Hφ1, Hφ2, GND – φSUB
CSUB – φSUB
VDD, VOUT, φRG, CSUB – GND
Vφ1A, Vφ1B, Vφ2, Vφ3A, Vφ3B, Vφ4 – GND
Hφ1, Hφ2 – GND
Vφ1A, Vφ1B, Vφ3A, Vφ3B – VL
Vφ2, Vφ4, Hφ1, Hφ2, GND – VL
Voltage difference between vertical clock input pins
Hφ1 – Hφ2
Hφ1, Hφ2 – Vφ4
Against φSUB
Against φGND
Against φVL
Between input
clock pins
Storage temperature
Guaranteed temperature of perfor mance
Operating temperature
–40 to +12
–50 to +15
–50 to +0.3
–40 to +0.3
–25 to
–0.3 to +22
–10 to +18
–10 to +6.5
–0.3 to +28
–0.3 to +15
to +15
–6.5 to +6.5
–10 to +16
–30 to +80
–10 to +60
–10 to +75
V
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
°C
∗1
Ratings Unit Remarks
∗1+24V (Max.) when clock width < 10µs, clock duty factor < 0.1%.
+16V (Max.) is guaranteed for tur ning on or off power supply.
– 4 –
ICX412AQ
Bias Conditions
Supply voltage
Protective transistor bias
Substrate clock
Reset gate clock
Item VDD
VL
φSUB
φRG
Symbol 15.0
∗1
∗2
∗2
Min. V
Unit RemarksTyp. Max.
∗1VL setting is the VVL voltage of the vertical clock waveform, or the same voltage as the VL power supply for
the V driver should be used.
∗2Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated
within the CCD.
DC Characteristics
14.55 15.45
Supply current
Item
IDD
Symbol
7.5
Min. Unit RemarksTyp. Max.
mA9.55.5
Clock Voltage Conditions
Readout clock voltage
Ver tical transfer clock
voltage
Horizontal transfer
clock voltage
Reset gate clock
voltage
Substrate clock voltage
Item
VVT
VVH1, VVH2
VVH3, VVH4
VVL1, VVL2,
VVL3, VVL4
VφV
VVH3 – VVH
VVH4 – VVH
VVHH
VVHL
VVLH
VVLL
VφH
VHL
VCR
VφRG
VRGLH – VRGLL
VRGL – VRGLm
VφSUB
Symbol
14.55
–0.05
–0.2
–8.0
6.8
–0.25
–0.25
4.0
–0.05
0.8
3.0
21.5
Min.
15.0
0
0
–7.5
7.5
5.0
0
2.5
3.3
22.5
Typ.
15.45
0.05
0.05
–7.0
8.05
0.1
0.1
0.8
0.9
0.9
0.8
5.25
0.05
5.25
0.4
0.5
23.5
Max. Unit
1
2
2
2
2
2
2
2
2
2
2
3
3
3
4
4
4
5
Waveform
Diagram
VVH = (VVH1 + VVH2)/2
VVL = (VVL3 + VVL4)/2
VφV = VVHn – VVLn (n = 1 to 4)
High-le vel coupling
High-le vel coupling
Low-level coupling
Low-level coupling
Cross-point voltage
Low-level coupling
Low-level coupling
Remarks
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
– 5 –
ICX412AQ
Clock Equivalent Circuit Constants
Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit
Hφ
1
Hφ
2
Cφ
H1
Cφ
H2
Cφ
HH
Rφ
H
Rφ
H
Hφ
1
Hφ
2
Rφ
H
Rφ
H
R
GND
Cφ
V1B3B
R
1B
Cφ
V41B
Vφ
1B
Cφ
V4
Cφ
V41A
Cφ
V1B
Cφ
V1B3A
Cφ
V1A1B
Cφ
V1A
Cφ
V1B2
R
1A
Vφ
1A
Cφ
V1A2
Vφ
2
R
2
Cφ
V24
Cφ
V1A3A
Cφ
V23A
Cφ
V23B
R
3A
Vφ
3A
Cφ
V2
Cφ
V3A
Cφ
V3A3B
Cφ
V1A3B
Cφ
V3B
R
3B
Vφ
3B
Cφ
V3A4
Cφ
V3B4
Vφ
4
R
4
CφV1A, CφV3A
CφV1B, CφV3B
CφV2, CφV4
CφV1A2, CφV3A4
CφV1B2, CφV3B4
CφV23A, CφV41A
CφV23B, CφV41B
CφV1A3A
CφV1B3B
CφV1A3B, CφV1B3A
CφV24
CφV1A1B, CφV3A3B
CφH1, CφH2
CφHH
CφRG
CφSUB
R1A, R1B, R2,
R3A, R3B, R4
RGND
RφH
Symbol
Capacitance between ve rtical transfer
clock and GND
Capacitance between ve rtical transfer
clocks
Capacitance between horizontal transfer
clock and GND
Capacitance between horizontal transfer
clocks
Capacitance between reset gate clock
and GND
Capacitance between substrate clock
and GND
Ver tical transfer clock series resistor
Ver tical transfer clock ground resistor
Horizontal transfer clock series resistor
Item Min. Typ. Max. pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
Ω
Ω
Ω
Unit Remarks
1500
5600
2700
390
470
120
180
39
220
62
75
68
36.5
88.5
8
1000
62
18
15
– 6 –
ICX412AQ
Drive Clock Waveform Conditions
(1) Readout clock waveform
VVH = (VVH1 + VVH2)/2
VVL = (VVL3 + VVL4)/2
VφV = VVHn – VVLn (n = 1 to 4)
(2) V ertical transfer clock waveform
100%
90%
10%
0% tr tf 0V
twh
φM
2
φM
V
VT
V
VH1
V
VHH
V
VHL
V
VH
V
VLH
V
VL1
V
VLL
V
VHL
V
VHH
V
VL
V
VH2
V
VHH
V
VHH
V
VHL
V
VHL
V
VH
V
VLH
V
VL2
V
VLL
V
VL
V
VHH
V
VH
V
VLH
V
VLL
V
VL
V
VHL
V
VL3
V
VHL
V
VH3
V
VHH
V
VH
V
VL
V
VHL
V
VLH
V
VLL
V
VHL
V
VH4
V
VHH
V
VHH
V
VL4
Vφ1A, Vφ1B Vφ3A, Vφ3B
Vφ2Vφ4
– 7 –
ICX412AQ
VHL
VCR
twl
two
twh
VφH
VφH
2
tr
Hφ2
90%
10%
Hφ1
tf
RG waveform
V
RGLH
V
RGH
V
RGL
V
RGLL
V
RGLm
tr twh
twl
tf
Vφ
RG
Point A
V
SUB
(A bias generated within the CCD)
100%
90%
10%
0% tr tftwh
φM
2
φM
Vφ
SUB
(3) Horizontal transfer clock waveform
Cross-point voltage for the Hφ1 r ising side of the horizontal transfer clocks Hφ1 and Hφ2 wavefor ms is VCR.
The over lap period for twh and twl of horizontal transfer clocks Hφ1 and H φ2 is two.
(4) Reset gate clock waveform
VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the per iod from
Point A in the above diagram until the rising edge of RG.
In addition, VRGL is the average value of VRGLH and VRGLL.
VRGL = (VRGLH + VRGLL)/2
Assuming VRGH is the minimum value during the interval with twh, then:
VφRG = VRGH – VRGL
Negative overshoot level during the falling edge of RG is VRGLm.
(5) Substrate clock waveform
– 8 –
ICX412AQ
Spectral Sensitivity Characteristics (excludes lens characteristics and light source characteristics)
Clock Switching Characteristics (Horizontal drive frequency: 22.5MHz)
0400 450 500 550 600 650 700
0.1
0.2
0.3
0.4
0.5
0.6
0.7 B
GR
0.8
0.9
1.0
Relative Response
Wave Length [nm]
Min.
twh
Typ. Max.Min. Typ. Max.Min. Typ. Max.Min. Typ. Max.
twl tr tf
2.63
12
12
6
2.5
2.83
16
16
8
3.02
12
12
16
16
31
0.5
6.5
6.5
3
10.5
10.5
0.5
15
0.5
6.5
6.5
3
350
10.5
10.5
0.5
Unit
µs
ns
ns
ns
µs
Remarks
During
readout
When using
CXD3400N
tf ≥ tr – 2ns
When draining
charge
Item
Readout clock
Vertical transfer
clock
Horizontal
transfer clock
Reset gate clock
Substrate clock
Symbol
VT
Vφ1A, Vφ1B,
Vφ2, Vφ3A,
Vφ3B, Vφ4
Hφ1
Hφ2
φRG
φSUB
Min. two
Typ. Max.
10 16
Unit
ns
RemarksItem
Horizontal transfer clock
Symbol
Hφ1, Hφ2
– 9 –
ICX412AQ
Image Sensor Characteristics (horizontal drive frequency: 22.5MHz) (Ta = 25°C)
∗1After closing the mechanical shutter, the smear can be reduced to below the detection limit by perfor ming
vertical register sweep operation.
∗2Excludes ver tical dark signal shading caused by vertical register high-speed transfer.
4
V
10
4
4
4
Ignored region
Effective pixel region
Zone 0, I
Zone II, II'
V
10
H
8H
8
2088 (H)
1550 (V)
Zone Definition of Video Signal Shading
Measurement System
CCD C.D.S S/H
S/H
AMP
CCD signal output [∗A]
Gr/Gb channel signal output [∗B]
R/B channel signal output [∗C]
Note) Adjust the amplifier gain so that the gain between [∗A] and [∗B], and between [∗A] and [∗C] equals 1.
Item
G Sensitivity
Sensitivity
comparison
Saturation signal
Smear
Video signal shading
Dark signal
Dark signal shading
Line crawl G
Line crawl R
Line crawl B
Lag
Symbol
Sg
Rr
Rb
Vsat
Sm
SHg
Vdt
∆Vdt
Lcg
Lcr
Lcb
Lag
Min.
364
0.4
0.35
500
Typ.
455
–92
–82.5
Max.
546
0.7
0.65
–84
–74.5
20
25
10
5
3.8
3.8
3.8
0.5
Unit
mV
mV
dB
%
mV
mV
%
%
%
%
Measurement
method
1
1
1
2
3
4
5
6
7
7
7
8
Remarks
1/30s accumulation
Ta = 60°C
Frame readout mode∗1
High frame rate readout mode
Zone 0 and I
Zone 0 to II'
Ta = 60°C, 5.0 frame/s
Ta = 60°C, 5.0 frame/s, ∗2
R
B
– 10 –
ICX412AQ
Image Sensor Characteristics Measurement Method
Measurement conditions
(1) In the following measurements, the device dr ive conditions are at the typical values of the bias and clock
voltage conditions, and the frame readout mode is used. In addition, VSUB Cont. is turned off.
(2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical
black level (OB) is used as the reference for the signal output, which is taken as the value of the Gr/Gb
channel signal output or the R/B channel signal output of the measurement system.
Color coding of this image sensor & Readout
The primary color filters of this image sensor are arranged in
the layout shown in the figure on the left (Bayer arrangement).
Gr and Gb denote the G signals on the same line as the R
signal and the B signal, respectively.
For frame readout, the A1 and A2 lines are output as signals in
the A field, and the B1 and B2 lines in the B field.
Gb B Gb B
RGrRGr
Gb B Gb B
RGrRGr
B2
B1
A2
A1
Horizontal register
Color Coding Diagram
– 11 –
ICX412AQ
2. Frame readout mode, high frame rate readout mode
Readout modes
1. Readout modes list
The following readout modes are possible by driving the image sensor at the timing specifications noted in this
Data Sheet.
1. Frame readout mode
In this mode, all pixel signals are divided into two fields and output.
All pixel signals are read out independently, making this mode suitable for high resolution image captur ing.
2. High frame rate readout mode
Output is performed at 30 frames per second by reading out 4 pixels for every 12 ver tical pixels and adding
2 pixels in the hor izontal CCD.
The number of output lines is 258 lines.
This readout mode emphasizes processing speed over vertical resolution.
Mode name Frame rate Number of effective output lines
Frame readout mode
High frame rate readout
mode
AF1 mode
AF2 mode
NTSC mode
PAL mode
NTSC mode
PAL mode
NTSC mode
PAL mode
NTSC mode
PAL mode
5.0 frame/s
5.0 frame/s
30 frame/s
25 frame/s
60 frame/s
50 frame/s
120 frame/s
100 frame/s
1550 (Odd 775, Even 775)
1550 (Odd 775, Even 775)
258
258
117
145
33
47
Frame readout mode High frame rate readout mode
1st field 2nd field
13
12
11
10
9
8
7
6
5
4
3
1
2
V
OUT
R
Gb
R
Gb
R
R
Gb
Gb
R
R
Gb
Gr
B
Gr
B
Gb B
Gr
Gr
B
B
Gr
Gr
B
RGr
13
12
11
10
9
8
7
6
5
4
3
1
2
V
OUT
R
Gb
R
Gb
R
Gb
R
Gb
R
Gb
R
R
Gb
Gr
B
Gr
B
Gr
B
Gr
B
Gr
B
Gr
Gr
B
13
12
11
10
9
8
7
6
5
4
3
1
2
V
OUT
R
Gb
R
Gb
R
Gb
R
Gb
R
Gb
R
R
Gb
Gr
B
Gr
B
Gr
B
Gr
B
Gr
B
Gr
Gr
B
Note) Blacked out portions in the diagram indicate pixels which are not read out.
– 12 –
ICX412AQ
3. AF1 mode , AF2 mode
The AF modes increase the frame rate by cutting out a portion of the picture through high-speed elimination of
the top and bottom of the picture in high frame rate readout mode. AF1 allows 1/60s and 1/50s output, and
AF2 allows 1/120s and 1/100s output, so these modes are effective for raising the auto focus (AF) speed.
In addition, it differs from the ICX252AQ, the output line position and number of output lines are fixed. See the
timing specifications for the cut-out region.
Number of effective lines
in high frame rate
readout mode
258
Top
frame shift region
Cut-out region
Bottom
high-speed sweep region
– 13 –
ICX412AQ
Definition of standard imaging conditions
(1) Standard imaging condition I:
Use a pattern box (luminance: 706cd/m2, color temperature of 3200K halogen source) as a subject.
(Patter n for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR
cut filter and image at F5.6. The luminous intensity to the sensor receiving surface at this point is defined
as the standard sensitivity testing luminous intensity.
(2) Standard imaging condition II:
Image a light source (color temperature of 3200K) with a unifor mity of br ightness within 2% at all angles.
Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted
to the value indicated in each testing item by the lens diaphragm.
(3) Standard imaging condition III:
Image a light source (color temperature of 3200K) with a unifor mity of br ightness within 2% at all angles.
Use a testing standard lens (exit pupil distance –33mm) with CM500S (t = 1.0mm) as an IR cut filter. The
luminous intensity is adjusted to the value indicated in each testing item by the lens diagram.
1. G Sensitivity, sensitivity comparison
Set to the standard imaging condition I. After setting the electronic shutter mode with a shutter speed of
1/100s, measure the signal outputs (VGR, VGb, V R and VB) at the center of each Gr, Gb, R and B channel
screen, and substitute the values into the following formulas.
VG = (VGr + VGb)/2
Sg = VG ×[mV]
Rr = VR/VG
Rb = VB/VG
2. Saturation signal
Set to the standard imaging condition II. After adjusting the luminous intensity to 20 times the intensity with
the average value of the Gr signal output, 150mV, measure the minimum values of the Gr, Gb, R and B
signal outputs.
3. Smear
Set to the standard imaging condition III. With the lens diaphragm at F5.6 to F8, first adjust the average
value of the Gr signal output to 150mV. Measure the average values of the Gr signal output, Gb signal
output, R signal output and B signal output (Gra, Gba, Ra, Ba), and then adjust the luminous intensity to
500 times the intensity with the average value of the Gr signal output, 150mV.
After the readout clock is stopped and the charge drain is executed by the electronic shutter at the
respective H blankings, measure the maximum value (Vsm [mV]) independent of the Gr, Gb, R and B
signal outputs, and substitute the values into the following formula.
Sm = 20 × log
(
Vsm ÷××
)
[dB] (1/10V method conversion value)
1
10
1
500
Gra + Gba + Ra + Ba
4
100
30
– 14 –
ICX412AQ
4. Video signal shading
Set to the standard imaging condition III. With the lens diaphragm at F5.6 to F8, adjusting the luminous
intensity so that the average value of the Gr signal output is 150mV. Then measure the maximum value
(Gr max [mV]) and minimum value (Gr min [mV]) of the Gr signal output and substitute the values into the
f ollowing formula.
SHg = (Gr max – Gr min)/150 × 100 [%]
5. Dark signal
Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature of 60°C
and the device in the light-obstructed state, using the horizontal idle transfer level as a reference.
6. Dark signal shading
After measuring 5, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dar k
signal output and substitute the values into the following for mula.
∆Vdt = Vdmax – Vdmin [mV]
7. Line crawl
Set to the standard imaging condition II. Adjusting the luminous intensity so that the average value of the
Gr signal output is 150mV, and then insert R, G and B filters and measure the difference between G signal
lines (∆Glr, ∆Glg, ∆Glb [mV]) as well as the average value of the G signal output (Gar, Gag, Gab).
Substitute the values into the following for mula.
Lci = × 100 [%] (i = r, g, b)
8. Lag
Adjust the Gr signal output value generated by the strobe light to 150mV. After setting the strobe light so
that it strobes with the following timing, measure the residual signal amount (Vlag). Substitute the value
into the following formula.
Lag = (Vlag/150) × 100 [%]
Light
VD
V1A/V1B
Strobe light timing
Output
Vlag (lag)Gr signal output 150mV
∆Gli
Gai
– 15 –
ICX412AQ
Drive Circuit
Notes) Substrate bias control
1. The saturation signal level decreases when exposure is perfor med using the mechanical shutter,
so control the substrate bias.
2. A saturation signal level equivalent to that for continuous exposure can be assured by connecting
a 10kΩ grounding registor to the CCD CSUB pin.
Drive timing precautions
1. Blooming occurs in modes (high frame rate readout, etc.) that do not use the mechanical shutter,
so do not ground the connected 10kΩ resistor.
2. tf is slow, so the inter nally generated voltage VSUB may not drop to a sufficiently low level if the
substrate bias control signal is not set to high level 20ms before entering the exposure period
and the 10kΩ resistor connected to the CSUB pin is not grounded.
3. The blooming signal generated during exposure in mechanical shutter mode is swept by
providing two fields or more of idle transfer through ver tical register high-speed sweep transfer
from the time the mechanical shutter closes until sensor readout is performed. However, note that
the VL potential and the φSUB pin DC voltage sag at this time.
Substrate bias
control signal
V
SUB
Cont.
Mechanical
shutter mode
Substrate bias
φSUB pin voltage
GND
tr ≈ 2mstf ≈ 10ms Internally
generated
value V
SUB
XSUB
XV3
XSG3B
XSG3A
XV1
XSG1B
XSG1A
XV4
XV2
VSUB Cont.
Hφ2
Hφ1
φRG
0.1
0.1
0.1
0.1
1M
0.1
0.01
3.3/20V
0.1
4.7k
100k
CCD OUT
VR1 (10k)
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
CXD3400N
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
ICX412
(BOTTOM VIEW)
3.3/16V
1/35V
3.3V
–7.5V 15V
Hφ2
φRG
GND
VDD
Hφ2
Hφ1
VL
CSUB
φSUB
Hφ1
TEST
GND
VOUT
Vφ4
Vφ3A
Vφ3B
Vφ2
Vφ1A
TEST
Vφ1B
2SC4250
– 16 –
ICX412AQ
Drive Timing Char t (Ver tical Sequence) High Frame Rate Readout Mode →→
→→
→ Frame Readout Mode/Electronic Shutter Normal Operation
Note) The B and C output signals contain a blooming component and should therefore not be used.
Apply 20 or more electronic shutter pulses at the star t of exposure for the recording image.
If less than 20 pulses are applied, the electronic shutter may occur a discharge error.
VD
Act.
CCD
OUT
V1A
SUB
TRG
Mechanical
shutter
VSUB
Cont.
OPEN OPEN
CLOSE
V1B
V3A
V4
V2
V3B
A B C E FD
A signal output B signal output C signal output D signal output (ODD) D signal output (EVEN)
Output after frame
readout
E signal output F signal output
High frame rate readout mode High frame rate readout mode
Exposure
operation
Frame readout mode
– 17 –
ICX412AQ
Drive Timing Char t (Ver tical Sync) NTSC/PAL Frame Readout Mode
NTSC: 5.0 frame/s, PAL: 5.0 frame/s
Note) 2544H, However, 886H and 1772H in NTSC mode are 810clk, 885H and 1770H in PAL mode are 1104clk.
Exposure period All pixels output period
CCD
OUT
Mechanical
shutter
V
SUB
Cont.
OPEN OPEN
CLOSE
HD
VD
V4
V3A/B
V1A/B
V2
SUB
TRG
PAL
11
99 1010
9494
9797 9898
102102
876876
886885 887886
895894 896895
980979
982981
984983
988987
17621761
17721770 11
"a" "b""c""c"
NTSC
1
3
5
7
1
3
5
7
9
11
1547
1549
2
4
6
8
2
4
6
8
10
12
1548
1550
– 18 –
ICX412AQ
Drive Timing Chart (Readout) NTSC/PAL Frame Readout Mode
"a" Enlarged
NTSC: #97
PAL : #97 NTSC: #98
PAL : #98
NTSC: #982
PAL : #981 NTSC: #983
PAL : #982
2544
1
52
1272
1310
1196
1310
13481272
1158
1234
1348
1366
428
2544
1
52
428
2544
1
52
428
2544
1
52
428
H1
V1A/B
V2
V3A/B
V4
H1
V1A/B
V2
V3A/B
V4
"b" Enlarged
– 19 –
ICX412AQ
Drive Timing Chart (High-speed Sweep Operation) NTSC/PAL Frame Readout Mode
"c" Enlarged
1
38
239136clk = 94 line
52
38 38 38 38 38 38 38 38 38 38 38 38 38 38 38
52
38 38 38 38
#1 #2 #3 #4 #1560
HD
V1A/B
V2
V3A/B
V4
Note) In the period of high-speed sweep operation, the rising of input clock XV1A/B, XV2, XV3A/B and XV4 to vertical transfer clock dr iver CXD3400N should be delaye d
by 1 clock against the above timing char t.
– 20 –
ICX412AQ
Drive Timing Chart (Horizontal Sync) NTSC/PAL Frame Readout Mode
CLK
RG
SHP
SHD
V1A/B
V2
V3A/B
V4
H1
H2
SUB
1308
1 148
1
1
1
1
1
48
5
2544
52
376 428
28 456
1
465
110
186
114
1
11 152
76
114
38
1
1
1
1
1
114
190
190
68
72
Ignored pixel 4 bits Ignored pixel 4 bits
4 bits before horizontal sync
48 bits after horizontal sync
11
1
– 21 –
ICX412AQ
Drive Timing Chart (Vertical Sync) NTSC/PAL High Frame Rate Readout Mode
NTSC: 30 frame/s, PAL: 25 frame/s
Note) 2624fH, However, 286H and 287H in NTSC mode are 1455clk, 343H in PAL mode is 2592clk.
NTSC
PAL
255
260
287
1
9
10
15
255
260
287
1
9
10
15
255
260
343
1
9
10
15
255
260
343
1
9
10
15
VD
HD
V1A
V1B
V2
V3A
V3B
V4
CCD
OUT
1549
1544
1537
1532
1525
13
8
1
4
32
25
20 15
10
3
6
34
27
22
1546
1539
1534
1527
1549
1544
1537
1532
1525
13
8
1
4
32
25
20 15
10
3
6
34
27
22
1546
1539
1534
1527
"d" "d"
– 22 –
ICX412AQ
Drive Timing Char t (Readout) NTSC/PAL High Frame Rate Readout Mode
"d" Enlarged
NTSC
PAL
H1
V1A
V1B
V2
V3A
V3B
V4
1455
1
52
428
1196 1348
1462 1538
15921640
1158 1386
1272
1576 1656
1310 1424 1624 1672
1234 1608 1688
2592 NTSC
PAL 2624
1
52
428
2624
#2#1
1348
1500
– 23 –
ICX412AQ
Drive Timing Char t (Horizontal Sync) NTSC/PAL High Frame Rate Readout Mode, AF1 Mode, AF2 Mode
CLK
RG
SHP
SHD
V1A/B
V2
V3A/B
V4
H1
H2
SUB
1388
1
1
48
5
2624
52
456
124
140
156
172
188
204
220
236
252
268
284
300
316
332
348
364
380
396
412
428
444
460
476
492
508
28 536
1
545
68
Ignored pixel 4 bits Ignored pixel 4 bits
4 bits before horizontal sync
48 bits after horizontal sync
11
1
– 24 –
ICX412AQ
Drive Timing Chart (Vertical Sync) NTSC/PAL AF1 Mode
NTSC: 60 frame/s, PAL: 50 frame/s
Note) 2624fH, However, 143H and 144H in NTSC mode are 1383clk, 172H in PAL mode is 1296clk.
High-speed sweep period 11H Frame shift period 10H
"d" "d""e""f" "e""f"
HD
VD
CCD
OUT
V1A
V2
V3A
V4
V1B
V3B
NTSC
PAL
PAL
131159
142170
144172 11
99
1212
1515
131159
11 144172
142170
99
1212
1515
NTSC
1112
1117 1114
1119
1280
1285 1282
1287
46
421 423
428 430
433 435
440 442
421 423
428 430
433 435
440 442
46
1112
1117 1114
1119
1280
1285 1282
1287
46
421 423421 423
46
AF1 mode output signal
– 25 –
ICX412AQ
Drive Timing Char t (Ver tical Sync) NTSC/PAL AF2 Mode
NTSC: 120 frame/s, PAL: 100 frame/s
Note) 2624fH, However, 72H in NTSC mode is 1384clk, and 86H in PAL mode is 1960clk.
The frame rate in NTSC mode is longer than 1/120s by 0.15clk.
"
d
" "
d
""
h
""g""h" "g"
HD
VD
CCD
OUT
V1A
V2
V3A
V4
V1B
V3B
NTSC
PAL
PAL
8468
7185 7286
11
99
1919
2222
5468
11
7286 7185
99
1919
2222
NTSC
860
865 862
867
944
949 946
951
46
673 675
680 682
685 687
692 694
673 675
680 682
685 687
692 694
46
860
865 862
867
944
949 946
951
46
673 675673 675
46
AF2 mode output signal
High-speed sweep period 17H
Frame shift period 17H
– 26 –
ICX412AQ
Drive Timing Chart (High-speed Frame Shift Operation) NTSC/PAL AF1 Mode, AF2 Mode
AF1 mode 10 lines
AF2 mode 17 lines
#1 #2 AF1 mode #68
AF2 mode #110
68
52
100
52
HD
V1A/B
V2
V3A/B
V4
48 80 48 80 8048
80
48 80 48 80 48
80
48 80 48 80 48
48
48 80 48 80 80
84
1
"e" Enlarged
– 27 –
ICX412AQ
Drive Timing Chart (High-speed Sweep Operation) NTSC/PAL AF1 Mode, AF2 Mode
"f" Enlarged
AF1 mode 11 lines
AF2 mode 17 lines
#1 #2 AF1 mode #75
AF2 mode #116
68
1
52
100
52
HD
V1A/B
V2
V3A/B
V4
48 80 48 80 8048
80
48 80 48 80 48
80
48 80 48 80 48
48
48 80 48 80 80
84
– 28 –
ICX412AQ
Plactic package
Cover glass
Compressive strength
50N50N 1.2Nm
Torsional strength
Notes on Handling
1) Static charge prevention
CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following
protective measures.
a) Either handle bare handed or use non-chargeable gloves, clothes or material.
Also use conductive shoes.
b) When handling directly use an ear th band.
c) Install a conductive mat on the floor or working table to prevent the generation of static electricity.
d) Ionized air is recommended for discharge when handling CCD image sensors.
e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges.
2) Soldering
a) Make sure the package temperature does not exceed 80°C.
b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a 30W
soldering iron with a ground wire and solder each pin in less than 2 seconds. For repairs and remount,
cool sufficiently.
c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering
tool, use a thermal controller of the zero-cross On/Off type and connect it to ground.
3) Dust and dir t protection
Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and
dir t . Clean glass plates with the following operations as required, and use them.
a) Perfor m all assembly operations in a clean room (class 1000 or less).
b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should
dir t stick to a glass surface, blow it off with an air blower. (For dir t stuck through static electricity ionized
air is recommended.)
c) Clean with a cotton bud and ethyl alcohol if grease stained. Be careful not to scratch the glass.
d) Keep in a case to protect from dust and dir t. To prevent dew condensation, preheat or precool when
moving to a room with great temperature differences.
e) When a protective tape is applied before shipping, just before use remove the tape applied for
electrostatic protection. Do not reuse the tape.
4) Installing (attaching)
a) Remain within the following limits when applying a static load to the package. Do not apply any load
more than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to
limited por tions. (This may cause cracks in the package.)
b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the
package may fracture, etc., depending on the flatness of the bottom of the package. Therefore, for
installation, use either an elastic load, such as a spring plate, or an adhesive.
– 29 –
ICX412AQ
Structure A Structure B
Chip
Metal plate
(lead frame)
Package
Cross section of
lead frame
c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated
voltage value is indicated on the rear surf ace. Therefore, the adhesive should not be applied to this area,
and indicated values should be transferred to other locations as a precaution.
d) The notch of the package is used for directional index, and that can not be used for reference of fixing.
In addition, the cover glass and seal resin may overlap with the notch of the package.
e) If the leads are bent repeatedly and metal, etc., clash or rub against the package, the dust may be
generated by the fragments of resin.
f) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyano-
acrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives.
(reference)
5) Others
a) Do not expose to strong light (sun rays) for long periods, as color filters will be discolored. When high
luminous objects are imaged with the exposure level controlled by the electronic iris, the luminance of
the image-plane may become excessive and discoloring of the color filter will possibly be accelerated. In
such a case, it is advisable that taking-lens with the automatic-ir is and closing of the shutter dur ing the
power-off mode should be properly arranged. For continuous using under cr uel condition exceeding the
normal using condition, consult our company.
b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or
usage in such conditions.
c) Brown stains may be seen on the bottom or side of the package. But this does not affect the CCD
characteristics.
d) This package has 2 kinds of internal structure. However, their package outline, optical size, and strength
are the same.
The cross section of lead frame can be seen on the side of the package for structure A.
– 30 –
ICX412AQ
Sony Corporation
Package Outline Unit: mm
20 pin DIP
B
~
B
'
M
A
1
1
C
H
V
D
12.2
PACKAGE STRUCTURE
PACKAGE MATERIAL
LEAD TREATMENT
LEAD MATERIAL
PACKAGE MASS
DRAWING NUMBER
Plastic
GOLD PLATING
42 ALLOY
AS-B6-04(E)
0.95g
1. “A” is the center of the effective image area.
2. The two points “B” of the package are the horizontal reference.
The point “B'” of the package is the vertical reference.
3. The bottom “C” of the package, and the top of the cover glass “D”
are the height reference.
4. The center of the effective image area relative to “B” and “B'”
is (H, V) = (6.9, 6.0) ± 0.075mm.
5. The rotation angle of the effective image area relative to H and V is ± 1˚.
6. The height from the bottom “C” to the effective image area is 1.41 ± 0.10mm.
The height from the top of the cover glass “D” to the effective image area is 1.49 ± 0.15mm.
7. The tilt of the effective image area relative to the bottom “C” is less than 50µm.
The tilt of the effective image area relative to the top “D” of the cover glass is less than 50µm.
8. The thickness of the cover glass is 0.5mm, and the refractive index is 1.5.
9. The notches on the bottom of the package are used only for directional index, they must
not be used for reference of fixing.
~
~
1.7
11 20
1.7
10
13.8 ± 0.1
12.7 10
20 11
6.9
10.9
0.8
1.27 0.3
0.3
10.0 2.5
0˚ to 9˚
0.5 2.5
9.0 2.5
6.0
12.0 ± 0.1
0.25
1.7
1.7
0.8
0.5
2.9 ± 0.15
2.4
3.5 ± 0.3
