CoolSET®-F3R
ICE3RBR1765JZ
Off-Line SMPS Current Mode
Controller with integrated 650V
CoolMOS® and Startup cell
(frequency jitter Mode) in DIP-7
Never stop thinking.
Power Management & Supply
Version 2.0, 7 Jun 2013
Edition 2013-6-7
Published by
Infineon Technologies AG,
81726 Munich, Germany,
© 2013 Infineon Technologies AG.
All Rights Reserved.
Legal disclaimer
The information given in this docu ment shall in no event be regard ed as a guarantee of conditions or
characteristics. With respe ct to any examples or hints given herein, any typical valu es stated herein and/or any
information regarding the application of the device, Infineon Technologies her eby disclaims any and all warranties
and liabilities of an y kind, including without lim itation, warranties of non-infringement of intellec tual property rights
of any third party.
Information
For further inf or m at io n on t echnology, deliv e ry terms and conditions and prices, please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements, components may contain dangerous subst ances. For information on the types in
question, please c ontact your nearest Infineon Technologies Office.
Infineon Technologies Components may be used in life-suppo rt devices or sy stems only with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system o r to a ffect the safe ty or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain
and/or protect human life. If they fail, it is rea sonable to as sum e that the health of th e user or o ther pers ons may
be endangered.
For questions on technolog y, delivery and prices please contact the Infin eon Technologies Offic es in Germany or
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CoolMOS®, CoolSET® are trademarks of Infineon Technologies AG.
ICE3RBR1765JZ
Revision History: 2013-6-7 Version 2.0
Previous Version: 0.0
Page Subjects (major changes since last revision)
3 add applications
Type Package Marking VDS FOSC RDSon1)
1) typ @ Tj=25°C
230VAC ±15%2)
2) Calculated maximum input power rating at Ta=50°C, Ti=125°C and without copper area as heat sink. Refer to input power curve for other Ta.
85-265 VAC2)
ICE3RBR1765JZ PG-DIP-7 3RBR1765JZ 650V 65kHz 1.70 44.5W 29.5W
ICE3RBR1765JZ
Version 2.0 3 7 Jun 2013
Off-Line SMPS Current Mode Controller with
integrated 650V CoolMOS® and Startup cell
(frequency jitter Mode) in DIP-7
P-DIP-7-1
PG-DIP-7
Description
ICE3RBR1765JZ (ICE3RBRxx65JZ series) is modified
from ICE3BRxx65J in DIP-7 package. It has more robust
design and can work to -40°C. The outstanding
performance includes BiCMOS technology, active burst
mode, built-in frequency jitter, soft gate driving,
propagation delay compensation, built-in soft start time,
built-in blanking time and extendable blanking time for
over load pr otection , externa l auto-restart enable feature,
etc.
Applications
• Adapter/Charger
• Blue Ray/DVD player, Set- top Box, Digital Photo
Frame
• Auxiliary power supply for Server, PC, Printer, TV,
Home theater/Audio System, White Goo ds, etc
Product Highlights
• Active Burst Mode to reach the lowest Standby Power
Requirements < 50mW
• Auto Restart protection for overload, overtemperature, overvoltage
• External auto-restart enable function
• Built-in soft start and blanking window
• Extendable blanking Window for high load jumps
• Built-in frequency jitter and soft driving for low EMI
• Low Operating temperature down to -40°C
• Green Mould Compound
• Pb-free lead plating; RoHS compliant
Features
• 650V avalanche rugged CoolMOS® with built-in
Startup Cell
• Active Burst Mode for lowest Standby Power
• Fast load jump response in Active Burst Mode
• 65kHz internally fixed switching frequency
• Auto Restart Protection Mode for Overload, Open
Loop, VCC Undervoltage, Overtemperature &
Overvoltage
• Built-in Soft Start
• Built-in blanking window with extendable blank ing
time for short duration high current
• External auto-restart enable pin
• Max Duty Cycle 75%
• Overall tolerance of Current Limiting < ±5%
• Internal PWM Leading Edge Blanking
• BiCMOS technology provide wide VCC ra nge
• Built-in Frequency jitter and soft driving for low EMI
CVCC
CBulk Converter
DC Output
+
Snubber
Power M anagem ent
PW M C ontroller
Current Mode
85 ... 270 VAC
Typical Application
RSense
BA
FB
GND Ac tive Bu r s t Mo d e
A uto Resta rt Mode
Control
Unit
-
CS
VCC
Startup Cell
Precise Low Tolerance Peak
Current Lim itation
Drain
CoolSET®-F3R
(Jitter M ode)
CoolMOS®
ICE3RBR1765JZ
Table of Contents Page
Version 2.0 4 7 Jun 2013
1 Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.1 Pin Configuration wit h PG-DIP-7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.2 Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
2 Representative Blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.2 Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.3 Improved Current Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.3.1 PWM-OP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.3.2 PWM-Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.4 Startup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.5 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.5.1 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.5.2 PWM-Latch FF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.5.3 Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.6 Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.6.1 Leading Edge Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.6.2 Propagation Delay Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.7 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.7.1 Basic and Extendable Blanking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.7.2 Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.7.2.1 Entering Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.7.2.2 Working in Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.7.2.3 Leaving Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.7.3 Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
3.7.3.1 Auto Restart mode with extended blanking time . . . . . . . . . . . . . . . . .17
3.7.3.2 Auto Restart without extended blanking time . . . . . . . . . . . . . . . . . . .18
4 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.3 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.3.1 Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4.3.2 Internal Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.3.3 PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.3.4 Soft Start time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.3.5 Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.3.6 Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.3.7 CoolMOS® Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
5 Typical CoolMOS® Performance Characteristic . . . . . . . . . . . . . . . . . . .24
ICE3RBR1765JZ
Version 2.0 5 7 Jun 2013
6 Input Power Curve . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
7 Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
8 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
9 Schematic for recommended PCB layout . . . . . . . . . . . . . . . . . . . . . . . .29
Version 2.0 6 7 Jun 2013
ICE3RBR1765JZ
Pin Configuration and Functionality
1 Pin Configuration and Functionality
1.1 Pin Configuration with PG-DIP-7
Figure 1 Pin Configuration PG-DIP-7 (top view)
1.2 Pin Functionality
BA (extended Blanking & Auto-restart enable)
The BA pin combines the functions of extendable
blanking time for over load protection and the external
auto-restart enable. The extendable blanking time
function is to extend the built-in 20 ms blank ing time by
adding an external capacitor at BA pin to ground. The
external auto-restart enable function is an external
access to stop the gate switching and force the IC enter
auto-restart mode. It is triggered by pulling down the
BA pin to less than 0.33V.
FB (Feedback)
The information about the regulation is prov ided by the
FB Pin to the internal Protection Unit and to the inte rnal
PWM-Comparator to control the duty cycle. The FB-
Signal is the only control signal in case of light load at
the Active Burst Mode.
CS (Current Sense)
The Current Sense pin senses the voltage developed
on the series resistor inserted in the source of the
integrated CoolMOS® If voltage in CS pin reaches the
internal threshold of the Current Limit Comparator, the
Driver output is immediately switched off. Furthermore
the current information is provided for the PWM-
Comparator to realize the Current Mode.
Drain (Dra in of integrated Co olMOS®)
Drain pin is the connection to the Drain of the
integrated CoolMOS®.
VCC (Power Supply)
VCC pin is the positive supply of the IC. The operating
range is between 10 .5V and 25V.
GND (Ground)
GND pin is the ground of the controller.
Pin Symbol Function
1 BA extended Blanking & Auto-restart
enable
2 FB FeedBack
3 CS Current Sense/
650V1) CoolMOS® Source
1) at Tj=110°C
4 n.c. not connected
5Drain
650V1) CoolMOS® Drain
6 n.c. Not connected
7 VCC Controller Supply Voltage
8 GND Controller GrouND
Package PG-DIP-7
1
7
8
4
3
2
5
GNDBA
FB
CS
VCC
n.c. Drain
ICE3RBR1765JZ
Representative Blockdiagram
Version 2.0 7 7 Jun 2013
2 Representative Blockdiagram
Figure 2 Representative Blockdiagram
Internal Bias Voltage
Reference
Oscillator
Duty Cycle
max
x3.2
Current Limiting
PWM OP
Current Mode
Soft Start
C2
C1
20.5V
25.5V
R
FB
Power Management
CBK
CVCC
85 ... 270 VAC CBulk
+
Converter
DC Output
VOUT
PWM
Comparator
C3
4.0V
C4
4.0V
Gate
Driver
0.72
Clock
RSense
10k
D1
C6a
3.0V
C5
1.35V C10
R
S
Q
Auto
Restart
Mode
&
G7
&
G5
&
G9
1
G8
&
G1
Thermal Shutdown
0.9V
S1
1
Power-Down
Reset
CS
BA GND
VCC
C7
C8
FB
PWM
Section
Control Unit
FF1
C12
&
0.34V
Leading
Edge
Blanking
220ns
25k
2pF
5.0V
G10
1pF
Propagation-Delay
Compensation
5.0V
Undervoltage Lockout
Vcsth
G2
-
ICE3RBRxx65J / CoolSET
®-F3R ( Jitter Mode )
Snubber
VCC Drain
CoolMOS
®
Startup Cell
C6b
&
G6
3.5V
&
G11
Active Burst
Mode
0.6V
10.5V
18V
#1
# : optional external components;
#1 : C
BK is used to extend the Blanking Time
#2 : TAE is used to enable the external Auto-restart feature
Freq. jitter
20ms
Blanking
Time
20ms Blanking
Time
120us Blanking Time
Soft
Start
Block
Soft-Start
Comparator
Spike
Blanking
30us
T2
3.25k 5.0V
T1
T3 0.6V
IBK
VCC
Auto-restart
Enable
Signal
TAE
C9
0.33V
1ms
counter
T
j
>130°C
#2
Version 2.0 8 7 Jun 2013
ICE3RBR1765JZ
Functional Description
3 Functional Description
All values which are used in the functional description
are typical values. For calculating the worst cases the
min/max values which can be found in section 4
Electrical Characteristics have to be considered.
3.1 Introduction
ICE3RBR1765JZ (ICE3RBRxx65JZ series) is derived
from ICE3BRxx65J in DIP-7 package. It has more
robust design and can work to -40°C.
A high voltage Startup Cell is integrated into the IC
which is switched off once the Undervoltage Lockout
on-threshold of 18V is exceeded. This Startup Cell is
part of the integrated C oolMOS®. The external startup
resistor is no longer necessary as this Startup Cell is
connected to the Drain. Power losses are therefore
reduced. This increases the efficiency under light load
conditions drastically.
The particular features are the active burst mode,
propagation delay compensation, modulated gate
driving, auto-restart protection for Vcc overvoltage,
over temperature, over load, open loop, built-in soft
start, blanking window and frequency jitter. It provides
the flexibility to increase th e blanking window by simply
addition of a capacitor in BA pin. In order to further
increase the flexibility of the protection feature, an
external auto-restart enable features are added.
The intelligent Ac tive Burst Mode can effectively obtain
the lowest Standby Power at light load and no load
conditions. After entering the burst mode, there is still a
full control of the power conversion to the output
through the optocoupler, that is used for the normal
PWM control. The res ponse on load jumps is o ptimized
and the voltage ripple on Vout is minimized. The Vout is
on well controlled in this mode.
The usually external connected RC-filter in the
feedback line after the optocoupler is integrated in the
IC to reduce the external part count.
Adopting the BiCMOS technology, it can increase the
design flexibility as the Vcc voltage range is increased
to 25V.
It has a built-in 20ms soft start function.
There are 2 modes of blanking time for high load
jumps; the basic mode and the extendable mode. The
blanking time for the basic mode is set at 20ms while
the extendable mode will increas e the blanking time by
adding an external cap acitor at the BA pin in addition to
the basic mode blank ing time. During this blanking time
window the sys tem can give the maximum power to the
loading.
In order to increase the robustness and safety of the
system, the IC provides Auto Restart protection. The
Auto Restart Mode reduces the average power
conversion to a minimum level under unsafe operating
conditions. This is necessary for a prolonged fault
condition which cou ld otherwise lead to a d estruction of
the SMPS over time. Once the malfunction is removed,
normal operation is automatically retained after the
next Start Up Phase. To make the protection more
flexible, an external auto-restart enable pin is prov ided.
When the pin is triggered, the switching pulse at gate
will stop and the IC enters the auto-restart mode after
the pre-defined spike blanking time.
The internal precise peak current control reduces the
costs for the transforme r and the secondary diode. Th e
influence of the change in the input voltage on the
maximum power limitation can be avoided together
with the integrated Propagation Delay Compensation.
Therefore the maximum power is nearly independent
on the input voltage, which is required for wide range
SMPS. Thus there is no need for the over-sizing of the
SMPS, e.g. the transformer and the output diode.
Furthermore, it implements the frequency jitter mod e to
the switching clock such that the EMI noise will be
effectively reduced.
3.2 Power Management
Figure 3 Power Management
The Undervoltage Lockout monitors the external
supply voltage VVCC. When the SMPS is plugged to the
main line the internal Startup Cell is biased and starts
to charge the external capacitor CVCC which is
connected to the VCC pin. This VCC charge current is
Internal Bias
Voltage
Reference
Power Management
5.0V
Undervoltage Lockout
18V
10.5V
Power-Down Reset
Ac tive B urst
Mode
Auto R esta rt
Mode
Startup Cell
VCCDrain
CoolMOS®
Soft Start block
ICE3RBR1765JZ
Functional Description
Version 2.0 9 7 Jun 2013
controlled to 0.9mA by the Startup Cell. W hen the VVCC
exceeds the on-threshold VCCon=18V the bias circuit
are switched on. Then the Startup Cell is switched off
by the Undervoltage Lockout and therefore no power
losses present due to the connection of the Startup Cell
to the Drain voltage. To avoid uncontrolled ringing at
switch-on, a hysteresis start up voltage is implemented.
The switch-off of the controller can only take place
when VVCC falls below 10.5V after normal operation
was entered. The maximum current consumption
before the controller is activated is about 150μA.
When VVCC falls below the off-threshold VCCoff=10.5V,
the bias circuit is switched off an d the soft start counte r
is reset. Thus it is ensured that at every startup cycle
the soft start starts at zero.
The internal bias circuit is switched off if Auto Restart
Mode is entered. The current consumption is then
reduced to 150μA.
Once the malfunction condition is removed, this block
will then turn back on. The recovery from Auto Restart
Mode does not require re-cycling the AC line.
When Active Burst Mode is entered, the inte rnal Bias is
switched off most of the time but the Voltage Reference
is kept alive in order to reduce the current consumption
below 450μA.
3.3 Improved Current Mode
Figure 4 Current Mode
Current Mode me ans the duty cycle is contro lled by the
slope of the primary c urrent. This is done by comparing
the FB signal with the amplified current sense signal.
Figure 5 Pulse Width Modulation
In case the amplified current sense signa l exceeds the
FB signal the on-time Ton of the driver is finished by
resetting the PWM-Latch (see Figure 5).
The primary current is sensed by the external series
resistor RSense inserted in the source of the integrated
CoolMOS®. By means of Current Mode regulation, the
secondary output voltage is insensitive to the line
variations. The current waveform slope will change with
the line variation, which controls the duty cycle.
The external RSense allows an individual adjustment of
the maximum source current of the integrated
CoolMOS®.
To improve the Current Mode during light load
conditions the amplified current ramp of the PWM-OP
is superimposed on a voltage ramp, which is built by
the switch T2, the voltage source V1 and a resistor R1
(see Figure 6). Every tim e the osc illato r shuts down for
maximum duty cycle li mitation the switch T2 is closed
by VOSC. When the oscillator triggers the Gate Driver,
T2 is opened so that the voltage ramp can start.
In case of light load the amplified current ramp is too
small to ensure a stable regulation. In that case the
Voltage Ramp is a well defined signal for the
comparison with the FB-signal. The duty cycle is then
controlled by the slope of the Voltage Ramp.
By means of the time delay circuit which is triggered by
the inverted VOSC signal, the Gate Driver is switched-off
until it reaches approximately 156ns delay time (see
Figure 7). It allows the duty cycle to be reduced
continuously till 0% by decreasing VFB below that
threshold.
t
FB
Amplified C urrent Signal
Ton
t
0.67V
Driver
ICE3RBR1765JZ
Functional Description
Version 2.0 10 7 Jun 2013
Figure 6 Improved Current Mode
Figure 7 Light Load Conditions
3.3.1 PWM-OP
The input of the PWM-OP is applied over the internal
leading edge blanking to the external sense resistor
RSense connected to pin CS. RSense conve rts the sourc e
current into a sense voltage. The sense voltage is
amplified with a gain of 3.3 by PWM OP. The output of
the PWM-OP is connected to the voltage source V1.
The voltage ramp with the superimposed amplified
current signal is fed into the positive inputs of the PWM-
Comparator C8 and the Soft-Start-Comparator (see
Figure 6).
3.3.2 PWM-Comparator
The PWM-Comparator compares the sensed current
signal of the integrated CoolMOS® with the feedback
signal VFB (see Figure 8). V FB is crea ted by a n external
optocoupler or external transistor in combination with
the internal pull-up resistor RFB and provides the load
information of the feedback circuitry. When the
amplified current signal of the integrated CoolMOS®
exceeds the signal VFB the PWM-Comparator s witches
off the Gate Driver.
Figure 8 PWM Controlling
PW M OP
0.67V
10kΩ
Oscillator
C8
T2R1
FB
PWM-Latch
V1
G a te D rive r
Voltage Ramp
VOSC
Soft-Start Comparator
time delay
circuit (156ns)
PW M Comp arator
X3.3
t
t
VOSC
0.67V
FB
t
max.
Duty Cycle
Gate Driver
Voltage Ramp
156ns time delay
X3.3
PWM OP
Improved
Current Mode
PWM Comparator
CS
Soft-Start Comparator
5V
C8
0.67V
FB
Optocoupler
RFB
PWM-Latch
ICE3RBR1765JZ
Functional Description
Version 2.0 11 7 Jun 2013
3.4 Startup Phase
Figure 9 Soft St art
In the Startup Phase, the IC provides a Soft Start
period to control the primary current by means of a duty
cycle limitation. The Soft Start function is a built-in
function and it is controlled by an internal counter.
.
Figure 10 Soft Start Phase
When the VVCC exceeds the on-threshold voltage, the
IC starts the Soft Start mode (s ee Figure 10).
The function is realized by an internal Soft Start
resistor, an current sink and a counter. And the
amplitude of the current sink is controlled by the
counter (see Figure 11).
Figure 11 Soft Start Circuit
After the IC is switched on, the VSFOFTS voltage is
controlled such that the voltage is increased step-
wisely (32 steps) with the increase of the counts. The
Soft Start counter would send a signal to the current
sink control in every 600us such that the current sink
decrease gradually and the duty ratio of the gate drive
increases gradually. The Soft Start will be finished in
20ms (TSoft-Start) after the IC is switched on. At the end
of the Soft Start period, the current sink is switched off.
Figure 12 Gate drive signal under Soft-Start Phase
So ft -Sta r t
Comparator
Soft Start
&
G7
C7 Ga te Dr iv e r
0.67V
x3.3
PW M OP CS
S oft Sta rt
counter
S oft Sta rt
Soft Start finish
SoftS
VSoftS
VSoftS2
VSoftS1
5V
RSoftS
SoftStart
Counter
I
2I
4I
SoftS
8I
32I
t
VSOFTS32
VSoftS
Gate
Driver
t
tSoft-Start
ICE3RBR1765JZ
Functional Description
Version 2.0 12 7 Jun 2013
Within the soft start period, the duty cycle is increasing
from zero to maximum gradually (see Figu re 12).
In addition to Start-Up, Soft-Start is also activated at
each restart attempt during Auto Restart.
Figure 13 Start Up Phase
The Start-Up time TStart-Up before the converter output
voltage VOUT is settled, must be shorter than the Soft-
Start Phase TSoft-Start (s ee Figure 13).
By means of Soft-Start there is an effective
minimization of current and voltage stresses on the
integrated CoolMOS®, the clamp circuit and the output
overshoot and it helps to prevent saturation of the
transformer during Sta rt-Up.
3.5 PWM Section
Figure 14 PWM Section Block
3.5.1 Oscillator
The oscillator generates a fixed frequency of 65KHz
with frequency jittering of ±4% (which is ±2.6KHz) at a
jittering period of 4ms.
A capacitor, a current source and current sink which
determine the frequency are integrated. In order to
achieve a very accurate switching frequency, the
charging and discharging current of the implemented
oscillator capacitor are internally trimmed. The ratio of
controlled charge to discharge current is adjusted to
reach a maximum duty cycle limitation of Dmax=0.75.
Once the Soft Start period is over and when the IC goes
into normal operating mode, the switchin g frequency of
the clock is varied by the control signal from the Soft
Start block. Then the switching frequency is varied in
range of 65KHz ± 2.6KHz at period of 4ms.
3.5.2 PWM-Latch FF1
The output of the oscillator block provides continuous
pulse to the PWM-Latch which turns on/off the
integrated CoolMOS®. After the PWM-Latch is set, it is
reset by the PWM comparator, the Soft Start
comparator or the Current -Limit comparator. When it is
in reset mode, the output of the driver is shut down
immediately.
t
t
VSoftS
t
VSOFTS32
4.0V
tSoft-Start
VOUT
VFB
VOUT
tStart-Up
Oscillator
Duty Cycle
max
Gate Driver
0.75
Clock
&
G9
1
G8
PWM Section
FF1
R
S
Q
Soft Start
Comparator
PWM
Comparator
Current
Limiting
CoolMOS®
Gate
Frequency
Jitter
Soft Start
Block
ICE3RBR1765JZ
Functional Description
Version 2.0 13 7 Jun 2013
3.5.3 Gate Driver
Figure 15 Gate Driver
The driver-stage is optimized to minimize EMI and to
provide high circuit efficiency. The switch on speed is
slowed down before it reaches the integrated
CoolMOS® turn on threshold. That is a slope control of
the rising edge at the output of the driver (see Figure
16).
Figure 16 Gate Rising Slope
Thus the leading switch on spike is minimized.
Furthermore the driver circuit is designed to eliminate
cross conduction of the outpu t stage.
During power up, when VCC is b elow the undervoltage
lockout threshold VVCCoff, the output of the Gate Driver
is set to low in order to disable power transfer to the
secondary side.
3.6 Current Limiting
Figure 17 Current Limiting Block
There is a cycle by cycle peak current limiting operation
realized by the Current-Limit comparator C10. The
source current of the integrated CoolMOS® is sensed
via an external sense resistor RSense. By means of
RSense the source current is transformed to a sense
voltage VSense which is fed into the CS pin. If the voltage
VSense exceeds the internal threshold voltage Vcsth, the
comparator C10 immediately tu rns off the gate drive by
resetting the PWM Latch FF1.
A Propagation Delay Compensation is added to
support the immediate shut down of the integrated
CoolMOS® with very short propagation delay. Thus the
influence of the AC input voltage on the maximum
output power can be reduced to minimal.
In order to prevent the current limit from distortions
caused by leading edge spikes, a Leading Edge
Blanking is integrated in the current sense path for the
comparators C10, C12 and the PWM-OP.
The output of comparator C12 is activated by the Gate
G10 if Active Burst Mode is entered. When it is
activated, the current limiting is reduced to 0.34V. This
voltage level determines the maximum power level in
Active Burst Mode.
VCC
1
PWM-Latch
CoolMOS®
Gate Driver
Gate
t
(internal)
VGate
5V
ca. t = 130ns
Current Limiting
C10
C12
&
0.34V
Leading
Edge
Blanking
220ns
G10
Pr o p a ga tio n-De lay
Compensation
Vcsth
A c ti ve Burs t
Mode
PWM Latch
FF1
10kD1
1pF
PWM-OP
CS
ICE3RBR1765JZ
Functional Description
Version 2.0 14 7 Jun 2013
3.6.1 Leading Edge Blanking
Figure 18 Leading Edge Blanking
Whenever the integrated CoolMOS® is switched on, a
leading edge spike is generated due to the primary-
side capacitances and reverse recovery time of the
secondary-s ide rectifier. This spike can cause th e gate
drive to switch off unintentionally. In order to avoid a
premature termin ation of the switching pulse, this spike
is blanked out with a time constant of tLEB = 220ns.
3.6.2 Propagation Delay Compensation
In case of over-current detection, there is always
propagation delay to switch off the integrated
CoolMOS®. An overshoot of the peak current Ipeak is
induced to the delay, which depends on the ratio of dI/
dt of the peak current (see Figure 19).
Figure 19 Current Limiting
The overshoot of Signal2 is larger than of Signal1 due
to the steeper rising waveform. This change in the
slope depends on the AC input voltage. Propagation
Delay Compensation is integrated to reduce the
overshoot due to dI/dt of the rising primary current.
Thus the propagation delay time between exceeding
the current sense threshold Vcsth and the switching off
of the integrated CoolMOS® is compensated over
temperature within a wide range. Current Limiting is
then very accurate.
For example, Ipeak = 0.5A with RSense = 2. The current
sense threshold is set to a static voltage level Vcsth=1V
without Propagation Delay Compensation. A current
ramp of dI/dt = 0.4A/µs, or dVSense/dt = 0.8V/µs, and a
propagation delay time of tPropagation Delay =180ns leads
to an Ipeak overshoot of 14.4%. With the propagation
delay compensation, the overshoot is only around 2%
(see Figure 20).
Figure 20 Overcurrent Shutdown
The Propagation Delay Compensation is realized by
means of a dynamic thres hold voltage Vcsth (see Figure
21). In case of a steeper slope the switch off of the
driver is earlier to compensate the delay.
Figure 21 Dynamic Voltage Threshold Vcsth
t
VSense
Vcsth tLEB = 220ns
0,9
0,95
1
1,05
1,1
1,15
1,2
1,25
1,3
0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2
with compensation without compensation
dt
dVSense s
V
μ
Sense
V
V
t
Vcsth
VOSC
Signal1 Signal2
VSense Propagation Delay
m ax. Duty Cycle
off tim e
t
ICE3RBR1765JZ
Functional Description
Version 2.0 15 7 Jun 2013
3.7 Control Unit
The Control Unit c ontains the functions fo r Active Burst
Mode and Auto Restart Mode. The Active Burst Mode
and the Auto Restart Mode both have 20ms internal
Blanking Time. For the Auto Restart Mode, a further
extendable Blanking Time is achieved by adding
external capacitor at BA pin. By means of this Blanking
Time, the IC avoids entering into these two modes
accidentally. Furthermore those buffer time for the
overload detection is very useful for the application that
works in low current but requires a short duration of
high current occasionally.
3.7.1 Basic and Extendable Blanking Mode
Figure 22 Basic and Extendable Blanking Mode
There are 2 kinds of Blanking mode; basic mode and
the extendable mode. The basic mode is just an
internal set 20ms blanking time while the extendable
mode has an extra blanking time by connecting an
external capacitor to the BA pin in addition to the pre-
set 20ms blanking time. For the extendable mode, the
gate G5 is blocked even though the 20ms blanking time
is reached if an external capacitor CBK is added to BA
pin. While the 20ms bla nking time is passed, the switch
S1 is opened by G2 . Then the 0.9V clamped v oltage at
BA pin is charged to 4.0V through the internal IBK
constant current. G5 is enabled by comparator C3.
After the 30us spike blanking time, the Auto Restart
Mode is activated.
For example, if CBK = 0.22uF, IBK = 13uA
Blanking time = 20ms + CBK x (4.0 - 0.9) / IBK = 72ms
In order to make the startup properly, the maximum CBK
capacitor is restricted to less than 0.65 uF.
The Active Burst Mode has basic blanking mode only
while the Auto Restart Mod e has both the basic and the
extendable blanking mod e.
3.7.2 Active Burst Mode
The IC enters Active Burst Mode under low load
conditions. With the Active Burst Mode, the efficiency
increases significantly at lig ht load condition s while still
maintaining a low ripple on VOUT and a fast response on
load jumps. During Active Burst Mode, the IC is
controlled by the FB signal. Since the IC is always
active, it can be a very fast response to the quick
change at the FB signal. The Start up Cell is kept OFF
in order to minimize the power loss.
Figure 23 Active Burst Mode
The Active Burst Mode is located in the Control Unit.
Figure 23 shows the related components.
3.7.2.1 Entering Active Burst Mode
The FB signal is kept monitoring by the comparator C5.
During normal operation, the internal blanking time
counter is reset to 0. Once the FB signal falls below
1.35V, it starts to count. Whe n the counter rea ch 20ms
C3
4.0V
C4
4.0V
C5
1.35V
&
G5
&
G6
0.9V
S1 1
G2
Control Unit
Active
Burst
Mode
Auto
Restart
Mode
5.0V
BA
FB
CBK
20ms
Blanking
Time
Spike
Blanking
8.0us
#
IBK
20ms
Blanking
Time
C4
4.0V
C6a
3.5V
C5
1.35V
FB
Control Unit
Active
Burst
Mode
Internal Bias
&
G10
Current
Limiting
C6b
3.0V
&
G11
20 ms
Blanking
Time
&
G6
ICE3RBR1765JZ
Functional Description
Version 2.0 16 7 Jun 2013
and FB signal is still below 1.35V, the system enters
the Active Burst Mode. This time window prevents a
sudden entering into the Active Burst Mode due to
large load jumps.
After entering Active Burst Mode, a burst flag is set and
the internal bias is switched off in order to reduce the
current consumption of the IC to approx. 450uA.
It needs the application to enforce the VCC voltage
above the Undervoltage Lockout level of 10.5V such
that the Startup Cell will not be switched on
accidentally. Or otherwise the power loss will increase
drastically. The minimum VCC level during Active Burst
Mode depends on the load condition and the
application. The lowest VCC level is reached at no load
condition.
3.7.2.2 Working in Active Burst Mode
After entering the Active Burst Mode, the FB voltage
rises as VOUT starts to decrease, which is due to the
inactive PWM section. The comparator C6a monitors
the FB signal. If the voltage level is larger than 3.5V, the
internal circuit will be activated; the Internal Bias circuit
resumes and starts to provide switching pulse. In
Active Burst Mode the gate G10 is released and the
current limit is reduced to 0.34V, which can reduce the
conduction loss and the audible noise. If the load at
VOUT is still kept unchanged, the FB signal will drop to
3.0V. At this level the C6b deactivates the internal
circuit again by switching off the internal Bias. The gate
G11 is active again as the burst flag is set after entering
Active Burst Mode. In Active Burst Mode, the FB
voltage is changing like a saw too th between 3.0V and
3.5V (see figu re 24).
3.7.2.3 Leaving Active Burst Mode
The FB voltage will increase immediately if there is a
high load jump. This is observed by the comparator C4.
Since the c urrent limit is app. 34% during Active Burst
Mode, it needs a ce rtain load jump to rise the FB signa l
to exceed 4. 0V. At that time the co mparat or C4 rese ts
the Active Burst Mode control which in turn blocks the
comparator C12 by the gate G10. The maximum
current can then be resumed to stabilize the VOUT.
Figure 24 Signals in Active Burst Mode
1.35V
3.5V
4.0V
VFB
t
t
0.34V
1.03V
VCS
10.5V
VVCC t
t
450uA
IVCC
t
2.5mA
VOUT
t
20ms Blanking Time
C urre nt lim it le v e l
during Active Burst
Mode
3.0V
Entering
A ct ive Burst
Mode
Leaving
A c tiv e Bur s t
Mode
Blanking Timer
ICE3RBR1765JZ
Functional Description
Version 2.0 17 7 Jun 2013
3.7.3 Protection Modes
The IC provides Auto Restart Mode as the protection
feature. Auto Restart mode can prevent the SMPS from
destructive states. The following table shows the
relationship between possible system failures and the
corresponding protection modes.
Before entering the Auto Restart protection mode,
some of the protections can have extended blanking
time to delay the protection and some needs to fast
react and will go straight to the protection. Overload
and open loop protection are the one can have
extended blanking time while Vcc Overvoltage, Over
temperature, Vcc Undervoltage, short opto-coupler
and external auto restart enable will go to protection
right away.
After the system enters the Auto-restart mode, the IC
will be off. Since there is no more switching, the Vcc
voltage will drop. When it hits the Vcc turn off threshold,
the start up cell will turn on and the Vcc is charged by
the startup cell current to Vcc turn on thresh old. The IC
is on and the startup cell will turn off. At this stage, it will
enter the startup phase (soft start) with switching
cycles. After the Start Up Phase, the fault condition is
checked. If the fault condition pers ists, the IC will go to
auto restart mode again. If, otherwise, the fault is
removed, normal operation is re sumed.
3.7.3.1 Auto Restart mode with extended
blanking time
Figure 25 Auto Restart Mode
In case of Overload or Open Loop, the FB exceeds
4.0V which will be observed by comparator C4. Then
the internal blanking counter starts to count. When it
reaches 20ms, the switch S1 is released. Then the
clamped voltage 0.9V at VBA ca n increase. When there
is no external capacitor CBK connected, the VBA will
reach 4.0V immedia tely. When bo th the input signals at
AND gate G5 is positive, the Auto Restart Mode will be
activated after the extra spike blanking time of 30us is
elapsed. However, when an extra blanking time is
needed, it can be achieved by adding an external
capacitor, CBK. A constant current source of IBK will start
to charge the capacitor CBK from 0.9V to 4.0V after the
switch S1 is released. The charging time from 0.9V to
4.0V are the extendable bl anking time . If CBK is 0.22uF
and IBK is 13uA, the extendable blan king time is around
52ms and the total bla nking time is 72ms. In combin ing
the FB and blanking time, there is a blanking window
generated which prevents the system to enter Auto
Restart Mode due to large load jumps.
VCC Overvoltage Auto Restart Mode
Overtemperature Auto Restart Mode
Overload Auto Restart Mode
Open Loop Auto Restart Mode
VCC Undervoltage Auto Restart Mode
Short Optocoupler Auto Restart Mode
Auto restart enable Auto Restart Mode
C3
4.0V
C4
4.0V
&
G5
0.9V
S1 1
G2
C ontr ol Unit
Auto
Restart
Mode
5.0V
BA
FB
CBK
Spike
Blanking
8.0us
#
IBK
20ms
Blanking
Time
ICE3RBR1765JZ
Functional Description
Version 2.0 18 7 Jun 2013
3.7.3.2 Auto Restart without ex tended blanking
time
Figure 26 Auto Restart mod e
There are 2 modes of VCC overvoltage protection; one
is during soft start and the other is at all conditions.
The first one is VVCC voltage is > 20.5V and FB is > 4.0V
and during soft_start period and the IC enters Auto
Restart Mode. The VCC voltage is observed by
comparator C1 and C4. The fault conditions are to
detect the abnormal operating during start up such as
open loop during light load start up, etc. The logic can
eliminate the possible of entering Auto R es t a rt mode if
there is a small voltage overshoots of VVCC during
normal operating.
The 2nd one is VVCC >25.5V and last for 120us and the
IC enters Auto Restart Mode. This 25.5V Vcc OVP
protection is inactivated during burst mode.
The Thermal Shutdown block monitors the junction
temperature of the IC. After detecting a junction
temperature higher than 130°C, the Auto Restart Mode
is entere d.
In case the pre-defined auto-restart features are not
sufficient, there is a customer defined external Auto-
restart Enable feature. This function can be triggered
by pulling down the BA pin to < 0.33V. It can simply add
a trigger signal to the base of the externally added
transistor, TAE at the BA pin. When the function is
enabled, the gate drive switching will be stopped and
then the IC will enter auto-restart mode if the signal
persists. To ensure this auto-resta rt function will not be
mis-triggered during start up, a 1ms delay time is
implemented to blank the unsta ble signal.
VCC undervoltage is the Vcc voltage drop below Vcc
turn off threshold. Then the IC will turn off and the start
up cell will turn on automatically. And this leads to Auto
Restart Mode.
Short Optocoupler also leads to VCC undervoltage as
there is no self supply after activating the internal
reference and bias.
C1
20.5V
Spike
Blanking
30us
&
G1
Auto Restart
mode
VCC
C4
4.0V Voltage
Reference
Control Unit
FB
C2 120us
Blanking
Time
VCC
25.5V
BA
Auto-restart
Enable
Signal
TAE
C9 8us
Blanking
Time
0.33V Stop
gate
drive
1ms
counter UVLO Auto Restart
Mode Reset
VVCC < 10.5V
softs_period
Thermal Shutdown
Tj>130°C
ICE3RBR1765JZ
Electrical Characteristics
Version 2.0 19 7 Jun 2013
4 Electrical Characteristics
Note: All voltages are measured with respect to ground (Pin 8). The volta ge levels are valid if other ratings are
not violated.
4.1 Absolute Maximum Ratings
Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction
of the integrated circuit. For the same rea son make sure, that any capacitor that will b e connected to pin 7
(VCC) is discharged before assembling the application circuit.Ta=25°C unless otherwise specified.
Parameter Symbol Limit Values Unit Remarks
min. max.
Switching drain current, pulse width tp
limited by Tj=150°C Is-4.03A
Pulse drain current, pulse width tp limited
by Tj=150°C ID_Puls -6.12A
Avalanche energy, repetitive tAR limited by
max. Tj=150°C1)
1) Repetitive avalanche causes additional power losses that can be calculated as PAV=EAR*f
EAR -0.15mJ
Avalanche current, repetitive tAR limited by
max. Tj=150°C1) IAR -1.5A
VCC Supply Voltage VVCC -0.3 27 V
FB Voltage VFB -0.3 5.5 V
BA Voltage VBA -0.3 5.5 V
CS Voltage VCS -0.3 5.5 V
Junction Temperature Tj-40 150 °C Controller & CoolMOS®
Storage Temperature TS-55 150 °C
Thermal Resistance
Junction -Ambient RthJA -96K/W
Soldering temperature, wavesoldering
only allowed at leads Tsold -260°C 1.6mm (0.063in.) from
case for 10s
ESD Capability (incl. Drain Pin) VESD - 2 kV Human body model2)
2) According to EIA/JESD22-A114-B (dischar ging a 100pF capacitor through a 1.5kΩ series resistor)
ICE3RBR1765JZ
Electrical Characteristics
Version 2.0 20 7 Jun 2013
4.2 Operating Range
Note: Within the operating range the IC operates as described in the functional description.
4.3 Characteristics
4.3.1 Supply Section
Note: The ele ctrical characteristic s involve th e spread of valu es within the specified supply voltag e and junction
temperature range TJ from - 40 °C to 125 °C. Typical values represent the median values, which are
related to 25°C. If not otherwise stated, a supply voltage of VCC = 18 V is assumed.
Parameter Symbol Limit Values Unit Remarks
min. max.
VCC Supply Voltage VVCC VVCCoff 25 V Max value limited due to Vcc OVP
Junction Temperature of
Controller TjCon -40 130 °C Max value limited due to thermal
shut down of controll er
Junction Temperature of
CoolMOS®TjCoolMOS -40 150 °C
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
Start Up Current IVCCstart - 150 250 μAVVCC =17V
VCC Charge Current IVCCcharge1 --5.0mAVVCC = 0V
IVCCcharge2 0.55 0.9 1.60 mA VVCC = 1V
IVCCcharge3 -0.7-mAVVCC =17V
Leakage Current of
Start Up Cell and CoolMOS®IStartLeak -0.250μAVDrain = 450V
at Tj=100°C
Supply Current with
Inactive Gate IVCCsup1 -1.52.5mA
Supply Current with Active Gate IVCCsup2 -2.73.4mAIFB = 0A
Supply Current in
Auto Restart Mode with Inactive
Gate
IVCCrestart -250-μAIFB = 0A
Supply Current in Active Burst
Mode with Inactive Gate IVCCburst1 - 450 950 μAVFB = 2.5V
IVCCburst2 - 450 950 μAVVCC = 11.5V,VFB = 2.5V
VCC Turn-On Threshold
VCC Turn-Off Threshold
VCC Turn-On/Off Hysteresis
VVCCon
VVCCoff
VVCChys
17.0
9.8
-
18.0
10.5
7.5
19.0
11.2
-
V
V
V
Version 2.0 21 7 Jun 2013
ICE3RBR1765JZ
Electrical Characteristics
4.3.2 Internal Voltage Reference
4.3.3 PWM Section
4.3.4 Soft Start time
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
Trimmed Reference Voltage VREF 4.90 5.00 5.10 V measured at pin FB
IFB = 0
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
Fixed Oscillator Frequency fOSC1 54.5 65.0 73.5 kHz
fOSC2 59.8 65.0 70.2 kHz Tj = 25°C
Frequency Jittering Range fjitter -±2.6-kHzTj = 25°C
Frequency Jittering period Tjitter -4.0-msTj = 25°C
Max. Duty Cycle Dmax 0.70 0.75 0.80
Min. Duty Cycle Dmin 0- - VFB < 0.3V
PWM-OP Gain AV3.1 3.3 3.5
Voltage Ramp Offset VOffset-Ramp -0.67-V
VFB Operating Range Min Level VFBmin -0.5-V
VFB Operating Range Max level VFBmax - - 4.3 V CS=1V, limited by
Comparator C41)
1) The parameter is not subjected to production test - verified by design/characterization
FB Pull-Up Re s i stor RFB 9 15.4 23 kΩ
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
Soft Start time tSS - 20.0 - ms
ICE3RBR1765JZ
Electrical Characteristics
Version 2.0 22 7 Jun 2013
4.3.5 Control Unit
Note: The trend o f all the v oltage leve ls in the Co nt rol Unit is the same regar ding the dev iation ex ce pt VVCCOVP.
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
Clamped VBA voltage during
Normal Operating Mode VBAclmp 0.85 0.9 0.95 V VFB = 4V
Blanking time voltage limit for
Comparator C3 VBKC3 3.85 4.00 4.15 V
Over Load & Open Loop Detection
Limit for Comparator C4 VFBC4 3.85 4.00 4.15 V
Active Burst Mode Level for
Comparator C5 VFBC5 1.25 1.35 1.45 V
Active Burst Mode Level for
Comparator C6a VFBC6a 3.35 3.50 3.65 V After Active Burst
Mode is entered
Active Burst Mode Level for
Comparator C6b VFBC6b 2.88 3.00 3.12 V After Active Burst
Mode is entered
Overvoltage Detection Limit for
Comparator C1 VVCCOVP1 19.5 20.5 21.5 V VFB = 5V
Overvoltage Detection Limit for
Comparator C2 VVCCOVP2 25.0 25.5 26.5 V
Auto-resta rt Enable level at BA pin VAE 0.25 0.33 0.4 V >30μs
Charging current at BA pin IBK 9.5 13.0 16.9 μA Charge starts after the
built-in 20ms blanking
time elapsed
Thermal Shutdown1)
1) The parameter is not subjected to produ ctio n test - verified by design/ch aracteriza tion . T he thermal s hutdo wn
temperature refers to the junction temperature of the controller.
TjSD 130 140 150 °C Controller
Built-in Blanking Time for
Overload Protection or enter
Active Burst Mode
tBK - 20 - ms without external
capacitor at BA pin
Inhibit Time for Auto-Restart
enable function during start up tIHAE - 1.0 - ms Count when VCC>18V
Spike Blanking Time before Auto-
Restart Protection tSpike -30-μs
ICE3RBR1765JZ
Electrical Characteristics
Version 2.0 23 7 Jun 2013
4.3.6 Current Limiting
4.3.7 CoolMOS® Section
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
Peak Current Limitation
(incl. Propagation Delay) Vcsth 0.95 1.03 1.10 V dVsense / dt = 0.6V / μs
(see Figure 20)
Peak Current Limitation during
Active Burst Mode VCS2 0.29 0.34 0.38 V
Leading Edge Blanking tLEB - 220 - ns
CS Input Bias Current ICSbias -1.6 -0.2 - μAVCS =0V
Parameter Symbol Limit Values Unit Test Condition
min. typ. max.
Drain Source Breakdown Voltage V(BR)DSS 650 - - V Tj = 110°C,
Refer to Figure 30 for
other V(BR)DSS in
different Tj
Drain Source On-Resistance RDSon -
-1.70
3.57 1.96
4.12 Ω
Ω
Tj = 25°C
Tj=125°C1)
at ID = 1.5A
1) The parameter is not subjected to production test - verified by design/characterization
Effective output capacitance, energy
related Co(er) -11.63- pFVDS = 0V to 480V1)
Rise Time trise -30
2)
2) Measured in a Typical Flyback Converter Application
-ns
Fall Time tfall -30
2) -ns
ICE3RBR1765JZ
Typical CoolMOS® Performance Characteristic
Version 2.0 24 7 Jun 2013
5 Typical CoolMOS® Performance Characteristic
Figure 27 Safe Operating area (S OA) curve for ICE3RBR1765JZ
Figure 28 SOA temperature derating coefficient curve
Safe Operating Area for ICE3RBR1765JZ
I
D
= f ( V
DS
)
parameter : D = 0, T
C
= 25deg.C
0.001
0.01
0.1
1
10
110 100 1000
V
DS
[V]
I
D
[A]
DC
tp = 100ms
tp = 0.1ms
tp = 1ms
tp = 10ms
tp = 1000ms
SOA temperature derating coefficient curve
( package dissipation ) for F3 & F2 CoolSET
0
20
40
60
80
100
120
0 20 40 60 80 100 120 140
Ambient/Case temperature Ta/Tc [deg.C]
Ta : DIP, Tc : TO220
SOA temperature derating coefficient [%]
ICE3RBR1765JZ
Typical CoolMOS® Performance Characteristic
Version 2.0 25 7 Jun 2013
Figure 29 Power dissipat io n; Ptot=f(Ta)
Figure 30 Drain-source breakdown voltage; VBR(DSS)=f(Tj), ID=0.25mA
Allowable Power Dissipation for F3 CoolSET in DIP-7 package
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0 20 40 60 80 100 120 140
Ambient temperature, T
A
[deg.C]
Allowable Power Dissipation, P
tot
[W]
540
580
620
660
700
-60 -20 20 60 100 140 180
T
j
[°C]
V
BR(DSS)
[V]
ICE3RBR1765JZ
Input Power Curve
Version 2.0 26 7 Jun 2013
6 Input Power Curve
Two input power curves giving the typical input power versus ambient temperature are showed below;
Vin=85Vac~265Vac (Figure 31) and Vin=230Vac+/-15% (Figure 32). The curves are derived based on a typical
discontinuous mod e flyback model which considers either 50% max imum duty ratio or 100V ma ximum secondary
to primary reflected voltage (higher priority). The calculation is based on no copper area as heatsink for the device.
The input power already includes the power loss at input common mode choke, bridge rectifier and the
CoolMOS.The device saturation current (ID_Puls @ Tj=125°C) is also co ns id ered.
To estimate the output power of the device, it is simply multiplying the input power at a particular operating ambient
temperature with the estimated efficienc y for the ap plication. For example, a wide rang e input voltage (Figure 31),
operating temperature is 50°C, estimated efficiency is 85%, then the estimated output power is 25W (29.5W *
85%).
Figure 31 Input pow er curve Vin=85~265Vac; Pin=f(Ta)
Figure 32 Input power curve Vin=230Vac+/-15%; Pin=f(Ta)
ICE3RBR1765JZ
Outline Dimension
Version 2.0 27 7 Jun 2013
7 Outline Dimension
Figure 33 PG-DIP-7 (Pb-free lead plating Plastic Dual-in-Line Outline)
PG-DIP-7
(Plastic Dual In-Line Outline)
ICE3RBR1765JZ
Marking
Version 2.0 28 7 Jun 2013
8Marking
Figure 34 Marking for ICE3RBR1765JZ
Marking
ICE3RBR1765JZ
Schematic for recommended PCB layout
Version 2.0 29 7 Jun 2013
9 Schematic for recommended PCB layout
Figure 35 Schema tic for recomme nded PCB layout
General guideline for PCB layout design using F3/F3R CoolSET® (refer to Figure 35):
1. “Star Ground “at bu lk capacitor ground, C11:
“Star Ground “means all primary DC grounds should be connected to the ground of bulk capacitor C11
separately in on e point. It can reduce th e switching noise going into the sensitive pins of the CoolSE T® device
effectively. The primary DC grounds include the followin gs.
a. DC ground of the primary auxiliary winding in power transformer, TR1, and ground of C16 and Z11.
b. DC ground of the current sense resistor, R12
c. DC ground of the CoolSET® device, GND pin of IC11; the signal grounds from C13, C14, C15 and collector
of IC12 should be connected to the GND pin of IC11 and then “star “conn ect to the bulk capacitor ground.
d. DC ground from bridge rectifier, BR1
e. DC ground from the bridging Y-capacitor, C4
2. High voltage traces clearanc e:
High voltage traces should keep enough spacing to the nearby traces. Otherwise, arcing would incur.
a. 400V traces (positive rail of bulk capacitor C11) to nearby trace: > 2.0mm
b. 600V traces (drain voltage of CoolSET® IC11) to nearby trace: > 2.5mm
3. Filter capacitor close to the controller ground:
Filter capacitors, C13, C14 and C15 should be placed as close to the c ontroller ground and the controller pin
as possible so as to reduce the switching noise coupled into the controller.
Guideline for PCB layout design when >3KV lightning surge test applied (refer to Figure 35):
1. Add spark gap
Spark gap is a pair of saw-tooth like copper plate facing each other which can discharge the accumulated
charge during surge test through the sharp point of the saw-tooth plate.
a. Spark Gap 3 and Spark Gap 4, input common mode choke, L1:
Gap separation is around 1.5 mm (no safety concern)
C11
bulk cap
R11
D11
C12
IC12
R12
C13
C16
C15
C14
D13
R14
R23 R22
IC21
C23 R24
C22
R21
R25
GND
Vo
D21
C21
F3 CoolSET schematic for recommended PCB layout
R13
Z11
TR1
N
L
BR1
C2
Y-CAP
C3
Y-CAP
C1
X-CAP
L1
FUSE1
C4
Y-CAP
GND
Spark Gap 3
Spark Gap 4 D11
Spark Gap 1
Spark Gap 2
FB
CS
GND NC
BA VCC
F3
DRAIN
CoolSET
IC11
*
ICE3RBR1765JZ
Schematic for recommended PCB layout
Version 2.0 30 7 Jun 2013
b. Spark Gap 1 and Spark Gap 2, Live / Neutral to GROUND:
These 2 Spark Gaps can be us ed when the lightning surge requirement is >6KV.
230Vac input voltage application, the gap separation is around 5.5mm
115Vac input voltage application, the gap separation is around 3mm
2. Add Y-capacitor (C2 and C3) in the Live and Neutral to ground even though it is a 2-pin inpu t
3. Add negative pulse clamping diode, D11 to the Current sense resistor, R12:
The negative pulse clamping diode can reduce the negative pulse going into the CS pin of the CoolSET® and
reduce the abnormal behavior of the CoolSET ®. The diode can be a fast speed diode such as IN4148.
The principle behind is to drain the high surg e voltage from Live/Neut ral to Ground without pa ssing through th e
sensitive components such as the primary controller, IC11.
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