TDA7491HV Datasheet 20 W + 20 W dual BTL class-D audio amplifier Features PowerSSO-36 exposed pad up PowerSSO-36 with exposed pad down * 20 W + 20 W continuous output power: - RL = 8 , THD = 10% at VCC = 18 V * * * * * * * * * Wide-range single-supply operation (5 - 18 V) High efficiency ( = 90%) Four selectable, fixed gain settings of nominally 20 dB, 26 dB, 30 dB and 32 dB Differential input minimize common-mode noise No `pop' at turn-on/off Standby and mute features Short-circuit protection Thermal overload protection External synchronisation Description The TDA7491HV is a dual BTL class-D audio amplifier with single power supply designed for LCD TVs and monitors. Thanks to the high efficiency and exposed-pad-up (EPU) and down (EPD) packages, no separate heatsink is required. The TDA7491HV is pin-to-pin compatible with the TDA7491P and TDA7491LP. Product status link TDA7491HV Product summary Order code TDA7491HV13TR Package PowerSSO-36 EPD Order code TDA7491HVU13TR Package PowerSSO-36 EPU Packing Tape and reel Temperature range -40 to 85 C DS5624 - Rev 9 - October 2018 For further information contact your local STMicroelectronics sales office. www.st.com TDA7491HV Device block diagram 1 Device block diagram Figure 1. Internal block diagram (showing one channel only) shows the block diagram of one of the two identical channels of the TDA7491HV. Figure 1. Internal block diagram (showing one channel only) DS5624 - Rev 9 page 2/50 TDA7491HV Pin description 2 Pin description 2.1 Pinout (EPD) Figure 2. Pin connections (top view, PCB view) DS5624 - Rev 9 S UB_GND 1 36 VS S OUTP B 2 35 S VCC OUTP B 3 34 VR E F P GNDB 4 33 INNB P GNDB 5 32 INP B P VC CB 6 31 GAIN P VC CB 7 30 P LIMIT OUTNB 8 29 S VR OUTNB 9 28 DIAG OUTNA 10 27 S GND OUTNA 11 26 VDDS P VC CA 12 25 S YNCLK EP P VC CA 13 24 R OS C P GNDA 14 23 INNA P GNDA 15 22 INP A OUTP A 16 21 MUTE OUTP A 17 20 S TBY P GND 18 19 VDDP W Exposed pad down (Connected to ground ) page 3/50 TDA7491HV Pin list (EPD) 2.2 Pin list (EPD) Table 1. Pin description list DS5624 - Rev 9 Number Name Type Description 1 SUB_GND PWR 2,3 OUTPB O 4,5 PGNDB PWR Power stage ground for right channel 6,7 PVCCB PWR Power supply for right channel 8,9 OUTNB O Negative PWM output for right channel 10,11 OUTNA O Negative PWM output for left channel 12,13 PVCCA PWR Power supply for left channel 14,15 PGNDA PWR Power stage ground for left channel 16,17 OUTPA O Positive PWM output for left channel 18 PGND PWR 19 VDDPW O 3.3-V (nominal) regulator output referred to ground for power stage 20 STBY I Standby mode control 21 MUTE I Mute mode control 22 INPA I Positive differential input of left channel 23 INNA I Negative differential input of left channel 24 ROSC O Master oscillator frequency-setting pin 25 SYNCLK I/O Clock in/out for external oscillator 26 VDDS O 3.3-V (nominal) regulator output referred to ground for signal blocks 27 SGND PWR 28 DIAG O Open-drain diagnostic output 29 SVR O Supply voltage rejection 30 GAIN0 I Gain setting input 1 31 GAIN1 I Gain setting input 2 32 INPB I Positive differential input of right channel 33 INNB I Negative differential input of right channel 34 VREF O Half VDDS (nominal) referred to ground 35 SVCC PWR 36 VSS O 3.3-V (nominal) regulator output referred to power supply - EP - Exposed pad for heatsink, to be connected to GND Connect to the frame Positive PWM for right channel Power stage ground Signal ground Signal power supply page 4/50 TDA7491HV Pinout (EPU) 2.3 Pinout (EPU) Figure 3. Pin connections (top view, PCB view) SUB GND 1 SVCC OUTPB 2 34 VREF OUTPB 3 33 INNB PGNDB 4 32 INPB PGNDB 5 31 GAIN PVCCB 6 30 PLIMIT PVCCB 7 29 OUTNB 8 28 DIAG OUTNB 9 27 SGND OUTNA 10 26 VDDS OUTNA 11 25 SYNCLK PVCCA 12 36 VSS 35 SVR 24 ROSC PVCCA 13 23 INNA PGNDA 14 22 INPA 21 MUTE 20 STBY 19 VDDPW DS5624 - Rev 9 PGNDA 15 EP exposed pad up Connect to ground OUTPA 16 OUTPA 17 PGND 18 page 5/50 TDA7491HV Pin list (EPU) 2.4 Pin list (EPU) Table 2. Pin description list DS5624 - Rev 9 Number Name Type Description 1 SUB_GND PWR 2, 3 OUTPB O 4, 5 PGNDB PWR Power stage ground for right channel 6, 7 PVCCB PWR Power supply for right channel 8, 9 OUTNB O Negative PWM output for right channel 10, 11 OUTNA O Negative PWM output for left channel 12, 13 PVCCA PWR Power supply for left channel 14, 15 PGNDA PWR Power stage ground for left channel 16, 17 OUTPA O Positive PWM output for left channel 18 PGND PWR 19 VDDPW O 3.3 V (nominal) regulator output referred to ground for power stage 20 STBY I Standby mode control 21 MUTE I Mute mode control 22 INPA I Positive differential input of left channel 23 INNA I Negative differential input of left channel 24 ROSC O Master oscillator frequency-setting pin 25 SYNCLK I/O Clock in/out for external oscillator 26 VDDS O 3.3 V (nominal) regulator output referred to ground for signal blocks 27 SGND PWR 28 DIAG O Open-drain diagnostic output 29 SVR O Supply voltage rejection 30 PLIMIT I Output voltage level setting 31 GAIN I Gain setting input 32 INPB I Positive differential input of right channel 33 INNB I Negative differential input of right channel 34 VREF O Half VDDS (nominal) referred to ground 35 SVCC PWR 36 VSS O 3.3 V (nominal) regulator output referred to power supply - EP - Exposed pad for heatsink, to be connected to GND Connect to the frame Positive PWM for right channel Power stage ground Signal ground Signal power supply page 6/50 TDA7491HV Absolute maximum ratings 3 Absolute maximum ratings Table 3. Absolute maximum ratings Symbol VCC Parameter Value Unit 23 V DC supply voltage for pins PVCCA, PVCCB VI Voltage limits for input pins STBY, MUTE, INNA, INPA, INNB, INPB, GAIN0, GAIN1 -0.3 - 3.6 V Top Operating temperature -40 to 85 C Tj Junction temperature -40 to 150 C Tstg Storage temperature -40 to 150 C Table 4. Thermal data Symbol Parameter Min. Typ. Max. 3 Rth j-case Thermal resistance, junction-to-case 2 Rth j-amb Thermal resistance, junction-to-ambient (mounted on a recommended PCB)(1). 24 Unit C/W 1. FR4 with vias to copper area of 9 cm2 DS5624 - Rev 9 page 7/50 TDA7491HV Electrical specifications 4 Electrical specifications Unless otherwise stated, the results in Table 1 below are given for the conditions: VCC = 18 V, RL (load) = 8 , ROSC = R3 = 39 k, C8 = 100 nF, f = 1 kHz, GV = 20 dB and Tamb = 25 C. Table 5. Electrical specifications Symbol VCC Iq IqSTBY Test conditions Min. Typ. Max. Unit Supply voltage 5 - 18 V Total quiescent current - 26 35 mA 2.5 5.0 A Quiescent current in standby Play mode -100 +100 Mute mode -60 +60 VOS Output offset voltage IOCP Overcurrent protection threshold Tj Junction temperature at thermal shutdown Ri Input resistance Differential input Undervoltage protection threshold - VUVP RDS(on) Po Po PD THD GV GV Power transistor on resistance Output power Output power Dissipated power RL = 0 eN Total input noise SVRR Supply voltage rejection ratio Tr, Tf Rise and fall times Switching frequency 60 k 4.5 THD = 10% 20 THD = 1% 16 RL = 8 , THD = 10%, VCC = 12 V 7.2 RL = 6 , THD = 1% VCC = 25 V 4.0 THD = 10% W 80 4.0 W 90 % 0.1 % GAIN0 = L, GAIN1 = L 18 20 22 GAIN0 = L, GAIN1 = H 24 26 28 GAIN0 = H, GAIN1 = L 28 30 32 GAIN0 = H, GAIN1 = H 30 32 34 -1 +1 f = 1 kHz, Po=1 W 70 A curve, GV = 20 dB 20 f = 22 Hz to 22 kHz - fr = 100 Hz, Vr = 1 Vpp, CSVR = 10 F Internal oscillator, master mode V W Po =20W +20 W, Gain matching A C 0.2 Po = 1 W - mV 150 Low-side Total harmonic distortion Cross-talk 54 5 0.2 Po = 20 W + 20W Closed-loop gain 3 High-side Efficiency CT fSW DS5624 - Rev 9 Parameter 290 25 dB dB dB 35 V 50 dB 40 ns 320 350 kHz page 8/50 TDA7491HV Electrical specifications Symbol Parameter fSWR Switching frequency range VinH Digital input high (H) VinL Digital input low (L) AMUTE Mute attenuation Standby mode Function mode Mute mode Play mode Test conditions (1) VMUTE = low, VSTBY= high Min. Typ. Max. Unit 250 - 400 kHz 2.3 0.8 80 V dB VSTBY < 0.5 V VMUTE = X VSTBY > 2.9 V VMUTE < 0.8 V VSTBY > 2.9 V VMUTE > 2.9 V 1. Refer to Section 8.4 Internal and external clocks. DS5624 - Rev 9 page 9/50 TDA7491HV Characterization curves 5 Characterization curves The following characterization curves have been produced by using the TDA7491HV evaluation board. The LC filter for 4 load uses components of 15 H and 470 nF, whilst that for 6 load uses 22 H and 220 nF and that for 8 load uses 33 H and 220 nF. 5.1 4 loads at VCC = 14 V Figure 4. Output power vs. supply voltage Test Condition : Vcc = 5~14V, RL = 4 ohm, Output power (W) Rosc = 39k , Cosc =100nF, f =1kHz, Gv = 30dB, Tamb = 25 Specification Limit: Typical: Vs =14V,Rl = 4 ohm Po = 20W @THD =10% Po =16W @THD =1% Supply voltage Figure 5. THD vs. output power (1 kHz) THD (%) 10 Test Condition: 5 Vcc=14V, RL=4 ohm, Rosc=39k , Cosc=100nF, f =1kHz, 2 1 0.5 Gv=30dB, Tamb=25 0.2 0.1 Specification Limit: 0.05 Typical: Po=20W @ THD=10% 0.02 0.01 100m 200m 500m 1 2 5 10 20 Output Power (W) DS5624 - Rev 9 page 10/50 TDA7491HV 4 loads at VCC = 14 V Figure 6. THD vs. output power (100 Hz) THD (%) 10 Test Condition: 5 Vcc=14V, RL=4 ohm, Rosc=39k , Cosc=100nF, f =100Hz, 2 1 0.5 Gv=30dB, Tamb=25 0.2 0.1 Specification Limit: 0.05 Typical: 20W @ THD=10% 0.02 0.01 100m 200m 500m 1 2 5 10 20 Output Power (W) Figure 7. THD vs. frequency THD (%) 0.5 Test Condition: 0.4 Vcc=14V, 0.3 RL=4 ohm, 0.2 Rosc=39k , Cosc=100nF, f = 1kHz, Gv=30dB, Po=1W Tamb=25 0.1 0.07 0.06 0.05 0.04 0.03 Specification Limit: 0.02 Typical: THD <0.5% 0.01 20 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz) DS5624 - Rev 9 page 11/50 TDA7491HV 4 loads at VCC = 14 V Figure 8. Frequency response Ampl (dB) +2 Test Condition: +1 Vcc =14V, RL= 4 ohm, -0 Rosc=39k , Cosc=100nF, f = 1kHz, -1 Gv = 30dB, Po =1W -2 Tamb = 25 -3 Specification Limit: -4 Max: +/-3dB @20Hz to 20kHz -5 10 20 50 100 200 500 1k 2k 5k 10k 30k Frequency (Hz) Figure 9. Crosstalk vs. frequency Crosstalk (dB) -40 -45 Test Condition: -50 Vcc =14V, -55 RL= 4 ohm, -60 Rosc= 39k , Cosc = 100nF, -65 -70 f = 1kHz, -75 Gv = 30dB, -80 Po = 1W -85 Tamb = 25 -90 -95 -100 Specification Limit: -105 Typical: >50dB (@ f = 1kHz) -110 -115 -120 20 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz) Figure 10. FFT performance (0 dB) FFT (dB) +10 Test Condition: Vcc =14V, +0 -10 -20 RL= 4 ohm, -30 Rosc = 39k , Cosc =100nF, -40 f =1kHz, Gv = 30dB, Po = 1W Tamb = 25 -50 -60 -70 -80 -90 -100 -110 Specification Limit: -120 Typical: >60dB -130 for the harmonic frequency -140 -150 20 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz) DS5624 - Rev 9 page 12/50 TDA7491HV 4 loads at VCC = 14 V Figure 11. FFT performance (-60 dB) FFT (dB) +0 -10 Test Condition: -20 Vcc =14V, -30 RL= 4 ohm, -40 Rosc = 39k , Cosc = 100nF, -50 f = 1kHz, -60 Gv=30dB, -70 -80 Po= -60dB (@ 1W =0dB) -90 Tamb=25 -100 -110 Specification Limit: -120 Typical: > 90dB -130 for the harmonic frequency -140 -150 20 50 100 200 500 1k 2k 5k 10k 20k 10k 20k Frequency (Hz) Figure 12. Power supply rejection ratio vs. frequency +0 -10 -20 Test Condition: Vcc =14V, RL= 4 ohm, Rosc = 39k , Cosc = 100nF, Vin=0, Ripple frequency=100Hz -40 Ripple voltage=500mV -50 Gv=30dB, d B r 0dB refers to 500mV,100Hz A Tamb=25 -30 -60 -70 -80 -90 -100 20 50 100 200 500 1k 2k 5k Hz Figure 13. Power dissipation and efficiency vs. output power Test Condition: Vcc=14V, RL=4 ohm, Rosc=39k , Cosc=100nF, DS5624 - Rev 9 Vcc=14V f =1kHz, Rload=4ohm Gv=30dB, Gain=30dB Tamb=25 f=1kHz page 13/50 TDA7491HV 4 loads at VCC = 14 V Figure 14. Closed-loop gain vs. frequency +2 +1.5 +1 Test Conditions: Gain=32dB Gain=26dB +0.5 -0 Vcc =14V, -0.5 RL= 4 ohm, -1 Rosc = 39k , Cosc = 100nF, F=1kHz, 0dB@f=1kHz,,Po=1w, Gain=32dB -1.5 d B r A Gain=22dB Gain=32dB -2 -2.5 -3 -3.5 Tamb=25 -4 -4.5 -5 20 50 100 200 500 1k 2k 5k 10k 20k 30k Hz Figure 15. Current consumption vs. voltage on pin MUTE Test Condition: Vcc =14V, RL= 4 ohm, Rosc = 39k , Cosc = 100nF, Vin=0, Vcc=14V Ta mb=25 Rload=4ohm Gain=30dB Vin=0 Figure 16. Attenuation vs. voltage on pin MUTE Test Condition: Vcc =14V, RL= 4 ohm, Rosc = 39k , Cosc = 100nF, 0dB@f=1kHz, Po=1w, Gain=30dB, Ta mb=25 DS5624 - Rev 9 Vcc=14V Rload=4ohm Gain=30dB 0dB@f=1kHz, Po=1w page 14/50 TDA7491HV 4 loads at VCC = 14 V Figure 17. Current consumption vs. voltage on pin STBY Test Condition: Vcc =14V, RL= 4 ohm, Rosc = 39k , Cosc = 100nF, Vcc=14V Vin=0, Rload=4ohm Ta mb=25 Gain=30dB Vin=0 Figure 18. Attenuation vs. voltage on pin STBY Test Condition: Vcc =14V, RL= 4 ohm, Vcc=14V Rload=4ohm Rosc = 39k , Cosc = 100nF, Gain=30dB 0dB@f=1kHz,Po=1w, Gain=30dB. 0dB@f=1kHz, Po=1w Tamb=25 DS5624 - Rev 9 page 15/50 TDA7491HV 6 loads at VCC = 16 V 5.2 6 loads at VCC = 16 V Figure 19. Output power vs. supply voltage Test Condition : f =1kHz Specification Limit: Typical: Vs =16V,Rl =6 ohm Po=20W @THD=10% Po=16W @THD=1% Figure 20. THD vs. output power (1 kHz) THD (%) 10 Test Condition: 5 Vcc =16V, RL= 6 ohm, Rosc =39k , Cosc =100nF, f =1kHz, 2 1 0.5 Gv =30dB, Tamb =25 0.2 0.1 Specification Limit: 0.05 Typical: Po=20W @ THD=10% 0.02 0.01 200m 500m 1 2 5 10 20 Output Power (W) DS5624 - Rev 9 page 16/50 TDA7491HV 6 loads at VCC = 16 V Figure 21. THD vs. output power (100 Hz) THD (%) 10 Test Condition: 5 Vcc =16V, RL = 6 ohm, Rosc =39k , Cosc =100nF, f =100Hz, Gv =30dB, Tamb =25 2 1 0.5 0.2 0.1 0.05 Specification Limit: Typical: 20W @ THD =10% 0.02 0.01 0.005 200m 500m 1 2 5 10 20 Output Power (W) Figure 22. THD vs. frequency THD (%) 2 Test Condition: Vcc =16V, RL= 6 ohm, 1 0.5 Ros c=39k , Cosc =100nF, f =1kHz, Gv =30dB, Po =1W 0.2 0.1 Tamb =25 0.05 Specification Limit: 0.02 Typical: THD<0.5% 0.01 20 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz) DS5624 - Rev 9 page 17/50 TDA7491HV 6 loads at VCC = 16 V Figure 23. Frequency response Ampl (dB) +2 Test Condition: Vcc=16V, +1 RL= 6 ohm, Rosc =39k , Cosc =100nF, -0 f = 1kHz, Gv =30dB, Po =1W Tamb =25 -1 -2 -3 Specification Limit: Max: +/-3dB -4 @20Hz to 20kHz -5 10 20 50 100 200 500 1k 2k 5k 10k 30k Frequency (Hz) Figure 24. Crosstalk vs. frequency Crosstalk (dB) -40 Test Condition: -45 -50 Vcc =16V, -55 RL= 6 ohm, -60 Rosc =39k , Cosc =100nF, -65 f = 1kHz, Gv =30dB, Po =1W Tamb=25 -70 -75 -80 -85 -90 -95 -100 Specification Limit: Typical: >50dB (@ f =1kHz) -105 -110 -115 -120 20 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz) DS5624 - Rev 9 page 18/50 TDA7491HV 6 loads at VCC = 16 V Figure 25. FFT performance (0 dB) FFT (dB) +10 +0 Test Condition: -10 Vcc =16V, -20 RL= 6 ohm, -30 Rosc =39k , Cosc =100nF, -40 -50 f =1kHz, -60 Gv =30dB, -70 -80 Po =1W -90 Tamb =25 -100 -110 Specification Limit: -120 Typical: >60dB -130 for the harmonic frequency -140 -150 20 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz) Figure 26. FFT performance (-60 dB) FFT (dB) +0 Test Condition: Vcc =16V, -10 -20 -30 RL= 6 ohm, -40 Rosc =39k , Cosc =100nF, -50 f =1kHz, -60 Gv =30dB, -70 Po = -60dB (@ 1W =0dB) Tamb =25 -80 -90 -100 -110 Specification Limit: -120 Typical: > 90dB -130 for the harmonic frequency -140 -150 20 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz) DS5624 - Rev 9 page 19/50 TDA7491HV 6 loads at VCC = 16 V Figure 27. Power supply rejection ratio vs. frequency +0 -10 -20 Ripple voltage=500mV Vcc =16V, -40 d B r RL= 6 ohm, Rosc =39k , Cosc =100nF, A Vin=0, Gv =30dB, Tamb =25 Ripple frequency=100Hz -30 Test Condition: -50 -60 -70 , -80 0dB refers to 500mV, 100Hz -90 -100 20 50 100 200 500 1k 2k 5k 10k 20k Hz Figure 28. Power dissipation and efficiency vs. output power Test Condition: Vcc =16V, RL= 6 ohm, Rosc =39k , Cosc =100nF, Vcc=16V f =1kHz, Rload=6ohm Gv =30dB, Gain=30dB Tamb =25 f=1kHz Figure 29. Closed-loop gain vs. frequency +2 +1.5 +1 Test Condition: +0.5 Vcc =16V, -0 RL= 6 ohm, Rosc =39k , Cosc =100nF, 0dB@f=1kHz,Po=1w, Gv=32dB, Tamb =25 Gain=26dB Gain=32dB -0.5 -1 d B r -1.5 A -2 Gain=30dB Gain=22dB -2.5 -3 -3.5 -4 -4.5 -5 20 50 100 200 500 1k 2k 5k 10k 20k 30k Hz DS5624 - Rev 9 page 20/50 TDA7491HV 6 loads at VCC = 16 V Figure 30. Current consumption vs. voltage on pin MUTE Test Condition: Vcc =16V, RL= 6 ohm, Rosc =39k , Cosc =100nF, Vcc=16V Rload=6ohm Vin=0, Gain=30dB Gain=30dB, Vin=0 Tamb =25 Mute voltage (V) Figure 31. Attenuation vs. voltage on pin MUTE Test Condition: Vcc =16V, Vcc=16V RL= 6 ohm, Rload=6ohm Rosc =39k , Cosc =100nF, 0dB@f=1kHz,Po=1w, Gain=30dB, Gain=30dB 0dB@f=1kHz, Po=1w Tamb =25 Mute voltage DS5624 - Rev 9 page 21/50 TDA7491HV 6 loads at VCC = 16 V Figure 32. Current consumption vs. voltage on pin STBY Test Condition: Vcc =16V, Vcc=16V RL= 6 ohm, Rload=6ohm Rosc =39k , Cosc =100nF, Gain=30dB Vin=0, Vin=0 Gain=30dB, Tamb =25 Test Condition: Vcc =16V, RL= 6 ohm, Rosc =39k , Cosc =100nF, 0dB@f=1kHz,Po=1w, Gain=30dB, Iquiescent (mA) Figure 33. Attenuation vs. voltage on pin STBY Vcc=16V Rload=6ohm Gain=30dB 0dB@f=1kHz, Po=1w Tamb =25 Standby voltage DS5624 - Rev 9 page 22/50 TDA7491HV 8 loads at VCC = 18 V 5.3 8 loads at VCC = 18 V Figure 34. Output power vs. supply voltage Test conditions : Vcc = 5~18V, Rosc =39k , Cosc =100nF f =1kHz, Gv =30dB, Tamb =25 Specification limit: Typical: Output power (W) RL = 8 ohm, Vs =18V,Rl = 8 ohm Po =20W @THD =10% Po =16W @THD =1% Supply voltage Figure 35. THD vs. output power (1 kHz) THD (%) 10 Test Condition: 5 Vcc =18V, RL= 8 ohm, 2 Rosc =39k , Cosc =100nF, 1 f =1kHz, Gv =30dB, Tamb =25 0.5 0.2 0.1 Specification Limit: Typical: Po =20W @ THD =10% 0.05 0.02 0.01 100m 200m 500m 1 2 5 10 20 Output Power (W) DS5624 - Rev 9 page 23/50 TDA7491HV 8 loads at VCC = 18 V Figure 36. THD vs. output power (100 Hz) THD (%) 10 Test Condition: 5 Vcc =18V, RL= 8 ohm, Rosc =39k , Cosc =100nF, f =100Hz, Gv =30dB, Tamb =25 2 1 0.5 0.2 0.1 0.05 Specification Limit: Typical: 20W @ THD =10% 0.02 0.01 0.005 100m 200m 500m 1 2 5 10 20 Output Power (W) Figure 37. THD vs. frequency THD (%) 2 Test Condition: Vcc =18V, RL= 8 ohm, 1 0.5 Rosc =39k , Cosc =100nF, f =1kHz, Gv =30dB, 0.2 0.1 Po =1W Tamb =25 0.05 0.02 Specification Limit: 0.01 Typical: THD<0.5% 0.005 20 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz) DS5624 - Rev 9 page 24/50 TDA7491HV 8 loads at VCC = 18 V Figure 38. Frequency response Ampl (dB) +2 Test Condition: Vcc =18V, +1 RL= 8 ohm, Rosc =39k , Cosc =100nF, -0 f =1kHz, -1 Gv =30dB, Po =1W -2 Tamb =25 -3 Specification Limit: -4 Max: +/-3dB @20Hz to 20kHz -5 10 20 50 100 200 500 1k 2k 5k 10k 30k Frequency (Hz) Figure 39. Crosstalk vs. frequency Crosstalk (dB) -40 Test Condition: -45 -50 Vcc =18V, -55 RL= 8 ohm, -60 Rosc =39k , Cosc =100nF, -65 f = 1kHz, Gv=30dB, Po=1W Tamb=25 -70 -75 -80 -85 -90 -95 -100 Specification Limit: Typical: >50dB (@ f =1kHz) -105 -110 -115 -120 20 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz) DS5624 - Rev 9 page 25/50 TDA7491HV 8 loads at VCC = 18 V Figure 40. FFT performance (0 dB) FFT (dB) +10 +0 Test Condition: -10 Vcc =18V, -20 RL= 8 ohm, -30 Rosc =39k , Cosc =100nF, -40 -50 f = 1kHz, -60 Gv =30dB, -70 Po =1W -80 -90 Tamb =25 -100 -110 Specification Limit: -120 Typical: >60dB -130 for the harmonic frequency -140 -150 20 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz) Figure 41. FFT performance (-60 dB) FFT (dB) +0 Test Condition: Vcc =18V, -10 -20 -30 RL= 8 ohm, -40 Rosc =39k , Cosc =100nF, -50 f =1kHz, -60 Gv =30dB, -70 Po = -60dB (@ 1W =0dB) Tamb =25 -80 -90 -100 -110 Specification Limit: -120 Typical: > 90dB -130 for the harmonic frequency -140 -150 20 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz) DS5624 - Rev 9 page 26/50 TDA7491HV 8 loads at VCC = 18 V Figure 42. Power supply rejection ratio vs. frequency +0 -10 Test Condition: -20 Vcc =18V, RL= 8 ohm, -30 Ripple frequency=100Hz -40 Ripple voltage=500mV Rosc =39k , Cosc =100nF, Vin=0, Gv =30dB, d B r Tamb =25 A 0dB refers to 500mV, 100Hz -50 -60 -70 -80 -90 -100 20 50 100 200 500 1k 2k 5k 10k 20k Hz 8ohm 18v PSRR.at27 Figure 43. Power dissipation and efficiency vs. output power RL= 8 ohm, Rosc =39k , Cosc =100nF, f=1kHz, Gv =30dB, Tamb =25 Vcc=18V Rload=8ohm Gain=30dB f=1kHz Power dissipation (W) Vcc =18V, Efficiency % Test Condition: Output power per channel (W) DS5624 - Rev 9 page 27/50 TDA7491HV 8 loads at VCC = 18 V Figure 44. Closed-loop gain vs. frequency +2 +1.5 Test Condition: +1 Vcc =18V, Gain=26dB Gain=32dB +0.5 RL= 8 ohm, -0 Rosc =39k , Cosc =100nF, 0dB@f=1kHz,Po=1w, Gain=32dB, Tamb =25 -0.5 -1 d B r -1.5 A -2 Gain=22dB Gain=30dB -2.5 -3 -3.5 -4 -4.5 -5 20 50 100 200 500 1k 2k 5k 10k 20k 30k Hz Figure 45. Current consumption vs. voltage on pin MUTE Vcc =18V, RL= 8 ohm, Rosc =39k , Cosc =100nF, Vin=0, Gain=30dB, Iquiescent (mA) Test Condition: Vcc=18V Rload=8ohm Gain=30dB Vin=0 Tamb =25 Mute voltage DS5624 - Rev 9 page 28/50 TDA7491HV 8 loads at VCC = 18 V Figure 46. Attenuation vs. voltage on pin MUTE Iquiescent (mA) Test Condition: Vcc =18V, RL= 8 ohm, Rosc =39k , Cosc =100nF, 0dB@f=1kHz,Po=1w, Gain=30dB, Vcc=18V Rload=8ohm Gain=30dB 0dB@f=1kHz, Po=1w Tamb =25 Mute voltage Figure 47. Current consumption vs. voltage on pin STBY Test Condition: RL= 8 ohm, Rosc =39k , Cosc =100nF, Vin=0, Gain=30dB, Tamb =25 Iquiescent (mA) Vcc =18V, Vcc=18V Rload=8ohm Gain=30dB Vin=0 Standby voltage (V) DS5624 - Rev 9 page 29/50 TDA7491HV 8 loads at VCC = 18 V Figure 48. Attenuation vs. voltage on pin STBY Vcc =18V, RL= 8 ohm, Rosc =39k , Cosc =100nF, 0dB@f=1kHz,Po=1w, Gain=30dB, Attenuation (dB) Test Condition: Vcc=18V Rload=8ohm Gain=30dB 0dB@f=1kHz, Po=1w Tamb =25 Standby voltage (V) DS5624 - Rev 9 page 30/50 TDA7491HV Test board 6 Test board Figure 49. Test board (TDA7491HV) layout DS5624 - Rev 9 page 31/50 TDA7491HV Application circuit 7 Application circuit Figure 50. Application circuit for class-D amplifier TDA7491HV DS5624 - Rev 9 page 32/50 TDA7491HV Application information 8 Application information 8.1 Mode selection The three operating modes of the TDA7491HV are set by the two inputs, STBY (pin 20) and MUTE (pin 21). * Standby mode: all circuits are turned off, very low current consumption. * Mute mode: inputs are connected to ground and the positive and negative PWM outputs are at 50% duty cycle. * Play mode: the amplifiers are active. The protection functions of the TDA7491HV are enabled by pulling down the voltages of the STBY and MUTE inputs shown in figure below. The input current of the corresponding pins must be limited to 200 A. Table 6. Mode settings Mode STBY MUTE Standby L(1). X (do not care) Mute H(1) L Play H H 1. Refer to VSTBY and VMUTE in Section 4 Electrical specifications Figure 51. Standby and mute circuits Standby 3.3 V 0V STBY R2 30 k C7 2.2 F R4 30 k C15 2.2 F Mute 3.3 V 0V DS5624 - Rev 9 TDA7491HV MUTE page 33/50 TDA7491HV Gain setting Figure 52. Turn-on/off sequence for minimizing speaker "pop" 8.2 Gain setting The gain of the TDA7491HV is set by the two inputs, GAIN0 (pin 30) and GAIN1 (pin31). Internally, the gain is set by changing the feedback resistors of the amplifier. Table 7. Gain settings GAIN0 GAIN1 Nominal gain, Gv (dB) L(1) H(1) 20 L H 26 H L 30 H H 32 1. Refer to Section 4 Electrical specifications for L and H drive levels. DS5624 - Rev 9 page 34/50 TDA7491HV Input resistance and capacitance 8.3 Input resistance and capacitance The input impedance is set by an internal resistor Ri = 68 k (typical). An input capacitor (Ci) is required to couple the AC input signal. The equivalent circuit and frequency response of the input components are shown in figure below. For Ci = 220 nF, the high-pass filter cut-off frequency is below 20 Hz: fc = 1 / (2 * * Ri * Ci) Figure 53. Device input circuit and frequency response 8.4 Internal and external clocks The clock of the class-D amplifier can be generated internally or can be driven by an external source. If two or more class-D amplifiers are used in the same system, it is recommended that all the devices operate at the same clock frequency. This can be implemented by using one TDA7491HV as master clock, while the other devices are in slave mode, that is, externally clocked. The clock interconnect is via pin SYNCLK of each device. As explained below, SYNCLK is an output in master mode and an output in master mode and an input in slave mode. 8.4.1 Master mode (internal clock) Using the internal oscillator, the output switching frequency, fSW, is controlled by the resistor, ROSC, connected to pin ROSC: fSW = 106 / ((16* ROSC+ 182) * 4) kHz where ROSC is in k. In master mode, pin SYNCLK is used as a clock output pin whose frequency is: fSYNCLK = 2 * fSW For master mode to operate correctly, then resistor ROSC must be less than 60 k as given below in Table 8. How to set up SYNCLK. DS5624 - Rev 9 page 35/50 TDA7491HV Modulation 8.4.2 Slave mode (external clock) In order to accept an external clock input the pin ROSC must be left open, that is, floating. This forces pin SYNCLK to be internally configured as an input as given in table below. The output switching frequency of the slave devices is: fSW = fSYNCLK / 2 Table 8. How to set up SYNCLK Mode ROSC SYNCLK Master ROSC < 60 k Output Slave Floating (not connected) Input Figure 54. Master and slave connection Master Slave TDA7491HV ROSC TDA7491HV SYNCLK Output Cosc 100 nF 8.5 SYNCLK ROSC Input Rosc 39 k Modulation The output modulation scheme of the BTL is called unipolar pulse width modulation (PWM). The differential output voltages change between 0 V and +VCC and between 0 V and -VCC. This is in contrast to the traditional bipolar PWM outputs which change between +VCC and -VCC. An advantage of this scheme is that it effectively doubles the switching frequency of the differential output waveform on the load then reducing the current ripple accordingly. The OUTP and OUTN are in the same phase almost overlapped when the input is zero under this condition, then the switching current is low and the related losses in the load are low. In practice, a short delay is introduced between these two outputs in order to avoid the BTL output switching simultaneously when the input is zero. Figure below shows the resulting differential output voltage and current when a positive, zero and negative input signal is applied. The resulting differential voltage on the load has a double frequency with respect to outputs OUTP and OUTN, resulting in reduced current ripple. DS5624 - Rev 9 page 36/50 TDA7491HV Reconstruction low-pass filter Figure 55. Unipolar PWM output 8.6 Reconstruction low-pass filter Standard applications use a low-pass filter before the speaker. The cut-off frequency should be higher than 22 kHz and much lower than the output switching frequency. It is necessary to choose the L-C component values depending on the loud speaker impedance. Some typical values, which give a cut-off frequency of 27 kHz, are shown in figures below. Figure 56. Typical LC filter for an 8 speaker DS5624 - Rev 9 page 37/50 TDA7491HV Protection functions Figure 57. Typical LC filter for an 4 speaker 8.7 Protection functions The TDA7491HV is fully protected against undervoltage, overcurrent and thermal overloads as explained here. Undervoltage protection (UVP) If the supply voltage drops below the value of VUVP given in Section 4 Electrical specifications the undervoltage protection is active and forces the outputs to the high-impedance state. When the supply voltage recovers, the device restarts. Overcurrent protection (OCP) If the output current exceeds the value for IOCP given in Section 4 Electrical specifications, the overcurrent protection is active and forces the outputs to the high-impedance state. Periodically, the device tries to restart. If the overcurrent condition is still present then the OCP remains active. The restart time, TOC, is determined by the R-C components connected to pin STBY. Thermal protection (OTP) If the junction temperature, Tj, reaches 145 C (nominal), the device goes to mute mode and the positive and negative PWM outputs are forced to 50% duty cycle. If the junction temperature reaches the value for Tj, given in Section 4 Electrical specifications, the device shuts down and the output is forced to the high-impedance state. When the device cools sufficiently the device restarts. 8.8 Diagnostic output The output pin DIAG is an open-drain transistor. When the protection is activated it is in the high-impedance state. The pin can be connected to a power supply (<18 V) by a pull-up resistor whose value is limited by the maximum sinking current (200 A) of the pin. Figure 58. Behavior of pin DIAG for various protection conditions VDD TDA7491HV R1 DIAG Protection logic VDD Overcurrent protection DS5624 - Rev 9 Restart Restart OV, UV, OT protection page 38/50 TDA7491HV Heatsink requirements 8.9 Heatsink requirements Due to the high efficiency of the class-D amplifier a 2-layer PCB can easily provide the heatsinking capability for low to medium power outputs. Using such a PCB with a copper ground layer of 3x3 cm2 and 16 vias connecting it to the contact area for the exposed pad, a thermal resistance, junction-to-ambient (in natural air convection), of 24 C/W can be achieved. The dissipated power within the device depends primarily on the supply voltage, load impedance and output modulation level. With the TDA7491HV driving 2 x 8 with a supply of 18 V then the device dissipation is approximately 4 W that gives with the above mentioned PCB a junction temperature rise of about 90 C. With a musical program, the dissipated power is about 40% less than the above maximum value. This leads to a junction temperature increase of around 60 C. So even at the maximum recommended ambient temperature there is a margin of safety before the maximum junction temperature is reached. Figure below shows the derating curves for copper areas of 4 cm2 and 9 cm2. Figure 59. Power derating curves for PCB used as heatsink Pd (W) 8 7 Copper Area 3x3 cm and via holes 6 5 TDA7491HV PSSO-36 4 3 Copper Area 2x2 cm and via holes 2 1 0 0 20 40 60 80 100 120 140 160 Tamb ( C) DS5624 - Rev 9 page 39/50 TDA7491HV Package information 9 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 9.1 PowerSSO-36 EPD Figure 60. PowerSSO-36 EPD package outline DS5624 - Rev 9 page 40/50 TDA7491HV PowerSSO-36 EPD Table 9. PowerSSO-36 EPD package dimensions Symbol mm Min. Typ. Max. Min. Typ. A 2.15 2.47 0.085 0.097 A2 2.15 2.40 0.085 0.094 a1 0.00 0.10 0.000 0.004 b 0.18 0.36 0.007 0.014 c 0.23 0.32 0.009 0.013 D 10.10 10.50 0.398 0.413 E 7.40 7.60 0.291 0.299 e 0.5 0.020 e3 8.5 0.335 F 2.3 0.091 G H 0.10 10.10 10.50 h 0.004 0.398 0.413 0.40 0.016 k 0 8 degrees 0 8 degrees L 0.60 1.00 0.024 0.039 M 4.30 N DS5624 - Rev 9 Inches 0.169 10 degrees 10 degrees O 1.20 0.047 Q 0.80 0.031 S 2.90 0.114 T 3.65 0.144 U 1.00 0.039 X 4.10 4.70 0.161 0.185 Y 4.90 7.10 0.193 0.280 page 41/50 TDA7491HV PowerSSO-36 with exposed pad up 9.2 PowerSSO-36 with exposed pad up Figure 61. PowerSSO-36 EPU package outline 7618147_6 DS5624 - Rev 9 page 42/50 TDA7491HV PowerSSO-36 with exposed pad up Table 10. PowerSSO-36 EPU package mechanical data Symbol DS5624 - Rev 9 mm Inches Min. Typ. Max. Min. Typ. Max. A 2.15 - 2.45 0.085 - 0.096 A2 2.15 - 2.35 0.085 - 0.093 a1 0 - 0.10 0 - 0.004 b 0.18 - 0.36 0.007 - 0.014 c 0.23 - 0.32 0.009 - 0.013 D 10.10 - 10.50 0.398 - 0.413 E 7.40 - 7.60 0.291 - 0.299 e - 0.5 - - 0.020 - e3 - 8.5 - - 0.335 - F - 2.3 - - 0.091 - G - - 0.10 - - 0.004 H 10.10 - 10.50 0.398 - 0.413 h - - 0.40 - - 0.016 k 0 - 8 degrees - - 8 degrees L 0.60 - 1.00 0.024 - 0.039 M - 4.30 - - 0.169 - N - - 10 degrees - - 10 degrees O - 1.20 - - 0.047 - Q - 0.80 - - 0.031 - S - 2.90 - - 0.114 - T - 3.65 - - 0.144 - U - 1.00 - - 0.039 - X 4.10 - 4.70 0.161 - 0.185 Y 6.50 - 7.10 0.256 - 0.280 page 43/50 TDA7491HV Revision history Table 11. Document revision history Date Revision 02-Jul-2008 1 Changes Initial release. Updated AMR table Updated Chapter 4: Characterization curves on page 12 03-Oct-2008 2 Added Figure 48: Test board (TDA7491HV) layout on page 29 Updated Figure 49: PowerSSO-36 EPD outline drawing on page 30 and Table 6: PowerSSO-36 EPD dimensions on page 31 Updated Figure 50: Applications circuit for class-D amplifier on page 32 Updated text concerning oscillator R and C in Section 3.3: Electrical specifications on page 10 29-Jun-2009 3 Updated VOVP minimum value, added VUVP maximum value, updated STBY and MUTE voltages in Table 5: Electrical specifications on page 10 Updated equation for fSW Table 5 on page 10 Updated Figure 50: Applications circuit for class-D amplifier on page 32 Added text for exposed pad in Figure 2 on page 8 03-Sep-2009 4 Added text for exposed pad in Table 2 on page 9 Updated exposed pad Y (Min) dimension in Table 6 on page 31 Updated supply voltage for pin DIAG pull-up resistor in Section 7.8 on page 40. Updated Features 24-Mar-2011 5 Updated Section 3: Electrical specifications Removed filter less operation Extended the temperature range to -40 to +85C. DS5624 - Rev 9 12Sep-2011 6 Updated OUTNA in Table 2: Pin description list 20-Feb-2014 7 Updated order code Table 1 on page 1 04-Jul-2018 8 Added PowerSSO-36 EPU silhouette in cover page, Section 2.3 Pinout (EPU), Section 2.4 Pin list (EPU) and Section 9.2 PowerSSO-36 with exposed pad up. 05-Oct-2018 9 Updated product summary table in cover page. page 44/50 TDA7491HV Contents Contents 1 Device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2.1 Pinout (EPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.2 Pin list (EPD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.3 Pinout (EPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.4 Pin list (EPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 Characterization curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 5.1 4 load at VCC = 14 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.2 6 load at VCC = 16 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3 8 load at VCC = 18 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6 Test board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 7 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 8 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 9 8.1 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8.2 Gain setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.3 Input resistance and capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.4 Internal and external clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.4.1 Master mode (internal clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 8.4.2 Slave mode (external clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.5 Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.6 Reconstruction low-pass filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.7 Protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.8 Diagnostic output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 8.9 Heatsink requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 9.1 PowerSSO-36 exposed pad down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 9.2 PowerSSO36 EPU package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 DS5624 - Rev 9 page 45/50 TDA7491HV Contents Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 DS5624 - Rev 9 page 46/50 TDA7491HV List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Pin description list . . . . . . . . . . . . . . . . . . . . Pin description list . . . . . . . . . . . . . . . . . . . . Absolute maximum ratings . . . . . . . . . . . . . . Thermal data. . . . . . . . . . . . . . . . . . . . . . . . Electrical specifications . . . . . . . . . . . . . . . . Mode settings . . . . . . . . . . . . . . . . . . . . . . . Gain settings . . . . . . . . . . . . . . . . . . . . . . . . How to set up SYNCLK. . . . . . . . . . . . . . . . . PowerSSO-36 EPD package dimensions . . . . PowerSSO-36 EPU package mechanical data . Document revision history . . . . . . . . . . . . . . . DS5624 - Rev 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 . 6 . 7 . 7 . 8 33 34 36 41 43 44 page 47/50 TDA7491HV List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. DS5624 - Rev 9 Internal block diagram (showing one channel only) Pin connections (top view, PCB view) . . . . . . . . Pin connections (top view, PCB view) . . . . . . . . Output power vs. supply voltage . . . . . . . . . . . . . THD vs. output power (1 kHz). . . . . . . . . . . . . . . THD vs. output power (100 Hz). . . . . . . . . . . . . . THD vs. frequency . . . . . . . . . . . . . . . . . . . . . . Frequency response . . . . . . . . . . . . . . . . . . . . . Crosstalk vs. frequency . . . . . . . . . . . . . . . . . . . FFT performance (0 dB) . . . . . . . . . . . . . . . . . . FFT performance (-60 dB) . . . . . . . . . . . . . . . . . Power supply rejection ratio vs. frequency . . . . . . Power dissipation and efficiency vs. output power . Closed-loop gain vs. frequency . . . . . . . . . . . . . . Current consumption vs. voltage on pin MUTE . . . Attenuation vs. voltage on pin MUTE . . . . . . . . . . Current consumption vs. voltage on pin STBY . . . Attenuation vs. voltage on pin STBY . . . . . . . . . . Output power vs. supply voltage . . . . . . . . . . . . . THD vs. output power (1 kHz). . . . . . . . . . . . . . . THD vs. output power (100 Hz). . . . . . . . . . . . . . THD vs. frequency . . . . . . . . . . . . . . . . . . . . . . Frequency response . . . . . . . . . . . . . . . . . . . . . Crosstalk vs. frequency . . . . . . . . . . . . . . . . . . . FFT performance (0 dB) . . . . . . . . . . . . . . . . . . FFT performance (-60 dB) . . . . . . . . . . . . . . . . . Power supply rejection ratio vs. frequency . . . . . . Power dissipation and efficiency vs. output power . Closed-loop gain vs. frequency . . . . . . . . . . . . . . Current consumption vs. voltage on pin MUTE . . . Attenuation vs. voltage on pin MUTE . . . . . . . . . . Current consumption vs. voltage on pin STBY . . . Attenuation vs. voltage on pin STBY . . . . . . . . . . Output power vs. supply voltage . . . . . . . . . . . . . THD vs. output power (1 kHz). . . . . . . . . . . . . . . THD vs. output power (100 Hz). . . . . . . . . . . . . . THD vs. frequency . . . . . . . . . . . . . . . . . . . . . . Frequency response . . . . . . . . . . . . . . . . . . . . . Crosstalk vs. frequency . . . . . . . . . . . . . . . . . . . FFT performance (0 dB) . . . . . . . . . . . . . . . . . . FFT performance (-60 dB) . . . . . . . . . . . . . . . . . Power supply rejection ratio vs. frequency . . . . . . Power dissipation and efficiency vs. output power . Closed-loop gain vs. frequency . . . . . . . . . . . . . . Current consumption vs. voltage on pin MUTE . . . Attenuation vs. voltage on pin MUTE . . . . . . . . . . Current consumption vs. voltage on pin STBY . . . Attenuation vs. voltage on pin STBY . . . . . . . . . . Test board (TDA7491HV) layout . . . . . . . . . . . . . Application circuit for class-D amplifier . . . . . . . . . Standby and mute circuits . . . . . . . . . . . . . . . . . Turn-on/off sequence for minimizing speaker "pop" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 . 3 . 5 10 10 11 11 12 12 12 13 13 13 14 14 14 15 15 16 16 17 17 18 18 19 19 20 20 20 21 21 22 22 23 23 24 24 25 25 26 26 27 27 28 28 29 29 30 31 32 33 34 page 48/50 TDA7491HV List of figures Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. DS5624 - Rev 9 Device input circuit and frequency response . . . . . . . . Master and slave connection . . . . . . . . . . . . . . . . . . Unipolar PWM output . . . . . . . . . . . . . . . . . . . . . . . Typical LC filter for an 8 speaker . . . . . . . . . . . . . . Typical LC filter for an 4 speaker . . . . . . . . . . . . . . Behavior of pin DIAG for various protection conditions . Power derating curves for PCB used as heatsink . . . . PowerSSO-36 EPD package outline . . . . . . . . . . . . . PowerSSO-36 EPU package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 36 37 37 38 38 39 40 42 page 49/50 TDA7491HV IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2018 STMicroelectronics - All rights reserved DS5624 - Rev 9 page 50/50