General Description
The MAX12553/MAX12554/MAX12555 evaluation kits (EV
kits) are fully assembled and tested PCBs that contain all
the components necessary to evaluate the performance
of this family of 14-bit, analog-to-digital converters
(ADCs). These ADCs accept differential or single-ended
analog inputs, however, the EV kits allow for evaluation
with either type of signal from one single-ended analog-
signal source. The digital outputs produced by the ADCs
are captured easily with a user-provided high-speed logic
analyzer or data-acquisition system. The EV kits operate
from a 1.8V and a 3.3V power supply and include circuit-
ry that generates a low-jitter clock signal from an AC
signal provided by the user.
Features
95Msps Sampling Rate with the MAX12555
80Msps Sampling Rate with the MAX12554
65Msps Sampling Rate with the MAX12553
Low-Voltage and Low-Power Operation
Fully Differential or Single-Ended Signal-Input
Configuration
Differential or Single-Ended Clock Configuration
On-Board Clock-Shaping Circuit with Adjustable
Duty Cycle
Fully Assembled and Tested
Evaluate: MAX12553/MAX12554/MAX12555
MAX12553/MAX12554/MAX12555
Evaluation Kits
________________________________________________________________
Maxim Integrated Products
1
19-3659; Rev 1; 10/06
Component List
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Ordering Information
+
Denotes a lead-free and RoHS-compliant EV kit.
*
EP = Exposed paddle.
PART TEMP RANGE IC PACKAGE
MAX12555EVKIT+ 0°C to +70°C 40 Thin QFN-EP*
MAX12554EVKIT+ 0°C to +70°C 40 Thin QFN-EP*
MAX12553EVKIT+ 0°C to +70°C 40 Thin QFN-EP*
Part Selection Table
PART NUMBER SPEED (Msps) APPLICATION
MAX12555ETL+ 95 IF/Baseband
Sampling
MAX12554ETL+ 80 IF/Baseband
Sampling
MAX12553ETL+ 65 IF/Baseband
Sampling
DESIGNATION QTY DESCRIPTION
C1, C2, C7, C33 4
22µF ±20%, 10V tantalum
capacitors (B-case)
AVX TAJB226M010
C3, C4, C6,
C8–C12, C17,
C21, C27, C34,
C43, C45
14
1.0µF ±10%, 6.3V X5R ceramic
capacitors (0402)
TDK C1005X5R0J105K
KEMET C0402C105K9PAC
C5, C14, C16,
C18, C19, C20,
C38, C44, C49,
C50
0 Not installed, capacitors (0402)
C13, C15,
C22–C26, C42 8
0.1µF ±20%, 10V X5R ceramic
capacitors (0402)
TDK C1005X5R1A104M
KEMET C0402C104K8PAC
C28 1
10µF ±20%, 6.3V X5R ceramic
capacitor (0805)
TDK C2012X5R0J106M
KEMET C0805C106K9PAC
DESIGNATION QTY DESCRIPTION
C29, C40, C41,
C48, C51, C52 0 Not installed, capacitors (0603)
C30, C31, C32,
C35, C36, C37 6
2.2µF ±20%, 6.3V X5R ceramic
capacitors (0603)
TDK C1608X5R0J225M
Panasonic ECJ1VB0J225K
C39 1
4.7µF ±10%, 6.3V X5R ceramic
capacitor (0603)
TDK C1608X5R0J475K
Panasonic ECJ1VB0J475K
C46, C47 2
15pF ±5%, 50V C0G ceramic
capacitors (0402)
Murata GRM1555C1H150J
CLOCK4 0 Not installed, SMA vertical
connector (SMA)
CLOCK, AINP,
AINN 3SMA vertical PC mount
connectors (SMA)
Component List continued on next page.
Evaluate: MAX12553/MAX12554/MAX12555
MAX12553/MAX12554/MAX12555
Evaluation Kits
2 _______________________________________________________________________________________
Component List (continued)
DESIGNATION QTY DESCRIPTION
D1 1
Dual Schottky diode (SOT23)
Central Semiconductor
CMPD6263S, lead free
(Top Mark: D96)
Vishay BAS70-04 (Top Mark: 74)
Diodes Inc. BAS70-04-7-F
(Top Mark: K74 or K7D)
D2 0 Not installed, diode (SOT23)
J1 1 Dual-row, 2 x 20, 40-pin header
JU1, JU9, JU10 0 Not installed, 2-pin headers
JU2–JU8 7 3-pin headers
L1–L4 4 EMI filters
Murata NFM41PC204F1H3B
R1, R8, R11,
R15–R28, R31 0 Not installed, resistors (0603)
R2, R12, R13,
R14 0 Not installed, resistors (0402)
R3, R4 2 75Ω ±0.5% resistors (0603)
R5, R6 2 1.0kΩ ±5% resistors (0402)
R7, R9 2 100Ω ±1% resistors (0603)
R10 1 10kΩ potentiometer, 12-turn,
1/4in
R29, R30 2 110Ω ±0.5% resistors (0603)
RA1–RA4 4 220Ω ±5% resistor arrays
Panasonic EXB-2HV-221J
DESIGNATION QTY DESCRIPTION
T1, T2 2 1:1 RF transformers
Mini-Circuits ADT1-1WT
T3 1 4:1 RF transformer
Mini-Circuits ADT4-6WT
T4 0 Not installed, transformer
TP1–TP4 4 Miniature PC test points (red)
Keystone Electronics 5000
TP5, TP6 2 Miniature PC test points (black)
Keystone Electronics 5001
U1 1 See the EV Kit-Specific
Component List
U2 1
Low-voltage, 16-bit register
(48-pin TSSOP)
Texas Instruments
SN74AVC16374DGGR
U3 0 Not installed (SC70-5)
U4 1 TinyLogic UHS buffer (SC70-5)
Fairchild NC7SZ125P5
U5 0 Not installed (8-pin SO)
U6 1
TinyLogic dual UHS inverter
(SC70-6)
Fairchild NC7WZ04P6
— 7 Shunts (JU2–JU8)
—1
MAX12553/MAX12554/
MAX12555EVKIT+ PCB
Component Suppliers
SUPPLIER PHONE WEBSITE
AVX Corp. 843-946-0238 www.avxcorp.com
Central Semiconductor 631-435-1110 www.centralsemi.com
Fairchild Semiconductor 888-522-5372 www.fairchildsemi.com
Murata Mfg. Co., Ltd. 770-436-1300 www.murata.com
Panasonic Corp. 714-373-7366 www.panasonic.com
TDK Corp. 847-803-6100 www.component.tdk.com
Note: Indicate that you are using the MAX12553, MAX12554, or MAX12555 when contacting these component suppliers.
EV Kit-Specific Component List
EV KIT PART NUMBER REFERENCE DESIGNATOR DESCRIPTION
MAX12555EVKIT+ MAX12555ETL+ (40-pin, 6mm x 6mm x 0.8mm Thin QFN with EP)
MAX12554EVKIT+ MAX12554ETL+ (40-pin, 6mm x 6mm x 0.8mm Thin QFN with EP)
MAX12553EVKIT+
U1
MAX12553ETL+ (40-pin, 6mm x 6mm x 0.8mm Thin QFN with EP)
Evaluate: MAX12553/MAX12554/MAX12555
Quick Start
Recommended Equipment
• DC power supplies:
Digital (VLDUT) 1.8V, 100mA
Logic (VL) 1.8V, 100mA
Analog (VDUT) 3.3V, 250mA
• Signal generator with low phase noise and low jitter
for clock input (e.g., HP/Agilent 8644B)
• Signal generator for analog-signal input (e.g.,
HP/Agilent 8644B)
• Logic analyzer or data-acquisition system (e.g.,
HP/Agilent 16500C)
• Analog bandpass filters (e.g., K&L Microwave) for
input and clock signals
• Digital voltmeter
Procedure
Each EV kit is a fully assembled and tested surface-
mount PCB. Follow the steps below to verify board opera-
tion. Caution: Do not turn on power supplies or enable
signal generators until all connections are completed.
1) Verify that shunts are installed across pins 2-3 of
jumpers JU2 (ADC enabled) and JU3 (two’s-com-
plement digital-output format).
2) Verify that shunts are installed across pins 1-2 of
jumpers JU4 (internal duty-cycle equalizer enabled)
and JU5 (differential clock configuration).
3) Verify that shunts are installed across pins 2-3 of
jumper JU6 and across pins 1-2 of jumpers JU7
and JU8.
4) Connect the clock generator output to the clock
bandpass filter input.
5) Connect the output of the clock bandpass filter to
the CLOCK SMA connector.
6) Connect the output of the analog-signal generator
to the input of the signal bandpass filter. Keep the
cable connection between the signal generators, fil-
ters, and EV kit board as short as possible for opti-
mum dynamic performance.
7) Connect the output of the signal bandpass filter to
the AINP SMA connector. Note: It is recommend-
ed that a 3dB or 6dB attenuation pad be used to
reduce reflections and distortion from the band-
pass filter.
8) Connect the logic analyzer to the square pin header
(J1). See the
Digital Output
section for bit locations
and J1 header designations. The system clock is
available on pin 3 of J1.
9) Connect a 3.3V, 250mA power supply to VDUT.
Connect the ground terminal of this supply to the
corresponding GND pad.
10) Connect a 1.8V, 100mA power supply to VL.
Connect the ground terminal of this supply to the
GND pad.
11) Connect a 1.8V, 100mA power supply to VLDUT.
Connect the ground terminal of this supply to the
GND pad.
12) Turn on the 3.3V power supply.
13) Turn on the 1.8V power supplies.
14) Enable the signal generators.
15) Set the clock-signal generator to the desired clock
frequency. See the
Part Selection Table
for appropri-
ate frequency settings for each EV kit. The amplitude
of the generator should be sufficient to produce a
16dBm signal at the SMA input of the EV kits.
16) Set the analog input-signal generators for an output
amplitude of less than or equal to 2VP-P and to the
desired test frequency.
17) Verify that the two signal generators are synchro-
nized to each other. Adjust the output power level
of the signal generators to overcome cable, band-
pass filter, and attenuation pad losses at the input.
18) Enable the logic analyzer.
19) Collect data using the logic analyzer.
Detailed Description
Each EV kit is a fully assembled and tested PCB that
contains all the components necessary to evaluate the
performance of the MAX12553, MAX12554, or MAX12555
IC. Data generated by the EV kits are captured on a
single 14-bit parallel bus. The EV kits accept differential
or single-ended analog inputs and single-ended clock
signals. With the proper board configuration, the ADC is
evaluated with both types of signals by supplying only
one single-ended analog signal to the EV kit.
The EV kits are designed as four-layer PCBs to opti-
mize the performance of this family of ADCs. For simple
operation, the EV kits require 3.3V and 1.8V power
supplies, applied to analog and digital power planes,
respectively. However, the digital plane operates down
to 1.7V without compromising the ADC’s performance.
The logic analyzer’s threshold must be adjusted
accordingly.
MAX12553/MAX12554/MAX12555
Evaluation Kits
_______________________________________________________________________________________ 3
Access to the digital outputs is provided through con-
nector J1. The 40-pin connector easily interfaces with a
user-provided logic analyzer or data-acquisition system.
The DAV buffered output clock signal is available at pin
3 of J1 (CLKO) and is used to synchronize the output
data to the logic analyzer.
Power Supplies
The EV kits require separate analog and digital power
supplies for best performance. Separate 3.3V power
supplies are used to power the analog circuit blocks of
the converter (VDUT) and the clock-shaping circuit
(VCLK). To evaluate single-ended clock-signal opera-
tion, 3.3V must be supplied to VCLK. Separate 1.8V
power supplies are used to power the digital circuit
block of the converter (VLDUT) and the buffer/driver, U2
(VL). The digital circuit blocks of the EV kits operate with
voltage supplies as low as 1.7V and as high as 3.6V.
Clock Input
The MAX12553, MAX12554, and MAX12555 accept dif-
ferential or single-ended clock input signals. However,
the EV kits only accept a single-ended clock signal.
The EV kits include circuitry that converts a single-
ended signal to a differential clock signal through a
transformer or a user-installed differential clock driver
IC (U5). The EV kits also include clock-shaping circuitry
for a single-ended clock-signal configuration. Jumper
JU5 must be configured for differential or single-ended
clock-signal operation. See Table 1 for jumper settings.
Transformer-Coupled Differential Clock
A single-ended signal connected to the CLOCK SMA
connector is converted to a differential signal by trans-
former T3. In this mode, diode D1 limits the clock-signal
amplitude. Using this diode in the signal path allows the
clock signal to be increased significantly without violat-
ing the absolute maximum ratings of the converter
inputs, as the diode clips the input signal. Overdriving
the clock input to the board (CLOCK SMA) results in an
increased slew rate, which, in turn, compensates for the
negative effects that clock jitter imposes on parameters
such as signal-to-noise ratio (SNR) and signal-to-noise
plus distortion (SINAD). See Table 2 for jumper settings.
Install a shunt across pins 1-2 of jumper JU5 for differ-
ential clock operation. Note: While in transformer-
coupled differential clock mode, power to VCLK
should not be applied unless R10 is turned to one
extreme to avoid unnecessary triggering of U6.
Unnecessary triggering could potentially disturb the
ground plane with unwanted spur energy.
Clock-Shaping Circuit with Variable Duty Cycle
An on-board variable duty-cycle, clock-shaping circuit
generates a single-ended clock signal from an AC-cou-
pled sine wave applied to the CLOCK SMA connector.
Measure the clock signal at pin 2 of jumper JU7 and
adjust potentiometer R10 to obtain the desired duty
cycle. See Table 2 for shunt positions. A 3.3V voltage
source must be connected across VCLK and GND to
power the clock-circuit comparators.
Input Signal
The MAX12553, MAX12554, and MAX12555 accept dif-
ferential or single-ended analog input signals. However,
the EV kits require only a single-ended analog input
signal. Because the amplitude of the received signal at
the ADC depends on the actual cable and bandpass
filter loss, account for these losses when configuring
the signal-input generator. In differential mode, on-
board transformers T1 and T2 take the single-ended
analog input connected to the AINP SMA connector
and generate a differential analog signal at the ADC’s
input pins. For direct single-ended or differential input-
signal operation, the EV kit board circuit modifications
are listed in the
Direct AC-Coupled Differential Input
and
Direct AC-Coupled Single-Ended Input
sections.
Evaluate: MAX12553/MAX12554/MAX12555
MAX12553/MAX12554/MAX12555
Evaluation Kits
4 _______________________________________________________________________________________
SHUNT
POSITION CLKTYP PIN CLOCK INPUT
CONFIGURATION
1-2* Connected to VLDUT Differential
2-3 Connected to GND Single-Ended
Table 1. Clock Input Settings (JU5)
*
Default position.
JUMPER SHUNT
POSITION CLOCK MODE
JU4 2-3
JU6 1-2
JU7 2-3
JU8 2-3
Single-Ended Clock
Mode—See the Clock-Shaping
Circuit with Variable Duty Cycle
section.
JU4 1-2*
JU6 2-3*
JU7 1-2*
JU8 1-2*
D i ffer enti al C l ock M od e— A
si ng l e- end ed si g nal i s conver ted
to a d i ffer enti al si g nal that d r i ves
the AD C cl ock i np uts.
Table 2. Clock Drive Settings
*
Default position.
Evaluate: MAX12553/MAX12554/MAX12555
MAX12553/MAX12554/MAX12555
Evaluation Kits
_______________________________________________________________________________________ 5
Direct AC-Coupled Differential Input
To evaluate the MAX12553/MAX12554/MAX12555 EV
kits with differential input signals directly connected to
the ADC input pins, modify the EV kits as follows:
1) Remove transformers T1 and T2.
2) Remove the short across resistor R15.
3) Remove R3 and R4.
4) Install 0Ωresistors across R20 and R24.
5) Install 0.1µF ceramic capacitors across C51 and
C52.
6) Modify resistors R29 and R30 to match the source
impedance (e.g., 25Ωresistors for a 50Ω differential
source impedance).
7) Connect the positive input-signal source to the
AINP SMA connector.
8) Connect the negative input-signal source to the
AINN SMA connector.
Direct AC-Coupled Single-Ended Input
To evaluate the MAX12553/MAX12554/MAX12555 EV
kits with a single-ended input signal directly connected
to the ADC input terminal, modify the EV kits as follows:
1) Remove transformers T1 and T2.
2) Remove resistor R3.
3) Install 0Ωresistors across R20, R29, and R13.
4) Install a 0.1µF ceramic capacitor across C51.
5) Install a 1µF capacitor across C47.
6) Modify resistor R30 to match the source impedance
(e.g., a 50Ωresistor for a 50Ωsource impedance).
7) Connect the positive input-signal source to the
AINP SMA connector.
Converter Power-Down
The MAX12553, MAX12554, and MAX12555 each fea-
ture an active-high global device power-down pin.
Jumper JU2 controls this feature. Other ICs on the EV
kits continue to draw quiescent current from the power
supplies. See Table 3 for power-down jumper settings.
Reference Voltage
The MAX12553, MAX12554, and MAX12555 require an
input-reference voltage at the converter’s REFIN pin to
set the full-scale analog-signal voltage input. The ADC
offers a stable on-chip reference voltage of 2.048V that
is accessed at the REFIN pad. The EV kits were
designed to use the on-chip reference voltage by short-
ing REFIN to REFOUT through resistor R12.
The user externally adjusts the reference level, hence
the full-scale range, by cutting open the PC trace short-
ing resistor R12 and installing the appropriate resistors
at locations R2 and R12 (located on the board’s com-
ponent side). Calculate the resistor values using the fol-
lowing equation:
where:
R2 = 10kΩ±1%
VREFOUT = 2.048V
VREFIN = desired REFIN voltage in the 0.7V to
2.2V range
Alternatively, resistors R12 and R2 can be left unpopu-
lated and the ADC’s full-scale range set by applying a
stable, low-noise, external voltage reference directly at
the REFIN pad.
Shorting the REFIN pad to ground through resistor R2
disables the internal reference voltage. In this mode,
test points TP1 (REFP), TP2 (REFN), and TP3 (COM)
must be driven with stable reference voltages. Refer to
the
Analog Inputs and Reference Configurations
sec-
tion in the MAX12553, MAX12554, and MAX12555 IC
data sheets for further details. Note: To drive test
point TP3 with an external reference voltage, add a
0Ωresistor across R27.
Output Coding
Set the digital output coding to either two’s-comple-
ment or Gray-code format by configuring jumper JU3.
See Table 4 for shunt positions.
R12 R2
V
V 1
REFOUT
REFIN
=⎛
⎝
⎜
⎞
⎠
⎟
−
SHUNT
POSITION PD PIN EV KIT
OPERATION
1-2 Connected to VLDUT Powered Down
2-3* Connected to GND Normal Operation
Table 3. Power-Down Settings (JU2)
*
Default position.
SHUNT
POSITION G/T PIN DIGITAL OUTPUT
FORMAT
1-2 Connected to VLDUT Gray Code
2-3* Connected to GND Two's Complement
Table 4. Output Code Settings (JU3)
*
Default position.
Evaluate: MAX12553/MAX12554/MAX12555
MAX12553/MAX12554/MAX12555
Evaluation Kits
6 _______________________________________________________________________________________
Digital Output
The MAX12553, MAX12554, and MAX12555 feature a
14-bit, parallel, CMOS-compatible output bus. The out-
puts of the ADC are applied to an output buffer (U2)
capable of driving large capacitive loads that may be
present at the logic analyzer connection. The digital
outputs are valid on the rising edge of the CLKO output
signal. The outputs of the buffer are connected to a
40-pin header (J1) located on the right side of the EV
kits, where the user connects a logic analyzer or data-
acquisition system. See Table 5 for bit locations at
header J1. The signals are available on the J1 pins
closest to the edge of the EV kit boards.
Component Placement and
Board Layout Recommendations
Refer to the
Schematic and Layout Guidelines for High-
Speed Data Converters
application note, located at
www.maxim-ic.com/appnotes.cfm/an_pk/3491,
for a detailed discussion about component place-
ment and PCB layout recommendations for the
MAX12553/MAX12554/MAX12555.
CLOCK DOR BIT
D13
BIT
D12
BIT
D11
BIT
D10
BIT
D9
BIT
D8
BIT
D7
BIT
D6
BIT
D5
BIT
D4
BIT
D3
BIT
D2
BIT
D1
BIT
D0
J1-3
CLKO J1-7 J1-11 J1-13 J1-15 J1-17 J1-19 J1-21 J1-23 J1-25 J1-27 J1-29 J1-31 J1-33 J1-35 J1-37
Table 5. Output Bit Locations (J1)
Evaluate: MAX12553/MAX12554/MAX12555
MAX12553/MAX12554/MAX12555
Evaluation Kits
_______________________________________________________________________________________ 7
15
14
13
12
11
10
9
2
3
4
5
6
7
8
161
RA3
220Ω
15
14
13
12
11
10
9
2
3
4
5
6
7
8
161
RA1
220Ω
15
14
13
12
11
10
9
2
3
4
5
6
7
8
161
RA4
220Ω
J1-39
J1-37
J1-35
J1-33
J1-31
J1-29
J1-27
J1-25
J1-23
J1-21
J1-19
J1-17
J1-15
J1-13
J1-11
J1-7
J1-5
J1-9
J1-3
J1-1
J1-40
J1-38
J1-36
J1-34
J1-32
J1-30
J1-28
J1-26
J1-24
J1-22
J1-20
J1-18
J1-16
J1-14
J1-12
J1-8
J1-6
J1-10
J1-4
J1-2
N.C.
N.C.
N.C.
J1
N.C.
N.C.
N.C.
CLK0
GND GND GND GNDGND GND GND GND
22
20
19
17
16
14
13
23
11
9
8
6
5
3
2
12
2Q7
2Q6
2Q5
2Q4
2Q3
2Q2
2Q1
2Q8
1Q7
1Q6
1Q5
1Q4
1Q3
1Q2
1Q1
1Q8
VCC VCC1CLK 2CLK
TP5
28 34 45 394101521
VCC VCC
31 4248 25 7 18
VCC
2D7
2D6
2D5
2D4
2D3
2D2
2D1
2D8
27
29
30
32
33
35
36
26
15
14
13
12
11
10
9
2
3
4
5
6
7
8
161
RA2
220Ω
1D7
1D6
1D5
1D4
1D3
1D2
1D1
1D8
38
40
41
43
44
46
47
1OE
2OE
1
24
37 U2
SN74AVC16374
MAX12553/
MAX12554/
MAX12555
U1
VDD VDD VDD VDD VDD OVDD OVDD DAV
OVDDVDD
12 13 14 15 36 17 34 33
D0
D1
D2
D3
D4
D5
D6
32
31
30
29
28
27
26
D8
D9
D10
D11
D12
D13
DOR
D7
24
23
22
21
20
19
18
25
TP4
R12
SHORT
(PC TRACE)
R2
OPEN
C44
OPEN
C26
0.1µF
REFIN
38
39
REFOUT
REFIN
TP6
GND GND GND GND
4 7 16 35
JU1
CUT HERE
OE
A
GND
U3
OPEN
VCC
Y
OE
A
GND
U4
NC7SZ125
VCC
Y
5
4
5
4
1
2
3
1
2
3CLK0
VCC VCC
C5
OPEN
C6
1.0µF
L4
1
2
3
C33
22µF
10V
C34
1.0µF
VCK
VCLK
GND
L1
1
2
3
C1
22µF
10V
C3
1.0µF
VDD
VDUT
GND
L2
1
2
3
C2
22µF
10V
C4
1.0µF
OVDD
VLDUT
GND
L3
1
2
3
C7
22µF
10V
C12
1.0µF
VCC
VL
JU2
1
2
3
OVDD
37 PD
JU3
1
2
3
OVDD
40 G/T
JU5
1
2
3
OVDD
11 CLKTYP
JU4
1
2
3
OVDD
8DCE
C45
1.0µF
C28
10µF
C17
1.0µF
C21
1.0µF
TP2
TP1
REFP
REFN
COM
INP
INN
CLKN
CLKP
1
2
3
5
6
9
10
C32
2.2µF
COM
INP
INN
CLKN
CLKP
C8
1.0µF
C9
1.0µF
C10
1.0µF
C11
1.0µF
VCC
C30
2.2µF
C13
0.1µF
C31
2.2µF
C15
0.1µF
OVDD
PLACE CAPACITORS IN THE FOLLOWING LOCATIONS OF U1:
C35 AND C23 NEXT TO PIN 36
C36 AND C24 NEXT TO PINS 12/13
C37 AND C25 NEXT TO PINS 14/15
C24
0.1µF
C37
2.2µF
C25
0.1µF
C35
2.2µF
C23
0.1µF
VDD
C36
2.2µF
Figure 1a. MAX12553/MAX12554/MAX12555 EV Kits Schematic (Sheet 1 of 2)
Evaluate: MAX12553/MAX12554/MAX12555
MAX12553/MAX12554/MAX12555
Evaluation Kits
8 _______________________________________________________________________________________
RL
12
3
RL
21
3
1
2
3
6
5
4
T4
OPEN
R1
OPEN
CLOCK4
OPEN
C29
OPEN
C48
OPEN
D2
OPEN
R21
OPEN
R25
OPEN
C16
OPEN
C14
OPEN
C38
OPEN
R16
OPEN
R11
OPEN
VCK
U5
OPEN
7
6
CLK
VBB
CLK
RESET
2
4
3
1
Q
Q
5
VEE
VCK C18
OPEN
VCC
8
R18
OPEN
R17
OPEN
R26
OPEN
C19
OPEN
C20
OPEN JU10
OPEN
JU9
OPEN
CLKN
CLKP
3
2
1
1
2
3
JU7
JU8
D1
C40
SHORT
C41
SHORT
R7
100Ω
1%
R9
100Ω
1%
C27
1.0µF
C42
0.1µF
4
5
6
3
2
1
T3
1
2
3
JU6
3
4
U6-B U6-A
1
6
2
C43
1.0µF
VCK
5
VCK
R8
OPEN
CLOCK
R5
1.0kΩ
R10
10kΩR6
1.0kΩ
C22
0.1µF
1
5
3
6
2
4
T1 1
5
3
6
2
4
T2
AINP
AINN
R31
OPEN
R19
SHORT
(PC TRACE)
R14
SHORT
(PC TRACE)
R22
SHORT
(PC TRACE)
R13
SHORT
(PC TRACE)
R23
SHORT
(PC TRACE)
R20
OPEN
R24
OPEN
R15
SHORT
(PC TRACE)
R28
SHORT
(PC TRACE)
R3
75Ω
0.5%
R4
75Ω
0.5%
C51
OPEN
C52
OPEN
C49
OPEN
C50
OPEN
R27
OPEN
C39
4.7µF
TP3
R30
110Ω
0.5%
R29
110Ω
0.5%
C46
15pF
C47
15pF
INP
COM
INN
Figure 1b. MAX12553/MAX12554/MAX12555 EV Kits Schematic (Sheet 2 of 2)
Evaluate: MAX12553/MAX12554/MAX12555
MAX12553/MAX12554/MAX12555
Evaluation Kits
_______________________________________________________________________________________ 9
Figure 2. MAX12553/MAX12554/MAX12555 EV Kits Component Placement Guide—Component Side
Evaluate: MAX12553/MAX12554/MAX12555
MAX12553/MAX12554/MAX12555
Evaluation Kits
10 ______________________________________________________________________________________
Figure 3. MAX12553/MAX12554/MAX12555 EV Kits PCB Layout—Component Side
Evaluate: MAX12553/MAX12554/MAX12555
MAX12553/MAX12554/MAX12555
Evaluation Kits
______________________________________________________________________________________ 11
Figure 4. MAX12553/MAX12554/MAX12555 EV Kits PCB Layout—Ground Planes
Evaluate: MAX12553/MAX12554/MAX12555
MAX12553/MAX12554/MAX12555
Evaluation Kits
12 ______________________________________________________________________________________
Figure 5. MAX12553/MAX12554/MAX12555 EV Kits PCB Layout—Power Planes
Evaluate: MAX12553/MAX12554/MAX12555
MAX12553/MAX12554/MAX12555
Evaluation Kits
______________________________________________________________________________________ 13
Figure 6. MAX12553/MAX12554/MAX12555 EV Kits PCB Layout—Solder Side
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________
14
© 2006 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
MAX12553/MAX12554/MAX12555
Evaluation Kits
Evaluate: MAX12553/MAX12554/MAX12555
Figure 7. MAX12553/MAX12554/MAX12555 EV Kits Component Placement Guide—Solder Side
Revision History
Pages changed at Rev 1: Title change—all pages, 1–14
