AT86RF401U-XI - Atmel - Product.Network

1424F–RKE–12/03

Features

•RF Frequency Range of 264–456 MHz

•6 dBm RF Output into Matched Antenna

•RF Output Power Adjustable over 36 dB with 1 dB Resolu tion

•Phase-locked Loop (PLL) Based Frequency Synthesizer

•Supports OOK Modulation

•Data Bandwidth of Up to 10 Kbps Manchester

•2-volt Operation

•8-bit AVR



 RISC Microcontroller Core

•Minimal Exter nal Components

•Space-saving 20-lead TSSOP

•2 KB (1K x 16) of Flash Program Memory

•128 Bytes of EEPROM

•128 Bytes of SRAM

•In-system Programmable Data and Progr am Memory

•Six I/Os (Serial I/F, LED Drive Outputs, Button Input Interru pts)

•Low Battery Det ect and Brown-out Protection

•Softw are Fine-tuning of VCO Tank Circuit

Applications

•Remote Keyless Entry (RKE) Tr ansmitters

•Wireless Security Systems

•Home Applicance Control ( Lighting Control, Ceiling Fans)

•Radio Remote Control (H obby, Toys )

•Garage Door Openers

•Wireless PC Peripherals (Keyboard, Mouse)

•Telemetry (Tire Pressure, Utility Meter, Asset Tracking)

Description

The Atmel AT86RF401 S mar t RF Microtransmitte r i s a highly integrated, low-cost RF

transm itte r, com bine d with a n AVR R IS C mic roco ntrolle r. It requires only a crystal, a

single LiMnO2 coin cell (CR2032 or similar), three capacitors, an inductor and a tuned-

loop antenna to implement a complete on-off keyed (OOF) wireless RF data

transmitter.

Figure 1. B lock Diagram

PHASE

DETECTOR

OSCILLATOR LOOP

FILTER VCO

PRESCALER

÷ 24

AMP

LOOP FIL

CLOCK

RESET

WATCHDOG

LOW-VOLTAGE DETECT

BROWN-OUT PROTECT

AVR RISC µC

2 KB Flash Program Memory

128 Bytes EEPROM Data Memory

DATA GAIN

TRIM

POWER

SUPPLY

SUPERVISOR

XTAL/CLK

XTALB

AVDD

AGND

ANT

ANTB

B+

DVDD

DGND

IO5

IO4

IO3

SCK/IO2

SDO/IO1

SDI/IO0

RESETB

Smart RF

Wireless Data

Microtransmitter

AT86RF401

2AT86RF401 1424F–RKE–12/03

In-system pro gramma ble , nonvolatile Fla sh program memory and EEPROM data stor-

ag e make p o ssible rapid time -to-market and lower inventory costs.

In-system pro gramma ble , nonvolatile Fla sh program memory and EEPROM data stor-

age make possible rapid time-to-market and lower inventory costs.In-system

programmable, nonvolatile Flash program memory and EEPROM data storage make

po ssi ble rapi d ti me- to- mar ket and lowe r inve nto ry c ost s.Sta ti c c urren t con su mpti on i s

kep t to a mini mum wi t h an ultr a-low current shutdow n mode. Normal operation resumes

w hen a bu tton is pres sed. T his act ivates t he cryst al osci llator ci rcuit tha t serves a s the

clock for the AVR microcon troller.

The RF carrier is synthesized utilizin g an on-board Voltage Controlled Oscillator (VCO).

Optimal tuning of the VCO i s maintained over component tol erance thr ough the use of a

software-controlled sw itched capacitor a rray. Its accuracy is m aintained wi th a PLL

detector that compares the crystal oscillator to a frequency-scaled version (divided by

24) of the RF carrier. The resulting error s ignal adju sts the VCO to produce a very stable

RF carrier.

An interrupt-based bi t-timer struc ture, integral to the AVR microcontrolle r, simplifies the

implem entation of user-speci fic, data-bit encoding routines, such as PWM or Manches-

ter, for modulating the RF carr ier. Thirty-six dB of RF power output control is available to

the user in 1 dB steps and i s addressable in software. Th e RF signal output is placed dif-

fere ntiall y o n a tun ed-loo p antenna , which may be re alized as a count erspr ead copp er

trace on a PCB.

Th e AT 86RF 401 i s fab ricat ed in At mel’s 0.6 µm Mixed Signal CMOS + EEPROM pro-

cess, enabling true system-le vel integration (SLI).

Fi gur e 2 . 20-lead TSSOP

ANTB

LOOPFIL

RESETB

N/C

I/O0 (SDI)

I/O1 (SDO)

I/O2 (SCK)

XTAL/CLK

ANT

N/C

AVDD

DVDD

AGND

DGND

I/O5

I/O4

I/O3

XTALB

AT86RF401

1424F–RKE–12/03

Figure 3. Sample Circuit

Table 1. Recommended Parts List

Pa r t Nu mb er Value

(Common) Value

(315 MHz) Value

(433.92 MHz) Value

(Ext. Loop Filter) Spec if ication

B1 3.6V CR2032, Li Battery

C1 0.01 µF0603, X7R, ± 10%

C2 100 pF 0603, COG, ± 5%

C3 Antenna Dependent Antenna Dependent Antenna Dependent 0603, COG, ± 0.1 pF

C4 Not req’dNot req’dFr equency Dependent 0603, COG, ± 5%

C5 Not req’dNot req’dFr equency Dependent 0603, COG, ± 0.25 pF

L1 82 nH 39 nH Frequency Dependent 1608, ± 5%

R1 Not req’dNot req’dFr equency Dependent 0603, ± 5%

S1 Switch SPST

S2 Switch SPST

S3 Switch SPST

U1 AT86RF401 20-lead TSSO P

Y1 13.125 MHz 18.08 MHz Frequency Dependent

13.125 MHz:

Crystek™ P/N 016757

18.080 MHz:

Cr ystek P/N 016758

ANTB

LOOPFIL

RESETB

IO0/SDI

IO1/SDO

IO2/SCLK

XTAL/CLK

ANT

AVDD

DVDD

AGND

DGND

IO5

IO4

IO3

XTALB

S1 S2 S

RESET SDO

SDI SCLK

V+

C4 C5

V+

C1 B1

SPI Programming Interface

EXTERNAL LOOP FILTER (OPTIONAL)

4AT86RF401 1424F–RKE–12/03

Table 2. Pin Descriptions – 20-lead TSSOP

Symbol Pin Description

ANTB 1Dif ferential Antenna Output

LOOPFIL 2External VCO Loo p-filter Connection.

VVCO is the VCO control voltage.

L1 3External VCO Inductor Connect ion.

VVCO is the VCO control voltage.

L2 4External VCO Inductor Connect ion.

VVCO is the VCO control voltage.

120

10 mA

VDD VDD

VVCO

VDD VDD

VVCO

VDD VDD

VVDD

AT86RF401

1424F–RKE–12/03

RESETB 5

SPI Reset Input: A “low” on this pin resets the device and puts

the part into SPI mode. A logic-high on this pin causes the

device to execute its program if the VDD is above the brown-

out voltage level.

NC 6No Connect. Float Pin.

I/O0 (SDI) 7SPI D ata In/Input/Output 0: General-purpose I/O and button

input. In SPI mo de, this pin ser ves as SDI (Serial Data Input).

I/O1 (S DO) 8SPI Data Out/I nput/Out put 1: Gener al-p urpose I/ O and button

input. In SPI mo de, this pin serves as SDO (Serial Data

Output).

I/O2 (SCK) 9SPI Clock/Input/Output 2: General-purpose I/O and button

input. In SPI mode, this pin se rves as SCK (SPI Clock Input).

XTAL/CLK 10 Crystal/Clock Input: Input to the inverting oscillator amplifier

and input to th e in ternal clock operating circuit. This pin ma y

be driven externally for t est purposes.

Table 2. Pin Descriptions – 20-lead TSSOP (Continued)

VDD

35 kΩ5

To AVR

VDD VDD

Data

nable−

Data

Enable

35 kΩ

To AVR

VDD VDD

Data

Enable−

Data

Enable

35 kΩ

To AVR

VDD VDD

Data

Enable−

Data

Enable

35 kΩ

To AVR

40 pF

6AT86RF401 1424F–RKE–12/03

XTALB 11 Crystal Output: Output from the inverting oscillator amplifier

IO3 12 Input/Output 3: General-purpose I/O and button input

IO4 13 Input/Output 4: General-purpose I/O and button input

IO5 14 Input/Output 5: General-purpose I/O and button input

DGND 15 Digi tal Ground

AGND 16 Analog Ground

DVDD 17 Digital Voltage Su pply

Table 2. Pin Descriptions – 20-lead TSSOP (Continued)

40 pF

Data

Enable

Data

Enable

35 kΩ

To AVR

Data

Enable

Data

Enable

35 kΩ

To AVR

Data

Enable

Data

Enable

35 kΩ

To AVR

AT86RF401

1424F–RKE–12/03

AVDD 18 Analog Voltage Supply

N/C 19 No Connect – Float Pin

ANT 20 Dif ferential Antenna Output

Table 2. Pin Descriptions – 20-lead TSSOP (Continued)

120

10 mA

8AT86RF401 1424F–RKE–12/03

Absolute Maximum Ratings*

Antenna Voltage (Pins 1, 20)......................................−1V to 10V *NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” m ay cause permanent dam-

age to the device. This is a stress rating only;

functional operation of the device at these or

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

condit ions for extended periods ma y aff ect device

reliability.

Operating Temperature........................................−40°C to +85°C

Storage Temperature (without bias) ................−55°C to +125°C

Voltage on VDD with respect to ground............................. 6.0V

Voltage on Pins 2–19 (TSSOP 20)................−0.1 to VDD +0.3V

Table 3. DC Characterist i cs

VDD = 3.3V; fXTAL = 13.125 MHz; fAVR = fXTAL ÷ 16; TA = 25°C unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

Supply

VDD Supply Voltage 2.0 3.3 5.0 V

IDD

Standby Current (off) VDD = 3.3V

TA = 25°C–0.1 0.5 µA

AVR Active –3.4 –mA

Frequency Synthesizer + AVR Acti ve –14.3 –mA

Transmit (FS, AVR and Power Amp activ e) CW modulation –23.2 –mA

Digital Inputs (SDI, SCK, RESETB, IOx)

VIH High-level Input Voltage 0.8* VDD –VDD V

VIL Low-l ev el Input Voltage 0–0.2* VDD V

IIH High-l evel Input Current VIH = VDD , VDD = 5.0V – – 1µA

IIL Lo w-l ev el Input Current VIL = 0V, VDD = 5.0V −140 – – µA

Digital Outputs (SDO, IOx)

VOH Hi gh-level Out put Voltage IOH = −500 µA VDD −0.4 – – V

VOL Low-le ve l Out put Voltage IOL= 2 m A – – 0.4 V

Microcontroller/System

tTX Time from Button Wake-up to RF Outputs Active –0.5 1.0 ms

fAVR AVR Clock Frequ ency – – 1.25 MHz

EELIFE EEPROM Retentio n

Init ial programm ing

conditions:

VDD = 3.3V ± 10%

Temp = 25°C ± 10%

– – 10 years

EECYCLES EEPROM Write/Erase Endurance 2.0V ≤ VDD ≤ 5.0V

−40°C ≤ Temp ≤

85°C– – 100,000 cycles

AT86RF401

1424F–RKE–12/03

Note: 1. Characterized but not guaranteed by test due to dependency on PCB trace antenna

Functional

Description The complete circuit consists of the followin g functional blocks.

Transmitter

Crys tal Osc illator T he c ry sta l osc illator circ uit is de sign ed to w ork w ith cry stal s with fundamental frequen-

cies between 11 and 19 MHz. Forty pF of internal capacitance is connected between

each of the crystal input pi ns and (chip) groun d. Alternat ively, an external clo ck c an be

used for these functions.

This circuit provides the master clock for the entire chip. A program mable divider is used

to provide th e AVR system clo ck.

Radio Frequency Power

Amplifier The RF power amplifier generates a differential output suitable for driving an off-chip

tuned-loop ante nna fr o m the PLL output . The PLL output signal is gated using on-off

keyed (OO K) modulation before transmission . It is used as the RF carrier frequenc y for

the transmitted data stream . The amplifier ca n be configured via software to reduce the

power output by 36 dB (with 1 dB resolution).

Fre quenc y Synthe sizer The frequency synthesizer utilizes a PLL, which consists of a phase detector, a ÷24

prescaler, an on-chip loop filter and an integrated VCO. Th e VCO output is buffered

p rior to th e out pu t a m plifier . The output frequency is 24 times th e crystal frequency. To

offset component tolerance, a switched capacitor array is connected between pins 3

and 4 of the VCO. Thirty-two discrete steps of capacitance are available to tune the

VCO control vo ltage. An inte rnal window comparator monitors the magnitude of the tun-

ing voltage and is used by t he AVR core to det ermine the optimal tuning configurat ion.

Lock Detector The lock detect ion block provides an indication of the state of the phas e lock loop (PLL).

Lock condition is determined by counting the number of cycle slips in a given time

Table 4. Analog/RF Specs

VDD = 3.3V; fXTAL = 13.125 MHz; fAVR = fXTAL ÷ 16; TA = 25°C unless otherwise specified.

Symbol Parameter Conditions Min Typ Max Unit

RF Amplifier

IPA Power Amp Output Current Transmitting (RF “ON”), 0 dB Attenuation –8.6 –mA

PCTLRANGE Power Control Range –36 –dB

PCTLRES Power Control Resolution –1–dB

Crystal Oscillator

fOSC Oscillation Frequency Range 11 –19 MHz

Frequency Synthesizer/PLL

FOUT Output Frequency Range 264 –456 MHz

PHARM1Harmonics I/O Pins Static during RF Transmission

Using PCB Trace Antenna –−60 –dBc

fMOD OOK Modulation Data Rate Using Manchester Data Bit Encoding – – 10 Kbps

10 AT86RF401 1424F–RKE–12/03

period. A number of registers are available to adjust the performance of th e l ock detec-

tor. These inc lude lock delay and unlock dela y timers a s well as a c y cle sl ip counter.

Bandgap Reference Th e devi ce us es a 1 .2V (nom in al) b and gap ref eren ce ge nera to r to provi de c on sist ent

performance over a wide range of input suppl y voltages . This reference voltage is used

throughout the device.

Brown-out Protect ion/Low

Battery Detection The brown-out protection and low battery detection functions consist of a voltage refer-

ence, a sampling block and an autozero comparator. The circuit’s primary operating

mode is brown-out pro tection.

Brown-out Protection The brown-out protection circuit detects when the level of VDD drops below the m inimum

volt age that guarantees proper opera tion. Th e brown-o ut voltage f or this devic e is typi-

cally 1.8 volts.

If a brown-out occurs, the devi ce enters a reset s tate. It s tays in this state until either of

the following occurs:

•The level of VDD increases ~0.1–0.2 volts above the brown-out voltage. T hi s c au s es

the device to enter a wa rm reboo t s t ate.

•The level of VDD drops to ~0 volts, then increases above the POR level. This places

the device into the “cold star t” mode of operation, identical to battery inse rtion.

Low Battery Detection Th e low ba ttery d ete ctio n fe atur e allow s t he pro gram mer to sele ct a v oltage thr eshol d

(1.5–2.7 volt s) for VDD at w hich a warni ng fl ag is issu ed to t he u ser. Fo r exam ple, thi s

warn ing ma y be util i zed to activ ate an I/O port or to change the transmitted message.

Addi tionally, the programmer has the option of defining t he amount of hysteresis on this

threshold. More detail can be found in register descriptions for I/O Enable (IO_ENAB,

$30, page 39) and Bat tery Low Configuration (BL_CONFIG, $35, page 42 ).

AT86RF401

1424F–RKE–12/03

Bit Timer A hardware assist has been included in the AT86RF401 to make transmission of data

easier. Keying of the transmitter is timed by this logic, and in terrupts are generated

when data is needed by the timer or when transmission is complete. The time r also sup-

po rts code that uses poll ing in stead of interrupts . Using polling instead of interrupts may

faci litate higher b it rates. Addition ally, this t imer may b e used to ti me pu lses arrivin g at

the I/O3 pin . This enables the AT86RF401 to b e used to decode th e signal detected by

an ex ternal re ceiver c hip. For ad ditiona l in format ion on how t o implemen t the bit timer,

see AT86RF401 Bit Timer Application Note, available at www.atmel.com.

Bit Tim e r in Tra n smit M od e Bit coding is done by the AVR before data is sent to the bit timer. Bit timin g is controlled

by the c ount value in the Bit Timer Count (B TCNT) register and the two mos t significant

bits in the Bit Timer Control Register (BTCR). Generally the time of each bit is:

where Pxx is the period of each time slot and countval i s the counter value i n the BTCNT

and BTCR registers. P is the AVR clock period that is set in the PWR_CTL register.

countval = {BTCR[7:6], BTCNT[7:0]}.

There are two interrupts associated with transmit mode:

1. T ransmit Buffer Empty Interrupt: This vectors to address 0x04. Flag 0 is set, and,

if enabled, this interrupt is generated when the timer removes the value from the

DAT A bit in the BTCR. This interrupt service routine should load the next transmit

bit into the DATA bit in the BTCR.

2. TXDONE In terrupt: T his vectors to address 0x02. Flag 2 is set, and, if enabled,

an interrupt is generated when the counter has counted down to zero and the

buffer is emp ty. This indicates t hat the trans mission is complete. This interrupt

service routine shoul d turn off the transmitter and turn of f the bit timer using the

mode bits.

Bit Timer in Receive Mode When put into receive mode, the bit timer times pulses arriving at the I/O3 pin. When

enabled, the counte r cou nts up fro m zero and places that valu e in th e BTCNT regi ster

when an edge occurs. If the edge is rising, th e DATA bit in t he BTCR is set. If the edge

is falling , the DA TA bit in the B TCR is res et. This mod e m ay be used to deco de signals

from a receiver chip easily.

Bit Timer in Ge neric

Timer/Counter Mode The bit timer may be used as a generic timer by not allowing it to key off the transmitter.

An inte r r upt is gener ated after the am ount of time dictated by the count value.

Pxx P countval 1+()×=

12 AT86RF401 1424F–RKE–12/03

Watchd og Ti mer When enabling the watchdog timer, the status of the watchdog time is unknown. The

user is advised to execute a WDR instruction before enabling the watchdog. Otherwise,

the device might get reset before the first WDR after enabling is reached. To prevent the

uni nte nti on al di sa blin g o f th e watchdog , a s pecial turn-off pro cedure mus t be followed

when the watchdog is disabled. Refe r t o the description of the Watchdog Timer Cont ro l

R egister on page 38 for detai ls (see R egiste r $22 in I /O Mem ory). The watch dog ti mer

prescaler determines t he number of system clocks that occur bef ore the watchdog reset

is asserte d. The system clock is determined by Bits[7:5] of the AVR_CONFIG reg ister.

Reset and Interrupt

Handling T he AT86RF4 01 Reset an d Interrup t vectors are defined in Table 5. The I-bi t in the sta-

tus register must be set to enable the interrupts.

The most typical and general program setup for the Reset and Interrupt Vector

Addresses are:

Rese t Sources The AT86RF401 has several sources of reset:

•Power-on Reset: The device is reset when the supply vol tage is applied between the

VDD and GND pins. There are 106 c ycles of delay between Power-on Reset

occurr ing and the part becoming active. This is to ensure that the power is stable.

•External Reset: The device is r eset when a log ic l ow l e ve l i s prese nt on th e RESETB

pin. This resets al l I/O Regi s ters and puts the pa r t into SP I mode. The I/O Registers

may be read a nd written by the SPI interface after two AVR System Clocks.

•Watchdog Reset: This is similar to power-on reset but is caused by the watchdog

timer and does not have a 106 cycle delay pr ior to becoming ac tive.

•Brown-out Rese t: This is caused by the b atte r y vo ltage dropping below the Brown-

out Threshold voltage trip point.

•Button Reset (sof tw are reset): T he part is placed into a special reset state by

software. The p ar t is released from rese t when a properly c onfigured button is

activated, and the p ar t is not in external reset or brown-ou t reset. In the button reset

state, most I/ O registers are not reset, and there i s n o t ime d e l ay bef or e be co min g

active.

Table 5. Reset and Interrupt Vectors

Vector

Number Program

Address Source Interrupt Definition

1 $000 RESETB, Watchdog, Buttons Hardware Pin or Watchdog or

Button Reset

2 $002 Transmission Done (TXDONE) Bit Timer Flag 2 Interrupt

4 $004 Transmi t Buffer Empty Bit Timer Flag 0 Interrupt

Address Labels Code Comments

$000 jmp RESET ; Reset handler

$002 jmp BT_F2_ISR ; Bit timer flag 2 interrupt service routine

$004 jmp BT_F0_ISR ; Bit timer flag 0 interrupt service routine

$006 MAIN: <instr> xxx ; Main program start

… … … …

AT86RF401

1424F–RKE–12/03

During power-on reset and watchdog reset, all I/O registers are se t to their initial value s,

and the program starts execution from address $000.

Note: The instruction placed in address $000 must be an RJMP (relative jump) instruction or a

JMP (absolute jump) to the reset handling routine. If an RJMP or JMP instruction is not

present at addr ess $000, the part is placed into a “no program” reset state. This is to pro-

tect the part from fetching instructions when no program is present.

Interrupt Respo nse Time The interrupt execut ion r esponse for all the enabled AVR inte rr upts is a minimum of four

clock cycles. After the four clock cycle s, the progr am vector address for the actual inter-

rupt handling routine is executed. During this four clock cycle period, the Program

Counte r is pushed ont o th e st ack. The vect or is a jump to the interrupt routine, and this

jump takes two clock cycles. If an interrupt occurs during execution of a multi-cycle

instruction, this instruction is completed before the interrupt is served.

A return from an interrupt handling routine takes four clock cycles. During these four

clo ck cycle s, the Program Counter is p opped b ack from the stac k. W hen AVR exits fr om

an i nte rrupt, it will always return to the main program and execute one more inst ruction

before any pending interrupt is served.

Note: The Status Register (SREG) is not saved by the AVR hardware. This must be performed

by user software when r equired.

Memory Programming

Program Memory Lock

Bits The AT 86RF401 microtransmitter provid es two lock bits tha t can be left unprogrammed

(“1”) or can be programmed (“0”) to obtain t he additional featur es listed in Table 6.

Note: The lock bits can only be erased with the Chip Erase operation.

In-system Flash and

EEPROM The AT86RF401 offers 2 Kbytes (1K x 16) of in-system reprogrammable Flash program

memory and 128 bytes of EE PROM data memory. This memory can b e programmed

serially v ia the SPI interface.

SPI Interface Both the program and data memory arrays can be programmed using the serial SPI bus

while RESETB is pulled to GND. The serial interface con sists of pins SCK, SDI (input)

and SDO (output ).

W hen programming, an auto-erase cycle is built into the self-timed programming opera-

tion, and there is no need to first execute th e Chi p Erase instruction. The Chip Erase

operation sets every memory location in the EEPROM array to $FF.

Either an external system clock is supplied at pin XTAL/C LK or a crystal needs to be

co nnect ed a cross pi ns XTA L/C LK and XTALB . The minim um low and h igh p eriod s for

the serial clock (SCK) input are defined as follows:

Low: 4 XTAL Clock Cycles High: 16 XTAL C lock Cy cles

Table 6. Lock Bit Prot ect ion Modes

Program Lock Bits

Protection Type

Mod

eLB1 LB2

1 1 1 No program lock features

201

Further serial (SPI) programming of the EEPROM is disabled (both

program and data memory).

3 0 0 Same as mode 2, but Verify is also disabled

14 AT86RF401 1424F–RKE–12/03

Serial Programming

Algorithm Refer to Figure 4 (page 15), Figure 5 (page 16) and Figure 6 (page 17). To program and

v erify th e AT 86RF401 in the se rial p rogrammi ng mo de, t he follow ing sequence i s

recommended.

Power-up Sequence:

1. Apply power between VDD and GND while RESETB and SCK are set to “0”. If a

crystal is not connected across pins XTAL and XTALB, apply a clock signal to the

XTA L pin. If the programmer can not guarantee that SCK is held low duri ng

power-up, RESET B must be given a positive pulse after SCK has been set to “0”.

2. Wait for at least 20 ms and enable serial programmin g by sending the Program-

ming Enable instruc tion to pin SDI . This must o ccur prior to any program/erase

operations.

3. If a chip erase is performed, wait 4 ms , give RESETB a positiv e pulse and start

over again from Step 2.

4. The array is programme d one byte at a time by supply ing the address and data

together with the appropriate Write instruction. The memory location is first auto-

matically erased before new data is written. The ne xt byte can be writte n af ter

4ms.

5. Any mem ory location can b e ver ified by u sing the Read instruction, which

returns the content at the sel ected address at serial output SDO.

6. At the end of the progra mming session, RE SETB must be set high to commence

normal operation.

Signature Bytes A ll Atmel microcontrollers have a three-byte signature code that identifies the device.

For t he AT86RF 401, the signature by tes ar e:

•0x000: 0x1E (indicates m anufactured by Atmel)

•0x001: 0x91 (indicates 2 Kbytes Flash progr am mem ory)

•0x002: 0x81 (indicates AT86RF401 when 0x001 is 0x91)

AT86RF401

1424F–RKE–12/03

Data EEPROM Acce ss from the AVR

Note: a = address high bits

b = address low bits

H = 0: Low byte, 1: High byte

o = data out

i = data in

x = don’t care

1= lo ck b i t 1

2= lo ck b i t 2

Fi gur e 4 . Serial Programming and Verify

Notes: 1. When writing, data is clocked on the rising edge of CLK.

2. When reading, data is clocked on the falling edge of CLK. See Figure 5 for an

explanation.

Table 7. AT86RF40 1 Serial Programming Instruction Set

Instruction

Instruction Format

OperationByte 1 Byte 2 Byt e 3 Byte 4

Programming

Enable 1010 1100 0101 0011 x xxx xxxx xxxx xxxx Enable Serial Programming after

RESETB goes low.

Chip Erase 1010 11 00 100x xxx x xxxx xxxx xxxx xxxx Chip erase EEPROM

Read Program

Memory 0010 H000 0000 00aa bbbb bbbb oooo oo oo Read H (hi gh or l ow) data o from Pro gr am

memory at word address a:b

Write P r ogram

Memory 0100 H000 0000 00aa bbbb bbbb iiii ii ii Write H (high or low) data i to Program

memory at word address a:b

Read

EEPROM Memory 1010 0000 0000 0000 xbbb bbbb oooo oooo Read data o from EEPROM memory at

address b

Write

EEPROM Memory 1100 0000 0000 0000 xbbb bbbb iiii ii ii Wri te data i to EEPROM memory at

address b

Wr ite Lock Bits 1010 11 00 111x x21xxxxx xxxx xxxx xxxx Write lock bi ts. S e t bits 21 = “0” to

program lock bits.

I/O Read 10110000 0000 0000 00bbbbbb oooo oooo Read data 0 from I/ O memo ry address b

I/O Write 11010000 0000 0000 00bbbbbb iiii iiii Write data i to I/O memo ry address b

Read Signature Byte 0011 0000 000x xxx x xxxx xxbb oooo oooo

BAT

SCK

SDO

SDI

RESETB

XTAL

XTALB

2.0–3.5V

CLOCK IN

DATA OUT

INSTR. IN, DATA IN

GND

6 to 20 MHz

AT86RF401

16 AT86RF401 1424F–RKE–12/03

Figure 5. Serial Programming Waveforms

Note: This device includes an integrated 128-byte EEPROM, which is accessed by three registers located in the I/O memory space.

These are the DEECR, DEEDR and DEEAR registers. For more information, refer to I/O Register Description.

AVR Core

Architectural Overview T he fast-access register file conc ept con tains 32 x 8 -b it gene ral-purpose working regis-

ters with a single clock cycle access t ime. This means that during one single clock cycle,

one Arithmetic Logic Unit (ALU) operation is executed. Two operands are output from

th e regi ster fi le, th e ope rati on is e xecu ted, and the res ult is st ored b ack i n the re gis ter

fil e in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for

Data Space addressing, enabling efficient address calculations. One of the three

addres s pointers is also used as the addr ess pointer for look-up tables in Flash program

m emory. These added fu nc tio n regis te rs are the 16 -bit X -r eg ist er, Y- re gi ster and Z-

The A LU supports arithmetic and logic operations bet ween registers or between a con-

sta nt and a register. Sing le r egis ter ope ratio ns are a lso execut ed in the A LU. F igure 6

shows the AT86RF401 AV R arc hitecture.

In addition to the register operatio n, the conventional m e mo ry addressing modes can be

us ed on th e re gister f ile a s wel l. T his i s enab led b y th e fact t ha t th e regis te r file is

assigned the 32 lowest data space addresses ( $ 0 0 –$1F), allowing them to be accessed

as though they were ordinary memory locations.

The I /O memory s pace c ontains 64 a ddresse s for CPU peri pheral funct ions as Con trol

Registers, Timer/Counters, A/ D converters and other I/O functions. The I/O Memory can

be ac cessed dire ctly or as the Data Sp ace locations following those of th e register file,

$20–$5F.

SERIAL DATA INPUT (SDI)

SERIAL DATA OUTPUT (SDO)

SERIAL CLOCK INPUT (SCK)

MSB

MSB LSB

LSB

AT86RF401

1424F–RKE–12/03

Fi gur e 6 . AVR Core Architecture

The AVR u ses a Harvard a rchi tectur e conc ept, w ith se parate m em ories a nd bus es f or

program and data. The program memory is executed with a two-stage pipeline. While

o n e i n s tr u ct i on i s b e in g exec ut e d, t he next in str u c tion i s pr efetched from th e program

memory. This concept enables ins tructions to be executed in every clock cycle. The pro-

gram me mory is i n-system , reprogrammable Flash memory.

With the jump and call instructions, the whole 1K word address space is directly

accessed. Most AVR instructions have a single 16-bit word format. Every program

mem ory address contains a 1 6- or 32-bit i ns truction.

During interrupts and subroutine calls, the return address program counter (PC) is

stored on the stack . The stack is effectively allocated in the general d ata SR AM, and

conseq uently the stack size is only limited b y the total SRAM size and the usage of the

SRAM . All user programs m ust in itialize the SP in the reset routine (be fore subro uti nes

or interrupts are executed). The 7-bit stack pointer SP is read/write accessible in the I/O

space.

The 1 28-byte d ata SR AM ca n be easil y a ccessed t hrough t he five different ad dressing

modes supported in the AVR architecture.

The memory sp aces in the AVR architec ture are all linear and regular memory m aps.

1K x 16

Program

Memory

Instruction

Decoder

Program

Counter

Control Lines

32 x 8

General

Purpose

Registers

ALU

Status

and Control Bit Timer

SPI Unit

Programmable

Clock Divider

128 x 8

EEPROM

Data Bus 8-bit

Brown-out/Low

Battery Detector

128 x 8

Data

SRAM

Direct Addressing

Indirect Addressing

Transmitter

Watchdog

Timer

I/O Lines

18 AT86RF401 1424F–RKE–12/03

A flexi b le inte rrup t mo du le ha s its c ont rol re giste rs in the I/O s pace w ith an additional

glob al interrup t enab le bit in the st atus re gister. All interru pts hav e a sepa rate in te rrupt

ve ctor in t he i nte rrupt vecto r tab le at the beginning of the progra m memory. The inter-

rupts have p riority i n accordanc e with their interrupt ve ctor po sition; the lower the

interrupt vector address, the higher the priority.

Fi gur e 7 . Memory Maps

$000

$3FF

Program Memory

Application Flash Section

AT86RF401

1424F–RKE–12/03

General-purpose

Re gis t er Fi le Figure 8 shows the structure of the 32 general-purpose working registers in the CPU.

Fi gur e 8 . AVR CPU General-purpose Working Registers

All the register op erating instructions in the instruction set have direct and singl e cycle

access to all registers. The only exception is the five constant arithmetic and logic

inst ruct i ons (SB CI, SUB I, CP I, ANDI and ORI) b et we en a c onst an t and a reg ist er, and

the LDI instruction for load immediate constant data. These instructions apply to the

se cond half of the registers in the register fil e, R1 6...R31. T he general SBC, S UB, CP,

AND and OR and all other operations between two registers or on a single register apply

to the entire register file.

As shown in Figure 9, ea ch register is also ass igned a data memory address, mapping

the registers directly into the first 32 l oc ati ons of the user data space. A lthough not being

physically implemented as SRAM locations, this memory organization provides great

flexibil ity in access of the regi sters, as the X, Y a nd Z registers can be set to index any

7 0 Addr.

R0 $00

R1 $01

R2 $02

…

R13 $0D

R14 $0E

R15 $0F

R16 $10

R17 $11

…

R26 $1A X-register low byte

R27 $1B X-register high byte

R28 $1C Y-register low byte

R29 $1D Y-register high byte

R30 $1E Z-register low byte

R31 $1F Z-register high byte

20 AT86RF401 1424F–RKE–12/03

The X, Y and Z Registers Th e registers R26...R31 have some added functions to their gene r al -pu r po s e u sage.

These registers are address pointers for indirect addressing of the data space. The

three indirect addres s registers X, Y and Z are defined as shown in Figure 9.

Figure 9. The X, Y and Z Registers

In the d ifferent addressing modes, t hese address registers have functions as fixed dis-

placement, automatic increment and decrement (see the descriptions for the different

instructions).

Ari thmetic Logi c Unit

(ALU) T he hi gh-p erfo rman ce AVR ALU op erat es in d irect con nec tion w ith all the 3 2 ge neral -

purp ose work ing registers. Within a single clock cycle, ALU operati ons betw een regis-

ters in the register file are executed. Th e ALU operations are divided into three main

categ ories: arithm etic, logical and bit-func tions. Th e multiplier is not present in this ver-

sion of the core. Therefore, the MUL instruction is not s upported.

In-system S elf-

programmable Flash

Program Memory

The A T86RF401 contains 2 K by tes of on-chip Flash memory for program st orage. Since

all instructions are 16- or 32-bit words, the Flash is organized as 1K x 16.

The Fl ash mem ory has an endurance of at lea st 1000 write/eras e cycles. The PC is 10

bits w ide, thus addressing t he 1024 program memo ry locations . See the Memory Pro-

gramm ing section (page 13) for a detailed description o n Flash dat a serial downl oadi ng.

Constant tab les can b e allocated within th e entire program memory address space (see

Table 22, Instruction Set, page 45).

15 XH XL 0

X Register 70 0 7 0

R27 ($1B) R26 ($1A)

15 YH YL 0

Y Register 70070

R29 ($1D) R28 ($1C)

15 ZH ZL 0

Z Register 70 0 7 0

R30 ($1F) R31 ($1E)

AT86RF401

1424F–RKE–12/03

SRAM Data M emor y Figure 10 shows how the AT86RF401 SRAM memory is organized.

Fi gur e 1 0. SRAM Organization

Th e lo wer 224 Dat a Me mor y loca tio ns ad dr ess the Re gist er F ile, th e I/ O Memory and

the int ernal data SR AM. The first 96 locat ions address th e Register File + I/O Memory,

and the next 128 locations addre ss the internal data S R AM.

The five different addressing modes for the data memory cover: Direct, Indirect with Dis-

pl ac em en t, Indirec t , In di re ct wit h Pr e-d e cr em en t, and Ind ir e c t wi t h Post -i nc re ment. In

the register f ile, re giste rs R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect wit h Displacement mode features a 63 address locati ons reach from the

base address given by the Y or Z register.

When using register in direct addressing modes w ith automatic pre-decrement and post-

incre ment, the address registers X, Y and Z are dec remented an d increme nted.

The 32 general-purpose working re gisters, 64 I/O registers and the 128 bytes of internal

data SRAM in the AT86RF401 a re all accessible through all these addressing modes.

Program and Data

Ad d ressing Modes The AT86RF401 AVR Enhanced RISC microcontroller supports powerful and efficient

addres sing modes for access to the program mem ory (Fla sh) a nd data memory (SRAM,

R egister File an d I/O Memo ry). This secti on des cribes t he d iffere nt addres sing mod es

supp orted by the AVR architec tu re . In the figures, OP means the operation code part of

the i nstruction word . To simplify, not all figures show the exact location of the a ddress-

ing bits.

R29

R30

R31

I/O Registers

$00

$01

$02

...

$3D

$3E

$3F

...

$0000

$0001

$0002

$001D

$001E

$001F

$0020

$0021

$0022

...

$005D

$005E

$005F

...

Data Address Space

$0060

$0061

$00DE

$00DF

...

Internal SRAM

22 AT86RF401 1424F–RKE–12/03

The operand is contained in registe r d ( Rd ).

Registers Rd and Rr Fi gur e 1 2. Direct Register Addressing, Two Registe rs

Op era nds ar e co ntain ed i n regi ster r (Rr) a nd d (R d). The r esult is st ored in re gister d

(Rd).

I/O Direct Fi gur e 1 3. I/O Direct Addressing

Ope rand address i s con tained i n 6 bits of th e in stru ction word. “n” is the destination or

source register address.

AT86RF401

1424F–RKE–12/03

Data Direct Fi gur e 1 4. Direct Data A ddressing

A 16-bit Data Address is contained in the 16 LSBs of a two-word instruction. Rd/Rr

speci fy the des tina tion or source register.

Data Indirect with

Displacement Fi gur e 1 5. Data Indirect with Displacement

Operand addres s is the result of t he Y or Z register contents added to the a ddress con-

taine d in 6 bits of the instruction word.

Data Indirect Fi gur e 1 6. Data Indirect Addressing

Operand address is the contents of the X, Y or Z register.

OP Rr/Rd 16

15 0

16 LSBs

$00

$DF

20 19 Data Space

Data Space $00

$DF

Y OR Z - REGISTER

OP an

05610

Data Space $0000

$DF

X, Y OR Z - REGISTER

015

24 AT86RF401 1424F–RKE–12/03

Data Indirect with

Pre-decrement Figur e 1 7. Data Indirect Addressing with Pre-decrement

The X, Y or Z re gister is decremented before the operation. Operand address is the

decrement ed cont ents of the X, Y or Z regist er.

Data Indirect with

Post-increment Figure 18. Data Indirect Addres s ing with Post -increment

The X, Y o r Z regist er i s increm ente d after the operatio n. Opera nd addre ss is the c on-

tent o f th e X, Y or Z register prior to incrementing .

Constant Addressing Using the LPM Instruction

Fi gur e 1 9. Code Memory C onstant Addressing

Constant byte address is specifi ed b y th e Z register c o n tents. The 10 MSBs select word

addre ss (0–1K). For LPM, the LSB selects low byte if cleared (LSB = 0) or high byte if

set (LSB = 1).

Data Space $0000

$DF

X, Y OR Z - REGISTER

015

-1

Data Space $0000

$DF

X, Y OR Z - REGISTER

015

$3FF

AT86RF401

1424F–RKE–12/03

Indirect Program Addressing,

IJMP and ICALL Fi gure 2 0. Indirect Program Me mory Addressing

Program execution continues at address contained by the Z register (i.e., the PC is

loaded with the contents of the Z register).

Relative Program Addressing,

RJMP and RCALL Fi gur e 2 1. Relativ e Program Memory Addressing

Program execution con tinues at address PC + k + 1. T he re lative address k is from

−204 8 to 2047.

$3FF

26 AT86RF401 1424F–RKE–12/03

EE PROM D ata Mem ory The A T86RF 401 contains 128 bytes of data EEPRO M memory. It is organized as a sep-

arate data space in which single bytes can be read and written. The access between the

EEPROM a nd the CPU is described in the Memory Programming section (page 13).

Memory Access Times

and Instruction

Execut i on Timing

This section describes the general access timing concepts for instruction execution and

internal memory access.

The AVR CPU is driven by the System Clock Ø gen erated from th e mai n osc illat or for

the ch ip. A program mable clock divid er generate s this clock fro m the crystal oscillator

input.

Fi gure 22 s hows t he pa ralle l instru ctio n fetch es a nd ins truct ion e xecu tions en ab led b y

the Ha rvard architecture and the fast-access register file concept. This is the basic pipe-

lining concept to obt ain up to 1 MIPS p e r MHz with the corr esponding unique results for

functions per cost, functions per clocks an d functions per power unit.

Fi gur e 2 2. The Parallel Instruction Fetches and Instruct ion Executions

Figu re 23 show s the interna l timing co ncept for the regis ter file. In a si ngle clock cycle ,

an ALU operation using two re gister operands is executed, and the result is stored back

to the destination register.

Fi gur e 2 3. Single Cycle ALU Operation

System Clock Ø

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

T1 T2 T3 T4

System Clock Ø

Total Execution Time

ALU Operation Execute

Result Write Back

T1 T2 T3 T4

AT86RF401

1424F–RKE–12/03

The i nternal data SR AM acc ess is perfo rm ed in two Sys te m Clock cycl es as describe d

in Figure 24.

Fi gur e 2 4. On-chip Data SRAM Access Cycles

All I /Os and peripherals a re placed in the I/O space. The I/O locations are accessed by

the IN and OUT instructions, transferring data between the 32 general-purpose working

registers and the I/O space. I/O reg isters within the address range $00 –$1F are directly

bit-acces s ible using the SBI and CBI instructions. In these registers, the value of single

bits can be checked by using the SBIS and SBIC instructions. Refer to Table 10,

“Instruction Set Manual,” on page 44 for more details. When using the I/O specific com-

ma n ds I N an d O UT , the I/ O addres ses $00–$3F mus t be u sed . Wh en a d dr essi ng I/O

registers as SRAM, $20 must b e added to these addresses.

For com patibil ity w ith future device s, rese rve d bits shou ld be w ritten to “0” if accessed.

Reserved I/O memory addresses should never be written.

So m e of the st atu s fl ags ar e cleared by wr i ti ng a logical “1” to them. Note that the CBI

an d SBI instruct ions will operate on all bits in the I/O register, writing a “1” back into any

flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers

$00 to $1F only.

The I/O and p e ripheral s control reg isters are explained in the fo llowing secti ons.

System Clock Ø

Write

Read

Data

Address

T1 T2 T3 T4

Prev. Address

Read Write

28 AT86RF401 1424F–RKE–12/03

I/O Memory

The I/O space definition of the AT86RF401 is shown in Table 8 below.

Note: Reserved and unused locations are not shown in the table.

Table 8. AT86RF401 I/O Space Definitions

Address Hex Nam e Function

$3F SREG Status Register

$3E SPH Stack Pointer High Register (program to 0 x 00)

$3D SPL Stack Pointer Low Register

$35 BL_CONFIG Battery Low Configuration Register

$34 B_DET Bu tt o n D e te c t Reg is ter

$33 AVR_CONFIG AVR Configuration Register

$32 IO_DATIN I/O DATA I N Register

$31 IO_DATOUT I/O DATA OUT Register

$30 IO_ENAB I/O Enable Register

$22 WDTCR Watchdog Timer Control Register

$21 BTCR Bit Timer Control Register

$20 BTCNT Bit Timer Count Register

$1E DEEAR Data EEPROM Address Register

$1D DEEDR Data EEPROM Data Register

$1C DEECR Data EEPROM Control Register

$17 LOCKDET2 Lock Detector Configuration Register 2

$16 VCOTUNE VCO Tuning Register

$14 PWR_ATTEN Power Attenuation Control Register

$12 TX_CNTL Transmitter Control Register

$10 LOCKDET1 Lock Detector Configuration Register 1

AT86RF401

1424F–RKE–12/03

I/O an d Control

Registers The AT86RF401 I/Os and peripherals are placed in the I/O space. The various I/O loca-

tions are accessed by the IN and OUT instructions transferring data between the 3 2

general-purpose working registers and the I/O space. I/O registers within the address

rang e $0 0–$1F a re dire ctly b it-acc essibl e using the SBI a nd CBI ins tructi ons. In t hese

regi sters, th e val ue of sing le bits can be checke d by usi ng th e SB IS an d SBIC i nstruc-

tions . Refer to Ta ble 22 on page 45 for m ore de tails. The di fferen t I/O an d peri phera ls

control registers are explained in the following se ctio ns.

Transmitter Control Register Descriptions

Lock Detector Configuration Register 1 – LOCKDET1

•Bits[7:5]

Reserved.

•Bit[4]: UPOK

If set hi gh, this bit resets th e un lock counter. The bit is leve l s ensitive, and the unlock

counter will not count unless this bit is set to “0”. Leaving this bit high essentially dis-

ables the unlock detector.

•Bit[3]: ENKO (Enab le Key on Bit)

If set to “1”, the rising edge of TXK starts the blackout period, during which any cycle

slips are ignored and do not affect the unlock circuit.

•Bit[2]: BOD (Black Out Disable)

W hen set hi gh, c ycle s lips ar e c ount ed imme d iatel y b ut only if LO CK is ass ert ed h igh

(TX_CNTL b[2]).

•Bits[1:0] CS[1:0]: Cycle Slip Counter

The se two b its determ ine how many cycle slips a re allo wed befor e the L OCKDETECT

signal is set low. The cycle slips are not counted unless the blackout lo gic is either dis-

abled or the blackout window has passed.

Table 9. Cycle Slip Counter Definition

Bit 76543210

$10 – – – UPOK ENKO BOD CS1 CS0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 00000000

CS[1:0] Functionality

00 1 cycle slip causes unlock condition

01 2 cycle slips cause unlock condition

10 3 cycle slips cause unlock condition

11 4 cycle slips cause unlock condition

30 AT86RF401 1424F–RKE–12/03

Transmit Control Register – TX_CNTL

•Bit[7:6]

Reserved.

•Bit[5]: TXE, Transmitter En able

Thi s bit, whe n set, turns on the phas e lock ed l oop (PLL) R F fr equency synthesiz er but

should not be used to modulate the RF carrier or excessive spurious noise may result.

•Bit[4]: TXK, Transmitter Key

Th is bit, w hen se t, tu rns on the RF po wer am pli fier. It should b e u sed to modulate t he

RF carrier manually. This bit should be cl ear ed when the bit tim er is configured in t r ans-

mit mode.

Fi gur e 2 5. Modul ati on Control Lo gic

•Bit[3]

Reserved.

•Bit[2]: LOC, P LL Lock

This bit is set when the frequency synthesizer in the tra nsmitter is lock ed. Typically, the

programmer should test the status of this bit to insure the RF carrier is stable prior to

turning on the RF power amplifi er.

Power Attenuation Control Register – PWR_ATTEN

This register is used to select the power attenuation level. The total power attenuation is

the sum of the coarse attenuation and fine attenuation. As an example , to obtain 15 dB

of attenuation, the coarse setting of 12 dB and fine setting of 3 dB would be selected. To

obtain 12 dB coarse attenuation, Bits[5:3] would be set to [010]. To obtain 3 dB of fine

attent uati on would require Bits[2:0] to be set to [011].

Note: Maximum RF output power occurs when Bits[5:0] = [000000].

•Bits[7:6]

Reserved

Bit 76543210

$12 – – TXE TXK –LOC – –

Read/Write R/W R/W R/W R/W R/W RR/W R/W

Initial Value 00000000

Bit Timer

TXK

ON/OFF

POWER

AMP

PLL RF

IN RF

OUT

Bit 76543210

$14 – – PCC2 PCC1 PCC0 PCF2 PCF1 PCF0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 00000000

AT86RF401

1424F–RKE–12/03

•Bits[5:3]: PCC, Pow er Control (coarse)

Atten uates the output power in 6 dB ste ps.

Table 10. Coarse Power Control Definition

•Bits[2:0]: PCF, Power Control (fine)

Atten uates the output power in 1 dB ste ps.

Table 11. Fine Power Control Definition

VCO Tu ning Register 6 – VCOTUNE

Note: * These values are unknown at initial startup.

•Bits[4:0]: VCO Tuning Capacitor Array

This devi ce requires the use of an external inductor to tune the VCO. Tolerance of the

induct or, coupled with proc ess variation of the de vice, can lead to variations in the t un-

ing point of the VCO. A switched array of tuning capacitors has been added internally to

the device in order to “fine tune” the VCO. This capacitance is switched across pins 3

and 4 (L1 and L2) of the device. The capacitor arra y i s set by VC OTUNE [4:0 ] and is

com p r is ed of the f ollowing switched capacit ance levels:

PCC[5:3] Output Attenuation

000 0 dB

001 6 dB

010 12 dB

011 18 dB

100 24 dB

101 30 dB

110 Invalid

111 Invalid

PCF[2:0] Output Attenuation

000 0 dB

001 1 dB

010 2 dB

011 3 dB

100 4 dB

101 5 dB

110 Invalid

111 Invalid

Bit 7 6 5 4 3 2 1 0

$16 VCOVDET[1] VCOVDET[0] –VCOTUNE[4] VCOTUNE[3] VCOTUNE[2] VCOTUNE[1] VCOTUNE[0]

Read/Write R R R/W R/W R/W R/W R/W R/W

Initial Value * * 0 0 0 0 0 0

32 AT86RF401 1424F–RKE–12/03

Table 12. VCO Tuning Capacitor Definition

VCOTUNE[4:0] Capacitance (pF)

00000 0

00001 0.03

00010 0.06

00011 0.09

00100 0.12

00101 0.15

00110 0.18

00111 0.21

01000 0.24

01001 0.27

01010 0.30

01011 0.33

01100 0.36

01101 0.39

01110 0.42

01111 0.45

10000 0.48

10001 0.51

10010 0.54

10011 0.57

10100 0.60

10101 0.63

10110 0.66

10111 0.69

11000 0.72

11001 0.75

11010 0.78

11011 0.81

11100 0.84

11101 0.87

11110 0.90

11111 0.93

AT86RF401

1424F–RKE–12/03

•Bits[7:6]: VCO Voltage Detector

The V C O Voltage Detector circuit monit ors the leve l of the VCO control voltage. This cir-

cuit, along with the VCO Switch Caps and the Lock Detect circuit, is intended for use

with a software al gorithm to tune the VCO such that the VCO control voltage is centered

approx imatel y at 1.1V.

The Volta ge Detecto r circuit con sists of two comparators with fi xed refere nce voltages

of V1 (lower reference voltage) and V2 (upper reference voltage). The VCO Control

Voltage is compared to these two reference voltages and generates the state table

listed in Table 13. The s tate of these com parators is output to Bits 7 and 6 ( Vcodet[1:0])

of the VCOTUNE register.

Lock Detector Configuration Register 2 – LOCKDET2

•Bit[7]: EUD

A “1” enables the unlock dete ct logic.

•Bit[6]: LAT (Lock Always True)

Forces t he lockde tect s ign al to “1” at the output of the lock detect circuitry. This may be

useful if the lock detec t signal is not going high for some reason, a nd a power amp inter-

lock has been implemented, and the user wishes to enable the power amp output stage.

Table 13. VCO Window Comparator States

VCOvde t[ 1:0] VCO Contr ol Voltage

00 Ab ove low e r comp arator threshold and below up per comparator

threshold. Control Voltage is within the valid window of operation.

01 Below both thresholds. Control Voltage is outside the recommended

window of operation.

10 Above both thresholds. Control Voltage is outside the recommended

window of operation.

11 Not a va lid state.

Bit 7 6 5 4 3 2 1 0

$17 EUD LAT ULC[2] ULC[1] ULC[0] LC[2] LC[1] LC[0]

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

34 AT86RF401 1424F–RKE–12/03

•Bit[5:3]: ULC[2:0]

The unlock count (ULC) bits count a certain number of ref er e nce clocks, after which the

unlock detect circuit looks for a number of cycle slips determined by CS[1:0] before

making the loc detect signal go low. The ULC bits essentially control the blackout period

of the unlock detect circuit. The unlock counter is reset by th e KEY signal rising (if

ENKO is as se rted), or by the LOC rising edge, or by the UPO K signal being set high.

Table 14. PLL Unlock Counter Definition

•Bits[2:0]: LC[2:0]

The Lock Count (LC) bits control a counter that, after a number of reference clocks,

cause lock detect to go hi gh. This cou nter will reset if a cycle slip or a reset signal occurs

(which happens if T XE goes low), if an out-of- lock condition occu r s, if the crystal oscilla-

tor frequency is too low, or if the VCO feedback frequenc y is too low.

Table 15. PLL Lo c k Counte r Definition

ULC[2:0] Number of REF

Clocks of Delay

000 8

001 16

010 32

011 64

100 128

101 256

110 512

111 1024

LC[2:0] Number of REF Clocks of Delay

000 8

001 16

010 32

011 64

100 128

101 256

110 512

111 1024

AT86RF401

1424F–RKE–12/03

EEPROM Control Regis ter Descriptions

Data EEPROM Control Register – DEECR

•Bits[7:4]

Reserved. These bits should be “0” when written; otherwise, results will be

unpredictable.

•Bit[3]: EEPROM Busy Bit

Initially set to “0”. This bit will be set high during writes to the EEPROM.

•Bit[2]: EEPROM Unlock Bit

Set this bit to “1” before writing the EEPROM. Res et this bit to “0” after the write is com-

plete. This bit should be left in the zero state when the EEPROM is not being used,

which will protect the EE PRO M data during po wer transients.

•Bit[1]: EEPROM Load Bit

To write the EEPROM, use th e following procedure:

Note: Because of noise and power considerations, the EEPROM should not be written while

the transmitter is enabled.

1. Set the un lock b i t.

2. Wr ite the address of the first byte to the DEEAR.

3. Set the load bit. T his locks the page address in the DEEAR. Keep the unlock bit

set.

4. Wr ite the desired data to the DEEDR register . This byte is loaded into the

EEPROM and will be written when the load bit is later deasserted.

5. If it is desired to write another byte in the same page, write the new address to

the DEEAR register, and a new byte to the D E E DR reg i ster. Continue unti l a ll

bytes that are to be written are l oaded into the EEPROM. Byte s may only be

loaded to an address once. There are eight bytes per page.

6. De a ss e rt th e load bit. Th i s starts th e writ e operation. Some ti me afte r load is

deasserted, the busy bit will go high. Another read or w rite operatio n ma y not be

started until the b usy bit has returned to “0”. Writes take approximately 4 ms to

complete. A gain, the unlock bit must still be set when deasserting the load bit.

7. After all writes are complete, write “0” to the unlock bit.

•Bit[0]: EEPROM Read Bit

To read the E EPROM use the following procedure:

1. Wr ite the addres s to the DEEAR.

2. Set the read bit.

3. Read the d ata register. The read bit will reset i t self.

4. If another read needs to be done, repeat steps 1–3 again.

Bit 76543210

$1C – – – – BSY EEU EEL EER

Read/Write R/W R/W R/W R/W RR/W R/W R/W

Initial Value 0 00000000

36 AT86RF401 1424F–RKE–12/03

Data EEPROM Data Register – DEEDR

•Bits[7:0]

This register co ntains the byte to be w ritten to EEPROM. If a r ead operation has been

done, this register contains that last by te read from the data EEPR OM.

Data EEPROM Address Register – DEEAR

•Bit[7]

Reserved.

•Bits[6:3]: Data EEPRO M Page Address

These bit s select the page i n the EEPROM that is to be accessed. These bits are write

locked and cannot be altered when the load bit is set.

•Bits[2:0]: Data EEPROM Byt e Address

These b its select the byte in the page that is to be accessed. During a page write opera-

ti on, thes e bits are use d in combinat ion w ith the DEEDR register to write bytes into a

page.

Bit 76543210

$1D ED7 ED6 ED5 ED4 ED3 ED2 ED1 ED0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 00000000

Bit 76543210

$1E –PA6 PA5 PA4 PA3 BA2 BA1 BA0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 00000000

AT86RF401

1424F–RKE–12/03

Bit Timer Register De scriptions

Bit Timer Count Register – BTCNT

•Bit [7:0]

Lowest 8 bits of countval. When com bined wi th bits [7:6] of the BTCR register, countval

det ermi nes a co un ter val ue that set s the w idth of a ma rk or a space t hat is s ent to t he

transmitter. The width o f the mark or space is:

PXX = PAVR * (countval +1)

w here PXX is the period of the mark or space, and PAVR is t he per iod of th e AVR clock

that i s determ ined by the A C S bits of th e AV R c on f iguration register , AVR_ CON FIG.

Bit Timer Control Register – BTCR

•Bit[7:6]

Count_val[9:8]. MSB of BTCNT counter value bits.

•Bits[5:4]

Table 16. Bit T imer Mode.

•Bit[3]: Interrupts Enabled

If this bit is set, the Flag2 and Fla g0 will gener a te th ei r res pec t iv e inte rru p ts wh en t h ey

ar e s et . Fl ag0 i nte rru pt vect o r i s l oc at ed at 0 x 04. Flag2 in te rrup t v e cto r is loca ted at

0 x 02. Typically, a JMP in struction resides at these vector locations to pass control to

an interrupt handler. For Flag0 only, s lightly faster execution can be achieved if the JMP

instruction is eliminated, and the interrupt service routine is located beginning at 0 x 04.

Bit 76543210

$20 C7 C6 C5 C4 C3 C2 C1 C0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 00000000

Bit 76543210

$21 C9 C8 M1 M0 IE F2 DATA F0

Read/Write R/W R/W R/W R/W R/W RR/W R

Initial Value 00000000

Mode[1:0] Bit Timer Function

00 Bit Timer Disabled

01 Bit Timer in Generic Timer/Count er Mode

10 Bit Timer in Receive Mode

11 Bit Ti mer in Transmit Mode

38 AT86RF401 1424F–RKE–12/03

•Bit[2]: Flag2

In transmit mode, this flag indicates the Transmit Done condition that occurs when the

buffer is emp ty and the counter has cou nte d down to “0”. In receive mode, th is flag indi-

c ate s tha t a n edge ha s o ccurr e d, and t h e A VR sho u ld p r ocess the count value in the

BT CR an d B T CNT registers. This bit is cleared upon read , e.g ., IN R16 , BTCR.

Table 17. Bit T imer F lag2 Definition

•Bit[1]: Data Bit

In transm it mode, this is a one-bit buffer that the AVR writes data to and the bit timer

extr acts data f r om. When the bit timer removes the value from this register, the Flag0 bit

is s et, and if ena bled, a n interru pt (INT2) is gene rated . If the in te rrupt is u sed, th e ISR

should load a new bit into the buffer. If the inter r upt is not enabled, then a polling method

should be used to detect Flag0 being set. Because of overhead associated with interrupt

handlin g, it may be slight ly f as te r to use poll i ng.

In rec eive mode, the value in this re gister indicates whether the edge at the IO3 pin was

rising or falling. A “1” indicates a rising edge occurr ed, and a “0” indicates that a falling

edge was detected. The numbe r of AVR clock cycles since the last edge is held in the

C[9:0] (countval) bits (that is, unle ss an overflow co ndition has occurred).

•Bit[0]: Flag0

In transmit mode, this flag indicates the buffer is empty and the AVR should load new

dat a into it . In r ecei ve mode, t hi s ind i cate s a co unte r ov erfl ow con di tion has o ccu rred.

The AVR should increment its software counter if this condition has occu rr ed. This bit is

cleared upon read, e.g., IN R16, BTCR.

Watchdog Timer Control Register – WDTCR

•Bits[7:5]

Reserved. These bits will always read as “0”.

•Bit[4]: WDTOE, Watchdog Turn-of f Enable

This bit m us t be set (“1”) when the WDE bit is cleared. Otherwise, the watchdog w ill no t

be di sabled. Once s et, hardware will clear this bit to “0” after four clock cycles. Refer to

the de s c rip tion of the WDE bit for a wat chdog disable procedure.

•Bit[3]: WD E, Watchdog Enable

Mode[1:0] Flag2 Function

00 Disabled

01 Indicates Transmit Done condition; buffer is empty and the

counter has expired.

10 An edge has been detected at the IO3 pin.

11 Indicates Transmit Done condition; buffer is empty and the

counter has expired.

Bit 76543210

$22 – – – WDTOE WDE WDP2 WDP1 WDP0 WDTCR

Read/Write R R R R/W R/W R/W R/W R/W

Initial Value 00000000

AT86RF401

1424F–RKE–12/03

When the WDE is set (“1”), the Watchdog Timer is enabled, and if the WDE is cleared

(“0”), the Watc hdog Timer func tion is disabled. WDE can only be cleared if the WDTO E

bit is set (“1”). To disable an enabled Watchdog Timer , the following procedure must be

followed: In the same operatio n, write a logical “1” to WDTOE and WDE. A logical “1”

must be written to W DE even though it is s et to “1” before the disable operation starts.

Within the next four clock cycles, write a logical “0” to WDE. This disables the watchdog.

•Bits[2:0]: WDP2, WDP1, WDP0, Watchdog Timer Prescaler 2, 1 and 0

The WDP 2, WDP1 and WDP 0 bits det ermine the Watc hdog Tim er prescaling when the

Watchdog Timer is enabled. The different prescaling values and their corresponding

time-out periods are shown in Table 18.

Note:

Example:

If the crystal period is 50 ns and the s ystem clock divider is set to 32 (Bits[7:5] in t he

PWR_CTL register are set to 010) and the WDT prescaler is set to 32K, then:

Watchdog Timeout = 50 ns × 32 × 32768 = 52 ms

I/O Enable Register – IO_EN A B

•Bit[7]

Reserved.

•Bit[6]

If set to “1”, additional hysteresis is added to the battery low and brown-out logic. See

BL_CONFIG regist er description and Table 21 on page 43 for more details.

Table 18. Watchdog Timer Prescale Select

WDP2 WDP1 WDP0 Number of System Clock Cycles

0002,048 cycles

0014,096 cycles

0108,192 cycles

01116,384 cycles

10032,768 cycles

10165,536 cycles

110131,072 cycles

111262,144 cycles

Twdt XTALBperiod ACSdiv WDTdiv

××=

Bit 7 6 5 4 3 2 1 0

$30 –BOHYST IOE5 IOE4 IOE3 IOE2 IOE1 IOE0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

40 AT86RF401 1424F–RKE–12/03

•Bits[5:0]

If se t to “1”, the corresponding bit (pin) IO[5:0] is configured as an output. Data may t hen

be written to that output by writing to the IO_DATA register. If set to “0”, the correspond-

ing bit (pin) may be either a button input (refer to the Button Detect Register, $34) used

to wake the part up or a normal digital input.

Table 19. I/O Pi n Defi n i tion

I/O Data Out Register – I O_DATOUT

•Bits[7:6]: Re served

These bits read “0”.

•Bits[5.0]

If enabled in the IO_ENA B register and not in tes t mode, the data in Bit s[5:0] goes to the

corresponding general-purpose output I O [5 :0 ].

I/O Data In Regis ter – IO_DATIN

•Bits[7:6]: Re served

This bit reads “0”.

•Bits[5:0]

Thes e bits dire ctly read the data f rom the I/O p ins IO [5:0]. Writes to thes e bits have no

effect.

AVR Configuration Register – AVR_CONFIG

IO_ENAB[n] IO_DATOUT[n] IO[n]

0 0 Normal Input

0 1 Button Input

1 0 Output Driven Low

1 1 Output Driven High

Bit 76543210

$31 – – IOO5 IOO4 IOO3 IOO2 IOO1 IOO0

Read/Write R R R/W R/W R/W R/W R/W R/W

Initial Value 00000000

Bit 76543210

$32 – – IOI5 IOI4 IOI3 IOI2 IOI1 IOI0

Read/Write R/W R/W R R R R R R

In itial Value 0 0

Bit 76543210

$33 –ACS1 ACS0 TM BD BLI SLEEP BBM

Read/Write R/W R/W R/W R/W R R W R/W

Initial Value 00000000

AT86RF401

1424F–RKE–12/03

•Bits[6:5]: AVR Sys tem Cl ock Select

These bits select the d ivide value of th e XTALB inp ut t hat is us ed to produce the AVR

System Clock.

Table 20. AVR Clock Select De finition

This clock select value may be programmed on the fly by either the AVR processor in

no rm a l o pe ra tion or b y an I/ O wr ite SP I co m m and d uri ng SP I mo de. Not e t hat du r ing

SPI mode, the I/O and serial programming logic runs at XTALB/16 frequency.

•Bit[4]: Test Mode

When th is b it is set to “1”, the part enters test mode . The I/O pins, if enabled, assume

the following functionality:

Notes: 1. IO_ENAB register is NOT used for SPI pins.

2. In SPI mode, the I/O registers may be directly accessed via the SPI interface. Txkey, lockdetect may be output using this

mode.

•Bit[3]: Batter y Dead

Indicates battery is dea d. Only readable by SPI interface.

•Bit [ 2 ] : B attery Low Indicator

This bi t is id entical to Bit[7] of Battery Low Co nfiguratio n Register ($35). Wh en Bit[6] of

Battery Low Configuration Register ($35) is set (Battery Low Valid), a set bit in this loca-

ti on indic ates tha t the ba ttery v oltage is lower than the voltage level that is determined

by Bits[5:0] of B at tery Low Configuration Register ($35).

•Bit [1]: Sleep Bit

W hen s et , this bit stops the c rystal oscillator. Th is stops the AVR processor with the pro-

gram counter frozen at the current instruction. Sleep will also stop the Watchdog Timer.

The Wa tchdog T imer i s only r estarte d if the par t wakes up. If an I/O pin is configured as

a button, a button press will s tart the os cilla to r and c h ec k t h e ba tter y lev el . If the bat t ery

level is greater than the Battery Dead level, the AVR system clock is started and normal

program execution continues. If the battery level is below the Battery Dead level , the

cry st al oscillator is turned off, putting the part back to sleep until a button is pressed

again (care should be taken not to put the part to sleep unless a button is configured and

enabled).

•Bit[0]: Button Boot Mode (BBM)

If the BBM bit is set a nd the part is brought out o f sleep mode by a button i nput act iva-

tion, t he par t wi ll enter the button reset state. In this state, the par t will reboot a nd begin

ACS[1:0] AVR System Clock

11 XTALB/16

10 XTALB/32

01 XTALB/64

00 XTALB/128

I/O5 I/O4 I/O3 I/O2 I/O1 I/O0

Normal Mode

(RESETB = 1) txkey

(Output) lockdetect

(Output) txenable

(Output) RFU RFU RFU

SPI Mode

(RESETB = 0) txkey

(Output) lockdetect

(Output) txenable

(Output) SPI_CLK SDO SDI

42 AT86RF401 1424F–RKE–12/03

code execution at the reset locat ion. This bit is reset at POR and when exi ting the button

reset s t at e. All oth er registers remain unch anged.

Button Detect Register – B_DET

•Bits[7:6]

Reser ved. These bits read “0”.

•Bits[5:0]

W hen an I/O pin is conf igured as a button u sing the IO _ENAB an d IO_D ATOUT re gis-

ters and a logic low is dete cted on that pin, the button detect logic is activated. If the part

is in sleep mode, the part responds as described in the AVR Configuration Register

descripti on. If a good batte ry is present, the appropriate bit is set in this register. A bit in

this register is cleared by writing a “0” to it.

Battery Low Configu rati on Register – BL_CONFIG

•Bit[7]: Battery Low

When B it[6] in this register is set (Battery Low Valid), the BL (Battery Low) bit indicates

th at th e b a ttery vol tage is lower than t he voltage level that is determined by Bit[5:0] of

this register. It is important that the programmer also chec k Bit[6] (Batter y Low Valid) to

be certain that this condition is valid.

•Bit[6]: Battery Low Valid

When the Battery Low Configuration Register is written, this bit is set to “0”. Wh en the

battery voltage has been sampled and compared to the voltage determined by the BLx

bits, this bit is set to “1” indicating that the data in Bit[7] ( Battery Low) is valid. This can

take up to 3100 XTAL cycles to complete.

Note: The programmer should ensure th at this bit is cleared prior to making a determination of

the Battery Low status. This can be done by reloading Bit[5] or directly clearing Bit[6].

Generally, the programmer loads Bit[5], loops until Bit[6] is se t, and then checks Bit[3] to

de term ine the st atus o f the ba ttery.

•Bit[5:0]: Batter y Low Detection Level

This value is sent to the battery monitor. The threshold is calculated using the formulas

shown in Table 21 on page 43.

Note: Th i s th r es hold can be set be l ow th e bro wn- ou t vo ltage level.

Bit 76543210

$34 – – BD5 BD4 BD3 BD2 BD1 BD0

Read/Write R R R/W R/W R/W R/W R/W R/W

Initial Value 00000000

Bit 76543210

$35 BL BLV BL5 BL4 BL3 BL2 BL1 BL0

Read/Write R R R/W R/W R/W R/W R/W R/W

Initial Value 00000000

AT86RF401

1424F–RKE–12/03

Table 21. Low Bat ter y Detection Thres hold Formulas (VREF is a pproxim ately 0. 7 volts)

VDD Falling

VDD Rising

BOHYST = 1 (large hysteresis) BOHYST = 0 (small hysteresis)

VDD 3.887 VREF

10.887

---------------×BL[5:0]+

-----------------------------------------------------------= VDD 4.05 VREF

10.887

---------------×BL[5:0]+

-----------------------------------------------------------= VDD 4.22 VREF

10.887

---------------×BL[5:0]+

-----------------------------------------------------------=

BL[5:0] 71 3.887 VREF

VDD

------------- 1–××=BL[5:0] 71 4.05 VREF

VDD

-------------1–××=BL[5:0] 71 4.22 VREF

VDD

-------------1–××=

44 AT86RF401 1424F–RKE–12/03

The St ack Pointer – SP The Stack P ointer i s implem ented a s two 8-bi t re gisters i n the I/O spa ce lo cations $3E

($5E ) and $3D ($5D ). Caution: A s the data me mory has 2 24 l ocations , onl y 8 bits a re

used and the SPH register must be programmed to 0 x 00.

The S tack Pointer points to the data SRAM stack area whe re the Subroutine and Inter-

rupt Stacks are located. This stack space in the data SRAM must be defined by the

pro gram before any sub ro utine calls are exec uted or inte rru pts are enabled. Th e Stack

Pointer must be set to point above $60. The Stack Pointer is decremented by one when

dat a is push ed o nto the st ack w ith the PUSH i nstructio n, and it is d ecrem ented b y tw o

when t he return address is pushed onto the stack with subroutine call and i nterrupt. T he

Stac k Pointer is increment ed by one when data is popped from the stack with the POP

instruction, and it is i ncremen ted b y two when data is popped from the stack with Return

from Subroutine (RET) or Return from Interrupt (RETI).

The Status Register – SREG The AVR status register – SREG – at I/O spac e location $3F is def ined as:

•Bit[7] – I: Glob al In terrup t Enabl e

The global interrupt enable bit must be set (“1”) f or t h e i n ter r upt s to b e enabl ed. The

individual interrupt enable control is then performe d in the interrupt mask registers

(GIMS K/TIM SK). If the global interrupt enab le register is cleared (“0”), non e of the inter-

rupts are enabled, independent of the GIMSK/TIMSK values. The I-bit is cleared by

h ar dw ar e after a n in t er ru p t ha s o cc u rre d and i s set by t he RET I in s tr uc tio n to e nable

subseq uent in terrupts.

•Bit[6] – T: Bit Co py Sto rage

The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source

and destination for the operated bit. A bit from a register in the register file can be copied

into T by the BST instruc tion, an d a bit in T can be copied into a bi t i n a regi ster in th e

•Bit[5] – H: Half Carry Flag

The half carry flag H indicates a half carry in some arithmetic operations. See Figure 10

on page 21 for detailed informati on.

Bit 15 14 13 12 11 10 9 8

$3E –––––SP10 SP9 SP8 SPH

$3D SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

76543210

Read/Write RRRRRR/WR/WR/W

R/W R/W R/W R/W R/W R/W R/W R/W

Init ia l Value 00000000

00000000

Bit 76543210

$3F ITHSVNZC

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 00000000

AT86RF401

1424F–RKE–12/03

•Bit[4] – S: Sign Bit, S = N⊕

⊕⊕

⊕V

The S-bit is always an exclusive or between the negative flag N and the two’s comple-

ment overflow flag V. See Table 22 for detailed information.

•Bit[3] – V: Two’s Complement Overflow Flag

The two’s complement overflow flag V supports two’s complement arithmetics. See

Table 22 below for detailed information.

•Bit[2] – N: Negative Flag

The ne gativ e flag N indicate s a negative result after the different arithmetic and logic

operations. See Table 22 below for detailed information.

•Bit[1] – Z: Zero Flag

The z e r o flag Z i ndicates a zero r e s u lt after the different arithmetic and logic operations.

See Table 22 below for detail ed inf ormation.

•Bit[0] – C: Carry Flag

Th e ca rry flag C indi ca tes a carry in an ari thme tic o r logic oper ation. Se e T abl e 22 for

detailed informa tion.

Table 22. Instruc tion Set

Mnemonics

Operands Description Operation Flags #Clocks

Arithmetic and Logic Instructions

ADD Rd, Rr Add Two Registers Rd ← Rd + Rr Z,C,N,V,H

ADC Rd, Rr Add with Carry Two Registers Rd ← Rd + Rr + C Z,C,N,V, H 1

ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 1

SUB Rd, Rr Sub tr act Two Registers Rd ← Rd - R r Z,C,N,V, H 2

SUBI Rd, K Subtr act Constant from Register Rd ← Rd - K Z,C, N,V,H 1

SBC Rd, Rr Subtract wi th Carry Two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1

SBCI Rd, K Subtrac t with Carry Constan t from

SBIW Rdl,K Subtract Immediate from Word R dh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 1

AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 2

ANDI Rd, K Logical AND Reg ister and

Constant Rd ← Rd • KZ,N,V1

OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1

ORI Rd, K Lo gical OR Register and Constant Rd ← Rd v K Z,N,V 1

EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1

COM Rd One’s Co mplemen t R d ← $FF − Rd Z,C,N,V 1

NEG Rd Two’s Complemen t Rd ← $00 − Rd Z,C,N,V,H 1

SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N, V 1

CBR Rd,K Clear Bit(s) in Register R d ← Rd • ($FF - K) Z,N,V 1

INC Rd Increment Rd ← Rd + 1 Z,N, V 1

DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1

TST Rd Test for Zero or Minus R d ← Rd • Rd Z,N,V 1

46 AT86RF401 1424F–RKE–12/03

CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1

SER Rd Set Register Rd ← $FF None 1

Branch Instructions

RJMP k Relative Jump PC ← PC + k + 1 None 1

IJMP Indirect Jump to (Z) PC ← Z None 2

JMP k Direct Jump PC ← k None 2

RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3

ICA L L Ind ir ec t C a ll to (Z) PC ← Z None 3

CALL k Direct Subroutine C all PC ← k None 3

RET Subroutine Return PC ← STACK None 4

RE T I In te r r u pt R e tu rn PC ← STACK I 4

CPSE Rd,Rr Compare , Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3

CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1

CPC Rd,Rr Compare with Carry Rd − Rr − CZ, N,V,C,H1

CPI Rd,K Compare Register with Immediate Rd − KZ, N,V,C,H1

SBRC Rr, b Skip if Bit in Register Cleared If (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3

SBRS Rr, b Skip if Bit in Register Set If (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3

SBIC P, b Skip if Bit i n I/O Register Cleared If (P(b)=0) PC ← PC + 2 or 3 None 1/2/3

SBIS P, b Skip if Bit i n I/O Register Set If (P(b)=1) PC ← PC + 2 or 3 None 1/2/3

BRBS s, k Branch if Status Flag Set If (SREG(s) = 1) then PC ← PC + k + 1 None 1/2

BRBC s, k Branch if Status Flag Cleared If (SREG(s) = 0) then PC ← PC + k + 1 None 1/2

BREQ k Branch if Equal If (Z = 1) then PC ← PC + k + 1 None 1/2

BRNE k Branch if No t Equal If (Z = 0) then PC ← PC + k + 1 None 1/2

BRCS k Branch if Carry Set If (C = 1) then PC ← PC + k + 1 None 1/2

BRCC k Branch if Carry Cleared If (C = 0) then PC ← PC + k + 1 None 1/2

BRSH k Branch if Same or Higher If (C = 0) then PC ← PC + k + 1 None 1/2

BRLO k Branch if Low er If ( C = 1) then PC ← PC + k + 1 None 1/2

BRMI k Bran ch if Mi nus If ( N = 1) then PC ← PC + k + 1 None 1/2

BRPL k Branch if Plus If (N = 0) then PC ← PC + k + 1 None 1/2

BRGE k Bran ch if Greate r or Equal , Signed If (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2

BRLT k Branch if Less Than Zero, Signed If (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2

BRHS k Branch if Half Carry Flag Set If (H = 1) then PC ← PC + k + 1 None 1/2

BRHC k Branch if Ha lf Carry Flag Cleared If ( H = 0) then PC ← PC + k + 1 None 1/2

BRTS k Branch if T Flag Set If (T = 1) then PC ← PC + k + 1 None 1/2

BRTC k Branch if T Flag Cleared If (T = 0) then PC ← PC + k + 1 None 1/2

BRVS k Branch if Overflow Flag Set If (V = 1) then PC ← PC + k + 1 None 1/2

Table 22. Instruction Set (Continued)

Mnemonics

Operands Description Operation Flags #Clocks

AT86RF401

1424F–RKE–12/03

BRVC k Branch if Overflow Flag Cleared If (V = 0) then PC ← PC + k + 1 None 1/2

BRIE k Branch if Interrupt Enabled If (I = 1) then PC ← PC + k + 1 None 1/2

BRID k Branch if Interrupt Disabled If (I = 0) then PC ← PC + k + 1 None 1/2

Data Transfer Instructions

MOV Rd, Rr Move Between Registers Rd ← Rr None 1

MOVW Rd, Rr Copy Register Word Rd+1:Rd ← Rr + 1:Rr None

LDI Rd, K Lo ad Immediate Rd ← K None 1

LD Rd, X Load Indirect Rd ← (X) None 2

LD Rd, X+ Load Indirect and Post-I nc. Rd ← (X), X ← X + 1 None 2

LD Rd, −X Load Indirect and Pre-Dec. X ← X − 1, Rd ← (X) None 2

LD Rd, Y Load Indirect Rd ← (Y) None 2

LD Rd, Y+ Load Indirect and Post-I nc. Rd ← (Y), Y ← Y + 1 None 2

LD Rd, −Y Load Indirect and Pre-Dec. Y ← Y − 1, Rd ← (Y) None 2

LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2

LD Rd, Z Load Indir ect Rd ← (Z) None 2

LD Rd, Z+ Load Indirect and P ost-I nc. Rd ← (Z), Z ← Z + 1 None 2

LD Rd, −Z Load Indirect and Pre-Dec. Z ← Z − 1, Rd ← (Z) None 2

LDD Rd, Z+q Load Indirect wit h Displacement Rd ← (Z + q) None 2

LDS Rd, k Load Direct fr om SRA M Rd ← (k) None 2

ST X, Rr Store Indi rect (X) ← Rr None 2

ST X+, Rr Stor e Indirect and P ost-Inc. (X) ← Rr, X ← X + 1 None 2

ST − X, Rr Store Indi rect and Pre-Dec. X ← X − 1, (X) ← Rr None 2

ST Y, Rr Store Indirect (Y) ← Rr None 2

ST Y+, Rr Stor e Indirect and P ost-Inc. (Y) ← Rr, Y ← Y + 1 None 2

ST −Y, Rr Store Indirect and Pre-D ec. Y ← Y − 1, (Y) ← Rr None 2

ST D Y+q,R r S tore Ind irect with Disp lacemen t (Y + q) ← Rr None 2

ST Z, Rr Stor e Indirect (Z) ← Rr None 2

ST Z+, Rr Store Indirect and Pos t- Inc. (Z) ← Rr, Z ← Z + 1 None 2

ST −Z, Rr Store Indirect and Pre-Dec. Z ← Z − 1, (Z) ← Rr None 2

ST D Z+q,R r Sto re Ind irect with Disp la cement (Z + q) ← Rr None 2

STS k, Rr Stor e Direct to SRAM (k) ← Rr None 2

LPM Load Program Memory R0 ← (Z) None 3

LPM Rd, Z Load Prog ram Memory Rd ← (Z) None 3

LPM Rd, Z+ Load Program Memory and Post-

Inc. Rd ← (Z), Z ← Z+1 None 3

IN Rd, P In Port Rd ← P None 1

Table 22. Instruction Set (Continued)

Mnemonics

Operands Description Operation Flags #Clocks

48 AT86RF401 1424F–RKE–12/03

OUT P, Rr Out Port P ← Rr None 1

PUSH Rr Push Register on Stack STACK ← Rr None 2

POP Rd Pop Register from Stack R d ← STACK None 2

Bit and Bit-test Instructions

SBI P, b Set Bit in I/O Register I/ O (P,b ) ← 1 None 2

CBI P, b Clear Bit in I/O Register I/O(P,b) ← 0 None 2

LSL Rd Logical Shif t Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1

LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1

ROL Rd Rotate Le ft Through Carry

Rd(0)

←

C, Rd(n+1 )

←

Rd(n), C

←

Rd(7)

Z,C,N,V 1

ROR Rd Rotate Right Through Carry

Rd(7)

←

C, Rd(n)

←

Rd(n+1), C

←

Rd(0)

Z,C,N,V 1

ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n = 0...6 Z,C,N,V 1

SWAP Rd Swap Nibbles

Rd(3...0)

←

Rd(7...4), Rd(7...4)

←

Rd(3...0)

None 1

BSET s Flag Set SREG(s) ← 1SREG(s)1

BCLR s F lag Clear SREG(s) ← 0 SREG(s) 1

BST Rr, b Bit Store from Register to T T ← Rr(b) T 1

BLD Rd, b Bit Load fr om T to Register Rd(b) ← T None 1

SEC Set Carry C ← 1C1

CLC Clear Carry C ← 0 C 1

SEN Set Negativ e Flag N ← 1N1

CLN Clear Negative Flag N ← 0 N 1

SEZ Set Zero Flag Z ← 1Z1

CLZ Clear Zero Flag Z ← 0 Z 1

SEI Global Interrupt Enable I ← 1I1

CLI Global Interrupt Disable I ← 0 I 1

SES Set Sig ned Test Flag S ← 1S1

CLS Clear Signed Test Flag S ← 0 S 1

SEV Set Two’s Complement Overflow V ← 1V1

CLV Clear Two’s Complement Ov erfl ow V ← 0 V 1

SET Set T in SREG T ← 1T1

CLT Clear T in SREG T ← 0 T 1

SEH Set Half Carry Fla g in SREG H ← 1H1

CLH Clear Half Carry Flag in SREG H ← 0 H 1

NOP No Operation None 1

SLEEP Sleep Not Implemented None 3

WDR Watchdog Reset ( See specific description for WDR/timer) None 1

Table 22. Instruction Set (Continued)

Mnemonics

Operands Description Operation Flags #Clocks

AT86RF401

1424F–RKE–12/03

Ordering Informatio n

RF Output Ordering Code Package Application Temperature

Operating Range

315 MHz AT86RF401U 20T Nor th Amer ican −40°C to 85°C

434 MHz AT86RF401E 20T European −40°C to 85°C

264 to 456 MHz AT86RF401X 20T All Applications −40°C to 85°C

50 AT86RF401 1424F–RKE–12/03

Packag e Drawi ng All devi ces are packaged on tape in reel; stan dard reel quantity is 2,500 piec es.

20A2 – TS S O

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

6/3/02

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

D 6.40 6.50 6.60 2, 5

E 6.40 BSC

E1 4.30 4.40 4.50 3, 5

A––1.20

A2 0.80 1.00 1.05

b 0.19 –0.30 4

e 0.65 BSC

L 0.45 0.60 0.75

L1 1.00 REF

20A2, 20-lead (4.4 x 6.5 mm Body), 0.65 pitch,

Thin Shrink Small Outline Package (TSSOP)

Notes: 1. This drawing is for general information only. Please refer to JEDEC Drawing MO-153, Variation AC, for additional

information.

2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall

not exceed 0.15 mm (0.006 in) per side.

3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed

0.25 mm (0.010 in) per side.

4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess

of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot.

Minimum space between protrusion and adjacent lead is 0.07 mm.

5. Dimension D and E1 to be determined at Datum Plane H.

20A2 C

DA2

EE1

Top Vie w

Side View

End View

AT86RF401

1424F–RKE–12/03

Data Sheet Change

Log Please note that the page n u m bers referenced below apply t o this document.

Ch anges from

Rev. 1424E-RKE-03/03 to

Rev. 1424F-RKE-9/03

•Updated text in Low Batte ry Detection section on page 10.

•Table 3, in Low Battery Detection section on page 10 was moved to Battery Low

Configuration Register section and became Table 21 (page 43).

•Updated text in B at ter y Low Configuration Register section (page 42).

•Renumbered tables as required to mainta in proper sequence.

•Added Data Sheet Change Log s ection (page 51).

•Replaced “Power Control Register” with “AVR C onfigur at ion Register ” in B utton

Detect Register section (page 42).

•Removed references to CFIL in Figures 1, 2, and 3 and Table 2.

•Changed description of Bit[2] (LOC) in Transmit Control Register section (page 30)

from R /W t o R and included additional d escriptive text for Bi t[5], Bit[4], and Bi t[2].

•Added “Read Si gnature Byte” c ommand to Seri al Programming Instr uc tion Set

shown in Table 7 on page 15 and added Signature Bytes s ec tion on page 14.

•Added note regarding maximum output power in P ow er Attenuation Control Register

description section (page 30).

•Added text to “Butt o n Rese t” paragraph in the Reset Sources section (page 12).

•Added text to Bit Timer section (page 11).

•Added text to Bit Timer Control Register section (page 37).

Pr inted o n rec ycled pa per.

Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s stan da rd

warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web si te. Th e C omp any ass ume s no res p onsi bi lity for any

errors which may appear in this document, reser ves the right to change devices or specifications detailed herein at any time witho ut noti ce, a nd

does not make any commitment to update the information contained herein. No licenses to patents or other intellectual proper ty of Atmel are

gran ted by the C om pany in co nnec ti on wit h th e sa le of Atm el p rod ucts, ex pres sly or by imp lica tio n. At me l’s products are not authorized for use

as critical components in life support devices or systems.

Atmel Corporation Atmel Operations

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San Jos e, CA 951 31, USA

Tel: 1(4 08) 4 41-0311

Fax : 1(408) 487-260 0

Regional Headquarters

Europe

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Memory

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Microcontrollers

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Tel : 1(408 ) 441-031 1

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Maxwell Building

East Kilbri de G7 5 0QR , Scotland

Tel : (44) 13 55-803- 000

Fax: (44) 1 355 -242-743

RF/Automotive

Ther esien strass e 2

Pos tfach 3 535

74025 H eil bronn, Ger many

Tel: (49) 71-31-67-0

Fax : (49) 71 - 31-67-234 0

1150 Ea st Cheyen ne M tn. B lvd.

Colo rado Spring s, CO 80906, USA

Tel: 1(7 19) 57 6-3300

Fax : 1(719) 540 -1759

Biometrics/Imaging/Hi-Rel MPU/

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Avenue de Rochepleine

BP 123

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Fax : (33) 4-76-58- 3 4-80

Literature Requests

www.atmel.com/literature

1424F–RKE–12/03

subs i diar ies. Oth er ter ms and prod uct nam es may be th e trad ema rks of ot hers.