UDA1334TS/N1,112 - NXP Semiconductors

DATA SH EET

Product speciﬁcation

Supersedes data of 1999 Nov 11

File under Integrated Circuits, IC01

2000 Oct 25

INTEGRATED CIRCUITS

UDA1334TS

Low power audio DAC

2000 Oct 25 2

Philips Semiconductors Product speciﬁcation

Low power audio DAC UDA1334TS

CONTENTS

1 FEATURES

1.1 General

1.2 Multiple format data interface

1.3 DAC digital sound processing

1.4 Advanced audio configuration

2 APPLICATIONS

3 GENERAL DESCRIPTION

4 ORDERING INFORMATION

5 QUICK REFERENCE DATA

6 BLOCK DIAGRAM

7 PINNING

8 FUNCTIONAL DESCRIPTION

8.1 System clock

8.2 Interpolation filter

8.3 Noise shaper

8.4 Filter stream DAC

8.5 Power-on reset

8.6 Feature settings

8.6.1 Digital interface format select

8.6.2 Mute control

8.6.3 De-emphasis control

8.6.4 Power control and sampling frequency select

9 LIMITING VALUES

10 HANDLING

11 THERMAL CHARACTERISTICS

12 QUALITY SPECIFICATION

13 DC CHARACTERISTICS

14 AC CHARACTERISTICS

14.1 2.0 V supply voltage

14.2 3.0 V supply voltage

14.3 Timing

15 APPLICATION INFORMATION

16 PACKAGE OUTLINE

17 SOLDERING

17.1 Introduction to soldering surface mount

packages

17.2 Reflow soldering

17.3 Wave soldering

17.4 Manual soldering

17.5 Suitability of surface mount IC packages for

wave and reflow soldering methods

18 DEFINITIONS

19 LIFE SUPPORT APPLICATIONS

2000 Oct 25 3

Philips Semiconductors Product speciﬁcation

Low power audio DAC UDA1334TS

1 FEATURES

1.1 General

•1.8 to 3.6 V power supply voltage

•Integrated digital filter plus DAC

•Supports sample frequencies from 8 to 100 kHz

•Automatic system clock versus sample rate detection

•Low power consumption

•No analog post filtering required for DAC

•Slave mode only applications

•Easy application

•SSOP16 package.

1.2 Multiple format data interface

•I2S-bus and LSB-justified format compatible

•1fs input data rate.

1.3 DAC digital sound processing

•Digital de-emphasis for 44.1 kHz sampling rate

•Mute function.

1.4 Advanced audio conﬁguration

•High linearity, wide dynamic range and low distortion

•Standby or Sleep mode in which the DAC is powered

down.

2 APPLICATIONS

This audio DAC is excellently suitable for digital audio

portable application, such as portable MD, MP3 and

DVD players.

3 GENERAL DESCRIPTION

The UDA1334TS supports the I2S-bus data format with

word lengths of up to 24 bits and the LSB-justified serial

data format with word lengths of 16, 20 and 24 bits.

The UDA1334TS has basic features such as de-emphasis

(at 44.1 kHz sampling rate) and mute.

4 ORDERING INFORMATION

TYPE

NUMBER PACKAGE

NAME DESCRIPTION VERSION

UDA1334TS SSOP16 plastic shrink small outline package; 16 leads; body width 4.4 mm SOT369-1

2000 Oct 25 4

Philips Semiconductors Product speciﬁcation

Low power audio DAC UDA1334TS

5 QUICK REFERENCE DATA

Note

1. The DAC output voltage scales proportional to the power supply voltage.

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

VDDA DAC analog supply voltage 1.8 2.0 3.6 V

VDDD digital supply voltage 1.8 2.0 3.6 V

IDDA DAC analog supply current normal operation −2.1 −mA

Sleep mode −150 −µA

DDD digital supply current normal operation −1.2 −mA

Sleep mode −50 −µA

amb ambient temperature −40 −+85 °C

Digital-to-analog convertor (VDDA =V

DDD = 2.0 V)

Vo(rms) output voltage (RMS value) at 0 dB (FS) digital input; note 1 −500 −mV

(THD + N)/S total harmonic

distortion-plus-noise to

signal ratio

fs= 44.1 kHz; at 0 dB −−80 −dB

fs= 44.1 kHz; at −60 dB; A-weighted −−37 −dB

fs= 96 kHz; at 0 dB −−75 −dB

fs= 96 kHz; at −60 dB; A-weighted −−35 −dB

S/N signal-to-noise ratio fs= 44.1 kHz; code = 0; A-weighted −97 −dB

fs= 96 kHz; code = 0; A-weighted −95 −dB

MUTE = HIGH; A-weighted −110 −dB

αcs channel separation −100 −dB

Digital-to-analog convertor (VDDA =V

DDD = 3.0 V)

Vo(rms) output voltage (RMS value) at 0 dB (FS) digital input; note 1 −750 −mV

(THD + N)/S total harmonic

distortion-plus-noise to

signal ratio

fs= 44.1 kHz; at 0 dB −−90 −dB

fs= 44.1 kHz; at −60 dB; A-weighted −−40 −dB

fs= 96 kHz; at 0 dB −−85 −dB

fs= 96 kHz; at −60 dB; A-weighted −−37 −dB

S/N signal-to-noise ratio fs= 44.1 kHz; code = 0; A-weighted −100 −dB

fs= 96 kHz; code = 0; A-weighted −98 −dB

MUTE = HIGH; A-weighted −110 −dB

αcs channel separation −100 −dB

Power dissipation (at fs= 44.1 kHz)

P power dissipation at 2.0 V supply voltage −7.0 −mW

at 3.0 V supply voltage −17 −mW

Sleep mode; at 2.0V supply voltage

clock running −0.75 −mW

no clock running −0.3 −mW

2000 Oct 25 5

Philips Semiconductors Product speciﬁcation

Low power audio DAC UDA1334TS

6 BLOCK DIAGRAM

handbook, full pagewidth

MGL877

DAC

UDA1334TS

NOISE SHAPER

INTERPOLATION FILTER

DE-EMPHASIS

DAC

DIGITAL INTERFACE

13 12

VOUTR

BCK

VSSA

VOUTL

DATAI

VDDA

VDDD

Vref(DAC)

VSSD

SFOR0

SYSCLK 8

MUTE 9

DEEM 10

PCS

SFOR1

Fig.1 Block diagram.

2000 Oct 25 6

Philips Semiconductors Product speciﬁcation

Low power audio DAC UDA1334TS

7 PINNING

Notes

1. 5 V tolerant is only supported if the power supply voltage is between 2.7 and 3.6 V. For lower power supply voltages

this is maximum 3.3 V tolerant.

2. Because of test issues these pads are not 5 V tolerant and they should be at power supply voltage level or at a

maximum of 0.5 V above that level.

SYMBOL PIN PAD TYPE DESCRIPTION

BCK 1 5 V tolerant digital input pad; note 1 bit clock input

WS 2 5 V tolerant digital input pad; note 1 word select input

DATAI 3 5 V tolerant digital input pad; note 1 serial data input

VDDD 4 digital supply pad digital supply voltage

VSSD 5 digital ground pad digital ground

SYSCLK 6 5 V tolerant digital input pad; note 1 system clock input

SFOR1 7 5 V tolerant digital input pad; note 1 serial format select 1

MUTE 8 5 V tolerant digital input pad; note 1 mute control

DEEM 9 5 V tolerant digital input pad; note 1 de-emphasis control

PCS 10 3-level input pad; note 2 power control and sampling frequency select

SFOR0 11 digital input pad; note 2 serial format select 0

Vref(DAC) 12 analog pad DAC reference voltage

VDDA 13 analog supply pad DAC analog supply voltage

VOUTL 14 analog output pad DAC output left

VSSA 15 analog ground pad DAC analog ground

VOUTR 16 analog output pad DAC output right

handbook, halfpage

UDA1334TS

MGL878

VOUTR

BCK

VSSA

VOUTL

DATAI

VDDA

VDDD

Vref(DAC)

VSSD

SFOR0SYSCLK

PCSSFOR1

DEEMMUTE

Fig.2 Pin configuration.

2000 Oct 25 7

Philips Semiconductors Product speciﬁcation

Low power audio DAC UDA1334TS

8 FUNCTIONAL DESCRIPTION

8.1 System clock

The UDA1334TS operates in slave mode only; this means

that in all applications the system must provide the system

clock and the digital audio interface signals

(BCK and WS).

Thesystemclockmustbelockedinfrequencytothedigital

interface signals.

The UDA1334TS automatically detects the ratio between

the SYSCLK and WS frequencies.

The BCK clock can be up to 64fs, or in other words the

BCK frequency is 64 times the Word Select (WS)

frequency or less: fBCK ≤64 ×fWS.

Remarks

1. The WS edge MUST fall on the negative edge of the

BCK at all times for proper operation of the digital I/O

data interface.

2. For LSB-justified formats it is important to have a WS

signal with a duty factor of 50%.

The modes which are supported are given in Table 1.

Table 1 Supported sampling ranges

Notes

1. This mode can only be supported for power supply

voltages down to 2.4 V. For lower voltages, in

192fsmode the sampling frequency should be limited

to 55 kHz.

2. Not supported in low-sampling frequency mode.

An example is given in Table 2 for a 12.228 MHz system

clock input.

Table 2 Example using a 12.228 MHz system clock

Note

1. This mode can only be supported for power supply

voltages down to 2.4 V. For lower voltages, in 192fs

mode the sampling frequency should be limited to

55 kHz.

8.2 Interpolation ﬁlter

The interpolation digital filter interpolates from 1fsto 64fs

by cascading FIR filters (see Table 3).

Table 3 Interpolation ﬁlter characteristics

8.3 Noise shaper

The 5th-order noise shaper operates at 64fs. It shifts

in-band quantization noise to frequencies well above the

audio band. This noise shaping technique enables high

signal-to-noise ratios to be achieved. The noise shaper

output is converted into an analog signal using an

Filter Stream DAC (FSDAC).

CLOCK MODE SAMPLING RANGE

768fs8to55kHz

512fs8 to 100 kHz

384fs8 to 100 kHz

256fs8 to 100 kHz

192fs8 to 100 kHz(1)(2)

128fs8 to 100 kHz(2)

SAMPLING FREQUENCY CLOCK MODE

96 kHz 128fs

64 kHz(1) 192fs

48 kHz 256fs

32 kHz 384fs

24 kHz 512fs

16 kHz 768fs

ITEM CONDITION VALUE (dB)

Pass-band ripple 0 to 0.45fs±0.02

Stop band >0.55fs−50

Dynamic range 0 to 0.45fs>114

2000 Oct 25 8

Philips Semiconductors Product speciﬁcation

Low power audio DAC UDA1334TS

8.4 Filter stream DAC

The FSDAC is a semi-digital reconstruction filter that

converts the 1-bit data stream of the noise shaper to an

analog output voltage. The filter coefficients are

implemented as current sources and are summed at

virtual ground of the output operational amplifier. In this

way very high signal-to-noise performance and low clock

jitter sensitivity is achieved. No post-filter is needed due to

the inherent filter function of the DAC. On-board amplifiers

convert the FSDAC output current to an output voltage

signal capable of driving a line output.

The output voltage of the FSDAC scales proportional with

the power supply voltage.

8.5 Power-on reset

The UDA1334TS has an internal Power-on reset circuit

(see Fig.3) which resets the test control block.

The reset time (see Fig.4) is determined by an external

capacitor which is connected between pin Vref(DAC) and

ground. The reset time should be at least 1 µs for

Vref(DAC) < 1.25 V. When VDDA is switched off, the device

will be reset again for Vref(DAC) < 0.75 V.

During the reset time the system clock should be running.

handbook, halfpage

VDDA

Vref(DAC)

3.0 V 13

MGU248

UDA1334TS

C1 >

10 µF

RESET

CIRCUIT

50 kΩ

Fig.3 Power-on reset circuit.

handbook, halfpage

3.0

VDDD

(V)

1.5

3.0

VDDA

(V)

1.5

3.0

Vref(DAC)

(V)

1.5

1.25

0.75

MGL984

>1 µs

Fig.4 Power-on reset timing.

2000 Oct 25 9

Philips Semiconductors Product speciﬁcation

Low power audio DAC UDA1334TS

8.6 Feature settings

The features of the UDA1334TS can be set by control

pins SFOR1, SFOR0, MUTE, DEEM and PCS.

8.6.1 DIGITAL INTERFACE FORMAT SELECT

The digital audio interface formats (see Fig.5) can be

selected via the pins SFOR1 and SFOR0 as shown in

Table 4.

The BCK frequency for the digital audio interface can be

maximum 64 times the WS frequency: fBCK ≤64fWS.

Table 4 Data format selection

8.6.2 MUTE CONTROL

The output signal can be soft muted by setting pin MUTE

to HIGH level as shown in Table 5.

Table 5 Mute control

When the output signal is fully muted (pin MUTE at

HIGH level), a silence switch inside the FSDAC is

activated. In this way a very high signal-to-noise ratio can

be achieved in case the output is muted.

8.6.3 DE-EMPHASIS CONTROL

De-emphasis can be switched on for fs= 44.1 kHz by

setting pin DEEM at HIGH level. The function description

of pin DEEM is given in Table 6.

Table 6 De-emphasis control

8.6.4 POWER CONTROL AND SAMPLING FREQUENCY

SELECT

Pin PCS is a 3-level pin and is used to set the mode of the

UDA1334TS. The definition is given in Table 7.

Table 7 PCS function deﬁnition

The low sampling frequency mode is required to have a

higher oversampling rate in the noise shaper in order to

improve the signal-to-noise ratio. In this mode the

oversamplingratioofthenoiseshaperwill be128fsinstead

of 64fs.

SFOR1 SFOR0 INPUT FORMAT

LOW LOW I2S-bus input

LOW HIGH LSB-justiﬁed 16 bits input

HIGH LOW LSB-justiﬁed 20 bits input

HIGH HIGH LSB-justiﬁed 24 bits input

MUTE FUNCTION

LOW mute off

HIGH mute on

DEEM FUNCTION

LOW de-emphasis off

HIGH de-emphasis on

PCS FUNCTION

LOW normal operating mode

MID low sampling frequency mode

HIGH Power-down or Sleep mode

2000 Oct 25 10

Philips Semiconductors Product speciﬁcation

Low power audio DAC UDA1334TS

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handbook, full pagewidth

MGS752

B5 B6 B7 B8 B9 B10

LEFT

LSB-JUSTIFIED FORMAT 24 BITS

BCK

DATA

RIGHT

1518 1720 1922 212324 2 1

B3 B4

MSB B2 B23 LSB

B5 B6 B7 B8 B9 B10

1518 1720 1922 212324 21

B3 B4

MSB B2 B23 LSB

MSB B2 B3 B4 B5 B6

LEFT

LSB-JUSTIFIED FORMAT 20 BITS

BCK

DATA

RIGHT

1518 1720 19 2 1

B19 LSB

MSB B2 B3 B4 B5 B6

1518 1720 19 2 1

B19 LSB

MSB B2

LEFT

LSB-JUSTIFIED FORMAT 16 BITS

BCK

DATA

RIGHT

15 2 1

B15 LSB

MSB B2

15 2 1

B15 LSB

MSB MSBB2

21> = 812 3

LEFT

I2S-BUS FORMAT

BCK

DATA

RIGHT

3> = 8

MSB B2

Fig.5 Digital audio formats.

2000 Oct 25 11

Philips Semiconductors Product speciﬁcation

Low power audio DAC UDA1334TS

9 LIMITING VALUES

In accordance with the Absolute Maximum Rating System (IEC 60134).

Note

1. All supply connections must be made to the same power supply.

10 HANDLING

Inputs and outputs are protected against electrostatic discharge in normal handling. However, it is good practice to take

normal precautions appropriate to handling MOS devices.

11 THERMAL CHARACTERISTICS

12 QUALITY SPECIFICATION

In accordance with

“SNW-FQ-611-E”

13 DC CHARACTERISTICS

VDDD =V

DDA = 2.0 V; Tamb =25°C; RL=5kΩ. All voltages with respect to ground (pins VSSA and VSSD); unless

otherwise speciﬁed.

SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT

VDD supply voltage note 1 −4.0 V

Txtal(max) maximum crystal temperature −150 °C

Tstg storage temperature −65 +125 °C

Tamb ambient temperature −40 +85 °C

Ves electrostatic handling voltage human body model −2000 +2000 V

machine model −200 +200 V

SYMBOL PARAMETER CONDITIONS VALUE UNIT

Rth(j-a) thermal resistance from junction to ambient in free air 145 K/W

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Supplies

VDDA DAC analog supply voltage note 1 1.8 2.0 3.6 V

VDDD digital supply voltage note 1 1.8 2.0 3.6 V

IDDA DAC analog supply current normal operating mode; at

2.0 V supply voltage −2.1 −mA

normal operating mode; at

3.0 V supply voltage −3.3 −mA

Sleep mode −150 −µA

DDD digital supply current normal operating mode; at

2.0 V supply voltage −1.2 −mA

normal operating mode; at

3.0 V supply voltage −2.1 −mA

Sleep mode −50 −µA

2000 Oct 25 12

Philips Semiconductors Product speciﬁcation

Low power audio DAC UDA1334TS

Notes

1. All supply connections must be made to the same external power supply unit.

2. At 3 V supply voltage, the input pads are TTL compatible. However, at 2.0 V supply voltage no TTL levels can be

accepted, but levels from 3.3 V domain can be applied to the pins.

3. When the DAC drives a capacitive load above 50 pF, a series resistance of 100 Ω must be used to prevent

oscillations in the output operational amplifier.

14 AC CHARACTERISTICS

14.1 2.0 V supply voltage

VDDD =V

DDA = 2.0 V; fi= 1 kHz; Tamb =25°C; RL=5kΩ. All voltages with respect to ground (pins VSSA and VSSD);

unless otherwise speciﬁed.

Digital input pins; note 2

VIH HIGH-level input voltage at 2.0 V supply voltage 1.3 −3.3 V

at 3.0 V supply voltage 2.0 −5.0 V

VIL LOW-level input voltage at 2.0 V supply voltage −0.5 −+0.5 V

at 3.0 V supply voltage −0.5 −+0.8 V

ILIinput leakage current −−1µA

iinput capacitance −−10 pF

3-level input: pin PCS

VIH HIGH-level input voltage 0.9VDDD −VDDD V

VIM MID-level input voltage 0.4VDDD −0.6VDDD V

VIL LOW-level input voltage 0 −0.5 V

DAC

Vref(DAC) reference voltage with respect to VSSA 0.45VDD 0.5VDD 0.55VDD V

RO(ref) Vref(DAC) reference output

resistance −12.5 −kΩ

Io(max) maximum output current (THD + N)/S < 0.1%;

RL= 800 Ω−0.88 −mA

RLload resistance 3 −−kΩ

Lload capacitance note 3 −−50 pF

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

DAC

Vo(rms) output voltage (RMS value) at 0 dB (FS) digital input −0.5 −V

∆Vounbalance between channels −0.1 −dB

(THD + N)/S total harmonic

distortion-plus-noise to signal

ratio

fs= 44.1 kHz; at 0 dB −−80 −dB

fs= 44.1 kHz; at −60 dB;

A-weighted −−37 −dB

fs= 96 kHz; at 0 dB −−75 −dB

fs= 96 kHz; at −60 dB; A-weighted −−35 −dB

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

2000 Oct 25 13

Philips Semiconductors Product speciﬁcation

Low power audio DAC UDA1334TS

14.2 3.0 V supply voltage

VDDD =V

DDA = 3.0 V; fi= 1 kHz; Tamb =25°C; RL=5kΩ. All voltages with respect to ground (pins VSSA and VSSD);

unless otherwise speciﬁed.

14.3 Timing

VDDD =V

DDA = 1.8 to 3.6 V; Tamb =−20 to +85 °C; RL=5kΩ. The typical timing is speciﬁed at fs= 44.1 kHz (sampling

frequency). All voltages with respect to ground (pins VSSA and VSSD); unless otherwise speciﬁed.

S/N signal-to-noise ratio fs= 44.1 kHz; code = 0;

A-weighted −97 −dB

fs= 96 kHz; code = 0; A-weighted −95 −dB

MUTE = HIGH; A-weighted −110 −dB

αcs channel separation −100 −dB

PSRR power supply rejection ratio fripple = 1 kHz; Vripple = 30 mV (p-p) −60 −dB

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

DAC

Vo(rms) output voltage (RMS value) at 0 dB (FS) digital input −0.75 −V

∆Vounbalance between channels −0.1 −dB

(THD + N)/S total harmonic

distortion-plus-noise to signal

ratio

fs= 44.1 kHz; at 0 dB −−90 −dB

fs= 44.1 kHz; at −60 dB;

A-weighted −−40 −dB

fs= 96 kHz; at 0 dB −−85 −dB

fs= 96 kHz; at −60 dB; A-weighted −−37 −dB

S/N signal-to-noise ratio fs= 44.1 kHz; code = 0;

A-weighted −100 −dB

fs= 96 kHz; code = 0; A-weighted −98 −dB

MUTE = HIGH; A-weighted −110 −dB

αcs channel separation −100 −dB

PSRR power supply rejection ratio fripple = 1 kHz; Vripple = 30 mV (p-p) −60 −dB

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

System clock timing (see Fig.6)

Tsys system clock cycle time fsys = 256fs35 88 780 ns

fsys = 384fs23 59 520 ns

fsys = 512fs17 44 390 ns

tCWH system clock HIGH time fsys < 19.2 MHz 0.3Tsys −0.7Tsys ns

fsys ≥19.2 MHz 0.4Tsys −0.6Tsys ns

tCWL system clock LOW time fsys < 19.2 MHz 0.3Tsys −0.7Tsys ns

fsys ≥19.2 MHz 0.4Tsys −0.6Tsys ns

Serial interface timing (see Fig.7)

fBCK bit clock frequency −−64fsHz

tBCKH bit clock HIGH time 50 −−ns

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

2000 Oct 25 14

Philips Semiconductors Product speciﬁcation

Low power audio DAC UDA1334TS

tBCKL bit clock LOW time 50 −−ns

trrise time −−20 ns

tffall time −−20 ns

tsu(DATAI) set-up time data input 20 −−ns

th(DATAI) hold time data input 0 −−ns

tsu(WS) set-up time word select 20 −−ns

th(WS) hold time word select 10 −−ns

SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

handbook, full pagewidth

MGR984

Tsys

tCWH

tCWL

Fig.6 System clock timing.

handbook, full pagewidth

MGL880

th(WS)

tsu(WS)

tsu(DATAI) th(DATAI)

tBCKH

tBCKL

Tcy(BCK)

BCK

DATAI

Fig.7 Serial interface timing.

2000 Oct 25 15

Philips Semiconductors Product speciﬁcation

Low power audio DAC UDA1334TS

15 APPLICATION INFORMATION

handbook, full pagewidth

MGL879

47 Ω

UDA1334TS

SYSCLK

system

clock

BCK

DATAI

14 VOUTL R3

100 Ω

220 kΩ

16 VOUTR R4

100 Ω

220 kΩ

SFOR1

SFOR0

DEEM

PCS

MUTE

47 µF

(16 V)

47 µF

(16 V)

C3 left

output

right

output

12 Vref(DAC)

47 µF

(16 V)

100 nF

(63 V)

VDDD

VSSD

1 Ω

digital

supply voltage

15 13

VSSA VDDA

1 Ω

47 µF

(16 V)

C10

100 nF

(63 V) 100 nF

(63 V)

analog

supply voltage

47 µF

(16 V)

C1 10 nF

(63 V)

10 nF

(63 V)

Fig.8 Typical application diagram.

2000 Oct 25 16

Philips Semiconductors Product speciﬁcation

Low power audio DAC UDA1334TS

16 PACKAGE OUTLINE

UNIT A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC EIAJ

mm 0.15

0.00 1.4

1.2 0.32

0.20 0.25

0.13 5.30

5.10 4.5

4.3 0.65 6.6

6.2 0.65

0.45 0.48

0.18 10

0.130.2 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.20 mm maximum per side are not included.

0.75

0.45

1.0

SOT369-1 MO-152 95-02-04

99-12-27

yHE

detail X

vMA

(A )

0.25

16 9

pin 1 index

0 2.5 5 mm

scale

SSOP16: plastic shrink small outline package; 16 leads; body width 4.4 mm SOT369-1

max.

1.5

2000 Oct 25 17

Philips Semiconductors Product speciﬁcation

Low power audio DAC UDA1334TS

17 SOLDERING

17.1 Introduction to soldering surface mount

packages

Thistextgivesaverybriefinsighttoacomplextechnology.

A more in-depth account of soldering ICs can be found in

our

“Data Handbook IC26; Integrated Circuit Packages”

(document order number 9398 652 90011).

There is no soldering method that is ideal for all surface

mount IC packages. Wave soldering can still be used for

certainsurfacemountICs, but it is notsuitableforfinepitch

SMDs. In these situations reflow soldering is

recommended.

17.2 Reﬂow soldering

Reflow soldering requires solder paste (a suspension of

fine solder particles, flux and binding agent) to be applied

totheprinted-circuit board byscreenprinting, stencilling or

pressure-syringe dispensing before package placement.

Several methods exist for reflowing; for example,

convection or convection/infrared heating in a conveyor

type oven. Throughput times (preheating, soldering and

cooling) vary between 100 and 200 seconds depending

on heating method.

Typical reflow peak temperatures range from

215 to 250 °C. The top-surface temperature of the

packages should preferable be kept below 220 °C for

thick/large packages, and below 235 °C for small/thin

packages.

17.3 Wave soldering

Conventional single wave soldering is not recommended

forsurfacemountdevices (SMDs) or printed-circuit boards

with a high component density, as solder bridging and

non-wetting can present major problems.

To overcome these problems the double-wave soldering

method was specifically developed.

If wave soldering is used the following conditions must be

observed for optimal results:

•Use a double-wave soldering method comprising a

turbulent wave with high upward pressure followed by a

smooth laminar wave.

•For packages with leads on two sides and a pitch (e):

– larger than or equal to 1.27 mm, the footprint

longitudinal axis is preferred to be parallel to the

transport direction of the printed-circuit board;

– smaller than 1.27 mm, the footprint longitudinal axis

must be parallel to the transport direction of the

printed-circuit board.

The footprint must incorporate solder thieves at the

downstream end.

•Forpackageswithleads on four sides,thefootprintmust

be placed at a 45°angle to the transport direction of the

printed-circuit board. The footprint must incorporate

solder thieves downstream and at the side corners.

During placement and before soldering, the package must

be fixed with a droplet of adhesive. The adhesive can be

applied by screen printing, pin transfer or syringe

dispensing. The package can be soldered after the

adhesive is cured.

Typical dwell time is 4 seconds at 250 °C.

A mildly-activated flux will eliminate the need for removal

of corrosive residues in most applications.

17.4 Manual soldering

Fix the component by first soldering two

diagonally-opposite end leads. Use a low voltage (24 V or

less) soldering iron applied to the flat part of the lead.

Contact time must be limited to 10 seconds at up to

300 °C.

When using a dedicated tool, all other leads can be

soldered in one operation within 2 to 5 seconds between

270 and 320 °C.

2000 Oct 25 18

Philips Semiconductors Product speciﬁcation

Low power audio DAC UDA1334TS

17.5 Suitability of surface mount IC packages for wave and reﬂow soldering methods

Notes

1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum

temperature (with respect to time) and body size of the package, there is a risk that internal or external package

cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the

Drypack information in the

“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”

2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink

(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).

3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.

The package footprint must incorporate solder thieves downstream and at the side corners.

4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;

it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.

5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is

definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

PACKAGE SOLDERING METHOD

WAVE REFLOW(1)

BGA, LFBGA, SQFP, TFBGA not suitable suitable

HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS not suitable(2) suitable

PLCC(3), SO, SOJ suitable suitable

LQFP, QFP, TQFP not recommended(3)(4) suitable

SSOP, TSSOP, VSO not recommended(5) suitable

2000 Oct 25 19

Philips Semiconductors Product speciﬁcation

Low power audio DAC UDA1334TS

18 DATA SHEET STATUS

Note

1. Please consult the most recently issued data sheet before initiating or completing a design.

DATA SHEET STATUS PRODUCT

STATUS DEFINITIONS (1)

Objective speciﬁcation Development This data sheet contains the design target or goal speciﬁcations for

product development. Speciﬁcation may change in any manner without

notice.

Preliminary speciﬁcation Qualiﬁcation This data sheet contains preliminary data, and supplementary data will be

published at a later date. Philips Semiconductors reserves the right to

make changes at any time without notice in order to improve design and

supply the best possible product.

Product speciﬁcation Production This data sheet contains ﬁnal speciﬁcations. Philips Semiconductors

reserves the right to make changes at any time without notice in order to

improve design and supply the best possible product.

19 DEFINITIONS

Short-form specification  The data in a short-form

specification is extracted from a full data sheet with the

same type number and title. For detailed information see

the relevant data sheet or data handbook.

Limiting values definition Limiting values given are in

accordance with the Absolute Maximum Rating System

(IEC 60134). Stress above one or more of the limiting

values may cause permanent damage to the device.

These are stress ratings only and operation of the device

attheseoratanyotherconditionsabove those given in the

Characteristics sections of the specification is not implied.

Exposure to limiting values for extended periods may

affect device reliability.

Application information  Applications that are

described herein for any of these products are for

illustrative purposes only. Philips Semiconductors make

norepresentation orwarrantythatsuchapplicationswill be

suitable for the specified use without further testing or

modification.

20 DISCLAIMERS

Life support applications  These products are not

designed for use in life support appliances, devices, or

systems where malfunction of these products can

reasonably be expected to result in personal injury. Philips

Semiconductorscustomers usingorsellingtheseproducts

for use in such applications do so at their own risk and

agree to fully indemnify Philips Semiconductors for any

damages resulting from such application.

Right to make changes  Philips Semiconductors

reserves the right to make changes, without notice, in the

products, including circuits, standard cells, and/or

software, described or contained herein in order to

improve design and/or performance. Philips

Semiconductors assumes no responsibility or liability for

theuseofany of these products, conveysnolicenceortitle

under any patent, copyright, or mask work right to these

products,andmakesno representations or warrantiesthat

these products are free from patent, copyright, or mask

work right infringement, unless otherwise specified.

All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.

The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed

without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license

under patent- or other industrial or intellectual property rights.

Internet: http://www.semiconductors.philips.com

2000 70

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Printed in The Netherlands 753503/25/02/pp20 Date of release: 2000 Oct 25 Document order number: 9397 750 07497