SN54LV161A, SN74LV161A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS404 APRIL 1998 EPIC (Enhanced-Performance Implanted SN54LV161A ... JOR W PACKAGE CMOS) Process SN74LV161A... D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW) @ Typical Vo_p (Output Ground Bounce) < 0.8 V at Voc, Ta = 25C SIRO: ~ sell Veo Typical Vopy (Output Voy Undershoot) CLK JJ2 15] RCO >2V at Vcc, Ta = 25C Alj3 141] Qa Internal Look-Ahead for Fast Counting BU4 13[] Qp Carry Output for n-Bit Cascading cls taf] Qc Synchronous Counting =NP to a Synchronously Programmable GND [8 gf] LOAD Package Options Include Plastic Small-Outline (D, NS), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), and SNS4LV161A . . . FK PACKAGE Thin Shrink Small-Outline (PW) Packages, (TOP VIEW) Ceramic Flat (W) Packages, Chip Carriers (FK), and DIPs (J) description The *LV1i61A devices are 4-bit synchronous binary counters designed for 2-V to 5.5-V Voc operation. These synchronous, presettable counters feature an internal carry look-ahead for application in 2a aQAO JOE high-speed counting designs. Synchronous fa 6 4 5 if ! operation is provided by having all flip-flops clocked simultaneously so that the outputs NC No internal connection change coincident with each other when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes that normally are associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform. These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. The clear function for the LV161A devices is asynchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low, regardless of the levels of the CLK, load (LOAD), or enable inputs. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO). Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a high-level pulse while the count is maximum (9 or 15 with Qa high). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 1998, Texas Instruments Incorporated PRODUCT PREVIEW information concerns products in the formative or e design phase of development. Characteristic data and other i specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. I TEXAS POST OFFICE BOX 655303 DALLAS, TEXAS 75265 1 PRODUCT PREVIEWPRODUCT PREVIEW SN54LV161A, SN74LV161A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS404 APRIL 1998 description (continued) These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times. The SN54LV 161A is characterized for operation over the full military temperature range of -55C to 125C. The SN74LV161A is characterized for operation from 40C to 85C. logic symbolt 1 CTRDIV16 cLR Nct=0 a: LOAD oT M1 15 10 M2 3CT=15 /}_ RCo ENT _] G3 7 ENP _| G4 CLK _> 5/2,3,44 3 1 c 14 A 1,5D [1] 1 Qa 4 13 B [2] J" @p 5 12 c [4] pe 6 11 D [8] +} Qn Tt This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages. wy TEXAS INSTRUMENTS 2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265SN54LV161A, SN74LV161A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS404 APRIL 1998 logic diagram (positive logic) 9 10 LOAD ENT RCO ENP CLK CLR M1 G2 1, 2T/1C3 G4 3D 4R Qa M1 G2 1, 2T/1C3 G4 3D 4R QB M1 G2 1, 2T/1C3 G4 3D 4R Qc M1 G2 1, 27/13 G4 3D 4R Qp t For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown on the logic diagram of the D/T flip-flops. Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages. Wi TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS, TEXAS 75265 3 PRODUCT PREVIEWPRODUCT PREVIEW SN54LV161A, SN74LV161A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS404 APRIL 1998 logic symbol, each D/T flip-flop LD (Load) M1 TE (Toggle Enable) G2 CK (Clock) + Ff 27/103 Q (Output) G4 D (Inverted Data) C] 3D R (Inverted Reset) C] 4R logic diagram, each D/T flip-flop (positive logic) cK e LD TE a [pt j Ta j-@ TG _ TG Lotq Ta | cRt 1 = Q D CKt TG TG CKt CcKt R t The origins of UD and CK are shown in the logic diagram of the overall device. wy TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS, TEXAS 75265SN54LV161A, SN74LV161A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS404 APRIL 1998 typical clear, preset, count, and inhibit sequence The following sequence is illustrated below: 1. Clear outputs to zero (asynchronous) 2. Preset to binary 12 3. Count to 13, 14, 15, 0, 1, and 2 4. Inhibit CLR | LOAD I ; UI coon | poo - - - - - - - - - - - 4+ LL. | ----------------------- Data B ___ a a a a a a nae eee Tuts pp a a a c | Lo dp _| | Lee | ENP | | | ENT | | | _ | Qa 1 | ) Q@CtOt~d | | | || Data B | Outputs | Qc _J | | | | | ao 4 | | | | | | RCO ly | | | ] | 12 ]13 14 15 oO 1 2 | | \ Count _>+|<__ Inhibit Sync Preset Clear Async Clear Wi TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS, TEXAS 75265 5 PRODUCT PREVIEWPRODUCT PREVIEW SN54LV161A, SN74LV161A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS404 APRIL 1998 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)t Supply voltage range, Voc... eee O5Vt0o7V Input voltage range, V| (see Note 1) .......... 2.2 eee -O5Vto7V Output voltage range, Vo (see Notes 1 and 2) ......... cee es -0.5 Vto Voc + 0.5 V Input clamp current, liq (Vj <0)... . tenet e tenet tenets 20 mA Output clamp current, lox (Vo <0 Or VO>VecC) ..-. ee eee +50 mA Continuous output current, lo (Vo =0t0 Voc) ... 6. ee +25 mA Continuous current through Voc or GND ... 1 teens +50 mA Package thermal impedance, 9), (see Note 3): D package ...................... 0002 eee, 113C/W DB package ......... 0... cece eee eee 131C/W DGV package ........... 0 eee eee 180C/W NS package ....... 0.0... eee eee 111C/W PW package ........... cc eee eee eee 149C/W Storage temperature range, Tgtg .. 6-1 ee eee eee 65C to 150C tT Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 7 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 4) SN54LV161A SN74LV161A UNIT MIN MAX MIN MAX Voc Supply voltage 2 5.5 2 5.5 Vv Voc=2V 1.5 1.5 Vid High-level input voltage Voc=23sVt027V Voc x0.7 Voc x 0.7 V Veoc=3Vto36V Voc x0.7 Voc x 0.7 Voc =45Vto5.5V Voc x0.7 Voc x 0.7 Voc=2V 0.5 0.5 . Voc=23sVt027V Voc x0.3 Voc x0.3 VIL Low-level input voltage Vv Veoc=3Vto36V Voc x0.3 Voc x0.3 Voc =45Vto5.5V Voc x0.3 Voc x0.3 V| Input voltage 0 5.5 0 5.5 Vv Vo Output voltage Vcec Vcec Vv Voc=2V 50 50 HA IOH High-level output current Veo =23 V2 2 2 Veoc=3Vto36V -6 -6 mA Voc =45Vto5.5V -12 -12 Voc=2V 50 50 HA Voc=23sVt027V 2 2 lOL Low-level output current Veoc=3Vto36V 6 6 mA Voc =45Vto5.5V 12 12 Voc=23sVt027V 200 200 Atv/Av _ Input transition rise or fall rate Voc=3Vto36V 0 100 0 100 ns/V Voc =45Vto5.5V 20 20 TA Operating free-air temperature 55 125 40 85 C NOTE 4: All unused inputs of the device must be held at Vcc or GND to ensure proper device operation. Refer to the Tl application report, Implications of Slow or Floating CMOS Inputs, literature number SCBAO04. wy TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS, TEXAS 75265SN54LV161A, SN74LV161A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS404 APRIL 1998 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) SN54LV161A SN74LV161A PARAMETER TEST CONDITIONS Vec UNIT MIN TYP MAX] MIN TYP MAX IOH = 50 HA 2Vto55V |Vcc-0.1 Voc-0.1 lIOH =-2 mA 2.3V 2 2 VOH Vv lIoH =-6 mA 3V 2.48 2.48 lon =-12 mA 45V 3.8 3.8 loL = 50 pA 2Vto55V 0.1 0.1 lol =2mA 2.3V 0.4 0.4 VOL Vv lol =6mA 3V 0.44 0.44 lol = 12 mA 45V 0.55 0.55 I| Vi =Voc or GND 55V +1 +1 HA loc Vi = Voc or GND, lo=0 55V 20 20 HA loft Vior Vo =0to 5.5V OV 5 5 HA 3.3V Cj Vi =Vocc or GND BV pF timing requirements over recommended operating free-air temperature range, Vcc = 2.5 V+0.2V (unless otherwise noted) (see Figure 1) Ta = 25C SN54LV161A | SN74LV161A UNIT MIN MAX] MIN MAX| MIN MAX . CLK high or low tw Pulse duration = ns CLR low CLR Data (A, B, C, and D) tsu Setup time before CLKT ENP, ENT ns LOAD low th Hold time, all synchronous inputs after CLKT ns timing requirements over recommended operating free-air temperature range, Vcc = 3.3 V+0.3 V (unless otherwise noted) (see Figure 1) Ta = 25C SN54LV161A | SN74LV161A UNIT MIN MAX] MIN MAX| MIN MAX ; CLK high or low tw Pulse duration = ns CLR low CLR Data (A, B, C, and D) tsu Setup time before CLKT ENP, ENT ns LOAD low th Hold time, all synchronous inputs after CLKT ns Wi TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS, TEXAS 75265 7 PRODUCT PREVIEWPRODUCT PREVIEW SN54LV161A, SN74LV161A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS404 APRIL 1998 timing requirements over recommended operating free-air temperature range, Vcc =5V+0.5V (unless otherwise noted) (see Figure 1) Ta = 25C SN54LV161A SN74LV161A MIN MAX MIN MAX MIN MAX UNIT CLK high or low tw Pulse duration = CLR low ns CLR Data (A, B, C, and D) t , su Setup time before CLKT ENP, ENT LOAD low ns th Hold time, all synchronous inputs after CLKT ns switching characteristics over recommended operating free-air temperature range, Vec = 2.5 V + 0.2 V (unless otherwise noted) (See Figure 1) Ta = 25C TYP FROM TO (INPUT) (OUTPUT) LOAD CAPACITANCE | Min CL = 15 pF* C_ =50 pF PARAMETER fm ax tPLH" tPHL" tPLH" tPHL" tPLH" tPHL" tPLH" tPHL" CLK Q RCO CLK (count mode) RCO CLK (preset mode) Cy = 15 pF ENT RCO Q * tPHL CLR tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL CLK Q RCO CLK (count mode) RCO CLK (preset mode) C, = 50 pF ENT RCO Q RCO * On products compliant to MIL-PRF-38535, this parameter is not production tested. tPHL CLR MAX SN54LV161A MIN MAX SN74LV161A MIN MAX wy TEXAS INSTRUMENTS 8 POST OFFICE BOX 655303 DALLAS, TEXAS 75265SN54LV161A, SN74LV161A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS404 APRIL 1998 switching characteristics over recommended operating free-air temperature range, Vec = 3.3 V + 0.3 V (unless otherwise noted) (see Figure 1) Ta = 25C SN54LV161A | SN74LV161A PARAMETER FROM TO LOAD A UNIT (INPUT) (OUTPUT) |CAPACITANCE | MIN TYP MAX| MIN MAX] MIN MAX ' CL = 15 pF* max Cl = 50 pF tPLH" tPHL" tPLH" CLK RCO tPHL* (count mode) CLK Q t * ee CLK RCO C= 15 pF tPHL (preset mode) tPLH" - ENT RCO tPHL Q * tPHL CLR tPLH tPHL t PLH CLK RCO tPHL (count mode) CLK Q tPLH RCO CLK CL = 50 pF tPHL (preset mode) tPLH ENT RCO tPHL Q RCO * On products compliant to MIL-PRF-38535, this parameter is not production tested. tPHL CLR Wi TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS, TEXAS 75265 9 PRODUCT PREVIEWPRODUCT PREVIEW SN54LV161A, SN74LV161A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS404 APRIL 1998 switching characteristics over recommended operating free-air temperature range, Vec =5 V+ 0.5 V (unless otherwise noted) (see Figure 1) Ta = 25C SN54LV161A | SN74LV161A PARAMETER FROM TO LOAD A UNIT (INPUT) (OUTPUT) | CAPACITANCE | MIN TYP MAX] MIN MAX] MIN MAX ' CL = 15 pF* max CL = 50 pF tPLH" tPHL" tPLH" CLK RCO tPHL* (count mode) CLK Q t * PLH CLK RCO tPHL* (preset mode) tPLH" - ENT RCO tPHL . Q tPHL CLR tPLH tPHL t PLH CLK RCO tPHL (count mode) CLK Q t PLH CLK RCO tPHL (preset mode) tPLH ENT RCO tPHL Q RCO * On products compliant to MIL-PRF-38535, this parameter is not production tested. tPHL CLR noise characteristics, Vcc = 3.3 V, C_ = 50 pF, Ta = 25C (see Note 5) PARAMETER SNTAWVISTA UNIT MIN TYP MAX VoOL(P) Quiet output, maximum dynamic VoL Vv VoL(v) Quiet output, minimum dynamic VoL Vv VOH(V) Quiet output, minimum dynamic VOH Vv VIH(D) High-level dynamic input voltage Vv VIL(D) Low-level dynamic input voltage Vv NOTE 5: Characteristics are for surface-mount packages only. operating characteristics, Ta = 25C PARAMETER TEST CONDITIONS Vec TYP | UNIT 33V Cod Power dissipation capacitance CL=50pF, f=10MHz BV pF wy TEXAS INSTRUMENTS 10 POST OFFICE BOX 655303 DALLAS, TEXAS 75265SN54LV161A, SN74LV161A 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS404 APRIL 1998 PARAMETER MEASUREMENT INFORMATION From Output Test Under Test Point (see Note A iT LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS From Output Under Test | | | | Voc Input 50% Vcc Ns Vcc OV VOLTAGE WAVEFORMS PULSE DURATION -T-T TT Vcc Input 50% Vcc 50% Vcc OV tPLH + a tPHL In-Ph posey,von n-rnase 50% vee 50% Voc Output VOL | tPHL + J tPLH Out-of-Phase 50% V, | 50% V, oH Output ce wr Voi VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS NOTES: A. C_ includes probe and jig capacitance. RL=1kQ CL (see Note A) T LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS o Voc S1/ 0 Open TEST St GND tPLHtPHL Open tpLzZ/tpzL Vcc tpHz/tpZH GND 1 Open Drain Voc ~~~ Veo Timing Input 50% Vcc | OV \ th tsu <_> | a Vcc Data Input 50% Voc 50% Voc OV VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Voc Output > 5 Control eo % Voc MK Veo ipzL | le | | Lz Output | | | =Vec Waveform 1 50% Vcc S1at Voc | VoL + 0.3 V OL | | Y (see Note B) | tpHz>| lq tpzH | Output | ~ Voy Waveform 2 Vou 0.3 V 0% V, OH $1 at GND 50% Voc \ ov (see Note B) VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. tpLz and tpyz are the same as tgs. tpz_ and tp7} are the same as ten. tPHL and tpLp are the same as tod: Onmoo All input pulses are supplied by generators having the following characteristics: PRR < 1 MHz, Zo = 50 Q, t, <3 ns, t<3 ns. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuit and Voltage Waveforms Wi TEXAS INSTRUMENTS POST OFFICE BOX 655303 DALLAS, TEXAS 75265 11 PRODUCT PREVIEWIMPORTANT NOTICE Texas Instruments and its subsidiaries (Tl) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. Tl warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with Tls standard warranty. Testing and other quality control techniques are utilized to the extent Tl deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (CRITICAL APPLICATIONS). Tl SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. 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