1
Copyright
Cirrus Logic, Inc. 1997
(All Rights Reserved)
Cirrus Logic, Inc.
Crystal Semiconductor Products Divisio n
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.crystal.com
CS5016/14/12A
16, 14, & 12-Bit, Self-Calibrating A/D Converters
Features
-Monolithic CMOS A/D Converters
-Microprocessor Compatible
-Parallel and Serial Output
-Inherent Tr ack/Hold Input
lTrue 12, 14 and 16-Bit Precision
lConversion Times:
-CS5016 16.25 µs
-CS5014 14.25 µs
-CS5012A 7.20 µs
lSelf Calibration Maintains Accuracy Over
Time and Temperature
lLow Power Dissipation: 150mW
lLow Distort ion
Description
The CS5012A/14/16 are 12, 14 and 16-bit monolithic an-
alog to digital converters with conversion times of 7.2 µs,
14.25 µs and 16.25 µs. Unique self-calibration circuitry
insures excellent linearity and differential non- linearity,
with no missing codes. Offset and full scale errors are
kept within 1/2 LSB (CS5012A/14) and 1 LSB (CS5016),
eliminating the need for calibration. Unipolar and bipolar
input ranges are digitally selectable.
The pin compatible CS5012A/14/16 consist of a DAC,
conversion and calibration microcontroller, oscillator,
comparator, microprocessor compatible 3-state I/O, and
calibration circuitry. The input track-and-hold, inherent to
the devices' sampling architecture, acquires the input
signal after each conversion using a fast slewing on-chip
buffer amplifier. This allows throughput rates up to
100 kHz (CS5012A), 56 kHz (CS5014) and 50 kHz
(CS5016).
An evaluation board (CDB5012/14/16) is available which
allows fast evaluation of ADC performance.
ORDERING INFORMATION
See pages 39-41.
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DS14F6
CS5012A
CS5012A ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V;
VA-, VD- = -5V; VREF = 2.5V to 4.5V; fclk = 6.4 MHz for -7, 4 MHz for -12; Analog Source Impedance = 200 Ω)
CS5012A-K CS5012A-B CS5012-T
Parameter* Min Typ Max Min Typ Max Min Typ Max Units
Specified Temperature Range 0 to +70 -40 to +85 -55 to +125 °C
Accuracy
Linearity Error (Note 1)
Drift (Note 2) ±1/4
±1/8 ±1/2 ±1/4
±1/8 ±1/2 ±1/4
±1/8 ±1/2 LSB12
∆LSB12
Differential Linearity (Note 1)
Drift (Note 2) ±1/4
±1/32 ±1/2 ±1/4
±1/32 ±1/2 ±1/4
±1/32 ±1/2 LSB12
∆LSB12
Full Scale Error (Note 1)
Drift (Note 2) ±1/4
±1/16 ±1/2 ±1/4
±1/16 ±1/2 ±1/4
±1/8 ±1/2 LSB12
∆LSB12
Unipolar Offset (Note 1)
Drift (Note 2) ±1/4
±1/16 ±1/2 ±1/4
±1/16 ±1/2 ±1/4
±1/16 ±1/2 LSB12
∆LSB12
Bipolar Offset (Note 1)
Drift (Note 2) ±1/4
±1/16 ±1/2 ±1/4
±1/16 ±1/2 ±1/4
±1/16 ±1/2 LSB12
∆LSB12
Bipolar Negative Full-Scale Error (Note 1)
Drift (Note 2) ±1/4
±1/16 ±1/2 ±1/4
±1/16 ±1/2 ±1/4
±1/16 ±1/2 LSB12
∆LSB12
Total Unadjusted Error (Note 1)
Drift (Note 2) ±1/4
±1/4 ±1/4
±1/4 ±1/4
±1/4 LSB12
∆LSB12
Dynamic Performance (Bipolar Mode)
Peak Harmonic or (Note 1)
Spurious Noise
Full Scale, 1 k Hz Input
Full Scale, 12 k Hz Input 84
84 92
88 84
84 92
88 84
84 92
88 dB
dB
Total Harmonic Distortion 0.008 0.008 0.008 %
Signal-to-Noise Ratio (Note 1)
1 kHz, 0 dB Input
1 kHz, - 60 dB Input 72 73
13 72 73
13 72 73
13 dB
dB
Noise (Note 3)
Unipolar Mode
Bipolar Mode 45
90 45
90 45
90 µVrms
µVrms
Notes: 1. Applies after calibration at any temperature within the specified temper ature range.
2. Total drift over specified temperature range since calibration at power-up at 25 °C
3. Wideband noise aliased into the baseband. Referred to the input.
* Refer to
Parameter Definitions
(immediately following the pin descriptions at the end of this data sheet).
Specifications are s ubject to change without notice.
2DS14F6
CS5012A ANALOG CHARACTERISTICS (continued)
CS5012A-K CS5012A-B CS5012-T
Parameter* Min Typ Max Min Typ Max Min Typ Max Units
Specified Temperature Range 0 to +70 -40 to +85 -55 to +125 °C
Analog Input
Aperture Time 25 25 25 ns
Aperture Jitter 100 100 100 ps
Input Capacitance (Note 4)
Unipolar Mode CS 5012
CS5012A
Bipolar Mode CS5012
CS5012A
275
103
165
72
375
137
220
96
275
103
165
72
375
137
220
96
275
103
165
72
375
137
220
96
pF
pF
pF
pF
Conversion & Throughput
Conversion Time -7 (Notes 5 and 6)
-12 7.2
12.25 7.2
12.25 12.25 µs
µs
Acquisition Time -7 (Note 6)
-12 2.5
3.0 2.8
3.75 2.5
3.0 2.8
3.75 3.0 3.75 µs
µs
Throughput -7 (Note 6)
-12 100
62.5 100
62.5 62.5 kHz
kHz
Power Supplies
DC Power Supply Currents (Note 7)
IA+
IA-
(CS5012) ID+
(CS5012A) ID+
ID-
12
-12
3
6
-3
19
-19
6
7.5
-6
12
-12
3
6
-3
19
-19
6
7.5
-6
12
-12
3
-3
19
-19
6
-6
mA
mA
mA
mA
mA
Power Dissipation (Note 7) 150 250 150 250 150 250 mW
Power Supply Rejection (Note 8)
Positive Supplies
Negative Supplies 84
84 84
84 84
84 dB
dB
Notes: 4. Applies only in track mode. When c onverting or calibrating, input c apacitance will not exceed 15 pF.
5. Measured from falling transition on HOLD to falling transition on EOC.
6. Conversion, acquisition, and throughput times depend on CLKIN, sampling, and calibration conditions.
The numbers shown assume sampling and conversion is synchronized with the CS5012A/14/16 ’s
conversion clock , interleave calibrate is disabled, and operation is from the full-rated, external clock.
Refer to the sec tion
Conversion Time/Throughput
for a detailed discussion of conversion timing.
7. All outputs unloaded. All inputs CMOS levels .
8. With 300 mV p-p, 1 kHz ripple applied to each analog supply separately in bipolar mode. Rejection
improves by 6 dB in the unipolar mode to 90 dB. Figure 13 shows a plot of typical power supply
rejection versus frequency.
CS5012A
DS14F6 3
CS5014 ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V;
VA-, VD - = -5V; VREF = 4.5V ; CLKIN = 4 MHz for -14, 2 MHz for -28; A nalog Source Impedance = 200 Ω)
CS5014-K CS5014-B CS5014-S, T
Parameter* Min Typ Max Min Typ Max Min Typ Max Units
Specified Temperature Range 0 to +70 -40 to +85 -55 to +125 °C
Accuracy
Linearity Error K, B, T (Note 1)
S
Drift (Note 2)
±1/4
±1/8
±1/2 ±1/4
±1/8
±1/2 ±1/4
±1/2
±1/8
±1/2
±1.5 LSB14
LSB14
∆LSB14
Differential Linearity (Note 1)
Drift (Note 2) ±1/4
±1/32 ±1/2 ±1/4
±1/32 ±1/2 ±1/4
±1/32 ±1/2 LSB14
∆LSB14
Full Scale Error (Note 1)
Drift (Note 2) ±1/2
±1/4 ±1±1/2
±1/4 ±1±1/2
±1/2 ±1LSB14
∆LSB14
Unipolar Offset K, B, T (Note 1)
S
Drift (Note 2)
±1/4
±1/4
±3/4 ±1/4
±1/4
±3/4 ±1/4
±1/2
±3/4
±1LSB14
LSB14
∆LSB14
Bipolar Offset K, B, T (Note 1)
S
Drift (Note 2)
±1/4
±1/4
±3/4 ±1/4
±1/2
±3/4 ±1/4
±1/2
±3/4
±1LSB14
LSB14
∆LSB14
Bipolar Negative Full-Scale Error (Note 1)
K, B, T
S
Drift (Note 2)
±1/2
±1/4
±1±1/2
±1/4
±1±1/2
±1/2
±1
±1.5 LSB14
LSB14
∆LSB14
Total Unadjusted Error (Note 1)
Drift (Note 2) ±1
±1/2 ±1
±1±1
±1LSB14
∆LSB14
Dynamic Performance (Bipolar Mode)
Peak Harmonic or (Note 1)
Spurious Noise
Full Scale, 1 kHz Input K, B, T
S
Full Scale, 12 kHz Input K, B, T
S
94
84
98
87
94
84
98
87
94
85
84
80
98
87
dB
dB
dB
dB
Total Harmonic Distortion 0.003 0.003 0.003 %
Signal-to-Noise Ratio (Notes 1 and 9)
1 kHz, 0 dB Input K, B, T
S
1 kHz, - 60 dB Input
82 84
23
82 84
23
82
80 84
23
dB
dB
dB
Noise (Note 3)
Unipolar Mode
Bipolar Mode 45
90 45
90 45
90 µVrms
µVrms
Notes: 9. A detailed plot of S/(N+D) vs. input amplitude appears in Figure 26 for the CS5014 and Figure 28
for the CS5016.
* Refer to
Parameter Definitions
(immediately following the pin descriptions at the end of this data sheet).
Specifications are s ubject to change without notice.
CS5014
4DS14F6
CS5014
CS5014 ANALOG CHARACTERISTICS (continued)
CS5014-K CS5014-B CS5014-S, T
Parameter* Min Typ Max Min Typ Max Min Typ Max Units
Specified Temperature Range 0 to +70 -40 to +85 -55 to +125 °C
Analog Input
Aperture Time 25 25 25 ns
Aperture Jitter 100 100 100 ps
Input Capacitance (Note 4)
Unipolar Mode
Bipolar Mode 275
165 375
220 275
165 375
220 275
165 375
220 pF
pF
Conversion & Throughput
Conversion Time -14 (Notes 5 and 6)
-28 14.25
28.5 14.25
28.5 14.25
28.5 µs
µs
Acquisition Time -14 (Note 6)
-28 3.0
4.5 3.75
5.25 3.0
4.5 3.75
5.25 3.0
4.5 3.75
5.25 µs
µs
Throughput -14 (Note 6)
-28 55.6
27.7 55.6
27.7 55.6
27.7 kHz
kHz
Power Supplies
DC Power Supply Currents (Note 7)
IA+
IA-
ID+
ID-
9
-9
3
-3
19
-19
6
-6
9
-9
3
-3
19
-19
6
-6
9
-9
3
-3
19
-19
6
-6
mA
mA
mA
mA
Power Dissipation (Note 7) 120 250 120 250 120 250 mW
Power Supply Rejection (Note 8)
Positive Supplies
Negative Supplies 84
84 84
84 84
84 dB
dB
DS14F6 5
CS5016
CS5016 ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V;
VA-, VD - = -5V; VREF = 4.5V ; CLKIN = 4 MHz for -16, 2 MHz for -32; A nalog Source Impedance = 200 Ω;
Synchronous S ampling.)
CS5016-J, K CS5016-A, B CS5016-S, T
Parameter* Min Typ Max Min Typ Max Min Typ Max Units
Specified Temperature Range 0 to +70 -40 to +85 -55 to +125 °C
Accuracy
Linearity Error J, A, S (Note 1)
K, B, T
Drift (Note 2)
0.002
0.001
±1/4
0.003
0.0015 0.002
0.001
±1/4
0.003
0.0015 0.002
0.001
±1/4
0.0076
0.0015 %FS
%FS
∆LSB16
Differential Linearity (Note 10) 16 16 16 Bits
Full Scale E rror J, A, S (Note 1)
K, B, T
Drift (Note 2)
±2
±2
±1
±3
±3±2
±2
±1
±3
±3±2
±2
±2
±4
±3LSB16
LSB16
∆LSB16
Unipolar Offset J, A, S (Note 1)
K, B, T
Drift (Note 2)
±1
±1
±1
±2
±3/2 ±1
±1
±1
±3
±3±1
±1
±2
±4
±3LSB16
LSB16
∆LSB16
Bipolar Offset J, A, S (Note 1)
K, B, T
Drift (Note 2)
±1
±1
±1
±2
±3/2 ±1
±1
±2
±2
±2±1
±1
±2
±4
±2LSB16
LSB16
∆LSB16
Bipolar Negative Full-Scale Error (Note 1)
J, A, S
K, B, T
Drift (Note 2)
±2
±2
±1
±3
±3±2
±2
±2
±3
±3±2
±2
±2
±5
±3LSB16
LSB16
∆LSB16
Dynamic Performance (Bipolar Mode)
Peak Harmonic or (Note 1)
Spurious Noise
Full Scale, 1 kHz Input J, A, S
K, B, T
Full Scale, 12 kHz Input J, A, S
K, B, T
96
100
85
85
100
104
88
91
96
100
85
85
100
104
88
91
92
100
82
85
100
104
88
91
dB
dB
dB
dB
Total Harmonic Distortion J, A, S
Full Scale, 1 kHz Input K, B, T 0.002
0.001 0.002
0.001 0.002
0.001 %
%
Signal-to-Noise Ratio (Notes 1 and 9)
1 kHz, 0 dB Input J, A, S
K, B, T
1 kHz, - 60 dB Input J, A, S
K, B, T
87
90 90
92
30
32
87
90 90
92
30
32
84
90 90
92
30
32
dB
dB
dB
dB
Noise (Note 3)
Unipolar Mode
Bipolar Mode 35
70 35
70 35
70 µVrms
µVrms
Notes: 10. Minimum resolution for which no missing codes is guaranteed
* Refer to
Parameter Definitions
(immediately following the pin descriptions at the end of this data sheet).
Specifications are s ubject to change without notice.
6DS14F6
CS5016
CS5016 ANALOG CHARACTERISTICS (continued)
CS5016-J, K CS5016-A, B CS5016-S, T
Parameter* Min Typ Max Min Typ Max Min Typ Max Units
Specified Temperature Range 0 to +70 -40 to +85 -55 to +125 °C
Analog Input
Aperture Time 25 25 25 ns
Aperture Jitter 100 100 100 ps
Input Capacitance (Note 4)
Unipolar Mode
Bipolar Mode 275
165 375
220 275
165 375
220 275
165 375
220 pF
pF
Conversion & Throughput
Conversion Time -16 (Notes 5 and 6)
-32 16.25
32.5 16.25
32.5 16.25
32.5 µs
µs
Acquisition Time -16 (Note 6)
-32 3.0
4.5 3.75
5.25 3.0
4.5 3.75
5.25 3.0
4.5 3.75
5.25 µs
µs
Throughput -16 (Note 6)
-32 50
26.5 50
26.5 50
26.5 kHz
kHz
Power Supplies
DC Power Supply Currents (Note 7)
IA+
IA-
ID+
ID-
9
-9
3
-3
19
-19
6
-6
9
-9
3
-3
19
-19
6
-6
9
-9
3
-3
19
-19
6
-6
mA
mA
mA
mA
Power Dissipation (Note 7) 120 250 120 250 120 250 mW
Power Supply Rejection (Note 8)
Positive Supplies
Negative Supplies 84
84 84
84 84
84 dB
dB
DS14F6 7
SWITCHING CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V ±10%;
VA-, VD- = -5V ±10%; Inputs: Logic 0 = 0V , Logic 1 = VD+ ; CL = 50 pF, BW = VD+)
Parameter Symbol Min Typ Max Units
CS5012A CLKIN Frequency:
Internally Generated:
Externally Supplied: -7
-12
fCLK 1.75
100 kHz
100 kHz
-
-
-
-
6.4
4.0
MHz
MHz
MHz
CS5014/5016 CLKIN Frequency:
Internally Generated: -14, -16
-28, -32
Externally Supplied: -14, -16
-28, -32
fCLK 1.75
1
100 kHz
100 kHz
-
-
-
-
-
-
4
2
MHz
MHz
MHz
MHz
CLKIN Duty Cycle 40 - 60 %
Rise Times: Any Digital Input
Any Digital Output trise -
--
20 1.0
-µs
ns
Fall Times: Any Digital Input
Any Digital Output tfall -
--
20 1.0
-µs
ns
HOLD Pulse Width thpw 1/fCLK+50 - tcns
Conversion Time: CS5012A
CS5014
CS5016
tc49/fCLK+50
57/fCLK
65/fCLK
-
-
-
53/fCLK+235
61/fCLK+235
69/fCLK+235
ns
ns
ns
Data Delay Time tdd - 40 100 ns
EOC Pulse Width (Note 11) tepw 4/fCLK-20 - - ns
Set Up Times: CAL, INTRLV to CS Low
A0 to CS and RD Low tcs
tas 20
20 10
10 -
-ns
ns
Hold Times: CS or RD High to A0 Invalid
CS High to CA L, INTRLV Invalid tah
tch 50
50 30
30 -
-ns
ns
Access Times: CS Low to Data Valid A, B, J, K
S, T
RD Low to Data Valid A, B, J, K
S, T
tca
tra
-
-
-
-
90
115
90
90
120
150
120
150
ns
ns
ns
ns
Output Float Delay: K, B
CS or RD High to Output Hi-Z T tfd -
-90
90 110
140 ns
ns
Serial Clock Pulse Width Low
Pulse Width High tpwl
tpwh -
-2/fCLK
2/fCLK -
-ns
ns
Set Up Times: SDATA to SCLK Rising tss 2/fCLK-50 2/fCLK -ns
Hold Times: SCLK Rising to S DATA tsh 2/fCLK-100 2/fCLK -ns
Notes: 11. EOC remains low 4 CLKIN cycles if CS and RD are held low. Otherwise, it returns high
within 4 CLKIN cycles from the start of a data read operation or a conversion cycle.
C S5012 A, C S5014, CS 5016
8DS14F6
90%
10%
t
fall
rise
t
90%
10%
Hi-Z Hi-Z
ch
t
t
cs
t
ah
t
fd
t
as
tra
t
ca
HOLD
EOC
Ou tp ut Da ta
t
hpw
t
c
LAST CONVERSION DATA VALID
t
dd NEW DATA VALID
t
epw
D0-D15
A0
CS
RD
C AL, INTRLV
SDATA
t
ss tsh
SCLK
t
pwl
t
pwh
Rise and Fall Times
Conversion Timing
Serial Output Timing
Read and Calibration Control Timing
C S5012 A, C S5014, CS 5016
DS14F6 9
C S5012 A, C S5014, CS 5016
DIGITAL CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V ±10%; VA-, VD- = -5V ±10%)
Parameter Symbol Min Typ Max Units
High-Level Input Voltage VIH 2.0 - - V
Low-Level Input Voltage VIL --0.8V
High-Level Output Voltage (Note 12) VOH (VD+ ) - 1.0V - - V
Low-Level Output Voltage Iout = 1.6mA VOL --0.4V
Input Leakage Current Iin --10
µA
3-State Leakage Current IOZ --
±10 µA
Digital Output Pin Capacitance Cout -9-pF
Notes: 12. Iout = -100 µA. This specification guarantees TTL compatibility (VOH = 2.4V @ Iout = -40 µA).
RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0V, see Note 13)
Parameter Symbol Min Typ Max Units
DC Power Supplies: Positive Digital
Negative Digital
Positive Analog
Negative Analog
VD+
VD-
VA+
VA-
4.5
-4.5
4.5
-4.5
5.0
-5.0
5.0
-5.0
VA+
-5.5
5.5
-5.5
V
V
V
V
Analog Reference Voltage VREF 2.5 4.5 (VA+) - 0.5 V
Analog Input Voltage: (Note 14)
Unipolar
Bipolar VAIN
VAIN AGND
-VREF -
-VREF
VREF V
V
Notes: 13. All voltages with respect to ground.
14. The CS5012A/14/16 can ac cept input voltages up to the analog supplies (VA+ and V A-).
It will output all 1’s for inputs above VREF and all 0’s for inputs below AGND in unipolar mode
and -VREF in bipolar mode.
ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0V, all voltages with repect to ground.)
WARNING: Operation at or beyond these limits may reult in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
Parameter Symbol Min Max Units
DC Power Supplies: Positive Digital (Note 15)
Negative Digital
Positive A nalog
Negative Analog
VD+
VD-
VA+
VA-
-0.3
0.3
-0.3
0.3
6.0
-6.0
6.0
-6.0
V
V
V
V
Input Current, Any P in Except Supplies (Note 16) Iin -±10 mA
Analog Input Voltage (AIN and V REF pins) V INA (VA-) - 0.3 (VA+) + 0.3 V
Digital Input Voltage VIND -0.3 (VA+) + 0.3 V
Ambient Operating Temperature TA-55 125 °C
Storage Temperature Tstg -65 150 °C
Notes: 15. In addition, VD+ s hould not be greater than (VA+) + 0.3V.
16. Transient currents of up to 100 mA will not cause SCR latch-up.
10 DS14F6
THEORY OF OPERATION
The CS5012A/14/16 family utilize a successive
approximation conversion technique. The analog
input is successively compared to the output of a
D/A converter controlled by the conversion algo-
rithm. Successive approximation begins by
comparing the analog input to the DAC output
which is set to half-scale (MSB on, all other bits
off). If the input is found to be below half-scale,
the MSB is reset to zero and the input is com-
pared to one-quarter scale (next MSB on, all
others off). If the input were above half-scale, the
MSB would remain high and the next compari-
son would be at three-quarters of full scale. This
procedure continues until all bits have been exer-
cised.
A unique charge redistribution architecture is
used to implement the successive approximation
algorithm. Instead of the traditional resistor net-
work, the DAC is an array of binary-weighted
capacitors. All capacitors in the array share a
common node at the comparator’s input. Their
other terminals are capable of being connected to
AIN, AGND, or VREF (Figure 1). When the de-
vice is not calibrating or converting, all
capacitors are tied to AIN forming Ctot. Switch
S1 is closed and the charge on the array, Qin,
tracks the input sign al Vin (Figure 2a).
When the conversion command is issued, switch
S1 opens as shown in Figure 2b. This traps
charge Qin on the comparator side of the capaci-
tor array and creates a floating node at the
comparator ’s input. The conversion algorithm op-
erates on this fixed charge, and the signal at the
analog input pin is ignored. In effect, the entire
DAC capacitor array serves as analog memory
AIN
VREF
AGND
CC/2
C/4 C/8
MSB
LSB
Bit 11 Bit 10
Bit 9
Bit 8
Bit 0
Dummy
C/X
S1
Bit 13
Bit 15
Bit 12
Bit 14 Bit 11
Bit 13
Bit 10
Bit 12
CS5012A:
CS5014:
CS5016:
C/X
X = 2048
X = 8192
X = 32768
CS5012A
CS5014
CS5016
C = C + C /2 + C/4 + ... + C /X
to t
Figure 1. Charge Redistribution DAC
(1-D)Ctot
in
Q+
-
Vfn To MCU
S1
Ctot
D.
VREF
AGND
D for
VREF
Vin =0V
fn
V=
Figure 2b. Conve rt Mode
in
Q
Ctot
S1
V
in
AIN
+
-
To MC U
=V
in
C
tot
in
-Q
Figure 2a. Tr acking Mode
C S5012 A, C S5014, CS 5016
DS14F6 11
during conversion much like a hold capacitor in a
sample/hold amplifier.
The conversion consists of manipulating the free
plates of the capacitor array to VREF and AGND
to form a capacitive divider. Since the charge at
the floating node remains fixed, the voltage at
that point depends on the proportion of capaci-
tance tied to VREF versus AGND. The
successive-approximation algorithm is used to
find the proportion of capacitance, termed D in
Figure 2b, which when connected to the refer-
ence will drive the voltage at the floating node
(Vfn) to zero. That binary fraction of capacitance
represents the converter ’s digital output.
This charge redistribution architecture easily sup-
ports bipolar input ranges. If half the capacitor
array (the MSB capacitor) is tied to VREF rather
than AIN in the track mode, the input range is
doubled and is offset half-scale. The magnitude
of the reference voltage thus defines both positive
and negative full-scale (-VREF to +VREF), and
the digital code is an offset binary representation
of the input.
Calibration
The ability of the CS5012A/14/16 to convert ac-
curately clearly depends on the accuracy of their
comparator and DAC. The CS5012A/14/16 util-
ize an "auto-zeroing" scheme to null errors
introduced by the comparator. All offsets are
stored on the capacitor array while in the track
mode and are effectively subtracted from the in-
put signal when a conversion is initiated.
Auto-zeroing enhances power supply rejection at
frequencies well below th e conversion rate.
To achieve complete accuracy from the DAC, the
CS5012A/14/16 use a novel self-calibration
scheme. Each bit capacitor, shown in Figure 1,
actually consists of several capacitors which can
be manipulated to adjust the overall bit weight.
An on-chip microcontroller adjusts the subarrays
to precisely ratio the bits. Each bit is adjusted to
just balance the sum of all less significant bits
plus one dummy LSB (for example, 16C = 8C +
4C + 2C + C + C). Calibration resolution for the
array is a small fraction of an LSB resulting in
nearly ideal differential and integral linearity.
DIGITAL CIRCUIT CONNECTIONS
The CS5012A/14/16 can be applied in a wide va-
riety of master clock, sampling, and calibration
conditions which directly affect the devices’ con-
version time and throughput. The devices also
feature on-chip 3-state output buffers and a com-
plete interface for connecting to 8-bit and 16-bit
digital systems. Output data is also available in
serial format.
Master Clock
The CS5012A/14/16 operate from a master clock
(CLKIN) which can be externally supplied or in-
ternally generated. The internal oscillator is
activated by externally tying the CLKIN input
low. Alternatively, the CS5012A/14/16 can be
synchronized to the external system by driving
the CLKIN pin with a TTL or CMOS clock sig-
nal.
CLKIN
Master Clock
(Optional)
HOLD
EOT
CS5012A/14/16
Figure 3b. Synchronous Sampling
CLKIN
Master Clock
(Optional)
HOLD
Sampling
Clock
CS5012A/14/16
Figure 3a. Asynchronous Sampling
C S5012 A, C S5014, CS 5016
12 DS14F6
All calibration, conversion, and throughput times
directly scale to CLKIN frequency. Thus,
throughput can be precisely controlled and/or
maximized using an external CLKIN signal. In
contrast, the CS5012A/14/16’s internal oscillator
will vary from unit-to-unit and over temperature.
The CS5012A/14/16 can typically convert with
CLKIN as low as 10 kHz at room temperature.
Initiating Conversions
A falling transition on the HOLD pin places the
input in the hold mode and initiates a conversion
cycle. Upon completion of the conversion cycle,
the CS5012A/14/16 automatically return to the
track mode. In contrast to systems with separate
track-and-holds and A/D converters, a sampling
clock can simply be connected to the HOLD in-
put (Figure 3a). The duty cycle of this clock is
not critical. It need only remain low at least one
CLKIN cycle plus 50 ns, but no longer than the
minimum conversion time or an additional con-
version cycle will be initiated with inadequate
time for acquisition.
Microprocessor-Controlled Operation
Sampling and conversion can be placed under
microprocessor control (Figure 4) by simply gat-
ing the devices’ decoded address with the write
strobe for the HOLD input. Thus, a write cycle to
the CS5012A/14/16’s base address will initiate a
conversion. However, the write cycle must be to
the odd address (A0 high) to avoid initiating a
software controlled reset (see Reset below).
The calibration control inputs, CAL, and
INTRLV are inputs to a set of transparent latches.
These signals are internally latched by CS return-
ing high. They must be in the appropriate state
whenever the chip is selected during a read or
write cycle. Address lines A1 and A2 are shown
connected to CAL and INTRLV in Figure 4 plac-
ing calibration under microprocessor control as
well. Thus, any read or write cycle to the
CS5012A/14/16’s base address will initiate or ter-
minate calibration. Alternatively, A0, INTRLV,
and CAL may be connected to the microproces-
sor data bus.
Conversion Time/Throughput
Upon completing a conversion cycle and return-
ing to the track mode, the CS5012A/14/16
require time to acquire the analog input signal
before another conversion can be initiated. The
acquisition time is specified as six CLKIN cycles
plus 2.25 µs (1.32 µs for the CS5012A -7 version
only). This adds to the conversion time to define
the converter’s maximum throughput. The con-
version time of the CS5012A/14/16, in turn,
depends on the sampling, calibration, and CLKIN
conditions.
HOLD
CS5012A/14/16
Addr
Dec
A3
AN
Address
Bus
WR
RD
CS
RD
INTRLV
A2
A1
CAL
A0
A0
ADDR VALID
Figure 4b. Conversions under Microprocessor Control
CS5012A/14/16
CS
Addr
Dec
A3
AN
Address
Bus
RDRD
CONCLK HOLD
INTRLV
CAL
A0
A2
A1
A0
ADDR VALID
Figure 4a. Conversions Asynchronous to CLKIN
C S5012 A, C S5014, CS 5016
DS14F6 13
Asynchronous Sampling
The CS5012A/14/16 internally operate from a
clock which is delayed and divided down from
CLKIN (fCLK/4). If sampling is not synchronized
to this internal clock, the conversion cycle may
not begin until up to four clock cycles after
HOLD goes low even though the charge is
trapped immediately. In this asynchronous mode
(Figure 3a), the four clock cycles add to the
minimum 49, 57 and 65 clock cycles (for the
CS5012A/14/16 respectively) to define the maxi-
mum conversion time (see Figure 5a and
Table 1).
Synchronous Sampling
To achieve maximum throughput, sampling can
be synchronized with the internal conversion
clock by connecting the End-of-Track (EOT) out-
put to HOLD (Figure 3b). The EOT output falls
15 CLKIN cycles after EOC indicating the ana-
log input has been acquired to the
CS5012A/14/16’s specified accuracy. The EOT
output is synchronized to the internal conversion
clock, so the four clock cycle synchronization un-
certainty is removed yielding throughput at
[1/64]fCLK for the CS5012A, [1/72]fCLK for
CS5014 and [1/80]fCLK for CS5016 where fCLK
is the CLKIN frequency (see Figure 5b and Ta-
ble 1).
*
Conversion
(49 + N cycles)
1 / Thro ughput
(64 + N cycles)
Output
EOT
Output
EOC
Input
HOLD
Acquisition
(15 cycles)
*Dashe d line : CS & RD = 0 CS50 12A N = 0
Solid line: See Figure 9 CS5014 N = 8
CS50 16 N = 16
Figure 5b. Synchronous (Loopback Mode)
Conversion
Synchronization U ncertainty (4 cycles)
Input
Output
Output
Acquisition
HOLD
EOC
EOT
1 / Throughput
Figure 5a. Asynchronous Sampling (External Clock)
Throughput TimeConversion Time
Sampling Mode
Synchronous (Loopback)
Asynchronous
Min
64 tclk
N/A
N/A
Max
64 tclk
59 1.32
µ
s
tclk+
59 2.25
µ
s
tclk+
Max
+ 235 ns53 tclk
49 tclk
+ 235 ns53 tclk
Min
49 tclk
49 tclk
49 tclk
-7
-12,-24
CS5012A
CS5014
57 tclk
57 tclk + 235 ns61 tclk
57 tclk 72 tclk
N/A
72 tclk
67 2.25
µ
s
tclk+
Synchronous (Loopback)
Asynchronous
65 tclk
65 tclk + 235 ns69 tclk
65 tclk 80 tclk
N/A
80 tclk
75 2.25
µ
s
tclk+
Synchronous (Loopback)
Asynchronous
CS5016
Table 1. Conv ersion and Throughput Times (tclk = Master Clock Period)
C S5012 A, C S5014, CS 5016
14 DS14F6
Also, the CS5012A/14/16’s internal RC oscillator
exhibits jitter (typically ± 0.05% of its period),
which is high compared to crystal oscillators. If
the CS5012A/14/16 is configured for synchro-
nous sampling while operating from its internal
oscillator, this jitter will directly affect sampling
purity. The user can obtain best sampling purity
while synchronously sampling by using an exter-
nal crystal-based clock.
Reset
Upon power up, the CS5012A/14/16 must be re-
set to guarantee a consistent starting condition
and initially calibrate the devices. Due to the
CS5012A/14/16’s low power dissipation and low
temperature drift, no warm-up time is required
before reset to accommodate any self-heating ef-
fects. However, the voltage reference input
should have stabilized to within 5%, 1% or
0.25% of its final value, for the CS5012A/14/16
respectively, before RST falls to guarantee an ac-
curate calibration. Later, the CS5012A/14/16 may
be reset at any time to initiate a single full cali-
bration. Reset overrides all other functions. If
reset, the CS5012A/14/16 will clear and initiate a
new calibration cycle mid-conversion or mid-
calibration.
Resets can be initiated in hardware or software.
The simplest method of resetting the
CS5012A/14/16 involves strobing the RST pin
high for at least 100 ns. When RST is brought
high all internal logic clears. When it returns low,
a full calibration begins which takes 58,280
CLKIN cycles for the CS5012A (approximately
9.1 ms with a 6.4 MHz clock) and 1,441,020
CLKIN cycles for the CS5016, CS5014 and
CS5012 (approximately 360 ms with a 4 MHz
CLKIN). A simple power-on reset circuit can be
built using a resistor and capacitor, and a
Schmitt-trigger inverter to prevent oscillation (see
Figure 6). The CS5012A/14/16 can also be reset
in software when under microprocessor control.
The CS5012A/14/16 will reset whenever CS, A0 ,
and HOLD are taken low simultaneously. See the
Microprocessor Interface section (below) to
eliminate the possibility of inadvertent software
reset. The EOC output remains high throughout
the calibration operation and will fall upon its
completion. It can thus be used to generate an
interrupt indicating the CS5012A/14/16 is ready
for operation. While calibrating, the HOLD input
is ignored until EOC falls. After EOC falls, six
CLKIN cycles plus 2.25 µs (1.32 µs for the
CS5012A -7 version only) must be allowed for
signal acquisition before HOLD is activated. Un-
der microprocessor-independent operation (CS,
RD low; A0 high) the CS5014’s and CS5016’s
EOC output will not fall at the completion of the
calibration cycle, but EOT will fall 15 CLKIN
cycles later.
Initiating Calibration
All modes of calibration can be controlled in
hardware or software. Accuracy can thereby be
insured at any time or temperature throughout
operating life. After initial calibration at power-
up, the CS5012A/14/16’s charge-redistribution
design yields better temperature drift and more
graceful aging than resistor-based technologies,
so calibration is normally only required once, af-
ter power-up.
The first mode of calibration, reset, results in a
single full calibration cycle. The second type of
calibration, "burst" cal, allows control of partial
calibration cycles. Due to an unforeseen con-
didtion inside the part, asynchronous termination
of calibration may result in a sub-optimal result.
Burst cal should not be used.
C
R
+5V
RST
CS5012A/14/16
Figure 6. Power- on Reset Circuit
C S5012 A, C S5014, CS 5016
DS14F6 15
The reset calibration always works perfectly, and
should be used instead of burst mode. The
CS5012’s and CS5012A/14/16’s very low drift
over temperature means that, under most circum-
stances, calibration will only need to be
performed at power-up, using reset.
The CS5012A/14/16 feature a background cali-
bration mode called "interleave." Interleave
appends a single calibration experiment to each
conversion cycle and thus requires no dead time
for calibration. The CS5012A/14/16 gathers data
between conversions and will adjust its transfer
function once it completes the entire sequence of
experiments (one calibration cycle per 2,014 con-
versions in the CS5012A and one calibration per
72,051 conversions in the CS5012, CS5014 and
CS5016). Initiated by bringing both the INTRLV
input and CS low (or hard-wiring INTRLV low),
interleave extends the CS5012A/14/16’s effective
conversion time by 20 CLKIN cycles. Other than
reduced throughput, interleave is totally transpar-
ent to the user. Interleave calibration should not
be used intermittently.
The fact that the CS5012A/14/16 offer several
calibration modes is not to imply that the devices
need to be recalibrated often. The devices are
very stable in the presence of large temperature
changes. Tests have indicated that after using a
single reset calibration at 25 °C most devices ex-
hibit very little change in offset or gain when
exposed to temperatures from -55 to +125 °C.
The data indicated 30 ppm as the typical worst
case total change in offset or gain over this tem-
perature range. Differential linearity remained
virtually unchanged. System error sources outside
of the A/D converter, whether due to changes in
temperature or to long-term aging, will generally
dominate total system error.
Microprocessor Interface
The CS5012A/14/16 feature an intelligent micro-
processor interface which offers detailed status
information and allows software control of the
self-calibration functions. Output data is available
in either 8-bit or 16-bit formats for easy interfac-
ing to industry-standard microprocessors.
Strobing both CS and RD low enables the
CS5012A/14/16’s 3-state output buffers with
either output data or status information depending
on the status of A0. An address bit can be con-
nected to A0 as shown in Figure 4b thereby
memory mapping the status register and output
data. Conversion status can be polled in software
by reading the status register (CS and RD strobed
low with A0 low), and masking status bits S0-S5
and S7 (by logically AND’ing the status word
with 01000000) to determine the value of S6.
Similarly, the software routine can determine
calibration status using other status bits (see Ta-
ble 2). Care must be taken not to read the status
register (A0 low) while HOLD is low, or a soft-
ware reset will result (see Reset above).
Alternatively, the End-of-Convert (EOC) output
can be used to generate an interrupt or drive a
DMA controller to dump the output directly into
memory after each conversion. The EOC pin falls
as each conversion cycle is completed and data is
valid at the output. It returns high within four
CLKIN cycles of the first subsequent data read
operation or after the start of a new conversion
cycle.
C S5012 A, C S5014, CS 5016
16 DS14F6
To interface with a 16-bit data bus, the BW input
to the CS5012A/14/16 should be held high and
all data bits (12, 14 and 16 for the CS5012A,
CS5014 and CS5016 respectively) read in paral-
lel on pins D4-D15 (CS5012A), D2-D15
(CS5014), or D0-D15 (CS5016). With an 8-bit
bus, the converter’s result must be read in two
portions. In this instance, BW should be held low
and the 8 MSB’s obtained on the first read cycle
following a conversion. The second read cycle
will yield the remaining LSB’s (4, 6 or 8 for the
CS5012A/14/16 respectively) with 4, 2 or 0 trail-
ing zeros. Both bytes appear on pins D0-D7. The
upper/lower bytes of the same data will continue
to toggle on subsequent reads until the next con-
version finishes. Status bit S2 indicates which
byte will appear on the next data read operation.
The CS5012A/14/16 internally buffer their output
data, so data can be read while the devices are
tracking or converting the next sample. There-
fore, retrieving the converters’ digital output
requires no reduction in ADC throughput. Ena-
bling the 3-state outputs while the
CS5012A/14/16 is converting will not introduce
conversion errors. Connecting CMOS logic to the
digital outputs is recommended. Suitable logic
families include 4000B, 74HC, 74AC, 74ACT,
and 74HCT.
PIN STATUS BIT STATUS DEFINITION
D0 S0 END OF CONV ERSION Fa lls upon compl etion of a con version ,
and returns high on the first subsequent read.
D1 S1 RESERVED Reserved for factory use.
D2 S2 LOW BYTE/HIGH BYTE When data is to be read in an 8-bit format (BW=0),
indica tes which byt e will appear at the outpu t next.
D3 S3 END OF TRACK When low, indi cates the inpu t has been a cquir ed to
the devi ces specif ied accurac y.
D4 S4 RESERVED Reserved for factory use.
D5 S5 TRACK ING High w hen the devi ce is track ing the in put.
D6 S6 CONVERTING High whe n the device is co nvertin g the held input .
D7 S7 CALIBR ATIN G H igh when the de vice is cali brating.
Table 2. Status Pin Definitions
D7 D0D5 D3 D2 D1D6 D4D12 D11 D10 D9 D8D15 D14 D13
XXXXX XX X S7 S6 S5 S4 S3 S2 S1 S0 8- or 16-Bit
Data Bus
Data
(A0=1)
Status
(A0=0)
"X" Denotes High Impedance Output
XXXXX XXX
8-Bit Bus
(BW=0)
16-Bit Bus
(BW=1)
B5 B4B11 B10 B7 B6B8B9
CS5012A
CS5014
CS5016 B13 B11 B9 B7 B6
B12 B10 B8
B5 B4B11 B10 B7 B6B8B9
B15 B13 B11 B9 B8
B14 B12 B10
B3 B2 B1 B0 0 000
B5 B4 B3 B2 0 0B1 B0
B7 B6 B5 B4 B1 B0B3 B2
B3 B2 B1 B0 0 000
XXXXX XXX B7 B6B13 B12 B9 B8B10B11
B5 B4 B3 B2 0 0B1 B0
XXXXX XXX B9 B8B15 B14 B11 B10B12B13
B7 B6 B5 B4 B1 B0B3 B2
CS5016
CS5014
CS5012A
Figure 7. CS5012A/14/16 Data Format
C S5012 A, C S5014, CS 5016
DS14F6 17
Microprocessor Independent Operation
The CS5012A/14/16 can be operated in a stand-
alone mode independent of intelligent control. In
this mode, CS and RD are hard-wired low. This
permanently enables the 3-state output buffers
and allows transparent latch inputs (CAL and
INTRLV) to be active. A free-running condition
is established when BW is tied high, CAL is tied
low, and HOLD is continually strobed low or tied
to EOT. The CS5012A/14/16’s EOC output can
be used to externally latch the output data if de-
sired. With CS and RD hard-wired low, EOC will
strobe low for four CLKIN cycles after each con-
version. Data will be unstable up to 100 ns after
EOC falls, so it should be latched on the rising
edge of EOC.
Serial Output
All successive-approximation A/D converters de-
rive their digital output serially starting with the
MSB. The CS501 2A/14/16 present each bit to the
SDATA pin four CLKIN cycles after it is derived
and can be latched using the serial clock output,
SCLK. Just subsequent to each bit decision
SCLK will fall and return high once the bit infor-
mation on SDATA has stabilized. Thus, the rising
edge of the SCLK output should be used to clock
the data from the CS5012A/14/16 (See Figure 9).
ANALOG CIRCUIT CONNECTIONS
Most popular successive-approximation A/D con-
verters generate dynamic loads at their analog
connections. The CS5012A/14/16 internally buff-
er all analog inputs (AIN, VREF, and AGND) to
ease the demands placed on external circuitry.
However, accurate system operation still requires
careful attention to details at the design stage re-
garding source impedances as well as grounding
and decoupling schemes.
Reference Considerations
An application note titled "Voltage References for
the CS501X Series of A/D Converters" is avail-
able for the CS5012A/14/16. In addition to
working through a reference circuit design exam-
ple, it offers several built-and-tested reference
circuits.
During conversion, each capacitor of the cali-
brated capacitor array is switched between VREF
and AGND in a manner determined by the suc-
cessive-approximation algorithm. The charging
and discharging of the array results in a current
load at the reference. The CS5012A/14/16 in-
clude an internal buffer amplifier to minimize the
external reference circuit’s drive requirement and
preserve the reference’s integrity. Whenever the
array is switched during conversion, the buffer is
used to pre-charge the array thereby providing
the bulk of the necessary charge. The appropriate
array capacitors are then switched to the unbuf-
fered VREF pin to avoid any errors due to offsets
and/or noise in the buffer.
The external reference circuitry need only pro-
vide the residual charge required to fully charge
the array after pre-charging from the buffer. This
creates an ac current load as the CS5012A/14/16
sequence through conversions. The reference cir-
cuitry must have a low enough output impedance
to drive the requisite current without changing its
output voltage significantly. As the analog input
signal varies, the switching sequence of the inter-
nal capacitor array changes. The current load on
the external reference circuitry thus varies in re-
sponse with the analog input. Therefore, the
external reference must not exhibit significant
BW
CAL
RST
Reset
A0
CS
HOLD
+5V
Sampling
Clock
RD
D4
D15
Data
Out
12-Bit
EOC
Latching
Output
INTRLV
CS5012A
CS5014
CS5016
Figure 8. Microprocessor-Independent Connections
C S5012 A, C S5014, CS 5016
18 DS14F6
peaking in its output impedance characteristic at
signal frequencies or their harmonics.
A large capacitor connected between VREF and
AGND can provide sufficiently low output im-
pedance at the high end of the frequency
spectrum, while almost all precision references
exhibit extremely low output imp edance at d c.
The magnitude of the current load on the external
reference circuitry will scale to the CLKIN fre-
quency. At full speed, the reference must supply a
maximum load current of 10 µA peak-to-peak
(1 µA typical). For the CS5012A an output im-
pedance of 15 Ω will therefore yield a maximum
error of 150 mV. With a 2.5V reference and LSB
size of 600 mV, this would insure better than 1/4
LSB accuracy. A 1 µF capacitor exhibits an im-
pedance of less than 15 Ω at frequencies greater
than 10 kHz. Similarly, for the CS5014 with a
4.5V reference (275µV/LSB), better than
1/4 LSB accuracy can be insured with an output
impedance of 4Ω or less (maximum error of
40 µV). A 2.2 µF capacitor exhibits an imped-
ance of less than 4Ω at frequencies greater than
5kHz. For the CS5016 with a 4.5V reference
(69µV/LSB), better than 1/4 LSB accuracy can
be insured with an output impedance of less than
2Ω (maximum error of 20 µV). A 20 µF capaci-
tor exhibits an impedance of less than 2Ω at
frequencies greater than 16 kHz. A high-quality
tantalum capacitor in parallel with a smaller ce-
ramic capacitor is recommended.
CLKIN
EOC
Status
EOT
HOLD
SCLK
SDATA
t
d
t
d
Determined
LSB F ine Charge Determined
MSB
Determined
MSB - 1
Determined
MSB - 2
Coarse Charge
LSB+1 LSB MSB
MSB - 1
LSB+2
246
8
10 12646260 80/076 787472706866
CS5016:
246
8
10 125654 72/068 70666462605852
CS5014:
246
8
10 12484644 64/060 625856545250
CS5012A:
Figure 9. Serial Output Timing
Notes: 1. Syn chronous (loopback) mode is illustrated. After EOC fa lls the co nverter g oes into co arse charge mo de for
6 CLK IN cycles , then to fin e charge mode for 9 cycles , then EOT falls. In loopback m ode, EOT trips HOLD
which captu res the analog sam ple. Conversion begins on the next risin g edge of CLKIN. If oper ated asynchro-
nously, EOT will remain low until after HOLD is taken low. When HOL D occ urs th e an alog sample is ca ptured
immediately, b ut conversion may not begin until four CLKIN cycles later. EOT will return high
when co nversion begins.
2. Timing delay t d (relative to CLKIN) can vary between 135 ns to 235 ns ov er the military temperature range
and ov er ± 10% supply variation
3. EOC returns high in 4 CLKIN cycles if A0 = 1 and CS = RD = 0 (Microprocesso r Independen t Mode );
within 4 CLKIN cycles after a data read (Microprocessor Mode); or 4 CLKIN cycles after HOLD = 0
is recognized on a rising edge of CLKIN/4.
C S5012 A, C S5014, CS 5016
DS14F6 19
Peaking in the reference’s output impedance can
occur because of capacitive loading at its output.
Any peaking that might occur can be reduced by
placing a small resistor in series with the capaci-
tors (Figure 10). The equation in Figure 10 can
be used to help calculate the optimum value of R
for a particular reference. The term "fpeak" is the
frequency of the peak in the output impedance of
the reference before the resistor is added.
The CS5012A/14/16 can operate with a wide
range of reference voltages, but signal-to-noise
performance is maximized by using as wide a
signal range as possible. The recommended refer-
ence voltage is between 2.5 and 4.5 V for the
CS5012A and 4.5 V for the CS5014/16. The
CS5012A/14/16 can actually accept reference
voltages up to the positive analog supply. How-
ever, the buffer’s offset may increase as the
reference voltage approaches VA+ thereby in-
creasing external drive requirements at VREF. A
4.5V reference is the maximum reference voltage
recommended. This allows 0.5V headroom for
the internal reference buffer. Also, the buffer en-
lists the aid of an external 0.1 µF ceramic
capacitor which must be tied between its output,
REFBUF, and the negative analog supply, VA-. For
more information on references, consult the applica-
tion note: Voltage References for the CS501X Se-
ries of A/D Converters. For an example of using
the CS5012A/14/16 with a 5 volt reference, see
the application note: A Collection of Application
Hints for the CS501X Series of A/D Converters.
Analog Input Connection
The analog input terminal functions similarly to
the VREF input after each conversion when
switching into the track mode. During the first
six CLKIN cycles in the track mode, the buffered
version of the analog input is used for pre-charg-
ing the capacitor array. An additional period is
required for fine-charging directly from AIN to
VREF
REFBUF
VA-
0.1
µ
F
-5V
R
29
28
30
ref
V
C1
1.0
µ
F
0.01
µ
F
C2
+V
ee
CS5012A
CS5014
CS5016
1
R= 2π (C1 + C2) fpeak
Figure 10. Reference Connections
Inte r na l C ha rg e E rro r (LS B ’ s )
Fine-ChargePre-Charge
Acquisition Time (us)
0.5 1.0 1.5 2.0 2.5
(Delay from EOC)
+12.5
0
-12.5
-25.0
+50
0
-50
-100
+200
0
-200
-400
CS5012ACS5014CS5016
Figure 11. Internal Acquisition T ime
C S5012 A, C S5014, CS 5016
20 DS14F6