Features
•High P e rformance, Low Power 32-bit Atmel® AVR® Microcontroller
– Compact Single-Cycle RISC Instruction Set Including DSP Instruction Set
– Read-Modify-Write Instructions and Atomic Bit Manipulation
– Performing up to 1.51DMIPS/MHz
• Up to 126 DMIPS Running at 84MHz from Flash (1 Wait-State)
• Up to 63 DMIPS Running at 42MHz from Flash (0 Wait-State)
– Memory Protectio n Unit
•Multi-Layer Bus System
– High-P erformance Data Transfers on Separate Buses for Increased Performance
– 8 Peripheral DMA Channels (PDCA) Improves Speed for Peripheral
Communication
– 4 generic DMA Channels for High Bandwidth Data Paths
•Internal High-Speed Flash
– 256KBytes, 128KBytes, 64KBytes versions
– Single-Cycle Flash Access up to 36MHz
– Prefetch Buffer Optimizing Instruction Execution at Maximum Speed
– 4ms Page Programming Time and 8ms Full-Chip Erase Time
– 100,000 Write Cycles, 15-year Data Retention Capability
– Flash Security Locks and User Defined Configuratio n Area
•Internal High-Speed SRAM
– 64KBytes Single-Cycle Access at Full Speed, Connected to CPU Local Bus
– 64KBytes (2x32KBytes with independent access) on the Multi-Layer Bus System
•Interrupt Controller
– Autovectored Low Latency Interrupt Service with Programmable Priority
•System Functions
– Power and Clock Manager Including Internal RC Clock and One 32KHz Oscillator
– Two Multipurpose Oscillators and Two Phase-Lock-Loop (PLL),
– Watchdog Timer, Real-Time Clock Timer
•External Memories
– Support SDRAM, SRAM, NandFlash (1-bit and 4-bit ECC), Compact Flash
– Up to 66 MHz
•External Storage device support
– MultiMediaCard (MMC V4.3), Secure-Digital (SD V2.0), SDIO V1.1
– CE-ATA V1.1, FastSD, SmartMedia, Compact Flash
– Memory Stick: Standard Format V1.40, PRO Format V1.00, Micro
– IDE Interface
•One Advanced Encryption System (AES) for AT32UC3A3256S, AT32UC3A3128S,
AT32UC3A364S, AT32UC3A4256S, AT32UC3A4128S and AT32UC3A364S
– 256-, 192-, 128-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications
– Buffer Encryption/Decryption Capabilities
•Universal Serial Bus (USB)
– High-Speed USB 2.0 (480Mbit/s) Device and Embedded Host
– Flexible End-Point Conf iguration and Manage ment with Dedicated DMA Channels
– On-Chip Transceivers Inc luding Pull-Ups
•One 8-channel 10-bit Analog-To-Digital Converter, multiplexed with Digital IOs.
•Two Three-Channel 16-bit Timer/Counter (TC)
•Four Universal Synchronous/Async hronous Receiver/Transmitters (USART)
– Fractionnal Baudrate Generator
32-bit AVR
Microcontroller
AT32UC3A3256S
AT32UC3A3256
AT32UC3A3128S
AT32UC3A3128
AT32UC3A364S
AT32UC3A364
AT32UC3A4256S
AT32UC3A4256
AT32UC3A4128S
AT32UC3A4128
AT32UC3A464S
AT32UC3A464
32072H-AVR32–10/2012
2
32072H–AVR32–10/2012
AT32UC3A3
– Support for SPI and LIN
– Optionnal support for IrDA, ISO7816, Hardware Handshaking, RS485 interfaces and Modem Line
•Two Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals
•One Synchronous Serial Protocol Controller
– Supports I2S and Generic Frame-Based Protocols
•Two Master/Slave Two-Wire Interface (TWI), 400kbit/s I2C-compatible
•16-bit Stereo Audio Bitstream
– Sample Rate Up to 50 KHz
•QTouch® Library Support
– Capacitive Touch Buttons, Sliders, and Wheels
– QTouch and QMatrix Acquis ition
•On-Chip Debug System (JTAG interface)
– Nexus Class 2+, Runtime Control, Non-Intrusive Data and Program Trace
•110 General Purpose Input/Output (GPIOs)
– Standard or High Speed mode
– Toggle capability: up to 84MHz
•Packages
– 144-ball TFBGA, 11x11 mm, pitch 0.8 mm
– 144-pin LQFP, 22x22 mm, pitch 0.5 mm
– 100-ball VFBGA, 7x7 mm, pitch 0.65 mm
•Single 3.3V Po wer Supply
3
32072H–AVR32–10/2012
AT32UC3A3
1. Description The AT32UC3A3/A4 is a complete System-On-Chip microcontroller based on the AVR32 UC
RISC processor running at frequencies up to 84MHz. AVR32 UC is a high-performance 32-bit
RISC microprocessor core, designed for cost-sensitive embedded applications, with particular
emphasis on low power consumption, high code density and high performance.
The processor implements a M emory Protection Unit (MPU) and a fast a nd flexible interru pt con-
troller for supporting modern operating systems and real-time operating systems. Higher
computation capabilities are achievable using a rich set of DSP instructions.
The AT32UC3A3/A4 incorporates on-chip Flash and SRAM memories for secure and fast
access. 64 KBytes of SRAM are directly coupled to the AVR32 UC for performa nces optimiza-
tion. Two blocks of 32 Kbytes SRAM are independently attached to the High Speed Bus Matrix,
allowing real ping-pong management.
The Peripheral Direct Memory Access Controller (PDCA) enables data transfers between
peripherals and memories without processor involvement. T he PDCA drastically reduces pro-
cessing overhead when transferring continuous and large data streams.
The Power Manager improves design flexibility and security: the on-chip Brown-Out Detector
monitors the power supply, the CPU runs from the on-chip RC oscillator or from one of external
oscillator sources, a Real-Time Clock and its associated timer keeps track of the time.
The device includes two sets of three identical 16-bit Timer/Counter (TC) channels. Each chan-
nel can be independently programmed to perform frequency measurement, event counting,
interval measurement, pulse generation, delay timin g and pulse width modulation. 16-bit chan-
nels are combined to operate as 32-bit channels.
The AT32UC3A3/A4 also features many communication interfaces for communication intensive
applications like UART, SPI or TWI. The USART supports different communication modes, like
SPI Mode and LIN Mode. Additionally, a flexible Synchronous Serial Controller (SSC) is avail-
able. The SSC provides easy access to serial communication protocols and audio standards like
I2S.
The AT32UC3A3/A4 includes a powerfull External Bus Interface to interface all standard mem-
ory device like SRAM, SDRAM, NAND Flash or parallel interfaces like LCD Module.
The peripheral set includes a Hig h Speed MCI for SDIO/SD/MMC and a hardware encryption
module based on AES algorithm.
The device embeds a 10-bit ADC and a Digital Audio bistream DAC.
The Direct Memory Access controller (DMACA) allows high bandwidth data flows between high
speed periphera ls (USB, External Memories, MM C, SDIO, ...) and through high speed internal
features (AES, internal memories).
The High-Speed (480MBit/s) USB 2.0 Device and Host interface supports several USB Classes
at the same time thanks to the rich Endp oint configu ratio n. The Embedded Host int erfa ce allows
device like a USB Flash disk or a USB printer to be directly connected to the processor. This
periphal has its own dedicat ed DMA and is perfect for Mass Storage application.
AT32UC3A3/A4 in te gr at es a class 2+ Nexu s 2.0 O n- Ch ip Debug (OCD) Sy ste m , wit h n o n-i nt ru -
sive real-time trace, full-speed read/write memory access in addition to basic runtime control.
4
32072H–AVR32–10/2012
AT32UC3A3
2. Overview
2.1 Block Diagram
Figure 2-1. Block Diagram
AVR32UC
CPU
NEXUS
CLASS 2+
OCD
INSTR
INTERFACE
DATA
INTERFACE
TIMER/COUNTER
0/1
INTERRUPT
CONTROLLER
REAL TIME
COUNTER
PERIPHERAL
DMA
CONTROLLER
256/128/64
KB
FLASH
HSB-PB
BRIDGE B
HSB-PB
BRIDGE A
MEMORY INTERFACE
S
MM M
M
M
S
S
S
S
S
M
EXTERNAL
INTERRUPT
CONTROLLER
HIGH SPEED
BUS MATRIX
FAST GPIO
GENERAL PURPOSE IOs
64 KB
SRAM
GENERAL PURPOSE IOs
PA
PB
PC
PX
A[2..0]
B[2..0]
CLK[2..0]
EXTINT[7..0]
SCAN[7..0]
NMI
GCLK[3..0]
XIN32
XOUT32
XIN0
XOUT0
PA
PB
PC
PX
RESET_N
EXTERNAL BUS INTERFACE
(SDRAM, STATIC MEMORY, COMPACT
FLASH & NAND FLASH)
CAS
RAS
SDA10
SDCK
SDCKE
SDWE
NCS[5..0]
NRD
NWAIT
NWE0
DATA[15..0]
USB HS
INTERFACE
DMA
ID
VBOF
DMFS, DMHS
32 KHz
OSC
115 kHz
RCSYS
OSC0
PLL0
USART3
SERIAL
PERIPHERAL
INTERFACE 0/1
TWO-WIRE
INTERFACE 0/1
DMA
DMADMA
RXD
TXD
CLK
MISO, MOSI
NPCS[3..1]
TWCK
TWD
USART1
DMA
RXD
TXD
CLK
RTS, CTS
DSR, DTR, DCD, RI
USART0
USART2
DMA
RXD
TXD
CLK
RTS, CTS
SYNCHRONOUS
SERIAL
CONTROLLER
DMA
TX_CLOCK, TX_FRAME_SYNC
RX_DATA
TX_DATA
RX_CLOCK, RX_FRAME_SYNC
ANALOG TO
DIGITAL
CONVERTER
DMA
AD[7..0]
WATCHDOG
TIMER
XIN1
XOUT1 OSC1
PLL1
SPCK
JTAG
INTERFACE
MCKO
MDO[5..0]
MSEO[1..0]
EVTI_N
EVTO_N
TCK
TDO
TDI
TMS
POWER
MANAGER
RESET
CONTROLLER
ADDR[23..0]
SLEEP
CONTROLLER
CLOCK
CONTROLLER
CLOCK
GENERATOR
FLASH
CONTROLLER
CONFIGURATION REGISTERS BUS
MEMORY PROTECTION UNIT
PB
PB
HSB
HSB
NWE1
NWE3
PBA
PBB
NPCS0
LOCAL BUS
INTERFACE
AUDIO
BITSTREAM
DAC
DMA
DATA[1..0]
DATAN[1..0]
M
MULTIMEDIA CARD
& MEMORY STICK
INTERFACE
CLK
CMD[1..0]
DATA[15..0]
DMA
S
AES
DMA
CFCE1
CFCE2
CFRW
NANDOE
NANDWE
32KB RAM
32KB RAM
HRAM0/ 1
DPFS, DPHS
USB_VBIAS
USB_VBUS
S
S
VDDIN
VDDCORE
GNDCORE
DMACA
1V8
Regulator
TWALM
5
32072H–AVR32–10/2012
AT32UC3A3
2.2 Configuration Summary
The table below lists all AT32UC3A3/A4 memory and package configurations:
Table 2-1. Configuration Summary
Feature AT32UC3A3256/128/64 AT32UC3A4256/128/64
Flash 256/128/64 KB
SRAM 64 KB
HSB RAM 64 KB
EBI Full Nand flash only
GPIO 110 70
Exter nal Interrupts 8
TWI 2
USART 4
Pe ripheral DMA Channels 8
Generic DMA Channels 4
SPI 2
MCI slots 2 MMC/SD slots 1 MMC/SD slot
+ 1 SD slot
High Speed USB 1
AES (S option) 1
SSC 1
Audio Bitstream DAC 1
Timer/Counter Channels 6
Watchdog Timer 1
Real-Tim e C lock Timer 1
Power Manager 1
Oscillators
PLL 80-240 MHz (PLL0/PLL1)
Crystal Oscillators 0.4-20 MHz (OSC0/OSC1)
Crystal Oscillator 32 KHz (OSC32K)
RC Oscillator 115 kHz (RCSYS)
10-bit ADC
number of channels 1
8
JTAG 1
Max Frequency 84 MHz
Package LQFP144, TFBGA144 VFBGA100
6
32072H–AVR32–10/2012
AT32UC3A3
3. Packa ge and Pinout
3.1 Package The device pins are multiplexed with peripheral functions as described in the Peripheral Multi-
plexing on I/O Line section.
Figure 3-1. TFBGA144 Pinout (top view)
12111098765
4
32
1
A
B
C
D
E
F
G
H
J
K
L
M
PX40 PB00 PA28 PA27 PB03 PA29 PC02 PC04 PC05 DPHS DMHS USB_VBUS
PA09GNDPLLDMFS
USB_VBIAS
VDDIOPC03PB04VDDIOPB02PA31PB11PX10
PX09 PX35 GNDIO
PX37 PX36
PB01 PX16
PX47 PX19
PB08PA30PX13
PA02PB10PX12
PA10PA08
GNDCORE
DPFS
PB06PB07PA11PA26
VDDIN PA12
VDDCORE
PA07PA25
PA06 PA16PA13PA05PA04
PX53 VDDIO PB09PX15
PX49 PX48 GNDIOGNDIO
PX08
VDDIO PX54PX38
PX07 PX06PX39
PX50 PX51 GNDIOGNDIOPX05 PX59PX00
PX57 VDDIO PA17PC01VDDIO PX58PX01
PX56 PX55 PA15PA14PX02 PX34PX04
PX46 PC00 PX52PX17PX44 GNDIOPX03
PX20 VDDIO PX43PX18GNDIO PX45PX11
PX14 PX21 PX24PX23PX41 PX42PX22
PA23 PA01PA00PA03PA24
VDDIO PB05
VDDANA
PA22PA21
PA19 RESET_N
TDOTMSPA20
PA18 TCKPX29GNDIOPX27
VDDIN TDI
GNDANA
PX28PX26
PX25 PX33PX30PX31PX32
7
32072H–AVR32–10/2012
AT32UC3A3
Figure 3-2. LQFP144 Pinout
USB_VBUS1
VDDIO2
USB_VBIAS3
GNDIO4
DMHS5
DPHS6
GNDIO7
DMFS8
DPFS9
VDDIO10
PB0811
PC0512
PC0413
PA3014
PA0215
PB1016
PB0917
PC0218
PC0319
GNDIO20
VDDIO21
PB0422
PA2923
PB0324
PB0225
PA2726
PB0127
PA2828
PA3129
PB0030
PB1131
PX1632
PX1333
PX1234
PX1935
PX4036
PX1037
PX3538
PX4739
PX1540
PX4841
PX5342
PX4943
PX3644
PX3745
PX5446
GNDIO47
VDDIO48
PX0949
PX0850
PX3851
PX3952
PX0653
PX0754
PX0055
PX5956
PX5857
PX0558
PX0159
PX0460
PX3461
PX0262
PX0363
VDDIO64
GNDIO65
PX4466
PX1167
PX1468
PX4269
PX4570
PX4171
PX2272
TDI108
TCK107
RESET_N106
TDO105
TMS104
VDDIO103
GNDIO102
PA15101
PA14100
PC0199
PC0098
PX3197
PX3096
PX3395
PX2994
PX3293
PX2592
PX2891
PX2690
PX2789
PX4388
PX5287
PX2486
PX2385
PX1884
PX1783
GNDIO82
VDDIO81
PX2180
PX5579
PX5678
PX5177
PX5776
PX5075
PX4674
PX2073
PA21 109
PA22 110
PA23 111
PA24 112
PA20 113
PA19 114
PA18 115
PA17 116
GNDANA 117
VDDANA 118
PA25 119
PA26 120
PB05 121
PA00 122
PA01 123
PA05 124
PA03 125
PA04 126
PA06 127
PA16 128
PA13 129
VDDIO 130
GNDIO 131
PA12 132
PA07 133
PB06 134
PB07 135
PA11 136
PA08 137
PA10 138
PA09 139
GNDCORE 140
VDDCORE 141
VDDIN 142
VDDIN 143
GNDPLL 144
8
32072H–AVR32–10/2012
AT32UC3A3
Figure 3-3. VFBGA100 Pinout (top view)
Note: 1. Those balls are physically connected to 2 GPIOs. Software must managed carrefully the GPIO
configuration to avoid electrical conflict
1098765
4
32
1
A
B
C
D
E
F
G
H
J
K
PA28 PA27 PB04 PA30 PC02 PC03 PC05 DPHS DMHS USB_VBUS
GNDPLL
DMFS
DPFSPC04VDDIOVDDIOPA29PB02PB01PB00
PB11 PA31 GNDIO
PX10 PX13
PB03 PB09
PX16/
PX53(1) PB10
GNDIO
USB_VBIAS
PB08
PA09PB06PB07
PA10
PA11
VDDINVDDIN
PA06/
PA13(1) VDDCORE
PA04
PA08 GNDCORE
PA03
PX09 VDDIO PA16GNDIO
PX07 GNDIO PA26/
PB05(1)
VDDIO
PX12
GNDIO PX08
PA02/
PX47(1)
VDDIO PX06
PX19/
PX59(1)
PX00 PX30 PA12/
PA25(1)
PA23/
PX46(1)
PX01 PX02PX05
PX25 PX31 TMS
PA22/
PX20(1)
PX21 GNDIOPX04
PX29 VDDIO PA15/
PX45(1)
VDDANA
PX24 PX26PX03
PX15/
PX32(1)
PC00/
PX14(1)
PA14/
PX11(1)
PC01PX27 PX28PX23
PA00/
PA18(1)
PA01/
PA17(1)
PA05
GNDANA PA07/
PA19(1)
PA20/
PX18(1)
TDO PA24/
PX17(1)
RESET_N
TDI PA21/
PX22(1)
TCK
9
32072H–AVR32–10/2012
AT32UC3A3
3.2 Peripheral Multiplexing on I/O lines
3.2.1 Multiplexed Signals
Each GPIO line can be assigned to one of the peripheral functions. The following table
describes the peripheral signals multiplexed to the GPIO lines.
Note that GPIO 44 is physically implemented in silicon but it must be kept unused and config-
ured in input mode.
Table 3-1. GPIO Controller Function Multiplexing
BGA
144 QFP
144 BGA
100 PIN
G
P
I
O Supply
PIN
Type
(2)
GPIO function
AB CD
G11 122 G8(1) PA00 0 VDDIO x3 USART0 - RTS TC0 - CLK1 SPI1 - NPCS[3]
G12 123 G10(1) PA01 1 VDDIO x1 USART0 - CTS TC0 - A1 USART2 - RTS
D8 15 E1(1) PA02 2 VDDIO x1 USART0 - CLK TC0 - B1 SPI0 - NPCS[0]
G10 125 F9 PA03 3 VDDIO x1 USART0 - RXD EIC - EXTINT[4] ABDAC - DATA[0]
F9 126 E9 PA04 4 VDDIO x1 USART0 - TXD EIC - EXTINT[5] ABDAC - DATAN[0]
F10 124 G9 PA05 5 VDDIO x1 USART1 - RXD TC1 - CLK0 USB - ID
F8 127 E8(1) PA06 6 VDDIO x1 USART1 - TXD TC1 - CLK1 USB - VBOF
E10 133 H10(1) PA07 7 VDDIO x1 SPI0 - NPCS[3] ABDAC - DATAN[0] USART1 - CLK
C11 137 F8 PA08 8 VDDIO x3 SPI0 - SPCK ABDAC - DATA[0] TC1 - B1
B12 139 D8 PA09 9 VDDIO x2 SPI0 - NPCS[0] EIC - EXTINT[6] TC1 - A1
C12 138 C10 PA10 10 VDDIO x2 SPI0 - MOSI USB - VBOF TC1 - B0
D10 136 C9 PA11 11 VD DIO x2 SPI0 - MISO USB - ID TC1 - A2
E12 132 G7(1) PA12 12 VDDIO x1 USART1 - CTS SPI0 - NPCS[2] TC1 - A0
F11 129 E8(1) PA13 13 VDDIO x1 USART1 - RTS SPI0 - NPCS[1] EIC - EXTINT[7]
J6 100 K7(1) PA14 14 VDDIO x1 SPI0 - NPCS[1] TWIMS0 - TWALM TWIMS1 - TWCK
J7 101 J7(1) PA15 15 VDDIO x1 MCI - CMD[1] SPI1 - SPCK TWIMS1 - TWD
F12 128 E7 PA16 16 VDDIO x1 MCI - DATA[11] SPI1 - MOSI TC1 - CLK2
H7 116 G10(1) PA17 17 VDDANA x1 MCI - DATA[10] SPI1 - NPCS[1] ADC - AD[7]
K8 115 G8(1) PA18 18 VDDANA x1 MCI - DATA[9] SPI1 - NPCS[2] ADC - AD[6]
J8 114 H10(1) PA19 19 VDDANA x1 MCI - D ATA[8] SPI1 - MISO ADC - AD[5]
J9 113 H9(1) PA20 20 VDDANA x1 EIC - NMI SSC - RX_FRAME_SYNC ADC - AD[4]
H9 109 K10(1) PA21 21 VDDANA x1 ADC - AD[0] EIC - EXTINT[0] USB - ID
H10 110 H6(1) PA22 22 VDDANA x1 ADC - AD[1] EIC - EXTINT[1] USB - VBOF
G8 111 G6(1) PA23 23 VDDANA x1 ADC - AD[2] EIC - EXTINT[2] ABD AC - DATA[1]
G9 112 J10(1) PA24 24 VDD ANA x1 ADC - AD[3] EIC - EXTINT[3] ABDA C - DATAN[1]
E9 119 G7(1) PA25 25 VDDIO x1 TWIMS0 - TWD TWIMS1 - TWALM USART1 - DCD
D9 120 F7(1)) PA26 26 VDDIO x1 TWIMS0 - TWCK USART2 - CTS USART1 - DSR
A4 26 A2 PA27 27 VDDIO x2 MCI - CLK SSC - RX_DATA USART3 - R T S MSI - SCLK
A3 28 A1 PA28 28 VDDIO x1 MCI - CMD[0] SSC - RX_CLOCK USART3 - CTS MSI - BS
A6 23 B4 PA29 29 VDDIO x1 MCI - DATA[0] USART3 - TXD TC0 - CLK0 MSI - DATA[0]
10
32072H–AVR32–10/2012
AT32UC3A3
C7 14 A4 PA30 30 VDDIO x1 MCI - DATA[1] USART3 - CLK DMACA - DMAACK[0] MSI - DATA[1]
B3 29 C2 PA31 31 VDDIO x1 MCI - DATA[2] USART2 - RXD DMACA - DMARQ[0] MSI - DATA[2]
A2 30 B1 PB00 32 VDDIO x1 MCI - DATA[3] USART2 - TXD ADC - TRIGGER MSI - DATA[3]
C4 27 B2 PB01 33 VDDIO x1 MCI - DATA[4] ABDAC - DATA[1] EIC - SCAN[0] MSI - INS
B4 25 B3 PB02 34 VDDIO x1 MCI - DATA[5] ABDAC - DATAN[1] EIC - SCAN[1]
A5 24 C4 PB03 35 VDDIO x1 MCI - DATA[6] USART2 - CLK EIC - SCAN[2]
B6 22 A3 PB04 36 VDDIO x1 MCI - DATA[7] USART3 - RXD EIC - SCAN[3]
H12 121 F7(1) PB05 37 VDDIO x3 USB - ID TC0 - A0 EIC - SCAN[4]
D12 134 D7 PB06 38 VDDIO x1 USB - VBOF TC0 - B0 EIC - SCAN[5]
D11 135 D6 PB07 39 VDDIO x3 SPI1 - SPCK SSC - TX_CLOCK EIC - SCAN[6]
C8 11 C6 PB08 40 VDDIO x2 SPI1 - MISO SSC - TX_DATA EIC - SCAN[ 7]
E7 17 C5 PB09 41 VDDIO x2 SPI1 - NPCS[0] SSC - RX_DATA EBI - NCS[4]
D7 16 D5 PB10 42 VDDIO x2 SPI1 - MOSI SSC - RX_FRAME_SYNC EBI - NCS[5]
B2 31 C1 PB11 43 VDDIO x1 USART1 - RXD SSC - TX_FRAME_SYNC PM - GCLK[1]
K5 98 K5(1) PC00 45 VDDIO x1
H6 99 K6 PC01 46 VDDIO x1
A7 18 A5 PC02 47 VDDIO x1
B7 19 A6 PC03 48 VDDIO x1
A8 13 B7 PC04 49 VDDIO x1
A9 12 A7 PC05 50 VDDIO x1
G1 55 G4 PX00 51 VDDIO x2 EBI - DATA[10] USART0 - RXD USART1 - RI
H1 59 G2 PX01 52 VDDIO x2 EBI - DATA[9] USART0 - TXD USART1 - DTR
J2 62 G3 PX02 53 VDDIO x2 EBI - DATA[8] USART0 - CTS PM - GCLK[0]
K1 63 J1 PX03 54 VDDIO x2 EBI - DATA[7] USART0 - RTS
J1 60 H1 PX04 55 VDDIO x2 EBI - DATA[6] USART1 - RXD
G2 58 G1 PX05 56 VDDIO x2 EBI - DATA[5] USART1 - TXD
F3 53 F3 PX06 57 VDDIO x2 EBI - DATA[4] USART1 - CTS
F2 54 F4 PX07 58 VDDIO x2 EBI - DATA[3] USART1 - RTS
D1 50 E3 PX08 59 VDDIO x2 EBI - DATA[2] USART3 - RXD
C1 49 E4 PX09 60 VDDIO x2 EBI - DATA[1] USART3 - TXD
B1 37 D2 PX10 61 VDDIO x2 EBI - DATA[0] USART2 - RXD
L1 67 K7(1) PX11 62 VDDIO x2 EBI - NWE1 USART2 - TXD
D6 34 D1 PX12 63 VDDIO x2 EBI - NWE0 USART2 - CTS MCI - CLK
C6 33 D3 PX13 64 VDDIO x2 EBI - NRD USART2 - RTS MCI - CLK
M4 68 K5(1) PX14 65 VDDIO x2 EBI - NCS[1] TC0 - A0
E6 40 K4(1) PX15 66 VDDIO x2 EBI - ADDR[19] USART3 - RTS TC0 - B0
C5 32 D4(1) PX16 67 VDDIO x2 EBI - ADDR[18] USART3 - CTS TC0 - A1
K6 83 J10(1) PX17 68 VDDIO x2 EBI - ADDR[17] DMACA - DMARQ[1] TC0 - B1
Table 3-1. GPIO Controller Function Multiplexing
BGA
144 QFP
144 BGA
100 PIN
G
P
I
O Supply
PIN
Type
(2)
GPIO function
AB CD
11
32072H–AVR32–10/2012
AT32UC3A3
L6 84 H9(1) PX18 69 VDDIO x2 EBI - ADDR[16] DMACA - DMAACK[1] TC0 - A2
D5 35 F1(1) PX19 70 VDDIO x2 EBI - ADDR[15] EIC - SCAN[0] TC0 - B2
L4 73 H6(1) PX20 71 VDDIO x2 EBI - ADDR[14] EIC - SCAN[1] TC0 - CLK0
M5 80 H2 PX21 72 VDDIO x2 EBI - ADDR[13] EIC - SCAN[2] TC0 - CLK1
M1 72 K10(1) PX22 73 VDDIO x2 EBI - ADDR[12] EIC - SCAN[3] TC0 - CLK2
M6 85 K1 PX23 74 VDDIO x2 EBI - ADDR[11] EIC - SCAN[4] SSC - TX_CLOCK
M7 86 J2 PX24 75 VDDIO x2 EBI - ADDR[10] EIC - SCAN[5] SSC - TX_DATA
M8 92 H4 PX25 76 VDDIO x2 EBI - ADDR[9] EIC - SCAN[6] SSC - RX_DATA
L9 90 J3 PX26 77 VDDIO x2 EBI - ADDR[8] EIC - SCAN[7] SSC - RX_FRAME_SYNC
K9 89 K2 PX27 78 VDDIO x2 EBI - ADDR[7] SPI0 - MISO SSC - TX_FRAME_SYNC
L10 91 K3 PX28 79 VDDIO x2 EBI - ADDR[6] SPI0 - MOSI SSC - RX_CLOCK
K11 94 J4 PX29 80 VDDIO x2 EBI - ADDR[5] SPI0 - SPCK
M11 96 G5 PX30 81 VDDIO x2 EBI - ADDR[4] SPI0 - NPCS[0]
M10 97 H5 PX31 82 VDDIO x2 EBI - ADDR[3] SPI0 - NPCS[1]
M9 93 K4(1) PX32 83 VDDIO x2 EBI - ADDR[2] SPI0 - NPCS[2]
M12 95 PX33 84 VDDIO x2 EBI - ADDR[1] SPI0 - NPCS[3]
J3 61 PX34 85 VDDIO x2 EBI - ADDR[0] SPI1 - MISO PM - GCLK[0]
C2 38 PX35 86 VDDIO x2 EBI - DATA[15] SPI1 - MOSI PM - GCLK[1]
D3 44 PX36 87 VDDIO x2 EBI - DATA[14] SPI1 - SPCK PM - GCLK[2]
D2 45 PX37 88 VDDIO x2 EBI - DATA[13] SPI1 - NPCS[0] PM - GCLK[3]
E1 51 PX38 89 VDDIO x2 EBI - DATA[12] SPI1 - NPCS[1] USART1 - DCD
F1 52 PX39 90 VDDIO x2 EBI - DATA[11] SPI1 - NPCS[2] USART1 - DSR
A1 36 PX40 91 VDDIO x2 MCI - CLK
M2 71 PX41 92 VDDIO x2 EBI - CAS
M3 69 PX42 93 VDDIO x2 EBI - RAS
L7 88 PX43 94 VDDIO x2 EBI - SDA10 USART1 - RI
K2 66 PX44 95 VDDIO x2 EBI - SDWE USART1 - DTR
L3 70 J7(1) PX45 96 VDDIO x3 EBI - SDCK
K4 74 G6(1) PX46 97 VDDIO x2 EBI - SDCKE
D4 39 E1(1) PX47 98 VDDIO x2 EBI - NANDOE ADC - TRIGGER MCI - DATA[11]
F5 41 PX48 99 VDDIO x2 EBI - ADDR[23] USB - VBOF MCI - DATA[10]
F4 43 PX49 100 VDDIO x2 EBI - CFRNW USB - ID MCI - DATA[9]
G4 75 PX50 101 VDDIO x2 EBI - CFCE2 TC1 - B2 MCI - DATA[8]
G5 77 PX51 102 VDDIO x2 EBI - CFCE1 DMACA - DMAACK[0] MCI - DATA[15]
K7 87 PX52 103 VDDIO x2 EBI - NCS[3] DMACA - DMARQ[0] MCI - DATA[14]
E4 42 D4(1) PX53 104 VDDIO x2 EBI - NCS[2] MCI - DATA[13]
E3 46 PX54 105 VDDIO x2 EBI - NWAIT USART3 - TXD MCI - D ATA[12]
J5 79 PX55 106 VDDIO x2 EBI - ADDR[22] EIC - SCAN[3] USART2 - RXD
Table 3-1. GPIO Controller Function Multiplexing
BGA
144 QFP
144 BGA
100 PIN
G
P
I
O Supply
PIN
Type
(2)
GPIO function
AB CD
12
32072H–AVR32–10/2012
AT32UC3A3
Note: 1. Those balls are physically connected to 2 GPIOs. Software must managed carrefully the GPIO
configuration to avoid electrical conflict.
2. Refer to ”Electrical Characteristics” on page 960 for a description of the electrical properties of
the pad types used..
3.2.2 Periph eral Functions
Each GPIO line can be assigned to one of several peripheral functions. The following table
describes how the various peripheral functions are selected. The last listed function has priority
in case multiple functions ar e enabled on the same pin.
3.2.3 Oscillator Pin o ut
The oscillators are not mapped to the normal GPIO functions and their muxings are controlled
by registers in the Power Mananger (PM). Please refer to the PM chapter for more information
about this.
Note: 1. This ball is physically connected to 2 GPIOs. Software must managed carrefully the GPIO con-
figuration to avoid electr ical conflict
J4 78 PX56 107 VDDIO x2 EBI - ADDR[21] EIC - SCAN[2] USART2 - TXD
H4 76 PX57 108 VDDIO x2 EBI - ADDR[20] EIC - SCAN[1] USART3 - RXD
H3 57 PX58 109 VDDIO x2 EBI - NCS[0] EIC - SCAN[0] USART3 - TXD
G3 56 F1(1) PX59 110 VDDIO x2 EBI - NANDWE MCI - CMD[1]
Table 3-1. GPIO Controller Function Multiplexing
BGA
144 QFP
144 BGA
100 PIN
G
P
I
O Supply
PIN
Type
(2)
GPIO function
AB CD
Table 3-2. Peripheral Functions
Function Description
GPIO Controller Function multiplexing GPIO and GPIO peripheral selection A to D
Nexus OCD AUX port connections OCD trace system
JTAG port connections JTAG debug por t
Oscillators OSC0, OSC1, OSC32
Table 3-3.Oscillator Pinout
TFBGA144 QFP144 VFBGA10 0 Pin name Oscillator pin
A7 18 A5 PC02 XIN0
B7 19 A6 PC03 XOUT0
A8 13 B7 PC04 XIN1
A9 12 A7 PC05 XOUT1
K5 98 K5(1) PC00 XIN32
H6 99 K6 PC01 XOUT32
13
32072H–AVR32–10/2012
AT32UC3A3
3.2.4 JTAG port connections
3.2.5 Nexus OCD AUX port connections
If the OCD trace system is enabled, the trace system will take control over a number of pins, irre-
spective of the GPIO configuration. Three differents OCD trace pin mappings are possible,
depending on the configuration of the OCD AXS register. For details, see the AVR32 UC Tech-
nical Reference Manual.
Table 3-4. JTAG Pinout
TFBGA144 QFP144 VFBGA100 Pin name JTAG pin
K12 107 K9 TCK TCK
L12 108 K8 TDI TDI
J11 105 J8 TDO TDO
J10 104 H7 TMS TMS
Table 3-5. Nexus OCD AUX port connections
Pin AXS=0 AXS=1 AXS=2
EVTI_N PB05 PA08 PX00
MDO[5] PA00 PX56 PX06
MDO[4] PA01 PX57 PX05
MDO[3] PA03 PX58 PX04
MDO[2] PA16 PA24 PX03
MDO[1] PA13 PA23 PX02
MDO[0] PA12 PA22 PX01
MSEO[1] PA10 PA07 PX08
MSEO[0] PA11 PX55 PX07
MCKO PB07 PX00 PB09
EVTO_N PB06 PB06 PB06
14
32072H–AVR32–10/2012
AT32UC3A3
3.3 Signal Descriptions
The following table gives details on signal name classified by peripheral.
Table 3-6. Signal Description List
Signal Name Function Type Active
Level Comments
Power
VDDIO I/O Power Supply Power 3.0 to 3.6V
VDDANA Analog Power Supply Power 3.0 to 3.6V
VDDIN Voltage Reg ulator Input Supply Power 3.0 to 3.6V
VDDCORE Vol tage Regulator Output for Digital Supply Power
Output 1.65 to 1.95 V
GNDANA Analog Ground Ground
GNDIO I/O Ground Ground
GNDCORE Digital Ground Ground
GNDPLL PLL Gro u nd Ground
Clocks, Oscillators, and PLL’s
XIN0, XIN1, XIN32 Crystal 0, 1, 32 Input Analog
XOUT0, XOUT1,
XOUT32 Crystal 0, 1, 32 Outp ut Analog
JTAG
TCK Test Clock Input
TDI Test Data In Input
TDO Test Data Out Output
TMS Test Mode Select Input
Auxiliary Port - AUX
MCKO Tr ace Dat a Output Clock Output
MDO[5:0] Trace Data Output Output
MSEO[1:0] Trace Frame Control Output
EVTI_N Event In Input Low
EVTO_N Event Out Output Low
Power Manager - PM
GCLK[3:0] Generic Clock Pins Output
15
32072H–AVR32–10/2012
AT32UC3A3
RESET_N Reset Pin Input Low
DMA Controller - DMACA (optional)
DMAACK[1:0] DMA Acknowledge Output
DMARQ[1:0] DMA Requests Input
External Interrupt Controller - EIC
EXTINT[7:0] External Interrupt Pins Input
SCAN[7:0] Keypad Scan Pins Output
NMI Non-Maskable Interrupt Pin Input Low
General Purpose Input/Output pin - GPIOA, GPIOB, GPIOC, GPIOX
PA[31:0] Parallel I/O Controller GPIO port A I/O
PB[11:0] Parallel I/O Controller GPIO port B I/O
PC[5:0] Parallel I/O Controller GPIO port C I/O
PX[59:0] Parallel I/O Controller GPIO port X I/O
External Bus Interface - EBI
ADDR[23:0] Address Bus Output
CAS Column Signal Output Low
CFCE1 Compact Flash 1 Chip Enable Output Low
CFCE2 Compact Flash 2 Chip Enable Output Low
CFRNW Compact Flash Read Not Write Output
DATA[15:0] Data Bus I/O
NANDOE NAND Flash Output Enable Output Low
NANDWE NAND Flash Write Enable Output Low
NCS[5:0] Ch i p Select Output Low
NRD Read Signal Output Low
NWAIT External Wait Signal Input Low
NWE0 Write En able 0 Output Low
NWE1 Write En able 1 Output Low
RAS Row Signal Output Low
Table 3-6. Signal Description List
Signal Name Function Type Active
Level Comments
16
32072H–AVR32–10/2012
AT32UC3A3
SDA10 SDRAM Address 10 Line Output
SDCK SDRAM Clock Output
SDCKE SDRAM Clock Enable Output
SDWE SDRAM Write Enable Output Low
MultiMedia Card Interface - MCI
CLK Multimedia Card Clock Output
CMD[1:0] Multimedia Card Command I/O
DATA[15:0] Multimedia Card Data I/O
Memory Stick Interface - MSI
SCLK Memory Stick Clock Output
BS Memory Stick Command I/O
DATA[3:0] Multimedia Card Data I/O
Serial Peripheral Interface - SPI0, SPI1
MISO Master In Slave Out I/O
MOSI Master Out Slave In I/O
NPCS[3:0] SPI Peripheral Chip Select I/O Low
SPCK Clock Output
Synchronous Serial Controll er - SSC
RX_CLOCK SSC Receive Clock I/O
RX_DATA SSC Receive Data Input
RX_FRAME_SYNC SSC Receive Frame Sync I/O
TX_CLOCK SSC Transmit Clock I/O
TX_DATA SSC Transmit Data Output
TX_FRAME_SYNC SSC Transmit Frame Sync I/O
Timer/Counter - TC0, TC1
A0 Channel 0 Line A I/O
A1 Channel 1 Line A I/O
A2 Channel 2 Line A I/O
Table 3-6. Signal Description List
Signal Name Function Type Active
Level Comments
17
32072H–AVR32–10/2012
AT32UC3A3
B0 Channel 0 Line B I/O
B1 Channel 1 Line B I/O
B2 Channel 2 Line B I/O
CLK0 Channel 0 External Clock Input Input
CLK1 Channel 1 External Clock Input Input
CLK2 Channel 2 External Clock Input Input
Two-wire Interface - TWI0, TWI1
TWCK Serial Clock I/O
TWD Serial Data I/O
TWALM SMBALERT signal I/O
Universal Synchronous Asynchronous Receiver Transmitter - USART0, USART1, USART2, USART3
CLK Clock I/O
CTS Clear To Send Input
DCD Data Carrier Detect Only USART1
DSR Data Set Ready Only USART1
DTR Data Terminal Ready Only USART1
RI Ring Indicator Only USART1
RTS Request To Send Output
RXD Receive Data Input
TXD Transmit Data Output
Analog to Digital Converter - ADC
AD0 - AD7 Ana log input pins Analog
input
Audio Bitstream DAC (A BDAC)
DATA0-DATA1 D/A Data out Output
DATAN0-DATAN1 D/A Data inverted out Output
Universal Serial Bus Device - USB
DMFS USB Full Speed Data - Analog
DPFS USB Full Speed Data + Analog
Table 3-6. Signal Description List
Signal Name Function Type Active
Level Comments
18
32072H–AVR32–10/2012
AT32UC3A3
DMHS USB High Speed Data - Analog
DPHS USB High Speed Data + Analog
USB_VBIAS USB VBIAS reference Analog
Connect to the ground through a
6810 ohms (+/- 1%) resistor in
parallel with a 10pf capacitor.
If USB hi-speed feature is not
required, leav e this pin
unconnected to save power
USB_VBUS USB VBUS signal Output
VBOF USB VBUS on/off bus power contro l po rt Output
ID ID Pin fo the USB bus In put
Table 3-6. Signal Description List
Signal Name Function Type Active
Level Comments
19
32072H–AVR32–10/2012
AT32UC3A3
3.4 I/O Line Considerations
3.4.1 JTAG Pins TMS and TDI pins have pull-up resistors. TDO pin is an output, driven at up to VDDIO, and has
no pull-up resistor.
3.4.2 RESET_N Pin The RESET_N pin is a schm itt input and integrates a permanent pull-up resistor to VDDIO. As
the product integrates a power-on reset cell, the RESET_N pin can be left unconnected in case
no reset from the system needs to be applied to the product.
3.4.3 T WI Pins When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and
inputs with inputs with spike filtering. When used as GPI O pi ns or used f or ot her p er iphe ra ls, the
pins have the same ch ar ac te rist ics as ot he r GPIO pins.
3.4.4 GPIO Pins All the I/O lines int egrate a pro grammable pul l-up resist or. Programming of this pull-up resistor is
performed in dependently f or each I/ O line thr ough th e I/O Contro ller. Aft er reset, I/O lines default
as inputs with pull-up resistors disabled, except when indicated otherwise in the column “Reset
State” of the I/O Controller multiplexing tables.
20
32072H–AVR32–10/2012
AT32UC3A3
3.5 Power Considerations
3.5.1 Power Supplies
The AT32UC3A3 has seve ral types of power supply pins:
•VDDIO: Powers I/O lines. Voltage is 3.3V nominal
•VDDANA: P owers the ADC. Voltage is 3.3V nominal
•VDDIN: Input voltage for the voltage regulator. Voltage is 3.3V no minal
•VDDCORE: Output voltage from regulator for filtering purpose and provides the supply to the
core, memories, and peripherals. Voltage is 1.8V nominal
The ground pin GNDCORE is common to VDDCORE and VDDIN. The ground pin for VDDANA
is GNDANA. The ground pins f or VDDIO are GNDIO.
Refer to Electrical Char ac te rist ics cha p te r for power consumption on the various supply pins.
3.5.2 Voltage Regulator
The AT32UC3A3 embeds a voltage regulator that converts from 3.3V to 1.8V with a load of up
to 100mA. The regulat or tak es its inpu t vo lta ge fro m VDDIN, and supplies the outp ut voltage on
VDDCORE and powers the core, memories and peripherals.
Adequate output supply decoupling is mandatory for VDDCORE to reduce ripple and avoid
oscillations.
The best way to achieve this is to use two capacitors in parallel between VDDCORE and
GNDCORE:
• One external 470pF (or 1nF) NPO capacitor (COUT1) should be connected as close to the
chip as possible .
• One external 2.2µF (or 3.3µF) X7R capacitor (COUT2).
Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability
and reduce source volt age drop.
The input decoup ling capacitor shou ld be placed close to th e chip, e.g., two capacito rs can be
used in parallel (1nF NPO and 4.7µF X7R).
For decoupling recommendations for VDDIO and VDDANA please refer to the Schematic
checklist.
3.3V
1.8V
VDDIN
VDDCORE
1.8V
Regulator
CIN1
COUT1
COUT2
CIN2
21
32072H–AVR32–10/2012
AT32UC3A3
4. Processor and Architecture
Rev: 1.4.2.0
This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the
AVR32 architecture. A summary of the programming model, instruction set, and MPU is pre-
sented. For further details, see the AVR32 Architecture Manual and the AVR32UC Technical
Reference Manual.
4.1 Features •32-bit load/store AVR32A RISC architecture
– 15 general-purpose 32-bit registers
– 32-bit Stac k Pointer, Program Counter and Link Register reside in register file
– Fully orthogonal instruction set
– Privileged and unprivileged modes enabling efficient and secure Operating Systems
– Innov ative instruction set together with va riable instruction length ensuring industry leading
code density
– DSP extention with saturating arithmetic, and a wide variety of multipl y instru ctio ns
•3-stage pipeline allows one instruction per cloc k c ycle for most instructions
– Byte, halfword, word and double word memory access
– Multiple interrupt priority levels
•MPU allows for operating systems with memory protection
4.2 AVR32 Architecture
AVR32 is a high-performance 32-bit RISC microprocessor architect ure, designed for cost-sensi-
tive embedded applications, with particular emphasis on low power consumption and high code
density. In addition, the instruction set architecture has been tuned to allow a variety of micro-
architectures, enabling the AVR32 to be implemented as low-, mid-, or high-performance
processors. AVR32 extends the AVR family into the world of 32- and 64-bit applicat ions.
Through a quantitative approach, a large set of industry recognized benchmarks has been com-
piled and analyzed to achieve the best code density in its class. In addition to lowering the
memory requirem ents, a compact cod e size also contr ibutes to the core’s low power charact eris-
tics. The processor supports byte and halfword data types without penalty in code size and
performance.
Memory load and store operations are provided for byte, halfword, word, and double word data
with automatic sign- or zero extension of halfword and byte data. The C-compiler is closely
linked to the architecture and is able to exploit code optimization features, both for size and
speed.
In order to reduce code size to a minimum, some instructions have multiple addressing modes.
As an example, instructions with immediates often have a compact format with a smaller imme-
diate, and an ext ended format with a larger imm ediate. In this way, the comp iler is able to use
the format giving the smallest code size.
Another feature of the instruction set is that frequently used instructions, like add, have a com-
pact format with two operands as well as an extended format with three operands. The larger
format increases perfor mance, allowing an a ddition and a data move in the sa me instr uction in a
single cycle. Load and store instructions have several different formats in order to reduce code
size and speed up execution.
22
32072H–AVR32–10/2012
AT32UC3A3
The register file is organized as sixteen 32-bit registers and inclu des the Program Counter, the
Link Register, and the Stack Pointer. In addition, register R12 is designed to hold return values
from function calls and is used implicitly by some instructions.
4.3 The AVR32UC CPU
The AVR32UC CPU targets low- and medium-performance applications, and provides an
advanced OCD system, no caches, and a Memory Protection Unit (MPU). Java acceleration
hardware is not implemented.
AVR32UC provides three memory interfaces, one High Speed Bus master for instruction fetch,
one High Speed Bus master for data access, and one High Speed Bus slave interface allowing
other bus masters to access data RAMs internal to the CPU. Keeping data RAMs internal to the
CPU allows fast access to the RAMs, reduces latency, and guarantees deterministic timing.
Also, power consumption is re duced by not needing a full High Speed Bus access for memory
accesses. A dedicated data RAM interface is provided for communicating with the internal data
RAMs.
A local bus interface is provided for connecting the CPU to device-specific high-speed systems,
such as floating-point units and fast GPIO ports. This local bus has to be enabled by writing the
LOCEN bit in the CPUCR system regist er. The local bus is able to transfer data between the
CPU and the local bus slave in a single clock cycle. The local bus has a dedicated memory
range allocated to it, and data transfers are performed using regular load and store instructions.
Details on which devices that are mapped into the local bus space is given in the Memories
chapter of this data sheet.
Figure 4-1 on page 23 displays the contents of AVR32UC.
23
32072H–AVR32–10/2012
AT32UC3A3
Figure 4-1. Overview of the AVR32UC CPU
4.3.1 Pipeline Overview
AVR32UC has three pipeline stages, Instru ction Fetch (I F), Instr uction Decode (ID), and Instruc-
tion Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic
(ALU) section, one multiply (MUL) section, and one load/store (LS) sect ion.
Instructions are issued and complete in order. Certain operations require several clock cycles to
complete, and in this case, the instruction resides in the ID and EX stages for the required num-
ber of clock cycles. Since there is only three pipeline stages, no internal data forwarding is
required, and no dat a dependencies can arise in the pipeline.
Figure 4-2 on page 24 shows an overview of the AVR32UC pipeline stages.
AVR32UC CPU pipeline
Instruction memory controller
High
Speed
Bus
master
MPU
High Speed Bus
High Speed Bus
OCD
system
OCD i nterface
Interrupt controller interface
High
Speed
Bus slave
High Speed Bus
Data RAM interface
High Speed Bus master
Power/
Reset
control
Reset interface
CPU Local
Bus
master
CPU Local Bus
Data memory controller
24
32072H–AVR32–10/2012
AT32UC3A3
Figure 4-2. The AVR32UC Pipeline
4.3.2 AVR32A Microarchitecture Compliance
AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is tar-
geted at cost-sensitive, lower-end applications like smaller microcontrollers. This
microarchitecture does not provide dedicated hardware registers for shadowing of register file
registers in interrupt contexts. Additionally, it does not provide hardware registers for the return
address registers a nd return status re gisters. Instead, all th is information is sto red on the system
stack. This saves chip area at the expense of slower interrupt handling.
Upon interrupt initiation, registers R8-R12 are automatically pushed to the system stack. These
registers are pushed regardless of the priority level of the pending interrupt. The return address
and status register are also automatically pushed to stack. The interrupt handler can therefore
use R8-R12 freely. Upon interrupt completion, the old R8-R12 re gisters and status register are
restored, and execution continues at the return address stored popped from stack.
The stack is also used to stor e the status register and ret urn address for exceptions and scall.
Executing the rete or rets instruction at the completion of an exception or system call will pop
this status register an d continue execution at the popped return address.
4.3.3 Java Supp ort AVR32UC does not provide Java hardware accelerat ion.
4.3.4 Memory Protection
The MPU allows the user to check all memory a ccesses for privilege violations. If an access is
attempted to an illegal memory address, the access is aborted and an exception is taken. The
MPU in AVR32UC is specified in the AVR32UC Technical Reference manual.
4.3.5 Unaligned Reference Handling
AVR32UC does not support unali gne d accesses, e xcept fo r do ublewor d accesses. AVR32 UC is
able to perform word-aligned st.d and ld.d. Any other unaligned memory access will cause an
address exception. Doubleword-sized accesses with word-aligned pointers will automatically be
performed as two word-sized accesses.
IF ID ALU
MUL
Regfile
write
Prefetch unit Decode unit
ALU unit
Multiply unit
Load-store
unit
LS
Regfile
Read
25
32072H–AVR32–10/2012
AT32UC3A3
The following table shows the instructions with support for unaligned addresses. All other
instructions require aligned addresses.
4.3.6 Unimplemented Instructions
The following instructions are unimplemented in AVR32UC, and will cause an Unimplemented
Instruction Exception if executed:
• All SIMD instructions
• All coprocessor instructions if no coprocessors are present
• retj, incjosp, popjc, pushjc
• tlbr, tlbs, tlbw
• cache
4.3.7 CPU and Arch itecture Revisi on
Three major revisions of the AVR32UC CPU currently exist.
The Architecture Revision field in the CONFIG0 system register identifies which architecture
revision is implemented in a specific device.
AVR32UC CPU revision 3 is fully backward-compatible with revisions 1 and 2, ie. co de compiled
for revision 1 or 2 is binary-compatible with r evision 3 CPUs.
Table 4-1. Instructions with Unaligned Reference Support
Instruction Suppor ted alignment
ld.d Word
st.d Word
26
32072H–AVR32–10/2012
AT32UC3A3
4.4 Programming Model
4.4.1 Register File Configuration
The AVR32UC register file is shown below.
Figure 4-3. The AVR32UC Register File
4.4.2 Status Register Configuration
The Status Register (SR) is split into two halfwor ds, one uppe r and one lower, se e Figu re 4-4 on
page 26 and Figure 4-5 on page 27. The lower word contains the C, Z, N, V, and Q condition
code flags and th e R, T, and L bits, while the upper ha lfword contains information ab out the
mode and state the processor executes in. Refer to the AVR32 Architecture Manual for details.
Figure 4-4. The Status Register High Halfword
Application
Bit 0
Supervisor
Bit 31
PC
SR
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R3
R1
R2
R0
Bit 0Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
INT0
SP_APP SP_SYS
R12
R11
R9
R10
R8
Exception NMIINT1 INT2 INT3
LRLR
Bit 0Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
SP_SYS
LR
Bit 0Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
SP_SYS
LR
Bit 0Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
SP_SYS
LR
Bit 0Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
SP_SYS
LR
Bit 0Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
SP_SYS
LR
Bit 0Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
SP_SYS
LR
Secure
Bit 0Bit 31
PC
SR
R12
INT0PC
FINTPC
INT1PC
SMPC
R7
R5
R6
R4
R11
R9
R10
R8
R3
R1
R2
R0
SP_SEC
LR
SS_STATUS
SS_ADRF
SS_ADRR
SS_ADR0
SS_ADR1
SS_SP_SYS
SS_SP_APP
SS_RAR
SS_RSR
27
32072H–AVR32–10/2012
AT32UC3A3
Figure 4-5. The Status Register Low Halfword
4.4.3 Processor States
4.4.3.1 Normal RISC State
The AVR32 processor supports several different execution contexts as shown in Table 4-2 on
page 27.
Mode changes can be made under software control, or can be caused by external interrupts or
exception processing. A mode can be interrupted by a hig her priority mode, but never by one
with lower priority. Nested exceptions can be supported with a minimal software overhead.
When running an operating system on the AVR32, user processes will typically execute in the
application mode. The programs execute d in this mode are restricted from executin g certain
instructions. Furthermore, most system registers together with the upper halfword of the status
register cannot be accesse d. Protect ed memo ry are as are also no t a vailab le. All other o perat ing
modes are privileged and ar e collectively called System Mod es. They have full acce ss to all priv-
ileged and unprivileged resources. After a reset, the processor will be in supervisor mode.
4.4.3.2 Debug State The AVR32 can be set in a debug state, which allows implementation of software monitor rou-
tines that can read ou t and al ter system in formation for use during ap plication develop ment. This
implies that all system and application regist ers, including the status registers and program
counters, are accessible in debug state. The privileged instruction s ar e als o availa ble .
Bit 15 Bit 0
Reserved
Carry
Zero
Sign
0 0 0 00000000000
- - --T- Bit name
Initial value
0 0
L Q V N Z C-
Overflow
Saturation
- - -
Lock
Reserved
Scratch
Table 4-2. Overview of Execution Modes, their Prior ities and Privilege Levels.
Priority Mode Security Description
1 Non Maskable Interrupt Privileged Non Maskable high priority interrupt mode
2 Exception Privileged Ex ecute exceptions
3 Interrupt 3 Privileged General purpose interrupt mode
4 Interrupt 2 Privileged General purpose interrupt mode
5 Interrupt 1 Privileged General purpose interrupt mode
6 Interrupt 0 Privileged General purpose interrupt mode
N/A Supervisor Privileged Runs supervisor calls
N/A Application Unprivileged Normal program exe c ution mode
28
32072H–AVR32–10/2012
AT32UC3A3
All interrupt levels are by default disabled when debug state is entered, but they can individually
be switched on by the monitor routine by clearing the respective mask bit in the status reg ister.
Debug state can be entered as described in the AVR32UC Technical Reference Manual.
Debug state is exited by the retd instruction.
4.4.4 System Registers
The system registers are placed outside of the virtual memory space, and are only accessible
using the privileged mfsr and mtsr instructions. The table below lists the system registers speci-
fied in the AVR32 architecture, some of which are unused in AVR32UC. The programmer is
responsible for maintaining correct sequencing of any instructions following a mtsr instruction.
For detail on the system registers, refer to the AVR32UC Technical Reference Manual.
Table 4-3. System Registers
Reg # Address Name Function
0 0 SR Status Register
1 4 EVBA Exception Vector Base Address
2 8 ACBA Application Call Base Address
3 12 CPUCR CPU Control Register
4 16 ECR Exception Cause Register
5 20 RSR_SUP Unused in AVR32UC
6 24 RSR_INT0 Unused in AVR32UC
7 28 RSR_INT1 Unused in AVR32UC
8 32 RSR_INT2 Unused in AVR32UC
9 36 RSR_INT3 Unused in AVR32UC
10 40 RSR_EX Unused in AVR32UC
11 44 RSR_NMI Unused in AVR32UC
12 48 RSR_DBG Return Status Register for Deb ug mode
13 52 RAR_SUP Unused in AVR32UC
14 56 RAR_INT0 Unused in AVR32UC
15 60 RAR_INT1 Unused in AVR32UC
16 64 RAR_INT2 Unused in AVR32UC
17 68 RAR_INT3 Unused in AVR32UC
18 72 RAR_EX Unused in AVR32UC
19 76 RAR_NMI Unused in AVR32UC
20 80 RAR_DBG Return Address Reg ister for Debug mode
21 84 JECR Unused in AVR32UC
22 88 JOSP Unused in AVR32UC
23 92 JAVA_LV0 Unused in AVR32UC
24 96 JAVA_LV1 Unused in AVR32UC
25 100 JAVA_LV2 Unused in AVR32UC
29
32072H–AVR32–10/2012
AT32UC3A3
26 104 JAVA_LV3 Unused in AVR32UC
27 108 JAVA_LV4 Unused in AVR32UC
28 112 JAVA_LV5 Unused in AVR32UC
29 116 JAVA_LV6 Unused in AVR32UC
30 120 JAVA_LV7 Unused in AVR32UC
31 124 JTBA Unused in AVR32UC
32 128 JBCR Unused in AVR32UC
33-63 132-252 Reserved Reserved for future use
64 256 CONFIG0 Configuration register 0
65 260 CONFIG1 Configuration register 1
66 264 COUNT Cycle Counter register
67 268 COMPARE Compare register
68 27 2 TLBEHI U nused in AVR32UC
69 27 6 TLBELO Unused i n AVR32UC
70 280 PTBR Unused in AVR32UC
71 28 4 TLBEAR Unused in AVR32UC
72 288 MMUCR Unused in AVR32UC
73 292 TLBARLO Unused in AVR32UC
74 296 TLBARHI Unused in AVR32UC
75 300 PCCNT Unused in AVR32UC
76 304 PCNT0 Unused in AVR32UC
77 308 PCNT1 Unused in AVR32UC
78 312 PCCR Unused in AVR32UC
79 316 BEAR Bus Error Address Register
80 320 MPU AR0 MPU Address Register region 0
81 324 MPU AR1 MPU Address Register region 1
82 328 MPU AR2 MPU Address Register region 2
83 332 MPU AR3 MPU Address Register region 3
84 336 MPU AR4 MPU Address Register region 4
85 340 MPU AR5 MPU Address Register region 5
86 344 MPU AR6 MPU Address Register region 6
87 348 MPU AR7 MPU Address Register region 7
88 352 MPUPSR0 MPU Privilege Select Register region 0
89 356 MPUPSR1 MPU Privilege Select Register region 1
90 360 MPUPSR2 MPU Privilege Select Register region 2
91 364 MPUPSR3 MPU Privilege Select Register region 3
Table 4-3. System Registers (Continued)
Reg # Address Name Function
30
32072H–AVR32–10/2012
AT32UC3A3
4.5 Exceptions and Interrupts
AVR32UC incorporates a powerful excep tion handling scheme. Th e differ ent exception sou rces,
like Illegal Op-code and extern al interrupt request s, have differen t priority levels, ensuri ng a well-
defined behavior when multiple exceptions are received simultaneously. Additionally, pending
exceptions of a higher priority class may preempt handling of ongoing exceptions of a lower pri-
ority class.
When an event occurs, t he exe cutio n of th e instr uct ion st r eam is ha lte d, an d e xecut ion co ntro l is
passed to an event handler at an address specified in Table 4-4 on page 33. Most of the han-
dlers are placed sequentially in the code space starting at the address specified by EVBA, with
four bytes between each handler. This gives ample space for a jump instruction to be placed
there, jumping to the event routine itself. A few critical handlers have larger spacing between
them, allowing the entire event routine to be placed directly at the add ress specified by the
EVBA-relative offset generated by hardware. All external interrupt sources have autovectored
interrupt service routine (ISR) addresses. This allows the interrupt controller to directly specify
the ISR addres s as an address relative to EVBA. The autovector offset has 14 address bits, giv-
ing an offset of maximum 16384 bytes. The target address of the event handler is calculated as
(EVBA | event_handler_offset), not (EVBA + event_handler_offset), so EVBA and exception
code segments must be set up appropriately. The same mechanisms are used to service all dif-
ferent types of events, including external interrupt requests, yielding a uniform event handling
scheme.
An interrupt controller does the priority handling of the external interrupts and provides the
autovector offset to the CPU.
4.5.1 System Stack Issues
Event handling in AVR32UC uses the system stack pointed to by the system stack pointer,
SP_SYS, for pushing and popping R8-R12, LR, status register, and return address. Since event
code may be timing-critical, SP_SYS should po int to memory addresses in the IRAM section,
since the timing of accesses to this memory section is both fast and deterministic.
92 368 MPUPSR4 MPU Privilege Select Register region 4
93 372 MPUPSR5 MPU Privilege Select Register region 5
94 376 MPUPSR6 MPU Privilege Select Register region 6
95 380 MPUPSR7 MPU Privilege Select Register region 7
96 384 MPUCRA Unused in this version of AVR32UC
97 388 MPUCRB Unused in this version of AVR32UC
98 392 MPUBRA Unused in this version of AVR32UC
99 396 MPUBRB Unused in this version of AVR32UC
100 400 MPUAPRA MPU Access Permission Register A
101 404 MPUAPRB MPU Access Permission Register B
102 408 MPUCR MPU Control Register
103-191 448-764 Reserved Reserved for future use
192-255 768-1020 IMPL IMPLEMENTATION DEFINED
Table 4-3. System Registers (Continued)
Reg # Address Name Function
31
32072H–AVR32–10/2012
AT32UC3A3
The user must also make sure that the system stack is large enough so that any event is able to
push the required registers to stack. If the system stack is full, and an event occurs, the system
will enter an UNDEFINED state.
4.5.2 Exceptions and Interrupt Requests
When an event other than scall or deb ug request is received by the core, the following act ions
are performed atomically:
1. The pending e vent will not be accepted if it is masked. The I3M, I2M, I1M, I0M, EM, and
GM bits in the Status Re gister are used to mask different events. Not all eve nts can be
masked. A few critical events (NMI, Unrecoverable Exception, TLB Multiple Hit, and
Bus Error) can not be masked. When an event is accepted, hardware automatically
sets the mask bits co rresponding t o all sour ces with eq ual or lo w er priority. This inh ibits
acceptance of other events of the same or lower priority, except for the critical events
listed above. Software may choose to clear some or all of these bits after saving the
necessary state if other priority schemes are desired. It is the event source’s respons-
ability to ensure that their events are left pending until accepted by the CPU.
2. When a request is accepted, the Status Regist er and Program Counter of the current
context is stored to the system stack. If the ev ent is an INT0, INT1, INT2, or INT3, reg-
isters R8-R12 and LR are a lso automatically stored to stack. Storing the Status
Register ensur es that the core is returned to the previous execution mode when the
current even t handlin g is co mplete d. When exceptions occur, both the EM and GM bits
are set, a nd the application may manually enable nested exceptions if desired by clear-
ing the appropriate bit. Each exception handler has a dedicated handler add ress, and
this address un iqu ely iden tifie s th e exception source.
3. The Mode bits are set to reflect the priority of the accepted event, and th e corr ect regi s-
ter file bank is selected. The address of the event handler, as shown in Table 4-4, is
loaded into the Program Counter.
The execution of the event handler routine then continues from the effective address calculated.
The rete instruction signals the end of the event. When encountered, th e Return Status Register
and Return Addr ess Register ar e popped f rom t he system st ack and r est ored to t he Statu s Re g-
ister and Program Counter. If the rete instruction returns from INT0, INT1, INT2, or INT3,
registers R8-R12 and LR are also popped from the system stack. The restored Status Register
contains informa tion allowin g th e core t o resum e ope ra tion in t he p re vious e xecut ion mode. T his
concludes the event handling.
4.5.3 Supervisor Calls
The AVR32 instruction set provides a supervisor mode call instruction. The scall ins truction is
designed so that privileged routines can be called from any context. This facilitates sharing of
code between different execution modes. Th e scall mechanism is designed so th at a minimal
execution cycle ov erhead is experienced when pe rforming supervisor routine ca lls from time-
critical event handlers.
The scall instruction behaves differently depending on which mode it is called from. The behav-
iour is detailed in the instruction set refer ence. In orde r to allow the scall ro utine to return to th e
correct context, a return from supervisor call instruction, rets, is implemented. In the AVR32UC
CPU, scall and rets uses the system stack to store the return address and the status register.
4.5.4 D ebug Requests
The AVR32 architecture d efines a dedicate d Debug mode. Wh en a debug requ est is received by
the core, Debug mode is entered. Entry into Debug mode can be masked by the DM bit in the
32
32072H–AVR32–10/2012
AT32UC3A3
status register. Upon entry into Debug mode, hardware sets the SR[D] bit and jumps to the
Debug Exception handler. By de fault, Debug mode executes in the exception context, but with
dedicated Return Address Register and Return Status Register. These dedicated registers
remove the need for storing this data to the system stack, thereby improving debuggability. The
mode bits in the status register can freely be manipulated in Debug mode, to observe registers
in all contexts, while retaining full privileges.
Debug mode is exited by executing the retd instruction. This returns to th e pr ev iou s con te x t.
4.5.5 Entry Points for Events
Several different event handler entry points exists. In AVR32UC, the reset address is
0x8000_0000. This places the reset address in the boot flash memory area.
TLB miss exceptions and scall have a dedicated space relative to EVBA where their event han-
dler can be placed. This speeds u p execution by removin g the need for a ju mp instruction placed
at the program address jumped to by the event hardware. All other exceptions have a dedicated
event routine entry point located relative to EVBA. The handler routine address identifies the
exception source directly.
AVR32UC uses the ITLB and DTLB protection exceptions to signal a MPU protection violation.
ITLB and DTLB miss exceptions are used to sig nal that an access address did not map to any of
the entries in the MPU. TLB multiple hit exception indicates that an access address did map to
multiple TLB entries, signalling an error.
All external interrupt requests have entry points located at an offset relative to EVBA. This
autovector offse t is specified by an external Inter rupt Controller. The program mer must make
sure that none of th e autovect or offset s inte rfere with the placement of other co de . Th e autovec-
tor offset has 14 addr ess bi ts, giving an offset of maximum 16384 bytes.
Special considerations should be made when loading EVBA with a pointer. Due to security con-
siderations, the event handlers should be located in non-writeable flash memory, or optionally in
a privileged memory protection region if an MPU is present.
If several events occur on t he same instruction, the y are handled in a prior itized way. The priorit y
ordering is presented in Tab le 4-4. If events o ccur on severa l instructions at different location s in
the pipeline, the events on the oldest instruction are a lways handled before any events on any
younger instruction, even if the younger instruction has events of higher priority than the oldest
instruction. An inst ruct io n B is youn ger than an instruction A if it was sent down the pipeline later
than A.
The addresses and priority of simultaneous events are shown in Table 4-4. Some of the excep-
tions are unused in AVR32UC since it has no MMU, copr ocessor interfa ce, or flo ating -po int unit.
33
32072H–AVR32–10/2012
AT32UC3A3
Table 4-4. Priority and Handler Addresses for Event s
Priority Handler Ad dr es s Nam e Event source Stored Return Address
1 0x8000_0000 Reset External input Undefined
2 Provided by OCD system OCD Stop CPU OCD system First non-completed instruction
3 EVBA+0x00 Unrecovera ble e xception Internal PC of offending instruction
4 EVBA+0x04 TLB multiple hit MPU
5 EVBA+0x08 Bus error data fetch Data bus First non-completed instru ction
6 EVBA+0x0C Bus error instruction fetch Data bus First non-completed instruction
7 EVBA+0x10 NMI External input First non-completed instruction
8 Autovectored Interrupt 3 request External input First non-completed instruction
9 Autovectored Interrupt 2 request External input First non-completed instruction
10 Autovectored Interrupt 1 request External input First non-completed instruction
11 Autovectored Interrupt 0 request External input First non-completed instruction
12 EVBA+0x14 Instruction Address CPU PC of offending instruction
13 EVBA+0x50 ITLB Miss MPU
14 EVBA+0x18 ITLB Protection MPU PC of offending instruction
15 EVBA+0x1C Breakpoint OCD system First non-completed instr uction
16 EVBA+0x20 Illegal Opcode Instruction PC of offending instruction
17 EVBA+0x24 Unimplemented instruction Instruction PC of offending instruction
18 EVBA+0x28 Privilege violation Instruction PC of offending instruction
19 EVBA+0x2C Floating-point UNUSED
20 EVBA+0x30 Coprocessor absent Instruction PC of offending instruction
21 EVBA+0x100 Supervisor call Instruction PC(Supervisor Call) +2
22 EVBA+0x34 Data Address (Read) CPU PC of offending instruction
23 EVBA+0x38 Data Address (Write) CPU PC of offe nding instruction
24 EVBA+0x60 DTLB Miss (Read) MPU
25 EVBA+0x70 DTLB Miss (Write) MPU
26 EVBA+0x3C DTLB Protection (Read) MPU PC of offending instruction
27 EVBA+0x40 DTLB Protection (Write) MPU PC of offending instruction
28 EVBA+0x44 DTLB Modified UNUSED
34
32072H–AVR32–10/2012
AT32UC3A3
4.6 Module Configuration
All AT32UC3A3 parts implement the CPU and Architecture Revision 2.
35
32072H–AVR32–10/2012
AT32UC3A3
5. Memories
5.1 Embedded Memories
•Internal High-Speed Flash
– 256KBytes (AT32UC3A3256/S)
– 128Kbytes (AT32UC3A3128/S)
– 64Kbytes (AT32UC3A364/S)
• 0 wait state access at up to 42MHz in worst case conditions
• 1 wait state access at up to 84MHz in worst case conditions
• Pipelined Flash arc hitecture, allo wing bur st reads from sequential Flash locations, hiding
penalty of 1 wait state access
• Pipelined Flash architecture typically reduces the cycle penalty of 1 wait state operation
to only 15% compared to 0 wait state operation
• 100 000 write cycles, 15-year data retention ca pability
• Sector lock capabilities, Bootloader protection, Security Bit
• 32 Fuses, Erased During Chip Erase
• User page for data to be preserved during Chip Erase
•Internal High-Speed SRAM
– 64KBytes, Single-cycle access at full speed on CPU Local Bus and accessible through the
High Speed Bud (HSB) matrix
– 2x32KBytes, acc essible independently through the High Speed Bud (HSB) matrix
5.2 Physical Memory Map
The System Bus is implemented as a bus matrix. All system bus addresses are fixed, and they
are never remapped in any way, not even in boot.
Note that AVR32 UC CPU uses unsegmented transla tion, as described in t he AVR32UC Techni-
cal Architecture Manual.
The 32-bit physical address space is mapped as follows:
Table 5-1. AT32UC3A3A4 Physical Memory Map
Device Start
Address
Size Size Size
AT32UC3A3256S
AT32UC3A3256
AT32UC3A4256S
AT32UC3A4256
AT32UC3A3128S
AT32UC3A3128
AT32UC3A4128S
AT32UC3A4128
AT32UC3A364S
AT32UC3A364
AT32UC3A464S
AT32UC3A464
Embedded CPU SRAM 0x00000000 64KByte 64KByte 64KByte
Embedded Flash 0x80000000 256KByte 128KByte 64KByte
EBI SRAM CS0 0xC0000000 16MByte 16MByte 16MByte
EBI SRAM CS2 0xC8000000 16MByte 16MByte 16MByte
EBI SRAM CS3 0xCC000000 16MByte 16MByte 16MByte
EBI SRAM CS4 0xD8000000 16MByte 16MByte 16MByte
EBI SRAM CS5 0xDC000000 16MByte 16MByte 16MByte
EBI SRAM CS1
/SDRAM CS0 0xD0000000 128MByte 128MByte 128MByte
USB Data 0xE0000000 64KByte 64KByte 64KByte
36
32072H–AVR32–10/2012
AT32UC3A3
5.3 Peripheral Address Map
HRAMC0 0xFF000000 32KByte 32KByte 32KByte
HRAMC1 0xFF008000 32KByte 32KByte 32KByte
HSB-PB Bridge A 0xFFFF0000 64KByte 64KByte 64KByte
HSB-PB Bridge B 0xFFFE0000 64KByte 64KByte 64KByte
Table 5-1. AT32UC3A3A4 Physical Memory Map
Device Start
Address
Size Size Size
AT32UC3A3256S
AT32UC3A3256
AT32UC3A4256S
AT32UC3A4256
AT32UC3A3128S
AT32UC3A3128
AT32UC3A4128S
AT32UC3A4128
AT32UC3A364S
AT32UC3A364
AT32UC3A464S
AT32UC3A464
Table 5-2. Peripheral Address Mapping
Address Peripheral Name
0xFF100000 DMACA DMA Controller - DMACA
0xFFFD0000 AES Advanced Encryption Standard - AES
0xFFFE0000 USB USB 2.0 Device and Host Interface - USB
0xFFFE1000 HMATRIX HSB Matrix - HMATRIX
0xFFFE1400 FLASHC Flash Controller - FLASHC
0xFFFE1C00 SMC Static Memory Controller - SMC
0xFFFE2000 SDRAMC SDRAM Controller - SDRAMC
0xFFFE2400 ECCHRS Error code corrector Hamming and Reed Solomon -
ECCHRS
0xFFFE2800 BUSMON Bus Monitor module - BUSMON
0xFFFE4000 MCI Mulitmedia Card Interface - MCI
0xFFFE8000 MSI Memory Stick Interface - MSI
0xFFFF0000 PDCA Peripheral DMA Controller - PDCA
0xFFFF0800 INTC Interrupt controller - INTC
37
32072H–AVR32–10/2012
AT32UC3A3
0xFFFF0C00 PM Power Manager - PM
0xFFFF0D00 RTC Real Time Counter - RTC
0xFFFF0D30 WDT Watchdog Timer - WDT
0xFFFF0D80 EIC External Interrupt Controller - EIC
0xFFFF1000 GPIO General Purpose Input/Output Controller - GPIO
0xFFFF1400 USART0 Universal Synchronous/Asynchronous
Receiver/Transmitter - USART0
0xFFFF1800 USART1 Universal Synchronous/Asynchronous
Receiver/Transmitter - USART1
0xFFFF1C00 USART2 Universal Synchronous/Asynchronous
Receiver/Transmitter - USART2
0xFFFF2000 USART3 Universal Synchronous/Asynchronous
Receiver/Transmitter - USART3
0xFFFF2400 SPI0 Serial Peripheral Interface - SPI0
0xFFFF2800 SPI1 Serial Peripheral Interface - SPI1
0xFFFF2C00 TWIM0 Two-wire Master Interface - TWIM0
0xFFFF3000 TWIM1 Two-wire Master Interface - TWIM1
0xFFFF3400 SSC Synchronous Serial Controller - SSC
0xFFFF3800 TC0 Timer/Counter - TC0
0xFFFF3C00 ADC Analog to Digital Converter - ADC
0xFFFF4000 ABDAC Audio Bitstream DAC - ABDAC
0xFFFF4400 TC1 Timer/Counter - TC1
Table 5-2. Peripheral Address Mapping
38
32072H–AVR32–10/2012
AT32UC3A3
5.4 CPU Local Bus Mapping
Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to
being mapped on the Peripheral Bus. These registers can therefore be reached both by
accesses on the Peripheral Bu s, and by accesses on the local bus.
Mapping these registers on the local bus allows cycle-deterministic toggling of GPIO pins since
the CPU and GPIO are the only modules connected to this bus. Also, since the local bus runs at
CPU speed, one write or read operation can be performed per clock cycle to the local bus-
mapped GPIO registers.
The following GPIO registers are mapped on the loca l bus:
0xFFFF5000 TWIS0 Two-wire Slave Interface - TWIS0
0xFFFF5400 TWIS1 Two-wire Slave Interface - TWIS1
Table 5-2. Peripheral Address Mapping
Table 5-3. Local Bus Mapped GPIO Registers
Port Register Mode Local Bus
Address Access
0 Output Driver Enable Register (ODER) WRITE 0x40000040 Write-only
SET 0x40000044 Write-only
CLEAR 0x40000048 Write-only
TOGGLE 0x4000004C Write-only
Output Value Register (OVR) WRITE 0x400000 50 Write-only
SET 0x40000054 Write-only
CLEAR 0x40000058 Write-only
TOGGLE 0x4000005C Write-only
Pin Value Registe r (PVR) - 0x40000060 Read-only
1 Output Driver Enable Register (ODER) WRITE 0x40000140 Write-only
SET 0x40000144 Write-only
CLEAR 0x40000148 Write-only
TOGGLE 0x4000014C Write-only
Output Value Register (OVR) WRITE 0x400001 50 Write-only
SET 0x40000154 Write-only
CLEAR 0x40000158 Write-only
TOGGLE 0x4000015C Write-only
Pin Value Registe r (PVR) - 0x40000160 Read-only
39
32072H–AVR32–10/2012
AT32UC3A3
2 Output Driver Enable Register (ODER) WRITE 0x40000240 Write-only
SET 0x40000244 Write-only
CLEAR 0x40000248 Write-only
TOGGLE 0x4000024C Write-only
Output Value Register (OVR) WRITE 0x400002 50 Write-only
SET 0x40000254 Write-only
CLEAR 0x40000258 Write-only
TOGGLE 0x4000025C Write-only
Pin Value Registe r (PVR) - 0x40000260 Read-only
3 Output Driver Enable Register (ODER) WRITE 0x40000340 Write-only
SET 0x40000344 Write-only
CLEAR 0x40000348 Write-only
TOGGLE 0x4000034C Write-only
Output Value Register (OVR) WRITE 0x400003 50 Write-only
SET 0x40000354 Write-only
CLEAR 0x40000358 Write-only
TOGGLE 0x4000035C Write-only
Pin Value Registe r (PVR) - 0x40000360 Read-only
Table 5-3. Local Bus Mapped GPIO Registers
Port Register Mode Local Bus
Address Access
40
32072H–AVR32–10/2012
AT32UC3A3
6. Boot Sequence
This chapter summarizes the boot sequence of the AT32UC3A3/A4. The behavior after power-
up is controlled by the Power Manager. For specific details, refer to Section 7. ”Power Manager
(PM)” on page 41 .
6.1 Starting of Clocks
After power-up, the device will be held in a reset state by the Power-On Reset circuitry, until the
power has stabilized throughout the device . Once the power has stabilized, the device will u se
the internal RC Oscillator as clock source.
On system start-up, the PLLs are disabled. All clocks to all modules are running. No clocks have
a divided frequency, all parts of the system receives a clock with the sam e frequency as the
internal RC Oscillator.
6.2 Fetching of Initial Instructions
After reset has been released, the AVR32 UC CP U starts fetching instruction s from the reset
address, which is 0x8000_0000. This address points to the first address in the intern al Flash.
The internal Flash uses VDDIO voltage during read and write operations. BOD33 monitors this
voltage and maintains the device under reset until VDDIO reaches the minimum voltage, pre-
venting any spurious execution from flash.
The code read from the internal Flash is free to configure the system to use for example the
PLLs, to divide the frequency of the clock routed to some of the peripherals, and to gate the
clocks to unused peripherals.
When powering up the device, there may be a delay before the voltage has stabilized, depend-
ing on the rise time of the supp ly used. The CPU can st art exe cuting code as soon as the supply
is above the POR thr eshold, and before the supply is stable. Befo re switching to a high-sp eed
clock source, the user should use the BOD to make sure the VDDCORE is above the minimum-
level (1.62V).
41
32072H–AVR32–10/2012
AT32UC3A3
7. Power Manager (PM)
Rev: 2.3.1.0
7.1 Features •Controls integrated oscillators and PLLs
•Generates cloc ks and resets f or digital logic
•Supports 2 crystal oscillators 0.4-20MHz
•Supports 2 PLLs 40-240MHz
•Supports 32KHz ultra-low power oscillator
•Integrated low-power RC oscillator
•On-the fly frequency change of CPU, HSB, PBA, and PBB clocks
•Sleep modes allow simple disabling of logic clocks, PLLs, and oscillators
•Module-level clock gating through maskable peripheral clocks
•Wake-up from internal or external interrupts
•Generic clocks with wide frequency range provided
•A utomatic identification of reset sources
•Controls brownout detector (BOD and BOD33), RC oscill ator, and ba ndgap voltage reference
through control and calibration registers
7.2 Overview The Power Manager (PM) controls the oscillators and PLLs, and generates the clocks and
resets in the device. The PM controls two fast crystal oscillators, as well as two PLLs, which can
multiply the clock from either oscillator to provide higher frequencies. Additionally, a low-power
32KHz oscillator is used to generate the real-time counter clock for high accuracy real-time mea-
surements. The PM also contains a low-power RC oscillator with fast start-up time, which can be
used to clock the digital logic.
The provided clocks are divided into synchronous and generic clocks. The synchronous clocks
are used to clock the main dig ital logic in the device, namely the CPU, and the modules a nd
peripherals connected to the HSB, PBA, and PBB buses. The generic clocks are asynchronous
clocks, which can be tuned precisely within a wide frequency range, which makes them suitable
for peripherals that require specific frequencie s, such as ti mers and communication modules.
The PM also contains advanced power-saving features, allowing the user to op timize the powe r
consumption for an application. The synchronous clocks are divided into three clock domains,
one for the CPU and HSB, one for modules on th e PBA bus, and one for modules on the PBB
bus.The three clocks can ru n a t dif fere nt spee ds, so the user ca n save powe r b y run nin g perip h-
erals at a relatively low clock, while maintaining a high CPU p erformance. Additionally , the
clocks can be independently changed on-the-fly, without halting any peripherals. This enables
the user to adjust the speed of the CPU and memories to the dynamic load of the application,
without disturbing or re- configuring active peripherals.
Each module also has a separate clock, enabling the user to switch off the clock for inactive
modules, to save further power. Additionally, clocks and oscillators can be automatically
switched off during idle periods by using the sleep instruction on the CPU. The system will return
to normal on occurrence of interrupts.
The Power Manager also contains a Reset Controller, which collects all possible reset sources,
generates ha rd and soft resets, and allows the reset source to be identified by software.
42
32072H–AVR32–10/2012
AT32UC3A3
7.3 Block Diagram
Figure 7-1. Power Manager Block Diagram
Sleep Controller
Oscillator and
PLL Control
PLL0
PLL1
Synchronous
Clock Generator
Generic Clock
Generator
Reset Controller
Oscillator 0
Oscillator 1
RC
Oscillator
Startup
Counter
Slow clock
Sleep
instruction
Power-On
Detector
Other reset
sources
resets
Generic clocks
Synchronous
clocks
CPU, HSB,
PBA, PBB
OSC/PLL
Control signals
RCSYS
32 KHz
Oscillator CLK_32
Interrupts
External Reset Pad
Calibration
Registers
Brown-Out
Detector
Voltage Regulator
fuses
43
32072H–AVR32–10/2012
AT32UC3A3
7.4 Product Dependencies
7.4.1 I/O Lines The PM provides a number of generic clock outputs, which can be connected to output pins,
multiplexed with I/O lines. The user must first program the I/O controller to assign these pins to
their peripheral function. If the I/O pins of the PM are not used by the application, they can be
used for other purposes by the I/O controller.
7.4.2 Interrupt The PM interrupt line is connect ed to o ne of t he inter nal sources of the in terr upt co ntro ller. Using
the PM interrupt requires the interrupt controller to be programmed first.
7.5 Functional Description
7.5.1 Slow Clock The slow clock is generated from an internal RC oscillator which is always running, except in
Static mode. The slow clock can be used for the main clock in the device, as described in Sec-
tion 7.5.5. The slow clock is also used for the Watchdog Timer and measuring various delays in
the Power Manager.
The RC oscillator has a 3 cycles startup time, and is always available when the CPU is running.
The RC oscillator operates at approximately 115 kHz. Software can change RC oscillator cali-
bration through the use of the RCCR register. Please see the Electrical Characteristics section
for details.
RC oscillator can also be used as the RTC clock when crystal accuracy is not required.
7.5.2 Oscillato r 0 an d 1 Ope rat io n
The two main oscillators are designed to be used with an external crystal and two biasing capac-
itors, as shown in Figure 7-2 on page 44. Oscillator 0 can be used for the main clock in the
device, as described in Section 7.5.5. Both oscillators can be used as source for the generic
clocks, as described in Section 7. 5. 8.
The oscillators are disabled by default after reset. When the oscillators are disabled, the XIN and
XOUT pins can be used as general purpose I/Os. When the oscillators are configured to use an
external clock, the clock must be applied to the XIN pin while the XOUT pin can be used as a
general purpose I/O.
The oscillators can be enabled by writing to the OSCnEN bits in MCCTR L. Operation mode
(external clock or crystal) is chosen by writing to the MODE field in OSCCTRLn. Oscillators are
automatically switched off in certain sleep modes to reduce power consumption, as described in
Section 7.5.7.
After a hard reset, or when waking up from a sleep mode that disabled the oscillators, the oscil-
lators may need a certain amount of time to stabilize on the correct frequency. This start-up time
can be set in the OSCCTRLn register.
The PM masks the oscillator outputs during the start-up time, to ens ure that no unstable clocks
propagate to the digital logic. The OSCnRDY bits in POSCSR are automatically set and cleared
according to the status of the oscillators. A z ero to one transition on these bits can also be con-
figured to generate an interrupt, as described in Section 7.6.7.
44
32072H–AVR32–10/2012
AT32UC3A3
Figure 7-2. Oscillator Connections
7.5.3 32 KHz Oscillato r Opera ti on
The 32 KHz oscillator operates as described for Oscillator 0 and 1 above. The 32 KHz oscillator
is used as source clo ck for the Real-Time Counter.
The oscillator is disabled by default, but can be enabled by writing OSC32EN in OSCCTRL32.
The oscillator is an ultra-low power design and remains enabled in all sleep modes except Static
mode.
While the 32 KHz oscillator is disabled, the XIN32 and XOUT32 pins are available as general
purpose I/Os. When the oscillator is configured to work with an external clock (MODE field in
OSCCTRL32 register), th e external clock must be connected to XIN32 wh ile the XOUT32 pin
can be used as a general purpose I/O.
The startup time of the 32 KHz oscillator can be set in the OSCCTRL32, after which OSC32RDY
in POSCSR is set. An interrupt can be generated on a zero to one transition of OSC32RDY.
As a crystal oscillator usually requ ires a very long startup time (up to 1 second), the 32 KHz
oscillator will keep running across resets, except Power-On-Reset.
7.5.4 PLL OperationThe device contains two PLLs, PLL0 and PLL1. These are disabled by default, but can be
enabled to provide high frequency source clocks for synchronous or generic clocks. The PLLs
can take either Oscillator 0 or 1 as reference clock. The PLL output is divided by a multiplication
factor, and the PLL compares the resulting clock to the reference clock. The PLL will adjust its
output frequency until the two compared clocks are equal, thus locking the output frequency to a
multiple of the reference clock frequency.
When the PLL is switched on, or when changing the clock source or multiplication factor for the
PLL, the PLL is unlocked and the output frequency is undefined. The PLL clock for the digital
logic is autom atically masked when the PL L is unlocked, to preven t connected digital logic from
receiving a too hig h fr eq ue n cy and th us become unstab le.
XIN
XOUT
C2
C1
45
32072H–AVR32–10/2012
AT32UC3A3
Figure 7-3. PLL with Control Logic and Filters
7.5.4.1 Enab ling the PLL
PLLn is enabled by writing the PLLEN bit in the PLLn register. PLLOSC selects Oscillator 0 or 1
as clock source. The PLLMUL and PLLDIV bitfields m ust be written with the multiplication and
division factors, respect ive ly, crea t ing t he voltag e contr olled ocillat or frequ ency f VCO and the PLL
frequency fPLL :
if PLLDIV > 0
fIN = fOSC/2 • PLLDIV
fVCO = (PLLMUL+1)/(PLLDIV) • fOSC
if PLLDIV = 0
fIN = fOSC
fVCO = 2 • (PLLMUL+1) • fOSC
Note: Refer to Electrical Characteristics section for FIN and FVCO frequency range.
If PLLOPT[1] field is set to 0:
fPLL = fVCO.
If PLLOPT[1] field is set to 1:
fPLL = fVCO / 2.
PLL
Output
Divider
0
1
Osc0 clock
Osc1 clock
PLLOSC
PLLEN
PLLOPT
PLLMUL
LOCK
Mask PLL clock
Input
Divider
PLLDIV
Fin
46
32072H–AVR32–10/2012
AT32UC3A3
The PLLn:PLLOPT field should be set to proper values according to the PLL operating fre-
quency. The PLLOPT field can also be set to divide the output frequency of the PLLs by 2.
The lock signal for each PLL is available as a LOCKn flag in POSCSR. An interrupt can be gen-
erated on a 0 to 1 transition of these bits.
7.5.5 Synchronous Clocks
The slow clock (default), Oscillator 0, or PLL0 provide the source for the main clock, which is the
common root for the synchronous clocks for the CPU/HSB, PBA, and PBB modules. The main
clock is divided by an 8-bit prescaler, and each of these four synchronous clocks can run from
any tapping of this prescaler, or the undivided main clock, as long as fCPU ≥ fPBA,B,. The synchro-
nous clock source can be changed on-the fly, responding to varying load in the application. The
clock domains can be shut down in sleep mode, as described in Section 7.5.7. Additionally, the
clocks for each module in the four domains can be individually masked, to avoid power con-
sumption in inactive modules.
Figure 7-4. Synchronous Clock Generation
7.5.5.1 Selecting PLL or oscillator for the main clock
The common main clock can be connected to the slo w clock, Oscillator 0, or PLL0. By default,
the main clock will be connected to the slow clock. The user can connect the main clock to Oscil-
lator 0 or PLL0 by writing the MCSEL field in the Main Clock Control Register (MCCTRL). This
must only be done after that unit has been enabled, otherwise a deadlock will occur. Care
should also be taken that the new frequency of the synchronous clocks does not excee d the
maximum frequency for each clock domain.
Mask
Prescaler
Osc0 clock
PLL0 clock
MCSEL
0
1
CPUSEL
CPUDIV
Main clock
Sleep
Controller
CPUMASK
CPU clocks
HSB clocks
PBAclocks
PBB clocks
Sleep
instruction
Slow clock
47
32072H–AVR32–10/2012
AT32UC3A3
7.5.5.2 Selecting synchronous clock division ratio
The main clock feeds an 8-bit presca ler, which ca n be used to gener ate the synchron ous clocks.
By default, the synchronous clocks run on the undivided main clock. The user can select a pres-
caler division for the CPU clock by writing CKSEL.CPUDIV to 1 and CPUSEL to the prescaling
value, resulting in a CPU clock frequency:
Similarly, the clock for the PBA, and PBB can be divided by writing their respective fields. To
ensure correct operation, frequencies must be selected so that fCPU ≥ fPBA,B. Also, frequencies
must never exceed the specified maximum frequency for each clock domain.
CKSEL can be written without halting or disabling peripheral modules. Writing CKSEL allows a
new clock setting to be written to all synchronous clocks at the sa me time. It is poss ible to kee p
one or more clocks unchanged by writing the same value a before to the xxxDIV and xxxSEL
fields. This way, it is possible to e.g. scale CPU and HSB speed according to the req uired perfor-
mance, while keeping the PBA and PBB frequency constant.
For modules connected to the HSB bus, the PB clock frequency must be set to the same fre-
quency than the CPU clock.
7.5.5.3 Clock ready flag
There is a slight delay from CKSEL is written and the new clock setting becomes effective. Dur-
ing this interval, the Clock Ready (CKRDY) flag in ISR will read as 0. If IER.CKRDY is written to
one, the Power Manager interrupt can be triggered when the new clock setting is effective.
CKSEL must not be re-written while CKRDY is zero, or the system may become unstable or
hang.
7.5.6 Periph eral Clock Mask ing
By default, the clock for all modules are enabled, regardless of which modules are actually being
used. It is possible to disable the clock for a module in the CPU, HSB, PBA, or PBB clock
domain by writing the corresponding bit in the Clock Mask register (CPU/HSB/PBA/PBB) to 0.
When a module is not clocked, it will cease operation, and its registers cannot be read or written.
The module can be re-enabled later by writing the corresponding mask bit to 1.
A module may be connected to several clock domains, in which case it will have several mask
bits.
Table 7-7 on page 58 contains the list of implemented maskable clocks.
7.5.6.1 Cautionary note
The OCD clock must never be switched off if the user wishes to debug the device with a JTAG
debugger.
Note that clocks should only be switched off if it is certain that the module will not be used.
Switching off the clock for the internal RAM will cause a problem if the stack is mapped there.
Switching off the clock to the Power Manager (PM), which contains the mask registers, or the
corresponding PBx bridge, will make it impossible to write the mask registers again. In this case,
they can only be re-enabled by a system reset.
fCPU fmain 2CPUSEL 1+()
⁄=
48
32072H–AVR32–10/2012
AT32UC3A3
7.5.6.2 Mask ready flag
Due to synchronization in the clock generator, there is a slight delay from a mask register is writ-
ten until the new mask setting goes into effect. When clearing mask bits, this delay can usually
be ignored. However, when setting mask bits, the registers in the corresponding module must
not be written until the clock has actually be re-enabled. The status flag MSKRDY in ISR pro-
vides the required mask status information. When writing either mask register with any value,
this bit is cleared. The bit is set when the clocks have been enabled and disabled according to
the new mask setting . Optionally, the Power Manager interrupt can be enabled by writing the
MSKRDY bit in IER.
7.5.7 Sleep Modes In normal operation, all clock domains are active, allowing software execution and peripheral
operation. When the CPU is idle, it is possible to switch off th e CPU clock and optionally other
clock domains to save power. This is activated by the sleep instruction, which takes the sleep
mode index number as arg ument.
7.5.7.1 Entering and exiting sleep modes
The sleep instruction will halt the CPU and all modules belonging to the stopped clock domains.
The modules will be halted regardless of the bit settings of the mask registers.
Oscillators and PLLs can also be switched off to save power. So me of these modules have a rel-
atively long start-up time, and are only switched off when very low power consumption is
required.
The CPU and affected modules are restarted when the sleep mode is exited. This occurs when
an interrupt triggers. Note that even if an interrupt is enabled in sleep mode, it may not trigger if
the source module is not clocked.
7.5.7.2 Supported sleep modes
The following sleep modes ar e supported. These are detailed in Table 7-1 on page 49.
• Idle: The CPU is stopped, the rest of the chip is operating. Wake-up sources are any
interrupt.
• Frozen: The CPU and HSB modules are stopped, peripherals are operating. Wake-up
sources are any interrupt from PB module s.
• Standby: All synchronous clocks are stopped, but oscillators and PLLs are running, allowing
quick wake-up to normal mode. Wake-up sources are RTC or exter n al interrupt.
• Stop: As Standby, but Oscillator 0 and 1, and the PLLs are stopped. 32 KHz (if enabled) and
RC oscillators and RTC/WDT still operate. Wake-up sources are RTC, external interrupt, or
external reset pin.
• DeepStop: All synchronous clocks, Oscillator 0 and 1 and PLL 0 and 1 are stopped. 32 KHz
oscillator can run if enabled. RC oscillator still operates. Bandgap voltage reference, BOD
and BOD33 are turned off. Wake-up sources are RTC, external interrupt (EIC) or external
reset pin.
• Static: All oscillators, including 32 KHz and RC oscillator are stopped. Bandgap voltage
ref erence , BOD a nd BOD33 detectors ar e turned off . Wake-up source s are extern al interrupt
(EIC) in asynchronous mode only or external reset pin.
49
32072H–AVR32–10/2012
AT32UC3A3
The power level of the internal voltage regulator is also adjusted according to the sleep mode to
reduce the internal regulator power consumption.
7.5.7.3 Precautions when entering sleep mode
Modules communicating with external circuits sho uld normally be disabled before entering a
sleep mode that will stop the module operation. This prevents erratic behavior when entering or
exiting sleep mode. Please refer to the relevant module documentation for recommended
actions.
Communication between the synchronous clock domains is disturbed when entering and exiting
sleep modes. This mean s t hat bus tr ansa ct ions ar e no t allowe d bet ween clo ck doma ins a ffe ct ed
by the sleep mode. The system may hang if the bus clocks are stopped in the middle of a bus
transaction.
The CPU is automatically stopp ed in a safe st ate to ensure that all CPU bus operations a re com-
plete when the sleep mode goes into effect. Thus, when entering Idle mode, no further action is
necessary.
When entering a sleep mode (except Idle mode), all HSB masters must be stopped before
entering the sleep mode. Also, if there is a chance that any PB write operations are incomplete,
the CPU should perform a read operation from any register on the PB bus before executing the
sleep instruction. This will stall the CPU while waiting for any pending PB operations to
complete.
When entering a sleep mode deeper or equal to DeepStop, the VBus asynchronous interrupt
should be disabled (USBCON.VBUSTE = 0).
7.5.7.4 Wake Up
The USB can be used to wake up the part from sleep modes through register AWEN of the
Power Manager.
7.5.8 Generic Clocks
Timers, communication modules, and other modules connected to external circuitry may require
specific clock frequencies to operate correctly. The Power Manager contains an implementation
defined num be r of gen er i c clocks that can prov ide a wide range of accurate clock frequencies.
Table 7-1. Sleep Modes
Index Sleep Mode CPU HSB PBA,B
GCLK
Osc0,1
PLL0,1,
SYSTIMER Osc32 RCSYS
BOD &
BOD33 &
Bandgap Voltage
Regulator
0 Idle Stop Run Run Run Run Run On Full power
1 Froz en Stop Sto p Run Run Run Run On Full power
2 Standby Stop Stop Stop Run Run Run On Full power
3 Stop Stop Stop Stop Stop Run Run On Low power
4 DeepStop Stop Stop Stop Stop Run Run Off Low power
5 Static Stop Stop Stop Stop Stop Stop Off Low power
50
32072H–AVR32–10/2012
AT32UC3A3
Each generic clock module runs from either Oscilla tor 0 or 1, or PLL0 or 1. The selected source
can optionally be divided by any even integer up to 512. Each clock can be independently
enabled and disabled, and is also automatically disabled along with peripheral clocks by the
Sleep Controller.
Figure 7-5. Generic Clock Generation
7.5.8.1 Enab ling a generic clock
A generic clock is enabled by writing the CEN bit in GCCTRL to 1. Each generic clock can use
either Oscillator 0 or 1 or PLL0 or 1 as source, as selected by the PLLSEL and OSCSEL bits.
The source clock can optionally be divided by writing DIVEN to 1 and the division factor to DIV,
resulting in the ou tp ut freq u ency:
7.5.8.2 Disabling a generic clock
The generic clock can be d isable d by writing CEN to zero or en tering a sleep mode t hat disab les
the PB clocks. In either case, the generic clock will be switched off on the firs t falling edge after
the disabling event, to ensure that no glitches occur. If CEN is written to 0, the bit will still read as
1 until the next falling edge occurs, and the clock is actually switched off. When writing CEN to 0,
the other bits in GCCTRL should not be changed until CEN reads as 0, to avoid glitches on the
generic clock.
When the clock is disabled, both the prescaler and output are reset.
7.5.8.3 Changing cl ock frequency
When changing generic clock frequ ency by writing GCCTRL, the cloc k should be switched off by
the procedure above, before bein g re-en abled wit h the new clo ck source or d ivision sett ing. T his
prevents glitches during the transition.
Divider
0
1
Osc0 clock
PLL0 clock
PLLSEL
OSCSEL
Osc1 clock
PLL1 clock
Generic Clock
DIV
0
1
DIVEN
Mask
CEN
Sleep
Controller
fGCLK fSRC 2DIV 1+()×()⁄=
51
32072H–AVR32–10/2012
AT32UC3A3
7.5.8.4 Generic clock implementation
The generic clocks are allocated to different functions as shown in Table 7-2 on page 51.
7.5.9 Divided PB Clocks
The clock generator in the Power Manager provide s divided PBA and PBB clocks for use by
peripherals that require a prescaled PBx clock. This is described in the documentation for the
relevant modules.
The divided clocks are not directly maskable, but are stopped in sleep modes where the PBx
clocks are stopped.
7.5.10 Debug Operation
The OCD clock must never be switched off if the user wishes to debug the device with a JTAG
debugger.
During a debug session, the user may need to halt the system to inspect mem ory and CPU reg-
isters. The clocks normally keep running during this debug operation, but some peripherals may
require the clocks to be stopped, e.g. to prevent timer overflow, which would cause the program
to fail. For this reason, peripherals on the PBA and PBB buses may use “debug qualified” PBx
clocks. This is described in the documentation for the relevant modules. The divided PBx clocks
are always debug qualified clocks.
Debug qualified PBx clocks are stopped during debug operation. The debug system can option-
ally keep these clocks running during the debug operation. This is described in the
documentat ion for the On-Chip Debug system.
7.5.11 Reset Controller
The Reset Controller collec ts the various r eset sources in t he system an d generates ha rd and
soft resets for the digital logic.
The device contains a Power-On Detector, which keeps the system reset until power is stable.
This eliminates the ne ed for external reset circuitry to guaran tee stable oper ation when powering
up the device.
It is also possible to reset the device by asserting the RESET_N pin. This pin has an internal pul-
lup, and does not need to be drive n externally when negated. Table 7-4 on page 53 lists these
and other reset sources supported by the Reset Controller.
Table 7-2. Generic Clock Allocation
Clock number Function
0 GCLK0 pin
1 GCLK1 pin
2 GCLK2 pin
3 GCLK3 pin
4 GCLK_USBB
5 GCLK_ABDAC
52
32072H–AVR32–10/2012
AT32UC3A3
Figure 7-6. Reset Controller Block Diagram
In addition to the listed reset types, the JTAG can keep parts of the device statically reset
through the JTAG Reset Register. See JTAG documentation for details.
Table 7-3. Reset Description
When a reset occurs, some parts of the chip are not necessarily reset, dep ending on the reset
source. Only the Power On Reset (POR) will force a reset of the whole chip.
Reset source Description
Power-on Reset Supply voltage below the power-on reset detector
threshold vo ltage
External Reset RESET_N pin asserted
Brownout Reset Supply voltage below the bro w no ut reset detector
threshold vo ltage
CPU Error Cause d by an illegal CPU access to external memory
while in Supervisor mode
Watchdog Timer See watchdog timer docu men t atio n.
OCD See On-Chip Debug document atio n
JTAG
Reset
Controller
RESET_N
Power-On
Detector
OCD
WDT
RC_RCAUSE
CPU, HSB,
PBA, PBB
OCD, RTC/WDT,
Clock Generator
Brownout
Detector
53
32072H–AVR32–10/2012
AT32UC3A3
Table 7-4 on page 53 lists parts of the device that are reset, depending on the reset source.
The cause of the last reset can be read fr om the RCAUSE reg ister. Th is registe r contains one bit
for each reset source, and can be read during the boot sequence of an application to determine
the proper ac tion to be taken.
7.5.11.1 Power-On detecto r
The Power-On Detector monitors the VDDCORE sup ply pin and generates a reset when the
device is powered on. The reset is active until the supply voltag e from the linear reg ulator is
above the power-on threshold level. The reset will be re-activated if the voltage drops below the
power-on threshold level. See Electrical Characteristics for parametric details.
7.5.11.2 Brown-Out detector
The Brown-Out Detector (BOD) monitors the VDDCORE supply pin and compares the supply
voltage to the bro wn-out de tection leve l, as set in BOD.LE VEL. The BOD is disabled by de fault,
but can be enable d ei ther by sof tw are or b y f lash fuse s. Th e Br own-Out Det ector can e ither gen-
erate an interrupt or a reset when the supply voltage is below the brown-out dete ction level. In
any case, the BOD output is available in bit POSCSR.BODDET bit.
Note that any change to the BOD.LEVEL field of the BOD register should be done with the BOD
deactivated to avoid spurious reset or interrupt.
See Electrical Characteristics chapter for parametric details.
Table 7-4. Effect of the Different Reset Events
Power-On
Reset External
Reset Watchdog
Reset BOD
Reset BOD33
Reset
CPU
Error
Reset OCD
Reset
CPU/HSB/PBA/PBB
(excluding Power Manager) YYYYYYY
32 KHz oscillator Y N N N N N N
RTC control register Y N N N N N N
GPLP register s Y N N N N N N
Watchdog control register Y Y N Y Y Y Y
Voltage calibration register Y N N N N N N
RCSYS Calibration register Y N N N N N N
BOD control register Y Y N N N N N
BOD33 control register Y Y N N N N N
Bandgap control register Y Y N N N N N
Clock control registers Y Y Y Y Y Y Y
Osc0/Osc1 and control registers Y Y Y Y Y Y Y
PLL0/PLL1 and control registers Y Y Y Y Y Y Y
OCD system and OCD registers Y Y N Y Y Y N
54
32072H–AVR32–10/2012
AT32UC3A3
7.5.11.3 Brown-Out detector 3V3
The Brown-Out Detector 3V3 (BOD33) monitors one VDDIO supply pin and compares the sup-
ply voltage to the brown-o ut detection 3V3 level, which is typically ca librated at 2V7. The BOD33
is enabled by default, but can be disabled by software. The Brown-Out Detector 3V3 can either
generate an interrupt or a reset when the supply voltage is below the brown-out detection3V3
level. In any case, the BOD33 output is available in bit POSCSR.BOD33DET bit.
Note that any change to the BOD33.LEVEL field of the BOD33 register should be done with the
BOD33 deactivated to avoid spurious reset or interrupt.
The BOD33.LEVEL default value is calibrated to 2V7
See Electrical Characteristics chapter for parametric details.
Table 7-5. VDDIO pin monitored by BOD33
7.5.11.4 External reset
The external reset detector monitors the state of the RESET_N pin. By default, a low level on
this pin will generate a reset.
7.5.12 Calibration Registers
The Power Manager contro ls the calibration of the RC oscillator, voltage regulator, bandga p
voltage reference through several calibrations registers.
Those calibration registers are loaded after a Power On Reset with default values stored in fac-
tory-progr a mm e d fla s h fu se s.
Although it is not recommended to override default factory settings, it is still possible to override
these default values by writing to those registers. To prevent unexpected writes due to software
bugs, write access t o th ese r egi ste rs is pro tec ted b y a “ke y”. Fir st, a write t o th e r egi ster must be
made with the field “KEY” equal to 0x55 then a second write must be issued with the “KEY” field
equal to 0xAA.
TFBGA144 QFP144 VFBGA1 00
H5 81 E5
55
32072H–AVR32–10/2012
AT32UC3A3
7.6 User Interface
Table 7-6. PM Register Memory Map
Offset Register Register Name Access Reset State
0x000 Main Clock Control MCCTRL Read/Write 0x00000000
0x0004 Clock Select CKSEL Read/Write 0x00000000
0x008 CPU Mask CPUMASK Read/Write 0x00000003
0x00C HSB Mask HSBMASK Read/Write 0x00000FFF
0x010 PBA Mask PBAMASK Read/Write 0x001FFFFF
0x014 PBB Mask PBBMASK Read/Write 0x000003FF
0x020 PLL0 Control PLL0 Read/Write 0x00000000
0x024 PLL1 Control PLL1 Read/Write 0x00000000
0x028 Oscillator 0 Control Register OSCCTRL0 Read/Write 0x00000000
0x02C Oscillator 1 Control Register OSCCTRL1 Read/Write 0x00000000
0x030 Oscillator 32 Control Register OSCCTRL32 Read/Write 0x00000000
0x040 PM Interrupt Enable Register IER Write-only 0x00000000
0x044 PM Interrupt Disable Register IDR Write-only 0x00000000
0x048 PM Interrupt Mask Register IMR Read-only 0x00000000
0x04C PM Interrupt Status Register ISR Read-only 0x00000000
00050 PM Interrupt Clear Register ICR Write-only 0x00000000
0x054 Power and Oscillators Status Register POSCSR Read/Write 0x00000000
0x060 Generic Clock Control 0 GCCTRL0 Read/Write 0x00000000
0x064 Generic Clock Control 1 GCCTRL1 Read/Write 0x00000000
0x068 Generic Clock Control 2 GCCTRL2 Read/Write 0x00000000
0x06C Generic Clock Control 3 GCCTRL3 Read/Write 0x00000000
0x070 Generic Clock Control 4 GCCTRL4 Read/Write 0x00000000
0x074 Generic Clock Control 5 GCCTRL5 Read/Write 0x00000000
0x0C0 RC Oscillator Calibration Register RCCR Read/Write Factory settings
0x0C4 Bandgap Calibration Register BGCR Read/Write Factory settings
0x0C8 Linear Regulator Calibration Register VREGCR Read/Write Factory settings
0x0D0 BOD Level Register BOD Read/Write BOD fuses in Flash
0x0D4 BOD33 Level Register BOD33 Read/Write BOD33 reset enable
BOD33 LEVEL=2V7
0x0140 Reset Cause Register RCAUSE Read/Write Latest Reset Source
0x0144 Asynchronous Wake Enable Register AWEN Read/Write 0x00000000
0x200 General Purpose Low-Power register GPLP Read/Write 0x00000000
56
32072H–AVR32–10/2012
AT32UC3A3
7.6.1 Main Clock Control Register
Name: MCCTRL
Access Type: Read/Write
Offset: 0x00
Reset Value: 0x00000000
• OSC1EN: Oscillator 1 Enable
1: Oscillator 1 is enabled
0: Oscillator 1 is disabled
• OSC0EN: Oscillator 0 Enable
1: Oscillator 0 is enabled
0: Oscillator 0 is disabled
• MCSEL: Main Clock Select
This field contains the clock selected as the main clock.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
----OSC1ENOSC0EN MCSEL
MCSEL Selected Clock
0b00 Slow Clock
0b01 Oscillator 0
0b10 PLL 0
0b11 Reserved
57
32072H–AVR32–10/2012
AT32UC3A3
7.6.2 Clock Select Register
Name: CKSEL
Access Type: Read/Write
Offset: 0x04
Reset Value: 0x00000000
• PBBDIV: PBB Division Enable
PBBDIV = 0: PBB clock equals main clock.
PBBDIV = 1: PBB clock equals main clock divided by 2(PBBSEL+1).
• PBADIV, PBASEL: PBA Division and Clock Select
PBADIV = 0: PBA clock equals main clock.
PBADIV = 1: PBA clock equals main clock divided by 2(PBASEL+1).
• CPUDIV, CPUSEL: CPU/HSB Division and Clock Select
CPUDIV = 0: CPU/HSB clock equals main clock.
CPUDIV = 1: CPU/HSB clock equals main clock divided by 2(CPUSEL+1).
Note that if xxxDIV is written t o 0, xxxSEL should also be written to 0 to ensure correct operation.
Also note that writing this register clears POSCSR.CKRDY. The register must not be re-written until CKRDY goes high.
31 30 29 28 27 26 25 24
PBBDIV ---- PBBSEL
23 22 21 20 19 18 17 16
PBADIV ---- PBASEL
15 14 13 12 11 10 9 8
--------
76543210
CPUDIV---- CPUSEL
58
32072H–AVR32–10/2012
AT32UC3A3
7.6.3 Clock Mask Registers
Name: CPU/HSB/PBA/PBBMASK
Access Type: Read/Write
Offset: 0x08-0x14
Reset Value: 0x00000003/0x00000FFF/0x001FFFFF/0x000003FF
• MASK: Clock Mask
If bit n is written to zero , the clock f or module n is stopped. If bit n is writen to one, the clock f or module n is enabled according to
the current power mode. The number of implemented bits in each mask register, as well as which module clock is controlled by
each bit, is shown in Table 7-7 on page 58.
31 30 29 28 27 26 25 24
MASK[31:24]
23 22 21 20 19 18 17 16
MASK[23:16]
15 14 13 12 11 10 9 8
MASK[15:8]
76543210
MASK[7:0]
Table 7-7. Maskable module clocks in AT32UC3A3.
Bit CPUMASK HSBMASK PBAMASK PBBMASK
0 - FLASHC INTC HMATRIX
1OCD
(1) PBA Bridge I/O USBB
2 - PBB Bridge PDCA FLASHC
3 - USBB PM/RTC/EIC SMC
4 - PDCA ADC SDRAMC
5 - EBI SPI0 ECCHRS
6 - PBC Bridge SPI1 MCI
7- DMACA TWIM0 BUSMON
8 - BUSMON TWIM1 MSI
9 - HRAMC0 TWIS0 AES
10 - HRAMC1 TWIS1 -
11 - (2) USART0 -
12 - - USART1 -
13 - - USART2 -
14 - - USART3 -
15 - - SSC -
59
32072H–AVR32–10/2012
AT32UC3A3
Note: 1. This bit must be set to one if the user wishes to debug the device with a JTAG debugger.
2. This bits must be set to one
16 SYSTIMER
(compare/count
registers clk)
-TC0-
17 - - TC1 -
18 - - ABDAC -
19 - - (2) -
20 - - (2) -
31:21 - - - -
Table 7-7. Maskable module clocks in AT32UC3A3.
Bit CPUMASK HSBMASK PBAMASK PBBMASK
60
32072H–AVR32–10/2012
AT32UC3A3
7.6.4 PLL Control Registers
Name: PLL0,1
Access Type: Read/Write
Offset: 0x20-0x24
Reset Value: 0x00000000
• PLLTEST: PLL Test
Reserved for internal use. Alwa ys write to 0.
• PLLCOUNT: PLL Count
Specifies the number of slow clock cycles before ISR.LOCKn will be set after PLLn has been written, or after PLLn has been
automatically re-enabled after exiti ng a sleep mode.
• PLLMUL: PLL Multiply Factor
• PLLDIV: PLL Division Factor
These fields determine the ratio of the PLL output frequency to the source oscilla tor frequency. Formula is detallied in Section
7.5.4.1
• PLLOPT: PLL Option
Select the operating range for the PLL.
PLLOPT[0]: Select the VCO frequency range
PLLOPT[1]: Enable the extra output divider
PLLOPT[2]: Disable the Wide-Bandwidth mode (Wide-Bandwidth mode allows a faster startup time and out-of-lock time)
• PLLOSC: PLL Oscillator Select
0: Oscillator 0 is the source for the PLL.
1: Oscillator 1 is the source for the PLL.
31 30 29 28 27 26 25 24
PLLTEST - PLLCOUNT
23 22 21 20 19 18 17 16
---- PLLMUL
15 14 13 12 11 10 9 8
---- PLLDIV
76543210
- - - PLLOPT PLLOSC PLLEN
Description
PLLOPT[0]: VCO frequency 0 80MHz<fvco<180MHz
1 160MHz<fvco<240MHz
PLLOPT[1]: Output divider 0 fPLL = fvco
1f
PLL = fvco/2
PLLOPT[2] 0 Wide Bandwidth Mode enabled
1 Wide Bandwidth Mode disabl ed
61
32072H–AVR32–10/2012
AT32UC3A3
• PLLEN: PLL Enable
0: PLL is disabled.
1: PLL is enabled.
62
32072H–AVR32–10/2012
AT32UC3A3
7.6.5 Oscillato r 0/ 1 Co nt rol Registers
Name: OSCCTRL0,1
Access Type: Read/Write
Offset: 0x28-0x2C
Reset Value: 0x00000000
• STARTUP: Oscillator Startup Time
Select startup time for the oscillator.
• MODE: Oscillato r Mode
Choose between crystal, or external clock
0: External clock connected on XIN, XOUT can be used as an I/O (no crystal)
1 to 3: reserved
4: Cr ystal is connected to XIN/XOUT - Oscillator is used with gain G0 ( XIN from 0.4 MHz to 0.9 MHz ).
5: Cr ystal is connected to XIN/XOUT - Oscillator is used with gain G1 ( XIN from 0.9 MHz to 3.0 MHz ).
6: Cr ystal is connected to XIN/XOUT - Oscillator is used with gain G2 ( XIN from 3.0 MHz to 8.0 MHz ).
7: Cr ystal is connected to XIN/XOUT - Oscillator is used with gain G3 ( XIN from 8.0 Mhz).
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
----- STARTUP
76543210
----- MODE
STARTUP Number of RC oscillator
clock cycle Approximative Equivalent time
(RCSYS = 115 kHz)
00 0
1 64 560 us
2128 1.1ms
32048 18ms
44096 36ms
58192 71ms
6 16384 142 ms
7 Reserved Reserved
63
32072H–AVR32–10/2012
AT32UC3A3
7.6.6 32 KHz Oscilla tor C ont rol Register
Name: OSCCTRL32
Access Type: Read/Write
Offset: 0x30
Reset Value: 0x00000000
• STARTUP: Oscillator Startup Time
Select startup time for 32 KHz oscillator
Note: This register is only reset by Power-On Reset
• MODE: Oscillato r Mode
Choose between crystal, or external clock
0: External clock connected on XIN32, XOUT32 can be used as a I/O (no crystal)
1: Cr ystal is connected to XIN32/XOUT32 - Oscillator is used with automatic gain control
2 to 7: Reserved
• OSC32EN: Enable the 32 KHz oscillator
0: 32 KHz Oscillator is disabled
1: 32 KHz Oscillator is enabled
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
----- STARTUP
15 14 13 12 11 10 9 8
----- MODE
76543210
-------OSC32EN
STARTUP Number of RC oscillator
clock cycle Approximative Equivalent time
(RCSYS = 115 kHz)
00 0
1128 1.1ms
2 8192 72.3 ms
3 16384 143 ms
4 65536 570 ms
5 131072 1.1 s
6 262144 2.3 s
7 524288 4.6 s
64
32072H–AVR32–10/2012
AT32UC3A3
7.6.7 Interrupt Enable Register
Name: IER
Access Type: Write-only
Offset: 0x40
Reset Value: 0x00000000
Writing a one to a bit in this register will set the corresponding bit in IMR.
Writing a zero to a bit in this register has no effect.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
- - - - - - BOD33DET BODDET
15 14 13 12 11 10 9 8
- - - - - - OSC32RDY OSC1RDY
76543210
OSC0RDY MSKRDY CKRDY - - - LOCK1 LOCK0
65
32072H–AVR32–10/2012
AT32UC3A3
7.6.8 Interrupt Disable Register
Name: IDR
Access Type: Write-only
Offset: 0x44
Reset Value: 0x00000000
Writing a one to a bit in this register will clear the corresponding bit in IMR.
Writing a zero to a bit in this register has no effect.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
- - - - - - BOD33DET BODDET
15 14 13 12 11 10 9 8
- - - - - - OSC32RDY OSC1RDY
76543210
OSC0RDY MSKRDY CKRDY - - - LOCK1 LOCK0
66
32072H–AVR32–10/2012
AT32UC3A3
7.6.9 Interrupt Mask Register
Name: IMR
Access Type: Read-only
Offset: 0x48
Reset Value: 0x00000000
0: The corresponding interr upt is disabled.
1: The corresponding interrupt is enabled.
A bit in this register is cleared when the corresponding bit in IDR is wr itten to one.
A bit in this register is set when the corresponding bit in IER is written to one.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
- - - - - - BOD33DET BODDET
15 14 13 12 11 10 9 8
- - - - - - OSC32RDY OSC1RDY
76543210
OSC0RDY MSKRDY CKRDY - - - LOCK1 LOCK0
67
32072H–AVR32–10/2012
AT32UC3A3
7.6.10 Interrupt Status Register
Name: ISR
Access Type: Read-only
Offset: 0x4C
Reset Value: 0x00000000
• BOD33DET: Bro wn out detection
This bit is set when a 0 to 1 transition on POSCSR.BOD33DET bit is detected: BOD33 has detecte d th at po we r su pp ly is
going below BOD33 re fe re nc e va lu e .
This bit is cleared when the corresponding bit in ICR is written to one.
• BODDET: Brown out detection
This bit is set when a 0 to 1 transition on POSCSR.BODDET bit is detected: BOD has detected that power supply is going
below BOD reference value.
This bit is cleared when the corresponding bit in ICR is written to one.
• OSC32RDY: 32 KHz oscillator Ready
This bit is set when a 0 to 1 transition on the POSCSR.OSC32RDY bit is detected: The 32 KHz oscillator is stable and
ready to be used as clock source.
This bit is cleared when the corresponding bit in ICR is written to one.
• OSC1RDY: Oscillator 1 Ready
This bit is set when a 0 to 1 transition on the POSCSR.OSC1RDY bit is detected: Oscillator 1 is stable and ready to be used
as clock source.
This bit is cleared when the corresponding bit in ICR is written to one.
• OSC0RDY: Oscillator 0 Ready
This bit is set when a 0 to 1 transition on the POSCSR.OSC1RDY bit is detected: Oscillator 1 is stable and ready to be used
as clock source.
This bit is cleared when the corresponding bit in ICR is written to one.
• MSKRDY: Mask Ready
This bit is set when a 0 to 1 transition on the POSCSR.MSKRDY bit is detected: Clocks are now masked according to the
(CPU/HSB/PBA/PBB)_MASK registers.
This bit is cleared when the corresponding bit in ICR is written to one.
• CKRDY: Clock Ready
0: The CKSEL register has been wri tten, and the new clock setting is not yet effective.
1: The synchronous clocks have frequencies as indicated in the CKSEL register .
Note: Writing a one to ICR.CKRDY has no effect.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
- - - - - - BOD33DET BODDET
15 14 13 12 11 10 9 8
- - - - - - OSC32RDY OSC1RDY
76543210
OSC0RDY MSKRDY CKRDY - - - LOCK1 LOCK0
68
32072H–AVR32–10/2012
AT32UC3A3
• LOCK1: PLL1 locked
This bit is set when a 0 to 1 transition on the POSCSR.LOCK1 bit is detected: PLL 1 is locked and ready to be selected as
clock source.
This bit is cleared when the corresponding bit in ICR is written to one.
• LOCK0: PLL0 locked
This bit is set when a 0 to 1 transition on the POSCSR.LOCK0 bit is detected: PLL 0 is locked and ready to be selected as
clock source.
This bit is cleared when the corresponding bit in ICR is written to one.
69
32072H–AVR32–10/2012
AT32UC3A3
7.6.11 Interrupt Clear Register
Name: ICR
Access Type: Write-only
Offset: 0x50
Reset Value: 0x00000000
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will clear the corresponding bit in ISR and the corresponding interrupt request.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
- - - - - - BOD33DET BODDET
15 14 13 12 11 10 9 8
- - - - - - OSC32RDY OSC1RDY
76543210
OSC0RDY MSKRDY CKRDY - - - LOCK1 LOCK0
70
32072H–AVR32–10/2012
AT32UC3A3
7.6.12 Power and Oscillators Status Register
Name: POSCSR
Access Type: Read-only
Offset: 0x54
Reset Value: 0x00000020
• BOD33DET: Brown out 3V3 detection
0: No BOD33 event
1: BOD33 has detected that power supply is going below BOD33 reference value.
• BODDET: Brown out detection
0: No BOD event
1: BOD has detected that power supply is going below BOD reference value.
• OSC32RDY: 32 KHz oscillator Ready
0: The 32 KHz oscillator is not enabled or not ready.
1: The 32 KHz oscillator is stable and ready to be used as clock source.
• OSC1RDY: OSC1 ready
0: Oscillator 1 not enabled or not ready.
1: Oscillator 1 is stable and ready to be used as clock source.
• OSC0RDY: OSC0 ready
0: Oscillator 0 not enabled or not ready.
1: Oscillator 0 is stable and ready to be used as clock source.
• MSKRDY: Mask ready
0: Mask register has been changed, masking in progress.
1: Clock are masked according to xxx_MASK
• CKRDY:
0: The CKSEL register has been wri tten, and the new clock setting is not yet effective.
1: The synchronous clocks have frequencies as indicated in the CKSEL register .
• LOCK1: PLL 1 locked
0:PLL 1 is unlocked
1:PLL 1 is locked, and ready to be selected as clock source.
• LOCK0: PLL 0 locked
0: PLL 0 is unlocked
1: PLL 0 is locked, and ready to be selected as clock source.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
------BOD33DETBODDET
15 14 13 12 11 10 9 8
------OSC32RDYOSC1RDY
76543210
OSC0RDY MSKRDY CKRDY - - - LOCK1 LOCK0
71
32072H–AVR32–10/2012
AT32UC3A3
7.6.13 Generic Clock Control Register
Name: GCCTRLx
Access Type: Read/Write
Offset: 0x60 - 0x74
Reset Value: 0x00000000
There is one GCCTRL register per generic clock in the design.
• DIV: Division Factor
• DIVEN: Divide Enable
0: The generic clock equals the undivided source clock.
1: The generic clock equals the source clock divided by 2*(DIV+1).
• CEN: Clock Enable
0: Clock is stopped.
1: Clock is running.
• PLLSEL: PLL Select
0: Oscillator is source for the generic clock.
1: PLL is source for the generic clock.
• OSCSEL: Oscillato r Select
0: Oscillator (or PLL) 0 is source for the generic clock.
1: Oscillator (or PLL) 1 is source for the generic clock.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
DIV[7:0]
76543210
- - - DIVEN - CEN PLLSEL OSCSEL
72
32072H–AVR32–10/2012
AT32UC3A3
7.6.14 RC Osc ill at or Cal ib r at io n Regis te r
Name: RCCR
Access Type: Read/Write
Offset: 0xC0
Reset Value: 0x00000000
• KEY: Register Wr ite protection
This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to have an effect.
• FCD: Flash Calibration Don e
Set to 1 when CTRL, HYST, and LEVEL fields have been updated by the Flash fuses after power-on reset, or after Flash fuses
are reprogrammed. The CTRL, HYST and LEVEL values wi ll not be updated again by the Flash fuses until a new power-on
reset or the FCD field is written to zero.
• CALIB: Ca libration Value
Calibration Value for the RC oscillator.
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
-------FCD
15 14 13 12 11 10 9 8
------ CALIB
76543210
CALIB
73
32072H–AVR32–10/2012
AT32UC3A3
7.6.15 Bandgap Calibration Register
Name: BGCR
Access Type: Read/Write
Offset: 0xC4
Reset Value: 0x00000000
• KEY: Register Wr ite protection
This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to have an effect.
• FCD: Flash Calibration Don e
Set to 1 when the CALIB field has been updated by the Flash fuses after power-on reset or when the Flash fuses are
reprogrammed. The CALIB field will not be updated again by the Flash fuses until a new power-on reset or the FCD field is
written to zero.
• CALIB: Ca libration value
Calibration value for Bandgap. See Electrical Characteristi cs for voltage values.
It is not recommended to override default factory settings in the BGCR register. Flash reliability is not guaranted if this value is
modified by the user
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
-------FCD
15 14 13 12 11 10 9 8
--------
76543210
----- CALIB
74
32072H–AVR32–10/2012
AT32UC3A3
7.6.16 PM Voltage Regulator Calibration Regist er
Name: VREGCR
Access Type: Read/Write
Offset: 0xC8
Reset Value: 0x00000000
• KEY: Register Wr ite protection
This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to have an effect.
Calibration value for Voltage Regulator. See Electrical Characteristics for vol tage values.
• FCD: Flash Calibration Don e
Set to 1 when the CALIB field has been updated by the Flash fuses after power-on reset or when the Flash fuses are
reprogrammed. The CALIB field will not be updated again by the Flash fuses until a new power-on reset or the FCD field is
written to zero.
• CALIB: Ca libration value
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
-------FCD
15 14 13 12 11 10 9 8
--------
76543210
----- CALIB
75
32072H–AVR32–10/2012
AT32UC3A3
7.6.17 BOD Control Register
Name: BOD
Access Type: Read/Write
Offset: 0xD0
Reset Value: 0x00000000
• KEY: Register Wr ite protection
This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to have an effect.
• FCD: BOD Fuse calibration done
Set to 1 when CTRL, HYST and LEVEL fields has been updated by the Flash fuses after power-on reset or Flash fuses update
If one, the CTRL, HYST and LEVEL values will no t be updated again by Flash fuses
Can be cleared to allow subsequent overwriting of the value by Flash fuses
• CTRL: BOD Control
0: BOD is off
1: BOD is enabled and can reset the chip
2: BOD is enabled and but cannot reset the chip. Only interrupt will be sent to interrupt controlle r, if enabled in the IMR register.
3: BOD is off
• HYST: BOD Hysteresis
0: No hysteresis
1: Hysteresis On
• LEVEL: BOD Level
This field sets the triggering threshold of the BOD. See Electric al Characteristics for actual voltage levels.
Note that any change to the LEVEL field of the BOD register should be done with the BOD deactivated to avoid spurious reset
or interrupt.
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
-------FCD
15 14 13 12 11 10 9 8
------ CTRL
76543210
- HYST LEVEL
76
32072H–AVR32–10/2012
AT32UC3A3
7.6.18 BOD3 3 Co nt rol Regist e r
Name: BOD33
Access Type: Read/Write
Offset: 0xD4
Reset Value: 0x0000010X
• KEY: Register Wr ite protection
This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to have an effect.
• FCD: BOD33 Fuse calibration done
Set to 1 when LEVEL field has been updated by the Flash fuses after power-on reset or Flash fuses update
If one, the LEVEL value will not be up dated again by Flash fuses
Can be cleared to allow subsequent overwriting of the value by Flash fuses
• CTRL: BOD33 Control
0: BOD33 is off
1: BOD33 is enabled and can reset the chip
2: BOD33 is enabled and but cannot reset the chip. On ly interrupt will be sent to interrupt controller , if enabled in the IMR
register.
3: BOD33 is off
• LEVEL: BOD33 Level
This field sets the triggering threshold of the BOD33. See Electrical Cha racteristics for actual voltage levels.
Note that any change to the LEVEL field of the BOD33 register should be done with the BOD33 deactivated to avoid spurious
reset or interrupt.
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
-------FCD
15 14 13 12 11 10 9 8
------ CTRL
76543210
-- LEVEL
77
32072H–AVR32–10/2012
AT32UC3A3
7.6.19 Reset Cause Register
Name: RCAUSE
Access Type: Read-only
Offset: 0x140
Reset Value: 0x00000000
• BOD33: Brown-out 3V3 Reset
The CPU was reset due to the supply voltage 3V3 being lower than the brown-out threshold leve l.
• OCDRST: OCD Reset
The CPU was reset because the RES strobe in the OCD Development Control register has been wri tten to one.
• CPUERR: CPU Error
The CPU was reset because it had detected an illegal access.
• JTAG: JTAG reset
The CPU was reset by setting the bit RC_CPU in the JTAG reset register.
• WDT: Watchdog Reset
The CPU was reset because of a watchdog timeout.
• EXT: External Reset Pin
The CPU was reset due to the RESET pin being asserted.
• BOD: Brown-out Reset
The CPU was reset due to the supply voltage 1V8 being lower than the brown-out threshold leve l.
• POR Power-on Reset
The CPU was reset due to the supply voltage being lower than the power-on threshold level.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
-----BOD33-OCDRST
76543210
CPUERR - - JTAG WDT EXT BOD POR
78
32072H–AVR32–10/2012
AT32UC3A3
7.6.20 Asynchronous Wake Up Enable
Name: AWEN
Access Type: Read/Write
Offset: 0x144
Reset Value: -
•USB_WAKEN : Wake Up Enable Register
Writing a zero to this bit will disable the USB wake up.
Writing a one to this bit will enable the USB wake up.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
-------USB_WAKEN
79
32072H–AVR32–10/2012
AT32UC3A3
7.6.21 General Purpose Low-power Register
Name: GPLP
Access Type: Read/Write
Offset: 0x200
Reset Value: 0x00000000
These registers are general purpose 32-bit registers that are reset only by po wer-on-reset. Any other reset will keep the content
of these registers untouched. User software can use these register to save context variables in a very low power mode.
Two GPLP register are implemented in AT32UC3A3.
31 30 29 28 27 26 25 24
GPLP
23 22 21 20 19 18 17 16
GPLP
15 14 13 12 11 10 9 8
GPLP
76543210
GPLP
80
32072H–AVR32–10/2012
AT32UC3A3
8. Real Time Counter (RTC)
Rev: 2.4.0.1
8.1 Features •32-bit real-time counter with 16-bit prescaler
•Clocked from RC oscillator or 32KHz oscillator
•Long delays
– Max timeout 272years
•High resolution: Max count frequency 16KHz
•Extremely low power consumption
•Available in all sleep modes except Static
•Interrupt on wrap
8.2 Overview The Real Time Counter (RTC) enables periodic interrupts at long intervals, or accurate mea-
surement of real-time sequences. The RTC is fed from a 16-bit prescaler, which is clocked from
the system RC oscillator or the 32KHz crystal oscillator. Any tapping of the prescaler can be
selected as clock source for the RT C, enabling both high resolution and lon g timeouts. The pres-
caler cannot be written directly, but can be cleared by the user.
The RTC can generate an interrupt when the counter wraps around the value stored in the top
register (TOP), producing accurate periodic interrupts.
8.3 Block Diagram
Figure 8-1. Real Time Counter Block Diagram
8.4 Product Dependencies
In order to use t his modu le, othe r p arts o f th e syst em must be conf igu red cor re ctly, as de scr ibed
below.
16-bit Prescaler
RCSYS
32-bit counter
VAL
TOP
TOPI IRQ
CLK_32
CTRL
EN
CLK32 PSEL
1
0
81
32072H–AVR32–10/2012
AT32UC3A3
8.4.1 Power Management
The RTC remains operating in all sleep modes except Static mode. Interrupts are not available
in DeepStop mode.
8.4.2 Clocks The RTC can us e the system RC oscillator as clock sourc e. This oscillator is always enabled
whenever this module is active. Please refer to the Electrical Characte ristics chapter for the
characteristic frequency of this oscillator (fRC).
The RTC can also use the 32 KHz crystal oscilla tor as clock source. This oscillator must be
enabled before use. Please refer to the Power Mana ger chapter for details.
The clock for the RTC bus interface (CLK_RTC) is generated by the Power Manager. This clock
is enabled at reset, and can be disabled in t he Power Ma nager. It is r ecommended to di sable the
RTC before disabling the clock, to avoid freezing the RTC in an undefined state.
8.4.3 Interrupts The RTC interrup t request line is connected to the interrupt contr oller. Using the RTC interrupt
requires the interrupt controller to be programmed first.
8.4.4 Debug Operation
The RTC prescaler is frozen during debug operation, unless the OCD system keeps peripherals
running in debug operation.
8.5 Functional Description
8.5.1 RTC Operation
8.5.1.1 Source clockThe RTC is enabled by writing a one to the Enable bit in the Control Register (CTRL.EN). The
16-bit prescaler will then increment on the selected clock. The prescaler cannot be read or writ-
ten, but it can be reset by wr iting a one to t he Prescaler Clear b it in CTRL register (CTRL.PCLR).
The 32KHz Os cillator Select bit in CTRL register (CTRL.CLK32) selects either the RC oscillator
or the 32 KHz oscillator as clock source (defined as INPUT in the formula below) for the
prescaler.
The Prescale Select field in CTRL register (CTRL.PSEL) selects the prescaler tapping, selecting
the source clock for the RTC:
8.5.1.2 Counter operation
When enabled, the RTC will increment until it reaches TOP, and then wraps to 0x0. The status
bit TOPI in Interrupt Status Register (ISR) is set to one when this occurs. From 0x0 the counter
will count TOP+1 cycles of the source clock before it wraps back to 0x0.
fRTC fINPUT 2⁄PSEL 1+()
=
82
32072H–AVR32–10/2012
AT32UC3A3
The RTC count value can be read from or written to the Value register (VAL). Due to synchroni-
zation, continuous reading of the VAL register with the lowest prescaler setting will skip every
other value.
8.5.1.3 RT C inte r rupt
The RTC interrupt is ena bled by writing a one to the Top Interrupt b it in the In terrupt Enable Reg-
ister (IER.TOPI), and is disabled by writing a one to the Top Interrupt bit in the Interrupt Disable
Register (IDR.TOPI). The Interrupt Mask Register (IMR) can be read to see whether or not the
interrupt is enabled. If enabled, an interrupt w ill be generated if the TOPI bit in the Interrupt Sta-
tus Register (ISR) is set. The TOPI bit in ISR can be cleared by writing a one to the TOPI bit in
the Interrupt Clea r Register (ICR.TOPI).
The RTC interrupt can wake the CPU from all sleep modes except DeepStop and Static modes.
8.5.1.4 RT C wakeupThe RTC can also wake up the CPU directly without triggering an interrupt when the ISR.TOPI
bit is set. In this case, the CPU will continue executing from the instruction following the sleep
instruction.
This direct RTC wake- up is enabled by writin g a one to the Wake Enab le bit in the CTRL r egister
(CTRL.WAKEN). When the CPU wakes from sleep, the CTRL.WAKEN bit must be written to
zero to clear the internal wake signal to the sleep controller, otherwise a new sleep instruction
will have no effect.
The RTC wakeup is available in all sleep modes except Static mode. The RTC wakeup can be
configured independently of the RTC interrupt.
8.5.1.5 Busy bit Due to the crossing of clock domains, the RTC uses a few clock cycles to propagate the values
stored in CTRL, TOP, and VAL to the RTC. The RTC Busy bit in CTRL (CTRL.BUSY) indicates
that a register write is still going on and all writes to TOP, CTRL, and VAL will be discarded until
the CTRL.BUSY bit goes low again.
83
32072H–AVR32–10/2012
AT32UC3A3
8.6 User Interface
Table 8-1. RTC Register Memory Map
Offset Register Register Name Access Reset
0x00 Control Register CTRL Read/Write 0x00010000
0x04 Value Register VAL Read/Write 0x00000000
0x08 Top Register TOP Read/Write 0xFFFFFFFF
0x10 Interrupt Enable Register IER W rite-only 0x00000000
0x14 Interrupt Disable Register IDR Write-onl y 0x00000000
0x18 Interrupt Mask Register IMR Read-only 0x00000000
0x1C Interrupt Status Register ISR Read-only 0x00000000
0x20 Interrupt Clear Register ICR Write-only 0x00000000
84
32072H–AVR32–10/2012
AT32UC3A3
8.6.1 Control Register
Name: CTRL
Access Type: Read/Write
Offset: 0x00
Reset Value: 0x00010000
• CLKEN: Clock Enable
1: The clock is enabled.
0: The clock is disabled.
• PSEL: Prescale Select
Selects prescaler bit PSEL as source clock for the RTC.
• BUSY: RTC Busy
This bit is set when the RTC is b usy and will discard writes to TOP, VAL, and CTRL.
This bit is cleared when the RTC accepts writes to T OP, VAL, and CTRL.
• CLK32: 32 KHz Oscillator Select
1: The RTC uses the 32 KHz oscillator as clock source.
0: The RTC uses the RC oscillator as clock source.
• WAKEN: Wakeup Enable
1: The RTC wakes up the CPU from sleep modes.
0: The RTC does not wake up the CPU from sleep modes.
• PCLR: Prescaler Clear
Writing a one to this bit clears the prescaler.
Writing a zero to this bit has no effect.
This bit alw ays reads as zero.
• EN: Enable
1: The RTC is enabled.
0: The RTC is disabled.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
-------CLKEN
15 14 13 12 11 10 9 8
- - - - PSEL
76543210
- - - BUSY CLK32 WAKEN PCLR EN
85
32072H–AVR32–10/2012
AT32UC3A3
8.6.2 Value Regi ster
Name: VAL
Access Type: Read/Write
Offset: 0x04
Reset Value: 0x00000000
• VAL[31:0]: RTC Value
This value is incremented on every rising edge of the source clock.
31 30 29 28 27 26 25 24
VAL[31:24]
23 22 21 20 19 18 17 16
VAL[23:16]
15 14 13 12 11 10 9 8
VAL[15:8]
76543210
VAL[7:0]
86
32072H–AVR32–10/2012
AT32UC3A3
8.6.3 Top Register
Name: TOP
Access Type: Read/Write
Offset: 0x08
Reset Value: 0xFFFFFFFF
• VAL[31:0]: RTC Top Value
VAL wraps at this value.
31 30 29 28 27 26 25 24
VAL[31:24]
23 22 21 20 19 18 17 16
VAL[23:16]
15 14 13 12 11 10 9 8
VAL[15:8]
76543210
VAL[7:0]
87
32072H–AVR32–10/2012
AT32UC3A3
8.6.4 Interrupt Enable Register
Name: IER
Access Type: Write-only
Offset: 0x10
Reset Value: 0x00000000
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will set the corresponding bit in IMR.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
-------TOPI
88
32072H–AVR32–10/2012
AT32UC3A3
8.6.5 Interrupt Disable Register
Name: IDR
Access Type: Write-only
Offset: 0x14
Reset Value: 0x00000000
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will clear the corresponding bit in IMR.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
-------TOPI
89
32072H–AVR32–10/2012
AT32UC3A3
8.6.6 Interrupt Mask Register
Name: IMR
Access Type: Read-only
Offset: 0x18
Reset Value: 0x00000000
0: The corresponding interr upt is disabled.
1: The corresponding interrupt is enabled.
A bit in this register is cleared when the corresponding bit in IDR is wr itten to one.
A bit in this register is set when the corresponding bit in IER is written to one.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
-------TOPI
90
32072H–AVR32–10/2012
AT32UC3A3
8.6.7 Interrupt Status Register
Name: ISR
Access Type: Read-only
Offset: 0x1C
Reset Value: 0x00000000
• TOPI: Top Interrupt
This bit is set when VAL has wrapped at its top value.
This bit is cleared when the corresponding bit in ICR is written to one.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
-------TOPI
91
32072H–AVR32–10/2012
AT32UC3A3
8.6.8 Interrupt Clear Register
Name: ICR
Access Type: Write-only
Offset: 0x20
Reset Value: 0x00000000
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will clear the corresponding bit in SR and the correspondi ng interrupt request.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
-------TOPI
92
32072H–AVR32–10/2012
AT32UC3A3
9. Watchdog Timer (WDT)
Rev: 2.4.0.1
9.1 Features •Watchdog timer counter with 32-bit prescaler
•Clocked fr om the system RC oscillator (RCSYS)
9.2 Overview The Watchdog Timer (WDT) has a prescaler generating a time-out period. This prescaler is
clocked from the RC oscillator. The watchdog timer must be periodic ally reset by software within
the time-out pe riod, othe rwise, the device is re se t and starts executing from the boot vect or. This
allows the device to recover from a condition that has caused the syst em to be unstable.
9.3 Block Diagram
Figure 9-1. WDT Block Diagra m
9.4 Product Dependencies
In order to use t his modu le, othe r p arts o f th e syst em must be conf igu red cor re ctly, as de scr ibed
below.
9.4.1 Power Management
When the WDT is enabled, the WDT r emains clocked in a ll sleep modes, and it is n ot possible to
enter Static mode.
9.4.2 Clocks The WDT can use the system RC oscillator (RCSYS) as clock source. This oscillator is always
enabled whenever these modules are active. Please refer to the Electrical Characteristics chap-
ter for the characteristic frequency of this oscillator (fRC).
9.4.3 Debug Operation
The WDT prescaler is frozen during debug operation, unless the On-Chip Debug (OCD) system
keeps peripherals running in debug operation.
RCSYS
CLR
Watchdog
Detector
CTRL
32-bit
Prescaler Watchdog Reset
EN
93
32072H–AVR32–10/2012
AT32UC3A3
9.5 Functional Description
The WDT is enabled by writing a one to the Enable bit in the Control register (CTRL.EN). This
also enables the system RC clock (CLK_RCSYS) for the prescaler. The Prescale Select field
(PSEL) in the CTRL register selects the watchdog time-out period:
TWDT = 2(PSEL+1) / fRC
The next time-out period will begin as soon as the watchdog reset has occurred and count down
during the reset sequence. Care must be taken when selecting the PSEL field value so that the
time-out perio d is greater tha n the start up time of the chip, otherwise a watch dog reset can r eset
the chip before any code has been run.
To avoid accidental di sa bling of the wat chdo g, the CTRL register must be writ ten twice, fi rst with
the KEY field set to 0x55, then 0xAA without changing the other bits. Failure to do so will cause
the write operation to be ignored, and the CTRL register value will not change.
The Clear regis ter (CLR) must be written with any va lue with regular inte rvals shorter than the
watchdog time-out period. Otherwise, the device will receive a soft reset, and the code will start
executing fro m th e bo ot vector.
When the WDT is enabled, it is not possible to enter Static mode. Attempting to do so will result
in entering Shutdown mod e, leaving the WDT operational.
9.6 User Interface
Table 9-1. WDT Register Memory Map
Offset Register Register Name Access Reset
0x00 Control Register CTRL Read/Write 0x00000000
0x04 Clear Register CLR Write-only 0x00000000
94
32072H–AVR32–10/2012
AT32UC3A3
9.6.1 Control Register
Name: CTRL
Access Type: Read/Write
Offset: 0x00
Reset Value: 0x00000000
•KEY: Write protection key
This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to be effective.
This field always reads as zero.
•PSEL: Prescale Select
PSEL is used as watchdog timeout period.
•EN: WDT Enable
1: WDT is enabled.
0: WDT is disabled.
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
- - - PSEL
76543210
-------EN
95
32072H–AVR32–10/2012
AT32UC3A3
9.6.2 Clear Register
Name: CLR
Access Type: Write-only
Offset: 0x04
Reset Value: 0x00000000
•CLR:
Writing periodically any value to this field when the WDT is enabled, within the watchdog time-out period, will prevent a
watchdog reset.
This field always reads as zero.
31 30 29 28 27 26 25 24
CLR[31:24]
23 22 21 20 19 18 17 16
CLR[23:16]
15 14 13 12 11 10 9 8
CLR[15:8]
76543210
CLR[7:0]
96
32072H–AVR32–10/2012
AT32UC3A3
10. Interrupt Controller (INTC)
Rev: 1.0.1.5
10.1 Features •Autovectored low latency interrupt service with programmable priority
– 4 priority levels for regular, maskable interrupts
– One Non-Maskable Interrupt
•Up to 64 groups of interrupts with up to 32 interrupt requests in each group
10.2 Overview The INTC collects inte rrupt re quests fr om the per iphe ra ls, pr ior itize s t hem , and de live rs an inte r-
rupt request a nd an auto vect or to t he CPU. Th e AVR32 archit ecture support s 4 pr iority leve ls for
regular, maskable interrupts, and a Non-Maskable Interrupt (NMI).
The INTC supports u p to 64 gr oups of in terrupts. Each group ca n have up to 32 inter rupt req uest
lines, these lines are connected to the peripherals. Each group has an Interrupt Priority Register
(IPR) and an Inte rrupt Reques t Register (IRR). The IPRs are use d to assign a prio rity level and
an autovector to each gr oup, and the IRRs a re used to identify the active interrupt request within
each group. If a group has only one interrupt request line, an active interrupt group uniquely
identifies the active interrup t request line, and the corresponding IRR is not needed. The INTC
also provides one Interrupt Cause Register (ICR) per priority le vel. These registers identify the
group that has a pending interrupt of the corresponding priority level. If several groups have a
pending interrupt of the same level, the group with the lowest number takes priority.
10.3 Block Diagram
Figure 10-1 gives an overview of the INTC. The grey boxes represent registers that can be
accessed via the user interface. The interrupt requests from the peripherals (IREQn) and the
NMI are input on the left side of the figure. Signals to and from the CPU are on the right side of
the figure .
97
32072H–AVR32–10/2012
AT32UC3A3
Figure 10-1. INTC Block Diagram
10.4 Product Dependencies
In order to use t his modu le, othe r p arts o f th e syst em must be conf igu red cor re ctly, as de scr ibed
below.
10.4.1 Power Management
If the CPU enters a sleep mode that disables CLK_SYNC, the INTC will stop functioning and
resume operation after the system wakes up from sleep mode.
10.4.2 Clocks The clock for the INTC bus interface (CLK_INTC) is generated by the Power Manager. This
clock is enabled at reset, and can be disabled in the Power Manager.
The INTC sampling logic runs on a clock which is stopped in any of the sleep modes where the
system RC oscillator is not running. This clock is referred to as CLK_SYNC. This clock is
enabled at reset, and only turned off in sleep modes where the system RC oscillator is stopped.
10.4.3 Debug Operation
When an external debugger forces the CPU into debug mode, the INTC continues normal
operation.
10.5 Functional Description
All of the incoming interrupt requests (IREQs) are sampled into the corresponding Interrupt
Request Register (IRR). The IRRs must be accessed to identify which IREQ within a group that
is active. If several IREQs within the same group are active, the interrupt service routine must
prioritize between them. All of the input lines in each group are logically ORed together to form
the GrpReqN lines, indicating if there is a pending interrupt in the corresponding group.
The Request Masking hardware maps each of the GrpReq lines to a priority level from INT0 to
INT3 by associating each group with the Interrupt Level (INTLEVEL) field in the corresponding
Request
Masking
OR
IREQ0
IREQ1
IREQ2
IREQ31
GrpReq0
Masks SREG
Masks
I[3-0]M
GM
INTLEVEL
AUTOVECTOR
Prioritizer
CPUInterrupt Controller
OR GrpReqN
NMIREQ
OR
IREQ32
IREQ33
IREQ34
IREQ63
GrpReq1
IRR Registers IPR Registers ICR Registers
INT_level,
offset
INT_level,
offset
INT_level,
offset
IPR0
IPR1
IPRn
IRR0
IRR1
IRRn
ValReq0
ValReq1
ValReqN
.
.
.
.
.
.
.
.
.
98
32072H–AVR32–10/2012
AT32UC3A3
Interrupt Priority Register (IPR). The GrpReq inputs are then masked by the mask bits from the
CPU status register. Any interrupt group that has a pending interrupt of a prior ity level that is not
masked by the CPU status register, gets its corresponding ValReq line asserted.
Masking of the interrup t requests is done based on five interr upt mask bits of the CPU status
register, namely Interrupt Level 3 Mask (I3M) to Interrupt Level 0 Mask (I0M), and Global Inter-
rupt Mask (GM). An interrupt request is masked if either the GM or the corresponding interrupt
level mask bit is set.
The Prioritizer hardware uses the ValReq lines and the INTLEVEL field in the IPRs to select the
pending interrupt of the highest priority. If an NMI interrupt request is pending, it automatically
gets the highest priority of any pending interrupt. If several interrupt groups of the highest pend-
ing interrupt level have pending interrupts, the interrupt group with the lowest number is
selected.
The INTLEVEL and handler autovector offset (AUTOVECTOR) of the selected interrupt are
transmitted to the CPU for interrupt handling and context switching. The CPU does not need to
know which interrupt is requesting handling, but only the level and the offset o f the handler
address. The IRR registers contain the interrupt request lines of the groups and can be read via
user interface registers for checking which interrupts of the group are actually active.
The delay through the INT C from the p eripheral interr upt r equest is set until the interrup t req uest
to the CPU is set is three cycles of CLK_SYNC.
10.5.1 Non-Maskable Interrupts
A NMI request has priority over all other interrupt requests. NMI has a dedicated exception vec-
tor address defined by the AVR32 architecture, so AUTOVECTOR is undefined when
INTLEVEL indicates that an NMI is pending.
10.5.2 CPU ResponseWhen the C PU receives an interrupt request it checks if any other exceptions are pending. If no
exceptions of higher priority are pending, interrupt handling is initiated. When initiating interrupt
handling, the corre sponding interrupt ma sk bit is set automatically for this and lower levels in sta-
tus register. E.g, if an interrupt of level 3 is approved for handling, the interrupt mask bits I3M,
I2M, I1M, and I0M are set in status register. If an interrupt of level 1 is approved, the masking
bits I1M and I0M are set in status register. The handler address is calculated by logical OR of
the AUTOVECTOR to the CPU system register Exception Vector Base Address (EVBA). The
CPU will then jump to the calculated address and start executing the interrupt handler.
Setting the interrupt mask bits prevents the interrupts from the same and lower levels to be
passed through the interrupt controller. Setting of the same level mask bit prevents also multiple
requests of the same interrupt to happen.
It is the responsibility of the handler software to clear the interrupt request that caused the inter-
rupt before re turning fro m the interrup t handler. If the conditions that caused the int errupt are not
cleared, the interr upt request remains active.
10.5.3 Clearing an Interrupt Request
Clearing of the interrupt request is done by writing to registers in the corresponding peripheral
module, which then clears the corresponding NMIREQ/IREQ signal.
The recommended way of clearing an interrupt request is a store operation to the controlling
peripheral register, followed by a dummy load operation from the same register. This causes a
99
32072H–AVR32–10/2012
AT32UC3A3
pipeline stall, which prevents the inter rupt from accidentally re-triggering in case th e handler is
exited and the interrupt mask is cleared before the interrupt request is cleared.
100
32072H–AVR32–10/2012
AT32UC3A3
10.6 User Interface
Table 10-1. INTC Register Memory Map
Offset Register Register Name Access Reset
0x000 Interrupt Priority Register 0 IPR0 Read/W rite 0x00000000
0x004 Interrupt Priority Register 1 IPR1 Read/W rite 0x00000000
... ... ... ... ...
0x0FC Interrupt Priority Register 63 IPR63 Read /Write 0x00000000
0x100 Interrupt Request Register 0 IRR0 Read-only N/A
0x104 Interrupt Request Register 1 IRR1 Read-only N/A
... ... ... ... ...
0x1FC Interrupt Request Register 63 IRR63 Read-only N/A
0x200 Interrupt Cause Register 3 ICR3 Read-only N/A
0x204 Interrupt Cause Register 2 ICR2 Read-only N/A
0x208 Interrupt Cause Register 1 ICR1 Read-only N/A
0x20C Interrupt Cause Register 0 ICR0 Read-only N/A
101
32072H–AVR32–10/2012
AT32UC3A3
10.6.1 Interrupt Priority Registers
Name: IPR0...IPR63
Access Type: Read/Write
Offset: 0x000 - 0x0FC
Reset Value: 0x00000000
• INTLEVEL: Interrupt Level
Indicates the EVBA-relative offset of the interrupt handler of the corresponding group:
00: INT0: Lowest prior ity
01: INT1
10: INT2
11: INT3: Highest priority
• AUTOVECTOR: Autovector Address
Handler offset is used to give the address of the interrupt handler. The least significa nt bit should be written to zero to give
halfword alignment.
31 30 29 28 27 26 25 24
INTLEVEL ------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
- - AUTOVECTOR[13:8]
76543210
AUTOVECTOR[7:0]
102
32072H–AVR32–10/2012
AT32UC3A3
10.6.2 Interrupt Request Registers
Name: IRR0...IRR63
Access Type: Read-only
Offset: 0x0FF - 0x1FC
Reset Value: N/A
• IRR: Interrupt Request line
This bit is cleared when no interrupt request is pendi ng on this input request line.
This bit is set when an interrupt request is pending on this input request line.
The are 64 IRRs, one for each group. Each IRR has 32 bits, one for each possible interrupt request, f or a total of 2048 possible
input lines. The IRRs are read by the software interrupt handler in order to determine which interrupt request is pending. The
IRRs are sampled continuously, and are read-only.
31 30 29 28 27 26 25 24
IRR[32*x+31] IRR[32*x+30] IRR[32*x+29] IRR[32*x+28] IRR[32*x+27] IRR[32*x+26] IRR[32*x+25] IRR[32*x+24]
23 22 21 20 19 18 17 16
IRR[32*x+23] IRR[32*x+22] IRR[32*x+21] IRR[32*x+20] IRR[32*x+19] IRR[32*x+18] IRR[32*x+17] IRR[32*x+16]
15 14 13 12 11 10 9 8
IRR[32*x+15] IRR[32*x+14] IRR[32*x+13] IRR[32*x+12] IRR[32*x+11] IRR[32*x+10] IRR[32*x+9] IRR[32*x+8]
76543210
IRR[32*x+7] IRR[32*x+6] IRR[32*x+5] IRR[32*x+4] IRR[32*x+3] IRR[32*x+2] IRR[32*x+1] IRR[32*x+0]
103
32072H–AVR32–10/2012
AT32UC3A3
10.6.3 Interrupt Cause Registers
Name: ICR0...ICR3
Access Type: Read-only
Offset: 0x200 - 0x20C
Reset Value: N/A
• CAUSE: Interrupt Group Causing Interrupt of Priority n
ICRn identifies the group with the highest priority that has a pending interrupt of level n. This value is only defined when at least
one interrupt of level n is pending.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
-- CAUSE
104
32072H–AVR32–10/2012
AT32UC3A3
10.7 Interrupt Request Signal Map
The various modules may out put Inte rrup t request signals. These sig nals are route d to the Inte r-
rupt Controller (INTC), described in a later chapter. The Interrupt Controller supports up to 64
groups of interr upt requests. Each gr oup can have up to 32 interrupt request signals. All inter rupt
signals in the same group share the same autovector address and priority level. Refer to the
documentation for the individual submodules for a description of the semantics of the different
interrupt requests.
The interrupt request signals are connected to the INTC as follows.
Table 10-2. Interrupt Re qu est Signal Map
Group Line Module Signal
0 0 CPU with optional MPU and optional OCD SYSREG
COMPARE
1
0 External Interrupt Controller EIC 0
1 External Interrupt Controller EIC 1
2 External Interrupt Controller EIC 2
3 External Interrupt Controller EIC 3
4 External Interrupt Controller EIC 4
5 External Interrupt Controller EIC 5
6 External Interrupt Controller EIC 6
7 External Interrupt Controller EIC 7
8 Real Time Counter RTC
9 Power Manager PM
2
0 General Purpose Input/Output Controller GPIO 0
1 General Purpose Input/Output Controller GPIO 1
2 General Purpose Input/Output Controller GPIO 2
3 General Purpose Input/Output Controller GPIO 3
4 General Purpose Input/Output Controller GPIO 4
5 General Purpose Input/Output Controller GPIO 5
6 General Purpose Input/Output Controller GPIO 6
7 General Purpose Input/Output Controller GPIO 7
8 General Purpose Input/Output Controller GPIO 8
9 General Purpose Input/Output Controller GPIO 9
10 General Purpose Input/Output Controller GPIO 10
11 General Purpose Input/Output Controller GPIO 11
12 General Purpose Input/Output Controller GPIO 12
13 General Purpose Input/Output Controller GPIO 13
105
32072H–AVR32–10/2012
AT32UC3A3
3
0 Peripheral DMA Controller PDCA 0
1 Peripheral DMA Controller PDCA 1
2 Peripheral DMA Controller PDCA 2
3 Peripheral DMA Controller PDCA 3
4 Peripheral DMA Controller PDCA 4
5 Peripheral DMA Controller PDCA 5
6 Peripheral DMA Controller PDCA 6
7 Peripheral DMA Controller PDCA 7
4 0 Flash Controller FLASHC
50
Universal Synchronous/Asynchronous
Receiver/Transmitter USART0
60
Universal Synchronous/Asynchronous
Receiver/Transmitter USART1
70
Universal Synchronous/Asynchronous
Receiver/Transmitter USART2
80
Universal Synchronous/Asynchronous
Receiver/Transmitter USART3
9 0 Serial Peripheral Interface SPI0
10 0 Serial Peripheral Interface SPI1
11 0 Two-wire Master Interface TWIM0
12 0 Two-wire Master Interface TWIM1
13 0 Synchro nous Serial Controller SSC
14
0 Timer/Counter TC00
1 Timer/Counter TC01
2 Timer/Counter TC02
15 0 Analog to Digital Converter ADC
16
0 Timer/Counter TC10
1 Timer/Counter TC11
2 Timer/Counter TC12
17 0 USB 2.0 OTG Interface USBB
18 0 SDRAM Controller SDRAMC
19 0 Audio Bitstream DAC ABDAC
20 0 Mulitmedia Card Interface MCI
21 0 A dvanced Encryption Standard AES
Table 10-2. Interrupt Re qu est Signal Map
106
32072H–AVR32–10/2012
AT32UC3A3
22
0 DMA Controller DMACA BLOCK
1 DMA Controller DMACA DSTT
2 DMA Controller DMACA ERR
3 DMA Controller DMACA SRCT
4 DMA Controller DMACA TFR
26 0 Memory Stick Interface MSI
27 0 Two-wire Slave Interface TWIS0
28 0 Two-wire Slave Interface TWIS1
29 0 Error code corrector Hamming and Reed
Solomon ECCHRS
Table 10-2. Interrupt Re qu est Signal Map
107
32072H–AVR32–10/2012
AT32UC3A3
11. External Interrupt Controller (EIC)
Rev: 2.4.0.0
11.1 Features •Dedicated interrupt request for each interrupt
•Individually maskable interrupts
•Interrupt on rising or falling edge
•Interrupt on high or low level
•Asynchronous interrupts for sleep modes without clock
•Filtering of interrupt lines
•Maskable NMI interrupt
•Ke ypad scan support
11.2 Overview The External Interrupt Controller (EIC) allows pins to be configured as external interrupts. Each
external interrupt has its own interrupt request and can be individually masked. Each external
interrupt can generate an interrupt on rising or falling edge, or high or low level. Every interrupt
input has a configurable filter to remove spikes from the interrupt source. Every interrupt pin can
also be configured to be asyn chro nous in order to wa ke up t he part fr om sleep mod es where the
CLK_SYNC clock has been disabled.
A Non-Maskable Interrupt (NMI) is also supported. Th is has the same properties as the other
external interrupts, but is connected to the NMI request of the CPU, enabling it to interrupt any
other interrupt mode.
The EIC can wake up the part from sleep modes witho ut triggering an interrupt. In this mode,
code execution starts from the instruction following the sleep instruction.
The External Interrupt Controller has support for keypad scanning for keypads laid out in rows
and columns. Columns are driven by a separate set of scanning outputs, while rows are sensed
by the external inte rrupt lines. The pressed key will trigger a n interrupt, which can be iden tified
through the user registers of the module.
108
32072H–AVR32–10/2012
AT32UC3A3
11.3 Block Diagram
Figure 11-1. EIC Block Diagram
11.4 I/O Lines Description
11.5 Product Dependencies
In order to use t his modu le, othe r p arts o f th e syst em must be conf igu red cor re ctly, as de scr ibed
below.
11.5.1 I/O Lines The external interrupt pins (EXTINTn and NMI) are multiplexed with I/O lines. To generate an
external interrupt from an external source the source pin must be configured as an input pins by
the I/O Controlle r. It is al so possible t o trig ger t he in terr up t by drivin g these pins f rom r egister s in
the I/O Controller, or another peripheral output connected to the same pin.
11.5.2 Power Management
All interrupts are available in all sleep modes as long as the EIC modu le is powered. However, in
sleep modes where CLK_SYNC is stopped, the interrupt must be configured to asynchronous
mode.
Edge/Level
Detector
Mask IR Q n
EXTINTn
NMI
IN T n
LEVEL
MODE
EDGE
IE R
ID R
IC R
CTRL
IS R IM R
Filter
FILTER
Polarity
control
LEVEL
MODE
EDGE
Asynchronus
detector
EIC_W AKE
Enable
EN
DIS
CTRL
CLK_SYNC
Wake
detect
ASYNC
Prescaler Shifter
PRESC EN
SCAN
PIN
SCANm
CLK_RCSYS
Table 11-1. I/O Lines Descrip tion
Pin Name Pin Descripti on Type
NMI Non-Maskable Interrupt Input
EXTINTn External Interrupt Input
SCANm Keypad scan pin m Output
109
32072H–AVR32–10/2012
AT32UC3A3
11.5.3 Clocks The clock for the EIC bus interf ace (CLK_EIC ) is gen erated by the Power Manag er. This clock is
enabled at reset, and can be disable d in the Power Manager.
The filter and synchronous ed ge/level detector runs on a clock which is sto pped in any of the
sleep modes where the system RC oscillator is not running. This clock is referred to as
CLK_SYNC. Refer to the Module Configuration section at th e end of this chapter for details.
The Keypad scan function operates on the system RC oscillator clock CLK_RCSYS.
11.5.4 Interrupts The external interrupt request lines are connected to the interrupt controller. Using the external
interrupts requires the interrupt controller to be programmed first.
Using the Non-Maskab le Interrupt does not require the interrupt controller to be programmed.
11.5.5 Debug Operation
The EIC is frozen during debug o peration, unless the OCD system keeps p eripherals running
during debug ope ration.
11.6 Functional Description
11.6.1 Externa l Inte rrupts
The external interru pts ar e not enab led by defa ult , allowing t he prop er interr upt vect ors t o be set
up by the CPU before the inte rru p ts ar e en a ble d.
Each external interrupt INTn can be configured to produce an interrupt on rising or falling edge,
or high or low level. External interrupts are configured by the MODE, EDGE, and LEVEL regis-
ters. Each interrupt n has a bit INTn in each of these registers. Writing a zero to the INTn bit in
the MODE register enables edge triggered interrupts, while writing a one to the bit enables level
triggered interrupts.
If INTn is configured as an edge triggered interrupt, writing a zero to the INTn bit in the EDGE
register will cause the interrupt to be triggered on a falling edge on EXTINTn, while writing a one
to the bit will cause the interrupt to be triggered on a rising edge on EXTINTn.
If INTn is configured as a level triggered interrupt, writing a zero to the INTn bit in the LEVEL
register will cause the interrupt to be triggered on a low level on EXTINTn, while writing a one to
the bit will cause the interrupt to be triggered on a high level on EXTINTn.
Each interrupt has a corresponding bit in each of the interrupt control and status registers. Writ-
ing a one to the INTn bit in the Interrupt Enable Register (IER) enables the external interrupt
from pin EXTINTn to propagate from the EIC to the interrupt controller, while writing a one to
INTn bit in the Interrupt Disable Register (IDR) disables this propagation. The Interrupt Mask
Register (IMR) can be read to check which interrupts are enabled. When an interrupt triggers,
the corresponding bit in the Interrupt Status Register (ISR) will be set. This bit remains set until a
one is written to the corresponding bit in the Interrupt Clear Register (ICR) or the interrupt is
disabled.
Writing a one to the INTn bit in the Enable Register (EN) enables the external interrupt on pin
EXTINTn, while writing a one to INTn bit in the Disable Register (DIS) disables the external inter-
rupt. The Control Register (CTRL) can be read to check which interrupts are enabled. If a bit in
the CTRL register is set, but the corresponding bit in IMR is not set, an interrupt will not propa-
110
32072H–AVR32–10/2012
AT32UC3A3
gate to the interrupt controller. However, the corresponding bit in ISR will be set, and
EIC_WAKE will be set.
If the CTRL.INTn bit is zero, then the correspondin g bit in ISR will always be zero. Disabling an
external interrupt by writing to the DIS.INTn bit will clear the corresponding bit in ISR.
11.6.2 Synchronization and Filtering of External Interrupts
In synchronous mode the pin value of the EXTINTn pin is synchronized to CLK_ SYNC, so
spikes shorter than one CLK_SYNC cycle are not guaranteed to produce an interrupt. The syn-
chronization of the EXTINTn to CLK_SYNC will delay the propagation of the interrupt to the
interrupt controller by two cycles of CLK_SYNC, see Figure 11-2 on page 110 and Figure 11-3
on page 110 for examples (FILTER off).
It is also possible to apply a filter on EXTINTn by wr iting a one to I NTn bit in the FILTER regi ster.
This filter is a majority vote r, if the co ndition for an interrup t is true fo r more t han one of the latest
three cycles of CLK_SYNC the interrupt will be set. This will additionally delay the propagation of
the interrupt to the interrupt controller by one or two cycles of CLK_SYNC, see Figure 11-2 on
page 110 an d Figure 11-3 on page 110 for examples (FILTER on).
Figure 11-2. Timing Diagram, Synchronous Interrupts, High Level or Rising Edge
Figure 11-3. Timing Diagram, Synchronous Interrupts, Low Level or Falling Edge
EXTINTn/NMI
CLK_SYNC
ISR.INTn:
FILTER off
ISR.INTn:
FILTER on
EXTINTn/NMI
CLK_SYNC
ISR.INTn:
FILTER off
ISR.INTn:
FILTER on
111
32072H–AVR32–10/2012
AT32UC3A3
11.6.3 Non-Maskable Interrupt
The NMI supports the same features as the external interrupts, and is accessed through the
same registers. The description in Section 11.6.1 should be followed, accessing the NMI bit
instead of the INTn bits.
The NMI is non-maskable within the CPU in the sense that it can interrupt any other exe cution
mode. Still, as for the other external interrupts, the actual NMI input can be enabled and disabled
by accessing the registers in t he EIC.
11.6.4 Asynchronous Interrupts
Each external interrupt can be made asynchronous by writing a one to INTn in the ASYNC reg-
ister. This will route the interrupt signal through the asynchronous path of the mod ule. All edge
interrupts will be interpreted as level interrupts and the f ilter is disabled. If an interrupt is config-
ured as edge triggered interrupt in asynchronous mode, a zero in EDGE.INTn will be interpreted
as low level, and a one in EDGE.INTn will be interpreted as high level.
EIC_WAKE will be set immediately after the source triggers the interrupt, while the correspond-
ing bit in ISR and the interrupt to the interrupt controller will be set on the next rising edge of
CLK_SYNC. Please refere to Figure 11-4 on page 111 for details.
When CLK_SYNC is stopped only asynchronous interrupts remain active , and any short spike
on this interrupt will wake up the device. EIC_WAKE will restart CLK_SYNC and ISR will be
updated on the fi rst rising edge of CLK_SYNC.
Figure 11-4. Timing Diagram, Asynchronous Interrupts
11.6.5 Wakeup The external interrupts can be used to wake up the part from sleep modes. The wakeup can be
interpreted in two ways. If the corresponding bit in IMR is one, then the execution starts at the
interrupt handler for this interrupt. If the bit in IMR is zero, then the execution starts from the next
instruction after the sleep instruction.
EXTINTn/NMI
CLK_SYNC
ISR.INTn:
rising EDGE or high
LEVEL
EIC_WAKE:
rising EDGE or high
LEVEL
EXTINTn/NMI
CLK_SYNC
ISR.INTn:
rising EDGE or high
LEVEL
EIC_WAKE:
rising EDGE or high
LEVEL
112
32072H–AVR32–10/2012
AT32UC3A3
11.6.6 Keypad scan support
The External Interrupt Controller also includes support for keypad scanning. The keypad scan
feature is compatible with keypads organized as rows and columns, where a row is shorted
against a column when a key is pressed.
The rows should be connected to t he external inte rrupt pins with pull-ups enabled in the I/O Co n-
troller. These external interrupts should be enabled as low level or falling edge interrupts. The
columns should be connected to the available scan pins. The I/O Controller must be configured
to let the requ ired scan pins be controlle d by th e EIC. Unu sed externa l inte rrupt o r scan pins can
be left controlled by the I/O Controller or other peripherals.
The Keypad Scan function is enabled by writing SCAN.EN to 1, which starts the keypad scan
counter. The SCAN outputs are tri-stated, except SCAN[0], which is driven to zero. After
2(SCAN.PRESC+1) RC clock cycles this pattern is left shifted, so that SCAN[1] is driven to zero while
the other outputs are tri-stated. This sequence repeats infinitely, wrapping from the most signifi-
cant SCAN pin to SCAN[0].
When a key is pressed, the pulled-up row is driven to zero by the column, and an external inter-
rupt triggers. The scannin g stops, and the software can then identify the key pressed b y the
interrupt stat us register and the SCAN.PINS value.
The scanning stops whenever there is an active interrupt request from the EIC to the CPU.
When the CPU clears the interrupt flags, scanning resumes.
113
32072H–AVR32–10/2012
AT32UC3A3
11.7 User Interface
Table 11-2. EIC Register Memory Map
Offset Register Register Name Access Reset
0x000 Inte rrupt Enable Register IER Write-only 0x00000000
0x004 Interrupt Disa ble Register IDR Write-only 0x00000000
0x008 Interrupt Mask Register IMR Read-only 0x00000000
0x00C Interrupt Status Register ISR Read-only 0x000 00000
0x010 Interrupt Clear Register ICR Write-only 0x00000000
0x014 Mode Register MODE Read/Write 0x00000000
0x018 Edge Register EDGE Read/Write 0x000 00000
0x01C Level Register LEVEL Read/Write 0x00000000
0x020 Filter Register FILTER Read/Write 0x00000000
0x024 Test Register TEST Read/Wri te 0x00000000
0x028 Asynchronous Register ASYNC Read/Write 0x00000000
0x2C Scan Register SCAN Read/W rite 0x00000000
0x030 Enable Register EN Write-only 0x00000000
0x034 Disable Register DIS Write-only 0x00000000
0x038 Control Register CTRL Read-only 0x00000000
114
32072H–AVR32–10/2012
AT32UC3A3
11.7.1 Interrupt Enable Register
Name: IER
Access Type: Write-only
Offset: 0x000
Reset Value: 0x00000000
•INTn: External Interrupt n
Writing a zero to this bit has no effect.
Writing a one to this bit will set the corresponding bit in IMR.
• NMI: Non-Maskable Interrupt
Writing a zero to this bit has no effect.
Writing a one to this bit will set the corresponding bit in IMR.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
-------NMI
76543210
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
115
32072H–AVR32–10/2012
AT32UC3A3
11.7.2 Interrupt Disable Register
Name: IDR
Access Type: Write-only
Offset: 0x004
Reset Value: 0x00000000
•INTn: External Interrupt n
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the corresponding bit in IMR.
• NMI: Non-Maskable Interrupt
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the corresponding bit in IMR.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
-------NMI
76543210
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
116
32072H–AVR32–10/2012
AT32UC3A3
11.7.3 Interrupt Mask Register
Name: IMR
Access Type: Read-only
Offset: 0x008
Reset Value: 0x00000000
•INTn: External Interrupt n
0: The corresponding interr upt is disabled.
1: The corresponding interrupt is enabled.
This bit is cleared when the corresponding bit in IDR is written to one.
This bit is set when the corresponding bit in IER is wri tten to one.
• NMI: Non-Maskable Interrupt
0: The Non-Maskable Interrupt is disabled.
1: The Non-Maskable Interrupt is enabled.
This bit is cleared when the corresponding bit in IDR is written to one.
This bit is set when the corresponding bit in IER is wri tten to one.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
-------NMI
76543210
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
117
32072H–AVR32–10/2012
AT32UC3A3
11.7.4 Interrupt Status Register
Name: ISR
Access Type: Read-only
Offset: 0x00C
Reset Value: 0x00000000
•INTn: External Interrupt n
0: An interrupt event has not occurred
1: An interrupt event has occurred
This bit is cleared by writing a one to the corresponding bit in ICR.
• NMI: Non-Maskable Interrupt
0: An interrupt event has not occurred
1: An interrupt event has occurred
This bit is cleared by writing a one to the corresponding bit in ICR.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
-------NMI
76543210
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
118
32072H–AVR32–10/2012
AT32UC3A3
11.7.5 Interrupt Clear Register
Name: ICR
Access Type: Write-only
Offset: 0x010
Reset Value: 0x00000000
•INTn: External Interrupt n
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the corresponding bit in ISR.
• NMI: Non-Maskable Interrupt
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the corresponding bit in ISR.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
-------NMI
76543210
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
119
32072H–AVR32–10/2012
AT32UC3A3
11.7.6 Mode Register
Name: MODE
Access Type: Read/Write
Offset: 0x014
Reset Value: 0x00000000
•INTn: External Interrupt n
0: The external interrupt is edge triggered.
1: The external interrupt is level triggered.
• NMI: Non-Maskable Interrupt
0: The Non-Maskable Interrupt is edge triggered.
1: The Non-Maskable Interrupt is level triggered.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
-------NMI
76543210
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
120
32072H–AVR32–10/2012
AT32UC3A3
11.7.7 Edge Register
Name: EDGE
Access Type: Read/Write
Offset: 0x018
Reset Value: 0x00000000
•INTn: External Interrupt n
0: The external interrupt triggers on falling edge.
1: The external interrupt triggers on rising edge.
• NMI: Non-Maskable Interrupt
0: The Non-Maskable Interrupt triggers on falling edge.
1: The Non-Maskable Interrupt triggers on rising edge.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
-------NMI
76543210
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
121
32072H–AVR32–10/2012
AT32UC3A3
11.7.8 Level Register
Name: LEVEL
Access Type: Read/Write
Offset: 0x01C
Reset Value: 0x00000000
•INTn: External Interrupt n
0: The external interrupt triggers on low level.
1: The external interrupt triggers on high level.
• NMI: Non-Maskable Interrupt
0: The Non-Maskable Interrupt triggers on low level.
1: The Non-Maskable Interrupt triggers on high level.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
-------NMI
76543210
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
122
32072H–AVR32–10/2012
AT32UC3A3
11.7.9 Filter Regist er
Name: FILTER
Access Type: Read/Write
Offset: 0x020
Reset Value: 0x00000000
•INTn: External Interrupt n
0: The external interrupt is not filtered.
1: The external interrupt is filtered.
• NMI: Non-Maskable Interrupt
0: The Non-Maskable Interrupt is not filtered.
1: The Non-Maskable Interrupt is filtered.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
-------NMI
76543210
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
123
32072H–AVR32–10/2012
AT32UC3A3
11.7.10 Test Regist er
Name: TEST
Access Type: Read/Write
Offset: 0x024
Reset Value: 0x00000000
• TESTEN: Test Enable
0: This bit disables external interrupt test mode.
1: This bit enables external interrupt test mode.
•INTn: External Interrupt n
If TESTEN is 1, the value written to this bit will be the value to the interrupt detector an d the value on the pad will be ignored.
• NMI: Non-Maskable Interrupt
If TESTEN is 1, the value written to this bit will be the value to the interrupt detector an d the value on the pad will be ignored.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
-------NMI
76543210
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
124
32072H–AVR32–10/2012
AT32UC3A3
11.7.11 Asynchronous Register
Name: ASYNC
Access Type: Read/Write
Offset: 0x028
Reset Value: 0x00000000
•INTn: External Interrupt n
0: The external interrupt is synchronized to CLK_SYNC.
1: The external interrupt is asynchronous.
• NMI: Non-Maskable Interrupt
0: The Non-Maskable Interrupt is synchronized to CLK_SYNC
1: The Non-Maskable Interrupt is asynchronous.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
-------NMI
76543210
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
125
32072H–AVR32–10/2012
AT32UC3A3
11.7.12 Scan Register
Name: SCAN
Access Type: Read/Write
Offset: 0x2C
Reset Value: 0x0000000
•EN 0: Keypad scanning is disabled
1: Keypad scanning is enabled
•PRESC
Prescale select f or the keypad scan rate:
Scan rate = 2(SCAN.PRESC+1) TRC
The RC clock period can be found in the Electrical Characteristics section.
•PIN The index of the currently active scan pi n . Writing to thi s bi tfi e l d ha s no effect.
31 30 29 28 27 26 25 24
- - - - - PIN[2:0]
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
- - - PRESC[4:0]
76543210
-------EN
126
32072H–AVR32–10/2012
AT32UC3A3
11.7.13 Enable Re gister
Name: EN
Access Type: Write-only
Offset: 0x030
Reset Value: 0x00000000
•INTn: External Interrupt n
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the corresponding external interrupt.
• NMI: Non-Maskable Interrupt
Writing a zero to this bit has no effect.
Writing a one to this bit will enable the Non-Maskable Interrupt.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
-------NMI
76543210
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
127
32072H–AVR32–10/2012
AT32UC3A3
11.7.14 Disable Register
Name: DIS
Access Type: Write-only
Offset: 0x034
Reset Value: 0x00000000
•INTn: External Interrupt n
Writing a zero to this bit has no effect.
Writing a one to this bit will disable the corresponding external interrupt.
• NMI: Non-Maskable Interrupt
Writing a zero to this bit has no effect.
Writing a one to this bit will disable the Non-Maskable Interrupt.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
-------NMI
76543210
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
128
32072H–AVR32–10/2012
AT32UC3A3
11.7.15 Control Register
Name: CTRL
Access Type: Read-only
Offset: 0x038
Reset Value: 0x00000000
•INTn: External Interrupt n
0: The corresponding external interrupt is disabled.
1: The corresponding external interrupt is enabled.
• NMI: Non-Maskable Interrupt
0: The Non-Maskable Interrupt is disabled.
1: The Non-Maskable Interrupt is enabled.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
-------NMI
76543210
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
129
32072H–AVR32–10/2012
AT32UC3A3
11.8 Module Configuration
The specific configuration for each EIC instance is listed in the following tables.The m odule bus
clocks listed here are connected to the system bus clocks. Please refer to the Power Manager
chapter for details.
Table 11-3. Module Configuration
Feature EIC
Number of external interrupts, including NMI 9
Table 11-4. Module Clock Name
Module Name Clock Name
EIC CLK_EIC
130
32072H–AVR32–10/2012
AT32UC3A3
12. Flash Controller (FLASHC)
Rev: 2.2.1.3
12.1 Features •Controls flash block with dual read ports allowing staggered reads.
•Supports 0 and 1 wait state bus access.
•Allows interleaved burst reads for systems with one wait sta t e, outp utti ng one 32-bit word per
clock cycle.
•32-bit HSB interface for reads from flash array and writes to page buffer.
•32-bit PB interface for issuing commands to and configuration of the controller.
•16 loc k bits, each protecting a region consistin g of (to tal n umber of pages in the flash block / 16)
pages.
•Regions can be individually pr otected or unprotected.
•Additional protection of the Boot Loader pages.
•Supports reads and writes of general-purpose NVM bits.
•Supports reads and writes of additional NVM pages.
•Supports device protection through a security bit.
•Dedicated command for chip-erase, first erasing all on-chip volatile memories before erasing
flash and clearing security bit.
•Interface to Power Manage r for power-down of flash-blocks in sleep mode.
•
12.2 Overview The flash controller (None) interfaces a flash block with the 32-bit internal HSB bus. Perfor-
mance for uncached systems with high clock-frequency and one wait state is increased by
placing words with sequential addresses in alternating flash subblocks. Having one read inter-
face per subblock allows them to be read in par allel. While da ta fro m one flash subblo ck is being
output on the bus, the sequential address is being read from the other flash subblock and will be
ready in the next clock cycle.
The controller also mana ges the programming, er asing, locking and unlocking sequence s with
dedicated commands.
12.3 Product dependencies
12.3.1 Power Manager
The FLASHC has two bus clocks connected: One High speed bus clock (CLK_FLASHC_HSB)
and one Peripheral bus clock (CLK_FLASHC_PB). These clocks are ge nerated by the Power
manager. Both clocks are turned on by default, but the user has to ensure that
CLK_FLASHC_HSB is not turned off before reading the flash or writing the pagebuffer and that
CLK_FLASHC_PB is not turned o f before accessing the FLASHC configur ation and control
registers.
12.3.2 Interrupt Controller
The FLASHC interrupt lin es are connected to internal sour ces of the interrupt controller. Using
FLASHC interrutps requires the interrupt controller to be programmed fi rst.
131
32072H–AVR32–10/2012
AT32UC3A3
12.4 Functional description
12.4.1 Bus interfacesThe None has two bus interfaces, one High-Speed Bus (HSB) interface for reads from the flash
array and writes to the page buffer, and one Per ipheral Bus (PB) interface for wr iting commands
and control to and reading status from the controller.
12.4.2 Memory organization
To maximize performance for high clock-frequency systems, None interfaces to a flash block
with two read por ts. The flash block has several parameters, given by the design of the flash
bl ock. Refer to the “Memories” chapter for t he device-specific values of the parameters.
•p pages (FLASH_P)
•w words in each page and in the page buffer (FLASH_W)
•pw words in total (FLASH_PW)
•f general-purpose fuse bits (FLASH_F)
• 1 security fuse bit
• 1 User Page
12.4.3 User page The User pag e is an additional page, outside the regular flash array, that can be used to store
various data, like calibration data and serial numbers. This page is not erased by regular chip
erase. The User pa ge can on ly be written and er ased b y p roprietary commands. Read accesses
to the User page is performed just as any othe r read access to the flash. Th e address map of the
User page is given in Figure 12-1.
12.4.4 Read oper at ions
The None provides two different read modes:
• 0 wait state (0ws) for clock freque ncies < (access time of the flash plus the bus delay)
• 1 wait state (1ws) for clock freque ncies < (access time of the flash plus the bus delay)/2
Higher clock frequencies that would require more wait states are not supported by the flash
controller.
The programmer can select t he wait states requi red by writing to the FWS field in the Flash Co n-
trol Register (FCR). It is the responsibility of the programmer to select a number of wait states
compatible with the clock frequency and timing characteristics of the flash block.
In 0ws mode, only one of the two flash read ports is accessed. The other flash read port is idle.
In 1ws mode, both flash read ports are active. One read port reading the addressed word, and
the other rea din g th e ne xt se qu en tia l w or d.
If the clock frequency allows, the user should use 0ws mode, because this gives the lowest
power consumption for low-frequency systems as only one flash read port is read. Using 1ws
mode has a power/performance ratio approaching 0ws mode as the clock frequency
approaches twice the max freque ncy of 0ws mode. Using two flash read ports use twice the
power, but also gi ve twice the performance.
132
32072H–AVR32–10/2012
AT32UC3A3
The flash controller sup ports flash blocks wit h up to 2^21 word ad dresses, as di splayed in Figure
12-1. Reading the memory space between address pw and 2^21-1 returns an undefined result.
The User page is perman ently mapped to word address 2^21.
Figure 12-1. Memory map for the Flash memories
Figure 12-2.
12.4.5 High Speed Read Mode
The flash provides a High Speed Read Mode, offering slightly higher flash read speed at the
cost of higher power consumption. Two dedicated commands, High Speed Read Mode Enable
(HSEN) and High Speed Read Mode Disable (HSDIS) control the speed mode. When a High
Speed Read Mode command is detected, the FLASHC automatically inserts additional wait
states until it is ready for the next read in flash. After reset, the High Speed Mode is disabled,
and must be manually enabled if the user wants to.
Refer to the Electrical Characteristics chapter at the end of this datashe et for det ails on the max-
imum clock frequencies in Normal and High Speed Read Mode.
Table 12-1. User page addresses
Memory type Start address, byte sized Size
Main array 0 pw words = 4pw bytes
User 2^23 = 8388608 128 words = 512 bytes
0
pw-1
pw
2^21+128
UnusedFlash data array
Unused
User page
Flash with
extra page
2^21
All addresses are word addresses
133
32072H–AVR32–10/2012
AT32UC3A3
Figure 12-3. High Speed Mode
12.4.6 Quick Page Read
A dedicated command, Quick Page Read (QPR), is provided to read all words in an addressed
page. All bits in all words in this page are AND’ed together, returning a 1-bit result. This result is
placed in the Quick Page Read Result (QPRR) bit in Flash Status Register (FSR). The QPR
command is useful to check that a page is in an erased state. The QPR instruction is much
faster than performing the erased-page check using a regular software subroutine.
12.4.7 Write page buffer operations
The internal memory area reserved for the embedded flash can also be written through a write-
only page buffer. The page buffer is addresse d only by the address bits re quired to address w
words (since the page buffer is word addressable) and thus wrap around within the internal
memory area address space and appear to be repeated within it.
When writing to the page buffer, the PAGEN field in the FCMD register is updated with the page
number corresponding to page address of the latest word written into the page buffer.
The page buffer is also used for writes to the User page.
Write operations can be prevented by programming the Me mory Protection Unit of the CPU.
Writing 8-bit and 1 6-bit data to th e page buffe r is not allowed and may lead to unpr edictabl e data
corruption.
Page buffer writ e oper at i on s ar e pe rf or me d with 2.2 .0 wait sta te s.
Writing to the page buffer can only change page buffer bits from one to zero, ie writing
0xaaaaaaaa to a page buffer location that has the value 0x00000000, will not change the page
buffer value . The only way to change a bit f rom zero to one, is to rese t the entire page buffer with
the Clear Page Buffer command.
Frequency
Frequency limit
for 0 wait state
operation
Normal
High
Speed mode
1 wait state
0 wait state
134
32072H–AVR32–10/2012
AT32UC3A3
The page buffer is not automatically reset after a page write. The programmer should do this
manually by issuing the Clear Page Buffer flash command. This can be done after a page write,
or before the p age buffer is loaded with data to be stored to the flash page.
Example: Writing a word into word address 130 of a flash with 128 words in the page buffer.
PAGEN will be updated with the value 1, and the word will be written into word 2 in the page
buffer.
12.4.8 Writing words to a page that is not completely er ased
This can be used for EEPROM em ulation, i.e. writes with granularity of one word instead of an
entire page. Only words that are in an completely erased state (0xFFFFFFFF) can be changed.
The procedure is as follows:
1. Clear page buff er
2. Write to the page buffer the result of the logical bitwise AND operation between the
contents of t he flash page and the ne w dat a to write. O nly words that wer e in an er ased
state can be change d from the original page.
3. Write Page.
12.5 Flash commands
The None offers a command set to manage programming of the flash memory, locking an d
unlocking of regions, and full flash erasing. See chapter 12.8.3 for a complete list of commands.
To run a command, the field CMD of the Flash Command Register (FCMD) has to be written
with the command number. As soon as the FCMD register is written, the FRDY flag is automati-
cally cleared. Once the current command is com plete, the FRDY flag is automatically set. If an
interrupt has been enabled by setting the bit FRDY in FCR, the interrupt line of the flash control-
ler is activated. All flash commands except for Quick Page Read (QPR) will generate an interrupt
request upon completion if FRDY is set.
After a command has been written to FCMD, the programming alg orithm should wait until the
command has been executed before attempting to read instructions or data from the flash or
writing to the page buffer, as the flash w ill be bus y. The w aiting can be performed either by poll-
ing the Flash Sta tus Register (FSR) or by waiting for the flash ready in terrupt. The comman d
written to FCMD is initiated on the first clock cycle where the HSB bus interface in FLASHC is
IDLE. The u ser must m ake sure th at the ac cess patte rn to the F LASHC HSB int erface cont ains
an IDLE cyc le so that the c ommand is allo wed to start. M ake sure that no bus mast ers such as
DMA controllers are performing endless burst transfers from the flash. Also, make sure that the
CPU does not perform endless burst transfers from flash. This is done by letting the CPU enter
sleep mode after writing to F CMD, or by polling FSR for co mmand completion. This polling will
result in an access pattern with IDLE HSB cycles.
All the commands are protected by the same keyword, which has to be written in the eight high-
est bits of the FCMD register. Writing FCMD with data that does not cont ain the correct key
and/or with an invalid comma nd has n o eff ect on th e flash mem ory; ho wever , the PROGE f lag is
set in the Flash Status Register (FSR). This flag is automatically cleared by a read access to the
FSR register.
Writing a command to FCMD while another command is being executed has no effect on the
flash memory; however, the PROGE flag is set in the Flash Status Register (FSR). This flag is
automatically cleared by a read access to the FSR register.
135
32072H–AVR32–10/2012
AT32UC3A3
If the current command writes or erases a page in a locked region, or a page protected by the
BOOTPROT fuses, the command has no effect on the flash memory; however, the LOCKE flag
is set in the FSR register. This fl ag is automatically cleared by a read access to the FSR register.
12.5.1 Write/erase page operation
Flash technology requ ires that an erase must be done b efore pr ogra mming. The entir e flash can
be erased by an Erase All command. Alternatively, pages can be individually erased by the
Erase Page command.
The User page can be written and erased using the mechanisms descr ibed in this chapter.
After programming, the page can be locked to prevent miscellaneous write or erase sequences.
Locking is performed o n a per -region basis, so locking a region locks all pages inside t he regio n.
Additional protection is provided for the lowermost address space of the flash. This address
space is allocated for the Boot Loader, and is protected both by the lock bit(s) corresponding to
this address space, and the BOOTPROT[2:0] fuses.
Data to be written are stored in an internal buffer called page buffer. The page buffer contains w
words. The page buffer wraps around within the internal memory area address space and
appears to be repeated by the number of pages in it. Writing of 8-bit and 16-bit data to the page
buffer is not allowed and may lead to unpredictable data corruption.
Data must be wr itten to t he page buff er before t he progr amming command is writt en to the Fla sh
Command Register FCMD. The sequence is as follows:
• Reset the page buffer with the Clear Page Buffer command.
• Fill the page buffer with the desired contents, using only 32-bit access.
• Programming starts as soon as the programming key and the programming command are
written to the Flash Command Register. The PAGEN field in the Flash Command Register
(FCMD) must contain the addres s of the page to write. PAGEN is automatically updated
when writing to the page buffer, but can also be written to directly. The FRDY bit in the Flash
Status Register (FSR) is automatically cleared when the page write operation starts.
• When programming is completed, the bit FRDY in the Flash Status Register (FSR) is set. If
an interrupt was enabled by setting the bit FRDY in FCR, the interrupt line of the flash
controller is set.
Two errors can be detected in the FSR register after a programming sequence:
• Programming Error: A bad keyword and/or an invalid command have been written in the
FCMD register.
• Lock Error: The page to be programmed belongs to a locked region. A command must be
executed to unlock the corresponding region before programming can start.
12.5.2 Erase All operation
The entire memory is erased if the Erase All command (EA) is written to the F lash Command
Register (FCMD). Erase All erases all bits in the flash array. The User page is not erased. All
flash memory locations, the general-purpose fuse bits, and the security bit a re erased (reset to
0xFF) after an Erase All.
The EA command also ensures that all volatile memories, such as register file and RAMs, are
erased before the security bit is erased.
Erase All operation is allowed only if no regions are locked, and the BOOTPROT fuses are pro-
grammed with a region size of 0. Thus, if at least one region is locked, the bit LOCKE in FSR is
136
32072H–AVR32–10/2012
AT32UC3A3
set and the command is cancelled. If the bit LOCKE has been written to 1 in FCR, the interrupt
line rises.
When the command i s co mple te , t he bit FRDY bit in t he Flash Stat us Regi ste r (FSR) is set . I f an
interrupt has been enabled by setting the bit FRDY in FCR, the interrupt line of the flash control-
ler is set. Two errors can be detected in the FSR register after issuing the comm and:
• Programming Error: A bad keyword and/or an invalid command have been written in the
FCMD register.
• Loc k Error: At least one lock regi on to be erased is protected, or BOO TPRO T is diff erent from
0. The erase command has been refused and no page has been erased. A Clear Lock Bit
command must be executed previously to unlock the corresponding lock regions.
12.5.3 Region lock bits
The flash block has p pages, and these pages are grouped into 16 lock regions, each region
containing p/16 pages. Each region has a dedicated lock bit preventing writing and erasing
pages in the region. After production, the device may have some regions locked. These locked
regions are reserved for a boot or default ap plication. Locked regions can be unlocked to be
erased and then programmed with another application or other data.
To lock or unlock a region, the commands Lock Region Containing Page (LP) and Unlock
Region Containing Page (UP) are provided. Writing one of these commands, togethe r with the
number of the page whose region should be locked/unlocked, performs the desired operation.
One error can be det ected in the FSR register after issuin g the command:
• Programming Error: A bad keyword and/or an invalid command have been written in the
FCMD register.
The lock bits are implemented using the lowest 16 general-purpose fuse bits. This means that
lock bits can also be set/cleare d using the commands for writing/er asing general-purpose fuse
bits, see chapter 12.6. The general-purpose bit being in an erased (1) state means that the
region is unlocked.
The lowermost pages in the Flash can additionally be protected by the BOOTPROT fuses, see
Section 12.6.
12.6 General-purpose fuse bits
Each flash block has a n umber of g eneral-pur pose fuse bi ts that the applicat ion progra mmer can
use freely. The fuse bits can be written and erased using dedicated commands, and read
137
32072H–AVR32–10/2012
AT32UC3A3
through a dedicated Peripheral Bus address. Some of the general-purpose fuse bits are
reserved for special purposes, and should not be used for other functions.:
The BOOTPROT fuses protects the following address space for the Boot Loader:
Table 12-2. General-purpose fuses with special f unctions
General-
Purpose fuse
number Name Usage
15:0 LOCK Region lock bits.
16 EPFL
External Privileged F etch Lock. Used to prevent the CPU from
f etching instructions from external memories when in privileged
mode. This bit can only be changed when the security bit is
cleared. The address range corresponding to external
memories is device-specific, and not known to the flash
controller. This fuse bit is simply routed out of the CPU or bus
system, the flash controller does not treat this fuse in any
special way, except that it can not be altered when the security
bit is set.
If the security bit is set, only an external JTAG Chip Erase can
clear EPFL. No internal commands can alter EPFL if the
security bit is set.
When the fuse is erased (i.e. "1"), the CPU can execute
instructions fetched from external memories. When the fuse is
programmed (i.e. "0"), instructions can not be exe cu te d from
external memories.
19:17 BOOTPROT
Used to select one of eight different bootloader sizes. Pages
included in the bootloader area can not be erased or
programmed except by a JTAG chip erase. BOOTPROT can
only be changed when the security bit is cleared.
If the security bit is set, only an external JTAG Chip Erase can
clear BOOTPROT, and thereby allow the pages protected by
BOOTPROT to be programmed. No internal commands can
alter BOOTPROT or the pages protected by BOOTPROT if the
security bit is set.
Table 12-3. Boot Loader area specified by BOOTPROT
BOOTPROT P ages protected by
BOOTPROT Size of protected
memory
7None 0
60-1 1kByte
50-3 2kByte
40-7 4kByte
3 0-15 8kByte
2 0-31 16kByte
1 0-63 32kByte
0 0-127 64kByte
138
32072H–AVR32–10/2012
AT32UC3A3
To erase or write a general-purpose fuse bit, the commands Write General-Purpose Fuse Bit
(WGPB) and Erase General-Purpose Fuse Bit (EGPB) are provided. Writing one of these com-
mands, together with the number of the fuse to write/erase, performs the desired operation.
An entire General-Purpose Fuse byte can be written at a time by using the Program GP Fuse
Byte (PGPFB) instruction. A PGPFB to GP fuse byte 2 is not allowed if the flash is locked by the
security bit. The PFB command is issued with a parameter in the PAGEN field:
• PAGEN[2:0] - byte to write
• PAGEN[10:3] - Fuse va lue to write
All General-Purpose fuses can be erased by the Erase All G eneral-Purpose fuses (EAGP) com-
mand. An EAGP command is not allowed if the flash is locked by the security bit.
Two errors can be detected in the FSR register after issuing these commands:
• Programming Error: A bad keyword and/or an invalid command have been written in the
FCMD register.
• Lock Error: A write or erase of any of the special-function fuse bits in Table 12-3 was
attempted while the flash is locked by the security bit.
The lock bits are implemented using the lowest 16 general-purpose fuse bits. This means that
the 16 lowest general-purpose fuse bits can also be written/erased using the commands for
locking/unlocking regions, see Section 12 .5.3.
12.7 Security bit The security bit allows the entire chip to be locked fro m external JTAG or other debug access for
code security. The security bit can be written by a dedicated command, Set Security Bit (SSB).
Once set, the only way to clear the security bit is through the JTAG Chip Erase command.
Once the Security bit is set, the following Flash controller commands will be unavailable and
return a lock error if attempted:
• Write General-Purpose Fuse Bit (WGPB) to BOOTPROT or EPFL fuses
• Erase General-Pur pose Fuse Bit (EGPB) to BOOTPROT or EPFL fuses
• Program General-Purpose Fuse Byte (PGPFB) of fuse byte 2
• Erase All General-Purpose Fuses (EAGPF)
One error can be det ected in the FSR register after issuin g the command:
• Programming Error: A bad keyword and/or an invalid command have been written in the
FCMD register.
139
32072H–AVR32–10/2012
AT32UC3A3
12.8 User interface
12.8.1 Address map The following addresses are used by the None. All offsets are relative to the base address allo-
cated to the flash controller.
(*) The value of th e Lock bits is depe ndent of t heir progr ammed state. All ot her bits in FSR are 0.
All bits in FGPFR and FCFR are dependent on the programmed state of the fuses they map to.
Any bits in these registers not mapped to a fuse read 0.
Table 12-4. Flash controller register mapping
Offset Register Name Access Reset
state
0x0 Flash Con trol Register FCR R/W 0
0x4 Flash Command Register FCMD R/W 0
0x8 Flash Sta tus Register FSR R/W 0 (*)
0xc Flash General Purpose Fuse Register Hi FGPFRHI R NA (*)
0x10 Flash General Purpose Fuse Register Lo FGPFRLO R NA (*)
140
32072H–AVR32–10/2012
AT32UC3A3
12.8.2 Flash Control Register
Name: FCR
Access Type: Read/Write
Offset: 0x00
Reset value: 0x00000000
• FRDY: Flash Ready Interrupt Enable
0: Flash Ready does not generate an interru pt.
1: Flash Ready generates an interrupt.
• LOCKE: Lock Error Interrupt Enable
0: Lock Error does not generate an interrupt.
1: Lock Error generates an interrupt.
• PROGE: Programming Error Interrupt Enable
0: Programming Error does not generate an interrupt.
1: Programming Error generates an interrupt.
• FWS: Flash Wait State
0: The flash is read with 0 wai t states.
1: The flash is read with 1 wai t state.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
- FWS - - PROGE LOCKE - FRDY
141
32072H–AVR32–10/2012
AT32UC3A3
12.8.3 Flash Command Register
Name: FCMD
Access Type: Read/Write
Offset: 0x04
Reset value: 0x00000000
The FCMD can not be written if the flash is in the process of perfor ming a flash command. Doing
so will cause the FCR write to be ignored, and the PROGE bit to be set.
• CMD: Command
This field defines the flash command. Issuing any unused command will cause the Programming Error flag to be set, and the
corresponding interrup t to be requested if the PROGE bit in FCR is set.
31 30 29 28 27 26 25 24
KEY
23 22 21 20 19 18 17 16
PAGEN [15:8]
15 14 13 12 11 10 9 8
PAGEN [7:0]
76543210
-- CMD
Table 12-5. Set of commands
Command Value Mnemonic
No operation 0 NOP
Write Page 1 WP
Erase Page 2 EP
Clear Page Buffer 3 CPB
Lock region containing given Page 4 LP
Unlock region containing given Page 5 UP
Erase All 6 EA
Write General-Purpose Fuse Bit 7 WGPB
Erase Genera l-P urpose Fuse Bit 8 EGPB
Set Security Bit 9 SSB
Program GP Fuse Byte 10 PGPFB
Erase All GPFuses 11 EAGPF
Quick Page Read 12 QPR
Write User Page 13 WUP
Erase User Page 14 EUP
142
32072H–AVR32–10/2012
AT32UC3A3
•PAGEN: Page number
The PAGEN field is used to address a page or fuse bit for certain operations. In order to simplify programming, the PA GEN field
is automatically updated ev ery time the page buff er is written to. F or e v ery page buff er write, the PA GEN field is updated with the
page number of the address being written to. Hardware automatically masks writes to the PAGEN field so that only bits
representing valid page numbers can be written, all other bits in PAGEN are always 0. As an example, in a flash with 1024
pages (page 0 - page 1023), bits 15:10 will always be 0.
• KEY: Write protection key
This field should be written with the value 0xA5 to enable the command defined by the bits of the register. If the field is written
with a different value, the write is not performed and no action is started.
This field always reads as 0.
Quick Page Rea d User Page 15 QPRUP
Read High Speed Enable 16 HSEN
Read High Speed Disable 17 HSDIS
Table 12-6. Semantic of PAGEN field in different commands
Command PAGEN description
No operation Not used
Write Page The number of the page to write
Clear Page Buffer Not used
Lock region containing given Page Page number whose region should be locked
Unlock region containing given Page Page number whose region should be unlocked
Erase All Not used
Write General-Purpose Fuse Bit GPFUSE #
Erase Genera l-P urpose Fuse Bit GPFUSE #
Set Security Bit Not used
Program GP Fuse Byte WriteData[7:0], ByteAddress[2:0]
Erase All GP Fuses Not used
Quick Page Read Page number
Write User Page Not used
Erase Us er Page Not used
Quick Page Rea d User Page Not used
Table 12-5. Set of commands
Command Value Mnemonic
143
32072H–AVR32–10/2012
AT32UC3A3
12.8.4 Flash Status Register
Name: FSR
Access Type: Read/Write
Offset: 0x08
Reset value: 0x00000000
• FRDY: Flash Ready Status
0: The flash controller is busy and the application must wait before running a new command.
1: The flash controller is ready to run a new command.
• LOCKE: Lock Error Status
A utomatically cleared when FSR is read.
0: No programming of at least one locked lock region has happened since the last read of FSR.
1: Programming of at least one locked lock region has happened since the last read of FSR.
• PROGE: Programming Error Status
A utomatically cleared when FSR is read.
0: No invalid commands and no bad keywords were written in the Flash Command Register FCMD.
1: An invalid command and/or a bad keyword was/were written in the Flash Command Register FCMD.
• SECURITY: Security Bit Status
0: The security bit is inactive.
1: The security bit is active.
• QPRR: Quick Page Read Result
0: The result is zero , i.e. the page is not erased.
1: The result is one, i.e. the page is erased.
31 30 29 28 27 26 25 24
LOCK15 LOCK14 LOCK13 LOCK12 LOCK11 LOCK10 LOCK9 LOCK8
23 22 21 20 19 18 17 16
LOCK7 LOCK6 LOCK5 LOCK4 LOCK3 LOCK2 LOCK1 LOCK0
15 14 13 12 11 10 9 8
FSZ ----
76543210
- QPRR SECURITY PROGE LOCKE - FRDY
144
32072H–AVR32–10/2012
AT32UC3A3
• FSZ: Flash Size
The size of the flash. Not all device families will provide all flash sizes indicated in the table.
• LOCKx: Lock Region x Lock Status
0: The corresponding lock region is not locked.
1: The corresponding lock region is locked.
Table 12-7. Flash size
FSZ Flash Size
0 32 KByte
1 64 kByte
2 128 kByte
3 256 kByte
4 384 kByte
5 512 kByte
6 768 kByte
7 1024 kByte
145
32072H–AVR32–10/2012
AT32UC3A3
12.8.5 Flash General Purpose Fuse Regist er High
Name: FGPFRHI
Access Type: Read
Offset: 0x0C
Reset value: N/A
This register is only used in systems with more than 32 GP fuses.
• GPFxx: General Purpose Fuse xx
0: The fuse has a written/programmed state.
1: The fuse has an erased state.
31 30 29 28 27 26 25 24
GPF63 GPF62 GPF61 GPF60 GPF59 GPF58 GPF57 GPF56
23 22 21 20 19 18 17 16
GPF55 GPF54 GPF53 GPF52 GPF51 GPF50 GPF49 GPF48
15 14 13 12 11 10 9 8
GPF47 GPF46 GPF45 GPF44 GPF43 GPF42 GPF41 GPF40
76543210
GPF39 GPF38 GPF37 GPF36 GPF35 GPF34 GPF33 GPF32
146
32072H–AVR32–10/2012
AT32UC3A3
12.8.6 Flash General Purpose Fuse Register Low
Name: FGPFRLO
Access Type: Read
Offset: 0x10
Reset value: N/A
• GPFxx: General Purpose Fuse xx
0: The fuse has a written/programmed state.
1: The fuse has an erased state.
31 30 29 28 27 26 25 24
GPF31 GPF30 GPF29 GPF28 GPF27 GPF26 GPF25 GPF24
23 22 21 20 19 18 17 16
GPF23 GPF22 GPF21 GPF20 GPF19 GPF18 GPF17 GPF16
15 14 13 12 11 10 9 8
GPF15 GPF14 GPF13 GPF12 GPF11 GPF10 GPF09 GPF08
76543210
GPF07 GPF06 GPF05 GPF04 GPF03 GPF02 GPF01 GPF00
147
32072H–AVR32–10/2012
AT32UC3A3
12.9 Fuses Settings
The flash block contains 32 general purpose fuses. These 32 fuses can be found in the Flash
General Purpose Fuse Regist er Low (FGPFRLO) of the Flash Controller (FLASHC).
Some of the FGPFRLO fuse s have def ine d meanin gs out side the FLASHC an d are de scrib ed in
this section.
The general purpo se fuses are set by a JTAG chip erase.
12.9.1 Flash General Purpose Fuse Register Low (FGPFRLO)
• BODEN: Brown Out Detector Enable
• BODHYST: Brown Out Detector Hystersis
0: The BOD hysteresis is disabled
1: The BOD hysteresis is enabled
• BODLEVEL: Brown Out Detector Trigger Level
This controls the voltage trigger lev el for the Brown out detector . F or v alue description refer to Electrical Characteristics chapter.
If the BODLEVEL is set higher than VDDCORE and enabled by fuses, the part will be in constant reset. To recover from this
situation, apply an external voltage on VDDCORE that is higher than the BOD Trigger level and disable the BOD.
• LOCK, EPFL, BOOTPROT
These are Flash controller fuses and are described in the FLASHC chapter.
12.9.2 Default Fus e Value
The devices are shipped with the FGPFRLO register value: 0xFFF7FFFF:
• GPF31 reserved for future use
Table 12-8. FGPFRLO Register Description
31 30 29 28 27 26 25 24
GPF31 GPF30 GPF29 BODEN BODHYST BODLEVEL[5:4]
23 22 21 20 19 18 17 16
BODLEVEL[3:0] BOOTPROT EPFL
15 14 13 12 11 10 9 8
LOCK[15:8]
76543210
LOCK[7:0]
Table 12-9. BODEN Field Description
BODEN Description
0x0 Brown Out Detector (BOD) disabled
0x1 BOD enabled, BOD reset enabled
0x2 BOD enabled, BOD reset disabled
0x3 BOD disabled
148
32072H–AVR32–10/2012
AT32UC3A3
• GPF30 reserved for future use
• GPF29 reserved for future use
• BODEN fuses set to 0b11. BOD is disabled.
• BODHYST fuse set to 0b1. The BOD hystersis is enabled.
• BODLEVEL fuses set to 0b111111. This is the minimum v oltage trigger level. BOD will ne ver
trigger as this level is below the POR level.
• BOOTPROT fuses set to 0b011. The bootloader protected size is 8KBytes.
• EPFL fuse set to 0b1. External privileged fetch is not locked.
• LOCK fuses set to 0b1111111111111111. No region locked.
The devices are shipped with 2 bootloader configuration words in the flash user pages:
at adress 8080 01F8h and 8 08001FCh. See a lso the USB DF U bootloa der user gu ide document.
After the JTAG chip erase command, the FGPFRLO register value is 0xFFFFFFFF.
12.10 Serial number in the factory page
Each device has a unique 120 bits serial number located in the factory page and readable from
address 0x80800204 to 0x80800212.
12.11 Module configuration
The specific configuration for the FLASHC instanc e is listed in the following tables.The module
bus clocks listed here are connected to the system bus clocks according to the table in the
Power Manager section.
Table 12-10. Module Configuration
Feature FLASH
Devices ATUC3A3256S
ATUC3A3256
ATUC3A4256S
ATUC3A4256
ATUC3A3128S
ATUC3A3128
ATUC3A4128S
ATUC3A4128
ATUC3A364S
ATUC3A364
ATUC3A464
ATUC3A464
Flash size 25 6Kbytes 128Kbytes 64Kbytes
Number of
pages 512 256 128
Page size 512 bytes 512 bytes 512 bytes
Table 12-11. Module Clock Name
Module name Clock name Clock name
FLASHC CLK_FLASHC_HSB CLK_FLASHC_PB
149
32072H–AVR32–10/2012
AT32UC3A3
13. HSB Bus Matrix (HMATRIX)
Rev: 2.3.0.2
13.1 Features •User Interface on peripheral bus
•Configurable Number of Masters (Up to sixteen)
•Configurable Number of Slaves (Up to sixteen)
•One Decoder for Each Master
•
•Programmable Arbitration for Each Slave
– Round-Robin
– Fixed Priority
•Programmable Default Master for Each Slave
– No Default Master
– Last Accessed Default Master
– Fixed Default Master
•One Cycle Latency f or the First Access of a Burst
•Zero Cycle Late ncy for Default Master
•One Special Function Register for Each Slave (Not dedicated)
13.2 Overview The Bus Matrix implements a multi-layer bus structure, that enables parallel access paths
between multiple High Speed Bus (HSB) masters and slaves in a system, thus increasing the
overall bandwidth. The Bus Matrix interconnects up to 16 HSB Masters to up to 16 HSB Slaves.
The normal latency to connect a master to a slave is one cycle except for the default master of
the accessed slave which is connected dir ec tly (zero cycle latenc y). Th e Bu s M atrix pr o vide s 1 6
Special Function Registers (SFR) that allow the Bus Matrix to support application specific
features.
13.3 Product Dependencies
In order to use t his modu le, othe r p arts o f th e syst em must be conf igu red cor re ctly, as de scr ibed
below.
13.3.1 Clocks The clock for the HMATRIX bus interf ace (CLK_ HMATRIX) is g enerat ed by th e Power M anage r.
This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to
disable the HMATRIX bef ore disablin g the clock, to avoid freezing t he HMATRIX in an u ndefined
state.
13.4 Functional Description
13.4.1 Special Bus Gra nting Mechanism
The Bus Matrix provides some specula tive bus grant ing techn iqu es in order to ant icipate a ccess
requests from some masters. This mechanism reduces lat ency at first access of a burst or single
transfer. This bus grantin g mechanism sets a different default master for every slave.
150
32072H–AVR32–10/2012
AT32UC3A3
At the end of the current access, if no other request is pending, the slave remains connected to
its associated default master. A slave can be associated with three kinds of default masters: no
default master, last access master and fixed default master.
13.4.1.1 No Default Master
At the end of the current access, if no other request is pending, the slave is disconnected from
all masters. No Default Master suits low-power mode.
13.4.1.2 Last Access Master
At the end of the current access, if no other request is pending, the slave remains connected to
the last master that performed an access request.
13.4.1.3 Fixed Default Ma st er
At the end of the current access, if no other request is pending, the slave connects to its fixed
default master. Unlike last access master, the fixed master does not change unless the user
modifies it by a software action (field FIXED_DEFMSTR of the related SCFG).
To change from one kind o f defa ult ma ster t o ano ther, the Bu s Matr ix user interf ace pro vides the
Slave Configur ation Register s, one for ea ch slave, that se t a default m aster for each slave. The
Slave Configuratio n Register con tains two fields: DEFMSTR_TYPE and FIXED_DEFMSTR. The
2-bit DEFMSTR_TYPE fi eld selects the d efault master type (no default, last access master, fixed
default master), whereas the 4-bit FIXED_DEFMSTR field selects a fixed default master pro-
vided that DEFMSTR_TYPE is set to fixed default master. Please refer to the Bus Matrix user
interface descri ption.
13.4.2 Arbitration T he Bus Matrix provides an arbitration me chanism that reduces latency when co nflict cases
occur, i.e. when tw o or mo re mast e rs try to access the sam e slave at the sa me time. One ar bit er
per HSB slave is provided, thus arbitr at in g each slave differe ntly .
The Bus Matrix provides the user with the possibility of choosing between 2 arbitration types for
each slave:
1. Round-Robin Arbitration (default)
2. Fixed Pr iority Arbitration
This choice is made via the field ARBT of the Slave Configuration Registers (SCFG).
Each algorithm may be complemented by selecting a default master configuration for each
slave.
When a re-arbitration must be done, specific conditions apply. See Section 13.4.2.1 ”Ar bitration
Rules” on page 150.
13.4.2.1 Ar bitration Ru les
Each arbiter has the ability to arbitrate between two or more different master requests. In order
to avoid burst breaking and also to provide the maximum throughput for slave interf aces, arbitra-
tion may only take place during the following cycles:
1. Idle Cycles: When a slave is not connected to any master or is connected to a master
which is not currently accessing it.
2. Single Cycles: When a slave is currently doing a single access.
151
32072H–AVR32–10/2012
AT32UC3A3
3. End of Burst Cycles: When the current cycle is the last cycle of a burst transfer. For
defined length burst, predicted end of burst mat ches the size of the transfer but is man-
aged differently for undefined length burst.
4. Slot Cycle Limit : Wh en the slot cycle co unte r has rea ched the limit value indicating that
the current master access is too long and must be broken.
• Undefined Length Burst Arbitration
In order to avoid long slave handling during undefined le ngth bu rsts ( INCR), the Bu s Matr ix pro-
vides specific logic in order to re-arbitrate before the end of the INCR transfer. A predicted end
of burst is used as a defined length burst transfer and can be selected from among the following
five possibilities:
1. Infinite: No predicted end of burst is generated and therefore INCR burst transfer will
never be broken.
2. One beat bursts: Predicted end of burst is generated at each single transfer inside the
INCP transfer.
3. Four beat bursts: Predicted end of burst is generated at the end of each four beat
boundar y ins ide INCR transfer.
4. Eight beat bursts: Predicted end of burst is generated at the end of each eight beat
boundar y ins ide INCR transfer.
5. Sixteen beat b ursts: Predicted end of b urst is gene rated at th e end of each sixteen be at
boundar y ins ide INCR transfer.
This selection can be done through the field ULBT of the Master Configuration Registers
(MCFG).
• Slot Cycle Limit Arbitration
The Bus Ma trix contains sp ecific logic to break long accesses, such as very long bursts on a
very slow slave (e.g., an external low speed memory). At the beginning of the burst access, a
counter is loaded with the value previously written in the SLOT_CYCLE field of the related Slave
Configuration Regist er (SCFG) and decrease d at each clock cycle. When the counter reaches
zero, the arbiter has the ability to re-arbitrate at the end of the current byte, h alf word or word
transfer.
13.4.2.2 Round-Robin Arbitration
This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to
the same slave in a round-robin manner. If two or more master requests arise at the same time,
the master with the lowest number is first serviced, th en the others are serviced in a round-robin
manner.
There are three round-robin algorithms implemented:
1. Round-Robin arbitration without default master
2. Round-Robin arbitration with last default master
3. Round-Robin arbi tration with fixed default master
• Round-Robin Arbitration without Default Master
This is the main algorithm used by Bus Matrix arbiters. It allows the Bu s Matrix to dispatch
requests from diffe rent masters to the sam e slave in a pure round-r obin manner. At the end of
152
32072H–AVR32–10/2012
AT32UC3A3
the current access, if no other request is pending, the slave is disconnected from all masters.
This configuration incurs one latency cycle for the first access of a burst. Arbitration without
default master can be used for masters that perform significant bursts.
• Round-Robin Arbit ration with Last Default Master
This is a biased round-robin algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to
remove the one latency cycle for the last master that accessed the slave. In fact, at the end of
the current transfer, if no other master request is pending, the slave remains connected to the
last master that performed the access. Other non privileged masters still get one latency cycle if
they want to access the same slave. This technique can be used for master s that mainly perform
single accesses.
• Round-Robin Arbitration with Fixed Default Master
This is another b iased round-robin algorithm . It allows the Bus Matrix arbiters to remove the one
latency cycle for the fixed default master per slave. At the end of the current access, the slave
remains connected to its fixed d efault master. Eve ry request att empted by t his fixed defau lt mas-
ter will not cause any latency whereas other non privileged masters w ill still get one latency
cycle. This technique can be used for masters that mainly perform single accesses.
13.4.2.3 Fixed Prior ity Arbit ration
This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to
the same slave by using the fixe d priorit y defined by the user. If two or more master requests are
active at the same t ime, the master with the hig hest priority number is serviced first. If two or
more master requests with the same priority are active at the same time, the master with the
highest number is serviced first.
For each slave, the priority of each master may be defined through the Priority Registers for
Slaves (PRAS and PRBS).
13.4.3 Slave and Master assignation
The index number assigned to Bus Matrix slaves and masters are described in Memories
chapter.
153
32072H–AVR32–10/2012
AT32UC3A3
13.5 User Interface
Table 13-1. HMATRIX Register Memory Map
Offset Register Name Access Reset Value
0x0000 Master Configuration Register 0 MCFG0 Read/Write 0x00000002
0x0004 Master Configuration Register 1 MCFG1 Read/Write 0x00000002
0x0008 Master Configuration Register 2 MCFG2 Read/Write 0x00000002
0x000C Master Configuration Register 3 MCFG3 Read/Write 0x00000002
0x0010 Master Configuration Register 4 MCFG4 Read/Write 0x00000002
0x0014 Master Configuration Register 5 MCFG5 Read/Write 0x00000002
0x0018 Master Configuration Register 6 MCFG6 Read/Write 0x00000002
0x001C Master Configuration Register 7 MCFG7 Read/Write 0x00000002
0x0020 Master Configuration Register 8 MCFG8 Read/Write 0x00000002
0x0024 Master Configuration Register 9 MCFG9 Read/Write 0x00000002
0x0028 Master Configuration Register 10 MCFG10 Read/Write 0x00000002
0x002C Master Configuration Register 11 MCFG11 Read/Write 0x00000002
0x0030 Master Configuration Register 12 MCFG12 Read/Write 0x00000002
0x0034 Master Configuration Register 13 MCFG13 Read/Write 0x00000002
0x0038 Master Configuration Register 14 MCFG14 Read/Write 0x00000002
0x003C Master Configuration Register 15 MCFG15 Read/Write 0x00000002
0x0040 Slave Configuration Register 0 SCFG0 Read/Write 0x00000010
0x0044 Slave Configuration Register 1 SCFG1 Read/Write 0x00000010
0x0048 Slave Configuration Register 2 SCFG2 Read/Write 0x00000010
0x004C Slave Configuration Register 3 SCFG3 Read/Write 0x00000010
0x0050 Slave Configuration Register 4 SCFG4 Read/Write 0x00000010
0x0054 Slave Configuration Register 5 SCFG5 Read/Write 0x00000010
0x0058 Slave Configuration Register 6 SCFG6 Read/Write 0x00000010
0x005C Slave Configuration Register 7 SCFG7 Read/Write 0x00000010
0x0060 Slave Configuration Register 8 SCFG8 Read/Write 0x00000010
0x0064 Slave Configuration Register 9 SCFG9 Read/Write 0x00000010
0x0068 Slave Configuration Register 10 SCFG10 Read/Write 0x00000010
0x006C Slave Configuration Register 11 SCFG11 Read/Write 0x00000010
0x0070 Slave Configuration Register 12 SCFG12 Read/Write 0x00000010
0x0074 Slave Configuration Register 13 SCFG13 Read/Write 0x00000010
0x0078 Slave Configuration Register 14 SCFG14 Read/Write 0x00000010
0x007C Slave Configuration Register 15 SCFG15 Read/Write 0x00000010
0x0080 Priority Register A for Slave 0 PRAS0 Read/Write 0x00000000
0x0084 Priority Register B for Slave 0 PRBS0 Read/Write 0x00000000
0x0088 Priority Register A for Slave 1 PRAS1 Read/Write 0x00000000
154
32072H–AVR32–10/2012
AT32UC3A3
0x008C Priority Register B for Slave 1 PRBS1 Read/Write 0x00000000
0x0090 Priority Register A for Slave 2 PRAS2 Read/Write 0x00000000
0x0094 Priority Register B for Slave 2 PRBS2 Read/Write 0x00000000
0x0098 Priority Register A for Slave 3 PRAS3 Read/Write 0x00000000
0x009C Priority Register B for Slave 3 PRBS3 Read/Write 0x00000000
0x00A0 Priority Register A for Slave 4 PRAS4 Read/Write 0x00000000
0x00A4 Priority Register B for Slave 4 PRBS4 Read/Write 0x00000000
0x00A8 Priority Register A for Slave 5 PRAS5 Read/Write 0x00000000
0x00AC Priority Register B for Slave 5 PRBS5 Read/Write 0x00000000
0x00B0 Priority Register A for Slave 6 PRAS6 Read/Write 0x00000000
0x00B4 Priority Register B for Slave 6 PRBS6 Read/Write 0x00000000
0x00B8 Priority Register A for Slave 7 PRAS7 Read/Write 0x00000000
0x00BC Priority Register B for Slave 7 PRBS7 Read/Write 0x00000000
0x00C0 Priority Register A for Slave 8 PRAS8 Read/Write 0x00000000
0x00C4 Priority Register B for Slave 8 PRBS8 Read/Write 0x00000000
0x00C8 Priority Register A for Slave 9 PRAS9 Read/Write 0x00000000
0x00CC Prior ity Register B for Slave 9 PRBS9 Read/Write 0x00000000
0x00D0 Priority Register A for Slave 10 PRAS10 Read/Write 0x00000000
0x00D4 Priority Register B for Slave 10 PRBS10 Read/Write 0x00000000
0x00D8 Priority Register A for Slave 11 PRAS11 Read/Write 0x00000000
0x00DC Prior ity Register B for Slave 11 PRBS11 Read/Write 0x00000000
0x00E0 Priority Register A for Slave 12 PRAS12 Read/Write 0x00000 000
0x00E4 Priority Register B for Slave 12 PRBS12 Read/Write 0x00000 000
0x00E8 Priority Register A for Slave 13 PRAS13 Read/Write 0x00000 000
0x00EC Priority Register B for Slave 13 PRBS13 Read/Wr ite 0x00000000
0x00F0 Pr iority Register A for Slave 14 PRAS14 Read/Write 0x00000 000
0x00F4 Pr iority Register B for Slave 14 PRBS14 Read/Write 0x00000 000
0x00F8 Pr iority Register A for Slave 15 PRAS15 Read/Write 0x00000 000
0x00FC Priority Register B for Slave 15 PRBS15 Read/Write 0x00000000
0x0110 Special Function Register 0 SFR0 Read/Write –
0x0114 Special Function Register 1 SFR1 Read/Write –
0x0118 Special Function Register 2 SFR2 Read/Write –
0x011C Special Function Register 3 SFR3 Read/Write –
0x0120 Special Function Register 4 SFR4 Read/Write –
0x0124 Special Function Register 5 SFR5 Read/Write –
0x0128 Special Function Register 6 SFR6 Read/Write –
Table 13-1. HMATRIX Register Memory Map (Continued)
Offset Register Name Access Reset Value
155
32072H–AVR32–10/2012
AT32UC3A3
0x012C Special Function Register 7 SFR7 Read/Write –
0x0130 Special Function Register 8 SFR8 Read/Write –
0x0134 Special Function Register 9 SFR9 Read/Write –
0x0138 Special Function Register 10 SFR10 Read/Write –
0x013C Special Function Register 11 SFR11 Read/Write –
0x0140 Special Function Register 12 SFR12 Read/Write –
0x0144 Special Function Register 13 SFR13 Read/Write –
0x0148 Special Function Register 14 SFR14 Read/Write –
0x014C Special Function Register 15 SFR15 Read/Write –
Table 13-1. HMATRIX Register Memory Map (Continued)
Offset Register Name Access Reset Value
156
32072H–AVR32–10/2012
AT32UC3A3
13.5.1 Master Configuration Registers
Name: MCFG0...MCFG15
Access Type: Read/Write
Offset: 0x00 - 0x3C
Reset Value: 0x00000002
•ULBT: Undefined Length Burst Type
0: Infinite Length Burst
No predicted end of burst is generated and therefore INCR bursts coming from this master cannot be broken.
1: Single Access
The undefined length burst is treated as a succession of single accesses, allowing re-arbitration at each beat of the INCR burst.
2: Four Beat Burst
The undefined length burst is split into a four-beat burst, allowing re-arbitration at each four-beat burst end.
3: Eight Beat Burst
The undefined length burst is split into an eight-beat burst, allowing re-arbitration at each eight-beat burst end.
4: Sixteen Beat Burst
The undefined length burst is split into a sixteen-beat burst, allowing re-arbitration at each sixteen-beat burst end.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––– ULBT
157
32072H–AVR32–10/2012
AT32UC3A3
13.5.2 Slave Configuration Registers
Name: SCFG0...SCFG15
Access Type: Read/Write
Offset: 0x40 - 0x7C
Reset Value: 0x00000010
•ARBT: Arbitration Type
0: Round-Robin Arbitration
1: Fixed Priority Arbitration
•FIXED_DEFMSTR: Fixed Default Master
This is the number of the Def ault Master for this slave. Only used if DEFMSTR_TYPE is 2. Specifying the number of a master
which is not connected to the selected slav e is equivalent to setting DEFMSTR_TYPE to 0.
The size of this field depends on the number of masters. This size is log2(number of masters).
•DEFMSTR_TYPE: Default Master Type
0: No Default Master
At the end of the current slave access, if no other master request is pending , the slave is disconnected from all masters.
This results in a one cycle latency for the first access of a burst transfer or for a single access.
1: Last Default Master
At the end of the current slav e access, if no other master request is pending, the slav e sta ys connected to the last master having
accessed it.
This results in not having one cycle latency when the last master tries to access the slave again.
2: Fixed Default Master
At the end of the current slave access, if no other master request is pending, the slav e con nect s to the f ixed master the nu mbe r
that has been written in the FIXED_DEFMSTR field.
This results in not having one cycle latency when the fixed master tries to access the slave again.
•SLOT_CYCLE: Maximum Number of Allowed Cycles for a Burst
When the SLOT_CYCLE limit is reached for a burst, it may be broken by another master trying to access this slave.
This limit has been placed to avoid locking a very slow slave when very long bursts are used.
This limit must not be very small. Unreasonably small values break e v ery burst and the Bus Matrix arbitrates without performing
any data transfer. 16 cycles is a reasonable value for SLOT_CYCLE.
31 30 29 28 27 26 25 24
–––––––ARBT
23 22 21 20 19 18 17 16
– – FIXED_DEFMSTR DEFMSTR_TYPE
15 14 13 12 11 10 9 8
––––––––
76543210
SLOT_CYCLE
158
32072H–AVR32–10/2012
AT32UC3A3
13.5.3 Priority Registers A For Slaves
Name: PRAS0...PRAS15
Access Type: Read/Write
Offset: -
Reset Value: 0x00000000
•MxPR: Master x Priority
Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority.
31 30 29 28 27 26 25 24
–– M7PR –– M6PR
23 22 21 20 19 18 17 16
–– M5PR –– M4PR
15 14 13 12 11 10 9 8
–– M3PR –– M2PR
76543210
–– M1PR –– M0PR
159
32072H–AVR32–10/2012
AT32UC3A3
13.5.4 Priority Registers B For Slaves
Name: PRBS0...PRBS15
Access Type: Read/Write
Offset: -
Reset Value: 0x00000000
•MxPR: Master x Priority
Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority.
31 30 29 28 27 26 25 24
– – M15PR – – M14PR
23 22 21 20 19 18 17 16
– – M13PR – – M12PR
15 14 13 12 11 10 9 8
– – M11PR – – M10PR
76543210
–– M9PR –– M8PR
160
32072H–AVR32–10/2012
AT32UC3A3
13.5.5 Special Function Registe rs
Name: SFR0...SFR15
Access Type: Read/Write
Offset: 0x110 - 0x115
Reset Value: -
•SFR: Special Function Reg ister Fi el ds
Those registers are not a HMATRIX specific register. Th e field of those will be defined where they are used.
31 30 29 28 27 26 25 24
SFR
23 22 21 20 19 18 17 16
SFR
15 14 13 12 11 10 9 8
SFR
76543210
SFR
161
32072H–AVR32–10/2012
AT32UC3A3
13.6 Bus Matrix Connections
Accesses to unused areas returns an error result to the master requesting such an access.
The bus matrix has the several masters and slaves. Each master has its own bus and its own
decoder, thus allowing a different memory mapping per master. The master number in the table
below can be used to index the HMATRIX control registers. For example, HMATRIX MCFG0
register is associated with the CPU Data mast er interface.
Each slave has its own arbiter, thus allowing a different arbitration per slave. The slave number
in the table below can be used to index the HMATRIX control registers. For example, HMATRIX
SCFG4 register is associated with the Embedded CPU SRAM Slave Interface.
Table 13-2. High Speed Bus masters
Master 0 CPU Data
Master 1 CPU Instruction
Master 2 CPU SAB
Master 3 PDCA
Master 4 DMACA HSB Master 1
Master 5 DMACA HSB Master 2
Master 6 USBB DMA
Table 13-3. High Speed Bus slaves
Slave 0 Internal Flash
Slave 1 HSB-PB Bridge A
Slave 2 HSB-PB Bridge B
Slave 3 AES
Slave 4 Embedded CPU SRAM
Slave 5 USBB DPRAM
Slave 6 EBI
Slave 7 DMACA Slave
Slave 8 HRAMC0
Slave 9 HRAMC1
162
32072H–AVR32–10/2012
AT32UC3A3
Figure 13-1. HMATRIX Master / Slave Connecti ons
CPU Data 0
CPU
Instruction 1
CPU SAB 2
PDCA 3
Internal Flash
0
HSB-PB
Bridge A
1
HSB-PB
Bridge B
2
AES
3
HMATRIX SLAVES
HMATRIX MASTERS
Embedded
CPU SRAM
4
DMACA
Master 0 4
DMACA
Master 1
USBB
DMA
5
6
USB DPRAM
EBI
DMACA
Slave
HRAMC0
HRAMC1
56789
163
32072H–AVR32–10/2012
AT32UC3A3
14. External Bus Interface (EBI)
Rev.: 1.7.0.1
14.1 Features •Optimized for application memory space support
•Integrates three external memory controller s:
– Static Memory Controller (SMC)
– SDRAM Controller (SDRAMC)
– Error Corrected Code (ECCHRS) controller
•Additional logic for NAND Flash/SmartMediaTM and CompactFlashTM support
– NAND Flash support: 8-bit as well as 16-bit devices are supported
– CompactFlas h support: Attribute Memory, Common Memory, I/O modes are supporte d but
the signal _IOIS16 (I/O mode) is not handled.
•Optimized external bus:16-bit data bus
– Up to 24-bit Address Bus, Up to 8-Mbytes Addressable
– Optimized pin multiplexing to reduce latencies on external memories
•Up to 6 Chip Selects, Configurable Assignment:
– Static Memory Controller on Chip Select 0
– SDRAM Controller or Static Memory Controller on Chip Select 1
– Static Memory Controller on Chip Select 2, Optional NAND Flash support
– Static Memory Controller on Chip Select 3, Optional NAND Flash support
– Static Memory Controller on Chip Select 4, Optional CompactFlashTM supp ort
– Static Memory Controller on Chip Select 5, Optional CompactFlashTM supp ort
14.2 Overview The External Bus Interface (EBI) is designed to ensure the successful data transfer between
several external devices and the embedded memory controller of an 32-bit AVR device. The
Static Memory, SDRAM and ECCHRS Controllers are all fea tured external memory controllers
on the EBI. These exter nal memo ry co ntro ller s are capa ble of ha ndling sever al t ypes of exter nal
memory and peripheral devices, such as SRAM, PROM, EPROM, EEPROM, Flash, and
SDRAM.
The EBI also supports the CompactFlash and the NAND Flash/SmartMedia protocols via inte-
grated circuit ry t hat gr ea tly r educe s th e requ irem ent s for e xt erna l co mpo ne nts. Furt he rmo re, t he
EBI handles data transfers with up to six external devices, each assigned to six address spaces
defined by the embedded memory controller. Data transfers are performed through a 16-bit, an
address bus of up to 23 bits, up to six chip select lines (NCS[5:0]), and several control pins that
are generally multiplexed between the different external memory controllers.
164
32072H–AVR32–10/2012
AT32UC3A3
14.3 Block Diagram
Figure 14-1. EBI Block Diagram
HSB
HMATRIX EBI
SDRAM
Controller
Static
Memory
Controller
Compact
FLash
Logic
NAND Flash
SmartMedia
Logic
ECCHRS
Controller
Address
Decoders
Chip Select
Assignor
MUX
Logic
Peripheral Bus
I/O
Controller
DATA[15:0]
NWE1
NWE0
NRD
NCS[5:0]
ADDR[23:0]
CAS
RAS
SDA10
SDWE
SDCK
SDCKE
NANDOE
NANDWE
CFRNW
CFCE1
CFCE2
NWAIT
HSB-PB
Bridge
INTC
SDRAMC_irq ECCHRS_irq
SFR
registers
165
32072H–AVR32–10/2012
AT32UC3A3
14.4 I/O Lines Description
Table 14-1. EBI I/O Lines Description
Pin Name Alternate
Name Pin Description Type Active
Level
EBI common lines
DATA[15:0] Data Bus I/O
SMC dedicated lines
ADDR[1] SMC Address Bus Line 1 Output
ADDR[12] SMC Address Bus Line 12 Output
ADDR[15] SMC Address Bus Line 15 Output
ADDR[23:18] SMC Address Bus Line [23:18] Output
NCS[0] SMC Chip Select Line 0 Output Low
NWAIT SMC External Wait Signal Input Low
SDRAMC dedicated lines
SDCK SDRAM Clock Output
SDCKE SDRAM Clock Enable Output High
SDWE SDRAM Write Enable Output Low
SDA10 SDRAM Address Bus Line 10 Output Low
RAS - CAS Row and Column Signal Output Low
CompactFlash dedicated lines
CFCE1 -
CFCE2 CompactFlash Chip Enable Output Low
CFRNW CompactFlash Read Not Write Signal Output
NAND Flash/SmartMedia dedicated lines
NANDOE NAND Flash Output Enable Output Low
NAND WE NAND Flash Write Enable Output Low
SMC/SDRAMC shared lines
NCS[1] NCS[1]
SDCS0 SMC Chip Select Line 1
SDRAMC Chip Select Line 0 Output Low
ADDR[0] DQM0
ADDR[0]-NBS0 SDRAMC DQM1
SMC Address Bus Line 0 or Byte Select 1 Output
ADDR[11:2] ADDR[9:0]
ADDR[11:2] SDRAMC Address Bus Lines [9:0]
SMC Address Bus Lines [11:2] Output
ADDR[14:13] ADDR[9:0]
ADDR[14:13] SDRAMC Address Bus Lines [12:11]
SMC Address Bus Lines [14:13] Output
ADDR[16] BA0
ADDR[16] SDRAMC Bank 0
SMC Address Bus Line 16 Output
166
32072H–AVR32–10/2012
AT32UC3A3
14.5 Product Dependencies
In order to use t his modu le, othe r p arts o f th e syst em must be conf igu red cor re ctly, as de scr ibed
below.
14.5.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with I/O Con-
troller lines. The user must first configure the I/O Controller to assign the EBI pins to their
peripheral functions.
14.5.2 Power Management
To prevent bus errors EBI operation must be terminated bef ore entering sleep mode.
14.5.3 Clocks A number of clocks can be selected as source for the EBI. The selected clock must be enabled
by the Power Manager.
The following clock sources are available:
• CLK_EBI
• CLK_SDRAMC
• CLK_SMC
ADDR[17] BA1
ADDR[17] SDRAMC Bank 1
SMCAddress Bus Line 17 Output
SMC/CompactFlash shared lines
NRD NRD
CFNOE SMC Read Signal
CompactFlash CFNOE Output Low
NWE0 NWE0-NWE
CFNWE SMC Write Enable10 or Write enable
CompactFlash CFNWE Output Low
NCS[4] NCS[4]
CFCS[0] SMC Chip Select Line 4
CompactFlash Chip Select Line 0 Output Low
NCS[5] NCS[5]
CFCS[1] SMC Chip Select Line 5
CompactFlash Chip Select Line 1 Output Low
SMC/NAND Flash/SmartMedia shared lines
NCS[2] NCS[2]
NANDCS[0]
SMC Chip Select Line 2
NANDFlash/SmartMedia Chip Select Line
0Output Low
NCS[3] NCS[3]
NANDCS[1]
SMC Chip Select Line 3
NANDFlash/SmartMedia Chip Select Line
1Output Low
SDRAMC/SMC/CompactFlash shared lines
NWE1 DQM1/
NWE1-NBS1/
CFNIORD
SDRAMC DQM1
SMC Write Enable1 or Byte Select 1
CompactFlash CFNIORD Output
Pin Name Alternate
Name Pin Description Type Active
Level
167
32072H–AVR32–10/2012
AT32UC3A3
• CLK_ECCHRS
Refer to Table 14-2 on page 167 to configure those clocks.
14.5.4 Interrupts The EBI interface has two interrupt lines connected to the Interrupt Controller:
• SDRAMC_IRQ: Interrupt signal coming from the SDRAMC
• ECCHRS_IRQ: Inter rupt signal coming from the ECCHRS
Handling the EBI interr upt requires co nfiguring the inte rrupt controller b efore configuring t he EBI.
14.5.5 HMATRIX The EBI interface is connected to the HMATRIX Special Function Register 6 (SFR6). The user
must first write to this HMATRIX.SFR6 to configure the EBI cor rectly.
Table 14-2. EBI Clocks Configuration
Clocks name Clocks
type
Type of the Interfaced Device
SDRAM SRAM, PROM,
EPROM,
EEPROM, Flash
NandFlash
SmartMedia CompactFlash
CLK_EBI HSB X X X X
CLK_SDRAMC PB X
CLK_SMC PB X X X
CLK_ECCHRS PB X
Table 14-3. EBI Special Function Register Fields Description
SFR6 Bit
Number Bit name Description
[31:6] Reserved
5CS5A
0 = Chip Select 5 (NCS[5]) is connected to a Static Memory device. For each
access to the NCS[5] memory space, all related pins act as SMC pins
1 = Chip Select 5 (NCS[5]) is connected to a CompactFlash device. For each
access to the NCS[5] memory space, all related pins act as CompactFlash
pins
4CS4A
0 = Chip Select 4 (NCS[4]) is connected to a Static Memory device. For each
access to the NCS[4] memory space, all related pins act as SMC pins
1 = Chip Select 4 (NCS[4]) is connected to a CompactFlash device. For each
access to the NCS[4] memory space, all related pins act as CompactFlash
pins
3CS3A
0 = Chip Select 3 (NCS[3]) is connected to a Static Memory device. For each
access to the NCS[3] memory space, all related pins act as SMC pins
1 = Chip Select 3 (NCS[3]) is connected to a NandFlash or a SmartMedia
device. For each access to the NCS[3] memory space, all related pins act as
NandFlash or SmartMedia pins
168
32072H–AVR32–10/2012
AT32UC3A3
14.6 Functional Description
The EBI transfers data between the internal HSB bus (handled by the HMATRIX) and the exter-
nal memories or peripheral devices. It controls the waveforms and the parameters of the
external address, data and control busses and is composed of the following elements:
• The Static Memory Controller (SMC)
• The SDRAM Controller (SDRAMC)
• The ECCHRS Controller (ECCHRS)
• A chip select assignment feature that assigns an HSB address space to the external devices
• A multiplex controller circuit that shares the pins between the different memory controllers
• Programmable Comp actFlash support logic
• Programmable Sma rtMedia and NAND Flash support logic
14.6.1 Bus Multiplexing
The EBI offers a complete set of control signals that share the 16-bit data lines, the address
lines of up to 24 bits and the cont rol signals through a multiplex logic operating in function of the
memory area requests.
Multiplexing is specifically organized in order to guarantee the maintenance of the address and
output contro l lines at a st ab le stat e wh ile n o ex ternal access is being performed. Multiplexing is
also designed to respect the data float times defined in the Memory Controllers. Furthermore,
refresh cycles of the SDRAM are executed independently by the SDRAMC without delaying the
other external memory controller accesses.
14.6.2 Static Memory Controller
For information on the Static Memory Controller, refer to the Static Memory Controller Section.
14.6.3 SDRAM Controller
Writing a one to the HMATRIX.SFR6.CS1A bit enables the SDRAM logic.
For information on the SDRAM Controller, refer to the SDRAM Section.
14.6.4 ECCHRS Cont roller
For information on the ECCHRS Controller, refer to the ECCHRS Section.
2CS2A
0 = Chip Select 2 (NCS[2]) is connected to a Static Memory device. For each
access to the NCS[2] memory space, all related pins act as SMC pins
1 = Chip Select 2 (NCS[2]) is connected to a NandFlash or a SmartMedia
device. For each access to the NCS[2] memory space, all related pins act as
NandFlash or SmartMedia pins
1CS1A
0 = Chip Select 1 (NCS[1]) is connected to a Static Memory device. For each
access to the NCS[1] memory space, all related pins act as SMC pins
1 = Chip Select 1 (NCS[1]) is connected to a SDRAM device. For each access
to the NCS[1] memory space, all related pins act as SDRAM pins
0 Reserved
Table 14-3. EBI Special Function Register Fields Description
SFR6 Bit
Number Bit name Description
169
32072H–AVR32–10/2012
AT32UC3A3
14.6.5 CompactFlash Support
The External Bus Interface integrates circuitry that interfaces to CompactFlash devices.
The CompactFlash logic is driven by the SMC on the NCS[4] and/or NCS[5] address space.
Writing to the HMATRIX.SFR6.CS4A and/or HMATRIX.SFR6.CS5A bits the appropriate value
enables this logic. Access to an external CompactFlash device is then made by accessing the
address space reserved to NCS[4] and/or NCS[5].
Attribute M em o ry, Co m m on M e mor y , I/O m o de s ar e su pp o rt ed b ut t he s ign als _ IOWR, _IOIS1 6
(I/O mode) ar e not handled.
14.6.5.1 I/O Mode, Common Memory Mode, Attribute Memory Mode
Within the NCS[4] and/or NCS[5] address space, the current transfer address is used to distin-
guish I/O mode, common memory mode andattribute memory mode.
The different modes are accessed through a specific m emory mapping as illustrated o n Figure
14-2 on page 169. ADDR[23:2 1] bi ts of th e tr ansfer addr ess are used to sele ct t he desire d mode
as described in Table 14-4 on page 169.
Figure 14-2. CompactFlash Memory Mapping
Note: The ADDR[22] I/O line is used to drive the REG signal of the CompactFlash Device.
14.6.5.2 CFCE1 and CFCE2 signals
To cover all types of access, the SMC must be alternatively set to drive 8-bit data bus or 16-bit
data bus. The odd byte access on the DATA[7:0] bus is only possible when the SMC is config-
Table 14-4. CompactFlash Mode Selection
ADDR[23:21] Mode Base Address
000 Attribute Memory
001 I/O Mode (Write operations)
010 Common Memor y
100 I/O Mode (Read operations)
I/O Mode Space
(Read operations)
Common Memory Mode Space
Att ri but e Memory Mode Space
Offset 0x0080 0000
Offset 0x0040 0000
Offset 0x0000 0000
CF Address Space
I/O Mode Space
(Write operations)
Offset 0x0020 0000
170
32072H–AVR32–10/2012
AT32UC3A3
ured to drive 8-bi t memory devices on the corre sponding NCS pin (NCS[ 4] or NCS[ 5]). The Data
Bus Width (DBW) field in the SMC Mode (MODE) register of the NCS[4] and/or NCS[5] address
space must be written as shown in Table 14-5 on page 170 to enable the required access type.
NBS1 and NBS0 are the byte selection signa ls from SMC and are available when the SMC is set
in Byte Select mode on the corresponding Chip Select.
The CFCE1 and CFCE2 waveforms are identical to the corresponding NCSx waveform. For
details on these waveforms and timings, refer to the SMC Section.
14.6.5.3 Read/Write signals
During read operations, in I/O mode, the CompactFlash logic drives the read command signals
of the SMC on CFNIORD signal, while the CFNOE is de activa ted. Likewise, in common memor y
mode and attribute memory mode, the SMC signals are driven on the CFNOE signal, while the
CFNIORD is deactivated. Figure 14-3 on page 171 demonstrates a schematic representation of
this logic.
During write operations, in all modes, the CompactFlash logic drives the write command signal
of the SMC on CFNWE signal. Addtionnal external logic is required to drive _WE and _IOWR
compact flash signals based on CFNWE. Figure 14-3 on page 171 demonstrates a schematic
representation of this logic. No e xternal logic is required if I/O mode is not used (in this cas e,
CNFWE signal can drive directly _WE compact flash signal).
Attribute memory mode, common memory mode and I/O mode are supported by writing the
address setup and hold time on the NCS[4 ] (and/or NCS[5]) chip sele ct to the appropriate va l-
ues. For details on these signal waveforms, please refer to the section: Setup and Hold Cycles
of the SMC Section.
Table 14-5. CFCE1 and CFCE2 Truth Table
Mode CFCE2 CFCE1 DBW Comment SMC Access
Mode
Attribute Memory NBS1 NBS0 16 bits Access to Even Byte on
DATA[7:0] Byte Select
Common Memor y NBS1 NBS0 16bits
Access to Even Byte on
DATA[7:0]
Access to Odd Byte on
DATA[15:8]
Byte Select
1 0 8 bits Access to Odd Byte on
DATA[7:0]
I/O Mode NBS1 NBS0 16 bits
Access to Even Byte on
DATA[7:0]
Access to Odd Byte on
DATA[15:8]
Byte Select
1 0 8 bits Access to Odd Byte on
DATA[7:0]
171
32072H–AVR32–10/2012
AT32UC3A3
Figure 14-3. CompactFlash Read/Write Control Signals
14.6.5.4 Multiplexing of CompactFlash signals on EBI pins
Table 14-7 on page 171 and Tabl e on pa ge 17 1 illustrate the multiplex ing of the Compac tFlash
logic signals with other EBI signals on the EBI pins. The EBI pins in Table 14-7 on page 171 are
strictly dedicated to the CompactFlash interface as soon as the HMATRIX.SFR6.CS4A and/or
HMATRIX.SFR6.CS5 A b its is/are writte n. T hese p ins must not b e used to drive an y ot he r me m -
ory devices.
The EBI pins in Table 14-8 on page 172 remain shared between all memory areas when the cor-
responding CompactFlash interface is enabled (CS4A = 1 and/or CS5A = 1).
Table 14-6. CompactFlash Mode Selection
Mode Base Address CFNOE CFNWE CFNIORD
Attribute Memor y
I/O Mode (Write operations)
Common Memory NRD_NOE NWR0_NWE 1
I/O Mode (Read operations) 1 1 NRD_NOE
A22
A23
SMC
NRD
NWR0/NWE
Compact Flash Logic
EBI
1
1
1
00
1
1
0
1
CFNOE
CFNWE
CFNIORD
Table 14-7. Dedicated CompactFlash Interface Multiplexing
Pins CompactFlash Signals EBI Signals
CS4A = 1 CS5A = 1 CS4A = 0 CS5A = 0
NCS[4] CFCS0 NCS[4]
NCS[5] CFCS1 NCS[5]
172
32072H–AVR32–10/2012
AT32UC3A3
14.6.5.5 Application example
Figure 14 -4 on page 172 illustrates an example of a CompactFlash application. CFCS0 and
CFRNW signals are not directly connected to the CompactFlash slot 0, but do control the direc-
tion and the output enable of the buffers between the EBI and the CompactFlash Device. The
timing of the CFCS0 signal is identical to the NCS[4] signal. The CFRNW signal remains valid
throughout the transfe r, as does the address bus. The CompactFlash _WAIT signal is con-
nected to the NWAIT input of the Static Memory Controller. For details on these waveforms and
timings, refer to the SMC Section.
Figure 14-4. CompactFlash Application Example with I/O mode
Table 14-8. Shared CompactFlash Interface Multiplexing
Pins
Access to
CompactFlash Device
CompactFlash Signals
NRD CFNOE
NWE0 CFNWE
NWE1 CFNIORD
CFRNW CFRNW
EBI
CompactFlash
Connector
DATA[15:0]
CFRNW
NCS[4]
Pxx
ADDR[10:0]
ADDR[22]
NRD
NWE0
NWE1
CFCE1
CFCE2
NWAIT _WAIT
_CE2
_CE1
_IOWR
_IORD
_WE
_OE
_REG
A[10:0]
_CD2
_CD1
D[15:0]
/OE
/OEDIR
ADDR[21]
173
32072H–AVR32–10/2012
AT32UC3A3
Figure 14-5. CompactFlash Application Example without I/O mode
14.6.6 SmartMedia and NAND Flash Support
The EBI integrates circuitry that interfaces to SmartMedia and NAND Flash devices.
The NAND Flash logic is driven by the Static Memory Controller on the NCS[2] (and/or NCS[3])
address space. Writing to the HM ATRIX.SFR6.CS2A (and/or HMATRIX.SFR6.CS3A) bit the
appropriate va lue enables the NAND Flas h logic. Access to an external NAND Flash device is
then made by accessing th e address space reserved to NCS[2] (and/or NCS[3]).
The NAND Flash logic drives the read and write command signals of the SMC on the NANDOE
and NANDWE signals when the NCS[2] (and/or NCS[3]) signal is active. NANDOE and
NANDWE are invalidated as soon as the transfer address fails to lie in the NCS[2] (and/or
NCS[3]) address space. See Figure 14-6 on page 174 for more informations. For details on
these waveform s, re fe r to th e SMC Sectio n .
The SmartMedia device is connected the same way as the NAND Flash device.
EBI
CompactFlash
Connector
DATA[15:0]
CFRNW
NCS[4]
Pxx
ADDR[10:0]
ADDR[22]
NRD
NWE0
NWE1
CFCE1
CFCE2
NWAIT _WAIT
_CE2
_CE1
_IOWR
_IORD
_WE
_OE
_REG
A[10:0]
_CD2
_CD1
D[15:0]
/OE
/OEDIR
ADDR[21]
174
32072H–AVR32–10/2012
AT32UC3A3
Figure 14-6. NAND Flash Signal Multiplexing on EBI Pins
14.6.6.1 NAND Flash signals
The address latch enable and command latch enable signals on the NAND Flash device are
driven by address bits ADDR[22] and ADDR[21] of the EBI address bus. The user should note
that any bit on t he EBI address bus can also be used for t his purpose. The command, addr ess or
data words on the data bus of the NAND Flash device are distinguished by using their address
within the NCSx address space. The chip enab le (CE) signal of the device and the ready/busy
(R/B) signals are conn ected to I/O Controller lines. The CE signa l then remains asserted eve n
when NCSx is not selected, preventing the device from returning to standby mode.
Figure 14-7. NAND Flash Application Example
Note: The External Bus Interfaces is also able to support 16-b its devices.
SMC NandFlash
Logic
NCS[2]/[3]
NRD
NWR0_NWE
NANDOE
NANDWE
EBI
EBI
NCS[2/3]
Or I/O line
I/O line
DATA[7:0]
ADDR[22]
ADDR[21]
ALE
CLE
AD[7:0]
NOE
NWE
CE
R/B
NandFlash
NANDOE
NANDWE
175
32072H–AVR32–10/2012
AT32UC3A3
14.7 Application Example
14.7.1 Hardware Interface
Note: 1. NWE1 enables upper byte writes. NWE0 enables lower byte writes.
2. NBS1 enables upper byte writes. NBS0 enables lower byte writes.
Table 14-9. EBI Pins and External Static Devices Connections
Pins name
Pins of the Interfaced Device
8-bit Static
Device
2 x 8-bit
Static
Devices
16-bit Static
Device
Controller SMC
DATA[7:0] D[7:0] D[7:0] D[7:0]
DATA[15:0 – D[15:8] D[15:8]
ADDR[0] A[0] – NBS0(2)
ADDR[1] A[1] A[0] A[0]
ADDR[23:2] A[23:2] A[22:1] A[22:1]
NCS[0] - NCS[5] CS CS CS
NRD OE OE OE
NWE0 WE WE(1) WE
NWE1 – WE(1) NBS1(2)
Table 14-10. EBI Pins and External Devices Connections
Pins name
Pins of the Interfaced Device
SDRAM Compact
Flash
Smart Media
or
NAND Flash
Controller SDRAMC SMC
DATA[7:0] D[7:0] D[7:0] AD[7:0]
DATA[15:8] D[15:8] D[15:8] AD[15:8]
ADDR[0] DQM0 A[0] –
ADDR[1] – A[1] –
ADDR[10:2] A[8:0] A[10:2] –
ADDR[11] A[9] – –
SDA10 A[10] – –
ADDR[12] – – –
ADDR[14:13] A[12:11] – –
ADDR[15] – – –
ADDR[16] BA0 – –
ADDR[17] BA1 – –
ADDR[20:18] – – –
176
32072H–AVR32–10/2012
AT32UC3A3
Note: 1. Not directly connected to the CompactFlash slot. Permits the control of the bidirectional buffer
between the EBI data bus and the CompactFlash slot.
2. Any I/O Controller line.
3. The CLE and ALE signals of the NAND Flash device may be driven by any address bit. For
details, see Section 14.6.6.
ADDR[21] – – CLE(3)
ADDR[22] – REG ALE(3)
NCS[0] – – –
NCS[1] SDCS[0] – –
NCS[2] – – CE0
NCS[3] – – CE1
NCS[4] – CFCS0(1) –
NCS[5] – CFCS1(1) –
NANDOE – – OE
NANDWE – – WE
NRD – OE –
NWE0 – WE –
NWE1 DQM1 IOR –
CFRNW – CFRNW(1) –
CFCE1 – CE1 –
CFCE2 – CE2 –
SDCK CLK – –
SDCKE CKE – –
RAS RAS – –
CAS CAS – –
SDWE WE – –
NWAIT – WAIT –
Pxx(2) – CD1 or CD2 –
Pxx(2) ––RDY
Table 14-10. EBI Pins and External Devices Connections (Continued)
Pins name
Pins of the Interfaced Device
SDRAM Compact
Flash
Smart Media
or
NAND Flash
Controller SDRAMC SMC
177
32072H–AVR32–10/2012
AT32UC3A3
14.7.2 Connection Examples
Figure 14-8 on page 177shows an example of connections between the EBI and external
devices.
Figure 14-8. EBI Connections to Memory Devices
EBI
DATA[15:0]
RAS
CAS
SDCK
SDCKE
SDWE
ADDR[0]
NWE1
NRD
NWE0
SDRAM
2Mx8
D[7:0]
CS
CLK
CKE
WE
RAS
CAS
DQM
A[9:0]
A[10]
A[11]
BA0
BA1
SDRAM
2Mx8
D[7:0]
CS
CLK
CKE
WE
RAS
CAS
DQM
A[9:0]
A[10]
A[11]
BA0
BA1
DATA[7:0] DATA[15:8]
ADDR[11:2]
SDA10
ADDR[13]
ADDR[16]
ADDR[17]
ADDR[11:2]
SDA10
ADDR[13]
ADDR[16]
ADDR[17]
SDCK
SDCKE
SDWE
RAS
CAS
ADDR[0]
SDCK
SDCKE
SDWE
RAS
CAS
NWE1
SDA10
ADDR[17:1]
NCS[1]
SRAM
128Kx8
WE
OE
CS
D[7:0] A[16:0]
SRAM
128Kx8
WE
OE
CS
D[7:0] A[16:0]
DATA[7:0]
DATA[15:8]
ADDR[17:1] ADDR[17:1]
NCS[0]
NCS[0] NCS[0]
NRD NRD
NWE0 NWE1
178
32072H–AVR32–10/2012
AT32UC3A3
15. Static Memory Controller (SMC)
Rev. 1.0.6.5
15.1 Features •6 chip selects available
•16-Mbytes address space per chip select
•8- or 16-bit data bus
•Word, halfword, byte transfers
•Byte write or byte select lines
•Programmable setup, pulse and hold time for read signals per chip select
•Programmable setup, pulse and hold time for write signals per chip select
•Programmable data float time per chip select
•Compliant with LCD module
•External wait request
•Automatic switch to slow clock mode
•Asynchronous read in page mode supported: page size ranges from 4 to 32 bytes
15.2 Overview The Static Memory Controller (SMC) generates the signals that control the access to the exter-
nal memory devices or peripheral devices. It has 6 ch ip selects and a 24-bit ad dress bus. The
16-bit data bus can be configured to interface with 8-16-bit external devices. Separate read and
write control signals allow for direct memory and peripheral interfacing. Read and write signal
waveforms ar e fu lly param e tr izab le .
The SMC can manage wait requests from exter nal devices to extend the current access. The
SMC is provided with an automatic slow clock mode. In slow clock mode, it switches from user-
programmed wavefor ms to slow-rate specific waveforms o n read and write sign als. The SMC
supports asynchronous bur st read in page mode access for page size up to 32 bytes.
179
32072H–AVR32–10/2012
AT32UC3A3
15.3 Block Diagram
Figure 15-1. SMC Block Diagram (AD_ MSB=23)
15.4 I/O Lines Description
15.5 Product Dependencies
In order to use t his modu le, othe r p arts o f th e syst em must be conf igu red cor re ctly, as de scr ibed
below.
SMC
Chip Select
HMatrix
Power
Manager CLK_SMC
SMC I/O
Controller
NCS[5:0]
NRD
NWE0
ADDR[0]
NWE1
ADDR[1]
ADDR[AD_MSB:2]
DATA[15:0]
NWAIT
User Interface
Peripheral Bus
NCS[5:0]
NRD
NWR0/NWE
A0/NBS0
NWR1/NBS1
A1/NWR2/NBS2
A[AD_MSB:2]
D[15:0]
NWAIT
EBI
Mux Logic
Table 15-1. I/O Lines Descrip tion
Pin Name Pin Description Type Active Level
NCS[5:0] Chip Select Lines Output Low
NRD Read Signal Output Low
NWR0/NWE Write 0/Write Enable Signal Output Low
A0/NBS0 Address Bit 0/Byte 0 Select Signal Output Low
NWR1/NBS1 Write 1/Byte 1 Select Signal Output Low
A[23:2] Address Bus Output
D[15:0] Data Bus Input/Output
NWAIT External Wait Signal Input Low
180
32072H–AVR32–10/2012
AT32UC3A3
15.5.1 I/O Lines The SMC signals pass through the External Bus Interface (EBI) module where they are multi-
plexed. The user must first configure the I/O Controller to assign the EBI pins corresponding to
SMC signals to their perip he ral fu ncti on. If th e I /O lin es of t he EBI cor respon ding t o SMC signals
are not used by th e application, they can be used for other purposes by the I/ O Controller.
15.5.2 Clocks The clock for the SMC bus interface (CLK_SMC) is generate d by the Power Ma nager. Th is clock
is enabled at reset, and can be disabled in t he Power Ma nager. It is r ecommended to di sable the
SMC before disabling the clock, to avo id freezing the SMC in an undefined state.
15.6 Functional Description
15.6.1 Application Example
Figure 15-2. SMC Connections to Static Memory Devices
15.6.2 Externa l Memory Mapping
The SMC provides up to 24 address lines, A[23:0]. This allows each chip select line to address
up to 16Mbytes of me mo r y .
If the physical memory device connected on one chip select is smaller than 16Mbytes, it wraps
around and appears to be rep eated within this space. The SMC correctly handles any valid
access to the memory device within the page (see Figure 15-3 on page 181).
A[23:0] is only significant for 8-bit memory, A[23:1] is used for 16-bit memory23.
128K x 8
SRAM
D0-D7
CS
OE
WE
A0-A16
128K x 8
SRAM
D0-D7
CS
OE
WE
A0-A16
D0-D15
NWR1/NBS1
A0/NBS0
NWR0/NWE
NCS0
NCS2
NCS1
NCS3
NCS5
NCS4
NRD NRD
A2-A18
Static Memory
Controller
NWR0/NWE NWR1/NBS1
D8-D15D0-D7
A2-A18A2-A18
181
32072H–AVR32–10/2012
AT32UC3A3
Figure 15-3. Memory Connections for Six External Devices
15.6.3 Connection to External Devices
15.6.3.1 Data bus width
A data bus width of 8 or 16 bits can be selected for each chip select. This option is controlled by
the Data Bus Width fiel d in the Mode Register (MODE.DBW) for the corresponding chip select.
Figure 15-4 on page 181 shows how t o connect a 512K x 8-bit m emory on NCS2. Figure 15-5 on
page 182 shows how t o connect a 512K x 16-bit memory on NCS2.
15.6.3.2 Byte write or byte select access
Each chip select with a 16-bit data bus can operate with one of two different types of write
access: byte write or byte select acce ss. This is controlled by the Byte Access Type bit in the
MODE register (MODE.BAT) for the corresponding chip select.
Figure 15-4. Memory Connection for an 8-bit Data Bus
NCS[0] - NCS[5]
NRD
NWE
A[AD_MSB:0]
D[15:0]
SMC NCS5
NCS4
NCS3
NCS2
NCS1
NCS0
8 or 16
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Output Enable
Write Enable
A[AD_MSB:0]
D[15:0] or D[7:0]
SMC
A0
NWE
NRD
NCS[2]
A0
Write Enable
Output Enable
Memory Enable
D[7:0] D[7:0]
A[18:2]
A[18:2]
A1 A1
182
32072H–AVR32–10/2012
AT32UC3A3
Figure 15-5. Memory Connec t ion for a 16 -b it Da ta Bus
•Byte write access
The byte write access mode supports one byte write signal per byte of the data bus and a single
read signal.
Note that the SMC does not allow boot in byte write access mode.
• For 16-bit devices: the SMC provides NWR0 and NWR1 write signals for respectively byte0
(low er b yte) and b yt e1 (upper b yte) of a 16-bit b us . One sin gle read signal (N RD) is pro vided.
The byte write access mode is used to connect two 8-bit devices as a 16-bit memory.
The byte write option is illustrated on Figure 15-6 on page 183.
•Byte select access
In this mode, read/write operations can be enabled/disabled at a byte level. One byte selec t line
per byte of the data bus is provided. One NRD and one NWE signal control read and write.
• For 16-bit devices: the SMC provides NBS0 and NBS1 selection signals f or respectively
byt e0 (lower byte) and byte1 (upper byte) of a 16-bit bus. The byte select access is used to
connect one 16-bit device.
SMC NBS0
NWE
NRD
NCS[2]
Low Byte Enable
Write Enable
Output Enable
Memory Enable
NBS1 High Byte Enable
D[15:0] D[15:0]
A[19:2] A[18:1]
A[0]A1
183
32072H–AVR32–10/2012
AT32UC3A3
Figure 15-6. Connection of two 8-bit Devices on a 16-bit Bus: Byte Write Option
•Signal multiplexing
Depending on the MODE.BAT bit, only the write si gnals or the byte select signals are used. To
save I/Os at the external bus interface, control signals at the SMC interface are multiplexed.
For 16-bit devices, bit A0 of address is unused. When byte select option is selected, NWR1 is
unused. When byte write option is selected, NBS0 to NBS1 are unused.
Table 15-3. SMC Multiplexed Signal Translation
15.6.4 Standard Read and Write Protocols
In the following sections, the byte access type is not considered. Byte select lines (NBS0 to
NBS1) always have the same timing as the address bus (A). NWE represents either the NWE
signal in byte select access type or one of the byte write lines (NWR0 to NWR1) in byte write
SMC A1
NWR0
NRD
NCS[3]
Write Enable
Read Enable
Memory Enable
NWR1
Write Enable
Read Enable
Memory Enable
D[7:0] D[7:0]
D[15:8]
D[15:8]
A[24:2]
A[23:1]
A[23:1]
A[0]
A[0]
Signal Name 16-bit Bus 8-bit Bus
Device Type 1 x 16-bit 2 x 8-bit 1 x 8-bit
Byte Access Type (BAT) Byte Select Byte Write
NBS0_A0 NBS0 A0
NWE_NWR0 NWE NWR0 NWE
NBS1_NWR1 NBS1 NWR1
NBS2_NWR2_A1 A1 A1 A1
184
32072H–AVR32–10/2012
AT32UC3A3
access type. NWR0 to NWR1 have the same timings and protocol as NWE. In the same way,
NCS represents one of the NCS[0..5] chip select lines.
15.6.4.1 Read wa vef o rms
The read cycle is shown on Figure 15-7 on page 184.
The read cycle starts with the address setting on the memory address bus, i.e.:
{A[23:2], A1, A0} for 8-bit devices
{A[23:2], A1} for 16-bit devices
Figure 15-7. Standard Read Cycle
•NRD waveform
The NRD signal is characterized by a setup timing, a pulse width, and a hold timing.
1. NRDSETUP: the NRD setup time is defined as the setup of address before the NRD
falling edge.
2. NRDPULSE: the NRD pulse length is the time between NRD falling edge and NRD ris-
ing edge.
3. NRDHOLD: the NRD hold t ime is defin ed as the ho ld time of add ress aft er the NRD ris-
ing edge.
•NCS waveform
Similarly, the NCS signal can be divided into a setup t ime, pulse length and hold time.
A[AD_MSB:2]
CLK_SMC
NBS0, NBS1,
A0, A1
NRD
NCS
D[15:0]
NCSRDSETUP
NRDSETUP NRDPULSE
NCSRDPULSE
NRDCYCLE
NRDHOLD
NCSRDHOLD
185
32072H–AVR32–10/2012
AT32UC3A3
1. NCSRDSETUP: the NCS setup time is defined as the set up time of address b efore the
NCS falling edge.
2. NCSRDPULSE: the NCS pulse length is the time between NCS falling edge and NCS
rising edge.
3. NCSRDHOLD: the NCS hold time is defined as the hold time of address after the NCS
rising edge.
•Read cycle
The NRDCYCLE time is defined as the total duration of the read cycle, i.e., from the time where
address is set on the address bus to the point where address may change. The total read cycle
time is equal to:
Similarly,
All NRD and NCS timings are defined separately for each chip select as an integer number of
CLK_SMC cycles. To ensure that the NR D and NCS timings are coherent, the user must define
the total read cycle instead of the hold timing. NRDCYCLE implicitly defines the NRD hold time
and NCS hold time as:
And,
•Null delay setup and hold
If null setup and hold parameters are programmed for NRD and/or NCS, NRD and NCS remain
active continuously in case of consecutive read cycles in the same memory (see Figure 15-8 on
page 186).
NRDCYCLE NRDSETUP NRDPULSE NRDHOLD++=
NRDCYCLE NCSRDSETUP NCSRDPULSE NCSRDHOLD++=
NRDHOLD NRDCYCLE NRDSETUP–NRDPULSE–=
NCSRDHOLD NRDCYCLE NCSRDSETUP–NCSRDPULSE–=
186
32072H–AVR32–10/2012
AT32UC3A3
Figure 15-8. No Setup, No Hold on NRD, and NCS Read Signals
• Null Pulse
Programming null pulse is not permitte d. Pulse must be at least written to one. A nul l value leads
to unpredictable behavior.
15.6.4.2 Read mode As NCS and NRD wave forms are defined independently of one other, the SMC needs to know
when the read data is availab le on the data bus. The SM C does not compare NCS and NRD tim-
ings to know which signal rises first. The Read Mode bit in the MODE register
(MODE.READMODE) of the corresponding chip select indicates which signal of NRD and NCS
controls the read op eration.
•Read is controlled by NRD (MODE.READMODE = 1)
Figure 15-9 on page 187 shows the waveforms of a read operation of a typical asynchronous
RAM. The read data is available tPACC after the falling edge of NRD, and turns to ‘Z’ after the ris-
ing edge of NRD. In this case, the MODE.READMODE bit must be written to one (read is
controlled by NRD), to indicate that data is available with the rising edge of NRD. The SMC sam-
ples the read data internally on the rising edge of CLK_SMC that generates the rising edge of
NRD, whatever the programmed waveform of NCS may be.
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NRD
NCS
D[15:0]
NRDSETUP NRDPULSE
NCSRDPULSE
NRDCYCLE NRDCYCLE
NCSRDPULSE NCSRDPULSE
NRDPULSE
NRDCYCLE
187
32072H–AVR32–10/2012
AT32UC3A3
Figure 15-9. READMODE = 1: Data Is Sampled by SMC Before the Rising Edge of NRD
•Read is controlled by NCS (MODE.READMODE = 0)
Figure 15-10 on page 188 shows the ty pical read cycle of an LCD module. The read data is valid
tPACC af ter the falling e dge of the NCS signal an d remains valid until the rising edge of NCS. Da ta
must be sampled when NCS is raised. In that case, the MODE.READMODE bit must be written
to zero (read is controlled by NCS): the SMC internally samples the data on the rising edge of
CML_SMC that generates the rising edge of NCS, whatever the programmed waveform of NRD
may be.
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NRD
NCS
D[15:0]
tPACC
Data Sampling
188
32072H–AVR32–10/2012
AT32UC3A3
Figure 15-10. READMODE = 0: Data Is Sampled by SMC Before the Rising Edge of NCS
15.6.4.3 Write waveforms
The write prot oc ol is sim ilar to th e re a d protocol. It is depict ed in Figure 15-11 on page 189. The
write cycle starts with the address setting on the memory address bus.
•NWE waveforms
The NWE signal is characterized by a setup timing, a pulse width and a hold timing.
1. NWESETUP: the NWE setup time is defined as the setup of address and data before
the NWE falling edge.
2. NWEPULSE: the NWE pulse length is the time between NWE falling edge and NWE
rising edge.
3. NWEHOLD: the NWE hold time is defined as the hold time of address and data after
the NWE rising edge.
The NWE waveforms apply to all byte-write lines in byte write access mode: NWR0 to NWR3.
15.6.4.4 NCS waveforms
The NCS signal wave f orm s in writ e ope ra tion a re not the same th at t hose app lied in r ea d o per a-
tions, but are separately defined.
1. NCS WRSETUP: the NCS setup tim e is defined as the setup time of address bef o re the
NCS falling edge.
2. NCSWRPULSE: the NCS pulse length is the time between NCS falling edge and NCS
rising edge;
3. NCS WRHOLD: the NCS hold time is defin ed as the hold time o f address aft er the NCS
rising edge.
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NRD
NCS
D[15:0]
tPACC
Data Sampling
189
32072H–AVR32–10/2012
AT32UC3A3
Figure 15-11. Write Cycle
•Write cycle
The write cycle time is de fined as the tota l duration of th e write cycle, that is, fro m the time where
address is set on the address bus to the point where address may change. The total write cycle
time is equal to:
Similarly,
All NWE and NCS (write) timings are defined separately for each chip select as an integer num-
ber of CLK_SMC cycles. To ensure that the NWE and NCS timings are coherent, the user must
define the total write cycle instead of the hold timing. This implicitly defines the NWE hold tim e
and NCS (write) hold times as:
And,
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NWE
NCS
NWESETUP NWEPULSE
NCSWRPULSE
NCSWRSETUP
NWECYCLE
NWEHOLD
NCSWRHOLD
NWECYCLE NWESETUP NWEPULSE NWEHOLD++=
NWECYCLE NCSWRSETUP NCSWRPULSE NCSWRHOLD++=
NWEHOLD NWECYCLE NWESETUP–NWEPULSE–=
NCSWRHOLD NWECYCLE NCSWRSETUP–NCSWRPULSE–=
190
32072H–AVR32–10/2012
AT32UC3A3
•Null delay setup and hold
If null setup parameters are programmed for NWE and/or NCS, NWE and/or NCS remain active
continuously in case of consecutive write cycles in the same memory (see Figure 15-12 on page
190). However, for devices that perform write operations on the rising edge of NWE or NCS,
such as SRAM, either a setup or a hold must be programmed.
Figure 15-12. Null Setup and Hold Values of NCS and NWE in Write Cycle
•Null pulse
Programming null pulse is not permitte d. Pulse must be at least written to one. A nul l value leads
to unpredictable behavior.
15.6.4.5 Write mode The Write Mode bit in the MODE register (MODE.WRITEMODE) of the corresponding chip
select indicates which signal controls the write operation.
•Write is controlled by NWE (MODE.WRITEMODE = 1)
Figure 15-13 on page 191 shows the waveforms of a write op eration with MODE.WRITE MODE
equal to one. The data is put on the bus during t he pulse and hold steps of the NWE signal. The
internal data buffers are turned out after the NWESETUP time, and until the end of the write
cycle, regardless of the programmed wavefo rm on NCS.
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NWE,
NWE0, NWE1
NCS
NWESETUP NWEPULSE
NCSWRPULSENCSWRSETUP
NWECYCLE
D[15:0]
NWECYCLE
NWEPULSE
NCSWRPULSE
NWECYCLE
191
32072H–AVR32–10/2012
AT32UC3A3
Figure 15-13. WRITEMODE = 1. The Write Operation Is Controlled by NWE
•Write is controlled by NCS (MODE.WRITEMODE = 0)
Figure 15-14 on page 191 shows the waveforms of a write op eration with MODE.WRITE MODE
written to zero. The data is put on the bus during the pulse and hold steps of the NCS signal.
The internal data buffers are turned out after the NCSWRSETUP time, and until the end of the
write cycle, regardless of the programmed waveform on NWE.
Figure 15-14. WRITEMODE = 0. The Write Operation Is Controlled by NCS
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NWE,
NWR0, NWR1
NCS
D[15:0]
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NWE,
NWR0, NWR1
NCS
D[15:0]
192
32072H–AVR32–10/2012
AT32UC3A3
15.6.4.6 Coding timing parameters
All timing parameters are defined for one chip select and are grouped together in one register
according to their type.
The Setup register (SETUP) groups the definition of all setup parameters:
• NRDSETUP, NCSRDSETUP, NWESETUP, and NCSWRSETUP.
The Pulse register (PULSE) groups the definition of all pulse par ameters:
• NRDPULSE, NCSRDPULSE, NWEPULSE, and NCSWRPULSE.
The Cycle register (CYCLE) groups the definition of all cycle parameters:
• NRDCYCLE, NWECYCLE.
Table 15-4 on page 192 shows how t he timin g paramet ers are cod ed and t heir pe rmitted r ange.
15.6.4.7 Us ag e re strictio n
The SMC does not check the validity of the user-programmed parameters. If the sum of SETUP
and PULSE parameters is larger tha n the cor respond ing CYCLE paramet er, this lead s to unpr e-
dictable behavior of the SMC.
For read operations:
Null but positive setup and hold of address and NRD and/or NCS can not be guaranteed at the
memory interface because of the propagation delay of theses signals through external logic and
pads. If positive setup an d hold values must b e verified, then it is strictly recom mended to pro-
gram non-null values so as to cover possible skews between address, NCS and NRD signals.
For write operations:
If a null hold value is programmed on NWE, the SMC can guarantee a positive hold of address,
byte select lines, and NCS signal af ter th e risin g ed ge of NWE. This is tr ue if the MO DE. WRI TE-
MODE bit is written to one. See Section 15.6.5.2.
For read and write operations: a null value for pulse parameters is forb idden and may lead to
unpredictable behavior.
In read and write cycles, the setup and hold time parameters are defined in reference to the
address bus. For external devices that require setup and hold time between NCS and NRD sig-
nals (read), or between NCS and NWE signals (write), these setup and hold times must be
converted into setup and hold times in reference to the address bus.
Table 15-4. Coding and Range of Timing Parameters
Coded Value Nu mber of Bits Effective Value
Permitted Rang e
Coded Value Effective Value
setup [5:0] 6 128 x setup[5] + setup[4:0] 0 ≤ value ≤ 31
32 ≤ value ≤ 63 0 ≤ value ≤ 31
128 ≤ value ≤ 128+31
pulse [6:0] 7 256 x pulse[6] + pulse[5:0] 0 ≤ value ≤ 63
64≤ value ≤ 127 0 ≤ value ≤ 63
256 ≤ value ≤ 256+63
cycle [8:0] 9 256 x cycle[8:7] + cycle[6:0]
0 ≤ value ≤ 127
128 ≤ value ≤ 255
256 ≤ value ≤ 383
384 ≤ value ≤ 511
0 ≤ value ≤ 127
256 ≤ value ≤ 256+127
512 ≤ value ≤ 512+127
768 ≤ value ≤ 768+127
193
32072H–AVR32–10/2012
AT32UC3A3
15.6.5 Automatic Wait States
Under certain circumstances, the SMC automatically inserts idle cycles between accesses to
avoid bus contention or operation conflict.
15.6.5.1 Chip se lect wait states
The SMC always inserts an idle cycle between two transfe rs on se parate ch ip selects. This idle
cycle ensures that there is no bus contention between the deactivation of one device and the
activation of t he next one.
During chip select wait state, all control lines are turned inactive: NBS0 to NBS3, NWR0 to
NWR3, NCS[0..5], NRD lines are all set to high level.
Figure 15-1 5 on page 193 illustrates a chip select wait state between access on Chip Select 0
(NCS0) and Chip Select 2 (NCS2).
Figure 15-15. Chip Select Wait State Between a Rea d Access on NCS0 and a Write Access on
NCS2
15.6.5.2 Early read wait state
In some cases, the SMC inserts a wait s tate cycle between a write access and a read access t o
allow time for the write cycle to end before the subsequent read cycle begins. This wait state is
not generated in addition to a chip select wait state. The early read cycle thus only occurs
between a write and re ad access to the same memory device (s ame chip select).
CLK_SMC
_MSB:2]
, NBS1,
, A1
NRD
NWE
NCS0
NCS2
D[15:0]
NRDCYCLE
Read to Write
Wait State
Chip Select
Wait State
NWECYCLE
194
32072H–AVR32–10/2012
AT32UC3A3
An early read wait state is automatically inserted if at least one of the following conditions is
valid:
• if the write controlling signal has no hold time and the read controlling signal has no setup
time (Figure 15-16 on page 194).
• in NCS write controlled mode (MODE.WRITEMODE = 0), if there is no hold timing on the
NCS signal and the NCSRDSETUP parameter is set to zero, regardless of the read mode
(Figure 15-17 on page 195). The write operation must end with a NCS rising edge. Without
an early read wait state, the write operation could not complete properly.
• in NWE controlled mode (MODE.WRITEMODE = 1) and if there is no hold timing
(NWEHOLD = 0), the feedbac k of the write control signal is used to control address, data,
chip select, and byte select lines. If the external write control signal is not inactivated as
expected due to load capacitances, an early read wait state is inserted and address, data
and control signals are maintained one more cycle. See Figure 15-18 on page 196.
Figure 15-16. Early Read Wait State: Write with No Hold Followed by Read with No Setup.
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NWE
NRD
D[15:0]
No hold
No setup
Read cycle
Early Read
Wait state
Write cycle
195
32072H–AVR32–10/2012
AT32UC3A3
Figure 15-17. Early Read Wait State: NCS Controlled Write with No Hold Followed by a Read
with No Setup.
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NWE
NRD
D[15:0]
No hold No setup
Read cycle
(READMODE=0 or READMODE=1)
Early Read
Wait State
Write cycle
(WRITEMODE=0)
196
32072H–AVR32–10/2012
AT32UC3A3
Figure 15-18. Early Read Wait State: NWE-controlled Write with No Hold Followed by a Read
with one Set-up Cyc le.
15.6.5.3 Reload user configuration wait state
The user may change any of the configuration parameters by writing the SMC user interface.
When detecting that a new user configuration has been written in the user interface, the SMC
inserts a wait state before starting the next access. The so called “reload user co nfiguration wait
state” is used by the SMC to load the new set of parameters to apply to next accesses.
The reload configuration wait state is not applied in addition to the chip select wait state. If
accesses before and after reprogramming the user interface are made to different devices (dif-
ferent chip selects), then one single chip select wait state is applied.
On the other hand, if accesses before and after writing the user interface are made to the same
device, a re load configurati on wait state is inser ted, even if t he change does not concern the cu r-
rent chip select.
•User procedure
To insert a reload configu ration wait state, the SMC detects a write access to any MODE register
of the user interface. If the user only modifies timing registers (SETUP, PULSE, CYCLE regis-
ters) in the user interface, he must validate the modification by writing the MODE register, even
if no change was made on the mode parameters.
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
Internal write controlling signal
external write controlling
signal(NWE)
NRD
D[15:0]
No hold Read setup=1
Write cycle
(WRITEMODE = 1)
Early Read
Wait State
Read cycle
(READMODE=0 or READMODE=1)
197
32072H–AVR32–10/2012
AT32UC3A3
•Slow clock mode transition
A reload configuration wait state is also inserted when the slow clock mode is entered or exited,
after the end of the current transfer (see Section 15.6.8).
15.6.5.4 Read to write wait state
Due to an internal mechanism, a wait cycle is always inserte d between consecutive read and
write SMC accesses.
This wait cycle is referred to as a read to write wait state in this document.
This wait cycle is applied in addition to chip select and reload user configuration w ait states
when they are to be inserted. See Figure 15-15 o n page 193.
15.6.6 Data Float Wait States
Some memory devices are slow to release the external bus. For such devices, it is necessary to
add wait states (data float wait states) after a read access:
• before starting a read access to a different external memory.
• before starting a write access to the same device or to a different external one .
The Data Float Output Time (tDF) for each external memory device is programmed in the Data
Float Time field of the MODE register (MODE.TDFCYCLES) for the corresponding chip select.
The value of MODE.TDFCYCLES indicates the number of data float wait cycles (between 0 and
15) before the external device releases the bus, and represents the time allowed for the data
output to go to high impedance after the memory is disabled.
Data float wait states do not delay internal memory accesses. Hence, a single access to an
external memory with long tDF will not slow down the execution of a program from internal
memory.
The data float wait states management depends on the MODE.READMODE bit and the TDF
Optimization bit of the MODE register (MODE.TDFMODE) for the corresponding chip select.
15.6.6.1 Read mode Writing a one to the MODE.READMODE bit indicates to the SMC that the NRD signal is respon-
sible for turnin g o ff t he t ri- stat e buf fer s of t he e xte rn al memor y de vice. Th e d ata f loa t per iod t hen
begins after the rising edge of the NRD signal and lasts MODE.TDFCYCLES cycles of the
CLK_SMC clock.
When the read operation is controlled by the NCS signal (MODE.READMODE = 0), the
MODE.TDFCYCLES field gives the number of CLK_SMC cycles during which the data bus
remains busy afte r the risin g ed ge of NCS.
Figure 15-19 on page 198 illustrates the data float period in NRD-controlled mode
(MODE.READMODE =1), assumin g a data flo at p er iod of two cycles (M ODE.TDFCYCLES = 2).
Figure 15-20 on page 198 shows the read operation when controlled by NCS (MODE.READ-
MODE = 0) and the MODE.TDFCYCLES field equals to three.
198
32072H–AVR32–10/2012
AT32UC3A3
Figure 15-19. TDF Period in NRD Controlled Read Access (TDFCYCLES = 2)
Figure 15-20. TDF Period in NCS Controlled Read Operation (TDFCYCLES = 3)
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NRD
NCS
D[15:0]
tPACC
NRD controlled read operation
TDF = 2 clock cycles
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NRD
NCS
D[15:0]
tPACC
NCS controlled read operation
TDF = 3 clock cycles
199
32072H–AVR32–10/2012
AT32UC3A3
15.6.6.2 TDF optimization enabled (MODE.TDFMODE = 1)
When the MODE.TDFMODE bit is written to one (TDF optimization is enabled), the SMC takes
advantage of the setup period of the next access to optimize the number of wait states cycle to
insert.
Figure 15-21 on page 199 shows a read access controlled by NRD, followed by a write access
controlled by NWE, on Chip Select 0. Chip Select 0 has been pr ogrammed with:
NRDHOLD = 4; READMODE = 1 (NRD controlled)
NWESETUP = 3; WRITEMODE = 1 (NWE controlled)
TDFCYCLES = 6; TDFMODE = 1 (optimization enabled).
Figure 15-21. TDF Optimization: No TDF Wait States Are Inserted if the TDF Period Is over when the Next Access Begins
15.6.6.3 TDF optimization disabled (MODE.TDFMODE = 0)
When optimization is disabled, data float wait states are inserted at the end of the read transfer,
so that the data float perio d is ended when the second access begins. If the ho ld period of the
read1 controlling signal overlaps the data float period, no additional data float wait states will be
inserted.
Figure 15-22 on page 200, Figure 15-23 on page 200 and Figure 15-24 on page 201 illustrate
the cases:
• read access followed by a read access on another chip select.
• read access followed by a write access on another chip select.
CLK_SMC
A[AD_MSB:2]
NRD
NWE
NCS0
D[15:0]
Read access on NCS0 (NRD controlled) Read to Write
Wait State
Write access on NCS0 (NWE controlled)
TDFCYCLES = 6
NWESETUP = 3
NRDHOLD = 4
200
32072H–AVR32–10/2012
AT32UC3A3
• read access followed by a write access on the same chip select.
with no TDF optimization.
Figure 15-22. TDF Optimization Disabled (MODE.TDFMODE = 0). TDF Wait States between Two Read Accesses on Dif-
ferent Chip Selects.
Figure 15-23. TDF Optimization Disabled (MODE.TDFMODE= 0). TDF Wait States between a Read and a Write Access
on Different Chip Selects.
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
Read1 controlling
signal(NRD)
Read2 controlling
signal(NRD)
D[15:0]
Read1 hold = 1
Read1 cycle
TDFCYCLES = 6
Chip Select Wait State
5 TDF WAIT STATES
TDFCYCLES = 6
Read2 setup = 1
Read 2 cycle
TDFMODE=0
(optimization disabled)
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
Read1 controlling
signal(NRD)
Write2 controlling
signal(NWE)
D[15:0]
Read1 cycle
TDFCYCLES = 4
Chip Select
Wait State
Read1 hold = 1
TDFCYCLES = 4
Read to Write
Wait State
2 TDF WAIT STATES
Write2 setup = 1
Write 2 cycle
TDFMODE=0
(optimization disabled)
201
32072H–AVR32–10/2012
AT32UC3A3
Figure 15-24. TDF Optimization Disabled (MODE.T DFMODE = 0). TDF Wait Stat es between Read and Write accesse s on
the Same Chip Select.
15.6.7 Exte rna l Wait Any access can be extended by an external device using the NWAIT input signal of the SMC.
The External Wa it Mode field of the MODE re giste r ( MODE.EXNWMODE) on the cor re spon ding
chip select must be written to either two (frozen mode) or three (ready mode). When the
MODE.EXNWMODE field is written to zero (disabled), the NWAIT signa l is simply ignored on
the correspo nding chip select. T he NWAIT signal de lays the read or write o peration in r egards to
the read or write controlling signal, depending on the read and write modes of the corresponding
chip select.
15.6.7.1 Restriction When one of the MODE.EXNWMODE is enabled, it is mand atory to program at least one hold
cycle for the read/write controlling signal. For that reason, the NWAIT signal cannot be used in
Page Mode (Section 15.6.9 ), or in Slow Clock Mode (Section 15.6.8).
The NWAIT signal is assumed to be a response of the external device to the read/write request
of the SMC. Then NWAIT is examined by the SMC only in the pulse state of the read or write
controlling signal. The assertion of the NWAIT signal outside the expected period has no impact
on SMC behavior.
15.6.7.2 Frozen modeWhen the external device asserts the NWAIT signal (active low), and after internal synchroniza-
tion of this signal , the SMC state is frozen, i.e., SMC internal counters are frozen, and all control
signals remain unchanged. When the synchronized NWAIT signal is deasserted, the SMC com-
pletes the access, resuming the access from the point where it was stopped. See Figure 15-25
on page 202. T his mode must be selected when the extern al device uses the NWAIT signal to
delay the access and to fr eeze the SMC.
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
Read1 controlling
signal(NRD)
Write2 controlling
signal(NWE)
D[15:0]
Read1 hold = 1
TDFCYCLES = 5
Read1 cycle
TDFCYCLES = 5
Read to Write
Wait State
4 TDF WAIT STATES
Write2 setup = 1
Write 2 cycle
TDFMODE=0
(optimization disabled)
202
32072H–AVR32–10/2012
AT32UC3A3
The assertion of the NWAIT signal outside the expected period is ignored as illustrated in Figure
15-26 on page 203.
Figure 15-25. Write Access with NWAIT Assertion in Frozen Mode (MODE.EXNWMODE = 2).
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NWE
NCS
D[15:0]
654
4
3
3
2
21 1
2
1
22
1
0
0
FROZEN STATE
NWAIT
Internally synchronized
NWAIT signal
Write cycle
EXNWMODE = 2 (Frozen)
WRITEMODE = 1 (NWE controlled)
NWEPULSE = 5
NCSWRPULSE = 7
203
32072H–AVR32–10/2012
AT32UC3A3
Figure 15-26. Read Access with NWAIT Assertion in Frozen Mode (MODE.EXNWMODE = 2).
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NCS
NRD
NWAIT
Internally synchronized
NWAIT signal
EXNWMODE = 2 (Frozen)
READMODE = 0 (NCS controlled)
NRDPULSE = 2, NRDHOLD = 6
NCSRDPULSE = 5, NCSRDHOLD = 3
Read cycle
Assertion is ignored
43 2 1022
10
555 43
2
21
10
0
FROZEN STATE
204
32072H–AVR32–10/2012
AT32UC3A3
15.6.7.3 Re ad y mo d eIn Re ady mode (MODE.EXNWMODE = 3), the SMC behaves differently. Normally, the SMC
begins the access by d own counting the setup and p ulse counters of the read/write controlling
signal. In the last cycle of the pulse phase, the resynchronized NWAIT signal is examined.
If asserted, the SMC suspends the access as shown in Figure 15-27 on page 204 and Figure
15-28 on page 205. After deassertion, the access is completed: the hold step of the access is
performed.
This mode must be se lected w hen the ex ternal de vice uses deassertion of the NWAIT signal to
indicate its ability to complete the read or write operation.
If the NWAIT sig nal is deassert ed before the end of the pulse, or asserted af ter the end of the
pulse of the controlling read/write signal, it has no impac t on the access length as shown in Fig-
ure 15-28 on page 205.
Figure 15-27. NWAIT Assertion in Write Access: Ready Mode (MODE.EXN WMOD E = 3).
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NWE
NCS
D[15:0]
654
4
3
3
2
21 0
1
0
11
0
FROZEN STATE
NWAIT
Internally synchronized
NWAIT signal
Write cycle
EXNWMODE = 3 (Ready mode)
WRITEMODE = 1 (NWE_controlled)
NWEPULSE = 5
NCSWRPULSE = 7
0
205
32072H–AVR32–10/2012
AT32UC3A3
Figure 15-28. NWAIT Assertion in Read Access: Ready Mode (EXNWMODE = 3).
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NCS
NRD 6
6
5
5
4
432
3
1
21
0
NWAIT
Internally synchronized
NWAIT signal
Read cycle
EXNWMODE = 3 (Ready mode)
READMODE = 0 (NCS_controlled)
NRDPULSE = 7
NCSRDPULSE = 7
1
0
0
Assertion is ignored Assertion is ignored
Wait STATE
206
32072H–AVR32–10/2012
AT32UC3A3
15.6.7.4 NWAIT latency and read/wr ite timin gs
There may be a latency between the assertion of the read/write controlling signal and the asser-
tion of the NWAIT signal by the device. The programmed pulse length of the read/write
controlling signal must be at least equal to this latency plus the two cycles of resynchronization
plus one cycle. Other wise, th e SMC may ent er t he hold sta te of t he access wit hout det ecting t he
NWAIT signal assertion. This is true in frozen mode as well as in ready mode. This is illustrated
on Figure 15-29 on page 206.
When the MODE.EXNWMODE field is enabled (ready or frozen), the user must program a pulse
length of the read and write controlling signal of at least:
Figure 15-29. NWAIT Latency
minimal pulse length NWAIT latency 2 synchronization cycles 1 cycle++=
Wait STATE
012
3
4
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NRD
NWAIT
nternally synchronized
NWAIT signal
Minimal pulse length
00
NWAIT latency 2 cycle resynchronization
Read cycle
EXNWMODE = 2 or 3
READMODE = 1 (NRD controlled)
NRDPULSE = 5
207
32072H–AVR32–10/2012
AT32UC3A3
15.6.8 Slow Clock Mode
The SMC is able to automatically apply a set of “slow clock mode” read/write waveforms when
an internal signal driven by the SMC’s Power Management Controller is asserted because
CLK_SMC has been turned to a very slow clock rate (typically 32kHz clock rate). In this mode,
the user-programmed waveforms are ignored and the slow clock mode waveforms are applied.
This mode is provided so as to avoid reprogramming the User Interface with appropriate wave-
forms at very slow clock rate. When activated, the slow mode is active on all chip selects.
15.6.8.1 Slow clock mode waveforms
Figure 15-30 on page 207 illustrates the read and write operations in slow clock mode. They are
valid on all chip selects. Table 15-5 on page 207 indicates the value of read and write parame-
ters in slow clock mode.
Figure 15-30. Read and Write Cycles in Slow Clock Mode
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NCS
NWE
NWECYCLES = 3
SLOW CLOCK MODE WRITE
1
1
1
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NCS
NRD
SLOW CLOCK MODE READ
NRDCYCLES = 2
1
1
Table 15-5. Read and Write Timing Parame ters in Slow Clock Mode
Read Parameters Duration (cycles) Write Parameters Duration (cycles)
NRDSETUP 1 NWESETUP 1
NRDPULSE 1 NWEPULSE 1
NCSRDSETUP 0 NCSWRSETUP 0
NCSRDPULSE 2 NCSWRPULSE 3
NRDCYCLE 2 NWECYCLE 3
208
32072H–AVR32–10/2012
AT32UC3A3
15.6.8.2 Switching from (to) slow clock mode to (from) normal mode
When switching from slow clock mode to the normal mode, the current slow clock mode transfer
is completed at high clock rate , with the set of slow clock mode param eters. See Figure 1 5-31
on page 208. The external device may not be fast enough to support such timings.
Figure 15-32 on page 209 illustrates the recommended procedure to properly switch from one
mode to the other.
Figure 15-31. Clock Rate Transition Occurs while the SMC is Performing a Write Operation
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NCS
NWE
Slow Clock Mode
Internal signal from PM
This write cycle finishes with the slow clock mode set
of parameters after the clock rate transition
NWECYCLE = 3
SLOW CLOCK MODE WRITE SLOW CLOCK MODE WRITE
11 1111232
NWECYCLE = 7
NORMAL MODE WRITE
Slow clock mode transition is detected:
Reload Configuration Wait State
209
32072H–AVR32–10/2012
AT32UC3A3
Figure 15-32. Recommended Procedure to Switch from Slow Clock Mode to Normal Mode or from Normal Mode to Slow
Clock Mode
15.6.9 Asynchronous Page Mode
The SMC supp orts asynchronous burst read s in page mode, p roviding that the Page M ode
Enabled bit is written to one in the MODE register (MODE.PMEN). The page size must be con-
figured in the Page Size field in the MODE register (MODE.PS) to 4, 8, 16, or 32 bytes.
The page defines a set of consecutive bytes into memory. A 4-byte page (resp. 8-, 16-, 32-byte
page) is always aligned to 4-byte bo undaries (r esp. 8- , 16-, 32-byte bo undaries) of memo ry. The
MSB of data address defines the address of the page in memory, the LSB of address define the
address of the data in the page as detailed in Table 15-6 on page 209.
With page mode memory devices, the first access to one page (tpa) takes longer than the su bse-
quent accesses to the page (tsa) as shown in Figure 15-33 on page 210. When in page mode,
the SMC enables the user to define different read timings for the first access within one page,
and next accesses within the page.
Notes: 1. A denotes the address bus of the memory device
2. For 16-bit devices, the bit 0 of address is ignored.
15.6.9.1 Protocol and timings in page mode
Figure 15-33 on page 210 shows the NRD and NCS timings in page mode access.
CLK_SMC
Slow Clock Mode
Internal signal from PM
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NWE
NCS
11
SLOW CLOCK MODE WRITE
23 2
IDLE STATE
Reload Configuration
Wait State
NORMAL MODE WRITE
1
Table 15-6. Page Address and Data Address within a Page
Page Size Page Address(1) Data Address in the Page(2)
4 bytes A[23:2] A[1:0]
8 bytes A[23:3] A[2:0]
16 bytes A[23:4] A[3:0]
32 bytes A[23:5] A[4:0]
210
32072H–AVR32–10/2012
AT32UC3A3
Figure 15-33. Page Mode Read Protocol (Address MSB and LSB Are Defined in Table 15-6 on page 209)
The NRD and NCS signals are held low d ur ing all rea d tra nsfers, whate ver th e prog ra mmed val-
ues of the setup and hold timings in the User Interface may be. Moreover, the NRD and NCS
timings are identical. The pulse length of the first access to the page is defined with the
PULSE.NCSRDPULSE field value. The pulse length of subsequent acce sses within the page
are defined using the PULSE.NRDPULSE field value.
In page mode, th e programming of the read timings is described in Table 15-7 on page 210:
The SMC does not check the c oherency of timings. It will always apply the NCSRDPULSE tim-
ings as page access timing (t pa) and the NRDPULSE for accesses to the page (tsa), even if the
programmed value for tpa is shorter than the programmed value for tsa.
15.6.9.2 Byte access type in page mode
The byte access t ype conf iguratio n remain s act ive in page mo de. For 16- bit or 3 2-bit p age mode
devices that require byte selection signals, configure the MODE.BAT bit to zero (byte select
access type).
CLK_SMC
A[MSB]
A[LSB]
NCS
NRD
D[15:0]
tpa
NCSRDPULSE
tsa
NRDPULSE NRDPULSE
tsa
Table 15-7. Programming of Read Timings in Page Mode
Parameter Value Definition
READMODE ‘x’ No impact
NCSRDSETUP ‘x’ No impact
NCSRDPULSE tpa Access time of first access to the page
NRDSETUP ‘x’ No impact
NRDPULSE tsa Access time of subsequent accesses in the page
NRDCYCLE ‘x’ No impact
211
32072H–AVR32–10/2012
AT32UC3A3
15.6.9.3 Page mode restriction
The page mode is not com patible with the use of the NWAIT signal. Using the page mode an d
the NWAIT signal may lead to unpredictable behavior.
15.6.9.4 Sequential and non-sequential accesses
If the chip select and the MSB of addresses as defined in Table 15-6 on page 209 are identical,
then the curr ent access lies in the same page as the previous one, and no page break occurs.
Using this information, all da ta wit hin th e sa me pa ge, seq uen tia l or not sequent ial, are acce ssed
with a minimum access time (tsa). Figure 15-34 on page 211 illustrates access to an 8-bit mem-
ory device in page mode, with 8-byte pages. Access to D1 causes a page access with a long
access time (tpa). Accesses to D3 and D7, though they are not sequentia l accesse s, only requ ire
a short access time (tsa).
If the MSB of addresses are different, the SMC performs the access of a new page. In the same
way, if the chip select is different from the previous access, a page break occurs. If two sequen-
tial accesses are mad e to the page mode memory , but separated by an other internal or externa l
peripheral access , a page break occurs on the sec ond access because the chip s elect of the
device was deasserted between both accesses.
Figure 15-34. Access to Non-sequential Data within the Same Page
CLK_SMC
A[AD_MSB:3]
A[2], A1, A0
NCS
NRD
D[7:0]
A1
Page address
A3 A7
D1 D3 D7
NCSRDPULSE NRDPULSE NRDPULSE
212
32072H–AVR32–10/2012
AT32UC3A3
15.7 User Interface
The SMC is programmed using the registers listed in Table 15-8 on page 212. For ea ch chip se lect, a set of f our re gisters
is used to program the parameters of the external device connected on it. In Table 15-8 on page 212, “CS_number”
denotes the chip select number. Sixteen bytes (0x10) are re quired per chip select.
The user must complete writing the configuration by writing anyone of the Mode Registers.
Table 15-8. SMC Register Memory Map
Offset Register Register Name Access Reset
0x00 + CS_number*0x10 Setup Register SETUP Read/Write 0x01010101
0x04 + CS_number*0x10 Pulse Register PULSE Read/Write 0x01010101
0x08 + CS_number*0x10 Cycle Register CYCLE Read/Write 0x00030003
0x0C + CS_number*0x10 Mode Register MODE Read/Write 0x10002103
213
32072H–AVR32–10/2012
AT32UC3A3
15.7.1 Setup Register
Register Name: SETUP
Access Type: Read/Write
Offset: 0x00 + CS_number*0x10
Reset Value: 0x01010101
• NCSRDSETUP: NCS Setup Length in READ Access
In read access, the NCS signal setup length is defined as:
• NRDSETUP: NRD Setup Length
The NRD signal setup length is defined in clock cycles as:
• NCSWRSETUP: NCS Setup Length in WRITE Access
In write access, the NCS signal setup length is defined as:
• NWESETUP: NWE Setup Length
The NWE signal setup length is defined as:
31 30 29 28 27 26 25 24
–– NCSRDSETUP
23 22 21 20 19 18 17 16
–– NRDSETUP
15 14 13 12 11 10 9 8
–– NCSWRSETUP
76543210
–– NWESETUP
NCS Setup Length in read access 128 NCSRDSETUP 5[] NCSRDSETUP 4:0[]+×() clock cycles=
NRD Setup Length 128 NRDSETUP 5[] NRDSETUP 4:0[]+×() clock cycles=
NCS Setup Length in write access 128 NCSWRSETUP 5[] NCSWRSETUP 4:0[]+×() clock cycles=
NWE Setup Length 128 NWESETUP 5[] NWESETUP 4:0[]+×() clock cycles=
214
32072H–AVR32–10/2012
AT32UC3A3
15.7.2 Pulse Re gi st er
Register Name: PULSE
Access Type: Read/Write
Offset: 0x04 + CS_number*0x10
Reset Value: 0x01010101
• NCSRDPULSE: NCS Pulse Length in READ Access
In standard read access, the NCS signal pulse length is defined as:
The NCS pulse length must be at least one clock cycle.
In page mode read access, the NCSRDPULSE field defines the duration of the first access to one page.
• NRDPULSE: NRD Pulse Length
In standard read access, the NRD signal pulse length is defined in clock cycles as:
The NRD pulse length must be at least one clock cycle.
In page mode read access, the NRDPULSE field defines the duration of the subsequent accesses in the page.
• NCSWRPULSE: NCS Pulse Length in WRITE Access
In write access, the NCS signal pulse length is defined as:
The NCS pulse length must be at least one clock cycle.
• NWEPULSE: NWE Pulse Length
The NWE signal pulse length is defined as:
The NWE pulse length must be at least one clock cycle.
31 30 29 28 27 26 25 24
–NCSRDPULSE
23 22 21 20 19 18 17 16
–NRDPULSE
15 14 13 12 11 10 9 8
–NCSWRPULSE
76543210
–NWEPULSE
NCS Pulse Length in read access 256 NCSRDPULSE 6[] NCSRDPULSE 5:0[]+×() clock cycles=
NRD Pulse Length 256 NRDPULSE 6[] NRDPULSE 5:0[]+×() clock cycles=
NCS Pulse Length in write access 256 NCSWRPULSE 6[] NCSWRPULSE 5:0[]+×() clock cycles=
NWE Pulse Length 256 NWEPULSE 6[] NWEPULSE 5:0[]+×() clock cycles=
215
32072H–AVR32–10/2012
AT32UC3A3
15.7.3 Cycle Register
Register Name: CYCLE
Access Type: Read/Write
Offset: 0x08 + CS_number*0x10
Reset Value: 0x00030003
• NRDCYCLE[8:0]: Total Read Cycle Length
The total read cycle length is the total duration in clock cycles of the read cycle. It is equal to the sum of the setup, pulse and
hold steps of the NRD and NCS signals. It is defined as:
• NWECYCLE[8:0]: Total Write Cycle Length
The total write cycle length is the total duration in clock cycles of the write cycle. It is equal to the sum of the setup, pulse and
hold steps of the NWE and NCS signals. It is defined as:
31 30 29 28 27 26 25 24
–––––––
NRDCYCLE[8]
23 22 21 20 19 18 17 16
NRDCYCLE[7:0]
15 14 13 12 11 10 9 8
–––––––
NWECYCLE[8]
76543210
NWECYCLE[7:0]
Read Cycle Length 256 NRDCYCLE 8:7[]NRDCYCLE 6:0[]+×() clock cycles=
Write Cycle Length 256 NWECYCLE 8:7[]NWECYCLE 6:0[]+×() clock cycles=
216
32072H–AVR32–10/2012
AT32UC3A3
15.7.4 Mode Register
Register Name: MODE
Access Type: Read/Write
Offset: 0x0C + CS_number *0x10
Reset Value: 0x10002103
• PS: Page Size
If page mode is enabled, this field indicates the size of the page in bytes.
• PMEN: Page Mode Enabled
1: Asynchronous burst read in page mode is applied on the corresponding chip select.
0: Standard read is applied.
• TDFMODE: TDF Optimization
1: TDF optimization is enabled. The number of TDF wait states is optimized using the setup pe riod of the next read/write
access.
0: TDF optimization is disabled.The number of TDF wait states is inserted before the next access begins.
• TDFCYCLES: Data Float Time
This field give s the integer number of clock cycles required b y the e xternal de vic e to release the data after the rising edge of the
read controlling signal. The SMC always provide one full cycle of bus turnaround after the TDFCYCLES period. The external
bus cannot be used by another chip select during TDFCYCLES plus one cycles. From 0 up to 15 TDFCYCLES can be set.
31 30 29 28 27 26 25 24
–– PS –––
PMEN
23 22 21 20 19 18 17 16
–––
TDFMODE TDFCYCLES
15 14 13 12 11 10 9 8
–– DBW –––
BAT
76543210
–– EXNWMODE ––WRITEMODE
READMODE
PS Page Size
0 4-byte page
1 8-byte page
2 16-byte page
3 32-byte page
217
32072H–AVR32–10/2012
AT32UC3A3
• DBW: Data Bus Width
• BAT: Byte Access Type
This field is used only if DBW defi nes a 16-bit data bus.
• EXNWMODE: External WAIT Mode
The NWAIT signal is used to extend the current read or write signal. It is only taken into account during the pulse phase of the
read and write controlling signal. When the use of NWAIT is enabled, at least one cycle hold duration must be programmed for
the read and write controlling signal.
• WRITEMODE: Write Mode
1: The write operation is controlled by the NWE signal. If TDF optimization is enabled (TDFMODE =1), TDF wait states will be
inserted after the setu p of NWE.
0: The write operation is controlled by the NCS signal. If TDF optimization is enabled (TDFMODE =1), TDF wait states will be
inserted after the setup of NCS.
DBW Data Bus Width
08-bit bus
116-bit bus
2 Reserved
3 Reserved
BAT Byte Access Type
0Byte select access type:
Write operation is controlled using NCS, NWE, NBS0, NBS1
Read operation is controlled using NCS, NRD, NBS0, NBS1
1Byte write access type:
Write operation is controlled using NCS, NWR0, NWR1
Read operation is controlled using NCS and NRD
EXNWMODE External NWAIT Mode
0Disabled:
the NWAIT input signal is ignored on th e corresponding chip select.
1 Reserved
2Frozen Mode:
if asserted, the NW AIT signal freezes the current read or write cycle. after deassertion, the read or write cycle
is resumed from the point where it was stopped.
3
Ready Mode:
the NWAIT signal indicates the availability of the external device at the end of the pulse of the controlling read
or write signal, to complete the access. If high, the acce ss normally completes. If low, the access is extended
until NWAIT returns high.
218
32072H–AVR32–10/2012
AT32UC3A3
• READMODE: Read Mode
READMODE Read Access Mode
0The read operation is controlled by the NCS signal.
If TDF are programmed, the external bus is marked busy after the rising edge of NCS.
If TDF optimization is enabled (TDFMODE = 1), TDF wait states are inserted after the setup of NCS.
1The read operation is controlled by the NRD signal.
If TDF cycles are programmed, the external bus is marked busy after the ri sing edge of NRD.
If TDF optimization is enabled (TDFMODE =1), TDF wait state s are inserted after the setup of NRD.
219
32072H–AVR32–10/2012
AT32UC3A3
16. SDRAM Controller (SDRAMC)
Rev: 2.2.0.4
16.1 Features •128-Mb ytes address space
•Numerous configurations supported
– 2K, 4K, 8K row address memory parts
– SDRAM with two or four internal banks
– SDRAM with 16-bit data path
•Programming facilities
– Word, halfword, byte access
– Automatic page break when memory boundary has been re ached
– Multibank ping-pong access
– Timing parameters specified by software
– Automatic refresh operation, refresh rate is programmable
– Automatic update of DS, TCR and PASR parame ters (mobile SDRAM devices)
•Energy-saving capabilities
– Self-refresh, power-down, and deep power-down modes supported
– Supports mobile SDRAM devices
•Error detection
– Refresh error interrupt
•SDRAM power-up initialization by software
•CAS latency of one, two , and three supp orted
•A uto Prechar ge com m an d not used
16.2 Overview The SDRAM Controller (SDRAMC) extends the memory capabilities of a chip by providing the
interface to an exter nal 16-bit SDRAM device. The pag e size supports ranges fr om 2048 to 8192
and the number of columns from 256 to 2048. It supports byte (8-bit) and halfword (16-bit)
accesses.
The SDRAMC supports a read or write burst length of one location. It keeps track of the active
row in each bank, thus maximizing SDRAM performance, e.g., the application may be placed in
one bank and data in the other banks. So a s to optimize performance, it is advisable to avoid
accessing different rows in the same bank.
The SDRAMC supports a CAS latency of one, two, or three and optimizes the read access
depending on the frequency.
The different modes available (self refresh, power-down, and deep power-down modes) mini-
mize power consumption on the SDRAM device.
220
32072H–AVR32–10/2012
AT32UC3A3
16.3 Block Diagram
Figure 16-1. SDRAM Controller Block Diagram
16.4 I/O Lines Description
Memory
Controller
Power
Manager
CLK_SDRAMC
SDRAMC
Chip Select
SDRAMC
Interrupt
SDRAMC
User Interface
Peripheral Bus
I/O
Controller
SDCS
SDCK
SDCKE
BA[1:0]
RAS
CAS
SDWE
DQM[0]
SDRAMC_A[9:0]
D[15:0]
EBI
MUX Logic
DATA[15:0]
SDCK
SDCKE
NCS[1]
RAS
CAS
ADDR[17:16]
SDWE
ADDR[0]
DQM[1] NWE1
ADDR[11:2]
SDRAMC_A[10] SDA10
SDRAMC_A[12:11]
ADDR[13:14]
Table 16-1. I/O Lines Descrip tion
Name Description Type Active Level
SDCK SDRAM Clock Output
SDCKE SDRAM Clock Enable Output H igh
SDCS SDRAM Chip Select Output Low
BA[1:0] Bank Select Signals O utput
RAS Row Signal Output Low
CAS Column Signal Output Low
SDWE SDRAM Write Enable Output Low
221
32072H–AVR32–10/2012
AT32UC3A3
16.5 Application Example
16.5.1 Hardware Interface
Figure 16-2 on page 221 shows an example of SDRAM device connection using a 16-bit data
bus width. It is important to note that this example is given for a direct connection of the devices
to the SDRAMC, without External Bus Interface or I/O Controller multiplexing.
Figure 16-2. SDRAM Controller Connections to SDRAM Devices: 16-bit Data Bus Width
16.5.2 Software Inte rfa ce
The SDRAM address space is organized into banks, rows, and colum ns. The SDRAMC allows
mapping differe nt me mor y t ypes a c cord ing to the valu es set in t he SDRAMC Configu ra tion Re g-
ister (CR).
The SDRAMC’s function is to make the SDRAM device access protocol transparent to the user.
Table 16-2 on page 222 to Table 16-4 on page 222 illustrate the SDRAM device memory map-
ping seen by the user in correlation with the device structure. Various configurations are
illustrated.
DQM[1:0] Data Mask Enable Signals Output High
SDRAMC_A[12:0] Address Bus Output
D[15:0] Data Bus Input/Output
Table 16-1. I/O Lines Descrip tion
Name Description Type Active Level
2Mx8
SDRAM
D0-D7
CS
DQM
CLK
CKE
WE
RAS
CAS
A0-A9 A11
BA0
A10
BA1
SDRAMC_A10
BA0
BA1
2Mx8
SDRAM
D0-D7
CS
DQM
CLK
CKE
WE
RAS
CAS
A0-A9 A11
BA0
A10
BA1
SDRAMC_A10
BA0
BA1
SDCS
BA1
BA0
SDRAMC_A[0-12]
SDRAM
Controller
DQM[0-1]
SDWE
SDCKE
SDCK
CAS
RAS
D0-D31
DQM0
D0-D7 D8-D15
DQM1
222
32072H–AVR32–10/2012
AT32UC3A3
16.5.2.1 16-bit memory data bus width
Notes: 1. M0 is the byte address inside a 16-bit halfword.
16.6 Product Dependencies
In order to use t his modu le, othe r p arts o f th e syst em must be conf igu red cor re ctly, as de scr ibed
below.
16.6.1 I/O Lines The SDRAMC module signals pass through the External Bus Interface (EBI) module where they
are multiplexed. The user must first configure the I/O controller to assign the EBI pins corre-
sponding to SDRAMC signals to t hei r per iph eral f unct ion . If I /O lin es o f th e EBI corr espo nd ing to
SDRAMC signals are not used by the application, they can be used for other purposes by the
I/O Controller.
16.6.2 Power Management
The SDRAMC must be properly stopped before enter ing in reset mode, i.e., the user must issue
a Deep power mode command in the Mode (MD) register and wait for the command to be
completed.
Table 16-2. SDRAM Configuration Mapping: 2K Rows, 256/512/1024/2048 Columns
CPU Address Line
272625242322212019181716151413121110987654321 0
BA[1:0] Row[10:0] Column[7:0] M0
BA[1:0] Row[10:0] Column[8:0] M0
BA[1:0] Row[10:0] Column[9:0] M0
BA[1:0] Row[10:0] Column[10:0] M0
Table 16-3. SDRAM Configuration Mapping: 4K Rows, 256/512/1024/2048 Columns
CPU Address Line
272625242322212019181716151413121110987654321 0
BA[1:0] Row[11:0] Column[7:0] M0
BA[1:0] Row[11:0] Column[8:0] M0
BA[1:0] Row[11:0] Column[9:0] M0
BA[1:0] Row[11:0] Column[10:0] M0
Table 16-4. SDRAM Configuration Mapping: 8K Rows, 256/512/1024/2048 Columns
CPU Address Line
272625242322212019181716151413121110987654321 0
BA[1:0] Row[12:0] Column[7:0] M0
BA[1:0] Row[12:0] Column[8:0] M0
BA[1:0] Row[12:0] Column[9:0] M0
BA[1:0] Row[12:0] Column[10:0] M0
223
32072H–AVR32–10/2012
AT32UC3A3
16.6.3 Clocks The clock for the SDRAMC bus interface (CLK_SDRAMC) is generated by the Power Manager.
This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to
disable the SDRAMC before disabling the clock, to avoid freezing the SDRAMC in an undefined
state.
16.6.4 Interrupts The SDRAMC interrupt request line is connected to the interrupt controller. Using the SDRAMC
interrupt requires the interrupt controller to be programmed first.
16.7 Functional Description
16.7.1 SDRAM Device Initialization
The initialization sequence is generated by software. The SDRAM devices are initialized by the
following sequence:
1. SDRAM features must be defined in the CR register by writing the following fields with
the desired value: asynchronous timings (TXSR, TRAS, TRCD, TRP, TRC, and TWR),
Number of Columns (NC), Number of Ro ws (NR), Number o f Banks (NB), CAS Latency
(CAS), and the Data Bus Width (DBW).
2. For mobile SDRAM devices, Temperature Compensated Self Refresh (TCSR), Drive
Strength (DS) and Partial Array Self Refresh (PASR) fields must be defined in the Low
Power Register (LPR).
3. The Memory Device Type field must be defined in the Memory Device Register
(MDR.MD).
4. A No Operation (NOP) command must be issued to the SDRAM devices to start the
SDRAM clock. The user must write the value on e to the Command Mode field in the
SDRAMC Mode Register (MR.MODE) and perform a write access to any SDRAM
address.
5. A minimum pause of 200µs is provided to precede any signal toggle.
6. An All Banks Precharge command must be issued to the SDRAM devices. The user
must write the value two to the MR.MODE field and perform a write access to any
SDRAM address.
7. Eight Auto Refresh commands are provided. The user must write the value four to the
MR.MODE field and performs a write access to any SDRAM location eight times.
8. A Load Mode Register command must be issued to program the parameters of the
SDRAM devices in its Mode Register, in particular CAS latency, burst type, and burst
length. The user must write the value three to the MR.MODE field and perform a write
access to the SDRAM. The write address must be chosen so that BA[1:0] are set to
zero. See Section 16.8.1 for details about Lo ad Mode Register command.
9. For mobile SDRAM initialization, an Extended Load Mode Register command must be
issued to program the SDRAM devices parameters (TCSR, PASR, DS). The user must
write the value five to the MR.MODE field and perform a write access to the SDRAM.
The write address must be chosen so th at BA[1] or BA[0] are equal to one . See Section
16.8.1 for details about Extended Load Mode Register comma nd.
10. The user must go int o Normal Mode, writing the value 0 to the MR.MODE field and per-
forming a write access at any location in the SDRAM.
11. Write the refresh rate into the Refresh Timer Count field in the Refresh Timer Register
(TR.COUNT). The refresh r ate is the dela y between two successiv e refresh cycles. The
SDRAM device requires a refresh every 15.625µs or 7.81µs. With a 100MHz fre-
224
32072H–AVR32–10/2012
AT32UC3A3
quency, the TR register must be written with the value 1562 (15.625 µs x 100 MHz) or
781 (7.81 µs x 100 MHz).
After initialization, the SDRAM devices are fully functional.
Figure 16-3. SDRAM Device Initialization Sequence
16.7.2 SDRAM Controller Write Cycle
The SDRAMC allow s bu rs t acc es s or sing le a ccess. In both cases, the SDRAMC keeps track of
the active row in each bank, thus maximizing performance. To initiate a burst access, the
SDRAMC uses the transfer type sig nal pro vided by the master requesting the access. If the next
access is a sequential write access, writing to the SDRAM device is carried out. If the next
access is a write-sequential access, but the current access is to a boundary page, or if the next
access is in another row, then the SDRAMC generates a precharge command, activates the
new row and initiates a write command. To c omply with SDRAM timing pa rameters, addit ional
clock cycles are inserted between precharge and active (tRP) commands and between active
and write (tRCD) commands. For definition of these timing parameters, refer to the Section
16.8.3. This is described in Figure 16-4 on page 225.
SDCKE
SDCK
SDRAMC_A[9:0]
A10
SDRAMC_A[12:11]
SDCS
RAS
CAS
SDWE
DQM
Inputs Stable for
200 usec
Valid CommandPrecharge All Banks 1st Auto Refresh 8th Auto Refresh LMR Command
tMRD
tRC
tRP
225
32072H–AVR32–10/2012
AT32UC3A3
Figure 16-4. Write Burst, 16-bit SDRAM Access
16.7.3 SDRAM Controller Read Cycle
The SDRAMC allows burst access, incremental burst of unspecified length or single access. In
all cases, the SDRAMC keeps track of the active row in each bank, thus maximizing perfor-
mance of the SDRAM. If row and bank addresses do not match the previous row/bank address,
then the SDRAMC automatically generates a precharge command, activates the new row and
starts the read command. To comply with the SDRAM timing parameters, additional clock cycles
on SDCK are inserted between precharge and ac tive (tRP) commands and between active and
read (tRCD) com mands. These two para meters are set in t he CR regist er of t he SDRAMC. Af ter a
read command, additional wait states are generated to comply with the CAS latency (one, two,
or three clock delays specified in the CR register).
For a single a cces s or an incre men ted burs t of un spec ified leng th, t he SDRA MC anticip ates the
next access. While the last value of the column is returned by the SDRAMC on the bus, the
SDRAMC anticipates the read to the next column and thus anticipates the CAS latency. This
reduces the effect of the CAS latency on the internal bus.
For burst acc ess of specified leng th (4, 8, 16 words) , access is not antic ipated. This ca se leads
to the best performa nce. If the bur st is br oken (bor de r, busy mode , etc.) , t he next acce ss is han-
dled as an incrementing burst of unspecified length.
SDCS
tRCD = 3
SDCK
SDRAMC_A[12:0]
RAS
CAS
SDWE
D[15:0] Dna Dnb Dnc Dnd Dne Dnf Dng Dnh Dni Dnj Dnk Dnl
Row n Col b Col c Col d Col e Col f Col g Col h Col i Col k Col l
Col j
Col a
226
32072H–AVR32–10/2012
AT32UC3A3
Figure 16-5. Read Burst, 16-bit SDRAM Access
16.7.4 Border Management
When the memory row bo un dary has been rea ched , an aut oma ti c pa ge brea k is insert e d. In t his
case, the SDRAMC generates a pre charge command, activates the ne w row and initiate s a read
or write command. To comply with SDRAM timing parameters, an additional clock cycle is
inserted between the precharg e and active (tRP) commands and between the active an d read
(tRCD) commands. This is described in Figure 16-6 on page 227.
SDCS
D[15:0]
(Input)
SDCK
SDRAMC_A[12:0]
RAS
CAS
SDWE
Dna Dnb Dnc Dnd Dne Dnf
Col a Col b Col c Col d Col e Col fRow n
CAS = 2tRCD = 3
227
32072H–AVR32–10/2012
AT32UC3A3
Figure 16-6. Read Burst with Boundary Row Access
16.7.5 SDRAM Controller Refresh Cycles
An auto refresh command is used to refresh the SDRAM device. Refresh addresses are gener-
ated internally by the SDRAM device and incremented after each auto refresh automatically.
The SDRAMC generates these auto refresh commands periodically. An internal timer is loaded
with the value in the Refresh Timer Register (TR) that indicates the number of clock cycles
between successive refresh cycles.
A refresh error interrupt is generated when the previous auto refresh command did not perform.
In this case a Refresh Error Status bit is set in the Interrupt Status Register (ISR.RES). It is
cleared by readin g th e IS R re gist er .
When the SDRAMC initiates a refresh of the SDRAM device, internal memory accesses are not
delayed. However, if the CPU tries to access the SDRAM, the slave indicates that the device is
busy and the master is held by a wait signal. See Figure 16-7 on page 228.
SDCS
SDCK
SDRAMC_A[12:0]
CAS
RAS
SDWE
D[15:0] Dna Dnb Dnc Dnd Dma Dmb Dmc DmeDmd
Row m Col a Col b Col c Col d Col e
Row n
Col a Col b Col c Col d
CAS = 2
TRCD = 3
TRP = 3
228
32072H–AVR32–10/2012
AT32UC3A3
Figure 16-7. Refresh Cycle Followed by a Read Access
16.7.6 Power Management
Three low power mod es ar e av aila ble :
• Self refresh mode: the SDRAM executes its own auto refresh cycles without control of the
SDRAMC. Current drained by the SDRAM is very low.
• P o wer-down mo de: auto refresh cycles are contr olled by the SDRAMC . Between au to refresh
cycles, the SDRAM is in power-down. Current drained in power-down mode is higher than in
self refresh mode.
• Deep po w e r-down mode (only a vailable with mobile SDRAM): t he SDRAM cont ents are lost,
but the SDRAM does not drain any current.
The SDRAMC activates one low power mode as soon as the SDRAM device is not selected. It is
possible to delay the entry in self refresh and power-down mode after the last access by config-
uring the Timeout field in the Low Power Register (LPR.TIMEOUT).
16.7.6.1 Self refresh mode
This mode is selected by writing the value one to the Low Power Configuration Bits field in the
SDRAMC Low Power Register (LPR.LPCB). In s elf refresh mode, the SDRAM device retains
data without external clocking and provides its own internal clocking, thus performing its own
auto refresh cycles. All the inputs to the SDRAM device become “don’t care” except SDCKE,
which remains low. As soon as the SDRAM device is selected, the SDRAMC provides a
sequence of commands and exits self refresh mode.
Some low power SDRAMs (e.g., mobile SDRAM) can refresh only one quarter or a half quarter
or all banks of the SDRAM array. This feature reduces the self refresh current. To configure this
feature, Temperature Compensated Self Refresh (TCSR), Partial Array Self Refresh (PASR)
SDCS
SDCK
SDRAMC_A[12:0]
Row n
Col c Col d
RAS
CAS
SDWE
D[15:0]
(input) Dnb Dnc Dnd Dma
Col a
Row m
CAS = 2tRCD = 3tRC = 8tRP = 3
229
32072H–AVR32–10/2012
AT32UC3A3
and Drive Strength (DS) parameters must be set by writing the corresponding fields in the LPR
register, and transmitted to the low power SDRAM device during initialization.
After initialization, as soon as the LPR.PASR, LPR.DS, or LPR.TCSR fields are modified and
self refresh mode is acti vated, the SDRAMC issues an Ext ended Lo ad Mode Reg ister command
to the SDRAM and the Extended Mode Register of the SDRAM de vice is accessed automati-
cally. The PASR/DS/TCSR parameters values are therefore updated before entry into self
refresh mo d e.
The SDRAM device must remain in self refr esh mode for a minimum period of tRAS and may
remain in self refresh mode for an indefinite period. This is described in Figure 16-8 on page
229.
Figure 16-8. Self Refresh Mode Behavior
16.7.6.2 Low power mode
This mode is selected by writing the value two to the LPR.LPCB field. Power consumption is
greater than in self refresh mode. All the input and output buffers of the SDRAM device are
deactivated except SDCKE, which remains low. In contrast to self refresh mode, th e SDRAM
device cannot remain in low power mode longer than the refresh period (64 ms for a whole
device ref resh op erat ion) . As no au t o ref re sh o per ation s ar e p er form ed by the SDRAM itse lf, t he
SDRAMC carries out the refresh operation. The exit procedure is faster than in self refresh
mode.
This is described in Figure 16-9 on page 230.
SDRAMC_A[12:0]
SDCK
SDCKE
SDCS
RAS
CAS
Access Request
To the SDRAM Controller
Self Refresh Mode
Row
TXSR = 3
SDWE
230
32072H–AVR32–10/2012
AT32UC3A3
Figure 16-9. Low Power Mode Behavior
16.7.6.3 Deep power-down mode
This mode is selected by writing the value three to the LPR.LPCB field. When this mode is acti-
vated, all internal voltage generators inside the SDRAM are stopped and all data is lost.
When this mode is enabled, the user must not access to the SDRAM until a new initialization
sequence is done (See Section 16.7.1).
This is described in Figure 16-10 on page 23 1.
Low Power Mode
CAS = 2TRCD = 3
SDCS
SDCK
SDRAMC_A[12:0]
RAS
CAS
SDCKE
D[15:0]
(input) Dna Dnb Dnc Dnd Dne Dnf
Col fCol eCol dCol cCol bCol aRow n
231
32072H–AVR32–10/2012
AT32UC3A3
Figure 16-10. Deep Power-down Mode Behavior
SDCS
SDCK
SDRAMC_A[12:0]
RAS
CAS
SDWE
SCKE
D[15:0]
(Input) Dnb Dnc Dnd
Col dCol c
Row n
tRP = 3
232
32072H–AVR32–10/2012
AT32UC3A3
16.8 User Interface
Table 16-5. SDRAMC Register Memory Map
Offset Register Register Name Access Reset
0x00 Mode Register MR Read/Write 0x00000000
0x04 Refresh Timer Register TR Read/Write 0x00000000
0x08 Configuration Register CR Read/Write 0x852372C0
0x0C High Speed Register HSR Read/Write 0x00000000
0x10 Low Power Register LPR Read/Write 0x00000000
0x14 Interrupt Enable Register IER Write-only 0x00000000
0x18 Interrupt Disable Register IDR Write-only 0x00000000
0x1C Interrupt Mask Register IMR Read-only 0x00000000
0x20 Interrupt Status Register ISR Read-only 0 x 00000000
0x24 Memory Device Register MDR Read/Write 0x00000000
0xFC Version Register VERSION Re ad-only - (1)
1. The reset values for these fields are device specific. Please refer to the Module Configuration section at the end of this chap-
ter.
233
32072H–AVR32–10/2012
AT32UC3A3
16.8.1 Mode Register
Register Name:MR
Access Type: Read/Write
Offset: 0x00
Reset Value: 0x00000000
• MODE: Command Mode
This field defines the command issued by the SDRAMC when the SDRAM device is accessed.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
----- MODE
MODE Description
0 Normal mode. Any acc ess to the SDRAM i s decod e d normally.
1 The SDRAMC issues a “NOP” command when the SDRAM device is accessed regardless of th e cycle.
2The SDRAMC issues an “All Banks Precharge” command when the SDRAM device is accessed regardless of
the cycle.
3
The SDRAMC issues a “Load Mode Register” command when the SDRAM device is accessed regardless of the
cycle. This command will load the CR.CAS field into the SDRAM de vice Mode Register. All the other parameters
of the SDRAM device Mode Register will be set to zero (burst length, burst type, operating mode, write burst
mode...).
4The SDRAMC issues an “Auto Refresh” command when the SDRAM de vice is accessed regardless of the cycle.
Previously, an “All Banks Precharge” command must be issued.
5
The SDRAMC issues an “Extended Load Mode Register” command when the SDRAM device is accessed
regardless of the cycle. This command will load the LPR.PASR, LPR.DS, and LPR.TCR fields into the SDRAM
device Extended Mode Re gister. All the other bits of the SDRAM device Extended Mode Register will be set to
zero.
6 Deep power-down mode. Enters deep power-down mode.
234
32072H–AVR32–10/2012
AT32UC3A3
16.8.2 Refresh Timer Register
Register Name:TR
Access Type: Read/Write
Offset: 0x04
Reset Value: 0x00000000
• COUNT[11:0]: Refresh Timer Count
This 12-bit field is loaded into a timer that generates the refresh pulse. Each time the refresh pulse is generated, a refresh burst
is initiated.
The value to be loaded depends on the SDRAMC clock frequency (CLK_SDRAMC), the refresh rate of the SDRAM device and
the refresh burst length where 15.6µs per row is a typical value for a burst of length one.
To refresh the SDRAM device, this 12-bit field must be written. If this condition is not sa tisfied, no refresh command is issued
and no refresh of the SDRAM device is carried out.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
- - - - COUNT[11:8]
76543210
COUNT[7:0]
235
32072H–AVR32–10/2012
AT32UC3A3
16.8.3 Configuration Register
Register Name:CR
Access Type: Read/Write
Offset: 0x08
Reset Value: 0x852372C0
• TXSR: Exit Self Refresh to Active Delay
Reset value is eight cycles.
This field defines the delay between SCKE set high and an Activate command in nu mber of cycles. Number of cycles is between
0 and 15.
• TRAS: Active to Precharge Delay
Reset value is five cycles.
This field defines the delay between an Activ ate command and a Precharge command in number of cycles . Number of cycles is
between 0 and 15.
• TRCD: Row to Column Delay
Reset value is two cycles.
This field defines the delay between an Activate command and a Read/Write command in number of cycles. Number of cycles
is between 0 and 15.
• TRP: Row Precharge Delay
Reset value is three cycles.
This field defines the delay between a Precharge command and another command in number of cycles. Number of cycles is
between 0 and 15.
• TRC: Row Cycle Delay
Reset value is seven cycles.
This field defines the delay between a Refresh and an Activate Co mmand in number of cycles. Number of cycles is between 0
and 15.
• TWR: Write Recovery Delay
Reset value is two cycles.
This field defines the Wr ite Recovery Time in number of cycles. Number of cycles is between 0 and 15.
• DBW: Data Bus Width
Reset value is 16 bits.
0: Reserved.
1: Data bus width is 16 bits.
31 30 29 28 27 26 25 24
TXSR TRAS
23 22 21 20 19 18 17 16
TRCD TRP
15 14 13 12 11 10 9 8
TRC TWR
76543210
DBW CAS NB NR NC
236
32072H–AVR32–10/2012
AT32UC3A3
• CAS: CAS Latency
Reset value is two cycles.
In the SDRAMC, only a CAS latency of one, two and three cycles is managed.
• NB: Number of Banks
Reset value is two banks.
• NR: Number of Row Bits
Reset value is 11 row bits.
• NC: Number of Column Bits
Reset value is 8 column bits.
CAS CAS Latency (Cycles)
0Reserved
11
22
33
NB Number of Banks
02
14
NR Row Bits
011
112
213
3Reserved
NC Column Bits
08
19
210
311
237
32072H–AVR32–10/2012
AT32UC3A3
16.8.4 High Speed Register
Register Name:HSR
Access Type: Read/Write
Offset: 0x0C
Reset Value: 0x00000000
• DA: Decode Cycle Enable
A decode cycle can be added on the addresses as soon as a non-sequential access is performed on the HSB bus.
The addition of the decode cycle allows the SDRAMC to gain time to access the SDRAM memory.
1: Decode cycle is enabled.
0: Decode cycle is disabled.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
-------DA
238
32072H–AVR32–10/2012
AT32UC3A3
16.8.5 Low Power Register
Register Name:LPR
Access Type: Read/Write
Offset: 0x10
Reset Value: 0x00000000
• TIMEOUT: Time to Define when Low Power Mode Is Enabled
• DS: Drive Strength (only for low power SDRAM)
This field is transmitted to the SDRAM during initialization to select the SDRAM strength of data output. This parameter m ust be
set according to the SDRAM de vice specification.
After initialization, as soon as this field is modified and self refresh mode is activated, the Extended Mode Register of the
SDRAM device is accessed automatically and its DS parameter value is updated before entry in self refresh mode.
• TCSR: Temperatur e C om pe n sa te d Se lf Re fr es h (only for low powe r SD RAM)
This field is transmitted to the SDRAM during initialization to set the refresh interval during self refresh mode depe nding on the
temperature of the low power SDRAM. This parameter must be set according to the SDRAM device specification.
After initialization, as soon as this field is modified and self refresh mode is activated, the Extended Mode Register of the
SDRAM device is accessed automatically and its TCSR parameter value is updated bef o re entry in self refresh mode.
• PASR: Partial Array Self Refresh (only for low power SDRAM)
This field is transmitted to the SDRAM during initialization to specify whether only one quarter, one half or all ban ks of the
SDRAM array are enabled. Disabled banks are not refreshed in self refresh mode. This parameter must be set according to the
SDRAM device specification.
After initialization, as soon as this field is modified and self refresh mode is activated, the Extended Mode Register of the
SDRAM device is accessed automatical ly and its PASR parameter value is updated before entry in self refresh mode.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
-- TIMEOUT DS TCSR
76543210
- PASR - - LPCB
TIMEOUT Time to Define when Low Power Mode Is Enabled
0 The SDRAMC activates the SDRAM low power mode immediately after the end of the last transfer.
1 The SDRAMC activates the SDRAM low power mode 64 clock cycles after the end of the last transfer.
2 The SDRAMC activates the SDRAM low power mode 128 clock cycles after the end of the last transfer.
3 Reserved.
239
32072H–AVR32–10/2012
AT32UC3A3
• LPCB: Low Power Configuration Bits
LPCB Low Power Configuration
0Low pow er feature is inhibited: no power-do wn, self refresh or deep power-down command is issued to
the SDRAM device.
1The SDRAMC issues a self refresh command to the SDRAM device , the SDCLK cloc k is deactivated and
the SDCKE signal is set low. The SDRAM device leaves the self refresh mode when accessed and
enters it after the access.
2The SDRAMC issues a power-down command to the SDRAM device after each access, the SDCKE
signal is set to low. The SDRAM de vice leaves the pow er-down mode when accessed and enters it after
the access.
3The SDRAMC issues a deep power-down command to the SDRAM device. This mode is unique to low-
power SDRAM.
240
32072H–AVR32–10/2012
AT32UC3A3
16.8.6 Interrupt Enable Register
Register Name:IER
Access Type: Write-only
Offset: 0x14
Reset Value: 0x00000000
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will set the corresponding bit in IMR.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
-------RES
241
32072H–AVR32–10/2012
AT32UC3A3
16.8.7 Interrupt Disable Register
Register Name:IDR
Access Type: Write-only
Offset: 0x18
Reset Value: 0x00000000
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will clear the corresponding bit in IMR.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
-------RES
242
32072H–AVR32–10/2012
AT32UC3A3
16.8.8 Interrupt Mask Register
Register Name:IMR
Access Type: Read-only
Offset: 0x1C
Reset Value: 0x00000000
0: The corresponding interr upt is disabled.
1: The corresponding interrupt is enabled.
A bit in this register is cleared when the corresponding bit in IDR is wr itten to one.
A bit in this register is set when the corresponding bit in IER is written to one.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
-------RES
243
32072H–AVR32–10/2012
AT32UC3A3
16.8.9 Interrupt Status Register
Register Name:ISR
Access Type: Read-only
Offset: 0x20
Reset Value: 0x00000000
• RES: Refresh Error Status
This bit is set when a refresh error is detected.
This bit is cleared when the register is read.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
-------RES
244
32072H–AVR32–10/2012
AT32UC3A3
16.8.10 Memory Device Register
Register Name:MDR
Access Type: Read/Write
Offset: 0x24
Reset Value: 0x00000000
• MD: Memory Device Type
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
------ MD
MD Device Type
0 SDRAM
1 Low power SDRAM
Other Reserved
245
32072H–AVR32–10/2012
AT32UC3A3
16.8.11 Version Register
Register Name: VERSION
Access Type: Read-only
Offset: 0xFC
Reset Value: -
• Variant: Variant Number
Reserved. No functionality associated.
• Version: Version Number
Version number of the module.No functionality associated.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
---- VARIANT
15 14 13 12 11 10 9 8
- - - - VERSION
76543210
VERSION
246
32072H–AVR32–10/2012
AT32UC3A3
17. Error Corrected Code Controller (ECCHRS)
Rev. 1.0.0.0
17.1 Features •Hardware Error Corrected Code Generation with two methods :
– Hamming code detection and corre ction by software (ECC-H)
– Reed-Solomon code detection by hardware, correction by hardware or software (ECC-RS)
•Supports NAND Flash and SmartMedia™ devices with 8- or 16-bit data path for ECC-H, and with
8-bit data path for ECC-RS
•Supports NAND Flash and SmartMedia™ with page sizes of 528, 1056, 2112, and 4224 bytes
(specified by software)
•ECC_H supports :
– One bit correction per page of 512,1024,2048, or 4096 bytes
– One bit correction per sector of 512 bytes of data for a page size of 512, 1024, 2048, or 4096
bytes
– One bit correction per sector of 256 bytes of data for a page size of 512, 1024, 2048, or 4096
bytes
•ECC_RS supports :
– 4 errors correction per sector of 512 bytes of data for a page size of 512, 1024, 2048, and
4096 bytes with 8-bit data path
17.2 Overview NAND Flash and SmartMedia™ devices contain by default invalid blocks which have one or
more invalid bits. Over the NAND Flash and SmartMedia™ lifetime, additional invalid blocks m ay
occur which can be detected and corrected by an Error Correct ed Code (ECC).
The ECC Controller is a mechanism that encodes data in a manner that makes possible the
identification and correction of certain errors in data. The ECC controller is capable of single-bit
error correc tion and t wo-bi t rando m dete ction when using th e Hamming cod e (ECC- H) and up to
four symbols (a symbol is a 8-bit data) correction whatever the number of errors in symbol (1 to
8 bits of error) when using the Reed-Solomon code (ECC-RS).
When NAND Flash/SmartMedia™ have more than two erroneous bits when using the Hamming
code (ECC-H) or more tha n four bits in e rror when using the Reed -Solomon code ( ECC-RS), the
data canno t be corrected.
247
32072H–AVR32–10/2012
AT32UC3A3
17.3 Block Diagram
Figure 17-1. ECCHRS Block Diagram
17.4 Product Dependencies
In order to use t his modu le, othe r p arts o f th e syst em must be conf igu red cor re ctly, as de scr ibed
below.
17.4.1 I/O Lines The ECCHRS signals pass through the External Bus Interface module (EBI) where they are
multiplexed.
The programmer must first configure the I/O Controller to assign the EBI pins corresponding to
the Static Memory Controller (SMC) signals to their peripheral function. If I/O lines of the EBI corre-
sponding to SMC signals are not used by the application, the y can be use d for other purposes by
the I/O Controller.
17.4.2 Power Management
If the CPU enters a sleep mode that disables clocks used by the ECCHRS, the ECCHRS will
stop functioni ng and resume operation after the system wakes up from sleep mode.
17.4.3 Clocks The clock for the ECCHRS bus interface (CLK_ECCHRS) is generated by the Power Manager.
This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to
disable the ECCHRS before disabling the clock, to avoid freezing the ECCHRS in an undefined
state.
17.4.4 Interrupts The ECCH RS interrupt request line is connected to the interrupt controller. Using the ECCHRS
interrupt requires the interrupt controller to be programmed first.
Encoder RS4
Polynomial
process
Partial Syndrome Chien Search
Error Evaluator
Ctrl/ECC 1bit Algorithm
HECC User Interface
NAND Flash
SmartMedia
Logic
Static
Memory
Controller
ECC Controller
Peripheral Bus
Rom 1024x10
GF(2 )
10
248
32072H–AVR32–10/2012
AT32UC3A3
17.5 Functional Description
A page in NAND Flash and Smart Media™ memories cont ains an ar ea for m ain data and an addi-
tional area used fo r redunda ncy (ECC). Th e page is organ ized in 8- bit or 16- bit words. The p age
size corresponds to the number of words in the main area plus the number of words in the extra
area used for redundancy.
Over time, some memory locatio ns may fail to program or er ase proper ly. In ord er to ensur e that
data is stored prope rly over the life of the NAND Flash device, NAND Flash provide rs recom-
mend to utilize either one ECC per 256 bytes of data, one ECC per 512 bytes of data, or one
ECC for all of the page. For the next generation of deep micron SLC NAND Flash and with the
new MLC NAND Flash, it is also recommended to ensure at least a four-error ECC per 512
bytes whatever is the page size.
The only configurations required for ECC are the NAND Flash or the SmartMedia™ page size
(528/1056/ 211 2/42 24) a nd th e type o f co rr ecti on want ed ( one ECC- H for all t he pag e, o ne ECC-
H per 256 bytes of data, one ECC-H per 512 bytes of data, or four-error ECC-RS per 512 bytes
of data). The page size is configured by writing in the Page Size field in the Mode Register
(MD.PAGESIZE). Type of correction is configur ed by writing the Type of Correction field in the
Mode Register (MD.TYPECORREC).
The ECC is automatically computed as soon as a read (0x00) or a write (0x80) command to the
NAND Flash or the SmartMedia™ is detected. Read and write access must start at a page
boundary.
The ECC results are a vailable as soon as the counter reaches t he end of the m ain area. The val-
ues in the Parity Registers (PR0 to PR15) for ECC-H and in the Codeword Parity registers
(CWPS00 to CWPS79) for ECC-RS are then valid and locked until a new start condition occurs
(read/write command followed by address cycles).
17.5.1 Write Ac ce ss Once the Flash memory page is writ te n, t he com put ed ECC co des a re availa ble i n PR0 t o PR15
registers for ECC-H and in CWPS00 to CWPS79 registers for ECC-RS. The ECC code values
must be written by the software application in the extra area used for redundancy. The number
of write access in the extra area depends on the value of the MD.TYPECORREC field.
For example, for one ECC per 256 bytes of data for a page of 512 bytes, only the values of PR0
and PR1 must be written by the software app lication in the extra area. For ECC-RS, a NAND
Flash with page of 512 bytes, the software application will have to write the ten registers
CWPS00 to CWPS09 in the extra area, and would have to write 40 registers (CWPS00 to
CWPS39) for a NAND Flash with page of 2048 bytes.
Other registers are meaningless.
17.5.2 Read Access After reading the whole data in the ma in area, the applicat ion must perfor m read accesses t o the
extra area where ECC code has been previously stored. Error detection is automatically per-
formed by th e ECC-H contr oller or the ECC -RS controller. In ECC-RS, writing a one to the Halt
of Computation b it in th e ECC Mod e Re giste r (MD.FREEZE) allows t o stop erro r det ection when
software is jumping to the correct parity area.
249
32072H–AVR32–10/2012
AT32UC3A3
Figure 17-2. FREEZE signal waveform
The application can check the ECC Status Registers (SR1/SR2) for any detected errors. It is up
to the application to correct any detected error for ECC-H. The application can correct any
detected error or let the hardware do the correction by writing a one to the Correction Enable bit
in the MD register (MD.CORRS4) for ECC-RS.
ECC computation can det ect four different circumstances:
• No error: XOR between the ECC computation and the ECC code stored at the end of the
NAND Flash or SmartMedia™ page is equal to z ero. All bits in the SR1 and SR2 registers will
be cleared.
• Recoverable error: Only the Recoverable Error bits in the ECC Status registers
(SR1.RECERRn and/or SR2 .RECERRn) are set. The corrupted word of fset in the re ad page
is defined by the Word Address field (WORDADDR) in the PR0 to PR15 registers. The
corrupted bit position in the concerned word is defined in the Bit Address field (BITADDR) in
the PR0 to PR15 registers.
• ECC error: The ECC Error bits in the ECC Stat us Registers (SR1.ECCERRn /
SR2.ECCERRn) are set. An error ha s been detected in the ECC code stored in the Flash
memory. The position of th e corrupted bit can be found by t he application performing an XOR
between the Parity and the NParity contained in the ECC code stored in the Flash memory.
F or ECC-RS it is the responsibility of the software to determine where the error is located on
ECC code stored in the spare zone flash area and not on user data area.
• Non correctable error: The Multiple Error bits (MULERRn) in the SR1 and SR2 re gisters are
set. Seve ral unrecoverab le errors have been detected in the Flash memory page.
ECC Status Registers, ECC Parity Registers are cleared when a read/write command is
detected or a software reset is performed.
For Single-bit Error Correction and Dou ble-bit Error Detection (SEC-DED) Hsiao code is used.
24-bit ECC is generated in order to perform one bit correction per 256 or 512 bytes for pages of
512/2048/4096 8-bit words. 32-bit ECC is generated in order to perform one bit correction per
512/1024/2048/4096 8- or 16-bit words.They are generated according to the schemes shown in
Figure 17-3 on page 250 and Figure 17-4 on page 251.
FREEZE
Spare Zon e
Nand Flash page 2048B
512B 512B 512B 512B
250
32072H–AVR32–10/2012
AT32UC3A3
Figure 17-3. Parity Generation for 512/1024/2048/4096 8-bit Words
To calculate P8’ to PX’ and P8 to PX, apply t he algorithm that follows.
Page size = 2n
for i =0 to n
begin
for (j = 0 to page_size_byte)
begin
if(j[i] ==1)
P[2i+3]=bit7(+)bit6(+)bit5(+)bit4(+)bit3(+)
bit2(+)bit1(+)bit0(+)P[2i+3]
else
P[2i+3]’=bit7(+)bit6(+)bit5(+)bit4(+)bit3(+)
bit2(+)bit1(+)bit0(+)P[2i+3]'
end
end
P8
P8'
P16
P32
P8
P8'
P16'
P16
P32'
P16'
PX
PX’
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 01st byte
4th byte
3rd byte
2nd byte
(page size-3)th byte
page size th byte
(page size-1)th byte
(page size-2)th byte
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P8
P8'
P8
P8'
P1
P2
P1' P1 P1' P1 P1' P1 P1'
P2' P2 P2'
P4 P4'
Page size = 512
Page size = 1024
Page size = 2048
Page size = 4096
Px = 2048
Px = 4096
Px = 8192
Px = 16384
P1=bit7(+)bit5(+)bit3(+)bit1(+)P1
P2=bit7(+)bit6(+)bit3(+)bit2(+)P2
P4=bit7(+)bit6(+)bit5(+)bit4(+)P4
P1'=bit6(+)bit4(+)bit2(+)bit0(+)P1'
P2'=bit5(+)bit4(+)bit1(+)bit0(+)P2'
P4'=bit7(+)bit6(+)bit5(+)bit4(+)P4'
251
32072H–AVR32–10/2012
AT32UC3A3
Figure 17-4. Parity Generat ion for 512/1024/2048/4096 16-bit Words
To calculate P8’ to PX’ and P8 to PX, apply t he algorithm that follows.
Page size = 2n
for i =0 to n
begin
for (j = 0 to page_size_word)
begin
if(j[i] ==1)
P[2i+3]= bit15(+)bit14(+)bit13(+)bit12(+)
bit11(+)bit10(+)bit9(+)bit8(+)
bit7(+)bit6(+)bit5(+)bit4(+)bit3(+)
bit2(+)bit1(+)bit0(+)P[2n+3]
else
P[2i+3]’=bit15(+)bit14(+)bit13(+)bit12(+)
bit11(+)bit10(+)bit9(+)bit8(+)
bit7(+)bit6(+)bit5(+)bit4(+)bit3(+)
bit2(+)bit1(+)bit0(+)P[2i+3]'
end
end
P8
P8'
P16
P32
P8
P8'
P16'
P16
P32'
P16'
PX
PX’
P8
P8'
P8
P8'
Page size = 512
Page size = 1024
Page size = 2048
Page size = 4096
Px = 2048
Px = 4096
Px = 8192
Px = 16384
P1=bit15(+)bit13(+)bit11(+)bit9(+)bit7(+)bit5(+)bit3(+)bit1(+)P1
P2=bit15(+)bit14(+)bit11(+)bit10(+)bit7(+)bit6(+)bit3(+)bit2(+)P2
P4=bit15(+)bit14(+)bit13(+)bit12(+)bit7(+)bit6(+)bit5(+)bit4(+)P4
P5=bit15(+)bit14(+)bit13(+)bit12(+)bit11(+)bit10(+)bit9(+)bit8(+)P5
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 81st byte
4th byte
3rd byte
2nd byte
(page size-3)th byte
page size th byte
(page size-1)th byte
(page size-2)th byte
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P1
P2
P1' P1 P1' P1 P1' P1 P1'
P2' P2 P2'
P4 P4'
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
P1
P2
P1' P1 P1' P1 P1' P1 P1'
P2' P2 P2'
P4 P4'
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
P5 P5'
252
32072H–AVR32–10/2012
AT32UC3A3
For ECC-RS, in order to perform 4-error correction per 512 bytes of 8-bit words, the cod eword
have to be generated by the RS4 Encoder module and stored into the NAND Flash extra area,
according to the scheme shown in Figure 17 -5 on page 252
Figure 17-5. RS Codeword Generation
In read mode, firstly, the detection for any error is done with the partial syndrome module. It is
the responsibility of the ECC-RS Controller to determine after receiving the old codeword stored
in the extra area if there is any error on data and /or on the old codeword. If all syndromes (Si)
are equal to zero, there is no error, otherwise a polynomial representation is written into
CWPS00 to CWPS79 registers. The Partial Syndrome module performs an algorithm according
to the scheme in Figure 17-6 on page 25 2
Figure 17-6. Partial Syndrome Block Diagram
If the Corr ect ion En a ble b it is set in the ECC M od e Re gis ter ( MD .CO RRS 4) th en t he p oly no mi al
representation of error are sent to the polynomial processor. The aim of this module is to per-
form the polynomial division in order to calculate two polynomials, Omega (Z) and Lambda (Z),
which are necessary for the two following modules (Chien Search and Error Evaluator). In order
to perform additio n, multiplication, and division a Read O nly Memory (ROM) has been ad ded
containing the 1024 elements of the Galois field. Both Chien Search and Error Evaluator work in
parallel. The Error Evaluat or has the responsibility to determin e the Nth error value in the data
and in the old codewo rd according to the scheme in Figure 17-7 on page 253
CW7 CW6 CW5 CW4 CW3 CW2 CW1 CW0
+
+ + + + ++ +
500
α
28
α397
α402
α603
α395
α383
α539
α
Feedback
DataIn
x
DataIn(x)
x
Mult α
RegOct
x
i
S0
S1
S2
S7
253
32072H–AVR32–10/2012
AT32UC3A3
Figure 17-7. Error Evaluator Block Diagram
The Chien Search takes charge o f deter mining if an erro r has occurre d at symb ol N acco rding to
the scheme in Figure 17-8 on page 253
Figure 17-8. Chien Search Block Diagram
ω0ω4
ω1ω5
ω3ω7
+
α-4
α-1 α-3 α-5 α-7
Array - Mult
Rom 1024x10
GF(2 ) inverted
Λodd( α )
-j
10
Err orLoc
Error value
@ position j
ω(α )
-j
λ0
Not
Error Located
counter
Deg r ee of Lambda
Err or locatedFlag error
+
+
+
λ0λ1
λ2λ3
λ8λ7
Λ(α )
-j
α-1
α-2 α-8 α-3 α-7
Λodd(α )
-j
254
32072H–AVR32–10/2012
AT32UC3A3
17.6 User Interface
Note: 1. The reset value is device specific. Please refer to the Module Configuration section at the end of this chapter.
Table 17-1. ECCHRS Register Memory Map
Offset Register Name Access Reset
0x000 Control Register CTRL Write-only 0x00000000
0x004 Mode Register MD Rea d/write 0x00000000
0x008 Status Register 1 SR1 Read-only 0x00000000
0x00C Parity Register 0 PR0 Read-only 0x00000000
0x010 Parity Register 1 PR1 Read-only 0x00000000
0x014 Status Register 2 SR2 Read-only 0x00000000
0x018 Parity Register 2 PR2 Read-only 0x00000000
0x01C Parity Register 3 PR3 Read-only 0x00000000
0x020 Parity Register 4 PR4 Read-only 0x00000000
0x024 Parity Register 5 PR5 Read-only 0x00000000
0x028 Parity Register 6 PR6 Read-only 0x00000000
0x02C Parity Register 7 PR7 Read-only 0x00000000
0x030 Parity Register 8 PR8 Read-only 0x00000000
0x034 Parity Register 9 PR9 Read-only 0x00000000
0x038 Parity Register 10 PR10 Read-only 0x00000000
0x03C P arity Register 11 PR11 Read-only 0x00000000
0x040 Parity Register 12 PR12 Read-only 0x00000000
0x044 Parity Register 13 PR13 Read-only 0x00000000
0x048 Parity Register 14 PR14 Read-only 0x00000000
0x04C P arity Register 15 PR15 Read-only 0x00000000
0x050 - 0x18C Codeword and Syndrome 00 -
Codeword and Syndrome 79 CWPS00 -
CWPS79 Read-only 0x00000000
0x190 - 0x19C MaskData 0 - Mask Data 3 M DATA0 - MDATA3 Read-only 0x00000000
0x1A0 - 0x1AC Address Offset 0 - Address Offset 3 ADOFF0 - ADOFF3 Read-only 0x00000000
0x1B0 Interrupt Enable Register IER Write-only 0x00000000
0x1B4 Interrupt Disable Register IDR Write-only 0x00000000
0x1B8 Interrup t Mask Register MR Read-only 0x00000000
0x1BC Interrupt Status Register ISR Read-only 0x00000000
0x1C0 Interrupt Status Clear Register ISCR Write-only 0x00000000
0x1FC Version Register VERSION Read-only -(1)
255
32072H–AVR32–10/2012
AT32UC3A3
17.6.1 Control Register
Name: CR
Access Type: Write-only
Offset:0x000
Reset Value: 0x00000000
• RST: RESET Parity
Writing a one to this bit will reset the ECC Parity registers.
Writing a zero to this bit has no effect.
This bit alw ays reads as zero.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
-------RST
256
32072H–AVR32–10/2012
AT32UC3A3
17.6.2 Mode Register
Name: MD
Access Type: Read/Write
Offset:0x004
Reset Value: 0x00000000
• CORRS4: Correction Enable
Writing a one to this bit will enable the correction to be done after the P artial Syndrome process and allow interrupt to be sent to
CPU.
Writing a zero to this bit will stop the correction after the Partial Syndrome process.
1: The correction will continue after the Partial Syndrome pro ces s.
0: The correction will stop after the P artial Syndrome process.
• FREEZE: Halt of Computation
Writing a one to this bit will stop the computation.
Writing a zero to this bit will allow the computation as soon as read/write command to th e NAND Flash or the SmartMedia™ is
detected.
1: The computation will stop until a zero is written to th is bit.
0: The computation is allowed.
• TYPECORREC: Type of Correction
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
-----CORRS4-FREEZE
76543210
- TYPECORREC - PAGESIZE
ECC code TYPECORREC Description
ECC-H
0b000 One bit correction per page
0b001 One bit correction per sector of 256 bytes
0b010 One bit correction per sector of 512 bytes
ECC-RS 0b100 Four bits correction per sector of 512 bytes
- Others Reserved
257
32072H–AVR32–10/2012
AT32UC3A3
• PAGESIZE: Page Size
This table defines the page size of the NAND Flash device when using the ECC-H code (TYPECORREC = 0b0xx).
A word has a value of 8 bits or 16 bits, depending on the NAND Flash or SmartMedia™ memory organization.
This table defines the page size of the NAND Flash device when using the ECC-RS code (TYPECORREC = 0b1xx)
i.e.: for NAND Flas h device with p age size of 4096 bytes and 1 28 bytes extra area ECC-RS ca n manage an y sub page of
512 bytes up to 8.
Page Size Description
0 528 words
1 1056 words
2 2112 words
3 4224 words
Others Reserved
Page Size Description Comment
0 528 bytes 1 page of 512 bytes
1 1056 bytes 2 pages of 512 bytes
2 1584 bytes 3 pages of 512 bytes
3 2112 bytes 4 pages of 512 bytes
4 2640 bytes 5 pages of 512 bytes
5 3168 bytes 6 pages of 512 bytes
6 3696 bytes 7 pages of 512 bytes
7 4224 bytes 8 pages of 512 bytes
258
32072H–AVR32–10/2012
AT32UC3A3
17.6.3 Status Register 1
Name: SR1
Access Type: Read-only
Offset:0x008
Reset Value: 0x000000000
MD.TYPECORREC=0b0xx, using ECC-H code
• MULERRn: Multiple Error in the sector number n of 256/512 bytes in the page
1: Multiple errors are detected.
0: No multiple error is detected.
• ECCERRn: ECC Error in the packet number n of 256/512 bytes in the page
1: A single bit error has occurred.
0: No error have be en detected.
31 30 29 28 27 26 25 24
- MULERR7 ECCERR7 RECERR7 - MULERR6 ECCERR6 RECERR6
23 22 21 20 19 18 17 16
- MULERR5 ECCERR5 RECERR5 - MULERR4 ECCERR4 RECERR4
15 14 13 12 11 10 9 8
- MULERR3 ECCERR3 RECERR3 - MULERR2 ECCERR2 RECERR2
76543210
- MULERR1 ECCERR1 RECERR1 - MULERR0 ECCERR0 RECERR0
TYPECORREC Sector Size Comments
0 page size Only MULERR0 is used
1 256 MULERR0 to MULERR7 are used depending on the page size
2 512 MULERR0 to MULERR7 are used depending on the page size
Others Reserved
TYPECORREC Sector Size Comments
0 page size Only ECCERR0 is used
The user should read PR0 and PR1 to know where the error occurs
in the page.
1 256 ECCERR0 to ECCERR7 are used depending on the page size
2 512 ECCERR0 to ECCERR7 are used depending on the page size
Others Reserved
259
32072H–AVR32–10/2012
AT32UC3A3
• RECERRn: Recoverable Error in the pac ket nu mber n of 256/512 Bytes in the page
1: Errors detected. If MULERRn is zero, a single correctab le error was detected. Otherwise multiple uncorrected errors were
detected.
0: No errors have be en detected.
MD.TYPECORREC=0b1xx, using ECC-RS code
• SYNVEC: Syndrome Vector
After reading a page made of n sector of 512 bytes, this field returns which sector contains error detected after the syndrome
analysis.
The SYNVEC[n] bit is set when there is at least one error in the corresponding sector.
The SYNVEC[n] bit is cleared when a read/write command is detected or a software reset is performed.
1: At least one error has occurred in the co rresponding sector.
0: No error has been detected.
TYPECORREC sector siz e Comments
0 page size Only RECERR0 is used
1 256 RECERR0 to RECERR7 are used depending on the page size
2 512 RECERR0 to RECERR7 are used depending on the page size
Others Reserved
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
SYNVEC
Bit Index (n) Sector Boundaries
00-511
1 512-1023
2 1023-1535
3 1536-2047
4 2048-2559
260
32072H–AVR32–10/2012
AT32UC3A3
5 2560-3071
6 3072-3583
7 3584-4095
Bit Index (n) Sector Boundaries
261
32072H–AVR32–10/2012
AT32UC3A3
17.6.4 Parity Register 0
Name: PR0
Access Type: Read-only
Offset:0x00C
Reset Value: 0x00000000
Using ECC-H code, one bit correction per page (MD.TYPECORREC=0b000)
Once the entire main area of a page is written with data, this register content must be stored at any free location of the spare
area.
• WORDADDR: Word Address
During a page read, this field contains the word address (8-bit or 16-bit word, depending on the memory plane organization)
where an error occurred, if a single error was detected. If multiple errors were detected, this field is meaningless.
• BITADDR: Bit Address
During a page read, this field contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple
errors were detected, this field is meaningless.
Using ECC-H code, one bit correction per sector of 256 bytes (MD.TYPECORREC=0b001)
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
WORDADDR[11:4]
76543210
WORDADDR[3:0] BITADDR
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
- NPARITY0[10:4]
15 14 13 12 11 10 9 8
262
32072H–AVR32–10/2012
AT32UC3A3
Once the entire main area of a page is written with data, this register content must be stored at any free location of the spare
area.
• NPARITY0: Parity N
Pari ty calculated by the ECC-H.
• WORDADDR0: Corrupted Word Address in the page between the first byte and the 255th byte
During a page read, this field contains the word address (8-bit word) where an error occurred, if a single error was detected. If
multiple errors were detected, this field is meaningless.
• BITADDR0: Corrupted Bit Address in the page between the first byte and the 255th byte
During a page read, this field contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple
errors were detected, this field is meaningless.
NPARITY0[3:0] 0 WORDADD0[7:5]
76543210
WORDADD0[4:0] BITADDR0
263
32072H–AVR32–10/2012
AT32UC3A3
Using ECC-H code, one bit correction per sector of 512 bytes (MD.TYPECORREC=0b010)
Once the entire main area of a page is written with data, this register content must be stored at any free location of the spare
area.
• NPARITY0: Parity N
Pari ty calculated by the ECC-H.
• WORDADDR0: Corrupted Word Address in the page between the first byte and the 511th byte
During a page read, this field contains the word address (8-bit word) where an error occurred, if a single error was detected. If
multiple errors were detected, this field is meaningless.
• BITADDR0: Corrupted Bit Address in the page between the first byte and the 511th byte
During a page read, this field contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple
errors were detected, this field is meaningless.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
NPARITY0[11:4]
15 14 13 12 11 10 9 8
NPARITY0[3:0] WORDADD0[8:5]
76543210
WORDADD0[4:0] BITADDR0
264
32072H–AVR32–10/2012
AT32UC3A3
17.6.5 Parity Register 1
Name: PR1
Access Type: Read-only
Offset:0x010
Reset Value: 0x00000000
Using ECC-H code, one bit correction per page (MD.TYPECORREC=0b000)
• NPARITY: Parity N
During a write, the field of this register must be written in the extra area used for redundancy (for a 512-byte page size:
address 514-515).
Using ECC-H code, one bit correction per sector of 256 bytes (MD.TYPECORREC=0b001)
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
NPARITY[15:8]
76543210
NPARITY[7:0]
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
- NPARITY1[10:0]
15 14 13 12 11 10 9 8
NPARITY1[3:0] 0 WORDADD1[7:5]
76543210
WORDADD1[4:0] BITADDR1
265
32072H–AVR32–10/2012
AT32UC3A3
Once the entire main area of a page is written with data, this register content must be stored at any free location of the spare
area.
• NPARITY1: Parity N
Parity alculated by the ECC-H.
• WORDADDR1: corrupted Word Address in the page between the 256th and the 511th byte
During a page read, this field contains the word address (8-bit word) where an error occurred, if a single error was detected. If
multiple errors were detected, this field is meaningless.
• BITADDR1: corrupted Bit Address in the page between the 256th and the 511th byte
During a page read, this field contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple
errors were detected, this field is meaningless.
Using ECC-H code, one bit correction per sector of 512 bytes (MD.TYPECORREC=0b010)
Once the entire main area of a page is written with data, this register content must be stored at any free location of the spare
area.
• NPARITY1: Parity N
Pari ty calculated by the ECC-H.
• WORDADDR1: Corrupted Word Address in the page between the 512th and the 10 23th byte
During a page read, this field contains the word address (8-bit word) where an error occurred, if a single error was detected. If
multiple errors were detected, this field is meaningless.
• BITADDR1: Corrupted Bit Address in the page between the 512th and the 1023th byte
During a page read, this field contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple
errors were detected, this field is meaningless.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
NPARITY1[11:4]
15 14 13 12 11 10 9 8
NPARITY1[3:0] WORDADD1[8:5]
76543210
WORDADD1[4:0] BITADDR1
266
32072H–AVR32–10/2012
AT32UC3A3
17.6.6 Status Register 2
Name: SR2
Access Type: Read-only
Offset:0x014
Reset Value: 0x00000000
MD.TYPECORREC=0b0xx, using ECC-H code
• MULERRn: Multiple Error in the sector number n of 256/512 bytes in the page
1: Multiple errors are detected.
0: No multiple error is detected.
• ECCERRn: ECC Error in the packet number n of 256/512 bytes in the page
1: A single bit error has occurred.
0: No error is detected.
31 30 29 28 27 26 25 24
- MULERR15 ECCERR15 RECERR15 - MULERR14 ECCERR14 RECERR14
23 22 21 20 19 18 17 16
- MULERR13 ECCERR13 RECERR13 - MULERR12 ECCERR12 RECERR12
15 14 13 12 11 10 9 8
- MULERR11 ECCERR11 RECERR11 - MULERR10 ECCERR10 RECERR10
76543210
- MULERR9 ECCERR9 RECERR9 - MULERR8 ECCERR8 RECERR8
TYPECORREC Sector Size Comments
0 page size Only MULERR0 is used
1 256 MULERR0 to MULERR7 are used depending on the page size
2 512 MULERR0 to MULERR7 are used depending on the page size
Others Reserved
TYPECORREC sector siz e Comments
0 page size Only ECCERR0 is used
The user should read PR0 and PR1 to know where the error occurs
in the page.
1 256 ECCERR0 to ECCERR7 are used depending on the page size
2 512 ECCERR0 to ECCERR7 are used depending on the page size
Others Reserved
267
32072H–AVR32–10/2012
AT32UC3A3
MD.TYPECORREC=0b1xx, using ECC-RS code
Only one sub page of 512 bytes is corrected at a time. If se v eral sub page are on error then it is necessary to do sev eral time the
correction process.
• MULERR: Multiple error
This bit is set to one when a multiple error have been detected by the ECC-RS.
This bit is cleared when a read/write command is detected or a software reset is performed.
1: Multiple errors detected: more than four errors.Registers for one ECC for a page of 512/1024/2048/4096 bytes
0: No multiple error detected
• RECERR: Number of recoverable errors if MULERR is zero
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
- - - - MULERR RECERR
RECERR Comments
000 no error
001 one single error detected
010 two errors detected
011 three errors detected
100 four errors detected
268
32072H–AVR32–10/2012
AT32UC3A3
17.6.7 Parit y Register 2 - 15
Name: PR2 - PR15
Access Type: Read-only
Offset: 0x018 - 0x04C
Reset Value: 0x00000000
Using ECC-H code, one bit correction per sector of 256 bytes (MD.TYPECORREC=0b001)
Once the entire main area of a page is written with data, this register content must be stored at any free location of the spare
area.
• NPARITYn: Parity N
Pari ty calculated by the ECC-H.
• WORDADDRn: corrupted Word Address in the packet number n of 256 bytes in the page
During a page read, this field contains the word address (8-bit word) where an error occurred, if a single error was detected. If
multiple errors were detected, this field is meaningless.
• BITADDRn: corrupted Bit Address in the packet number n of 256 bytes in the page
During a page read, this field contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple
errors were detected, this field is meaningless.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
- NPARITYn[10:4]
15 14 13 12 11 10 9 8
NPARITYn[3:0] 0 WORDADDn[7:5]
76543210
WORDADDn[4:0] BITADDRn
269
32072H–AVR32–10/2012
AT32UC3A3
Using ECC-H code, one bit correction per sector of 512 bytes (MD.TYPECORREC=0b010)
Once the entire main area of a page is written with data, this register content must be stored to any free location of the spare
area.
Only PR2 to PR7 registers are available in this case.
• NPARITYn: Parity N
Pari ty calculated by the ECC-H.
• WORDADDRn: corrupted Word Address in the packet number n of 512 bytes in the page
During a page read, this field contains the word address (8-bit word) where an error occurred, if a single error was detected. If
multiple errors were detected, this field is meaningless.
• BITADDRn: corrupted Bit Address in the packet number n of 512 bytes in the page
During a page read, this field contains the corrupted bit offset where an error occurred, if a single error was detected. If multiple
errors were detected, this field is meaningless.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
NPARITYn[11:4]
15 14 13 12 11 10 9 8
NPARITYn[3:0] WORDADDn[8:5]
76543210
WORDADDn[4:0] BITADDRn
270
32072H–AVR32–10/2012
AT32UC3A3
17.6.8 Codeword 00 - Codeword79
Name: CWPS00 - CWPS79
Access Type: Read-only
Offset: 0x050 - 0x18C
Reset Value: 0x00000000
Page Write:
• CODEWORD:
Once the 512 bytes of a page is written with data, this register content must be stored to any free location of the spare area.
For a page of 512 bytes the entire redundancy words are made of 8 words of 10 bits. All those redundancies words are
concatenated to a word of 80 bits and then cut to 10 words of 8 bits to facilitate their writing in the extra area.
At the end of a page write, this field contains the redundancy word to be stored to the extra area.
Page Read:
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
CODEWORD
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
PARSYND
271
32072H–AVR32–10/2012
AT32UC3A3
• PARSYND:
At the end of a page read, this field contains the Partial Syndrome S.
PARSYND00-PARSYND09: this conclude all the codew ord and partial syndrome word for the sub page 1
PARSYND10-PARSYND19: this conclude all the codew ord and partial syndrome word for the sub page 2
PARSYND20-PARSYND29: this conclude all the codew ord and partial syndrome word for the sub page 3
PARSYND30-PARSYND39: this conclude all the codew ord and partial syndrome word for the sub page 4
PARSYND40-PARSYND49: this conclude all the codew ord and partial syndrome word for the sub page 5
PARSYND50-PARSYND59: this conclude all the codew ord and partial syndrome word for the sub page 6
PARSYND60-PARSYND69: this conclude all the codew ord and partial syndrome word for the sub page 7
PARSYND70-PARSYND79: this conclude all the codew ord and partial syndrome word for the sub page 8
272
32072H–AVR32–10/2012
AT32UC3A3
17.6.9 Mask Data 0 - Mask Data 3
Name: MDATA0 -MDATA3
Access Type: Read-only
Offset: 0x190 - 0x19C
Reset Value: 0x00000000
• MASKDATA:
At the end of the correction process, this field contains the mask to be XORed with the data read to perf orm the final
correction.This XORed is under the responsibility of the software.
This field is meaningless if MD.CORRS4 is zero.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
- - - - - - MASKDATA[9:8]
76543210
MASKDATA[7:0]
273
32072H–AVR32–10/2012
AT32UC3A3
17.6.10 Address Offset 0 - Address Offset 3
Name: ADOFF0 - ADOFF3
Access Type: Read-only
Offset: 0x1A0 - 0x1AC
Reset Value: 0x00000000
• OFFSET:
At the end of correction process, this field contains the offset address of the data read to be corrected.
This field is meaningless if MD.CORRS4 is zero.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
------ OFFSET[9:8]
76543210
OFFSET[7:0]
274
32072H–AVR32–10/2012
AT32UC3A3
17.6.11 Interrupt Enable Register
Name: IER
Access Type: Write-only
Offset: 0x1B0
Reset Value: 0x00000000
• ENDCOR:
Writing a zero to this bit has no effect.
Writing a one to this bit will set the corresponding bit in IMR.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
-------ENDCOR
275
32072H–AVR32–10/2012
AT32UC3A3
17.6.12 Interrupt Disable Register
Name: IDR
Access Type: Write-only
Offset: 0x1B4
Reset Value: 0x00000000
• ENDCOR:
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the corresponding bit in IMR.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
-------
76543210
-------ENDCOR
276
32072H–AVR32–10/2012
AT32UC3A3
17.6.13 Interrupt Mask Register
Name: IMR
Access Type: Read-only
Offset: 0x1B8
Reset Value: 0x00000000
• ENDCOR:
0: The corresponding interr upt is disabled.
1: The corresponding interrupt is enabled.
This bit is cleared when the corresponding bit in IDR is written to one.
This bit is set when the corresponding bit in IER is wri tten to one.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
-------ENDCOR
277
32072H–AVR32–10/2012
AT32UC3A3
17.6.14 Interrupt Status Register
Name: ISR
Access Type: Read-only
Offset:0x1BC
Reset Value: 0x00000000
• ENDCOR:
This bit is cleared when the corresponding bit in ISCR is written to one.
This bit is set when a correction process has ended.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
-----
15 14 13 12 11 10 9 8
--------
76543210
-------ENDCOR
278
32072H–AVR32–10/2012
AT32UC3A3
17.6.15 Interrupt Status Clear Register
Name: ISCR
Access Type: Write-only
Offset:0x1C0
Reset Value: 0x00000000
• ENDCOR:
Writing a zero to this bit has no effect
Writing a one to this bit will clear the corresponding bit in ISR and the corresponding interrupt reque st.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
-----
15 14 13 12 11 10 9 8
--------
76543210
-------ENDCOR
279
32072H–AVR32–10/2012
AT32UC3A3
17.6.16 Version Register
Name: VERSION
Access Type: Read-only
Offset:0x1FC
Reset Value: 0x00000000
• VARIANT: Variant Number
Reserved. No functionality associated.
• VERSION: Version Number
Version number of the module. No functionality associated.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
----- VARIANT
15 14 13 12 11 10 9 8
- - - - VERSION[11:8]
76543210
VERSION[7:0]
280
32072H–AVR32–10/2012
AT32UC3A3
17.7 Module Configuration
The specific configuration for the ECCHRS instance is listed in the following tables.The module
bus clocks listed here are connected to the system bus clocks according to the table in the
Power Manager section.
Table 17-2. Module clock name
Module name Clock name
ECCHRS CLK_ECCHRS
Table 17-3. Register Reset Values
Register Reset Value
VERSION 0x00000100
281
32072H–AVR32–10/2012
AT32UC3A3
18. Peripheral DMA Controller (PDCA)
Rev: 1.1.0.1
18.1 Features •Multiple channels
•Generates tr ansfers be tween memories and pe r ipherals such as USA RT and SPI
•Two addr ess pointers/counters per ch annel allowing double buffering
•Performance monitors to measure average and maximum transfer latency
18.2 Overview The Peripheral DMA Controlle r (PDCA) transfers data betwee n on-chip peripheral mod ules such
as USART, SPI and memories (those memories may be on- and off-chip memories). Using the
PDCA avoids CPU intervention for data transfers, improving the performance of the microcon-
troller. The PDCA can transfer data from memory to a peripheral or from a peripheral to memory.
The PDCA consists of multiple DMA channels. Each channel has:
• A Peripheral Select Register
• A 32-bit memory pointer
• A 16-bit transfer counter
• A 32-bit memory pointer reload value
• A 16-bit transfer counter reload value
The PDCA communicates with the peripheral modules over a set of handshake interfaces. The
peripheral signals the PDCA when it is ready to receive or transmit data. The PDCA acknowl-
edges the request when the transmission has started.
When a transmit buffer is empty or a receive buffer is full, an optional interrupt request can be
generated.
282
32072H–AVR32–10/2012
AT32UC3A3
18.3 Block Diagram
Figure 18-1. PDCA Block Diagram
18.4 Product Dependencies
In order to use t his modu le, othe r p arts o f th e syst em must be conf igu red cor re ctly, as de scr ibed
below.
18.4.1 Power Management
If the CPU enters a sleep mode that disables the PDCA clocks, the PDCA will stop functioning
and resume operation after the system wakes up from sleep mode.
18.4.2 Clocks The PDCA has two bus clocks connected: On e High Speed Bus clock (CLK_PDCA_HSB) and
one Peripheral Bus clock (CLK_PDCA_PB). These clocks are generated by the Power Man-
ager. Both clocks are enabled at reset, and can be disabled in the Power Manager. It is
recommended to disable the PDCA before disabling the clocks, to avoid freezing the PDCA in
an undefined state.
18.4.3 Interrupts The PDCA interrupt request lines are connected to the interrupt controller. Using the PDCA
interrupts requires the interrupt controller to be programmed first.
HSB to PB
Bridge
Peripheral DMA
Controller
(PDCA)
Peripheral
0
High Speed
Bus Matrix
Handshake Interfaces
Peripheral Bus
IRQ
HSB
HSB
Interrupt
Controller
Peripheral
1
Peripheral
2
Peripheral
(n-1)
...
Memory
HSB
283
32072H–AVR32–10/2012
AT32UC3A3
18.5 Functional Description
18.5.1 Basi c Opera t ion
The PDCA consists of multiple independent PDCA channels, each capable of handling DMA
requests in paralle l. Each PDCA channels contains a set of configuration registers which must
be configured to start a DMA tr ansfer.
In this section the steps necessary to configure one PDCA channel is outlined.
The peripheral to tran sfer data to or from must be configured correctly in the Peripheral Select
Register (PSR). This is performed by writing the Peripheral Identity (PID) value for the corre-
sponding peripheral to the PID field in the PS R register. The PID also encodes the transfer
direction, i.e. memory to peripheral or peripheral to memory. See Section 18.5.5.
The transfer size must be wr itte n to the Tran sfer Size field in t he Mode Regist er (MR.SIZE) . The
size must match the data size produced or consumed by the selected peripheral. See Section
18.5.6.
The memory address to transfer to or from, depending on the PSR, must be written to the Mem-
ory Address Register (MAR). For each transfer the memory address is increased by either a
one, two or four , depending on the size set in MR. See Section 18.5.2.
The number of data items to transfer is written to the TCR register. If the PDCA channel is
enabled, a transfer will start immediately after writing a non-zero value to TCR or the reload ver-
sion of TCR, TCRR. Afte r each transfer the TCR value is decreased by one. Both MAR and TCR
can be read while the PDCA channe l is active to mon itor t he DMA pro gress. Se e Section 18.5.3.
The channel must be enabled for a transfer to start. A channel is enable by writing a one to the
EN bit in the Control Register (CR).
18.5.2 Memor y Pointer
Each channel has a 32-bit Memory Address Register (MAR). This register holds the memory
address for the ne xt transfer to be performed. The register is automatically upda ted after each
transfer. The address will be increased by either one, two or four depending on the size of the
DMA transfer (byt e, halfword or word). The MAR can be r ead at any time during transfer.
18.5.3 Transfer Counter
Each channel has a 16-bit Transfer Counter Register (TCR). This register must be written with
the number of transfers to be performed. The TCR register should contain the number of data
items to be transferred independently of the transfer size. The TCR can be read at any time dur-
ing transfer to see the number of remaining transfers.
18.5.4 Reloa d Regi st ers
Both the MAR and the TCR have a relo ad regist er, r espectively Memo ry Address Relo ad Regis-
ter (MARR) and Transfer Counter Reload Register (TCRR). These registers provide the
possibility for the PDCA to work on tw o memory buffers for each channel. When one buffer has
completed, MAR and TCR will be reloaded with the values in MARR and TCRR. The reload logic
is always enabled and will trigger if the TCR reaches zero while TCRR holds a non-zero value.
After reload, the MARR and TCRR registers are cleared.
If TCR is zero when writing to TCRR, the TCR and MAR are automatically updated with the
value written in TCRR and MARR.
284
32072H–AVR32–10/2012
AT32UC3A3
18.5.5 Peripheral Selection
The Peripheral Select Register (PSR) decides which pe ripheral should be connected to the
PDCA channel. A peripheral is selected by writing the corresponding Peripheral Identity (PID) to
the PID field in the PSR register. Writing the PID will both select the direction of the transfer
(memory to peripheral or peripheral to memory), which handshake interface to use, and the
address of th e periphe ral holding re gister. Refer to the Per ipheral Id entity (PI D) table in the Mod-
ule Configuration section for the peripheral PID values.
18.5.6 Transfer Size The transfer size can be set individually for each channel to be either byte, halfword or word (8-
bit, 16-bit or 32-bit respectively). Transfer size is set by writing the desired value to the Transfer
Size field in the Mode Regi ster (MR.SIZE).
When the PDCA moves data betwee n periphera ls and memory, data is automatic ally sized and
aligned. When memory is accessed, the size specified in MR.SIZE and system alignment is
used. When a peripheral register is accessed the data to be transferred is converted to a word
where bit n in the data corr esponds to bit n in the periphe ral register. If the transfer size is byte or
halfword, bits greater than 8 and16 respectively are set to zero.
Refer to the Module Configu ration section fo r inform ation regar ding what peri pheral regist ers are
used for the different peripherals and then to the peripheral specific chapter for information
about the size option available for the different registers.
18.5.7 Enabling and Disabling
Each DMA channel is enabled by writing a one to the Transfer Enable bit in the Control Register
(CR.TEN) and disabled by writing a one to the Transfer Disable bit (CR.TDIS). The current sta-
tus can be read from the Status Register (SR).
While the PDCA channel is enabled all DMA request will be handled as long the TCR and TCRR
is not zero.
18.5.8 Interrupts Interrupts can be enabled by wr iting a one to the correspond ing bit in th e Interrupt Enable Regis-
ter (IER) and disabled by writing a one to the corresponding bit in the Interrupt Disable Register
(IDR). The Interrupt Mask Register (IMR) can be read to see whether an interrupt is enabled or
not. The current status of an interrupt source can be read through the Interrupt Status Register
(ISR).
The PDCA has three interrupt sources:
• Reload Counter Zero - The TCRR register is zero.
• Transfer Finished - Both the TCR and TCRR registers are z ero.
• Transfer Error - An error has occurre d in accessing memory.
18.5.9 Priority If more than one PDCA channel is requesting transfer at a given tim e, the PDCA channels are
prioritized by their channel number. Channels with lower numbers have priority over channels
with higher numbers, giving channel zero the highest priority.
18.5.10 Error HandlingIf the Memory Address Register (MAR) is set to point to an invalid location in memory, an error
will occur when the PDCA tries to perform a transfer. When an error occurs, the Transfer Error
285
32072H–AVR32–10/2012
AT32UC3A3
bit in the Interrupt Status Register (ISR.TERR) will be set and the DMA channel that caused the
error will be stopped. In order to restart the channel, the user must program the Memory
Address Register to a valid address and then write a one to the Error Clear bit in the Control
Register (CR.ECLR). If the Transfer Error interrupt is enabled, an interrupt request will be gener-
ated when a tra nsfer error occurs.
18.6 Performance Monitors
Up to two performance mon itors allo w the use r to measure the activit y and stall cycles for PDCA
transfers. To monitor a PDCA channel, the correspon ding channel number must be written to
one of the MON0/1CH fiel ds in the Pe rfor ma nce Co ntro l Registe r (PCONTROL) an d a on e must
be written to the corresponding CH0/1EN bit in the same regist er.
Due to performance monitor hardware resource sharing, the two monitor channels should NOT
be programmed to monitor the same PDCA channe l. This may result in UNDEFINED perfor-
mance monitor behavior.
18.6.1 Measuring mechanisms
Three different parameters can be measured by each channel:
• The number of data transfer cycles since last channel reset, both for read and write
• The number of stall cycles since last channel reset, both for read and write
• The maximum latency since last channel reset, both for read and write
These measurements can be extracted by software and used to generate indicators for bus
latency, bus load, and maximum bus latency.
Each of the counters has a fixed width, and may therefore overflow. When an overflow is
encountered in eithe r the Performance Channel Data Read/Wr ite Cycle registers (PRDAT A0/1
and PWDATA0/1) or the Performance Channel Read/Write Stall Cycles registers (PRSTALL0/1
and PWSTALL0/1) of a channel, all registers in the channel are reset. This behavior is altered if
the Channel Overflow Freeze bit is one in the Performance Control register (PCON-
TROL.CH0/1OVF). If this bit is one, the channel registers are frozen when either DATA or
STALL reaches its maximum value. This simplifies one-shot readout of the counter values.
The registers can also be man ually reset by writing a one to th e Channel Re set bit in the PCON-
TROL register (PCONTROL.CH0/1RES). The Performance Channel Read/Write Latency
registers (PRLAT0/1 and PWLAT0/1) are saturating when their maximum count value is
reached. The PRLAT0/1 and PWLAT0/1 registers can only be reset by writing a one to the cor-
responding reset bit in PCONTROL (PCONTROL.CH0 /1RES).
A counter is enable d by writing a one t o the Channe l Enable b it in t he Perfo rmance Cont rol Reg-
ister (PCONTROL.CH0/1EN).
286
32072H–AVR32–10/2012
AT32UC3A3
18.7 User Interface
18.7.1 Memory Map Overview
The channels are mapped as shown in Table 18-1. Each cha nnel has a set of configuration reg-
isters, shown in Table 18-2, where n is the channel number.
18.7.2 Channel Memory Map
Note: 1. The reset values are device specific. Please refer to the Module Configuration section at the
end of this chapter.
Table 18-1. PDCA Register Memory Map
Address Range Contents
0x000 - 0x03F DMA channel 0 configuration registers
0x040 - 0x07F DMA channel 1 configuration registers
... ...
(0x000 - 0x03F)+m*0x040 DMA channel m configuration registers
0x800-0x830 Performance Monitor registers
0x834 Version register
Table 18-2. PDCA Channel Configuration Registers
Offset Register Register Name Access Reset
0x000 + n*0x040 Memory Address Register MAR Read /Write 0x00000000
0x004 + n*0x040 Peripheral Select Register PSR Read/Wr ite - (1)
0x008 + n*0x040 Transfer Counter Register TCR Read/Write 0x00000000
0x00C + n*0x040 Memory Address Reload Register MARR Read/Wr ite 0x00000000
0x010 + n*0x040 Transfer Counter Reload Register TCRR Read/Write 0x00000000
0x014 + n*0x040 Control Register CR Write-only 0x00000000
0x018 + n*0x040 Mode Register MR Read/Write 0x00000000
0x01C + n*0x040 Status Register SR Read-only 0x00000000
0x020 + n*0x040 Interrupt Enable Register IER Write-only 0x00000000
0x024 + n*0x040 Interrupt Disable Register IDR Write-only 0x00000000
0x028 + n*0x040 Interrupt Mask Register IMR Read-only 0x0000000 0
0x02C + n*0x040 Interrupt Status Register ISR Read-only 0x00000000
287
32072H–AVR32–10/2012
AT32UC3A3
18.7.3 Performance Monitor Memory Map
Note: 1. The number of performance monitors is device specific. If the device has only one perfor-
mance monitor, the Channel1 regi sters are not available. Please refer to the Module
Configuration section at the end of this chapter f or the number of performance monitors on this
device.
18.7.4 Version Register Memory Map
Note: 1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter.
Table 18-3. PDCA Performance Monitor Registers(1)
Offset Register Register Name Access Reset
0x800 Performance Control Register PCONTROL Read/Write 0x00000000
0x804 Channel0 Read Data Cycles PRDATA0 Read-only 0x00000000
0x808 Channel0 Read Stall Cycles PRSTALL0 Read-only 0x00000000
0x80C Channel0 Read Max Latency PRLAT0 Read-only 0x00000000
0x810 Channel0 Write Data Cycles PWDATA0 Read-only 0x00000000
0x814 Channel0 Write Stal l Cycles PWSTALL0 Read-only 0x00000000
0x818 Channel0 Write Max Latency PWLAT0 Rea d-only 0x00000000
0x81C Channel1 Read Data Cycles PRDATA1 Read-only 0x00000000
0x820 Channel1 Read Stall Cycles PRSTALL1 Read-only 0x00000000
0x824 Channel1 Read Max Latency PRL AT1 Read-only 0x00000000
0x828 Channel1 Write Data Cycles PWDATA1 Read-only 0x00000000
0x82C Channel1 Write Stall Cycles PWSTALL1 Read-only 0x00000000
0x830 Channel1 Write Max Latency PWLAT1 Rea d-only 0x00000000
Table 18-4. PDCA Version Register Memory Map
Offset Register Register Name Access Reset
0x834 Version Register VERSION Read-only - (1)
288
32072H–AVR32–10/2012
AT32UC3A3
18.7.5 Memo ry Address Regist er
Name: MAR
Access Type: Read/Write
Offset: 0x000 + n*0x040
Reset Value: 0x00000000
• MADDR: Memory Address
Address of memory buffer. MADDR should be programmed to point to the start of the memory buffer when configuring the
PDCA. During transfer, MADDR will point to the ne xt memory location to be read/written.
31 30 29 28 27 26 25 24
MADDR[31:24]
23 22 21 20 19 18 17 16
MADDR[23:16]
15 14 13 12 11 10 9 8
MADDR[15:8]
76543210
MADDR[7:0]
289
32072H–AVR32–10/2012
AT32UC3A3
18.7.6 Peripheral Select Register
Name: PSR
Access Type: Read/Write
Offset: 0x004 + n*0x040
Reset Value: -
• PID: Peripheral Identifier
The P e ripheral Identifier selects which peripheral should be connected to the DMA channel. Writing a PID will select both which
handshake interface to use, the direction of the transfer and also the address of the Receive/Transfer Holding Register for the
peripheral. See the Module Configuration section of PDCA for details. The width of the PID field is device specific and
dependent on the number of peripheral module s in the device.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
PID
290
32072H–AVR32–10/2012
AT32UC3A3
18.7.7 Transfer Counter Register
Name: TCR
Access Type: Read/Write
Offset: 0x008 + n*0x040
Reset Value: 0x00000000
• TCV: Transfer Counter Value
Number of data items to be transferred by the PDCA. TCV must be programmed with the total number of transfers to be made.
During transfer, TCV contains the number of remaining transfers to be done.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
TCV[15:8]
76543210
TCV[7:0]
291
32072H–AVR32–10/2012
AT32UC3A3
18.7.8 Memor y Address Reload Register
Name: MARR
Access Type: Read/Write
Offset: 0x00C + n*0x040
Reset Value: 0x00000000
• MARV: Memory Address Reload Value
Reload Value f or the MAR register. This value will be loaded into MAR when TCR reaches zero if the TCRR register has a non-
zero value.
31 30 29 28 27 26 25 24
MARV[31:24]
23 22 21 20 19 18 17 16
MARV[23:16]
15 14 13 12 11 10 9 8
MARV[15:8]
76543210
MARV[7:0]
292
32072H–AVR32–10/2012
AT32UC3A3
18.7.9 Transfer Counter Reload Register
Name: TCRR
Access Type: Read/Write
Offset: 0x010 + n*0x040
Reset Value: 0x00000000
• TCRV: Transfer Counter Reload Value
Reload value f or the TCR register . When TCR reaches zero , it will be reloaded with TCRV if TCRV has a positive v alue. If TCRV
is zero, no more transfers will be performed for the channel. When TCR is reloaded, the TCRR register is cleared.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
TCRV[15:8]
76543210
TCRV[7:0]
293
32072H–AVR32–10/2012
AT32UC3A3
18.7.10 Control Register
Name: CR
Access Type: Write-only
Offset: 0x014 + n*0x040
Reset Value: 0x00000000
• ECLR: Transfer Error Clear
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the Transf er Error bit in the Status Register (SR.TERR). Clearing the SR.TERR bit will allow the
channel to transmit data. The memory address must first be set to point to a valid location.
• TDIS: Transfer Disable
Writing a zero to this bit has no effect.
Writing a one to this bit will disable transfer for the DMA channel.
• TEN: Transfer Enable
Writing a zero to this bit has no effect.
Writing a one to this bit will enable transfer for the DMA channel.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
-------ECLR
76543210
------TDISTEN
294
32072H–AVR32–10/2012
AT32UC3A3
18.7.11 Mode Register
Name: MR
Access Type: Read/Write
Offset: 0x018 + n*0x040
Reset Value: 0x00000000
• SIZE: Size of Transfer
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
------ SIZE
Table 18-5. Size of Transfer
SIZE Size of Transfer
0 Byte
1 Halfword
2Word
3 Reserved
295
32072H–AVR32–10/2012
AT32UC3A3
18.7.12 Status Register
Name: SR
Access Type: Read-only
Offset: 0x01C + n*0x040
Reset Value: 0x00000000
• TEN: Transfer Enabled
This bit is cleared when the TDIS bit in CR is written to one.
This bit is set when the TEN bit in CR is written to one.
0: Transfer is disabled for the DMA channel.
1: Transfer is enabled for the DMA channel.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
-------TEN
296
32072H–AVR32–10/2012
AT32UC3A3
18.7.13 Interrupt Enable Register
Name: IER
Access Type: Write-only
Offset: 0x020 + n*0x040
Reset Value: 0x00000000
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will set the corresponding bit in IMR.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
- - - - - TERR TRC RCZ
297
32072H–AVR32–10/2012
AT32UC3A3
18.7.14 Interrupt Disable Register
Name: IDR
Access Type: Write-only
Offset: 0x024 + n*0x040
Reset Value: 0x00000000
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will clear the corresponding bit in IMR.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
- - - - - TERR TRC RCZ
298
32072H–AVR32–10/2012
AT32UC3A3
18.7.15 Interrupt Mask Register
Name: IMR
Access Type: Read-only
Offset: 0x028 + n*0x040
Reset Value: 0x00000000
0: The corresponding interr upt is disabled.
1: The corresponding interrupt is enabled.
A bit in this register is cleared when the corresponding bit in IDR is wr itten to one.
A bit in this register is set when the corresponding bit in IER is written to one.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
- - - - - TERR TRC RCZ
299
32072H–AVR32–10/2012
AT32UC3A3
18.7.16 Interrupt Status Register
Name: ISR
Access Type: Read-only
Offset: 0x02C + n*0x040
Reset Value: 0x00000000
• TERR: Transfer Error
This bit is cleared when no transfer errors have occurred since the last write to CR.ECLR.
This bit is set when one or more transfer errors has occurred since reset or the last write to CR.ECLR.
• TRC: Transfer Complete
This bit is cleared when the TCR and/o r the TCRR holds a non-zero value.
This bit is set when both the TCR and the TCRR are zero.
• RCZ: Reload Counter Zero
This bit is cleared when the TCRR holds a non-zero value.
This bit is set when TCRR is zero.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
- - - - - TERR TRC RCZ
300
32072H–AVR32–10/2012
AT32UC3A3
18.7.17 Performance Control Register
Name: PCONTROL
Access Type: Read/Write
Offset: 0x800
Reset Value: 0x00000000
• MON1CH: Perf ormance Monitor Channel 1
• MON0CH: Perf ormance Monitor Channel 0
The PDCA channel number to monitor with counter n
Due to performance monitor hardware resource sharing, the two performance monitor channels should NOT be programmed to
monitor the same PDCA channel. This may result in UNDEFINED monitor behavior.
• CH1RES: Perf ormance Channel 1 Counter Reset
Writing a zero to this bit has no effect.
Writing a one to this bit will reset the counter in the channel specified in MON1CH.
This bit alw ays reads as zero.
• CH0RES: Perf ormance Channel 0 Counter Reset
Writing a zero to this bit has no effect.
Writing a one to this bit will reset the counter in the channel specified in MON0CH.
This bit alw ays reads as zero.
• CH1OF: Channel 1 Overflow Freeze
0: The performance channel registers are reset if D ATA or STALL overflows .
1: All performance channel registers are frozen just before DATA or STALL overflows.
• CH1OF: Channel 0 Overflow Freeze
0: The performance channel registers are reset if D ATA or STALL overflows .
1: All performance channel registers are frozen just before DATA or STALL overflows.
• CH1EN: Performance Channel 1 Enable
0: Performance channe l 1 is disabled.
1: Performance channel 1 is enabled.
• CH0EN: Performance Channel 0 Enable
0: Performance channe l 0 is disabled.
1: Performance channel 0 is enabled.
31 30 29 28 27 26 25 24
-- MON1CH
23 22 21 20 19 18 17 16
-- MON0CH
15 14 13 12 11 10 9 8
------CH1RESCH0RES
76543210
- - CH1OF CH0OF - - CH1EN CH0EN
301
32072H–AVR32–10/2012
AT32UC3A3
18.7.18 Performance Channel 0 Read Data Cycles
Name: PRDATA0
Access Type: Read-only
Offset: 0x804
Reset Value: 0x00000000
• DATA: Data Cycles Counted Since Last Reset
Clock cycles are counted using the CLK_PDCA_HSB clock
31 30 29 28 27 26 25 24
DATA[31:24]
23 22 21 20 19 18 17 16
DATA[23:16]
15 14 13 12 11 10 9 8
DATA[15:8]
76543210
DATA[7:0]
302
32072H–AVR32–10/2012
AT32UC3A3
18.7.19 Performance Channel 0 Read Stall Cycles
Name: PRSTALL0
Access Type: Read-only
Offset: 0x808
Reset Value: 0x00000000
• STALL: Stall Cycles Counted Since Last Reset
Clock cycles are counted using the CLK_PDCA_HSB clock
31 30 29 28 27 26 25 24
STALL[31:24]
23 22 21 20 19 18 17 16
STALL[23:16]
15 14 13 12 11 10 9 8
STALL[15:8]
76543210
STALL[7:0]
303
32072H–AVR32–10/2012
AT32UC3A3
18.7.20 Performance Channel 0 Read Max Latency
Name: PRLAT0
Access Type: Read/Write
Offset: 0x80C
Reset Value: 0x00000000
• LAT : Maxi mum Transfer Initiation Cycles Counted Since Last Reset
Clock cycles are counted using the CLK_PDCA_HSB clock
This counter is saturating. The register is reset only when PCONTROL.CH0RES is written to one.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
LAT[15:8]
76543210
LAT[7:0]
304
32072H–AVR32–10/2012
AT32UC3A3
18.7.21 Performance Channel 0 Write Data Cycles
Name: PWDATA0
Access Type: Read-only
Offset: 0x810
Reset Value: 0x00000000
• DATA: Data Cycles Counted Since Last Reset
Clock cycles are counted using the CLK_PDCA_HSB clock
31 30 29 28 27 26 25 24
DATA[31:24]
23 22 21 20 19 18 17 16
DATA[23:16]
15 14 13 12 11 10 9 8
DATA[15:8]
76543210
DATA[7:0]
305
32072H–AVR32–10/2012
AT32UC3A3
18.7.22 Performance Channel 0 Write Stall Cycles
Name: PWSTALL0
Access Type: Read-only
Offset: 0x814
Reset Value: 0x00000000
• STALL: Stall Cycles Counted Since Last Reset
Clock cycles are counted using the CLK_PDCA_HSB clock
31 30 29 28 27 26 25 24
STALL[31:24]
23 22 21 20 19 18 17 16
STALL[23:16]
15 14 13 12 11 10 9 8
STALL[15:8]
76543210
STALL[7:0]
306
32072H–AVR32–10/2012
AT32UC3A3
18.7.23 Performance Channel 0 Write Max Latency
Name: PWLAT0
Access Type: Read/Write
Offset: 0x818
Reset Value: 0x00000000
• LAT : Maxi mum Transfer Initiation Cycles Counted Since Last Reset
Clock cycles are counted using the CLK_PDCA_HSB clock
This counter is saturating. The register is reset only when PCONTROL.CH0RES is written to one.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
LAT[15:8]
76543210
LAT[7:0]
307
32072H–AVR32–10/2012
AT32UC3A3
18.7.24 Performance Channel 1 Read Data Cycles
Name: PRDATA1
Access Type: Read-only
Offset: 0x81C
Reset Value: 0x00000000
• DATA: Data Cycles Counted Since Last Reset
Clock cycles are counted using the CLK_PDCA_HSB clock
31 30 29 28 27 26 25 24
DATA[31:24]
23 22 21 20 19 18 17 16
DATA[23:16]
15 14 13 12 11 10 9 8
DATA[15:8]
76543210
DATA[7:0]
308
32072H–AVR32–10/2012
AT32UC3A3
18.7.25 Performance Channel 1 Read Stall Cycles
Name: PRSTALL1
Access Type: Read-only
Offset: 0x820
Reset Value: 0x00000000
• STALL: Stall Cycles Counted Since Last Reset
Clock cycles are counted using the CLK_PDCA_HSB clock
31 30 29 28 27 26 25 24
STALL[31:24]
23 22 21 20 19 18 17 16
STALL[23:16]
15 14 13 12 11 10 9 8
STALL[15:8]
76543210
STALL[7:0]
309
32072H–AVR32–10/2012
AT32UC3A3
18.7.26 Performance Channel 1 Read Max Latency
Name: PRLAT1
Access Type: Read/Write
Offset: 0x824
Reset Value: 0x00000000
• LAT : Maxi mum Transfer Initiation Cycles Counted Since Last Reset
Clock cycles are counted using the CLK_PDCA_HSB clock
This counter is saturating. The register is reset only when PCONTROL.CH1RES is written to one.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
LAT[15:8]
76543210
LAT[7:0]
310
32072H–AVR32–10/2012
AT32UC3A3
18.7.27 Performance Channel 1 Write Data Cycles
Name: PWDATA1
Access Type: Read-only
Offset: 0x828
Reset Value: 0x00000000
• DATA: Data Cycles Counted Since Last Reset
Clock cycles are counted using the CLK_PDCA_HSB clock
31 30 29 28 27 26 25 24
DATA[31:24]
23 22 21 20 19 18 17 16
DATA[23:16]
15 14 13 12 11 10 9 8
DATA[15:8]
76543210
DATA[7:0]
311
32072H–AVR32–10/2012
AT32UC3A3
18.7.28 Performance Channel 1 Write Stall Cycles
Name: PWSTALL1
Access Type: Read-only
Offset: 0x82C
Reset Value: 0x00000000
• STALL: Stall Cycles Counted Since Last Reset
Clock cycles are counted using the CLK_PDCA_HSB clock
31 30 29 28 27 26 25 24
STALL[31:24]
23 22 21 20 19 18 17 16
STALL[23:16]
15 14 13 12 11 10 9 8
STALL[15:8]
76543210
STALL[7:0]
312
32072H–AVR32–10/2012
AT32UC3A3
18.7.29 Performance Channel 1 Write Max Latency
Name: PWLAT1
Access Type: Read/Write
Offset: 0x830
Reset Value: 0x00000000
• LAT : Maxi mum Transfer Initiation Cycles Counted Since Last Reset
Clock cycles are counted using the CLK_PDCA_HSB clock
This counter is saturating. The register is reset only when PCONTROL.CH1RES is written to one.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
LAT[15:8]
76543210
LAT[7:0]
313
32072H–AVR32–10/2012
AT32UC3A3
18.7.30 PDCA Version Register
Name: VERSION
Access Type: Read-only
Offset: 0x834
Reset Value: -
• VARIANT: Variant Number
Reserved. No functionality associated.
• VERSION: Version Number
Version number of the module. No functionality associated.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
---- VARIANT
15 14 13 12 11 10 9 8
- - - - VERSION[11:8]
76543210
VERSION[7:0]
314
32072H–AVR32–10/2012
AT32UC3A3
18.8 Module Configuration
The specific configuration for the PDCA instance is listed in the following tables.
18.8.1 DMA Handshake Signals
The table below defines the valid Peripheral Identifiers (PIDs). The direction is specified as
observed from the memory, so RX means transfers from peripheral to memory and TX means
from memory to peripheral.
Table 18-6. PDCA Configuration
Features PDCA
Number of channels 8
Table 18-7. Register Reset Values
Register Reset Value
PSRn n
VERSION 0x00000110
Table 18-8. PDCA Handshake Signals
PID Value Direction Peripheral Instance Peripheral Register
0 RX ADC CDRx
1 RX SSC RHR
2 RX USART0 RHR
3 RX USART1 RHR
4 RX USART2 RHR
5 RX USART3 RHR
6 RX TWIM0 RHR
7 RX TWIM1 RHR
8 RX TWIS0 RHR
9 RX TWIS1 RHR
10 RX SPI0 RDR
11 RX SPI1 RDR
12 TX SSC THR
13 TX USART0 THR
14 TX USART1 THR
15 TX USART2 THR
16 TX USART3 THR
17 TX TWIM0 THR
18 TX TWIM1 THR
19 TX TWIS0 THR
20 TX TWIS1 THR
315
32072H–AVR32–10/2012
AT32UC3A3
21 TX SPI0 TDR
22 TX SPI1 TDR
23 TX ABDAC SDR
Table 18-8. PDCA Handshake Signals
PID Value Direction Peripheral Instance Peripheral Register
316
32072H–AVR32–10/2012
AT32UC3A3
19. DMA Controller (DMACA)
Rev: 2.0.6.6
19.1 Features •2 HSB Master Interfaces
•4 Channels
•Software and Hardware Handshaking Interfaces
– 8 Hardware Handshaking Interfaces
•Memory/N on-Memory Peripherals to Memory/Non-Memory Peripherals Transfer
•Single-block DMA Transfer
•Multi-block DMA Transfer
– Linked Lists
– Auto-Reloading
– Contiguous Bl ocks
•DMA Controller is Always the Flow Controller
•Additional Feat ures
– Scatter and Gather Operations
– Channel Locking
– Bus Locking
– FIFO Mode
– Pseudo Fly-by Operation
19.2 Overview The DMA Controller (DMACA) is an HSB-central DMA controller core that transfers data from a
source peripheral to a destination peripheral over one or more System Bus. One channel is
required for each source/destination pair. In the most basic configuration, the DMACA has one
master inte rface and on e chann el. The ma ste r in terf ace reads t h e d ata f rom a sour ce a nd wr it es
it to a destination. Two System Bus transfers are required for each DMA data transfer. This is
also known as a dual-access transfer.
The DMACA is programmed via the HSB slave interface.
317
32072H–AVR32–10/2012
AT32UC3A3
19.3 Block Diagram
Figure 19-1. DMA Controller (DMAC A) Block Diagram
19.4 Product Dependencies
In order to use t his modu le, othe r p arts o f th e syst em must be conf igu red cor re ctly, as de scr ibed
below.
19.4.1 I/O Lines The pins used for interfacing the compliant external devices may be multip lexed with GPIO lines.
The user must first program the GPIO controller to assign the DMACA pins to their peripheral
functions.
19.4.2 Power Management
To prevent bus errors the DMACA operation must be terminated before entering sleep mode.
19.4.3 Clocks The CLK_DMACA to the DM ACA is generated by the Power Manager (PM). Before u sing the
DMACA, the user must ensure that the DMACA clock is enabled in the power manager.
19.4.4 Interrupts The DMACA interface has an interrupt line connected to the Interrupt Controller. Handling the
DMACA interrupt re quires programming the interrupt controller before conf igu ring th e DM ACA.
19.4.5 Peripherals Both the source peripheral and the destination peripheral must be set up correctly prior to the
DMA transfer.
HSB Slave
I/F
HSB Master
I/F
CFG Interrupt
Generator
FIFO
Channel 0
SRC
FSM
DST
FSM
Channel 1
DMA Controller
irq_dmaHSB Slave
HSB Master
318
32072H–AVR32–10/2012
AT32UC3A3
19.5 Functional Description
19.5.1 Basic Definitions
Source peripheral: Device on a System Bus layer from where the DMACA reads data, which is
then stored in the chan nel FIFO. The source peripheral teams up wit h a destinat ion peripher al to
form a channel.
Destination peripheral: Device t o which th e DMACA writ e s th e stor ed dat a from t he FIFO ( pr e-
viously read from the source peripheral).
Memory: Source or destination that is always “ready” for a DMA transfer and does not require a
handshaking interface to interact with the DMACA. A peripheral should be assigned as memory
only if it does not insert more than 16 wait states. If more than 16 wait states are required, then
the peripheral should use a handshaking interface (the default if the peripheral is not pro-
grammed to be memory) in order to signal when it is ready to accept or supply data.
Channel: Read/write datapath between a source peripheral on one configured System Bus
layer and a destination periph eral on t he same o r differ ent System Bus layer tha t occurs th rough
the channel FIFO. If the source peripheral is not memory, then a source handshaking interface
is assigned to the channel. If the destination peripheral is not memory, then a destination hand-
shaking interface is assigned to t he channel. Sou rce and destination handsh aking interfaces can
be assigned dynamically by programming the channel registers.
Master interfa ce: DMACA is a maste r on the HSB bu s read ing data fr om the source and writ ing
it to the destination ove r the HSB bu s.
Slave interface: The HSB interface over which the DMACA is programmed . The sla ve int er face
in practice could be on the same layer as any of the master interfaces or on a separate layer.
Handshakin g interface: A set of signal registers that conform to a protocol and handshake
between the DMACA and source or destination peripheral to control the transfer of a single or
burst transaction between them. This interface is used to request, acknowledge, and control a
DMACA transaction. A channel can receive a request through one of three types of handshaking
interface: hardware, software, or peripheral interrupt.
Hardware handshaking interface: Uses hardware signals to control the transfer of a single or
burst transaction between the DMACA and the source or destination peripheral.
Software handshaking interface: Uses software registers to control the transfer of a single or
burst transaction between the DMACA and the source or destinatio n peripheral. No special
DMACA handshaking signals are needed on the I/O of the peripheral. This mode is useful for
interfacing an existing peripheral to the DMACA without modifying it.
Peripheral interrupt handshaking interface: A simple use of the hardware handshaking inter-
face. In this mode, the interrupt line from the peripheral is tied to the dma_req input of the
hardware handshaking interface. Other interface signals are ignored.
Flow controller: The device (either the DMACA or source/destination peripheral) that deter-
mines the length of and te rminat es a DMA block tran sfer . If t he length of a b lock is known be fore
enabling the channel, then the DMACA should be programmed as the flow con troller. If the
length of a block is not known prior to enabling the channel, the source or destination peripheral
needs to terminate a block transfer. In this mode, the peripheral is the flow controller.
Flow control mode (CFG x.FCMODE): Special mode that only applies when th e destination
peripheral is the flow controller. It controls the pre-fetching of data from the source peripheral.
319
32072H–AVR32–10/2012
AT32UC3A3
Transfer hierarchy: Figure 19-2 on pag e 319 illustrates the hierarchy between DMACA trans-
fers, block transfers, transactions (single or burst), and System Bus transfers (single or burst) for
non-memory peripherals. Figure 19-3 on page 319 shows the transfer hierarchy for memory.
Figure 19-2. DMACA Transfer Hierarchy for Non-Memory Peripheral
Figure 19-3. DMACA Transfer Hierarchy for Memory
Block: A block of DMACA data. The amount of data (block length) is determined by the flow
controller. For transfers b etween the DMACA and memory, a blo ck is broken directly into a
sequence of System Bus bursts and single transfers. For transfers between the DMACA and a
non-memory pe ripheral, a block is broken into a sequence of DMACA transactions (single an d
bursts). These are in turn broken into a sequence of System Bus transfers.
Transaction: A basic unit of a DMACA transfer as determined by either the hardware or soft-
ware handshaking interface. A transaction is only relevant for transfers between the DMACA
and a source or destination peripheral if the source or destination peripheral is a non-memory
device. Th ere are two types of transactions: single and burst.
DMAC Transfer DMA Transf er
Level
Block Block Block Block Transfer
Level
Burst
Transaction Burst
Transaction Burst
Transaction Single
Transaction DMA Transaction
Level
Burst
Transfer
System Bus Burst
Transfer
System Bus Burst
Transfer
System Bus Single
Transfer
System Bus System Bus
Transfer Level
Single
Transfer
System Bus
DMAC Transfer DMA Transf er
Level
Block Block Block Block Transf er
Level
Burst
Transfer
System Bus Burst
Transfer
System Bus Burst
Transfer
System Bus Single
Transfer
System Bus System Bus
Transfer Level
320
32072H–AVR32–10/2012
AT32UC3A3
–Single transact ion: The length of a single transaction is always 1 and is converted
to a single System Bus transfer.
–Burst transaction: The length of a burst transaction is programmed into the
DMACA. The burst transaction is converted into a sequence of System Bus bursts
and single transfers. DMACA executes each burst transfer by performing
incremental bursts that are no longer than the maximum System Bus burst size set.
The burst transaction length is under program control and normally bears some
relationship to the FIFO sizes in the DMACA and in the source and destination
peripherals.
DMA transfer: Software controls the number of blocks in a DMACA transfer. Once the DMA
transfer has completed, then hardware within the DMACA disables the channel and can gener-
ate an interrupt to signal the completion of the DMA transfer. You can then re-program the
channel for a new DMA transfer.
Single-block DMA transfer: Consists of a single block.
Multi-block DM A transfer: A DMA tran sfer may consist of multiple DMACA blocks. Multi-block
DMA transfers are supported through block chaining (linked list pointers), auto-reloading of
channel registers, and contiguous blocks. The source and destination can independently select
which method to use.
–Linked lists (block chaining) – A linked list pointer (LLP) points to the location in
system memory where the next linked list item (LLI) exists. The LLI is a set of
registers that describe the next block (block descriptor) and an LLP register. The
DMACA fetches the LLI at the beginning of every block when block chaining is
enabled.
–Auto-reloading – The DMACA automatically reloads t he channel registers at the
end of each block to the value when the channel was first enabled.
–Contiguous bl ocks – Where the address betw een succe ssive bloc ks is sele cte d to
be a continuation from the end of the previous block.
Scatter: Relevant to dest in ation t ransfe rs within a blo ck. Th e destina tio n Syst em Bus addr ess is
incremented or decr emented by a programmed amount -the scatter increme nt- when a scatter
boundary is reached. The destination System Bus address is incremented or decremented by
the value stored in the destination scatter increment (DSRx.DSI) field, multiplied by the number
of bytes in a single HSB tra nsfer to the dest ination ( decoded va lue of CTLx.DST _TR_WIDTH) /8.
The number of destination transfers between successive scatter boundaries is programmed into
the Destination Scatter Count (DSC) field of the DSRx register.
Scatter is enabled by writing a ‘1’ to the CTLx.DST_SCATTER_EN bit. The CTLx.DINC field
determines if the address is incremented, decremented or remains fixed when a scatter bound-
ary is reached. If the CTLx.DINC field indicates a fixed-address control throughout a DMA
transfer, then the CTLx.DST_SCATTER_EN bit is ignored, and the scatter feature is automati-
cally disabled.
Gather: Relevant to source transfers within a block. The source System Bus address is incre-
mented or decrem ented by a programmed amo unt when a gather boundary is reach ed. The
number of System Bus transfers between successive gather boundaries is programmed into the
Source Gather Coun t ( SGRx. SGC) fiel d. The source a ddr ess is increment ed o r decr em ented by
the value stored in the source gather increment (SGRx.SGI) field multiplied by the number of
bytes in a single HSB tra nsfer from the source -(decod ed value of CTLx.SRC_TR_W IDTH)/8 -
when a gather boundary is reached.
321
32072H–AVR32–10/2012
AT32UC3A3
Gather is enabled by writing a ‘1’ to the CTLx.SRC_GATHER_EN bit. The CTLx.SINC field
determines if the address is incremented, decremented or remains fixed when a gather bound-
ary is reached. If the CTLx.SINC field indicates a fixed-address control throughout a DMA
transfer, then the CTLx.SRC_GATHER_EN bit is ignored and the gath er featu re is automat ically
disabled.
Note: For multi-bl ock transfers, the counte rs that keep track of the numb er of transfer left to
reach a gather/scatter boundary are re-initialized to the source gather count (SGRx.SGC) and
destination scatter count (DSRx.DSC), respectively, at the start of each block transfer.
Figure 19-4. Destination Scatter Transf er
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
0 x 080
System Memory
A0 + 0x218
A0 + 0x210
A0 + 0x208
A0 + 0x200
A0 + 0x118
A0 + 0x110
A0 + 0x108
A0 + 0x100
Scatter Increment
A0 + 0x018
A0 + 0x010
A0 + 0x008
A0
Scatter Increment
0 x 080
Scatter Boundary A0 + 0x220
Scatter Boundary A0 + 0x120
Scatter Boundary A0 + 0x020
Data Stream
d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11
d11
d8
d7
d4
d3
d0
DSR.DSI * 8 = 0x80 (Scatter Increment in bytes)
CTLx.DST_TR_WIDTH = 3'b011 (64bit/8 = 8 bytes)
DSR.DSI = 16
DSR.DSC = 4
322
32072H–AVR32–10/2012
AT32UC3A3
Figure 19-5. Source Gather Transfer
Channel locking: Software can program a channel to kee p the HSB mast er inter face by locking
the arbitration for the master bus interface for the duration of a DMA transfer, block, or transac-
tion (single or burst).
Bus locking: Software can program a channel to maintain control of the System Bus bus by
asserting hlock for the duration of a DMA transfer, block, or transaction (single or burst). Chan-
nel locking is asserted for the duration of bus locking at a minimum.
FIFO mode: Special mode to improve bandwidth. When enabled, the channel waits until the
FIFO is less than half full to fetch the data from the source peripheral and waits until the FIFO is
greater than or equal to half fu ll to send data to the destinatio n peripher al. Thus, the chan nel can
transfer the data using System Bus bursts, eliminating the need to arbitrate for the HSB master
interface for ea ch single Syste m Bus transfer . When this mode is not enabled, the channel only
waits until the FIFO can transmit/accept a single System Bus transfer before requesting the
master bus interface.
Pseudo fly-by operation: Typically, it takes two System Bus cycles to comple te a tran sfe r, on e
for reading the source and one for writing to the dest ination. However, when th e source and des-
tination peripherals of a DMA transfer are on different System Bus layers, it is possible for the
DMACA to fetch data from the source and store it in the channel FIFO at the same time as the
DMACA extracts data from the channel FIFO and writes it to the destination peripheral. This
activity is known as pseudo fly-by operation. For this to occur, the master interface for both
source and destination layers must win arbitration of their HSB layer. Similarly, the source and
destination peripherals must win ownership of their respective master interface s.
D11
D10
D9
D8
System Memory
A0 + 0x034
A0 + 0x030
A0 + 0x02C
A0 + 0x028
d11
d8
d7
d4
A0 + 0x020
A0 + 0x01C
A0 + 0x018
A0 + 0x014
D7
D6
D5
D4
D3
D2
D1
D0
A0 + 0x00C
A0 + 0x008
A0 + 0x004
A0
d3
d0
Gather Boundary A0 + 0x24
Gather Increment = 4
Data Stream
d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11
Gather Boundary A0 + 0x38
Gather Increment = 4
Gather Boundary A0 + 0x10
Gather Increment = 4
SGR.SGI * 4 = 0x4 (Gather Increment in bytes)
CTLx.SRC_TR_WIDTH = 3'b010 (32bit/8 = 4 bytes)
SGR.SGI = 1
SGR.SGC = 4
323
32072H–AVR32–10/2012
AT32UC3A3
19.6 Arbitration for HSB Master Interface
Each DMACA channel has two request lines that request ownership of a particular master bus
interface: channel source and channel destination request lines.
Source and destination arbitrate separately for the bus. Once a source/destination state
machine gains ownership of the master bus inte rface and the master bus interface has owner-
ship of the HSB bus, then HSB transfers can proceed between the peripheral and the DMACA.
An arbitration scheme decides which o f the request lines (2 * DMAH_NUM_CHANNELS) is
granted the particular master bus interface. Each channel has a programmable priority. A
request for the master bus interface can be made at any time, but is granted only after the cur-
rent HSB transfer (burst or single) has completed. Therefore, if the master interface is
transferring data for a lower priority channel and a higher priority channel requests service, then
the master interface will complete the current burst for the lower priority channel before switch-
ing to transfer data for the higher priority channel.
If only one request line is a ctive at t he highest priori ty level, then t he reque st with the h ighest p ri-
ority wins ownership of the HSB master bus interface; it is not necessary for the priority levels to
be unique.
If more than one request is active at the highest requesting priority, then these competing
requests proceed to a second tier of arb itration:
If equal priority requests occur, then the lower-numbered channel is granted.
In other words, if a peripheral request attached to Channel 7 and a peripheral request attached
to Channel 8 have the same priority, then the peripher al attached to Channel 7 is granted first.
19.7 Memory Peripherals
Figure 19-3 on pag e 319 sh ows the DMA tran sfer hie rarchy of the DMACA for a memory p eriph-
eral. There is no handshaking interface with the DMACA, and therefore the memory peripheral
can never be a flow controller. Once the channel is enabled, the transfer proceeds immediately
without waiting for a transaction request. The alternative to not having a transaction-level hand-
shaking interface is to allow the DMACA to attempt System Bus transfers to the peripheral once
the channel is enabled. If the peripheral slave cannot accept these System Bus transfers, it
inserts wait states onto the bus until it is ready; it is not recommended that m ore than 16 wait
states be inserte d onto the bus. By using the handshaking interface, the peripheral can signal to
the DMACA that it is ready to transmit/receive data, and then the DMACA can access the
peripheral without the peripheral inserting wait states onto the bus.
19.8 Handshaking Interface
Handshaking interfaces are used at the transaction level to control the flow of single or burst
transactions. The operation of the hand shaking interface is different and depends on whether
the peripheral or the DMACA is the flow controller.
The peripheral uses the ha ndshaking inte rface to ind ica te to the DM ACA that it is read y to tr ans-
fer/accept data over the System Bus. A non-memory peripheral can request a DMA transfer
through the DMACA using one of two handshaking interfaces:
• Hardware handshaking
• Software ha nd sh a kin g
324
32072H–AVR32–10/2012
AT32UC3A3
Software selects between the hardwa re or software handshaking interface on a per-chan nel
basis. Software handshaking is accom plished through memory-mapped registers, while hard-
ware handshaking is accomplished using a dedicated handshaking interface.
19.8.1 Software Ha nds h aking
When the slave per ipheral requ ires t he DMAC A to perfor m a DMA tr ansactio n, it c ommu nicate s
this request by sending an interrupt to the CPU or interrupt controller.
The interrupt service rout ine then uses the softwar e registers to initiate and control a DMA trans-
action. These software registers are used to implement the software handshaking interface.
The HS_SEL_SRC/HS_SEL_DST bit in the CFGx channel configuration register must be set to
enable software handshaking.
When the peri pheral is not the flow co ntroller, then the last transaction registers LstSrcReg and
LstDstReg are not used, and the values in these registers are ignored.
19.8.1.1 Burst Transactions
Writing a 1 to the ReqSrcReg[x]/ReqDstReg[x] register is always interpreted as a burst transac-
tion request, where x is the channel number. However, in or der fo r a burst tr ansacti on reque st to
start, softwar e must write a 1 to the SglReqSrc Re g[ x]/SglReqDstReg[x] register.
You can write a 1 to the SglReqSrcReg[x]/SglReqDstReg[x] and ReqSrcReg[x]/ReqDstReg[x]
registers in any order, but both registers must be asserted in order to initia te a burst transaction.
Upon completion of the burst transaction, the hardware clears the SglReqSrcReg[x]/SglReqD-
stReg[x] and ReqSrcReg[x]/ReqDstReg[x] registers.
19.8.1.2 Single Transactions
Writing a 1 to the SglReqSrcReg/SglReqDstReg initiates a single transaction. Upon completion
of the single transaction, both the SglReqSrcReg/SglReqDstReg and ReqSrcReg/ReqDstReg
bits are cleared by hardware. Therefore, writing a 1 to the ReqSrcReg/ReqDstReg is ignored
while a single transactio n has been initiated, and the requested b urst transaction is not serv iced.
Again, writing a 1 to the ReqSrcReg/ReqDstRe g register is always a burst transaction request.
However, in order for a burst transaction request to start, the corresponding channel bit in the
SglReqSrcReg/SglReqDstReg mu st be asserted. Therefore, t o ensure that a bu rst transaction is
serviced, you must write a 1 to the ReqSrcReg/ReqDstReg before writing a 1 to the SglReqSr-
cReg/SglReqDstReg register.
Software can poll the relevant channel bit in the SglReqSrcReg/ SglReqDstReg and ReqSr-
cReg/ReqDstReg registers. When both are 0, then either the requested burst or single
transaction has completed. Alternatively, the IntSrcTran or IntDstTran interrupts can be enabled
and unmasked in order to generate an interrupt when the requested source or destination trans-
action has completed.
Note: The transaction-complete interrupts are triggered when both single and burst transactions are
complete. The same transaction-complete interrupt is used for both single and burst transactions.
19.8.2 Hardware Handshaking
There are 8 ha rdware handshaking interfaces between the DMACA an d peripherals. Refer to
the module configuration chapter for the device-specific mapping of these interfaces.
325
32072H–AVR32–10/2012
AT32UC3A3
19.8.2.1 External DMA Request Definition
When an external slave peripheral requires the DMACA to perform DMA transactions, it commu-
nicates its request by asserting the external nDMAREQx signal. This signal is resynchronized to
ensure a proper functionality (see ”External DMA Request Timing” on page 325).
The external nDMAREQx signal should be asserte d when th e so ur ce th re sh old le ve l is reached.
After resynchronization, the rising edge of dma_req starts the transfer. An external DMAACKx
acknowledge signal is also provided to indicate when the DMA transfer has completed. The
peripheral should de-assert the DMA request signal when DMAACKx is asserted.
The external nDMAREQx signal must be de-asserted after the last transfer and re-asserted
again before a new transaction starts.
For a source FIFO, an active edge should be triggered on nDMAREQx when the source FIFO
exceeds a watermark level. For a destination FIFO, an active edge should be triggered on
nDMAREQx when the destination FIFO drops below the watermark level.
The source transaction length, CTLx.SRC_MSIZE, and destination transaction length,
CTLx.DEST_MSIZE, must be set according to watermark levels on the source/destination
peripherals.
Figure 19-6. External DMA Request Timing
19.9 DMACA Transfer Types
A DMA transfer may consist of single or multi-block transfers. O n successive blocks of a multi-
block transfer, the SARx/DARx register in the DMACA is reprogrammed using either of the fol-
lowing methods:
• Block chaining using linked lists
• Auto-reloading
• Contiguous address between blocks
On successive blocks of a multi-block transfer, the CTLx register in the DMACA is re-pro-
grammed using either of the following methods:
• Block chaining using linked lists
• Auto-reloading
When block chaining, using linked lists is the multi-block method of choice, and on successive
blocks, the LLPx register in the DMACA is re-programmed using the following method:
• Block chaining using linked lists
DMA Transfers DMA Transfers
Hclk
nDMAREQx
dma_req
dma_ack
DMA Transfers
DMA Transaction
326
32072H–AVR32–10/2012
AT32UC3A3
A block descriptor (LLI) consists of following registers, SARx, DARx, LLPx, CTL. These regis-
ters, along with the CFGx register, are used by the DMACA to set up and describe the block
transfer.
19.9.1 Multi-block Transfers
19.9.1.1 Block Chaining Using Linked Lists
In this case, the DMACA re-programs the channel registers prior to the start of each block by
fetching the block descripto r for that block from system memory . This is known as an LLI update.
DMACA block chaining is supported by using a Linked List Pointer register (LLPx) that stores the
address in memory of the next linked list item. Each LLI (block descrip tor) contains the corre-
sponding block descriptor (SARx, DARx, LLPx, CTLx).
To set up block chaining, a sequence of linked lists must be programmed in memo ry.
The SARx, DARx, LLPx and CTLx registers are fetched from system memory on an LLI update.
The updated co ntent s of the CTLx r eg ist er ar e wr itte n b ack to memor y on block comp let ion . Fig-
ure 19-7 on page 326 shows how to use chained linked lists in memory to define multi-block
transfers using block chaining.
The Linked List multi-block transfers is initiated by programming LLPx with LLPx(0) (LLI(0) base
address) and CTLx with CTLx.LLP_S_EN and CTLx.LLP_D_EN.
Figure 19-7. Multi-block Transfer Using Linked Lists
System Memory
SARx
DARx
LLPx(1)
CTLx[31..0]
CTLx[63..32]
SARx
DARx
LLPx(2)
CTLx[31..0]
CTLx[63..32]
LLPx(0) LLPx(2)
LLPx(1)
LLI(0) LLI(1)
327
32072H–AVR32–10/2012
AT32UC3A3
19.9.1.2 Auto-reloading of Channel Registers
During auto-reloading, the channel registers are reloaded with their initial values at the comple-
tion of each block and the new values used for the new block. Depending on the row number in
Table 19-1 on page 327, some or all of the SARx, DARx and CTLx channel registers are
reloaded from their initial value at the start of a block transfer.
19.9.1.3 Contiguous Address Between Blocks
In this case, the address between successive blocks is selected to be a continuation from the
end of the previous block. Enabling the source or destination address to be contiguous between
Table 19-1. Programming of Transfer Types and Channel Register Update Method (DMACA State Machine Table)
Transfer Type LLP.
LOC
= 0
LLP_S_EN
(
CTLx)
RELOAD
_SR
(
CFGx)
LLP_D_EN
(
CTLx)
RELOAD_
DS
(
CFGx)
CTLx,
LLPx
Update
Method
SARx
Update
Method
DARx
Update
Method Write
Back
1) Single Block or
last transfer of
multi-Block Yes 0 0 0 0 None, user
reprograms None (single) None
(single) No
2) Auto Reload
multi-block transfer
with contiguous
SAR
Yes 0 0 0 1 CTLx,LLPx are
reloaded from
initial values. Contiguous Auto-
Reload No
3) Auto Reload
multi-block transfer
with contiguous
DAR
Yes 0 1 0 0 CTLx,LLPx are
reloaded from
initial values. Auto-Reload Con-
tiguous No
4) Auto Reload
multi-block transfer Yes 0 1 0 1 CTLx,LLPx are
reloaded from
initial values. Auto-Reload Auto-
Reload No
5) Single Block or
last transfer of
multi-block No 0 0 0 0 None, user
reprograms None (single) None
(single) Yes
6) Linked List
multi-block transfer
with contiguous
SAR
No 0 0 1 0
CTLx,LLPx
loaded from
next Linked List
item
Contiguous Linked
List Yes
7) Linked List
multi-block transfer
with auto-reload
SAR
No 0 1 1 0
CTLx,LLPx
loaded from
next Linked List
item
Auto-Reload Linked
List Yes
8) Linked List
multi-block transfer
with contiguous
DAR
No 1 0 0 0
CTLx,LLPx
loaded from
next Linked List
item
Linked List Con-
tiguous Yes
9) Linked List
multi-block transfer
with auto-reload
DAR
No 1 0 0 1
CTLx,LLPx
loaded from
next Linked List
item
Linked List Auto-
Reload Yes
10) Linked List
multi-block transfer No 1 0 1 0
CTLx,LLPx
loaded from
next Linked List
item
Linked List Linked
List Yes
328
32072H–AVR32–10/2012
AT32UC3A3
blocks is a function of CTLx.LLP_S_EN, CFGx.RELOAD_SR, CTLx.LLP_D_EN, and
CFGx.RELOAD_DS registers (see Figure 19-1 on page 317).
Note: Both SARx and DARx updates cannot be selected to be contiguous. If this functionality is
required, the size of the Block Transfer (CTLx.BLOCK_TS) must be increased. If this is at the max-
imum value, use Row 10 of Table 19-1 on page 327 and setup the LLI.SARx address of the
block descriptor to be equal to the end SARx address of the previous block. Similarly, setup the
LLI.DARx address of th e block descriptor to be equal to the end DARx address of the previous
block.
19.9.1.4 Suspension of Transfers Between Blocks
At the end of every blo ck tra n sfe r, an en d of block inte rr up t is asse rt ed if:
• interrupts are enabled, CTLx.INT_EN = 1
• the channel block interrupt is unmasked, MaskBlock[n] = 0, where n is the channel number.
Note: The block complete interrupt is generated at the completion of the block transf er to the destination.
For rows 6, 8, and 10 of Table 19-1 on page 327, the DMA transfer does not stall between block
transfers. For example, at the end of bloc k N, the DMACA automati cally proceeds to block N + 1.
For rows 2, 3, 4, 7 , and 9 of T able 19-1 on p age 327 (SARx and/ or DARx auto-reload ed between
block transf ers), the DMA transfer autom atically stalls after th e end of block. Interrup t is asserted
if the end of block interrupt is enabled and unmasked.
The DMACA does not proceed to the next block transfer until a write to the block interrupt clear
register, ClearBlock[n], is performed by software. This clears the channel block complete
interrupt.
For rows 2, 3, 4, 7 , and 9 of T able 19-1 on p age 327 (SARx and/ or DARx auto-reload ed between
block transfers), the DMA transfer does not stall if either:
• interrupts are disabled, CTLx.INT_EN = 0, or
• the channel block interrupt is masked, MaskBlock[n] = 1, where n is the channel number.
Channel suspension between blocks is used to en sure that the end of block ISR (interrupt ser-
vice routine) of the next-to-last block is serviced before the start of the final block commences.
This ensures that the ISR has cleared the CFGx.RELOAD_SR and/or CFGx.RELOAD_DS bits
before completion of the final block. The reload bits CFGx.RELOAD_SR and/or
CFGx.RELOAD_DS should be cleared in the ‘end of block ISR’ for the next-to-last block
transfer.
19.9.2 Ending Multi-block Transfers
All multi-block tr ansfers mu st end as sho wn in either Row 1 or Row 5 of Ta ble 19-1 on page 32 7.
At the end of every block transfer, the DMACA samples t he row number, and if the DMACA is in
Row 1 or Row 5 state, then the previous block transferred was the last block and the DMA trans-
fer is terminated.
Note: Row 1 and Row 5 are used f or single b lock transf ers or terminating multibloc k tr ansfers. Ending in
Row 5 state enables status f e tch f or the last bloc k. Ending in Row 1 state disab les status f etch f o r
the last block.
For rows 2,3 and 4 of Table 19-1 on page 327, (LLPx = 0 and CFGx.RELOAD_SR and/or
CFGx.RELOAD_DS is set), multi-block DMA transfers continue until both the
CFGx.RELOAD_SR and CFGx.RELOAD_DS registers are cleared by software. They should be
329
32072H–AVR32–10/2012
AT32UC3A3
programmed to zero in the end of block interrupt service routine that services the next-to-last
block transfer. This put s the DMACA into Row 1 state.
For rows 6, 8, and 10 (bot h CFGx.RELOAD_SR and CFGx.RELOAD_DS cleared) the user must
setup the last block descriptor in memory such that both LLI.CTLx.LLP_S_EN and
LLI.CTLx.LLP_D_EN are zero. If the LLI.LLPx register of the last block descriptor in memory is
non-zero, then the DMA transfer is terminated in Row 5. If the LLI.LLPx register of the last block
descriptor in memory is zero, then the DMA transfer is terminated in Row 1.
For rows 7 and 9, the end-of-block interrupt service routine that services the next-to-last block
transfer should clear the CFGx.RELOAD_SR and CFGx.RELOAD_DS reloa d bits. The last
block descriptor in memory should be set up so that both the LLI.CTLx.LLP_S_EN and
LLI.CTLx.LLP_D_EN are zero. If the LLI.LLPx register of the last block descriptor in memory is
non-zero, then the DMA transfer is terminated in Row 5. If the LLI.LLPx register of the last block
descriptor in memory is zero, then the DMA transfer is terminated in Row 1.
Note: The only allowed transitions between the rows of Table 19-1 on page 327are from any ro w into
row 1 or row 5. As already stated, a transition into row 1 or row 5 is used to terminate the DMA
transf er. All other transitions between rows are not allowed. Software must ensure that illegal tran-
sitions between rows do not occur between bloc ks of a multi-block transf er . F or example, if b lock N
is in row 10 then the only allowed rows for block N + 1 are rows 10, 5 or 1.
19.10 Programming a Channel
Three register s, the LLPx, th e CTLx and CFGx, need to be program med to set up whe ther single
or multi-block transfers take place, and which type of mu lti-block transfer is used. The different
transfer types are shown in Table 19-1 on page 327.
The “Update Method” column indicates where the values of SARx, DARx, CTLx, and LLPx are
obtained for the next block transfer when multi-block DMACA transfers are enabled.
Note: In Table 19-1 on pag e 327, all other combinations of LLPx.LOC = 0, CTLx.LLP_S_EN,
CFGx.RELOAD_SR, CTLx.LLP_D_EN, and CFGx.RELOAD_DS are illegal, and causes indeter-
minate or erroneous behavior.
19.10.1 Programming Examples
19.10.1.1 Single-block Transfer (Row 1)
Row 5 in Table 19-1 on page 327 is also a single block transfer.
1. Read the Channel Enable register to choose a free (disabled) channel.
2. Clear any pending interrupts on the channel from the previous DMA transfer by writing
to the Interrupt Clear registers: ClearTfr, ClearBlock, ClearSrcTr an, ClearDstTran,
ClearErr. Reading the Inter rupt Raw St atus an d Inte rrupt Statu s register s confirms that
all interrupts have been cleared.
3. Program the following channel registers:
a. Write the starting source address in the SARx register for channel x.
b. Write the starting destination address in the DARx register for channel x.
c. Program CTLx and CFGx accord ing to Row 1 as sho wn in Table 19-1 on page 327.
Program the LLPx register with ‘0’.
d. Write the control information for the DMA transfer in the CTLx register for channel
x. For example, in the register, you can program the following:
– i. Set up the transfer type (memory or non-memory peripheral for source and
destination) and flow contr ol de vice b y progr amming the TT_FC of th e CTLx register.
330
32072H–AVR32–10/2012
AT32UC3A3
– ii. Set up the transfer characteristics, such as:
– Transfer width for th e sou r ce in th e SRC_ TR_W IDTH fie l d.
– Transfer width for the destination in the DST_TR_WIDTH field.
– Source master layer in the SMS fiel d where source resides.
– Desti nation master layer in the DMS field where destination resides.
– Incrementing/decrementing or fixed address for source in SINC field.
– Incrementing/decrementing or fixed address for destination in DINC field.
e. Write the channel configuration information into the CFGx reg ister for channel x.
– i. Designate the handshaking interface type (hardware or software) for the source
and destination peripherals. This is not required for memory. This step requires
programming the HS_SEL_SRC/HS_SEL_DST bits, respe ctively. Writing a ‘0’
activ ates the hardwar e handshaking interf ace to handle source/d estination requests.
Writing a ‘1’ activates the software han dshaking interface to handle
source/destination requests.
– ii. If the hardware handshaking interface is activ ated for the source or destination
peripheral, assign a hand sh aking inte rface to the source and destination pe ripher al.
This requires programming the SRC_ PER and DEST_PER bits, respectively.
4. After the DMACA selected channel has been programmed, enable the channel by writ-
ing a ‘1’ to the Ch EnReg.CH_EN bit . Make sure that bit 0 of t he DmaCfg Reg r egist er is
enabled.
5. Source and destination request single a nd burst DMA transactions to tr ansfer the b lock
of data (assuming non-memory peripherals). The DMACA acknowledges at the com-
pletion of every transaction (burst and single) in the block and carry out the block
transfer.
6. Once the transfer completes, hard w are sets the int errupts and disa bles the channel. At
this time y ou can e ither respon d to the Bloc k Comple te or Transfer Complete interrupts ,
or poll for the Channel Enable (ChEnReg.CH_EN) bit until it is cleared by hardware, to
detect when the transfer is complete.
19.10.1.2 Multi-block Transfer with Linked List for Source and Linked List for Destination (Row 10)
1. Read the Channel Enable register to choose a free (disabled) channel.
2. Set up the chain of Linked L ist Items (otherwise known as b lock descriptors) in memory.
Write the control inf ormation in the LLI.CTLx regist er location of the b loc k de scriptor f or
each LLI in memory (see Figure 19-7 on pa ge 326) for channel x. F or example, in the
register, you can program the following:
a. Set up the transfer type (memory or non-memory peripheral for source and desti-
nation) and flow contro l device by programmin g th e TT _ F C of the CTL x re gist er.
b. Set up the transfer characteristics, such as:
– i. Transfer width for the source in the SRC_ TR_WIDTH field.
– ii. Transfer width for the destination in the DST_TR_WIDTH field.
– iii. Source master layer in the SMS field where source resides.
– iv. Destination master layer in the DMS field where destination resides.
– v. Incrementing/decrementing or fixed address for source in SINC field.
– vi. Incrementing/decrementing or fixed address for destination DINC field.
3. Write the channel configuration information into the CF Gx register for channel x.
331
32072H–AVR32–10/2012
AT32UC3A3
a. Designate the handshaking interface type (hardware or software) for the source
and destination pe ripherals . This is not requir ed f or memory. This step require s pro-
gramming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a ‘0’
activates the hardware handshaking interface to handle source/destination
requests for the specific channel. Writing a ‘1’ activ ates the software handshaking
interface to handle source/destination requests.
b. If the hardware handshaking interface is activated for the source or destination
peripheral, assign the handshaking interface to the source and destina tion periph-
eral. This requires programming the SRC_ PER an d DEST_ PER bit s, respectively.
4. Make sure that the LLI.CTLx register locations of all LLI entries in memory (except the
last) are set as shown in Row 10 of Table 19-1 on page 327. The LLI.CTLx register of
the last Linked List Item must be set as described in Row 1 or Row 5 of Table 19-1 on
page 327. Figure 19-9 on page 333 sho ws a Linked List example with two list items.
5. Make sure that the LLI.LLPx register locations of all LLI entries in memory (except the
last) are non-zero and point to the base address of the next Linked List Item.
6. Make sure that the LLI.SARx/LLI.DARx register locations of all LLI entries in memory
point to the start source/destination block address preceding that LLI fetch.
7. Make sure that the LLI.CTLx.DONE field of the LLI.CTLx register locations of all LLI
entries in memory are cleared.
8. Clear any pending interrupts on the channel from the previous DMA transfer by writing
to the Interrupt Clear registers: ClearTfr, ClearBlock, ClearSrcTr an, ClearDstTran,
ClearErr. Reading the Inter rupt Raw St atus an d Inte rrupt Statu s register s confirms that
all interrupts have been cleared.
9. Program the CTLx, CFGx registers according to Row 10 as shown in Table 19-1 on
page 327.
10. Program the LLPx register with LLPx(0), the pointer to the first Linked List item.
11. Finally, enable the channel by writing a ‘1’ to the ChEnReg.CH_EN bit . The transfer is
performed.
12. The DMACA fetches the first LLI from the location pointed to by LLPx(0).
Note: The LLI.SARx, LLI. DARx, LLI.LLPx and LLI.CTLx registers ar e fetched. The DMACA automati-
cally reprograms the SARx, DARx, LLPx and CTLx channel registers from the LLPx(0).
13. Source and destinat ion r equest singl e and burst DMA tr ansaction s to tr ansfer the blo c k
of data (assuming non-memory peripheral). The DMACA acknowledges at the comple-
tion of every transaction (burst and single) in the block and carry out the block transfer.
Note: Table 19-1 on page 327
14. The DMACA does not wait for the block interrupt to be cleared, but continues fetching
the next LLI from the memory location pointed to by current LLPx register and aut oma t-
ically reprograms the SARx, DARx, LLPx and CTLx channel registers. The DMA
transfer continues until th e DMA CA determines that the CTLx and LLPx registers at the
end of a block transfer match that described in Row 1 or Row 5 of Table 19-1 on page
327. The DMACA then knows that the previous block transferred was the last block in
the DMA transfer. The DMA transfer might look like that shown in Figure 19-8 on page
332.
332
32072H–AVR32–10/2012
AT32UC3A3
Figure 19-8. Multi-Block with Linked List Address for Source and Destin ation
If the user needs to execute a DMA transfer where the source and destination address are con-
tiguous but the amount of data to be transferred is greater than the maximum block size
CTLx.BLOCK_TS, then this can be achieved using the type of multi-block transfer as shown in
Figure 19-9 on page 333.
SAR(2)
SAR(1)
SAR(0)
DAR(2)
DAR(1)
DAR(0)
Block 2
Block 1
Block 0 Block 0
Block 1
Block 2
Address of
Source Layer Address of
Destination Layer
Source Blocks Destination Blocks
333
32072H–AVR32–10/2012
AT32UC3A3
Figure 19-9. Multi-Block with Linked Address for Source and Destination Blocks are
Contiguous
The DMA transfer flow is shown in Figure 19-11 on page 336 .
SAR(2)
SAR(1)
SAR(0)
DAR(2)
DAR(1)
DAR(0)
Block 2
Block 1
Block 0
Block 0
Block 1
Block 2
Address of
Source Layer Address of
Destination Layer
Source Blocks Destination Blocks
SAR(3)
Block 2
DAR(3)
Block 2
334
32072H–AVR32–10/2012
AT32UC3A3
Figure 19-10. DMA Transfer Flow for Source and Destination Linked List Address
19.10.1.3 Multi-block Transfer with Source Address Auto-reloaded and Destination Address Auto-reloaded (Row 4)
1. Read the Channel Enable register to choose an available (disabled) channel.
2. Clear any pending interrupts on the channel from the previous DMA transfer by writing
to the Interrupt Clear registers: ClearTfr, ClearBlock, ClearSrcTr an, ClearDstTran,
ClearErr. Reading the Inter rupt Raw St atus an d Inte rrupt Statu s register s confirms that
all interrupts have been cleared.
3. Program the following channel registers:
Channel enabled by
software
LLI Fetch
Hardware reprograms
SARx, DARx, CTLx, LLPx
DMAC block transfer
Source/destination
status fetch
Is DMAC in
Row1 of
DMAC State Machine Table?
Channel Disabled by
hardware
Block Complete interrupt
generated here
DMAC transfer Complete
interrupt generated here yes
no
335
32072H–AVR32–10/2012
AT32UC3A3
a. Write the starting source address in the SARx register for channel x.
b. Write the starting destination address in the DARx register for channel x.
c. Program CTLx and CFGx accord ing to Row 4 as sho wn in Table 19-1 on page 327.
Program the LLPx register with ‘0’.
d. Write the control information for the DMA transfer in the CTLx register for channel
x. For example, in the register, you can program the following:
– i. Set up the transfer type (memory or non-memory peripheral for source and
destination) and flow contr ol de vice b y progr amming the TT_FC of th e CTLx register.
– ii. Set up the transfer characteristics, such as:
– Transfer width for th e sou r ce in th e SRC_ TR_W IDTH fie l d.
– Transfer width for the destination in the DST_TR_WIDTH field.
– Source master layer in the SMS fiel d where source resides.
– Desti nation master layer in the DMS field where destination resides.
– Incrementing/decrementing or fixed address for source in SINC field.
– Incrementing/decrementing or fixed address for destination in DINC field.
e. Write the channel configuration information into the CFGx reg ister for channel x.
Ensure that the reload bits, CFGx. RELOAD_SR and CFGx.RELOAD_DS are
enabled.
– i. Designate the handshaking interface type (hardware or software) for the source
and destination peripherals. This is not required for memory. This step requires
programming the HS_SEL_SRC/HS_SEL_DST bits, respe ctively. Writing a ‘0’
activ ates t he hardw a re han dshaking int erface to handle source/destination requests
f or t he specific cha nnel. Writing a ‘1’ activates the softwar e handshaking i nterface to
handle source/destination requests.
– ii. If the hardware handshaking interface is activ ated for the source or destination
peripheral, assign handshaking interface to the source and destination peripheral.
This requires programming the SRC_ PER and DEST_PER bits, respectively.
4. After the DMACA selected channel has been programmed, enable the channel by writ-
ing a ‘1’ to the Ch EnReg.CH_EN bit . Make sure that bit 0 of t he DmaCfg Reg r egist er is
enabled.
5. Source and destination request single and burst DMACA transactions to transfer the
bl ock of data (assuming non-memo ry peripherals). The DMACA ackno wledges on com-
pletion of each burst/single transaction and carry out the block transfer.
6. When the block transfer has completed, the DMACA reloads the SARx, DARx and
CTLx registers. Hardware sets the Block Complete interrupt. The DMACA then sam-
ples the row number as shown in Table 19-1 on page 327. If the DMACA is in Row 1,
then the DMA transfer has completed. Hardware sets the transfer complete interrupt
and disab l es th e channe l. So y ou can eith er re spon d to the Block Complete or Transfer
Complete interrupts , or poll for the Channel Enab le (ChEnReg .CH_EN) bit un ti l it is dis-
abled, to detect when the transfer is complete. If the DMACA is not in Row 1, the next
step is performed.
7. The DMA transf er proceeds as follows:
a. If interrupts are enabled (CTLx.INT_EN = 1) and the block complete interrupt is un-
masked (MaskBlock[x] = 1’b1, where x is the channel number) hardware sets the
bl ock complete interrupt when the block transfer has completed. It then stalls until
the bloc k complete interrupt is cleared by software. If the ne xt bloc k is to be the last
block in the DMA transfer, then the block complete ISR (interrupt service routine)
336
32072H–AVR32–10/2012
AT32UC3A3
should clear the reload bits in the CFGx.RELOAD_SR and CFGx.RELOAD_DS
registers. This put the DMACA into Row 1 as shown in Table 19-1 on page 327. If
the next block is not the last block in the DMA transfer, then the reload bits should
remain enabled to keep the DMACA in Row 4.
b. If interrupts are disabled (CTLx.INT_EN = 0) or the block complete interrupt is
mask ed (MaskBlock[x] = 1’b 0, where x is the channel n umber), then hardw are does
not stall until it detects a write to the block complet e interrupt clear register but
starts the next block transfer immediately. In this case software must clear the
reload bits in the CFGx.RELOAD_SR and CFGx.RELOAD_DS registers to put the
DMACA into ROW 1 of Table 19-1 on page 327 before the last block of the DMA
transfer has completed. The transfer is similar to that shown in Figure 19-11 on
page 336. The DMA transfer flow is shown in Figure 19-12 on page 337.
Figure 19-11. Multi-Block DMA Transfer with Source and Destination Address Auto-reloaded
Address of
Source Layer
Address of
Destination Layer
Source Blocks Destination Blocks
BlockN
Block2
Block1
Block0
SAR DAR
337
32072H–AVR32–10/2012
AT32UC3A3
Figure 19-12. DMA Transfer Flow for Source and Destination Address Auto-reloaded
19.10.1.4 Multi-block Transfer with Source Address Auto-reloaded and Linked List Destination Address (Row7)
1. Read the Channel Enable register to choose a free (disabled) channel.
2. Set up the chain of linked list items (otherwise known as block descriptors) in memory.
Write the control inf ormation in the LLI.CTLx regist er location of the b loc k de scriptor f or
each LLI in memory for channel x. For example, in the regist er you can program the
following:
a. Set up the transfer type (memory or non-memory peripheral for source and desti-
nation) and flo w contro l peripheral b y prog ramming t he TT_FC of the CTL x register.
b. Set up the transfer characteristics, such as:
– i. Transfer width for the source in the SRC_ TR_WIDTH field.
– ii. Transfer width for the destination in the DST_TR_WIDTH field.
– iii. Source master layer in the SMS field where source resides.
– iv. Destination master layer in the DMS field where destination resides.
– v. Incrementing/decrementing or fixed address for source in SINC field.
– vi. Incrementing/decrementing or fixed address for destination DINC field.
Channel Enabled by
software
Block Transfer
Reload SARx, DARx, CTLx
Channel Disabled by
hardware
Block Complete interrupt
generated here
DMAC transfer Complete
interrupt generated here yes
no
yes
Stall until block complete
interrupt cleared by software
CTLx.INT_EN=1
&&
MASKBLOCK[x]=1?
no
Is DMAC in Row1 of
DMAC State Machine Table?
338
32072H–AVR32–10/2012
AT32UC3A3
3. Write the starting source address in the SARx register for channel x.
Note: The values in the LLI.SARx register locations of each of the Linked List Items (LLIs) setup up in
memory, although fetched during a LLI fetch, are not used .
4. Write the channel configuration information into the CF Gx register for channel x.
a. Designate the handshaking interface type (hardware or software) for the source
and destination pe ripherals . This is not requir ed f or memory. This step require s pro-
gramming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a ‘0’
activates the hardware handshaking interface to handle source/destination
requests for the specific channel. Writing a ‘1’ activ ates the software handshaking
interface source/destination requests.
b. If the hardware handshaking interface is activated for the source or destination
peripheral, assign handshaking interface to the source and destination peripheral.
This requires programming the SRC_ PER and DEST_PER bits, respectively.
5. Make sure that the LLI.CTLx register locations of all LLIs in memory (except the last)
are set as sho wn in Row 7 o f Table 19-1 on pa ge 327 while the LLI.CTLx register of the
last Link ed List item m ust be set as described in Ro w 1 or Row 5 of Table 19-1 on page
327. Figure 19-7 on page 326 shows a Linked List example wit h two list items.
6. Make sure that the LLI.LLPx register locations of all LLIs in memory (except the last)
are non-zero and point to the next Linked List Item.
7. Make sure that the LLI.DARx register location of all LLIs in memory point to the start
destination block address proceeding that LLI f etch.
8. Make sure that the LLI .CTLx.DONE field of the LLI .CTLx registe r locations of all LLIs in
memory is cleared.
9. Clear any pending interrupts on the channel from the previous DMA transfer by writing
to the Interrupt Clear registers: ClearTfr, ClearBlock, ClearSrcTr an, ClearDstTran,
ClearErr. Reading the Inter rupt Raw St atus an d Inte rrupt Statu s register s confirms that
all interrupts have been cleared.
10. Program the CTLx, CFGx regist ers according to Ro w 7 as sho wn in Table 19 -1 on page
327.
11. Program the LLPx register with LLPx(0), the pointer to the first Linked List item.
12. Finally, enable the channel by writing a ‘1’ to the ChEnReg.CH_EN bit . The transfer is
performed. Make sure that bit 0 of the DmaCfgReg register is enabled.
13. The DMACA fetches the first LLI from the location pointed to by LLPx(0).
Note: The LLI.SARx, LLI.DARx, LLI. LLPx and LLI.CTLx registers are fetched. The LLI.SARx register
although fetched is not used.
14. Source and destination request single and burst DMACA transactions to transfer the
block of data (assuming non-memory peripherals). DMACA acknowledges at the com-
pletion of every transaction (burst and single) in the block and carry out the block
transfer.
15. Table 19-1 on page 327The DMACA reloads the SARx register from the initial value.
Hardware sets the block complete interrupt. The DMACA samples the row number as
shown in Table 19-1 on page 327. If the DMACA is in Row 1 or 5, then the DMA trans-
fer has completed. Hardware sets the transfer complete interrupt and disables the
channel. You can either respond to the Bloc k Complete or Transf er Complete interrupts ,
or poll for the Channel Enable (ChEnReg.CH_EN) bit until it is cleared by hardware, to
detect when the transfer is complete. If the DMAC A is not in Row 1 or 5 as shown in
Table 19-1 on page 327 the following steps are performed.
16. The DMA transfer proceeds as follows:
a. If interrupts are enabled (CTLx.INT_EN = 1) and the block complete interrupt is un-
masked (MaskBlock[x] = 1’b1, where x is the channel number) hardware sets the
339
32072H–AVR32–10/2012
AT32UC3A3
bl ock complete interrupt when the block transfer has completed. It then stalls until
the bloc k complete interrupt is cleared by software. If the ne xt bloc k is to be the last
block in the DMA transfer, then the block complete ISR (interrupt service routine)
should clear the CFGx.RELOAD_SR source reload bit. This puts the DMACA into
Row1 as shown in Table 19-1 on page 327. If the next block is not the last block in
the DMA transfer, then the source reload bit should remain enabled to keep the
DMACA in Row 7 as shown in Table 19-1 on page 327.
b. If interrupts are disabled (CTLx.INT_EN = 0) or the block complete interrupt is
mask ed (MaskBloc k[x] = 1’b0 , where x is the channel n umber) then har dware does
not stall until it detects a write to the block complet e interrupt clear register but
starts the next block transfer immediately. In this case, software must clear the
source reload bit, CFGx.RELOAD_SR, to put the device into Row 1 of Table 19-1
on page 327 befor e the last block of the DMA transfer has completed.
17. The DMACA fetches the next LLI from memory location pointed to by the current LLPx
register, and automatically reprograms the DARx, CTLx and LLPx channel registers.
Note that the SARx is not re-programmed as the reloaded value is used for the next
DMA blo c k tr ansfer . If th e next bloc k is the last b l oc k of the DMA tr ansfer then the CTLx
and LLPx registers just fetched from the LLI should matc h Row 1 or Row 5 of Table 19-
1 on page 327. The DMA transfer might look like that shown in Figure 19-13 on page
339.
Figure 19-13. Multi-Block DMA Transfer with Source Address Auto-reloaded an d Linked List
Destination Address
The DMA Transfer flow is shown in Figure 19-14 on page 340.
Address of
Source Layer
Address of
Destination Layer
Source Blocks Destination Blocks
SAR
Block0
Block1
Block2
BlockN
DAR(N)
DAR(1)
DAR(0)
DAR(2)
340
32072H–AVR32–10/2012
AT32UC3A3
Figure 19-14. DMA Transfer Flow for Source Address Auto-reloaded and Linked List Destina-
tion Address
Channel Enabled by
software
LLI Fetch
yes
no
no
yes
Hardware reprograms
DARx, CTLx, LLPx
DMAC block transfer
Source/destination status fetch
Reload SARx
Block Complete interrupt
generated here
DMAC Transfer Complete
interrupt generated here
Channel Disabled by
hardware
CTLx.INT_EN=1
&&
MASKBLOCK[X]=1 ?
Stall until block interrupt
Cleared by hardware
Is DMAC in
Row1 or Row5 of
DMAC State Machine Table?
341
32072H–AVR32–10/2012
AT32UC3A3
19.10.1.5 Multi-block Transfer with Source Address Auto-reloaded and Contiguous Destination Address (Row 3)
1. Read the Channel Enable register to choose a free (disabled) channel.
2. Clear any pending interrupts on the channel from the previous DMA transfer by writing
a ‘1’ to the Interrupt Clear registers: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran,
ClearErr. Reading the Inter rupt Raw St atus an d Inte rrupt Statu s register s confirms that
all interrupts have been cleared.
3. Program the following channel registers:
a. Write the starting source address in the SARx register for channel x.
b. Write the starting destination address in the DARx register for channel x.
c. Program CTLx and CFGx accord ing to Row 3 as sho wn in Table 19-1 on page 327.
Program the LLPx register with ‘0’.
d. Write the control information for the DMA transfer in the CTLx register for channel
x. For example, in this register, you can program the following:
– i. Set up the transfer type (memory or non-memory peripheral for source and
destination) and flow contr ol de vice b y progr amming the TT_FC of th e CTLx register.
– ii. Set up the transfer characteristics, such as:
– Transfer width for th e sou r ce in th e SRC_ TR_W IDTH fie l d.
– Transfer width for the destination in the DST_TR_WIDTH field.
– Source master layer in the SMS fiel d where source resides.
– Desti nation master layer in the DMS field where destination resides.
– Incrementing/decrementing or fixed address for source in SINC field.
– Incrementing/decrementing or fixed address for destination in DINC field.
e. Write the channel configuration information into the CFGx reg ister for channel x.
– i. Designate the handshaking interface type (hardware or software) for the source
and destination peripherals. This is not required for memory. This step requires
programming the HS_SEL_SRC/HS_SEL_DST bits, respe ctively. Writing a ‘0’
activ ates t he hardw a re han dshaking int erface to handle source/destination requests
f or t he specific cha nnel. Writing a ‘1’ activates the softwar e handshaking i nterface to
handle source/destination requests.
– ii. If the hardware handshaking interface is activ ated for the source or destination
peripheral, assign handshaking interface to the source and destination peripheral.
This requires programming the SRC_ PER and DEST_PER bits, respectively.
4. After the DMACA cha nnel has been prog rammed, enable the channel by writing a ‘1’ to
the ChEnReg.CH_EN bit. Make sure that bit 0 of the DmaCfgRe g register is enabled.
5. Source and destination request single and burst DMACA transactions to transfer the
bl ock of data (assuming non-memory peripherals). The DMACA acknowledges at the
completion of every transaction (burst and single) in th e block and carries out the bloc k
transfer.
6. When the block transfer has completed, the DMACA reloads the SARx register. The
DARx register remain s unchanged. Hardware sets the block complete interrupt. The
DMACA then samples the row number as shown in Table 19-1 on page 327. If the
DMACA is in Row 1, then the DMA transfer has completed. Hardware sets the transfer
complete interrupt and disables the channel. So you can either respond to the Block
Complete or Transfer Complete interrupts, or poll for the Channel Enable (ChEn-
342
32072H–AVR32–10/2012
AT32UC3A3
Reg.CH_EN) bit until it is cle ared by hardwar e , to detect when the tr ansfer is complete.
If the DMACA is not in Row 1, the next step is performed.
7. The DMA transf er proceeds as follows:
a. If interrupts are enabled (CTLx.INT_EN = 1) and the block complete interrupt is un-
masked (MaskBlock[x] = 1’b1, where x is the channel number) hardware sets the
bl ock complete interrupt when the block transfer has completed. It then stalls until
the bloc k complete interrupt is cleared by software. If the ne xt bloc k is to be the last
block in the DMA transfer, then the block complete ISR (interrupt service routine)
should clear the source reload bit, CFGx.RELOAD_SR. This puts the DMACA into
Row1 as shown in Table 19-1 on page 327. If the next block is not the last block in
the DMA transfer then the source reload bit should remain enabled to keep the
DMACA in Row3 as shown in Table 19-1 on page 327.
b. If interrupts are disabled (CTLx.INT_EN = 0) or the block complete interrupt is
mask ed (MaskBloc k[x] = 1’b0 , where x is the channel n umber) then har dware does
not stall until it detects a write to the block complet e interrupt clear register but
starts the next block transfer immediately. In this case software must clear the
source reload bit, CFGx.RELOAD_SR, to put the device into ROW 1 of Table 19-1
on page 327 befor e the last block of the DMA transfer has completed.
The transfer is similar to that shown in Figure 19-15 on page 342.
The DMA Transfer flow is shown in Figure 19-16 on page 343.
Figure 19-15. Multi-block Transfer with Source Address Auto-reloaded and Contiguous Desti-
nation Address
Address of
Source Layer
Address of
Destination Layer
Source Blocks Destination Blocks
SAR
Block0
Block1
Block2
DAR(1)
DAR(0)
DAR(2)
343
32072H–AVR32–10/2012
AT32UC3A3
Figure 19-16. DMA Transfer for Source Address Auto-reloaded and Contiguous Destination
Address
19.10.1.6 Multi-block DMA Transfer with Linked List for Source and Contiguous Destination Address (Row 8)
1. Read the Channel Enable register to choose a free (disabled) channel.
2. Set up the linked list in memory. Write the control information in the LLI. CTLx register
location of the block descriptor f or each LLI in memory for channel x. For example, in
the register, you can program the following:
a. Set up the transfer type (memory or non-memory peripheral for source and desti-
nation) and flow contro l device by programmin g th e TT _ F C of the CTL x re gist er.
b. Set up the transfer characteristics, such as:
– i. Transfer width for the source in the SRC_ TR_WIDTH field.
– ii. Transfer width for the destination in the DST_TR_WIDTH field.
– iii. Source master layer in the SMS field where source resides.
– iv. Destination master layer in the DMS field where destination resides.
Channel Enabled by
software
Block Transfer
Reload SARx, CTLx
Channel Disabled by
hardware
Block Complete interrupt
generated here
DMAC Transfer Complete
interrupt generated here yes
no
no
yes
Stall until Block Complete
interrupt cleared by software
CTLx.INT_EN=1
&&
MASKBLOCK[x]=1?
Is DMAC in Row1 of
DMAC State Machine Table?
344
32072H–AVR32–10/2012
AT32UC3A3
– v. Incrementing/decrementing or fixed address for source in SINC field.
– vi. Incrementing/decrementing or fixed address for destination DINC field.
3. Write the starting destination address in the DARx register for channel x.
Note: The values in the LLI.DARx register location of each Linked List Item (LLI) in memory, although
fetched during an LLI fetch, are not used.
4. Write the channel configuration information into the CF Gx register for channel x.
a. Designate the handshaking interface type (hardware or software) for the source
and destination pe ripherals . This is not requir ed f or memory. This step require s pro-
gramming the HS_SEL_SRC/HS_SEL_DST bits, respectively. Writing a ‘0’
activates the hardware handshaking interface to handle source/destination
requests for the specific channel. Writing a ‘1’ activ ates the software handshaking
interface to handle source/destination requests.
b. If the hardware handshaking interface is activated for the source or destination
peripheral, a ssign handshaking in terf ace to t he source and destinat ion peripherals .
This requires programming the SRC_ PER and DEST_PER bits, respectively.
5. Make sure that all LLI.CTLx register locations of the LLI (except the last) are set as
shown in Row 8 of Table 19-1 on page 327, while the LLI.CTLx register of the last
Linked List item must be set as described in Row 1 or Row 5 of Table 19-1 on pag e
327. Figure 19-7 on page 326 shows a Linked List example wit h two list items.
6. Make sure that the LLI.LLPx register locations of all LLIs in memory (except the last)
are non-zero and point to the next Linked List Item.
7. Make sure that the LLI.S ARx re gis ter loca tio n of all LLIs in mem o ry po int to the start
source block address proceeding that LLI fetch.
8. Make sure that the LLI .CTLx.DONE field of the LLI .CTLx registe r locations of all LLIs in
memory is cleared.
9. Clear any pending interrupts on the channel from the previous DMA transfer by writing
a ‘1’ to the Interrupt Clear registers: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran,
ClearErr. Reading the Inter rupt Raw St atus an d Inte rrupt Statu s register s confirms that
all interrupts have been cleared.
10. Program the CTLx, CFGx regist ers according to Ro w 8 as sho wn in Table 19 -1 on page
327
11. Program the LLPx register with LLPx(0), the pointer to the first Linked List item.
12. Finally, enable the channel by writing a ‘1’ to the ChEnReg.CH_EN bit . The transfer is
performed. Make sure that bit 0 of the DmaCfgReg register is enabled.
13. The DMACA fetches the first LLI from the location pointed to by LLPx(0).
Note: The LLI.SARx, LLI.DARx, LLI.LLPx and LLI.CTLx registers are fetched. Th e LLI.DARx register
location of the LLI although fetched is not used. The DARx register in the DMACA remains
unchanged.
14. Source and destination requests single and burst DMACA transactions to transfer the
bl ock of data (assuming non-memory peripherals). The DMACA acknowledges at the
completion of every transactio n (burst and single) in the block and carry out the block
transfer.
Note:
15. The DMACA does not wait for the block interrupt to be cleared, but continues and
fetches the next LLI from the memo ry location pointed to by current LLPx register and
automatically reprograms the SARx, CTLx and LLPx channel registers. The DARx reg-
ister is left unchanged. The DMA tr ansfer cont inues until the DMA CA samples the CTLx
and LLPx register s at t he en d of a block tr ansfer match that described in Ro w 1 or Row
345
32072H–AVR32–10/2012
AT32UC3A3
5 of Table 19-1 on page 327. The DMACA then knows that the previous block trans-
ferred was the last block in the DMA transfer.
The DMACA transfer might look like that shown in Figure 19-17 on page 345 Note that the des-
tination address is decrementing.
Figure 19-17. DMA Transfer with Linked List Source Address and Contiguous Destination
Address
The DMA transfer flow is shown in Figure 19-19 on page 346 .
Figure 19-18.
SAR(2)
SAR(1)
SAR(0)
DAR(2)
DAR(1)
DAR(0)
Block 2
Block 1
Block 0
Block 0
Block 1
Block 2
Address of
Source Layer Address of
Destination Layer
Source Blocks Destination Blocks
346
32072H–AVR32–10/2012
AT32UC3A3
Figure 19-19. DMA Transfer Flow for Source Address Auto-reloaded and Contiguous Destination Address
19.11 Disabling a Channel Prior to Transfer Completion
Under normal op erat ion, sof t ware en ables a ch ann el by writing a ‘1 ’ t o the Channe l Ena ble Reg-
ister, ChEnReg.CH_EN, and hardware disa bles a chann el on transfe r completion by cle aring the
ChEnReg.CH_EN register bit.
The recommended way for software to disable a channel without losing data is to use the
CH_SUSP bit in conjunction with the FIFO_EMPTY bit in the Channel Config uration Register
(CFGx) register.
1. If software wishes to disa ble a ch annel prior to the DMA transf er completion, then it ca n
set the CFGx.CH_SUSP bit to tell the DMACA to halt all transf ers from the source
peripheral. Therefore, the channel FIFO receives no new data.
2. Software can now poll the CFGx.FIFO_EMPTY bit until it indicates that the channel
FIFO is empty.
Channel Enabled by
software
LLI Fetch
Hardware reprograms
SARx, CTLx, LLPx
DMAC block transfer
Source/destination
status fetch
Is DMAC in
Row 1 of Table 4 ?
Channel Disabled by
hardware
Block Complete interrupt
generated here
DMAC Transfer Complete
interrupt generated here yes
no
347
32072H–AVR32–10/2012
AT32UC3A3
3. The ChEnReg.CH_EN bit can then be cleared by software once the channel FIFO is
empty.
When CTLx.SRC_TR_WIDTH is less than CTLx.D ST_TR_WIDTH and the CFGx.CH_SUSP bit
is high, the CFGx.FIFO_ EMPTY is asserted once t he contents of th e FIFO do not perm it a single
word of CTLx.DST_TR_WIDTH to be formed. However, there may still be d ata in the channel
FIFO but not enough to form a single transfe r of CTLx.DST_TR_WIDTH width. In this configura-
tion, once the channel is disabled, the remaining data in the channel FIFO are not transferred to
the destination peripheral. It is permitted to remove the ch annel from the suspension state by
writing a ‘0’ to the CFGx.CH_SUSP register. The DMA transfer completes in the normal manner.
Note: If a channel is disabled by software, an active single or burst transaction is not guaranteed to
receive an acknowledgement.
19.11.1 Abnormal Transfer Termination
A DMACA DMA transfer may be te rminated abruptly by software by clearing the channel enable
bit, ChEnReg.CH_EN. This does not mean that the channel is disabled immediately after the
ChEnReg.CH_EN bit is cleared over the HSB slave interface. Consider this as a request to dis-
able the channel. The ChEnReg.CH_EN must be polled and then it must be confirmed that the
channel is disabled by rea ding back 0. A case wh ere the channel is not be disabled a fter a chan-
nel disable request is where either the source or destination has received a split or retry
response. The DMACA must kee p re-attempting the transfer to the system HADDR that origi-
nally received the split or retry response until an OKAY response is returned. To do otherwise is
an System Bus protoco l vi ola tion.
Software may termin ate all channels abruptly by clearin g the global enable bit in the DMACA
Configuration Register (DmaCfgReg[0]). Again, this does not mean that all channels are dis-
abled immediate ly after the DmaCfgReg[0] is cle ared over the HSB slave interfac e. Consider
this as a request to disable all channels. The ChEnReg must be polled and then it must be con-
firmed that all channels are disabled by reading back ‘0’.
Note: If the channel enable bit is cleared while there is data in the channel FIFO, this data is not sent to
the destination peripheral and is not present when the channel is re-enabled. Fo r read sensitive
source peripherals such as a source FIFO this data is therefore lost. When the source is not a
read sensitive device (i.e., memory), disabling a channel without waiting for the channel FIFO to
empty may be acceptable as the data is available from the source peripheral upon request and is
not lost.
Note: If a channel is disabled by software, an active single or burst transaction is not guaranteed to
receive an acknowledgement.
348
32072H–AVR32–10/2012
AT32UC3A3
19.12 User Interface
Table 19-2. DMA Controller Mem or y Ma p
Offset Register Register Name Access Reset Value
0x000 Channel 0 Source Address Registe r SAR0 Read/Write 0x00000000
0x008 Channel 0 Destination Address Register DAR0 Read/Write 0x00000000
0x010 Channel 0 Linked List Pointer Register LLP0 Read/Write 0x00000000
0x018 Channel 0 Control Register Low CTL0L Read/Write 0x00304801
0x01C Channel 0 Contro l Register High CTL0H Read/Write 0x00000002
0x040 Channel 0 Configuration Register Low CFG0L Read/Write 0x00000c00
0x044 Chann el 0 Configuration Register High CFG0H Read/Wr ite 0x00000004
0x048 Channel 0 Source Gather Register SGR0 Read/Write 0x00000000
0x050 Channel 0 Destination Scatter Register DSR0 Read/Write 0x0 0000000
0x058 Channel 1 Source Address Registe r SAR1 Read/Write 0x00000000
0x060 Channel 1 Destination Address Register DAR1 Read/Write 0x00000000
0x068 Channel 1 Linked List Pointer Register LLP1 Read/Write 0x00000000
0x070 Channel 1 Control Register Low CTL1L Read/Write 0x00304801
0x074 Channel 1 Contro l Register High CTL1H Read/Write 0x00000002
0x098 Channel 1 Configuration Register Low CFG1L Read/Write 0x00000c20
0x09C Channel 1 Configuration Register Hi gh CFG1H Read/Write 0x00000004
0x0A0 Channel 1Source Gather Register SGR1 Read/Write 0x00000000
0x0A8 Channe l 1 Destination Scatter Register DSR1 Read/Write 0x00000000
0x0B0 Channel 2 Source Address Register SAR2 Read/Write 0x00000000
0x0B8 Channel 2 Destination Address Register DAR2 Read/Write 0x0 0000000
0x0C0 Channel 2 Linked List P ointer Register LLP2 Read/Write 0x00000000
0x0C8 Channel 2 Control Register Low CTL2L Read/Write 0x00304801
0x0CC Channel 2 Control Register High CTL2H Read/Write 0x00000 002
0x0F0 Channe l 2 Configuration Register Low CFG2L Read/Write 0x00000c40
0x0F4 Channel 2 Configuration Register Hi gh CFG2H Read/Write 0x00000004
0x0F8 Channel 2 Source Gather Register SGR2 Read/Write 0x00000000
0x100 Channel 2 Destination Scatter Register DSR2 Read/Write 0x0 0000000
0x108 Channel 3 Source Address Registe r SAR3 Read/Write 0x00000000
0x110 Channel 3 Destination Address Register DAR3 Read/Write 0x00000000
0x118 Channel 3 Linked List Pointer Register LLP3 Read/Write 0x00000000
0x120 Channel 3 Control Register Low CTL3L Read/Write 0x00304801
0x124 Channel 3 Contro l Register High CTL3H Read/Write 0x00000002
0x148 Channel 3 Configuration Register Low CFG3L Read/Write 0x00000c60
0x14c Channel 3 Con figuration Register High CFG3H Read/Write 0x0 0000004
0x150 Channel 3 Source Gather Register SGR3 Read/Write 0x00000000
349
32072H–AVR32–10/2012
AT32UC3A3
0x158 Channel 3Destinatio n Scatter Register DSR3 Read/W rite 0x00000000
0x2C0 Raw Status for IntTfr Interrupt RawTfr Read-only 0x00000000
0x2C8 Raw Status for IntBlock Interrupt RawBlock Read-only 0x00000000
0x2D0 Raw Status for IntSrcTran Interrupt RawSrcTran Read-only 0x00000000
0x2D8 Raw Status for IntDstTran Interrupt RawDstTran Read-only 0x00000000
0x2E0 Raw Status for IntErr Interrupt R awErr Read-on ly 0x00000000
0x2E8 Status for IntTfr Interrupt StatusTfr Read-only 0x00000000
0x2F0 Status for IntBlock Interrupt StatusBlock Re ad-only 0x00000000
0x2F8 Status for IntSrcTran Interrupt S tatusSrcTran Read-only 0x00000000
0x300 Status for IntDstTran Interrupt StatusDstTran Read-only 0x00000000
0x308 Status for IntErr Interrupt StatusErr Read-only 0x00000000
0x310 Mask for IntTfr Interrupt MaskTfr Read/Write 0x00000000
0x318 Mask for IntBlock Interrupt MaskBlock Read/Write 0x00000000
0x320 Mask for IntSrcTran Interrupt MaskSrcTran Read/Wr ite 0x00000000
0x328 Mask for IntDstTran Interrupt MaskDstTran Read/Wr ite 0x00000000
0x330 Mask for IntErr Interrupt MaskErr Read/Write 0x00000000
0x338 Cl ear for IntTfr Interrupt ClearTfr Write-only 0x00000000
0x340 Clear for IntBlock Interrupt ClearBlock Write-only 0x00000000
0x348 Clear for IntSrcTran Interrupt ClearSrcTran Write-only 0x00000000
0x350 Clear for IntDstTran Interrupt ClearDstTran Write-only 0x00000000
0x358 Clear for IntErr Interrupt ClearErr Write-only 0x00000000
0x360 Status for each interrupt type StatusInt Read-only 0x00000000
0x368 Source Software Transaction Req uest Register ReqSrcReg Read/Write 0x00000000
0x370 Destination Software Transaction Request Register ReqDstReg Read/W rite 0x00000000
0x378 Single Source Transaction Request Register SglReqSrcReg Read/Write 0x00000000
0x380 Single Destination Transaction Request Register SglReqDstReg Read/Write 0x00000000
0x388 Last Sou rce Transaction Request Register LstSrcReg Read/Write 0x00000000
0x390 Last Destination Transaction Request Register LstDstReg Read/Write 0x00000000
0x398 DMA Configuration Register DmaCfgReg Read/Write 0x00000000
0x3A0 DMA Channel Enable Register ChEnReg Read/Write 0x00000000
0x3F8 DMA Component ID Register Low DmaCompIdRegL Read-only 0x44571110
0x3FC DMA Component ID Register High DmaCompIdRegH Read-only 0x3230362A
Table 19-2. DMA Controller Memory Map (Continued)
Offset Register Register Name Access Reset Value
350
32072H–AVR32–10/2012
AT32UC3A3
19.12.1 Channel x Source Address Register
Name: SARx
Access Type: Read/Write
Offset: 0x0 00 + [x * 0x58]
Reset Value: 0x00000000
• SADD: Source Address of DMA transfer
The starting Syste m Bus sour ce address is programmed by software be fore the DM A channel is enabled o r by a LLI u pdate
before the start of the DMA transfer. As the DMA transfer is in progress, this register is updated to reflect the source
address of the current System Bus transfer.
Updated after each source System Bus transfer. The SINC field in the CTLx regist er determin es whether the ad dress incre-
ments, decr ements, or is left unchanged on every source System Bus transfer throughout the block transfer.
31 30 29 28 27 26 25 24
SADD[31:24]
23 22 21 20 19 18 17 16
SADD[23:16]
15 14 13 12 11 10 9 8
SADD[15:8]
76543210
SADD[7:0]
351
32072H–AVR32–10/2012
AT32UC3A3
19.12.2 Channel x Destinatio n Address Register
Name: DARx
Access Type: Read/Write
Offset: 0x0 08 + [x * 0x58]
Reset Value: 0x00000000
• DADD: Destination Address of DMA transfer
The starting System Bus de stination address is programmed b y software before the DMA cha nnel is enabled or by a L LI
update before the start of the DMA transfer. As the DMA transfer is in progress, this register is updated to reflect the desti-
nation address of the current System Bus transfer.
Updated after each destination System Bus transfer. The DINC field in the CTLx register determines whether the address
increments, decrements or is left unchanged on every destination System Bus transfer throughout the block transfer.
31 30 29 28 27 26 25 24
DADD[31:24]
23 22 21 20 19 18 17 16
DADD[23:16]
15 14 13 12 11 10 9 8
DADD[15:8]
76543210
DADD[7:0]
352
32072H–AVR32–10/2012
AT32UC3A3
19.12.3 Linked List Pointer Register for Channel x
Name: LLPx
Access Type: Read/Write
Offset: 0x0 10 + [x * 0x58]
Reset Value: 0x00000000
• LOC: Address of the next LLI
Starting address in memory of next LLI if block chaining is enabled.
The user need to program this register to point to the first Linked List Item (LLI) in memory prior to enabling the channel if
block chaining is enable d.
The LLP register has two functions:
The logical result of the equation LLP.LOC != 0 is used to set up the t ype of DMA transfer (single or multi-block).
If LLP.LOC is set to 0x0, then transfers using linked lists are NOT enabled. This register must be programmed prior to
enabling the channel in order to set up the transfer type.
It (LLP.LOC != 0) contains the poin ter to the next Linked Listed Item for block chaining using linked lists. In th is case,
LOC[29:0] corresponds to A[31:2] of the next Linked Listed Item address
The LLPx register is also used to point to the address where write back of the control and source/destination status infor-
mation occurs after block completion.
• LMS: List Master Select
Identifies the High speed bus interface for the device that stores the next linked list item:
31 30 29 28 27 26 25 24
LOC[29:22]
23 22 21 20 19 18 17 16
LOC[21:14]
15 14 13 12 11 10 9 8
LOC[13:6]
76543210
LOC[5:0] LMS
Table 19-3. List Master Select
LMS HSB Master
0 HSB master 1
1 HSB master 2
Other Reserved
353
32072H–AVR32–10/2012
AT32UC3A3
19.12.4 Control Register for Channel x Low
Name: CTLxL
Access Type: Read/Write
Offset: 0x0 18 + [x * 0x58]
Reset Value: 0x00304801
This register cont ains fields that con trol the DMA transfer. T he CTLxL reg ister is part o f the block descriptor (linke d list it em)
when block chaining is enabled. It can be varied on a block-b y-block basis within a DMA transfer when block chaining is
enabled.
• LLP_SRC_EN
Block chaining is only enabled on the source side if the LLP_SRC_EN field is high and LLPx.LOC is non-zero.
• LLP_DST_EN
Block chaining is only enabled on the destination side if the LLP_DST_EN field is high and LLPx.LOC is non- zero.
• SMS: Source Master Select
Identifies the Master Interface layer where the source device (peripheral or memory) is accessed from
31 30 29 28 27 26 25 24
LLP_SRC_E
NLLP_DST_E
NSMS DMS[1]
23 22 21 20 19 18 17 16
DMS[0] TT_FC DST_GATHE
R_EN SRC_GATHE
R_EN SRC_MSIZE
[2]
15 14 13 12 11 10 9 8
SRC_MSIZE[1:0] DEST_MSIZE SINC DINC[1]
76543210
DINC[0] SRC_TR_WIDTH DST_TR_WIDTH INT_EN
Table 19-4. Source Master Select
SMS HSB Master
0 HSB master 1
1 HSB master 2
Other Reserved
354
32072H–AVR32–10/2012
AT32UC3A3
•DMS: Destination Master Select
Identifies the Master Interfac e laye r where the destinatio n de vice (pe rip h er al or memo ry) resides
• TT_FC: Transfer Type and Flow Contr ol
The four following transfer types are supported:
• Memory to Memory, Memory to Peripheral, Peripheral to Memory and Peripheral to Peripheral.
The DMACA is always the Flow Controller.
• DST_SCATTER_EN: Destina tion Scatter Enable
0 = Scatter disabled
1 = Scatter enabled
Scatter on the destination side is applicable only when the CTLx.DINC bit indicates an incrementing or decrementing
address control.
• SRC_GATHER_EN: Source Gather Enable
0 = Gather disabled
1 = Gather enabled
Gather on the source side is applicable only when the CTLx.SINC bit indicates an incrementing or decrementing address
control.
• SRC_MSIZE: Source Burst Transaction Length
Number of data items, each of width CTLx.SRC_TR_WIDTH, to be read f rom the source every ti me a source burst transac-
tion request is made from either the corresponding hardware or software handshaking interface.
Table 19-5. Destination Master Select
DMS HSB Master
0 HSB master 1
1 HSB master 2
Other Reserved
TT_FC Transfer Type Flow Controller
000 Memory to Memory DMACA
001 Memory to Peripheral DMACA
010 Peripheral to Memory DMACA
011 Peripheral to Peripheral DMA CA
Other Reserved Reserved
SRC_MSIZE Size (items number)
01
14
28
355
32072H–AVR32–10/2012
AT32UC3A3
• DST_MSIZE: Destination Burst Transaction Length
Number of data items, each of width CTLx.DST_TR_WIDTH, to be written to the destination every time a destination burst
transaction request is mad e from either the correspondin g hardware or software handshaking interface.
•SINC: Source Address Increment
Indicates whether to increment or decrement the source address on every source System Bus transfer. If your device is
fetching data from a source peripheral F IFO with a fixed address, then set this fi eld to “No change”
• DINC: Destination Address Increment
Indicates whether to increment or decrement the destination address on every destination System Bus transfer. If your
device is writing data to a destination peripheral FIFO with a fixed address, then set this field to “No change”
316
432
Other Reserved
DST_MSIZE Size (items number)
01
14
28
316
432
Other Reserved
SINC Source Address
Increment
0 Increment
1 Decrement
Other No change
DINC Destination Address
Increment
0 Increment
1 Decrement
Other No change
SRC_MSIZE Size (items number)
356
32072H–AVR32–10/2012
AT32UC3A3
• SRT_TR_WIDTH: Source Transfer Width
• DSC_TR_WIDTH: Destination Transfer Width
• INT_EN: Interrupt Enable Bit
If set, then all fi ve interrupt generating sources are enabled.
SRC_TR_WIDTH/DST_TR_WIDTH Size (bits)
08
116
232
Other Reserved
357
32072H–AVR32–10/2012
AT32UC3A3
19.12.5 Control Regi ster for Channel x High
Name: CTLxH
Access Type: Read/Write
Offset: 0x01C + [x * 0x58]
Reset Value: 0x00000002
• DONE: Done Bit
Software can poll this bit to see when a block transfer is complete
• BLOCK_TS: Block Transfer Size
When the DMACA is flow controller, this field is written by the user before the chann el is en abled to indicate th e block size.
The number progr ammed into BLOCK_TS indicates the total number of single transactions to perfo rm for every block
transfer, unless the transfer is already in progress, in which case the value of BLOCK_ TS indicates the number of single
transactions that have been performed so far.
The width of the single transaction is determined by CTLx.SRC_TR_WIDTH.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
- - - DONE BLOCK_TS[11:8]
76543210
BLOCK_TS[7:0]
358
32072H–AVR32–10/2012
AT32UC3A3
19.12.6 Configuration Register for Channel x Low
Name: CFGxL
Access Type: Read/Write
Offset: 0x0 40 + [x * 0x58]
• Reset Value: 0x00000C00 + [x * 0x20]
•RELOAD_DST: Automatic Des tination Reload
The DARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A
new block transfer is then initiated.
• RELOAD_SRC: Automatic Source Reload
The SARx register can be automatically reloaded from its initial value at the end of every block for multi-block transfers. A
new block transfer is then initiated.
• SRC_HS_POL: Source Handshaking Interface Polarity
0 = Active high
1 = Active low
• DST_HS_POL: Destination Ha nd shaking Interface Polarity
0 = Active high
1 = Active low
• HS_SEL_SRC: Source Software or Hardware Handshaking Select
This register selects which of the handshaking interfaces, hardware or software, is active for source requests on this
channel.
0 = Hardware handshaking interface. Software-initiated transaction requests are ignored.
1 = Software handshaking interface. Hardware-initiated transaction requests are ignored.
If the source peripheral is memory, then this bit is ignored.
• HS_SEL_DST: Destination Software or Hardware Handshaking Select
This register selects which of the handshaking interfaces, hard ware or software, is active for destination requests on this
channel.
31 30 29 28 27 26 25 24
RELOAD_D
ST RELOAD_S
RC ------
23 22 21 20 19 18 17 16
- - - - SRC_HS_P
OL DST_HS_PO
L--
15 14 13 12 11 10 9 8
--HS_SEL_SR
CHS_SEL_DS
TFIFO_EMPT
YCH_SUSP
76543210
CH_PRIOR - - - - -
359
32072H–AVR32–10/2012
AT32UC3A3
0 = Hardware handshaking interface. Software-initiated transaction requests are ignored.
1 = Software handshaking interface. Hardware Initiated transaction requests are ignored.
If the destination peripheral is memory, then this bit is ignored.
• FIFO_EMPTY
Indicates if there is data left in the channel's FIFO. Can be used in conjunction with CFGx.CH_SUSP to cleanly disable a
channel.
1 = Channel's FIFO empty
0 = Channel's FIFO not empty
• CH_SUSP: Channel Suspend
Suspends all DMA data tr an sfer s fr om th e sour ce un til th is b it is clea red. The re is n o g uar ante e t ha t the curren t t ransa ct ion
will complete. Can also be used in conjunction with CFGx.FIFO_EMPTY to cleanly disable a channel without losing any
data.
0 = Not Suspended.
1 = Suspend. Suspend DMA transfer from the source.
• CH_PRIOR: Channel priority
A priority of 7 is the highest priority, and 0 is the lowest. This field must be programmed within the following range [0, x-1].
A programmed value outside th is range causes erroneous behavior.
360
32072H–AVR32–10/2012
AT32UC3A3
19.12.7 Configuration Register for Channel x High
Name: CFGxH
Access Type: Read/Write
Offset: 0x0 44 + [x * 0x58]
Reset Value: 0x00000004
• DEST_PER: Destination Hardware Handshaking Interface
Assigns a hardware handshaking interface (0 - DMAH_NUM_HS_INT-1) to the destination of channel x if the
CFGx.HS_SEL_DST field is 0. Otherwise, this field is ignored. The channe l can then communicate with the de stination
peripheral connected to t hat interface via the assigned hardware handshaking interface.
For correct DMA operation, only one peripheral (source or destination) should be assigned to the same handshaking
interface.
• SRC_PER: Source Har dware Handshaking Interface
Assigns a hardware handshaking interface (0 - DMAH_NUM_HS_INT-1) to the source of channel x if the
CFGx.HS_SEL_SRC field is 0. Otherwise, this field is ignored. The channel can then com m unica te with th e sou r ce pe r i ph -
eral connected to that interface via the assigned hardware handshaking interface.
For correct DMACA operation, only one peripheral (source or destination) should be assigned to the same handshaking
interface.
•PROTCTL: Protection Control
Bits used to drive the System Bus HPROT[3:1] bus. The System Bus Specification recommends that the default value of
HPROT indicates a non-cached, nonbuffered, privile ged data access. The reset value is used to indicate such an access.
HPROT[0] is tied h igh as a ll t ransf ers ar e d ata acce sse s as t he re ar e no op co de f et ches. Th ere is a o ne- to- one ma pping of
these register bits to the HPROT[3:1] master interface signals.
•FIFO_MODE: R/W 0x0 FI FO Mode Select
Determines how much space or data needs to be available in the FIFO bef ore a burst transaction request is serviced.
0 = Space/data available for single System Bus transfer of the specified transfer width.
1 = Space/data available is greater than or equal to half the FIFO depth for destination transfers and less than half the FIFO
depth for source transf e rs. The exceptions are at the end of a burst transaction request or at the end of a block transfer.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
- DEST_PER SRC_PER[3:1]
76543210
SRC_PER[0] - - PROTCTL FIFO_MODE FCMODE
361
32072H–AVR32–10/2012
AT32UC3A3
•FCMODE: Flow Control Mode
Determines when source transaction requests are serviced when the Destination Peripheral is the flow controller.
0 = Source transaction requests are serviced when they occur. Data pre-fetching is enabled.
1 = Source transaction requests are not serviced until a destination transaction request occurs. In this mode the amount of data
transferred from the source is limited such that it is guaranteed to be transferred to the destination prior to block termination by
the destination. Data pre-fetching is disabled.
362
32072H–AVR32–10/2012
AT32UC3A3
19.12.8 Source Gather Register for Channel x
Name: SGRx
Access Type: Read/Write
Offset: 0x0 48 + [x * 0x58]
Reset Value: 0x00000000
• SGC: Source Gather Count
Specifies the number of contiguous source transfers of CTLx.SRC_TR_WIDTH between successive gather intervals. This
is defined as a gather boundary.
•SGI: Source Gather Interval
Specifies the source address increment/decrement in multiples of CTLx.SRC_TR_WIDTH on a gather boundary when
gather mode is enabled for the source transfer.
31 30 29 28 27 26 25 24
SGC[11:4]
23 22 21 20 19 18 17 16
SGC[3:0] SGI[19:16]
15 14 13 12 11 10 9 8
SGI[15:8]
76543210
SGI[7:0]
363
32072H–AVR32–10/2012
AT32UC3A3
19.12.9 Destination Scatter Re gister for Channel x
Name: DSRx
Access Type: Read/Write
Offset: 0x0 50 + [x * 0x58]
Reset Value: 0x00000000
• DSC: Destination Scatter Count
Specifies the number of contiguous destination transfers of CTLx.DST_TR_WIDTH between successive scatter
boundaries.
•DSI: Destination Scatter Interval
Specifies the destination address increment/decrement in multiples of CTLx.DST_TR_WIDTH on a scatter boundary when
scatter mode is enabled for the destination transfer.
31 30 29 28 27 26 25 24
DSC[11:4]
23 22 21 20 19 18 17 16
DSC[3:0] DSI[19:16]
15 14 13 12 11 10 9 8
DSI[15:8]
76543210
DSI[7:0]
364
32072H–AVR32–10/2012
AT32UC3A3
19.12.10 Interrupt Registers
The following sections describe the register s pert aining to interru pts, their st atus, an d how to clea r them. Fo r each chann el,
there are five types of interrupt sources:
• IntTfr: DMA Transfer Complete Interrupt
This interrupt is generated on DMA transfer completion to the destina tion peripheral.
• IntBlock: Block Transfer Complete Interrupt
This interrupt is generated on DMA block transfer completion to the destination peripheral.
• IntSrcTran: Source Transaction Complete Interrupt
This interrupt is generated after completion of the last System Bus transfer of the requested single/burst transaction from
the handshaking interface on the source side.
If the source for a channel is memor y, th en tha t chan nel never gene ra te s a Int SrcTr an inte rr upt and hen ce the correspon d-
ing bit in this field is not set.
• IntDstTran: Destination Transaction Complete Interrupt
This interrupt is generated after completion of the last System Bus transfer of the requested single/burst transaction from
the handshaking interface on the destination side.
If the destination for a channel is memory, then that channel never generates the IntDstTran interrupt and hence the corre-
sponding bit in this field is not set.
• IntErr: Error Interrupt
This interrupt is generated when an ERROR response is received from an HSB slave on the HRESP bus during a DMA
transfer. In addition, the DMA transfer is cancelled and the channel is disabled.
365
32072H–AVR32–10/2012
AT32UC3A3
19.12.11 Interrupt Raw Status Registers
Name: RawTfr, RawBlock, RawSrcTran, RawDstTra n , RawErr
Access Type: Read-only
Offset: 0x2C0, 0x2C8, 0x2D0, 0x2D8, 0x2E0
Reset Value: 0x00000000
• RAW[3:0]Raw interrupt for each channel
Interrupt events are stored in these Raw Interrupt Status Registers before masking: RawTfr, RawBlock, RawSrcTran,
RawDstTran, RawErr. Each Raw Interrupt Status register has a bit allocated per channel, for example, RawTfr[2] is Chan-
nel 2’s raw transfer complete interrupt. Each bit in these registers is cleared by writing a 1 to the corresponding location in
the ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran, ClearErr registers.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
- - - - RAW3 RAW2 RAW1 RAW0
366
32072H–AVR32–10/2012
AT32UC3A3
19.12.12 Interrupt Status Registers
Name: StatusTfr, StatusBlock, StatusSrcTran, StatusDstTran, StatusErr
Access Type: Read-only
Offset: 0x2E8, 0x2F0, 0x2F8, 0x300, 0x308
Reset Value: 0x00000000
• STATUS[3:0]
All interrupt events from all channels are stored in these Interrupt Status Registers after masking: StatusTfr, StatusBlock,
StatusSrcTran, StatusDstTran, StatusErr. Each Interrupt Status register has a bit allocated per channel, for example, Sta-
tusTfr[2] is Channel 2’s status transfer complete interr upt.Th e conten ts of these r egist ers are used t o gene rate th e interru pt
signals leaving the DMACA.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
- - - - STATUS3 STATUS2 STATUS1 STATUS0
367
32072H–AVR32–10/2012
AT32UC3A3
19.12.13 Interrupt Mask Registers
Name: MaskTfr, MaskBlock, MaskSrcTran, MaskDstTran, MaskErr
Access Type: Read/Write
Offset: 0x310, 0x318, 0x320, 0x328, 0x330
Reset Value: 0x00000000
The contents of t he Raw Status Registers are masked with t he contents of the Mask Regist ers: MaskTfr, MaskBlock, Mask-
SrcTran, MaskDstTran, MaskErr. Each Interrupt Mask register has a bit allocated per channel, for example, MaskTfr[2] is
the mask bit for Channel 2’s transfer complete interrupt.
A channel’s INT_MASK bit is only written if the corresponding mask write enable bit in the INT_MASK_WE field is asserted
on the same System Bus write transfer. This allows software to set a mask bit without performing a read-mod ified write
operation.
For example, writing hex 01x1 to the MaskTfr register writes a 1 into MaskTfr[0], while MaskTfr[7:1] remains unchanged.
Writing hex 00xx leaves MaskTfr[7:0] unchanged.
Writing a 1 to any bit in these registers unmasks the corresponding interrupt, thus allowing the DMACA to set the approp ri-
ate bit in the Status Registers.
• INT_M_WE[11:8]: Interrupt Mask Write Enable
0 = Write disabled
1 = Write enabled
• INT_MASK[3:0]: Interrupt Mask
0= Masked
1 = Unmasked
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
- - - - INT_M_WE3 INT_M_WE2 INT_M_WE1 INT_M_WE0
76543210
- - - - INT_MASK3 INT_MASK2 INT_MASK1 INT_MASK0
368
32072H–AVR32–10/2012
AT32UC3A3
19.12.14 Interrupt Clear Registers
Name: ClearTfr, ClearBlock, ClearSrcTran, ClearDstTran, Cle ar Err
Access Type: Write-only
Offset: 0x338, 0x340, 0x348, 0x350, 0x358
Reset Value: 0x00000000
• CLEAR[3:0]: Interrupt Clear
0 = No effect
1 = Clear interrupt
Each bit in the Raw Status and Status registe rs is cleared on t he same cycle by writ ing a 1 to the corresp ond ing locati on in
the Clear r egisters: Clea rTfr, Cle arBlock, ClearSr cTran, Clear DstTran, Cle arErr. Each Interrupt Clear regist er has a bit allo-
cated per channel, for exam ple, ClearTfr[2] is the clear bit for Chan nel 2’s transfer complete interrupt. Writing a 0 has no
effect. These registers are not readable.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
- - - - CLEAR3 CLEAR2 CLEAR1 CLEAR0
369
32072H–AVR32–10/2012
AT32UC3A3
19.12.15 Combined Interrupt Status Registers
Name: StatusInt
Access Type: Read-only
Offset: 0x360
Reset Value: 0x00000000
The contents of each of the five Status Registers (StatusTfr, StatusBlock, StatusSrcTran, StatusDstTran, StatusErr) is
OR’ed to produce a single bit per interrupt type in the Combined Status Register (StatusInt).
•ERR
OR of the contents of StatusErr Register.
•DSTT
OR of the contents of StatusDstTran Register.
• SRCT
OR of the contents of StatusSrcTran Register.
•BLOCK
OR of the contents of StatusBlock Register.
•TFR
OR of the contents of StatusTfr Register.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
- - - ERR DSTT SRCT BLOCK TFR
370
32072H–AVR32–10/2012
AT32UC3A3
19.12.16 Source Software Transaction Request Register
Name: ReqSrcReg
Access Type: Read/write
Offset: 0x368
Reset Value: 0x00000000
A bit is assigned for each channel in this register. ReqSrcReg[n] is ignored when software handshaking is not enabled for
the source of channel n.
A channel SRC_REQ bit is written only if the corr esponding chann el write enable bit in the REQ_WE field is asserted on
the same System Bus write tr ansfer.
For example, writing 0x101 writes a 1 into ReqSrcReg[0], while ReqSrcReg[4:1] remains unchanged. Writing hex 0x0yy
leaves ReqSrcReg[4:0] unchanged. This allows software to set a bit in the ReqSrcReg register without performing a read-
modified write
• REQ_WE[11:8]: Request write enable
0 = Write disabled
1 = Write enabled
• SRC_REQ[3:0]: Source request
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
- - - - REQ_WE3 REQ_WE2 REQ_WE1 REQ_WE0
76543210
- - - - SRC_REQ3 SRC_REQ2 SRC_REQ1 SRC_REQ0
371
32072H–AVR32–10/2012
AT32UC3A3
19.12.17 Destination Software Transaction Request Register
Name: ReqDstReg
Access Type: Read/write
Offset: 0x370
Reset Value: 0x00000000
A bit is assigned for each channel in this register. ReqDstReg[n] is ignored when software handshaking is not enabled for
the source of channel n.
A channel DST_REQ bit is written only if the corresponding ch annel write enable bit in the REQ_WE fi eld is asserted on t he
same System Bus write transfer.
• REQ_WE[11:8]: Request write enable
0 = Write disabled
1 = Write enabled
• DST_REQ[3:0]: Destination request
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
- - - - REQ_WE3 REQ_WE2 REQ_WE1 REQ_WE0
76543210
- - - - DST_REQ3 DST_REQ2 DST_REQ1 DST_REQ0
372
32072H–AVR32–10/2012
AT32UC3A3
19.12.18 Single Source Transaction Request Register
Name: SglReqSrcReg
Access Type: Read/write
Offset: 0x378
Reset Value: 0x00000000
A bit is assigned for each channel in this register. SglReqSrcReg[n] is ignore d when softwar e handshak ing is not enable d
for the source of chan n el n.
A channel S_SG_REQ bit is written only if the corresponding channel write enable bit in the REQ_WE field is a sserted on
the same System Bus write tr ansfer.
• REQ_WE[11:8]: Request write enable
0 = Write disabled
1 = Write enabled
• S_SG_REQ[3:0]: Source single request
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
- - - - REQ_WE3 REQ_WE2 REQ_WE1 REQ_WE0
76543210
- - - - S_SG_REQ3 S_SG_REQ2 S_SG_REQ1 S_SG_REQ0
373
32072H–AVR32–10/2012
AT32UC3A3
19.12.19 Single Destination Transaction Request Register
Name: SglReqDstReg
Access Type: Read/write
Offset: 0x380
Reset Value: 0x0000000
A bit is assigned for each channel in this register. SglReqDstReg[n] is igno red when softw are handsh aking is not enab led
for the source of chan n el n.
A channel D_SG_REQ bit is written only if the corresponding channel write enable bit in the REQ_WE field is asserted on
the same System Bus write tr ansfer.
• REQ_WE[11:8]: Request write enable
0 = Write disabled
1 = Write enabled
• D_SG_REQ[3:0]: Destination sing le request
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
- - - - REQ_WE3 REQ_WE2 REQ_WE1 REQ_WE0
76543210
- - - - D_SG_REQ3 D_SG_REQ2 D_SG_REQ1 D_SG_REQ0
374
32072H–AVR32–10/2012
AT32UC3A3
19.12.20 Last Source Transaction Request Register
Name: LstSrcReg
Access Type: Read/write
Offset: 0x388
Reset Value: 0x0000000
A bit is assigned for each channel in this register. LstSrcReg[n] is ignored whe n software handshaking is not enabled for
the source of channel n.
A channel LSTSRC bit is written only if the corresponding channel write enable bit in the LSTSRC_WE field is asserted on
the same System Bus write tr ansfer.
• LSTSRC_WE[11:8]: Source Last Transaction request write enable
0 = Write disabled
1 = Write enabled
• LSTSRC[3:0]: Source Last Transaction request
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
----LSTSRC_W
E3 LSTSRC_W
E2 LSTSRC_W
E1 LSTSRC_W
E0
76543210
- - - - LSTSRC3 LSTSRC2 LSTSRC1 LSTSRC0
375
32072H–AVR32–10/2012
AT32UC3A3
19.12.21 Last Destination Transaction Request Register
Name: LstDstReg
Access Type: Read/write
Offset: 0x390
Reset Value: 0x00000000
A bit is assigned for each channel in this register. LstDstReg[n] is ignored whe n software handshaking is not enabled for
the source of channel n.
A channel LSTDST bit is written only if the corresponding channel write enable bit in the LSTDST_WE field is asserted on
the same System Bus write tr ansfer.
• LSTDST_WE[11:8]: Destination Last Transaction request write enable
0 = Write disabled
1 = Write enabled
• LSTDST[3:0]: Destination Last Transaction request
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
- - - - LSTDST_WE
3LSTDST_WE
2LSTDST_WE
1LSTDST_WE
0
76543210
- - - - LSTDST3 LSTDST2 LSTDST1 LSTDST0
376
32072H–AVR32–10/2012
AT32UC3A3
19.12.22 DMA Configuration Register
Name: DmaCfgReg
Access Type: Read/Write
Offset: 0x398
Reset Value: 0x00000000
• DMA_EN: DMA Controller Enable
0 = DMACA Disabled
1 = DMACA Enabled.
This register is used to enab le the DMACA, which must be done before any channel activity can begin.
If the global channel enable bit is cleared while any channel is still active, then DmaCfgReg.DMA_EN still returns ‘1’ to indi-
cate that there are channels still active until hardware has terminated all activity on all channels, at which point the
DmaCfgReg.DMA_EN bit returns ‘0’.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
-------DMA_EN
377
32072H–AVR32–10/2012
AT32UC3A3
19.12.23 DMA Channel Enable Register
Name: ChEnReg
Access Type: Read/Write
Offset: 0x3A0
Reset Value: 0x00000000
• CH_EN_WE[11:8]: Channel Enable Write Enable
The channel enable bit, CH_EN, is only written if the corresponding channel write enable bit, CH_EN_WE, is asserted on
the same System Bus write tr ansfer.
For example, writing 0x1 01 writes a 1 into ChEnReg[0], while ChEnReg[7:1] remains unchanged.
• CH_EN[3:0]
0 = Disable the Channel
1 = Enable the Channel
Enables/Disables the channel. Setting this bit enables a channel, clearing this bit disables the channel.
The ChEnReg.CH_EN bit is automatically cleared by hardware to disable the channel after the last System Bus transfer of
the DMA transfer to the destination has completed.Software can therefore po ll this bit to determine when a DMA transfer
has completed.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
----CH_EN_WE
3CH_EN_WE
2CH_EN_WE
1CH_EN_WE
0
76543210
- - - - CH_EN3 CH_EN2 CH_EN1 CH_EN0
378
32072H–AVR32–10/2012
AT32UC3A3
19.12.24 DMACA Component Id Register Low
Name: DmaCompIdRegL
Access Type: Read-only
Offset: 0x3F8
Reset Value: 0x44571110
• DMA_COMP_TYPE
DesignWare component type number = 0x44571110.
This assigned unique hex value is constant and is derived from the two ASCII letters “DW” followed by a 32-bit unsigned
number
31 30 29 28 27 26 25 24
DMA_COMP_TYPE[31:24]
23 22 21 20 19 18 17 16
DMA_COMP_TYPE[23:16]
15 14 13 12 11 10 9 8
DMA_COMP_TYPE[15:8]
76543210
DMA_COMP_TYPE[7:0]
379
32072H–AVR32–10/2012
AT32UC3A3
19.12.25 DMACA Component Id Register High
Name: DmaCompIdRegH
Access Type: Read-only
Offset: 0x3FC
Reset Value: 0x3230362A
• DMA_COMP_VERSION: Version of the component
31 30 29 28 27 26 25 24
DMA_COMP_VERSION[31:24]
23 22 21 20 19 18 17 16
DMA_COMP_VERSION[23:16]
15 14 13 12 11 10 9 8
DMA_COMP_VERSION[15:8]
76543210
DMA_COMP_VERSION[7:0]
380
32072H–AVR32–10/2012
AT32UC3A3
19.13 Module Configuration
The following table de fines the valid settings for the DEST_PER and SRC_PER fields in the
CFGxH register. The direction is specified as observed f rom the DMACA. So for inst ance, AES -
RX means this hardware handshaking interface is connected to the input of the AES modulel
.
Table 19-6. DMACA Handshake Interfaces
PER Value Hardware Handshaking Interface
0 AES - RX
1 AES - TX
2 MCI - RX
3MCI -TX
4MSI - RX
5MSI - TX
6 DMACA - EXT0
7 DMACA - EXT1
Table 19-7. DMACA External Handshake Signals
Handshaking
Interface Function Signal Name
DMACA - EXT0 DMA Acknowledge (DMACK0) DMAACK[0]
DMA Request (nDMAREQ0) DMARQ[0]
DMACA - EXT1 DMA Acknowledge (DMACK1) DMAACK[1]
DMA Request (nDMAREQ1) DMARQ[1]
381
32072H–AVR32–10/2012
AT32UC3A3
20. General-Purpose Input/Output Controller (GPIO)
Rev: 1.1.0.4
20.1 Features Each I/O line of the GPIO features:
•Configurable pin-change, rising -edge or falling-edge interrupt on any I/O line
•A glitch filter providing rejection of pulses shorter than one clock cycle
•Input visibility and output control
•Multiplexing of up to four peripheral functions per I/O line
•Programmable internal pull-up resistor
20.2 Overview The General Purpose Input/Output Controller manages the I/O pins of the microcontroller. Each
I/O line may be dedicated as a general-purpo se I/O or be assigned to a f unction of an embed ded
peripheral. This assures effect ive optimization of the pins of a product.
20.3 Block Diagram
Figure 20-1. GPIO Block Diagram
20.4 Product Dependencies
In order to use t his modu le, othe r p arts o f th e syst em must be conf igu red cor re ctly, as de scr ibed
below.
Interrupt Controller
Power Manager
Embedded
Peripheral
General Purpose
Input/Output - GPIO
GPIO Interrupt Request
CLK_GPIO
Pin Control
Signals
PIN
PIN
PIN
PIN
PIN
MCU
I/O Pins
PB Configuration
Interface
382
32072H–AVR32–10/2012
AT32UC3A3
20.4.1 Module Configuration
Most of the features of the GPIO are configurable for ea ch product. The user must refe r to the
Package and Pinout chapter for these settings.
Product specific settings includes:
• Number of I/O pins.
• Functions implemente d on each pin
• Peripheral function(s) multiplexed on each I/O pin
• Reset value of registers
20.4.2 Clocks The clock for the GPIO bus interface (CLK_GPIO) is generated by the Power Manager. This
clock is enabled at reset, and can be disabled in the Power Manager.
The CLK_GPIO must b e e nabled in o rd er to access th e config ur ation re giste rs of t he GPI O or to
use the GPIO interr upts. Aft er con figuring t he GPI O, the CL K_GPIO can be disabled if interr upts
are not used.
20.4.3 Interrupts The GPIO interrupt lines are connected to the interrupt controller. Using the GPIO interrupt
requires the interrupt controller to be configured first.
20.5 Functional Description
The GPIO controls th e I/O lines of the microcont roller. The co ntrol lo gic associate d with each pin
is represente d in th e figu r e be l ow :
383
32072H–AVR32–10/2012
AT32UC3A3
Figure 20-2. Overview of the GPIO Pad Connections
20.5.1 Basi c Opera t ion
20.5.1.1 I/O Line or peripheral function selection
When a pin is multiplexed with one or more peripheral functions, the selection is controlled with
the GPIO Enable Register (GPER). If a bit in GPER is written to one, the corresponding pin is
controlled by the GPIO. If a bit is writ ten to zero, the correspo n din g p in is con tr olle d by a pe r i ph -
eral function.
20.5.1.2 P eripheral selection
The GPIO provides multiplexing of up to four peripheral functions on a single pin. The selection
is performed b y accessing Peripheral M ux Register 0 (PMR0) and Per ipheral Mux Register 1
(PMR1).
20.5.1.3 Output control
When the I/O line is assigned to a peripheral function, i.e. the corresponding bit in GPER is writ-
ten to zero, the drive of the I/O line is controlled by the peripheral. The peripheral, depending on
the value in PMR0 and PMR1, determines whether the pi n is driven or not.
When the I/O line is controlled by the GPIO, the value of the Output Driver Enable Register
(ODER) determines if the pin is driven or no t. When a bit in th is register is wri tten to one, the cor-
0
1
GPER
1
0
OVR
ODER
PMR1
Periph. A output enable
Periph. B output enable
Periph. C output enable
Periph. D output enable
Periph. A output data
Periph. B output data
Periph. C output data
Periph. D output data PAD
PUER
Periph. A input data
Periph. B input data
Periph. C input data
Periph. D input data
PVR
0
1
Glitch Filter
GFER
Edge Detector 1
0Interrupt Request
IMR1
PMR0
IMR0
IER
384
32072H–AVR32–10/2012
AT32UC3A3
responding I/O line is driven by the GPIO. When the bit is written to zero, the GPIO does not
drive the line.
The level driven on an I/O line can be deter mined by writing to t he Output Value Register (OVR).
20.5.1.4 Inputs The level on each I/O line can be read through the Pin Value Register (PVR). This register indi-
cates the level of the I/O lines regard less of whether the lines are driven by the GPIO or by a n
external component. Note that due to power saving measures, the PVR register can only be
read when GPER is written to on e for the corresponding pin or if interrupt is enabled for the pin.
20.5.1.5 Output line timings
The figure below shows th e timing of the I/O line when writing a one and a zero to OVR. The
same timing applies when performing a ‘set’ or ‘clear’ access, i.e., writing a one to the Output
Value Set Register (OVRS) or the Output Value Clear Register (OVRC). The timing of PVR is
also shown.
Figure 20-3. Output Line Timings
20.5.2 Advanced Operation
20.5.2.1 Pu ll-u p resist or con tro l
Each I/O line is design ed with a n embedd ed pull-u p resist or. The pull- up resist or can b e enabled
or disabled by writing a one or a zero to the corresponding bit in the Pull-up Enable Register
(PUER). Control of the pull-up resistor is possible whether an I/O line is controlled by a periph-
eral or the GPIO.
20.5.2.2 In pu t glit ch filter
Optional input glitch filte rs can be enabled on each I/O line. When the glit ch filter is enabled, a
glitch with duration of less than 1 clock cycle is automatically rejected, while a pulse with dura-
tion of 2 clock cycles or more is accep ted. For pulse durations be tween 1 clock cycle and 2 clock
cycles, the pulse may or may not be taken into account, depending on the precise timing of its
occurrence. Thus for a pulse to be guaran teed visible it must exceed 2 clock cycles, whereas for
a glitch to be reliably filtered out, its duration must not exceed 1 clock cycle. The filter introduces
2 clock cycles of latency.
The glitch filters are contr olled by the Glitch Filter Enable Register (GFE R). When a bit is written
to one in GFER , the glitch filt er on the corres pon ding pin is enable d. T he glitch filter affe cts on ly
interrupt in puts. Inputs to periphe rals or the value read thr ough PVR are not affe cted by the
glitch filters.
PB Access
PB Access
CLK_GPIO
Write OVR to 1
Write OVR to 0
OVR / I/O Line
PVR
385
32072H–AVR32–10/2012
AT32UC3A3
20.5.3 Interrupts The GPIO can be configured to generate an interrupt when it detects an input change on an I/O
line. The module can be configured to signal an interrupt whenever a pin changes value or only
to trigger on rising edges or falling edges. Interrupts are enabled on a pin by writing a one to the
corresponding bit in the Interrupt Enable Register (IER). The interrupt mode is set by writing to
the Interr upt Mode Register 0 (IMR0) and th e Interrupt Mode Registe r 1(IMR1). Int errupts ca n be
enabled on a pin, regardless of the conf iguration of th e I/O line, i.e. whether it is contr olled by the
GPIO or assigned to a peripheral function.
In every port there are four interrupt lines connected to the interrupt controller. Gro ups of eight
interrupts in the port are ORed together to form an interrupt line.
When an interrupt event is detected on an I/O line, and the corresponding bit in IER is written to
one, the GPIO interrupt request line is asserted. A number of interrup t signals are ORed-wired
together to generate a single interrupt signal to the interrupt controller.
The Interrupt Flag Register (IFR) can by read to determine which pin(s) caused the interrupt.
The interrupt bit must be cleared by writing a one to the Interrupt Flag Clear Register (IFRC). To
take effect, the clear operation must be performed when the interrupt line is enabled in IER. Oth-
erwise, it will be ignored.
GPIO interrupts can only be triggered when the CLK_GPIO is enabled.
20.5.4 Interrupt Timings
The figure belo w shows the timing for rising edge (or pin-change) interrupts when the glitch filter
is disabled. For the pulse to be registered, it must be sampled at the rising edge of the clock. In
this example, this is not the case for the first pulse. The second pulse is however sampled on a
rising edge and will trigger an interrupt request.
Figure 20-4. Interrupt Timin g With Glitch Filter Disab led
The figure belo w shows the timing for rising edge (or pin-change) interrupts when the glitch filter
is enabled. For the pulse to be registered, it must be sampled on two subsequent rising edges.
In the example, the first pulse is rejected while the second pulse is accepted and causes an
interrupt request.
Figure 20-5. Interrupt Timin g With Glitch Filter Enab led
clock
Pin Level
GPIO_IFR
clock
Pin Level
GPIO_IFR
386
32072H–AVR32–10/2012
AT32UC3A3
20.6 User Interface
The GPIO controls all the I/O pins on the AVR32 microcontroller. The pins are managed as 32-
bit ports that are configurable through a PB interface. Each port has a set of configuration regis-
ters. The overall memory map of the GPIO is shown below. The number of pins and hence the
number of ports are product specific.
Figure 20-6. Overall Mermory Map
In the GPIO Controller Function Multiplexingtable in the Package and Pinout chapter, each
GPIO line has a unique number. Note that the PA, PB, PC and PX ports do not directly corre-
spond to the GPIO ports. To find the corresponding port and pin the follo wing formula can be
used:
GPIO port = floor((GPIO number) / 32), example: floor((36)/ 32) = 1
GPIO pin = GPIO number mod 32, example: 36 mod 32 = 4
The table below shows the configuration registers for one port. Addresses shown are relative to
the port address offset. The specific address of a configuration register is found by adding the
Port 0 Configuration Registers
Port 1 Configuration Registers
Port 2 Configuration Registers
Port 3 Configuration Registers
Port 4 Configuration Registers
0x0000
0x0100
0x0200
0x0300
0x0400
387
32072H–AVR32–10/2012
AT32UC3A3
register offset and the port offset to the GPIO start address. One bit in each of the configuration
registers corre sponds to an I/O pin.
Table 20-1. GPIO Register Memory Map
Offset Register Function Name Access Reset value
0x00 GPIO Ena ble Register Read/Write GPER Read/Write ( 1)
0x04 GPIO Ena ble Register Set GPERS Write-Only
0x08 GPIO Ena ble Register Clear GPERC Write-Only
0x0C GPIO Enable Register Toggle GPERT Write-Only
0x10 Peripheral Mux Register 0 Read/Write PMR0 Read/Write (1)
0x14 Peripheral Mux Register 0 Set PMR0S Write-Only
0x18 Peripheral Mux Register 0 Clear PMR0C Write-Only
0x1C Peripheral Mux Register 0 Toggle PMR0T Write-Only
0x20 Peripheral Mux Register 1 Read/Write PMR1 Read/Write (1)
0x24 Peripheral Mux Register 1 Set PMR1S Write-Only
0x28 Peripheral Mux Register 1 Clear PMR1C Write-Only
0x2C P eripheral Mux Register 1 Toggle PMR1T Write-Only
0x40 Output Driver Enable Register Read/Write ODER Read/Write (1)
0x44 Output Driver Enable Register Set ODERS Write-Only
0x48 Output Driver Enable Register Clear ODERC Write-Only
0x4C Output Driver Enable Register Toggle ODERT Write-Only
0x50 Output Value Register Read/Write OVR Read/Write (1)
0x54 Output Value Register Set OVRS Write-Only
0x58 Output Value Register Clear OVRC Write-Only
0x5c Output Value Register Toggle OVRT Write-Only
0x60 Pin Value Register Read PVR Read-Only (2)
0x70 Pull-up Enable Register Read/Write PUER Read/Write (1)
0x74 Pull-up Enable Register Set PUERS Write-Only
0x78 Pull-up Enable Register Clear PUERC Write-Only
0x7C Pull-up Enable Register Toggle PUERT Write-Only
0x90 Interrupt Enable Register Read/Write IER Read/Write (1)
0x94 Interrupt Enable Register Set IERS Write-Only
0x98 Interrupt Enable Register Clear IERC Write-Only
0x9C Interrupt Enable Register Toggle IERT Write-Only
0xA0 Interrupt Mode Register 0 Read /Write IMR0 Read/Write (1)
0xA4 Interrupt Mode Register 0 Set IMR0S Write-Only
0xA8 Interrupt Mode Register 0 Clear IMR0C Write-Only
0xAC Interrupt Mode Register 0 Toggle IMR0T Write-Only
0xB0 Interrupt Mo de Register 1 Read/Write IMR1 Read/Write (1)
388
32072H–AVR32–10/2012
AT32UC3A3
1) The reset value for these registers are device specific. Please refer to the Module Config-
uration sectio n at the en d of this ch ap te r.
2) The reset value is undefined depending on the pin states.
20.6.1 Access Types Each configuration register can be accessed in four different ways. The first address location
can be used to write the register directly. This address can also be used to read the register
value. The following addresses facilitate three different types of write access to the register. Per-
forming a “set” access, all bits written to one will be set. Bits written to zero will be unchanged by
the operation. Performing a “clea r” access, all bits written to one will be cleared. Bits written to
zero will be unchanged by the operation. Finally, a toggle access will toggle the value of all bits
written to one. Ag ain all bits writ ten to zer o remain uncha nged. Note that for so me regist ers (e. g.
IFR), not all access methods are permitted.
Note that for ports with less than 32 bits, the corresponding control registers will have unused
bits. This is also the case for features that are not implemented for a specific pin. Writing to an
unused bit will have no effect. Reading unused bits will always return 0.
0xB4 Interrupt Mo de Register 1 Set IMR1S Write-Only
0xB8 Interrupt Mo de Register 1 Clear IMR1C Write-Only
0xBC Interrupt Mo de Register 1 Toggle IMR1T Write-Only
0xC0 Glitch Filter Enable Register Read/Write GFER Read/Write (1)
0xC4 Glitch Filter Enable Register Set GFERS Write-Only
0xC8 Glitch Filter Enable Register Clear GFERC Write-Only
0xCC Glitch Filter Enable Register Toggle GFERT Write-Only
0xD0 Interrupt Flag Registe r Read IFR Read-Only (1)
0xD4 Interrupt Flag Registe r - - -
0xD8 Interrupt Flag Registe r Clear IFRC Write-Only
0xDC Interrupt Flag Regi ster - - -
Table 20-1. GPIO Register Memory Map
Offset Register Function Name Access Reset value
389
32072H–AVR32–10/2012
AT32UC3A3
20.6.2 Enable Regi st er
Name: GPER
Access Type: Read, Write, Set, Clear, Toggle
Offset: 0x00, 0x04, 0x08, 0x0C
Reset Value: -
• P0-P31: Pin Enable
0: A peripheral function controls the corresponding pin.
1: The GPIO controls the corresponding pin.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
390
32072H–AVR32–10/2012
AT32UC3A3
20.6.3 Per ipheral Mux Register 0
Name: PMR0
Access Type: Read, Write, Set, Clear, Toggle
Offset: 0x10, 0x14, 0x18, 0x1C
Reset Value: -
• P0-31: Peripheral Multiplexer Select bit 0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
391
32072H–AVR32–10/2012
AT32UC3A3
20.6.4 Per ipheral Mux Register 1
Name: PMR1
Access Type: Read, Write, Set, Clear, Toggle
Offset: 0x20, 0x24, 0x28, 0x2C
Reset Value: -
• P0-31: Peripheral Multiplexer Select bit 1
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
{PMR1, PMR0} Selected Peripheral Function
00 A
01 B
10 C
11 D
392
32072H–AVR32–10/2012
AT32UC3A3
20.6.5 Output Driver Enable Reg ister
Name: ODER
Access Type: Read, Write, Set, Clear, Toggle
Offset: 0x40, 0x44, 0x48, 0x4C
Reset Value: -
• P0-31: Output Driver Enable
0: The output driver is disabled for the corresponding pin.
1: The output driver is enabled f o r the corresponding pin.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
393
32072H–AVR32–10/2012
AT32UC3A3
20.6.6 Output Value Register
Name: OVR
Access Type: Read, Write, Set, Clear, Toggle
Offset: 0x50, 0x54, 0x58, 0x5C
Reset Value: -
• P0-31: Output Value
0: The value to be driven on the I/O line is 0.
1: The value to be driven on the I/O line is 1.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
394
32072H–AVR32–10/2012
AT32UC3A3
20.6.7 Pin Value Register
Name: PVR
Access Type: Read
Offset: 0x60, 0x64, 0x68, 0x6C
Reset Value: -
• P0-31: Pin Value
0: The I/O line is at level ‘0’.
1: The I/O line is at level ‘1’.
Note that the level of a pin can only be read when GPER is set or interrupt is enabled for the pin.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
395
32072H–AVR32–10/2012
AT32UC3A3
20.6.8 Pull-up Enable Regi st er
Name: PUER
Access Type: Read, Write, Set, Clear, Toggle
Offset: 0x70, 0x74, 0x78, 0x7C
Reset Value: -
• P0-31: Pull-up Enable
0: The internal pull-up resistor is disabled for the corresponding pin.
1: The internal pull-up resistor is enabled for the corresponding pin.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
396
32072H–AVR32–10/2012
AT32UC3A3
20.6.9 Interrupt Enable Register
Name: IER
Access Type: Read, Write, Set, Clear, Toggle
Offset: 0x90, 0x94, 0x98, 0x9C
Reset Value: -
• P0-31: Interrupt Enable
0: Interrupt is disabled for the correspond ing pin.
1: Interrupt is enabled for the corre s ponding pin.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
397
32072H–AVR32–10/2012
AT32UC3A3
20.6.10 Interrupt Mode Register 0
Name: IMR0
Access Type: Read, Write, Set, Clear, Toggle
Offset: 0xA0, 0xA4, 0xA8, 0xAC
Reset Value: -
• P0-31: Interrupt Mode Bit 0
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
398
32072H–AVR32–10/2012
AT32UC3A3
20.6.11 Interrupt Mode Register 1
Name: IMR1
Access Type: Read, Write, Set, Clear, Toggle
Offset: 0xB0, 0xB4, 0xB8, 0xBC
Reset Value: -
• P0-31: Interrupt Mode Bit 1
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
{IMR1, IMR0} Interrupt Mode
00 Pin Change
01 Rising Edge
10 Falling Edge
11 Reserved
399
32072H–AVR32–10/2012
AT32UC3A3
20.6.12 Glitch Filter Enable Register
Name: GFER
Access Type: Read, Write, Set, Clear, Toggle
Offset: 0xC0, 0xC4, 0xC8, 0xCC
Reset Value: -
• P0-31: Glitch Filter Enable
0: Glitch filter is disabled for the corresponding pin.
1: Glitch filter is enabled for the corresponding pin.
NOTE! The value of this register should only be changed when IER is ‘0’. Updating this GFER while interrupt on the
corresponding pin is enabled can cause an unintentional interrupt to be triggered.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
400
32072H–AVR32–10/2012
AT32UC3A3
20.6.13 Interrupt Flag Register
Name: IFR
Access Type: Read, Clear
Offset: 0xD0, 0xD8
Reset Value: -
• P0-31: Interrupt Flag
1: An interrupt condition has been detected on the corresponding pin.
0: No interrupt cond ition has beedn detected on the co rresponding pin since reset or the last time it was cleared.
The number of interrupt request lines is dependant on the number of I/O pins on the MCU. Ref er to the product specific data for
details. Note also that a bit in the Interrupt Flag register is only valid if the corresponding bit in IER is set.
31 30 29 28 27 26 25 24
P31 P30 P29 P28 P27 P26 P25 P24
23 22 21 20 19 18 17 16
P23 P22 P21 P20 P19 P18 P17 P16
15 14 13 12 11 10 9 8
P15 P14 P13 P12 P11 P10 P9 P8
76543210
P7 P6 P5 P4 P3 P2 P1 P0
401
32072H–AVR32–10/2012
AT32UC3A3
20.7 Programming Examples
20.7.1 8-bit LED-Chaser
// Set R0 to GPIO base address
mov R0, LO(AVR32_GPIO_ADDRESS)
orh R0, HI(AVR32_GPIO_ADDRESS)
// Enable GPIO control of pin 0-8
mov R1, 0xFF
st.w R0[AVR32_GPIO_GPERS], R1
// Set initial value of port
mov R2, 0x01
st.w R0[AVR32_GPIO_OVRS], R2
// Set up toggle value. Two pins are toggled
// in each round. The bit that is currently set,
// and the next bit to be set.
mov R2, 0x0303
orh R2, 0x0303
loop:
// Only change 8 LSB
mov R3, 0x00FF
and R3, R2
st.w R0[AVR32_GPIO_OVRT], R3
rol R2
rcall delay
rjmp loop
It is assumed in this example that a subroutine "delay" exists that returns after a given time.
20.7.2 Configuration of USART pins
The example below shows how to configure a peripheral module to control I/O pins. It assumed
in this example that the USART receive pin (RXD) is connected to PC16 and that the USART
transmit pin (TXD) is con nected to PC17. For both pins, the USART is peripheral B. In this
example, the state of the GPIO registers is assumed to be unknown. T he two USART pins are
therefore first se t to be cont rolled by the GPIO with output dr ivers disable d. The pi ns can then be
assured to be tri-stated while changing the Peripheral Mux Registers.
// Set up pointer to GPIO, PORTC
mov R0, LO(AVR32_GPIO_ADDRESS + PORTC_OFFSET)
orh R0, HI(AVR32_GPIO_ADDRESS + PORTC_OFFSET)
// Disable output drivers
402
32072H–AVR32–10/2012
AT32UC3A3
mov R1, 0x0000
orh R1, 0x0003
st.w R0[AVR32_GPIO_ODERC], R1
// Make the GPIO control the pins
st.w R0[AVR32_GPIO_GPERS], R1
// Select peripheral B on PC16-PC17
st.w R0[AVR32_GPIO_PMR0S], R1
st.w R0[AVR32_GPIO_PMR1C], R1
// Enable peripheral control
st.w R0[AVR32_GPIO_GPERC], R1
403
32072H–AVR32–10/2012
AT32UC3A3
20.8 Module configuration
The specific configuration for each GPIO instance is liste d in the following tables.The module
bus clocks listed here are connected to the system bus clocks according to the table in the Sys-
tem Bus Clock Connections section.
The reset values for all GPIO registers are zero with the following exceptions:
Table 20-2. Module configuration
Feature GPIO
Number of GPIO p orts 4
Number of peripheral functions 4
Table 20-3. Module clock name
Module name Clock name
GPIO CLK_GPIO
Table 20-4. Register Reset Values
Por t Register Reset Value
0 GPER 0xFFFFFFFF
0 GFER 0xFFFFFFFF
1 GPER 0xFFFFFFFF
1 GFER 0xFFFFFFFF
2 GPER 0xFFFFFFFF
2 GFER 0xFFFFFFFF
3 GPER 0x00007FFF
3 GFER 0x00007FFF
404
32072H–AVR32–10/2012
AT32UC3A3
21. Serial Peripheral Interface (SPI)
Rev: 2.1.0.3
21.1 Features •Compatible with an embedded 32-bit microcontroller
•Supports communication with serial external devices
– Four chip selects with external decoder support allow communication with up to 15
peripherals
– Serial memories, such as DataFlash and 3-wire EEPROMs
– Serial peripherals, such as ADCs, DACs, LCD controllers, CAN controllers and Sensors
– External co-processors
•Master or Slave Serial Peripheral Bus Interface
– 4 - to 16-bit programmable data length per chip select
– Programmable phase and polarity per chip select
– Programmable transfer delays between consecutive transfers and between clock and data
per chip select
– Programmable delay between consecutive transfers
– Selectable mode fault detection
•Connection to Peripheral DMA Controller channel capabilities optimizes data transfers
– One channel for the receiver, one channel for the transmitter
– Next buffer support
– Four character FIFO in reception
21.2 Overview The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides com-
munication with external devices in Master or Slave mode. It also enables communication
between processors if an external processor is connected to the system.
The Serial Peripheral Interface is essentially a shift regi ster that serially transmits data bits to
other SPIs. During a data transfer, one SPI system acts as the “master”' which controls the data
flow, while the other devices act as “slaves'' which have data shifted into and out by the master.
Different CPUs can take turn being masters (Multiple Master Protocol opposite to Single Master
Protocol where one CPU is always the master while all of the others are always slaves) and one
master may simu ltaneo usly shift data into multiple slaves. However, only one slave may drive its
output to write data back to the master at any given time.
A slave device is selected when the master asserts its NSS signal. If multiple slave devices
exist, the master generates a separate slave select signal for each slave (NPCS).
The SPI system consists of two data lines and two control lines:
• Master Out Slave In (MOSI): this data line supplies the output data from the master shifted
into the input(s) of the slave(s).
• Master In Slave Out (MISO): this data line supplies the output data from a slav e to the input of
the master. There may be no more than one slave transmitting data dur in g any particular
transfer.
• Serial Clock (SPCK): this control line is driven by the master and regulates the flow of the
data bits . The master may transmit data at a v ariety of baud rates; the SPCK line cycles once
for each bit that is transmitted.
• Slave Select (NSS): this control line allows slaves to be turned on and off by hardware.
405
32072H–AVR32–10/2012
AT32UC3A3
21.3 Block Diagram
Figure 21-1. SPI Block Diagram
21.4 Application Block Diagram
Figure 21-2. Application Block Diagram: Single Master/Multiple Slave Implementation
Spi Interface
Interrupt Control
Peripheral DMA
Controller
I/O
Controller
CLK_SPI
Peripheral Bus
SPI Interrupt
SPCK
NPCS3
NPCS2
NPCS1
NPCS0/NSS
MOSI
MISO
Slave 0
Slave 2
Slave 1
SPCK
NPCS3
NPCS2
NPCS1
NPCS0
MOSI
MISO
Spi Master
SPCK
NSS
MOSI
MISO
SPCK
NSS
MOSI
MISO
SPCK
NSS
MOSI
MISO
NC
406
32072H–AVR32–10/2012
AT32UC3A3
21.5 I/O Lines Description
21.6 Product Dependencies
In order to use t his modu le, othe r p arts o f th e syst em must be conf igu red cor re ctly, as de scr ibed
below.
21.6.1 I/O Lines The pins used for interfacing the compliant external de vices may be multiplexed with I/O lines.
The user must first configure the I/O Controller to assign the SPI pins to their peripheral
functions.
21.6.2 Clocks The clock for the SPI bus interf ace (CLK_ SPI) is gen erat ed by th e Powe r M ana ger. Thi s clock is
enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the
SPI before disabling the clock, to avoid freezing the SPI in an undefined state.
21.6.3 Interrupts The SPI interrupt request line is connected to the interrupt controller. Using the SPI interrupt
requires the interrupt controller to be programmed first.
21.7 Functional Description
21.7.1 Modes of Operation
The SPI operates in master mode or in slave mode.
Operation in master mode is configured by writing a one to the Master/Slave Mode bit in the
Mode Register (MR. MSTR). The pins NPCS0 to NPCS3 are a ll configured as outputs, the SPCK
pin is driven, the MISO line is wired on the receiver input and the MOSI line driven as an output
by the transmitter.
If the MR.MSTR bit is written to zero, the SPI operates in slave mode. The MISO line is driven by
the transmitter outp ut, the MOSI line is wired on the r eceiver input, the SPCK pin is driven by the
transmitter to synchronize the receiver. The NPCS0 pin becom es an input, and is used as a
Slave Select signal (NSS). The pins NPCS1 to NPCS3 are not driven and can be used for other
purposes.
The data transfers are iden tically programmable for both mod es of operations. The baud rate
generator is a ctivated only in master mode.
Table 21-1. I/O Lines Descrip tion
Pin Name Pin Description
Type
Master Slave
MISO Master In Slave Out Input Output
MOSI Master Out Slave In Output Input
SPCK Serial Clock Output Inp ut
NPCS1-NPCS3 Peripheral Chip Selects Output Unused
NPCS0/NSS P eripheral Chip Select/Slave Select Output Input
407
32072H–AVR32–10/2012
AT32UC3A3
21.7.2 Data Transfer Four combination s of polarity and phase are availa ble for data transfers. The clock polarity is
configured with the Clock Polarity bit in the Chip Select Registers (CSRn.CPOL). The clock
phase is configured with the Clock Phase bit in the CSRn registers (CSRn.NCPHA). These two
bits determine the edges of the clock signal on which data is driven and sampled. Each of the
two bits has two possible states, resultin g in four possible combinations that are incompatible
with one another. Thus, a master/slave pair must use the same parameter pair values to com-
municate. If multiple slaves are used and fixed in different configurations, the master must
reconfigure itself each time it needs to communicate with a different slave.
Table 21-2 on page 407 shows the four modes and corresponding parameter settings.
Figure 21-3 on page 407 and Figure 21-4 on page 408 show examples of data transfers.
Figure 21-3. SPI Transfer Format (NCPHA = 1, 8 bits per transfer)
Table 21-2. SPI modes
SPI Mode CPOL NCPHA
001
100
211
310
143
25876
SPCK cycle (for reference)
SPCK
(CPOL = 0)
NSS
(to slave)
MISO
(from slave)
MOSI
(from master)
SPCK
(CPOL = 1)
MSB 6 45LSB123
MSB 6 ***LSB12345
*** Not Defined, but normaly MSB of previous character received
408
32072H–AVR32–10/2012
AT32UC3A3
Figure 21-4. SPI Transfer Format (NCPHA = 0, 8 bits per transfer)
21.7.3 Master Mode Operations
When configured in master mode, the SPI uses the internal programmable baud rate generator
as clock source. It fully controls the data transfers to and from the slave(s) connected to the SPI
bus. The SPI drives the ch ip select line to the slave and the seria l clock signa l (SPCK) .
The SPI features two holding registers, the Transmit Data Register (T DR) and the Receive Data
Register (RDR), and a single Shift Register. The holding registers maintain the data flow at a
constant rate.
After enabling the SPI, a data transfer begins when the processor writes to the TDR register.
The written data is immediately transferred in the Shift Register and transfer on the SPI bus
starts. While the data in the Shift Register is shifted on the MOSI line, the MISO line is sampled
and shifted in the Shift Register. Transmission cannot occur withou t reception.
Before writing to the TDR, the Peripheral Chip Select field in TDR (TDR.PCS) must be written in
order to select a slave.
If new data is written to TDR during the transfer, it stays in it until the current transfer is com-
pleted. Then, the received data is transferred from the Shift Register to RDR, the data in TDR is
loaded in the Shift Register and a new transfer starts.
The transfer of a data wr itt en in TDR in t he Sh if t Reg ist er is indica te d by the T ra nsmit Da ta Re g-
ister Empty bit in the Status Register (SR.TDRE). When new data is written in TDR, this bit is
cleared. The SR.TDRE bit is used to trigger the Transmit Peripheral DMA Controller channel.
The end of transfer is indicated by the Transmission Registers Empty bit in the SR register
(SR.TXEMPTY). If a tran sfer delay (CSRn.DLYBCT) is greater than zero fo r the last transfer,
SR.TXEMPTY is set after the complet ion of said delay. Th e CL K_SPI can be switch ed off at this
time.
During reception, re ceived data are transferred from the Shift Re gister to the reception FIFO.
The FIFO can contain up to 4 characters (both Receive Data and Peripheral Chip Select fields).
While a character of the FIFO is unread, the Receive Data Register Full bit in SR remains high
(SR.RDRF). Characters are read through the RDR register. If the four characters stored in the
FIFO are not read and if a new character is stored, this sets the Overrun Error Status bit in the
SR register (SR.OVRES). The procedure to follow in such a case is described in Section
21.7.3.8.
143
25876
SPCK cycle (for reference)
SPCK
(CPOL = 0)
NSS
(to slave)
MISO
(from slave)
MOSI
(from master)
SPCK
(CPOL = 1)
MSB 6 45LSB123
6LSB12345
*** Not Defined, but normaly LSB of previous character transmitted
MSB***
409
32072H–AVR32–10/2012
AT32UC3A3
In master mode, if the receive d data is not read fast enough compare d to the transfer rhythm
imposed by the write accesses in the TDR, some overrun errors may occur, even if the FIFO is
enabled. To insure a perfect data integrity of received data (especially at high data rate), the
mode Wait Data Read Before Transfer can be enabled in the MR register (MR.WDRBT). When
this mode is activated, no transfer starts while received data remains unread in the RDR. When
data is written to the TDR and if unread received data is stored in the RDR, the transfer is
paused until the RDR is read. In this mode no overrun error can occur. Please note that if this
mode is enabled, it is useless to activate the FIFO in re ception.
Figure 21-5 on page 409shows a block diagram o f the SPI when oper ating in master mod e. Fig-
ure 21-6 on page 410 shows a flow chart describing how transfers are handle d.
21.7.3.1 Master mode block diagram
Figure 21-5. Master Mode Block Diagram
Baud Rate Generator
RXFIFOEN
4 – Character FIFO
Shift Register
TDRE
RXFIFOEN
4 – Character FIFO
PS
PCSDEC
Current
Peripheral
MODF
MODFDIS
MSTR
SCBR
CSR0..3
CSR0..3
CPOL
NCPHA
BITS
RDR
RD
RDRF
OVRES
TD
TDR
RDR
CSAAT
CSNAAT
CSR0..3
PCS
MR
PCS
TDR
SPCK
CLK_SPI
MISO MOSI
MSBLSB
NPCS1
NPCS2
NPCS3
NPCS0
SPI
Clock
0
1
0
1
0
1
NPCS0
410
32072H–AVR32–10/2012
AT32UC3A3
21.7.3.2 Master mode flow diagram
Figure 21-6. Master Mode Flow Diagram
SPI Enable
CSAAT ?
PS ?
1
0
0
1
1
NPCS = TDR(PCS) NPCS = MR(PCS)
Delay DLYBS
Serializer = TDR(TD)
TDRE = 1
Data Transfer
RDR(RD) = Serializer
RDRF = 1
TDRE ?
NPCS = 0xF
Delay DLYBCS
Fixed
peripheral
Variable
peripheral
Delay DLYBCT
0
1CSAAT ?
0
TDRE ? 1
0
PS ? 0
1
TDR(PCS)
= NPCS ?
no
yes MR(PCS)
= NPCS ?
no
NPCS = 0xF
Delay DLYBCS
NPCS = TDR(PCS)
NPCS = 0xF
Delay DLYBCS
NPCS = MR(PCS),
TDR(PCS)
Fixed
peripheral
Variable
peripheral
- NPCS defines the current Chip Select
- CSAAT, DLYBS, DLYBCT refer to the fields of the
Chip Select Register corresponding to the Current Chip Select
- When NPCS is 0xF, CSAAT is 0.
411
32072H–AVR32–10/2012
AT32UC3A3
21.7.3.3 Clock generation
The SPI Baud rate clock is generated by dividing the CLK_SPI , by a value between 1 and 255.
This allows a maximum operating baud rate at up to CLK_SPI and a minimum operating baud
rate of CLK_SPI divided by 255.
Writing the Serial Clock Baud Rate field in the CSRn registers (CSRn.SCBR) to zero is forbid-
den. Triggering a transfer while CSRn.SCBR is zero can lead to unpredictable results.
At reset, CSRn.SCBR is zero and the user has to configure it at a valid value before performing
the first transfer.
The divisor can be defined independently for each chip select, as it has to be configured in the
CSRn.SCBR field. This allows the SPI to automatically adapt the baud rate for each interfaced
peripheral without reprogramming.
21.7.3.4 Transfer delays
Figure 21-7 on page 411 shows a chip select transfer change and consecutive transfers on the
same chip select. Three delays can be configured to modify the transfer waveforms:
• The delay betw een chip selects , progr ammab le on ly once for all the chip selects by writing to
the Delay Between Chip Selects field in the MR register (M R.DLYBCS). Allows insertion of a
delay between release of one chip select and before assertion of a new one.
• The delay before SPCK, independently programmable for each chip select by writing the
Delay Before SPCK field in the CSRn registers (CSRn.DLYBS). Allows the start of SPCK to
be delayed after the chip select has been asserted.
• The delay between consecutive transfers, independent ly programmable f or each chip select
by writing the Delay Between Consecutive Transfers field in the CSRn regi sters
(CSRn.DLYBCT). Allows inser tion of a delay betw een two transfers occurring on the same
chip select
These delays allow the SPI to be adapted to the interfaced peripherals and their speed and bus
release time.
Figure 21-7. Programmab le Dela ys
DLYBCS DLYBS DLYBCT DLYBCT
Chip Select 1
Chip Select 2
SPCK
412
32072H–AVR32–10/2012
AT32UC3A3
21.7.3.5 P eripheral selection
The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By
default, all the NPCS signals ar e high before and after each transfer.
The peripheral selection can be performed in two different ways:
• Fixed Peripheral Select: SPI exchanges data with only on e peripheral
• Variable Peripheral Select: Data can be exchanged with more than one peripheral
Fixed Peripheral Select is activated by writing a zero to the Peripheral Select bit in MR (MR.PS).
In this case, the current periphe ral is defined by t he MR.PCS field an d the TDR.PCS field ha s no
effect.
Variable Peripher al Select is activated by wr iting a one to the MR.PS bit . The TD R.PCS field is
used to select the curr ent p eriphe ral. This mean s that th e perip heral select ion can be define d for
each new data.
The Fixed Peripher al Selectio n allows b uffer tr ansfer s with a sing le periphe ral. Using the Periph-
eral DMA Controller is an optimal means, as the size of the data transfer between the memory
and the SPI is either 4 bits or 16 bits. However, changing the peripheral selection requires the
Mode Register to be reprogrammed.
The Variable Peripheral Selection allows buffer transfers with multiple peripherals without repro-
gramming the MR register. Data written to TDR is 32-bits wide and defines the real data to be
transmitted and the peripheral it is destined t o. Using the Peri pheral DMA Contr oller in this m ode
requires 32-bit wide buffers, with the data in the LSBs and the PCS and LASTXFER fields in the
MSBs, however the SPI still controls the number of bits (8 to16) to be transferred through MISO
and MOSI lines with the CSRn registers. T his is not the optimal means in term of memory size
for the buffers, but it provides a very effective means to exchange data with several peripherals
without any inte rvention of the processor.
21.7.3.6 P eripheral chip select decoding
The user can configur e the SPI to operate with up to 15 periphera ls by decoding the four Chip
Select lines, NPCS0 to NPCS3 with an external logic. This can be enabled by writing a one to
the Chip Select Decode bit in the MR register (MR.PCSDEC).
When operating without decoding, the SPI makes sure that in any case only one chip select line
is activated, i.e. driven low at a time. If two bits are defined low in a PCS field, only the lowest
numbered chip select is driven low.
When operating with decoding, the SPI directly outputs the value defined by the PCS field of
either the MR register or the TDR register (depending on PS).
As the SPI sets a default value of 0xF on the chip select lines (i.e. all chip select lines at one)
when not processing any transfer, only 15 peripherals can be decoded.
The SPI has only four Chip Select Registers, not 15. As a result, when decoding is activated,
each chip select defines the characteristics of up to four peripherals. As an example, the CRS0
register defines the char acteristics of th e externally decoded peripherals 0 to 3, corresponding to
the PCS values 0x0 to 0x3. Thus, the user has to make sure to connect compatible peripherals
on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14.
21.7.3.7 P e ripheral deselection
When operating normally, as soo n as the transfer of the last data written in TDR is completed,
the NPCS lines all rise. This might lead to runt ime error if the pr ocessor is too long in responding
413
32072H–AVR32–10/2012
AT32UC3A3
to an interrupt, a nd thus might lead to difficultie s for interfacing with some seri al peripherals
requiring the chip select line to remain active during a full set of transfers.
To facilitate interfacing with such devices, the CSRn registers can be configured with the Chip
Select Active After Transfer bit written to one (CSRn.CSAAT) . This allows the chip select lines
to remain in their current state (low = active) until transfer to another peripheral is required.
When the CSRn.CSAAT bit is written to qero, the NPCS does not rise in all cases between two
transfers on the same peripheral. During a transfer on a Chip Select, the SR.TDRE bit rises as
soon as the content of the T DR is transferred into the internal shifter. Whe n this bit is detected
the TDR can be reloaded. If this reload occurs before the end o f the current transfer and if the
next transfer is performed on the same chip select as the current transfer, the Chip Select is not
de-asserted between the two transfers. This might lead to difficulties for interfacing with some
serial peripherals requiring the chip select to be de-asserted after each transfer. To facilitate
interfacing with such devices, the CSRn registers can be configured with the Chip Select Not
Active After Tr an sf er b it (CSRn.CSNAAT) written to one. This allows to de-assert sys tematically
the chip select lines during a time DLYBCS. (The value of the CSRn.CSNAAT bit is taken into
account only if the CSRn.CSAAT bit is written to zero for the same Chip Select).
Figure 21-8 on page 414 sh ows different peripheral deselection cases and the e ffect of the
CSRn.CSAAT and CSRn.CSNAAT bits.
21.7.3.8 FIFO management
A FIFO has been imple mented in Reception FIFO ( both in master and in slave mo de), in order to
be able to store up to 4 characters without causing an overrun error. If an attempt is made to
store a fifth ch ar acter, an over r un err or rises. I f such an e vent occurs, the FIFO mu st b e fl ushed.
There are two ways to Flush the FIFO:
• By performing four read accesses of the RDR (the data read must be ignored)
• By writing a one to the Flush Fifo Command bit in the CR register (CR.FLUSHFIFO).
After that, the SPI is able to receive new data.
414
32072H–AVR32–10/2012
AT32UC3A3
Figure 21-8. Peripheral Deselection
Figure 21-8 on page 414 sh ows different peripheral deselection cases and the e ffect of the
CSRn.CSAAT and CSRn.CSNAAT bits.
21.7.3.9 Mode fault detection
The SPI is capable of detecting a mode fault when it is configured in master mode and NPCS0,
MOSI, MISO, and SPCK are configured as open drain through the I/O Controller with either
internal or external pullup resistors. If the I/O Controller does not have open-drain capability,
mode fault det ection must be disabled by writ ing a one to the Mo de Fault Detection bit in the MR
A
NPCS[0..3]
Write TDR
TDRE
NPCS[0..3]
Write TDR
TDRE
NPCS[0..3]
Write TDR
TDRE
DLYBCS
PCS = A
DLYBCS
DLYBCT
A
PCS = B
B
DLYBCS
PCS = A
DLYBCS
DLYBCT
A
PCS = B
B
DLYBCS
DLYBCT
PCS=A
ADLYBCS
DLYBCT
A
PCS = A
AA
DLYBCT
AA
CSAAT = 0 and CSNAAT = 0
DLYBCT
AA
CSAAT = 1 and CSNAAT= 0 / 1
A
DLYBCS
PCS = A
DLYBCT
AA
CSAAT = 0 and CSNAAT = 1
NPCS[0..3]
Write TDR
TDRE
PCS = A
DLYBCT
AA
CSAAT = 0 and CSNAAT = 0
415
32072H–AVR32–10/2012
AT32UC3A3
register (MR.MODFDIS). In systems with open-drain I/O lines, a mode fault is detected when a
low level is driven by an external master on the NPCS0/NSS signal.
When a mode fault is de tect ed, th e Mode Fault Err or bit in the SR (S R.MODF) is set until the SR
is read and the SPI is automatically disabled until re-enabled by writing a one to the SPI Enable
bit in the CR register (CR.SPIEN).
By default, the mode fault detection circuitry is enabled. The user can disable mode fault detec-
tion by writing a one to the Mod e F au lt Det e ction bit in the MR register (MR.MODFDIS).
21.7.4 SPI Slave Mode
When operating in slave m ode, the SPI processes data bits on the clock pro vided on the SPI
clock pin (SPCK).
The SPI waits for NSS to go active before receiving the serial clock from an external master.
When NSS falls, the clock is validated on the serializer, which processes the number of bits
defined by th e Bits Per Tran sfer field of the Chip Se lect Re gister 0 (CSR0 .BITS) . The se bit s are
processed following a phase and a polarity defined respectively by the CSR0.NCPHA and
CSR0.CPOL bits. Note that t he BITS, CPOL, and NCPHA bits of the other Chip Select Registers
have no effect when the SPI is configured in Slave Mode.
The bits are shifted ou t on the MISO line and sampled on the MOSI line.
When all the bits are processed, the received data is transferred in the Receive Data Register
and the SR.RDRF bit rises. If the RDR register has not been read before new data is received,
the SR.OVRES bit is set. Data is loaded in RDR even if this flag is set. The user has to read the
SR register to clear the SR.OVRES bit.
When a transfer starts, the data shifted out is the data present in the Shift Register. If no data
has been written in the TDR register, the last data received is transferred. If no data has been
received since the last reset, all bits are transmitted low, as the Shift Register resets to zero.
When a first data is written in TDR, it is transferred immediately in the Shift Register and the
SR.TDRE bit rises. If new data is written, it remains in TDR until a transfer occurs, i.e. NSS falls
and there is a valid clock on the SPCK pin. When the transfer occurs, the last data written in
TDR is transferred in the Shift Register and the SR.TDRE bit rises. This enables frequent
updates of critical variables with single transfers.
Then, a new data is loaded in the Shift Register from the TDR. In case no character is ready to
be transmitted, i.e. no character has been written in TDR since the last load from TDR to the
Shift Register, the Shift Register is not modified and the last received character is retransmitted.
In this case the Underrun Erro r Sta tu s bit is set in SR (SR.U NDES).
Figure 21-9 on page 416 shows a block diagram of the SPI whe n operating in slave mode.
416
32072H–AVR32–10/2012
AT32UC3A3
Figure 21-9. Slave Mode Functional Block Diagram
Shift Register
SPCK
SPIENS
LSB MSB
NSS
MOSI
SPI
Clock
TDRE
TDR TD
RDRF
OVRES
CSR0
CPOL
NCPHA
BITS
SPIEN
SPIDIS
MISO
UNDES
RDR RD
4 - Character FIFO
0
1
RXFIFOEN
417
32072H–AVR32–10/2012
AT32UC3A3
21.8 User Interface
Note: 1. The reset values are device specific. Please refer to the Module Config uration section at the end of this chapter.
Table 21-3. SPI Register Memory Map
Offset Register Register Name Access Reset
0x00 Control Register CR Write-only 0x00000000
0x04 Mode Register MR Read/Write 0x00000000
0x08 Receive Data Register RDR Read-only 0x00000000
0x0C Transmit Data Register TDR Write-only 0x00000000
0x10 Status Register SR Read-only 0x00000 000
0x14 Interrupt Enable Register IER Write-only 0x00000000
0x18 Interrupt Disable Register IDR Write-only 0x00000000
0x1C Interrupt Mask Register IMR Read-only 0x00000000
0x30 Chip Select Register 0 CSR0 Read/Write 0x00000000
0x34 Chip Select Register 1 CSR1 Read/Write 0x00000000
0x38 Chip Select Register 2 CSR2 Read/Write 0x00000000
0x3C Chip Select Register 3 CSR3 Read/Write 0x00000000
0x E4 Write Protection Control Register WPCR Read/Write 0X00000000
0xE8 Write Protection Status Register WPSR Read-only 0x00000000
0xFC Version Register VERSION Read-only - (1)
418
32072H–AVR32–10/2012
AT32UC3A3
21.8.1 Control Register
Name: CR
Access Type: Write-only
Offset: 0x00
Reset Value: 0x00000000
• LASTXFER: Last Transfer
1: The current NPCS will be deasserted after the character written in TD has been transferred. When CSRn.CSAAT is one, this
allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD
transfer has completed.
0: Writing a ze ro to this bi t ha s no ef fect.
• FLUSHFIFO: Flush Fifo Command
1: If The FIFO Mode is enabled (MR.FIFOEN written to one) and if an overrun error has been detected, this command allows to
empty the FIFO.
0: Writing a ze ro to this bi t ha s no ef fect.
• SWRST: SPI Software Reset
1: Writing a one to this bit will reset the SPI. A software-triggered hardware reset of the SPI interface is performed. The SPI is in
slave mode after software reset. Peripheral DMA Controller channels are not affected by software reset.
0: Writing a ze ro to this bi t ha s no ef fect.
• SPIDIS: SPI Disable
1: Writing a one to this bit will disable the SPI. As soon as SPIDIS is written to one, the SPI finishes its transfer, all pins are set
in input mode and no data is received or transmitted. If a transfer is in prog ress, the transfer is finished before the SPI is
disabled. If both SPIEN and SPIDIS are equal to one when the CR register is written, the SPI is disabled.
0: Writing a ze ro to this bi t ha s no ef fect.
• SPIEN: SPI Enable
1: Writing a one to this bi t will enable the SPI to transfer and receive data.
0: Writing a ze ro to this bi t ha s no ef fect.
31 30 29 28 27 26 25 24
-------LASTXFER
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
-------FLUSHFIFO
76543210
SWRST - - - - - SPIDIS SPIEN
419
32072H–AVR32–10/2012
AT32UC3A3
21.8.2 Mode Register
Name: MR
Access Type: Read/Write
Offset: 0x04
Reset Value: 0x00000000
• DLYBCS: Delay Between Chip Selects
This field defines the delay from NPCS inactive to the activation of another NPCS. The DLYBCS time guarantees non-
over lapping chip selects and solves bus contentions in case of peripherals having long data float times.
If DLYBCS is less than or equal to six, six CLK_SPI periods will be inserted by default.
Otherwise, the following equation determines the delay:
• PCS: Peripheral Chip Select
This field is only used if Fixed Peripheral Select is active (PS = 0).
If PCSDEC = 0:
PCS = xxx0NPCS[3:0] = 1110
PCS = xx01NPCS[3:0] = 1101
PCS = x011NPCS[3:0] = 1011
PCS = 0111NPCS[3:0] = 0111
PCS = 1111forbidden (no peripheral is selected)
(x = don’t care)
If PCSDEC = 1:
NPCS[3:0] output signals = PCS.
• LLB: Local Loopback Enable
1: Local loopback path enabled. LLB controls the local loopback on the data serializer for testing in master mode only (MISO is
inter nally connected on MOSI).
0: Local loopback path disabled.
• RXFIFOEN: FIFO in Reception Enable
1: The FIFO is used in reception (four characters can be stored in the SPI).
31 30 29 28 27 26 25 24
DLYBCS
23 22 21 20 19 18 17 16
---- PCS
15 14 13 12 11 10 9 8
--------
76543210
LLB RXFIFOEN WDRBT- MODFDIS - PCSDEC PS MSTR
Delay Between Chip Selects DLYBCS
CLKSPI
-----------------------=
420
32072H–AVR32–10/2012
AT32UC3A3
0: The FIFO is not used in reception (only one character can be stored in the SPI).
• WDRBT: Wait Data Read Before Transfer
1: In master mode, a transfer ca n start only if the RDR register is empty, i.e. does not contain any unread data. This mode
prevents overrun error in reception.
0: No Effect. In master mode, a transfer can be initiated whatever the state of th e RDR register is.
• MODFDIS: Mode Fault Detection
1: Mode fault detection is disabled. If the I/O controller does not have open-drain capability, mode fault detection must be
disabled for proper operation of the SPI.
0: Mode fault detection is enabled.
• PCSDEC: Chip Select Decode
0: The chip selects are directly connected to a peripheral device.
1: The four chip select lines are connected to a 4- to 16-bit decoder.
When PCSDEC equals one, up to 15 Chip Select signals can be generated with the four lines using an external 4- to 16-bit
decoder. The CSRn registers define the characteristics of the 15 chip sele cts according to the following rules:
CSR0 defines per ipheral chip select signals 0 to 3.
CSR1 defines per ipheral chip select signals 4 to 7.
CSR2 defines per ipheral chip select signals 8 to 11.
CSR3 defines peripheral chip select signals 12 to 14.
• PS: Peripheral Select
1: Variable Peripheral Sele ct.
0: Fixed Peripheral Select.
• MSTR: Master/Slave Mode
1: SPI is in master mode.
0: SPI is in slave mode.
421
32072H–AVR32–10/2012
AT32UC3A3
21.8.3 Receive Data Register
Name: RDR
Access Type: Read-only
Offset: 0x08
Reset Value: 0x00000000
• RD: Receive Data
Data received by the SPI Inte rface is stored in this register right-justified. Unused bits read zero.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
RD[15:8]
76543210
RD[7:0]
422
32072H–AVR32–10/2012
AT32UC3A3
21.8.4 Transmit Data Register
Name: TDR
Access Type: Write-only
Offset: 0x0C
Reset Value: 0x00000000
• LASTXFER: Last Transfer
1: The current NPCS will be deasserted after the character written in TD has been transferred. When CSRn.CSAAT is one, this
allows to close the communication with the current serial peripheral by raising the corresponding NPCS line as soon as TD
transfer has completed.
0: Writing a ze ro to this bi t ha s no ef fect.
This field is only used if Variable Peripheral Select is active (MR.PS = 1).
• PCS: Peripheral Chip Select
If PCSDEC = 0:
PCS = xxx0NPCS[3:0] = 1110
PCS = xx01NPCS[3:0] = 1101
PCS = x011NPCS[3:0] = 1011
PCS = 0111NPCS[3:0] = 0111
PCS = 1111forbidden (no peripheral is selected)
(x = don’t care)
If PCSDEC = 1:
NPCS[3:0] output signals = PCS
This field is only used if Variable Peripheral Select is active (MR.PS = 1).
• TD: Transmit Data
Data to be transmitted by the SPI Interface is stored in this register. Information to be transmitted must be written to the TDR
register in a right-justified format.
31 30 29 28 27 26 25 24
-------LASTXFER
23 22 21 20 19 18 17 16
---- PCS
15 14 13 12 11 10 9 8
TD[15:8]
76543210
TD[7:0]
423
32072H–AVR32–10/2012
AT32UC3A3
21.8.5 Status Register
Name: SR
Access Type: Read-only
Offset: 0x10
Reset Value: 0x00000000
• SPIENS: SPI Enable Status
1: This bit is set when the SPI is enabled.
0: This bit is cleared when the SPI is disabled.
• UNDES: Underrun Error Status (Slave Mode Only)
1: This bit is set when a transfer begins whereas no data has been loaded in the TDR register.
0: This bit is cleared when the SR register is read.
• TXEMPTY: Tra nsm ission Registers Empty
1: This bit is set when TDR and internal shifter are empty. If a transfer delay has been defined, TXEMPTY is set after the
completion of such delay.
0: This bit is cleared as soon as data is written in TDR.
• NSSR: NSS Rising
1: A rising edg e occurred on NSS pin since last read.
0: This bit is cleared when the SR register is read.
• OVRES: Overrun Error Status
1: This bit is set when an overrun has occurred. An overru n occurs when RDR is loaded at least twice from the serializer since
the last read of the RDR.
0: This bit is cleared when the SR register is read.
• MODF: Mode Fault Error
1: This bit is set when a Mode Fault occurred.
0: This bit is cleared when the SR register is read.
• TDRE: Transmit Data Register Empty
1: This bit is set when the last data written in the TDR register has been transferred to the serializer.
0: This bit is cleared when data has been written to TDR and not yet transferred to the serial izer.
TDRE equals zero when the SPI is disabled or at reset. The SPI enable command sets this bit to one.
• RDRF: Receive Data Register Full
1: Data has been received and the received data has been transferred from the serializer to RDR since the last read of RDR.
0: No data has been received since the last read of RDR
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
-------SPIENS
15 14 13 12 11 10 9 8
- - - - - UNDES TXEMPTY NSSR
76543210
- - - - OVRES MODF TDRE RDRF
424
32072H–AVR32–10/2012
AT32UC3A3
21.8.6 Interrupt Enable Register
Name: IER
Access Type: Write-only
Offset: 0x14
Reset Value: 0x00000000
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will set the corresponding bit in IMR.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
- - - - - UNDES TXEMPTY NSSR
76543210
- - - - OVRES MODF TDRE RDRF
425
32072H–AVR32–10/2012
AT32UC3A3
21.8.7 Interrupt Disable Register
Name: IDR
Access Type: Write-only
Offset: 0x18
Reset Value: 0x00000000
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will clear the corresponding bit in IMR.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
- - - - - UNDES TXEMPTY NSSR
76543210
- - - - OVRES MODF TDRE RDRF
426
32072H–AVR32–10/2012
AT32UC3A3
21.8.8 Interrupt Mask Register
Name: IMR
Access Type: Read-only
Offset: 0x1C
Reset Value: 0x00000000
0: The corresponding interr upt is disabled.
1: The corresponding interrupt is enabled.
A bit in this register is cleared when the corresponding bit in IDR is wr itten to one.
A bit in this register is set when the corresponding bit in IER is written to one.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
- - - - - UNDES TXEMPTY NSSR
76543210
- - - - OVRES MODF TDRE RDRF
427
32072H–AVR32–10/2012
AT32UC3A3
21.8.9 Chip Select Register 0
Name: CSR0
Access Type: Read/Write
Offset: 0x30
Reset Value: 0x00000000
• DLYBCT: Delay Between Consecutive Transfers
This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The
delay is always inserted after each transfer and before removing the chip select if needed.
When DLYBCT equals zero, no delay between co nsecutive transfers is inserted and the clock keeps its duty cycle over the
character transfers.
Otherwise, the following equation determines the delay:
• DLYBS: Delay Before SPCK
This field defines the delay from NPCS valid to the first valid SPCK transition.
When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period.
Otherwise, the following equations determine the delay:
• SCBR: Serial Clock Baud Rate
In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the CLK_SPI. The Baud rate is
selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate:
Writing the SCBR field to zero is forbidden. Triggering a transfer while SCBR is zero can lead to unpredictable results.
At reset, SCBR is zero and the user has to write it to a valid value before performing the first transfer.
If a clock divider (SCBRn) field is set to one and the other SCBR fields differ from one, access on CSn is correct but no correct
access will be possible on other CS.
31 30 29 28 27 26 25 24
DLYBCT
23 22 21 20 19 18 17 16
DLYBS
15 14 13 12 11 10 9 8
SCBR
76543210
BITS CSAAT CSNAAT NCPHA CPOL
Delay Between Consecutive Transfers 32 DLYBCT×
CLKSPI
------------------------------------=
Delay Before SPCK DLYBS
CLKSPI
---------------------=
SPCK Baudrate CLKSPI
SCBR
---------------------=
428
32072H–AVR32–10/2012
AT32UC3A3
• BITS: Bits Per Transfer
The BITS field determines the number of data bits transferred. Reserved va lues should not be used.
• CSAAT: Chip Select Active After Transfer
1: The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested
on a different chip select.
0: The Peripheral Chip Select Line rises as soon as the last transf er is achieved.
• CSNAAT: Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
0: The Peripheral Chip Select does not rise between two transfers if the TDR is reloaded before the end of the first transfer and
if the two transfers occur on the same Chip Select.
1: The P eripheral Chip Select rises systematically between each transfer perf ormed on the same slav e for a minimal duration of:
(if DLYBCT field is different from 0)
(if DLYBCT field equals 0)
• NCPHA: Clock Phase
1: Data is captured after the leading (inactive-to-active) edge of SPCK and changed on the trailing (active-to-inactive) edge of
SPCK.
0: Data is changed on the leading (inactive-to-active) edge of SPCK and captured after the trailing (active-to-inactive) edge of
SPCK.
NCPHA deter mines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used
with CPOL to produce the required clock/data relationship between master and slave devices.
•CPOL: Clock Polarity
1: The inactive state valu e of SPCK is logic level one.
0: The inactive state valu e of SPCK is l ogi c level z e ro.
BITS Bits Per Transfer
0000 8
0001 9
0010 10
0011 11
0100 12
0101 13
0110 14
0111 15
1000 16
1001 4
1010 5
1011 6
1100 7
1101 Reserved
1110 Reserved
1111 Reserved
DLYBCS
CLKSPI
-----------------------
DLYBCS 1+
CLKSPI
---------------------------------
429
32072H–AVR32–10/2012
AT32UC3A3
CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required
clock/data relationship between master and slave devices.
430
32072H–AVR32–10/2012
AT32UC3A3
21.8.10 Chip Select Register 1
Name: CSR1
Access Type: Read/Write
Offset: 0x34
Reset Value: 0x00000000
• DLYBCT: Delay Between Consecutive Transfers
This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The
delay is always inserted after each transfer and before removing the chip select if needed.
When DLYBCT equals zero, no delay between co nsecutive transfers is inserted and the clock keeps its duty cycle over the
character transfers.
Otherwise, the following equation determines the delay:
• DLYBS: Delay Before SPCK
This field defines the delay from NPCS valid to the first valid SPCK transition.
When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period.
Otherwise, the following equations determine the delay:
• SCBR: Serial Clock Baud Rate
In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the CLK_SPI. The Baud rate is
selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate:
Writing the SCBR field to zero is forbidden. Triggering a transfer while SCBR is zero can lead to unpredictable results.
At reset, SCBR is zero and the user has to write it to a valid value before performing the first transfer.
If a clock divider (SCBRn) field is set to one and the other SCBR fields differ from one, access on CSn is correct but no correct
access will be possible on other CS.
31 30 29 28 27 26 25 24
DLYBCT
23 22 21 20 19 18 17 16
DLYBS
15 14 13 12 11 10 9 8
SCBR
76543210
BITS CSAAT CSNAAT NCPHA CPOL
Delay Between Consecutive Transfers 32 DLYBCT×
CLKSPI
------------------------------------=
Delay Before SPCK DLYBS
CLKSPI
---------------------=
SPCK Baudrate CLKSPI
SCBR
---------------------=
431
32072H–AVR32–10/2012
AT32UC3A3
• BITS: Bits Per Transfer
The BITS field determines the number of data bits transferred. Reserved va lues should not be used.
• CSAAT: Chip Select Active After Transfer
1: The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested
on a different chip select.
0: The Peripheral Chip Select Line rises as soon as the last transf er is achieved.
• CSNAAT: Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
0: The Peripheral Chip Select does not rise between two transfers if the TDR is reloaded before the end of the first transfer and
if the two transfers occur on the same Chip Select.
1: The P eripheral Chip Select rises systematically between each transfer perf ormed on the same slav e for a minimal duration of:
(if DLYBCT field is different from 0)
(if DLYBCT field equals 0)
• NCPHA: Clock Phase
1: Data is captured after the leading (inactive-to-active) edge of SPCK and changed on the trailing (active-to-inactive) edge of
SPCK.
0: Data is changed on the leading (inactive-to-active) edge of SPCK and captured after the trailing (active-to-inactive) edge of
SPCK.
NCPHA deter mines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used
with CPOL to produce the required clock/data relationship between master and slave devices.
•CPOL: Clock Polarity
1: The inactive state valu e of SPCK is logic level one.
0: The inactive state valu e of SPCK is l ogi c level z e ro.
BITS Bits Per Transfer
0000 8
0001 9
0010 10
0011 11
0100 12
0101 13
0110 14
0111 15
1000 16
1001 4
1010 5
1011 6
1100 7
1101 Reserved
1110 Reserved
1111 Reserved
DLYBCS
CLKSPI
-----------------------
DLYBCS 1+
CLKSPI
---------------------------------
432
32072H–AVR32–10/2012
AT32UC3A3
CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required
clock/data relationship between master and slave devices.
433
32072H–AVR32–10/2012
AT32UC3A3
21.8.11 Chip Select Register 2
Name: CSR2
Access Type: Read/Write
Offset: 0x38
Reset Value: 0x00000000
• DLYBCT: Delay Between Consecutive Transfers
This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The
delay is always inserted after each transfer and before removing the chip select if needed.
When DLYBCT equals zero, no delay between co nsecutive transfers is inserted and the clock keeps its duty cycle over the
character transfers.
Otherwise, the following equation determines the delay:
• DLYBS: Delay Before SPCK
This field defines the delay from NPCS valid to the first valid SPCK transition.
When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period.
Otherwise, the following equations determine the delay:
• SCBR: Serial Clock Baud Rate
In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the CLK_SPI. The Baud rate is
selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate:
Writing the SCBR field to zero is forbidden. Triggering a transfer while SCBR is zero can lead to unpredictable results.
At reset, SCBR is zero and the user has to write it to a valid value before performing the first transfer.
If a clock divider (SCBRn) field is set to one and the other SCBR fields differ from one, access on CSn is correct but no correct
access will be possible on other CS.
31 30 29 28 27 26 25 24
DLYBCT
23 22 21 20 19 18 17 16
DLYBS
15 14 13 12 11 10 9 8
SCBR
76543210
BITS CSAAT CSNAAT NCPHA CPOL
Delay Between Consecutive Transfers 32 DLYBCT×
CLKSPI
------------------------------------=
Delay Before SPCK DLYBS
CLKSPI
---------------------=
SPCK Baudrate CLKSPI
SCBR
---------------------=
434
32072H–AVR32–10/2012
AT32UC3A3
• BITS: Bits Per Transfer
The BITS field determines the number of data bits transferred. Reserved va lues should not be used.
• CSAAT: Chip Select Active After Transfer
1: The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested
on a different chip select.
0: The Peripheral Chip Select Line rises as soon as the last transf er is achieved.
• CSNAAT: Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
0: The Peripheral Chip Select does not rise between two transfers if the TDR is reloaded before the end of the first transfer and
if the two transfers occur on the same Chip Select.
1: The P eripheral Chip Select rises systematically between each transfer perf ormed on the same slav e for a minimal duration of:
(if DLYBCT field is different from 0)
(if DLYBCT field equals 0)
• NCPHA: Clock Phase
1: Data is captured after the leading (inactive-to-active) edge of SPCK and changed on the trailing (active-to-inactive) edge of
SPCK.
0: Data is changed on the leading (inactive-to-active) edge of SPCK and captured after the trailing (active-to-inactive) edge of
SPCK.
NCPHA deter mines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used
with CPOL to produce the required clock/data relationship between master and slave devices.
•CPOL: Clock Polarity
1: The inactive state valu e of SPCK is logic level one.
0: The inactive state valu e of SPCK is l ogi c level z e ro.
BITS Bits Per Transfer
0000 8
0001 9
0010 10
0011 11
0100 12
0101 13
0110 14
0111 15
1000 16
1001 4
1010 5
1011 6
1100 7
1101 Reserved
1110 Reserved
1111 Reserved
DLYBCS
CLKSPI
-----------------------
DLYBCS 1+
CLKSPI
---------------------------------
435
32072H–AVR32–10/2012
AT32UC3A3
CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required
clock/data relationship between master and slave devices.
436
32072H–AVR32–10/2012
AT32UC3A3
21.8.12 Chip Select Register 3
Name: CSR3
Access Type: Read/Write
Offset: 0x3C
Reset Value: 0x00000000
• DLYBCT: Delay Between Consecutive Transfers
This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select. The
delay is always inserted after each transfer and before removing the chip select if needed.
When DLYBCT equals zero, no delay between co nsecutive transfers is inserted and the clock keeps its duty cycle over the
character transfers.
Otherwise, the following equation determines the delay:
• DLYBS: Delay Before SPCK
This field defines the delay from NPCS valid to the first valid SPCK transition.
When DLYBS equals zero, the NPCS valid to SPCK transition is 1/2 the SPCK clock period.
Otherwise, the following equations determine the delay:
• SCBR: Serial Clock Baud Rate
In Master Mode, the SPI Interface uses a modulus counter to derive the SPCK baud rate from the CLK_SPI. The Baud rate is
selected by writing a value from 1 to 255 in the SCBR field. The following equations determine the SPCK baud rate:
Writing the SCBR field to zero is forbidden. Triggering a transfer while SCBR is zero can lead to unpredictable results.
At reset, SCBR is zero and the user has to write it to a valid value before performing the first transfer.
If a clock divider (SCBRn) field is set to one and the other SCBR fields differ from one, access on CSn is correct but no correct
access will be possible on other CS.
31 30 29 28 27 26 25 24
DLYBCT
23 22 21 20 19 18 17 16
DLYBS
15 14 13 12 11 10 9 8
SCBR
76543210
BITS CSAAT CSNAAT NCPHA CPOL
Delay Between Consecutive Transfers 32 DLYBCT×
CLKSPI
------------------------------------=
Delay Before SPCK DLYBS
CLKSPI
---------------------=
SPCK Baudrate CLKSPI
SCBR
---------------------=
437
32072H–AVR32–10/2012
AT32UC3A3
• BITS: Bits Per Transfer
The BITS field determines the number of data bits transferred. Reserved va lues should not be used.
• CSAAT: Chip Select Active After Transfer
1: The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested
on a different chip select.
0: The Peripheral Chip Select Line rises as soon as the last transf er is achieved.
• CSNAAT: Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
0: The Peripheral Chip Select does not rise between two transfers if the TDR is reloaded before the end of the first transfer and
if the two transfers occur on the same Chip Select.
1: The P eripheral Chip Select rises systematically between each transfer perf ormed on the same slav e for a minimal duration of:
(if DLYBCT field is different from 0)
(if DLYBCT field equals 0)
• NCPHA: Clock Phase
1: Data is captured after the leading (inactive-to-active) edge of SPCK and changed on the trailing (active-to-inactive) edge of
SPCK.
0: Data is changed on the leading (inactive-to-active) edge of SPCK and captured after the trailing (active-to-inactive) edge of
SPCK.
NCPHA deter mines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used
with CPOL to produce the required clock/data relationship between master and slave devices.
•CPOL: Clock Polarity
1: The inactive state valu e of SPCK is logic level one.
0: The inactive state valu e of SPCK is l ogi c level z e ro.
BITS Bits Per Transfer
0000 8
0001 9
0010 10
0011 11
0100 12
0101 13
0110 14
0111 15
1000 16
1001 4
1010 5
1011 6
1100 7
1101 Reserved
1110 Reserved
1111 Reserved
DLYBCS
CLKSPI
-----------------------
DLYBCS 1+
CLKSPI
---------------------------------
438
32072H–AVR32–10/2012
AT32UC3A3
CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required
clock/data relationship between master and slave devices.
439
32072H–AVR32–10/2012
AT32UC3A3
21.8.13 Write Protection Control Register
Register Name: WPCR
Access Type: Read-write
Offset: 0xE4
Reset Value: 0x00000000
•SPIWPKEY: SPI Write Protection Key Password
If a value is written in SPIWPEN, the value is taken into account only if SPIWPKEY is written with “SPI” (SPI written in ASCII
Code, i.e. 0x535049 in hexadecimal).
•SPIWPEN: SPI Write Protection Enable
1: The Write Protection is Enabled
0: The Write Protection is Disabled
31 30 29 28 27 26 25 24
SPIWPKEY[23:16]
23 22 21 20 19 18 17 16
SPIWPKEY[15:8]
15 14 13 12 11 10 9 8
SPIWPKEY[7:0]
76543210
-------SPIWPEN
440
32072H–AVR32–10/2012
AT32UC3A3
21.8.14 Write Protection Status Register
Register Name: WPSR
Access Type: Read-only
Offset: 0xE8
Reset Value: 0x00000000
• SPIWPVSRC: SPI Write Protection Violation Source
This Field indicates the Peripheral Bus Offset of the register concerned by the violation (MR or CSRx)
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
SPIWPVSRC
76543210
- - - - - SPIWPVS
441
32072H–AVR32–10/2012
AT32UC3A3
• SPIWPVS: SPI Write Protection Violation Status
•
•
•
•
•
•
•
•
•
•
•
•
SPIWPVS value Violation Type
1 The Write Protection has block ed a Write access to a protected register (since the last read).
2Software Reset has been performed while Wri te Protection was enabled (since the last read
or since the last write access on MR, IER, IDR or CSRx).
3Both Write Protection violation and software reset with Write Protection enabled have
occurred since the last read.
4Write accesses hav e been detected on MR (while a chip select was activ e) or on CSRi (while
the Chip Select “i” was active) since the last read.
5The Write Protection has blocked a Write access to a protected register and write accesses
have been detected on MR (while a chip select was active) or on CSRi (while the Chip Select
“i” was active) since the last read.
6
Software Reset has been performed while Wri te Protection was enabled (since the last read
or since the last write access on MR, IER, IDR or CSRx) and some write accesses hav e been
detected on MR (while a chip select was active) or on CSRi (while the Chip Select “i” was
active) since the last rea d.
7
- The Write Prote c tion has blocked a Write access to a protected register.
and
- Software Reset has been performed while Write Protectio n was enabled.
and
- Write accesses have been detected on MR (while a chip select was active) or on CSRi
(while the Chip Select “i” was active) since the last read.
442
32072H–AVR32–10/2012
AT32UC3A3
21.8.15 Version Register
Register Name: VERSION
Access Type: Read-only
Offset: 0xFC
Reset Value: –
•MFN Reserved. No functionality associated.
•VERSION
Version number of the module. No functionality associated.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
---- MFN
15 14 13 12 11 10 9 8
VERSION[11:8]
76543210
VERSION[7:0]
443
32072H–AVR32–10/2012
AT32UC3A3
21.9 Module Configuration
The specific configuration for each SPI instance is listed in the following tables.The module bus
clocks listed here are connected to the system bus clocks. Please refer to the Power Manager
section for details.
Table 21-4. Module Clock Name
Module Name Clock Name
SPI0 CLK_SPI0
SPI1 CLK_SPI1
Table 21-5. Register Reset Values
Register Reset Value
VERSION 0x00000210
444
32072H–AVR32–10/2012
AT32UC3A3
22. Two-wire Slave Interface (TWIS)
Rev.: 1.0.0.1
22.1 Features •Compatible with I²C standard
– Transfer speeds of 100 and 400 kbit/s
– 7 and 10-bit and General Call addressing
•Compatible with SMBus standard
– Hardware Packet Error Checking (CRC) generation and verification with ACK response
– SMBALERT interface
– 25 ms clock low timeout delay
– 25 ms slave cumulative clock low e x te nd tim e
•Compatible with PMBus
•DMA interface for reducing CPU load
•Arbitrary transfer lengths, including 0 data bytes
•Optional clock stretching if transmit or receive buffers not ready for data transfer
•32-bit Peripheral Bus interface for configuration of the interface
22.2 Overview The Atmel Two-wire Slave Interface (TWIS) interconnects components on a unique two-wire
bus, made up of one clock line and one dat a line with speeds of up t o 400 kbit/s, based on a
byte-oriented transfer forma t. It can be used with any Atmel Two -wire Interface bus, I²C, or
SMBus-compatible master. The TWIS is always a bus slave and can transfer sequential or sin-
gle bytes.
Below, Table 22 -1 lists the compatibility lev el of the Atmel Two-wire Slave Interface and a full I²C
compatible device.
Note: 1. START + b000000001 + Ack + Sr
Table 22-1. Atmel TWIS Compatibility with I²C Standard
I²C Standard Atmel TWIS
Standard-mode (100 kbit/s) Supported
Fast-mode (400 kbit/s) Supported
7 or 10 bits Slave Addressing Supported
START BYTE(1) Not Supported
Repeated Start (Sr) Condition Supported
ACK and NAK Management Supported
Slope control and input filtering (Fast mode) Supported
Clock stretching Supported
445
32072H–AVR32–10/2012
AT32UC3A3
Below, Table 22-2 lists the compatibility level of the Atmel Two-wire Slave Interface and a full
SMBus compatible device.
22.3 List of Abbreviations
22.4 Block Diagram
Figure 22-1. Block Diagram
Table 22-2. Atmel TWIS Compatibility with SMBus Standard
SMBus Standard Atmel TWIS
Bus Timeouts Supported
Address Resolution Protocol Supported
Alert Supported
Packet Error Checking Supported
Table 22-3. Abbreviations
Abbreviation Description
TWI Two-wire Interface
A Acknowledge
NA Non Acknowledge
PStop
SStart
Sr Repeated Start
SADR Slave Address
ADR Any address except SADR
R Read
WWrite
Peripheral
Bus Bridge
Two-wire
Interface
I/O Controller
TWCK
TWD
Interrupt
Controller
TWI Interrupt
Power
Manager
CLK_TWIS
TWALM
446
32072H–AVR32–10/2012
AT32UC3A3
22.5 Application Block Diagram
Figure 22-2. Application Block Diagram
22.6 I/O Lines Description
22.7 Product Dependencies
In order to use t his modu le, othe r p arts o f th e syst em must be conf igu red cor re ctly, as de scr ibed
below.
22.7.1 I/O Lines TWDand TWCK are bidirectional lines, connected to a p ositive supply voltage via a current
source or pull-up resistor (see Figure 22-5 on page 448). When the bus is free, both lines are
high. The output stages of devices connected to the bus must have an open-drain or open-col-
lector to perform t he wired-AND function.
TWALM is used to implement the opt ional SMBus SMBALERT signal.
TWALM, TWD, and TWCK pins may be multiplexed with I/O Controller lines. To enable the
TWIS, the user must perform the fo llowing steps:
• Program the I/O Controller to:
– Dedicate TWD, TWCK, and optionally TWALM as peripheral lines.
– Define TWD, TWCK, and optionally TWALM as open-drain.
Host with
TWI
Interface
TWD
TWCK
Atmel TWI
serial EEPROM I²C RTC I²C LCD
controller
Slave 1 Slave 2 Slave 3
VDD
I²C temp.
sensor
Slave 4
Rp: Pull up value as given by the I²C Standard
Rp Rp
Table 22-4. I/O Lines Description
Pin Name Pin Description Type
TWD Two-wire Serial Data Input/Output
TWCK Two-wire Serial Clock Input/Output
TWALM SMBus SMBALERT Input/Output
447
32072H–AVR32–10/2012
AT32UC3A3
22.7.2 Power Management
If the CPU enters a sleep mode that dis ables c locks used by the TWIS, the TW IS will stop func-
tioning and resume operation after th e system wakes up from sleep mode.
22.7.3 Clocks The clock for the TWIS bus interface (CLK_TWIS) is generated by the Power Manager. This
clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to dis-
able the TWIS before disabling the clock, to avoid freezing the TWIS in an und efined state.
22.7.4 DMA The TWIS DMA handshake interface is connected to the Peripheral DMA Controller. Using the
TWIS DMA functionality requires the Peripheral DMA Controller to be programmed after setting
up the TWIS.
22.7.5 Interrupts The TWIS interrupt request lines are connected to the interrupt controller. Using the TWIS inter-
rupts requires the interrupt controller to be programmed first.
22.7.6 Debug Operation
When an external debugger forces the CPU into debug m ode, the TWIS continues normal oper-
ation. If the TWIS is configured in a way that requires it to be periodically serviced by the CPU
through interrupt s or similar, improper operation or data loss may result durin g debugging.
22.8 Functional Description
22.8.1 Transfer Format
The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must
be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure
22-4 on page 448).
Each transfer begins with a START condition and terminates with a STOP condition (see Figure
22-3).
• A high-to-low transition on the TWD line while TWCK is high defines the START condition.
• A low-to-high transition on the TWD line while TWCK is high defines a STOP condition.
Figure 22-3. START and STOP Conditions
TWD
TWCK
Start Stop
448
32072H–AVR32–10/2012
AT32UC3A3
Figure 22-4. Transfer Format
22.8.2 Operation The TWIS has two modes of oper ation:
• Slave transmitter mode
• Slave receiver mode
A master is a device which start s and stops a transfer and gen erates the TWCK clock. A slave is
assigned an address and responds to requests from the master. These modes are described in
the following chapte rs.
Figure 22-5. Typical Application Block Diagram
22.8.2.1 Bus Timing The Timing Register (TR) is used to control the timing of bus signals driven by the TWIS. TR
describes bus timings as a function of cycles of the prescaled CLK_TWIS. The clock prescaling
can be selected through TR.EXP.
TR has the following fields:
TLOWS: Prescaled clock cycles used to time SMBUS timeout TLOW:SEXT.
TWD
TWCK
Start Address R/W Ack Data Ack Data Ack Stop
Host with
TWI
Interface
TWD
TWCK
Atmel TWI
Serial EEPROM I²C RTC I²C LCD
Controller
Slave 1 Slave 2 Slave 3
VDD
I²C Temp .
Sensor
Slave 4
Rp: Pull up value as given by the I²C Standard
Rp Rp
fPRESCALED fCLK_TWIS
2EXP 1+()
-------------------------=
449
32072H–AVR32–10/2012
AT32UC3A3
TTOUT: Prescaled clock cycles used to time SMBUS timeout TTIMEOUT.
SUDAT: Non-prescaled clock cycles for data setup and hold count. Used to time TSU_DAT.
EXP: Specifies the clock prescaler setting used for the SMBUS timeouts.
Figure 22-6. Bus Timing Diagram
22.8.2.2 Setting Up and Performing a Transfer
Operation of the TWIS is mainly controlled by the Control Register (CR). The following list pres-
ents the main steps in a typical comm unication:
4. Before any tr ansfers can be performed, bus timings must be configured by writing to the
Timing Register (TR).If the Peripheral DMA Controller is to be used for the transfers, it
must be set up.
5. The Control Register (CR) must be configured with information such as the slave
address , SMBus mo de, Packet Error Checking (PEC), number of bytes to transfer, and
which addresses to ma tch.
The interrupt syst em can be set up to generate interrupt request on specific events or error con-
ditions, for example when a byte has been received.
The NBYTES register is only used in SMBus mode, when PEC is enabled. In I²C mode or in
SMBus mode wh en PEC is disa bled, th e NBYT ES regis ter is not us ed, and shou ld be w ritten to
zero. NBYTES is updated by hardware, so in order to avoid hazards, software updates of
NBYTES can only be done through writes to the NBYTES register.
22.8.2.3 Address Matching
The TWIS can be set up to match several different addres ses. More than one address match
may be enabled simultaneously, allowing the TWIS to be assigned to several addresses. The
address matching phase is initiated after a START or REPEATED START condition. When the
TWIS receives an address that generates an address match, an ACK is automatically returned
to the mast er.
StHD:STA
tLOW
tSU:DAT
tHIGH
tHD:DAT
tLOW
P
tSU:STO
Sr
tSU:STA
tSU:DAT
450
32072H–AVR32–10/2012
AT32UC3A3
In I²C mode:
• The address in CR.ADR is checked for address match if CR.SMATCH is one.
• The General Call address is checked for address matc h if CR.GCMATCH is one.
In SMBus mode:
• The address in CR.ADR is checked for address match if CR.SMATCH is one.
• The Alert Response Address is checked for address match if CR.SMAL is one.
• The Default Address is checked for address match if CR.SMDA is one.
• The Host Header Address is chec ked for address match if CR.SMHH is one.
22.8.2.4 Clock Stretching
Any slave or bus master taking part in a transfer may extend the TWCK low period at any time.
The TWIS may extend the TWCK low period after each byte transfer if CR.STREN is one an d :
• Module is in slave transmitter mode, data should be transmitted, but THR is empty, or
• Module is in slave receiver mode, a by te has been received and placed into the internal
shifter, but the Receive Holding Register (RHR) is full, or
• Stretch-on-address-match bit CR.SOAM=1 and slave was addressed. Bus clock remains
stretched until all address match bits in the Status Register (SR) have been cleared.
If CR.STREN is zero and:
• Module is in slave transmitter mode, data should be transmitted but THR is empty: Transmit
the value present in THR (the last transmitted byte or reset value), and set SR.URUN.
• Module is in slave receiver mode, a by te has been received and placed into the internal
shifter, but RHR is full: Discard the received byte and set SR.ORUN.
22.8.2.5 Bus Errors If a bus error (misplaced START or STOP) condition is detected, the SR.BUSERR bit is set and
the TWIS waits for a new START condition.
22.8.3 Slave Transmitter Mode
If the TWIS matches an address in which the R/W bit in the TWI address phase transfer is set, it
will enter slave transmitter mode and set the SR.TRA bit (note that SR.TRA is set one
CLK_TWIS cycle after the rele vant address match bit in the same register is set).
After the address phase, the following actions are performed:
1. If SMBus mode and PEC is used, NBYTES must be set up with the nu mbe r of bytes to
transmit. This is necessary in order to know when to transmit the PEC byte. NBYTES
can also be used to count the number of bytes received if using DMA.
2. Byte to transmit depends on I²C/SMBus mode and CR.PEC:
– If in I²C mode or CR.PEC is zero or NBYTES is non-zero: The TWIS waits until THR
contains a valid data byte, possibly stretching the low period of TWCK. After THR
contains a valid data byte, the data byte is transferred to a shifter, and then
SR.TXRDY is changed to one because the THR is empty again.
– SMBus mode and CR.PEC is one: If NBYTES is zero, the generated PEC byte is
automatically transmitted instead of a data byte from THR. TWCK will not be
stretched by the TWIS.
3. The data byte in th e shifter is transmitted.
451
32072H–AVR32–10/2012
AT32UC3A3
4. NBYTES is updated. If CR.CUP is one, NBYTES is incremented, otherwise NBYTES is
decremented.
5. After each data b yte has been tr ansmitted, the master transmits an A CK (Ac knowledge )
or NAK (Not Acknowledge) bit. If a NAK bit is received by the TWIS, the SR.NAK bit is
set. Note that this is done tw o CLK_TWIS cycle s after TWCK has been sam pled b y the
TWIS to be HIGH (see Figure 22-9). The NAK indicates that the transf er is finished, and
the TWIS will wait for a STOP or REPEATED START. If an ACK bit is received, the
SR.NAK bit remains LOW. The ACK indicates that more data should be transmitted,
jump to step 2. At the end of the ACK/NAK clock cycle, the Byte Transfer Finished
(SR.BTF) bit is set. Note that this is done two CLK_TWIS cycles after TWCK has been
sampled by the TWIS to be LOW (see Figure 22-9). Also note that in the event that
SR.NAK bit is set, it must not be cleared before the SR.BTF bit is set to ensure correct
TWIS behavior.
6. If STOP is received, SR.TCOMP and SR.STO will be set.
7. If REPEAT ED START is received, SR.REP will be set.
The TWI transfers require the receiver to acknowledge each received data byte. During the
acknowledge clock pulse (9th pulse), the slave releases the data line (HI GH), enabling the mas-
ter to pull it down in order to generate the acknowledge. The slave polls the data line during this
clock pulse and sets the NAK bit in SR if the ma ster do es not acknowledge th e data byte. A NAK
means that the m aster does not wish to receive addition al data bytes. As with the ot her status
bits, an interrupt can be generated if enabled in the Interrupt Enable Register (IER).
SR.TXRDY is used as Transmit Ready for the Peripheral DMA Controller transmit channel.
The end of the complete transfer is marked by the SR.TCOMP bit changing from zero to one.
See Figure 22-7 and Figure 22-8.
Figure 22-7. Slave Transmitter with One Data Byte
TCOMP
TXRDY
Write THR (DATA) STOP sent by master
TWD ADATANSDADRR P
NBYTES set to 1
452
32072H–AVR32–10/2012
AT32UC3A3
Figure 22-8. Slave Transmitter with Multiple Data Bytes
Figure 22-9. Timing Relationship between TWCK, SR.NAK, and SR.BTF
22.8.4 Slave Receiver Mode
If the TWIS matches an address in which the R/W bit in the TWI address phase transfer is
cleared, it will enter slave receiver mode and clear SR.TRA (note that SR.TRA is cleared on e
CLK_TWIS cycle after the rele vant address match bit in the same register is set).
After the address phase, the following is repeated:
1. If SMBus mode and PEC is used, NBYTES must be set up with the nu mbe r of bytes to
receive . This is necessary in order to know which of the received b ytes is the PEC byte .
NBYTES can also be used to count the number of bytes received if using DMA.
2. Receive a byte. Set SR.BT F when done.
3. Update NBYTES. If CR.CUP is written to one, NBYTES is incremented, otherwise
NBYTES is decremented. NBYTES is usually co nfigured to co unt downwards if PEC is
used.
4. After a data byte has been received, the slave transmit s an ACK or NAK bit. For ordi-
nary data b ytes , the CR.A CK field cont rols if an A CK or NAK should be returned. If PEC
is enable d and the last byte received was a PEC byte (indicated by NBYTES equal to
zero), The TWIS will automatically return an ACK if the PEC value was correct, other-
wise a NAK will be returned.
5. If STOP is received, SR.TCOMP will be set.
6. If REPEAT ED START is received, SR.REP will be set.
The TWI transfers require the receiver to acknowledge each received data byte. During the
acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the
ADATA nASDADRR DATA n+5A PDATA n+m N
TCO M P
TXRDY
Write THR (Data n)
NBYTES set to m
STOP sent by master
TWD
Write THR (Data n+1) Write THR (Data n+m)
Last data sent
DATA (LSB) N P
TWCK
SR.NAK
SR.BTF
t1t1
t1: (CLK_TWIS period) x 2
TWD
453
32072H–AVR32–10/2012
AT32UC3A3
slave to pull it down in order to generate the acknowledge. The master polls the data line during
this clock pulse.
The SR.RXRDY bit indicates that a data byte is available in the RHR. The RXRDY bit is also
used as Receive Ready for the Peri pheral DMA Controller receive channel.
Figure 22-10. Slave Receiver with One Data Byte
Figure 22-11. Slave Receiver with Multiple Data Bytes
22.8.5 Using the Peripheral DMA Controller
The use of the Peripheral DMA Controller significantly reduces the CPU load . The user can set
up ring buffer s for the Peripheral DMA Co ntroller, conta ining data to tran smit or free buffer space
to place received data. By initializing NBYTES to zero before a transfer, and writing a one to
CR.CUP, NBYTES is incremented by one each time a data has been transmitted or received.
This allows the user to detect how much data was actually transferred by the DMA system.
To assure correct behavior, respect the following programm ing sequences:
22.8.5.1 Data Transmit with the Peripheral DMA Controller
1. Initialize the transmit Peripheral DMA Controller (memory pointers, size, etc.).
2. Configure the TWIS (ADR, NBYTES, etc.).
3. Start the transfer by enabling the Peripheral DMA Controller to transmit.
4. Wait for the Peripheral DMA Controller end-of-transmit flag.
5. Disable the Peripheral DMA Controller.
22.8.5.2 Data Receive with the Peripheral DMA Controller
1. Initialize the receive Peripheral DMA Contr oller (memory pointers, size - 1, etc.).
2. Configure the TWIS (ADR, NBYTES, etc.).
ASDADRW DATA AP
TCOMP
RX RDY
Read RHR
TWD
A
ASDADRW DATA nA ADATA (n+1) A DATA (n+m)DATA (n+m)-1 PTWD
TCO M P
RX RDY
Read RHR
DATA n
Read RHR
DATA ( n+1)
Read RHR
DAT A (n+m)-1
Read RHR
DATA (n+m)
454
32072H–AVR32–10/2012
AT32UC3A3
3. Start the transfer by enabling the Peripheral DMA Controller to receive.
4. Wait for the Peripheral DMA Contr oller end-of-receive flag.
5. Disable the Peripheral DMA Controller.
22.8.6 SMBus Mode SMBus mode is enabled by writing a one to the SMBus Mode Enable (SMEN) bit in CR. SMBus
mode operation is similar to I²C operation with the following exceptions:
• Only 7-bit addressing can be used.
• The SMBus standard describes a set of timeout v alues to ensure prog ress and throughput on
the bus. These timeou t values must be written to TR.
• Transmissions can optionally include a CRC byte, called Packet Error Check (PEC).
• A dedicated bus line, SMBALERT, allows a slave to get a master’s attention.
• A set of addresses have been reserved for protocol handling, such as Alert Response
Address (ARA) and Host Header (HH) Address. Address matching on these addresses can
be enabled by configuring CR approp riatel y.
22.8.6.1 Packet Error Checking (PEC)
Each SMBus transfer can optionally end with a CRC byte, called the PEC byte. Writing a one to
the Packet Error Checking Enable (PECEN) bit in CR enables automatic PEC hand ling in the
current transfer. The PEC generator is always updated on e very bit transmitted or received, so
that PEC handling on following linked transfers will be correct.
In slave re ceiver m ode, th e master calculates a PEC value and tr ansmits it to the slave after all
data bytes have been transmitted. Upon reception of this PEC byte, the slave w ill compare it to
the PEC value it has compu ted itself. If the values match, the d ata was received correctly, and
the slave will return an ACK to the master. If the PEC values differ, data was corrupted, and the
slave will return a NAK value. The SR.SMBPECERR bit is set automatically if a PEC error
occurred.
In slave transmitter mode, the slave calculates a PEC value and transmits it to the master after
all data bytes have been transmitted. Upon reception of this PEC byte, the master will compare
it to the PEC value it has computed itself. If the values match, the data was received correctly. If
the PEC values differ, data was corrupted, and the master must take appropriate action.
The PEC byte is automatically inserted in a slave transmitter transmission if PEC enabled when
NBYTES reaches zero. The PEC byte is identified in a slave receiver transmission if PEC
enabled when NBYTES reaches zer o. NBYTES must therefo re be set to the total number of
data bytes in the transmission, including the PEC byte.
22.8.6.2 Timeouts The Timing Register (TR) configures the SMBus timeout values. If a timeout occurs, the slave
will leave the bus. The SR.SMBTOUT bit is also set.
22.8.6.3 SMBALERT A slave can get the master’s attention by pulling the SMBALERT line low. This is done by writing
a one to the SMBus Alert (SMBALERT) bit in CR. This will also enable address match on the
Alert Response Address (ARA).
455
32072H–AVR32–10/2012
AT32UC3A3
22.8.7 Identifying Bus Events
This chapter lists the different bus events, and how these affects the bits in the TWIS registers.
This is intended to help writing drivers for the TWIS.
Table 22-5. Bus Events
Event Effect
Slav e transmitter has sent a
data byte
SR.THR is cleared.
SR.BTF is set.
The value of the ACK bit sent imme d i ately after the d at a byte is giv e n
by CR.ACK.
Slave receiver has received
a data byte
SR.RHR is set.
SR.BTF is set.
SR.NAK updated according to value of ACK bit received from master.
Start+Sadr on bus, but
address is to another slave None.
Start+Sadr on bus, current
slave is addressed, but
address match enable bit in
CR is not set
None.
Start+Sadr on bus, current
slave is addressed,
corresponding address
match enable bit in CR set
Correct address match bit in SR is set.
SR.TRA updated according to transfer direction (updating is done one
CLK_TWIS cycle after address match bit is set)
Slave enters appropria te transfer direction mode and data transfer
can commence.
Start+Sadr on bus, current
slave is addressed,
corresponding address
match enable bit in CR set,
SR.STREN and SR.SOAM
are set.
Correct address match bit in SR is set.
SR.TRA updated according to transfer direction (updating is done one
CLK_TWIS cycle after address match bit is set).
Slave stretches TWCK immediately after transmitting the address
ACK bit. TWCK remains stretched until all address match bits in SR
have been cleared .
Slave enters appropria te transfer direction mode and data transfer
can commence.
Repeated Start received
after being ad d ressed SR.REP set.
SR.TCOMP unchanged.
Stop received after being
addressed SR.ST O set.
SR.TCOMP set.
Start, Repeated Start, or
Stop received in illegal
position on bus
SR.BUSERR set.
SR.STO and SR.TCOMP may or ma y not be set depending on the
exact position of an illegal stop.
Data is to be received in
slave receiver mode,
SR.STREN is set, and RHR
is full
TWCK is stretched until RHR has been read.
Data is to be transmitted in
slave receiver mode,
SR.STREN is set, and THR
is empty
TWCK is stretched until THR has been written.
456
32072H–AVR32–10/2012
AT32UC3A3
Data is to be received in
slave receiver mode,
SR.STREN is cleared, and
RHR is full
TWCK is not stretched, read data is discarded.
SR.ORUN is set.
Data is to be transmitted in
slave receiver mode,
SR.STREN is cleared, and
THR is empt y
TWCK is not stretched, previous contents of THR is written to bus.
SR.URUN is set.
SMBus timeout received SR.SMBTOUT is set.
TWCK and TWD are immediately released.
Slave transmitter in SMBus
PEC mode has transmitted
a PEC byte, th at was not
identical to the PEC
calculated by the master
receiver.
Master receiver will transmit a NAK as usual after the last byte of a
master receiver transfer.
Master receiver will retry the transfer at a later time.
Slave receiver discovers
SMBus PEC Error SR.SMBPECERR is set.
NAK returned after the data byte .
Table 22-5. Bus Events
Event Effect
457
32072H–AVR32–10/2012
AT32UC3A3
22.9 User Interface
Note: 1. The reset values for these registers are device specific. Please refer to the Module Configuration section at the end of this
chapter.
Table 22-6. TWIS Register Memory Map
Offset Register Register Name Access Reset
0x00 Control Register CR Read/Write 0x00000000
0x04 NBYTES Register NBYTES Read/Write 0x00000000
0x08 Timing Reg ister TR Re ad/Write 0x00000000
0x0C Receive Holding Register RHR Read-only 0x00000000
0x10 Transmit Holding Register THR Write-only 0x000000 00
0x14 Packet Error Check Register PECR Read-only 0x00000000
0x18 Status Register SR Read-only 0x00000002
0x1C Interr upt Enable Register IER Write-only 0x00000000
0x20 Interrupt Disable Register IDR Write-only 0x00000000
0x24 Interrupt Mask Register IMR Read-only 0x00000000
0x28 Status Clear Register SCR Write-only 0x00000000
0x2C Parameter Register PR Read-only -(1)
0x30 Version Register VR Read-only -(1)
458
32072H–AVR32–10/2012
AT32UC3A3
22.9.1 Control Register
Name: CR
Access Type: Read/Write
Offset:0x00
Reset Value: 0x00000000
• TENBIT: Ten Bit Address Match
0: Disables Ten Bit Address Match.
1: Enables Ten Bit Address Match.
• ADR: Slave Address
Slave address used in slave address match. Bits 9:0 are used if in 10-bit mode, bits 6:0 otherwise.
• SOAM: Stretch Clock on Address Match
0: Does not stretch bus clock after address match.
1: Stretches bus clock after address match.
• CUP: NBYTES Count Up
0: Causes NBYTES to count down (decrement) per byte transferred.
1: Causes NBYTES to count up (increment) per byte transferred.
• ACK: Slave Receiver Data Phase ACK Value
0: Causes a low value to be returned in the ACK cycle of the data phase in slave receiver mode.
1: Causes a high value to be returned in th e ACK cycle of the data phase in slave receiver mode.
• PECEN: Packet Error Checking Enable
0: Disables SMBus PEC (CRC) generation and check.
1: Enables SMBus PEC (CRC) generation and check.
• SMHH: SMBus Host Header
0: Causes the TWIS not to acknowledge the SMBus Host Header.
1: Causes the TWIS to acknowledge the SMBus Host Header.
• SMDA: SMBus Default Address
0: Causes the TWIS not to acknowledge the SMBus Default Address.
1: Causes the TWIS to acknowledge the SMBus Default Address.
• SMBALERT: SMBus Alert
0: Causes the TWIS to release the SMBALERT line and not to acknowledge the SMBus Alert Response Address (ARA).
1: Causes the TWIS to pull down the SMBALERT line and to acknowledge the SMBus Alert Response Address (ARA).
• SWRST : Software Reset
This bit will always read as 0.
Writing a zero to this bit has no effect.
31 30 29 28 27 26 25 24
-----TENBITADR[9:8]
23 22 21 20 19 18 17 16
ADR[7:0]
15 14 13 12 11 10 9 8
SOAM CUP ACK PECEN SMHH SMDA SMBALERT
76543210
SWRST - - STREN GCMATCH SMATCH SMEN SEN
459
32072H–AVR32–10/2012
AT32UC3A3
Writing a one to this bit resets the TWIS.
• STREN : Clock Stretch Enable
0: Disables clock stretching if RHR/THR buffer full/empty. May cause over/underrun.
1: Enables clock stretching if RHR/THR buffer full/empty.
• GCMATCH: General Call Address Match
0: Causes the TWIS not to acknowledge the General Call Address.
1: Causes the TWIS to acknowledge the General Call Ad dress.
• SMATCH: Slave Address Match
0: Causes the TWIS not to acknowledge the Slave Address.
1: Causes the TWIS to acknowledge the Slave Address.
• SMEN: SMBus Mode Enable
0: Disables SMBus mode.
1: Enables SMBus mode.
• SEN: Slave Enab le
0: Disables the slave interface.
1: Enables the slave interface .
460
32072H–AVR32–10/2012
AT32UC3A3
22.9.2 NBYTES Register
Name: NBYTES
Access Type: Read/Write
Offset:0x04
Reset Value: 0x00000000
• NBYTES: Number of Bytes to Transfer
Writing to this field updates the NBYTES counter. The field can also be read to learn the progress of the transfer. NBYTES can
be incremented or decremented automatically by hardware.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
NBYTES
461
32072H–AVR32–10/2012
AT32UC3A3
22.9.3 Timing Register
Name: TR
Access Type: Read/Write
Offset:0x08
Reset Value: 0x00000000
• EXP: Clock Prescaler
Used to specify how to prescale the SMBus TLOWS counter. The counter is prescaled ac cord in g to the following formula:
• SUDAT: Data Setup Cycles
Non-prescaled clock cycles for data setup count. Used to time TSU_DAT. Data is driven SUDAT cycles after TWCK low detected.
This timing is used for timing the ACK/NAK bits, and any data bits driven in slave transmitter mode.
•TTOUT: SMBus T
TIMEOUT Cycles
Prescaled clock cycles used to time SMBus TTIMEOUT.
•TLOWS: SMBus T
LOW:SEXT Cycles
Prescaled clock cycles used to time SMBus TLOW:SEXT.
31 30 29 28 27 26 25 24
EXP ----
23 22 21 20 19 18 17 16
SUDAT
15 14 13 12 11 10 9 8
TTOUT
76543210
TLOWS
fPRESCALED fCLK_TWIS
2EXP 1+()
-------------------------=
462
32072H–AVR32–10/2012
AT32UC3A3
22.9.4 Receive Holding Register
Name: RHR
Access Type: Read-only
Offset:0x0C
Reset Value: 0x00000000
• RXDATA: Received Data Byte
When the RXRDY bit in the Status Register (SR) is one, this field contains a byte received from the TWI bus.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
RXDATA
463
32072H–AVR32–10/2012
AT32UC3A3
22.9.5 Transmit Holding Register
Name: THR
Access Type: Write-only
Offset:0x10
Reset Value: 0x00000000
• TXD ATA: Data Byte to Transmit
Write data to be transferred on the TWI bus here.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
TXDATA
464
32072H–AVR32–10/2012
AT32UC3A3
22.9.6 Packet Error Check Register
Name: PECR
Access Type: Read-only
Offset:0x14
Reset Value: 0x00000000
• PEC: Calculated PEC Value
The calculated PEC value. Updated automatically by ha rdware after each byte has been tr ansferred. Reset b y hard w are af ter a
ST OP condition. Provided if the user manually wishes to control when the PEC byte is transmitted, or wishes to access the PEC
value for other reasons. In ordinary operation, the PEC handling is done automatically by hardware.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
PEC
465
32072H–AVR32–10/2012
AT32UC3A3
22.9.7 Status Register
Name: SR
Access Type: Read-only
Offset:0x18
Reset Value: 0x000000002
• BTF: Byte Transfer Finished
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when byte transfer has completed.
• REP: Repeated Start Received
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when a REPEATED START condition is received.
• STO: Stop Received
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the STOP condition is received.
• SMBDAM: SMBus Default Address Match
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the received address matched the SMBus Default Address.
• SMBHHM: SMBus Host Header Address Match
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the received address matched the SMBus Host Header Address.
• SMBALERTM: SMBus Alert Respons e Address Match
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the received address matched the SMBus Alert Response Address.
• GCM: General Call Match
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the received address matched the General Call Address.
• SAM: Slave Address Match
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when the received address matched the Slave Address.
• BUSERR: Bus Error
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when a misplaced START or STOP condition has occurred .
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
BTF REP STO SMBDAM SMBHHM SMBALERTM GCM SAM
15 14 13 12 11 10 9 8
- BUSERR SMBPECERR SMBTOUT - - - NAK
76543210
ORUN URUN TRA - TCOMP SEN TXRDY RXRDY
466
32072H–AVR32–10/2012
AT32UC3A3
• SMBPECERR: SMBus PEC Error
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when a SMBus PEC error has occurred.
• SMBTOUT: SMBus Timeout
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when a SMBus timeout has occurred.
• NAK: NAK Received
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when a NAK was received from the ma ster during slave transmitter operation.
• ORUN: Overrun
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when an overrun has occurred in slave receiver mode. Can only occur if CR.STREN is zero.
• URUN: Underrun
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when an underrun has occurred in slave transmitter mode. Can only occur if CR.STREN is zero.
• TRA: Transmitter Mode
0: The slave is in slave receiver mode.
1: The slave is in slave transmitter mode.
• TCOMP: Transmission Complete
This bit is cleared when the corresponding bit in SCR is written to one.
This bit is set when transmission is complete. Set after receiving a STOP after being addressed.
• SEN: Slave Enab led
0: The slave inte rface is disabl ed .
1: The slave interface is enabled.
• TXRDY: TX Buffer Ready
0: The TX buffer is full and should not be written to.
1: The TX buffer is empty, and can accept new data.
• RXRDY: RX Buffer Ready
0: No RX data ready in RHR.
1: RX data is ready to be read from RHR.
467
32072H–AVR32–10/2012
AT32UC3A3
22.9.8 Interrupt Enable Register
Name: IER
Access Type: Write-only
Offset:0x1C
Reset Value: 0x00000000
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will write a one to the corresponding bit in IMR.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
BTF REP STO SMBDAM SMBHHM SMBALERTM GCM SAM
15 14 13 12 11 10 9 8
- BUSERR SMBPECERR SMBTOUT - - - NAK
76543210
ORUN URUN - - TCOMP - TXRDY RXRDY
468
32072H–AVR32–10/2012
AT32UC3A3
22.9.9 Interrupt Disable Register
Name: IDR
Access Type: Write-only
Offset:0x20
Reset Value: 0x00000000
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will clear the corresponding bit in IMR.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
BTF REP STO SMBDAM SMBHHM SMBALERTM GCM SAM
15 14 13 12 11 10 9 8
- BUSERR SMBPECERR SMBTOUT - - - NAK
76543210
ORUN URUN - - TCOMP - TXRDY RXRDY
469
32072H–AVR32–10/2012
AT32UC3A3
22.9.10 Interrupt Mask Register
Name: IMR
Access Type: Read-only
Offset:0x24
Reset Value: 0x00000000
0: The corresponding interr upt is disabled.
1: The corresponding interrupt is enabled.
This bit is cleared when the corresponding bit in IDR is written to one.
This bit is set when the corresponding bit in IER is wri tten to one.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
BTF REP STO SMBDAM SMBHHM SMBALERTM GCM SAM
15 14 13 12 11 10 9 8
- BUSERR SMBPECERR SMBTOUT - - - NAK
76543210
ORUN URUN - - TCOMP - TXRDY RXRDY
470
32072H–AVR32–10/2012
AT32UC3A3
22.9.11 Status Clear Register
Name: SCR
Access Type: Write-only
Offset:0x28
Reset Value: 0x00000000
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will clear the corresponding bit in SR and the correspondi ng interrupt request.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
BTF REP STO SMBDAM SMBHHM SMBALERTM GCM SAM
15 14 13 12 11 10 9 8
- BUSERR SMBPECERR SMBTOUT - - - NAK
76543210
ORUN URUN - - TCOMP - - -
471
32072H–AVR32–10/2012
AT32UC3A3
22.9.12 Parameter Register
Name: PR
Access Type: Read-only
Offset:0x2C
Reset Value: -
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
--------
472
32072H–AVR32–10/2012
AT32UC3A3
22.9.13 Version Register (VR)
Name: VR
Access Type: Read-only
Offset: 0x30
Reset Value: -
• VARIANT: Variant Number
Reserved. No functionality associated.
•VERSION: Version Number
Version number of the module. No functionality associated.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
---- VARIANT
15 14 13 12 11 10 9 8
---- VERSION [11:8]
76543210
VERSION [7:0]
473
32072H–AVR32–10/2012
AT32UC3A3
22.10 Module Configuration
The specific configuration for each TWIS instan ce is listed in the following tables.The module
bus clocks listed here are connected to the system bus clocks according to the table in the
Power Manager section.
Table 22-7. Module Clock Name
Module name Clock name
TWIS0 CLK_TWIS0
TWIS1 CLK_TWIS1
Table 22-8. Register Reset Values
Register Reset Value
VR 0x00000100
PR 0x00000000
474
32072H–AVR32–10/2012
AT32UC3A3
23. Two-wire Master Interface (TWIM)
Rev.: 1.0.0.1
23.1 Features •Compatible with I²C standard
– Multi-master support
– Transfer speeds of 100 and 400 kbit/s
– 7- and 10-bit and General Call addressing
•Compatible with SMBus standard
– Hardware Packet Error Checking (CRC) generation and verification with ACK control
– SMBus ALERT interface
– 25 ms clock low timeout delay
– 10 ms master cumulative clock low extend time
– 25 ms slave cumulative clock low e x te nd tim e
•Compatible with PMBus
•Compatible with Atmel Two-wire Interface Serial Memories
•DMA interface for reducing CPU load
•Arbitrary transfer lengths, including 0 data bytes
•Optional clock stretching if transmit or receive buffers not ready for data transfer
23.2 Overview The Atmel Tw o-wire Master In terface (TW IM) interconnects components on a unique two-wire
bus, made up of one clock line and one dat a line with speeds of up t o 400 kbit/s, based on a
byte-oriented transfer format. It can be used with any Atmel Two-wire Interface bus serial
EEPROM and I²C compatible device such as a real time clock (RTC), dot matrix/graphic LCD
controller, and temperature sensor, to name a few. The TWIM is always a bus master and can
transfer sequential or single bytes. Multiple master capability is supported. Arbitration of the bus
is performed internally and relinquishes the bus automatically if the bus arbitration is lo st.
A configurable ba ud ra te gener ator permits t he ou tput da ta r ate to be ada pted to a wid e ran ge of
core clock frequencies. Table 23-1 lists the compatibility level of the Atmel Two-wire Interface in
Master Mode and a full I²C compatible device.
Note: 1. START + b000000001 + Ack + Sr
Table 23-1. Atmel TWIM Compatibility with I²C Standard
I²C Standard Atmel TWIM
Standard-mode (100 kbit/s) Supported
Fast-mode (400 kbit/s) Supported
Fast-mode Plus (1 Mbit/s) Supported
7- or 10-bits Slave Addressing Supported
START BYTE(1) Not Supported
Repeated Start (Sr) Condition Supported
ACK and NACK Management Supported
Slope Control and Input Filtering (Fast mode) Supported
Clock Stretching Supported
475
32072H–AVR32–10/2012
AT32UC3A3
Table 23-2 lists the compatibility level of the Atmel Two-wire Master Interface and a full SMBus
compatible master.
23.3 List of Abbreviations
23.4 Block Diagram
Figure 23-1. Block Diagram
Table 23-2. Atmel TWIM Compatibility with SMBus Standard
SMBus Standard Atmel TWIM
Bus Timeouts Supported
Address Resolution Protocol Supported
Alert Supported
Host Functionality Supported
Packet Error Checking Supported
Table 23-3. Abbreviations
Abbreviation Description
TWI Two-wire Interface
A Acknowledge
NA Non Acknowledge
PStop
SStart
Sr Repeated Start
SADR Slave Address
ADR Any address except SADR
R Read
WWrite
Peripheral
Bus Bridge
Two-wire
Interface
I/O Controller
TWCK
TWD
INTC
TWI Interrupt
Power
Manager
CLK_TWIM
TWALM
476
32072H–AVR32–10/2012
AT32UC3A3
23.5 Application Block Diagram
Figure 23-2. Application Block Diagram
23.6 I/O Lines Description
23.7 Product Dependencies
In order to use t his modu le, othe r p arts o f th e syst em must be conf igu red cor re ctly, as de scr ibed
below.
23.7.1 I/O Lines TWD and TWCK are bidirectional lines, connected to a positive supply voltage via a current
source or pull-up resistor (see Figure 23-4 on page 478). When the bus is free, both lines are
high. The output stages of devices connected to the bus must have an open-drain or open-col-
lector to perform t he wired-AND function.
TWALM is used to implement the opt ional SMBus SMBALERT signal.
The TWALM, TWD, and TWCK pins may be multiplexed with I/O Controller lines. To enable the
TWIM, the user must perform the following steps:
• Program the I/O Controller to:
– Dedicate TWD, TWCK, and optionally TWALM as peripheral lines.
– Define TWD, TWCK, and optionally TWALM as open-drain.
23.7.2 Power Management
If the CPU enters a sleep mode that disables clocks used by the TWIM, the TWIM will stop func-
tioning and resume operation after th e system wakes up from sleep mode.
TWI
Master
TWD
TWCK
Atmel TWI
serial EEPROM I2C RTC I2C LCD
controller
I2C temp
sensor
Slave 2Slave 3Slave 4
VDD
Rp: pull-up value as given by the I2C Standard
TWALM
Slave 1
Rp Rp Rp
Table 23-4. I/O Lines Description
Pin Name Pin Description Type
TWD Two-wire Serial Data Input/Output
TWCK Two-wire Serial Clock Input/Output
TWALM SMBus SMBALERT Input/Output
477
32072H–AVR32–10/2012
AT32UC3A3
23.7.3 Clocks The clock for the TWIM bus interface (CLK_TWIM) is generat ed by the Power Manager. This
clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to dis-
able the TWIM before disabling the clock, to avoid freezing the TWIM in an undefined state.
23.7.4 DMA The TWIM DMA handshake interface is connected to the Peripheral DMA Controller. Using the
TWIM DMA functionality requires the Peripheral DMA Controller to be programmed after setting
up the TWIM.
23.7.5 Interrupts The TWIM interrupt request lines ar e connected to th e interrupt cont roller. Using th e TWIM inter-
rupts requires the interrupt controller to be programmed first.
23.7.6 Debug Operation
When an external d ebugger f orces t he CPU into debu g mode, the TWIM cont inues normal ope r-
ation. If the TWIM is configured in a way that requires it to be periodically serviced by the CPU
through interrupt s or similar, improper operation or data loss may result durin g debugging.
478
32072H–AVR32–10/2012
AT32UC3A3
23.8 Functional Description
23.8.1 Transfer Format
The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must
be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure
23-4).
Each transfer begins with a START condition and terminates with a STOP condition (see Figure
23-4).
• A high-to-low transition on the TWD line while TWCK is high defines the START condition.
• A low-to-high transition on the TWD line while TWCK is high defines a STOP condition.
Figure 23-3. START and STOP Conditions
Figure 23-4. Transfer Format
23.8.2 Operation The TWIM has two modes of operation:
• Master transmitter mode
• Master receiver mode
The master is the device which starts and stops a transfer and generates the TWCK clock.
These modes are described in the following chapters.
TWD
TWCK
Start Stop
TWD
TWCK
Start Address R/W Ack Data Ack Data Ack Stop
479
32072H–AVR32–10/2012
AT32UC3A3
23.8.2.1 Clock Generation
The Clock Waveform Generator Register (CWGR) is used to control the waveform of the TWCK
clock. CWGR must be written so that the desired TWI bus timings are generated. CWGR
describes bus timings as a function of cycles of a prescaled clock. The clock prescaling can be
selected through the Clock Prescaler field in CWGR (CWGR.EXP).
CWGR has the following fields:
LOW: Prescaled clock cycles in clock low count. Used to time TLOW and TBUF.
HIGH: Prescaled clock cycles in clock high coun t. Use d to time THIGH.
STASTO: Prescaled clock cycles in clock high count. Used to time THD_STA, TSU_STA, TSU_STO.
DATA: Prescaled clock cycles for data setup and hold count. Used to time THD_DAT, TSU_DAT.
EXP: Specifies the clock prescaler setting.
Note that the total clock low time generated is the sum of THD_DAT + TSU_DAT + TLOW.
Any slave or other bus master taking part in the transfer may extend the TWCK low period at any
time.
The TWIM hardware monitors the state of the TWCK line as req uired by the I²C specification.
The clock generation counters are started when a high/low level is detected on the TWCK line,
not when the T WIM hardware releas es/drives the TWCK line. This m eans that the CWGR set -
tings alone do not determine the TWCK frequency. The CWGR settings determine the clock low
time and the clock high t ime, but the TWCK rise a nd fall times ar e determined by the external cir-
cuitry (capacitive load, etc.) .
Figure 23-5. Bus Timing Diagram
fPRESCALER fCLK_TWIM
2EXP 1+()
--------------------------=
StHD:STA
tLOW
tSU:DAT
tHIGH
tHD:DAT
tLOW
P
tSU:STO
Sr
tSU:STA
tSU:DAT
480
32072H–AVR32–10/2012
AT32UC3A3
23.8.2.2 Setting up and Performing a Transfer
Operation of t he TWIM is mainly contr olled by the Con trol Register (CR) and the Co mmand Reg-
ister (CMDR). TWIM status is provided in the Status Register (SR). The following list presents
the main steps in a typical communication:
1. Before any tr ansfers can be performed, bus timings must be configured by writing to the
Clock Waveform Generator Register (CWGR). If operat ing in SMBus mode , the SMBu s
Timing Register (SMBTR) register must also be configured.
2. If the Peripheral DMA Controller is to be used for the transfers, it must be set up.
3. CMDR or NCMDR must be written with a value describing the tr ansfer to be performed.
The interrupt system can be set up to give interrupt requests on specific events or error condi-
tions in the SR, for example when the transfer is complete or if arbitration is lost. The Interru pt
Enable Register (I ER) and Interrupt Disable Register (I DR) can be written to specif y which bits in
the SR will generate interrupt requests.
The SR.BUSFREE bit is set when activity is completed on the two-wire bus. The SR.CRDY bit is
set when CMDR and/or NCMDR is ready to receive one or more commands.
The controller will refuse to start a new transfer while ANAK , DNAK, or ARBLST in the Status
Register (SR) is one. This is necessary to avoid a race when the software issues a continuation
of the current transfer at the same time as one of these errors happen. Also, if ANAK or DNAK
occurs, a STOP condition is sent automatically. The user will have to restart the transmission by
clearing the error bits in SR after resolving the cause for the NACK.
After a data or address NACK from the slave, a STOP will be transmitted automatically. Note
that the VALID bit in CMDR is NOT cleared in this case. If this transfer is to be discarded, the
VALID bit can be cleared manually allowing any command in NCMDR to be copied into CMDR.
When a data or address NACK is returned by the slave while the master is transmitting, it is pos-
sible that new data has already been written to the THR register. This data will be transferred out
as the first data byte of the next transfer. If this behavior is to be avoided, the safest approach is
to perform a software reset of the TWIM.
23.8.3 Master Transmitter Mode
A START condition is transmitted and master transmitter mode is initiated when the bus is free
and CMDR has been written with START=1 and READ=0. START and SADR+W will then be
transmitted. During the address acknowledge clock pulse (9th pulse), the master releases the
data line (HIGH), ena bling the slave to pull it down in order to acknow ledge the address. The
master polls the data line during this clock pulse and sets the Address Not Acknowledged bit
(ANAK) in the Status Register if no slave acknowledges the address.
After the address phase, the following is repeated:
while (NBYTES>0)
1. Wait until THR co ntains a valid data byte, stretching low period of TWCK. SR.TXRDY
indicates the state of THR. Software or the Peripheral DMA Controller must write the
data byte to THR.
2. Transmit this data byte
3. Decrement NBYTES
4. If (NBYTES==0) and STOP=1, transmit STOP condition
Writing CMDR with START=STOP=1 and NBYTES=0 will generate a trans mission with no data
bytes, ie START, SADR+W, STOP.
481
32072H–AVR32–10/2012
AT32UC3A3
TWI transfers require the slave to acknowle dge each received data byte. During the acknowl-
edge clock pulse (9th pulse), th e master releases th e data line (HIGH), enab ling the slave to pu ll
it down in order to generate the acknowledge. The master polls the data line during this clock
pulse and sets the Data Acknowledge bit (DNACK) in the Status Register if the slave does not
acknowledge the data byte. As with the other status bits, an interrupt can be generated if
enabled in the Interrupt Enable Register (IER) .
TXRDY is used as Transmit Ready for the Peripheral DMA Controller transmit channel.
The end of a command is marked when the TWIM sets th e SR.CCOMP bit. See Figu re 2 3-6 and
Figure 23-7.
Figure 23-6. Master Write with One Data Byte
Figure 23-7. Master Write with Multiple Data Bytes
23.8.4 Master Receiver Mode
A START condition is transmitted and master receiver mode is initiated wh en the bus is free and
CMDR has been written with START=1 and READ=1. START and SADR+R will then be trans-
mitted. During the address acknowledge clock pulse (9th pulse), the master releases the data
line (HIGH), enabling the slave to pull it down in order to acknowledge the address. The master
polls the data line during this clock pulse and sets the Address Not Acknowledged bit (ANAK) in
the Status Register if no slave acknowledges the address.
After the address phase, the following is repeated:
while (NBYTES>0)
TWD
SR.IDLE
TXRDY
Write THR (DATA)
NBYTES set to 1
STOP sent automatically
(ACK received and NBYTES=0)
SDADR WA DATA AP
TWD
SR.IDLE
TXRDY
Write THR
(DATAn)
NBYTES set to n
STOP sent automatically
(ACK received and NBYTES=0)
SDADR WA DATAn ADATAn+5 AA
DATAn+m P
Write THR
(DATAn+1)
Write THR
(DATAn+m)
Last data sent
482
32072H–AVR32–10/2012
AT32UC3A3
1. Wait unt il RHR is empty, str etching lo w period of TWCK. SR.RXRDY indicates the sta te
of RHR. Software or the Peripheral DMA Controlle r must read any data byte present in
RHR.
2. Release TWCK generating a clock that the slave uses to transmit a data byte.
3. Place the received data byte in RHR, set RXRDY.
4. If NBYTES=0, generate a NAK after the data byte, otherwise generate an ACK.
5. Decrement NBYTES
6. If (NBYTES==0) and STOP=1, transmit STOP condition.
Writing CMDR with START=STOP=1 and NBYTES=0 will generate a trans mission with no data
bytes, ie START, DADR+R, STOP
The TWI transfers require the master to acknowledge each received data byte. During the
acknowledge clock pulse (9th pulse), the slave releases the data line (HI GH), enabling the mas-
ter to pull it down in or der to generate the acknowledge. All data bytes except the last are
acknowledged by the mast er. No t acknowledg ing th e last byte info rms the sla ve that the tr ansfer
is finished.
RXRDY is used as Receive Ready for the Peripheral DMA Controller receive channel.
Figure 23-8. Master Read with One Data Byte
Figure 23-9. Master Read with Multiple Data Bytes
TWD
SR.IDLE
RXRDY
Write START &
STOP bit
NBYTES set to 1
Read RHR
SDADR R A DATA NP
TWD
SR.IDLE
RXRDY
Write START +
STOP bit
NBYTES set to m
SDADR R A DATAn ADATAn+m-1 AN
DATAn+m P
Read RHR
DATAn
DATAn+1
Read RHR
DATAn+m-2
Read RHR
DATAn+m-1
Read RHR
DATAn+m
Send STOP
When NBYTES=0
483
32072H–AVR32–10/2012
AT32UC3A3
23.8.5 Using the Peripheral DMA Controller
The use of the Peripheral DMA Controller significantly reduces the CPU load . The user can set
up ring buffer s for the Peripheral DMA Co ntroller, conta ining data to tran smit or free buffer space
to place received data.
To assure correct behavior, respect the following programm ing sequences:
23.8.5.1 Data Transmit with the Peripheral DMA Controller
1. Initialize the transmit Peripheral DMA Controller (memory pointers, size, etc.).
2. Configure the TWIM (ADR, NBYTES, etc.).
3. Start the transfer by enabling the Peripheral DMA Controller to transmit.
4. Wait for the Peripheral DMA Controller end-of-transmit flag.
5. Disable the Peripheral DMA Controller.
23.8.5.2 Data Receive with the Peripheral DMA Controller
1. Initialize the receive Peripheral DMA Contr oller (memory pointers, size, etc.).
2. Configure the TWIM (ADR, NBYTES, etc.).
3. Start the transfer by enabling the Peripheral DMA Controller to receive.
4. Wait for the Peripheral DMA Controller end-of-receive flag.
5. Disable the Peripheral DMA Controller.
23.8.6 Multi-master Mode
More than one master ma y access the bus at the same time without data corruption by using
arbitration.
Arbitration start s as soon as tw o or more master s place infor mation on the bus at the same time,
and stops (arbitration is lost) for the master that intends to send a logical one while the other
master sends a logical zero.
As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to
detect a STOP. The SR.ARBLST flag will be set. When the STOP is detected, the master who
lost arbitration may reinitiate the data transfer.
Arbitration is illustrated in Figure 23-11.
If the user starts a transfer and if the bus is busy, the TWIM automatically waits for a STOP con-
dition on the bus before initiating the transfer (see Figure 23-10).
Note: The state of the bus (busy or free) is not indicated in the user interface.
484
32072H–AVR32–10/2012
AT32UC3A3
Figure 23-10. User Sends Data While the Bus is Busy
Figure 23-11. Arbitration Cases
23.8.7 Combined Transfers
CMDR and NCMDR may be used to generate longer sequences of connected transfers, since
generation of START and/or STOP conditions is programmable on a per-command basis.
Writing NCMDR with START=1 when the previous transfer was written with STOP=0 will cause
a REPEATED START on the bus. The ability to generate such connected tr ansfers allows arbi-
trary transfer lengths, since it is legal to write CMDR with both START=0 and STOP=0. If this is
done in master receiver mode, the CMDR.ACKLAST bit must also be controlled.
TWCK
TWD DATA sent by a master
STOP sent by the master START sent by the TWI
DATA sent by the TWI
Bus is busy
Bus is free
A transfer is programmed
(DADR + W + START + Write THR) Transfer is initiated
TWI DATA transfer Transfer is kept
Bus is considered as free
TWCK
Bus is busy Bus is free
A transfer is programmed
(DADR + W + START + Write THR) Transfer is initiated
TWI DATA transfer Transfer is kept
Bus is considered as free
Data from a Master
Data from TWI S0
S00
1
1
1
ARBLST
S0
S00
1
1
1
TWD S00
1
11
11
Arbitration is lost
TWI stops sending data
P
S0
1
P0
11
11
Data from the master Data from the TWI
Arbitration is lost
The master stops sending data
Transfer is stopped Transfer is programmed again
(DADR + W + START + Write THR)
TWCK
TWD
485
32072H–AVR32–10/2012
AT32UC3A3
As for single data transfers, the TXRDY and RXRDY bits in the Status Register indicates when
data to transmit can be written to THR, or when received data can be read from RHR. Transfer
of data to THR and from RHR can also be done automatically by DMA, see Section 23.8.5
23.8.7.1 Write Followed by Write
Consider the following transfer:
START, DADR+W, DATA+A, DATA+A, REPSTART, DADR+W, DATA+A, DATA+A, STOP.
To generate this tran sf er :
1. Write CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=0.
2. Write NCMDR with START=1, STOP=1, DADR, NBYTES=2 and READ=0.
3. Wait until SR.TXRDY==1, then write first data byte to transfer to THR.
4. Wait until SR.TXRDY==1, then write second data byte to transfer to THR.
5. Wait until SR.TXRDY==1, then write third data byte to transfer to THR.
6. Wait until SR.TXRDY==1, then write fourth data byte to transfer to THR.
23.8.7.2 Read Followed by Read
Consider the following transfer:
START, DADR+R, DATA+A, DATA+NA, REPSTART, DADR+R, DATA+A, DATA+NA, STOP.
To generate this tran sf er :
1. Write CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=1.
2. Write NCMDR with START=1, STOP=1, DADR, NBYTES=2 and READ=1.
3. Wait until SR.RXRDY==1, then read first data byte received from RHR.
4. Wait until SR.RXRDY==1, then read second data byte received from RHR.
5. Wait until SR.RXRDY==1, then read third data byte received from RHR.
6. Wait until SR.RXRDY==1, then read fourth data byte received from RHR.
If combining several transfers, without any STOP or REPEATED START between them, remem-
ber to write a one t o th e ACKLAST bit in CMDR to ke ep fr om en din g e ach of t he pa rt ial tr ansf er s
with a NACK.
23.8.7.3 Write Followed by Read
Consider the following transfer:
START, DADR+W, DATA+A, DATA+A, REPSTART, DADR+R, DATA+A, DATA+NA, STOP.
486
32072H–AVR32–10/2012
AT32UC3A3
Figure 23-12. Combining a Write and Read Transfer
To generate this tran sf er :
1. Write CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=0.
2. Write NCMDR with START=1, STOP=1, DADR, NBYTES=2 and READ=1.
3. Wait until SR.TXRDY==1, then write first data byte to transfer to THR.
4. Wait until SR.TXRDY==1, then write second data byte to transfer to THR.
5. Wait until SR.RXRDY==1, then read first data byte received from RHR.
6. Wait until SR.RXRDY==1, then read second data byte received from RHR.
23.8.7.4 Read Followed by Write
Consider the following transfer:
START, DADR+R, DATA+A, DATA+NA, REPSTART, DADR+W, DATA+A, DATA+A, STOP.
Figure 23-13. Combining a Read and Write Transf er
To generate this tran sf er :
1. Write CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=1.
2. Write NCMDR with START=1, STOP=1, DADR, NBYTES=2 and READ=0.
3. Wait until SR.RXRDY==1, then read first data byte received from RHR.
4. Wait until SR.RXRDY==1, then read second data byte received from RHR.
5. Wait until SR.TXRDY==1, then write first data byte to transfer to THR.
6. Wait until SR.TXRDY==1, then write second data byte to transfer to THR.
TWD
SR.IDLE
TXRDY
SDADR WA DATA0 ADATA1 NA Sr DADR R A DATA2 ADATA3 A P
DATA0 DATA1
THR
RXRDY
1
RHR DATA3DATA2
TWD
SR.IDLE
TXRDY
SSADR RA DATA0 ADATA1 Sr DADR W A DATA2 ADATA3 NA P
DATA2
THR
RXRDY
RHR DATA3DATA0
A
1
2
DATA3
Read
TWI_RHR
487
32072H–AVR32–10/2012
AT32UC3A3
23.8.8 Ten Bit Addressing
Writing a one to CMDR.TENBIT enables 10-bit addressing in hardware. Performing transfers
with 10-bit addressing is similar to transfers with 7-bit addresses, except that bits 9:7 of
CMDR.SADR must be written appropriately.
In Figur e 23-14 and Figure 23-15, the grey boxes repres ent signals driven by the master, the
white boxes are driven by the slave.
23.8.8.1 Master Transmitter
To perform a master transmitter tr ansfer:
1. Write CMDR with TENBIT=1, REPSAME=0, READ=0, START=1, STOP=1 and the
desired addres s an d NBYTES value.
Figure 23-14. A Write Transfer with 10-bit Addressing
23.8.8.2 Master Receiver
When using master receiver mode with 10-bit addressing, CMDR.REPSAME must also be con-
trolled. CMDR.REPSAME must be writ ten to one when the addre ss pha se of the tr ansfer should
consist of only 1 address byte (the 11110xx byte) and not 2 address bytes. The I²C standard
specifies that such addressing is required when addressing a slave for reads using 10-bit
addressing.
To perform a master receiver transfer:
1. Write CMDR with TENBIT=1, REPSAME=0, READ=0, START=1, STOP=0,
NBYTES=0 and the desired address.
2. Write NCMDR with TENBIT=1, REPSAME=1, READ=1, START=1, STOP=1 and the
desired addres s an d NBYTES value.
Figure 23-15. A Read Transfer with 10-bit Addressing
23.8.9 SMBus Mode SMBus mode is enabled and disabled by writing to the SMEN an d SMDIS bits in CR. SMBus
mode operation is similar to I²C operation with the following exceptions:
• Only 7-bit addressing can be used.
• The SMBus standard describes a set of timeout v alues to ensure prog ress and throughput on
the bus. These timeout values must be written into SMBTR.
• Transmissions can optionally include a CRC byte, called Packet Error Check (PEC).
• A dedicated bus line, SMBALERT, allows a slave to get a master’s attention.
• A set of addresses have been reserved for protocol handling, such as Alert Response
Address (ARA) and Host Header (HH) Address.
SSLAVE ADDRESS
1st 7 bits PADATARW A1 A2
SLAVE ADDRESS
2nd byte AADATA
11110XX0
SSLAVE ADDRESS
1st 7 bits PADATARW A1 A2
SLAVE ADDRESS
2nd byte ADATA
11110XX0
Sr SLAVE ADDRESS
1st 7 bits RW A3
11110XX1
488
32072H–AVR32–10/2012
AT32UC3A3
23.8.9.1 Packet Error Checking
Each SMBus transfer can optionally end with a CRC byte, called the PEC byte. Writing a one to
CMDR.PECEN enables au to mati c PEC han dling in the cu rrent tran sf er. Tr ansf er s with and wit h-
out PEC can freely be intermixed in the same system, since some slaves may no t support PEC.
The PEC LFSR is always updated on every bit transmitted or received, so that PEC handling on
combined transfers will be correct.
In master transmitter mode, the maste r calculates a PEC value and tran smits it to t he slave after
all data bytes have been transmitted. Upon reception of this PEC byte, the slave will compare it
to the PEC value it has computed itself. If the values match, the data was received correctly, and
the slave will return an ACK to the master. If the PEC values differ, data was corrupted, and the
slave will return a NACK value. The DNAK bit in SR reflects the state of the last received
ACK/NACK value. Some slaves may not be able to ch eck the received PEC in time to return a
NACK if an error occurred. In this case, the slave should always return an ACK after the PEC
byte, and some other mechanism must be implemented to verify that the transmission was
received correctly.
In master receiver mode, the slave calculates a PEC value and transmits it to the master after all
data bytes have been transmitted. Upon reception of this PEC byte, the master will compare it to
the PEC value it h as co mpute d itse lf. If t he valu es m atch, the data wa s rec eived co rre ctly. If the
PEC values differ, data was corrupted, and SR.PECERR is set. In master re ceiver mode, the
PEC byte is always followed by a NACK transmitted by the master, since it is the last byte in the
transfer.
The PEC byte is automatically inserted in a master transmitter transmission if PEC is enabled
when NBYTES reaches zero. The PEC byte is identified in a master rece iver transmission if
PEC is enabled when NBYTES reaches zero. NBYTES must therefore be written with the total
number of data bytes in t he transmission, including the PEC byte.
In combined transfers, the PECEN bit should only be written to one in the last of the combined
transfers. Consid e r the following transfer:
S, ADR+W, COMMAND_BYTE, ACK, SR, ADR+R, DATA_BYTE, ACK, PEC_BYTE, NACK, P
This transfer is generated by writing two commands to the command registers. The first com-
mand is a write with NBYTES=1 and PECEN=0, and the second is a read with NBYTES=2 and
PECEN=1.
Writing a one to the STOP bit in CR will place a STOP condition on the bus after the current
byte. No PEC byte will be sent in this case.
23.8.9.2 Timeouts The TLOWS and TLOWM fields in SMBTR configure the SMBus timeout values. If a timeout
occurs, the master will transmit a STOP condition and leave the bus. The SR.TOUT bit is set.
23.8.9.3 SMBus ALERT Signal
A slave can get the master’s attention by pulling the TWALM line low. The TWIM will then set the
SR.SMBALERT bit. This can be set up to trigger an interru pt, and software can then take the
appropriate action, as defined in the SMBus standard.
489
32072H–AVR32–10/2012
AT32UC3A3
23.8.10 Identifying Bus Events
This chapter lists the different bus events, and how they affect bits in the TWIM registers. This is
intended to help writing drivers for the TWIM.
Table 23-5. Bus Events
Event Effect
Master transmitter has sent
a data byte SR.THR is cleared.
Master receiver has
received a data byte SR.RHR is set.
Start+Sadr sent, no ack
received from slave
SR.ANAK is set.
SR.CCOMP not set.
CMDR.VALID remains set.
STOP automatically transmitted on bus.
Data byte sent to slave, no
ack received from slave
SR.DNAK is set.
SR.CCOMP not set.
CMDR.VALID remains set.
STOP automatically transmitted on bus.
Arbitration lost
SR.ARBLST is set.
SR.CCOMP not set.
CMDR.VALID remains set.
TWCK and TWD immediately released to a pulled-up state.
SMBus Alert received SR.SM BALERT is set.
SMBus timeout received
SR.SMBTOUT is set.
SR.CCOMP not set.
CMDR.VALID remains set.
STOP automatically transmitted on bus.
Master transmitter receives
SMBus PEC Error
SR.DNAK is set.
SR.CCOMP not set.
CMDR.VALID remains set.
STOP automatically transmitted on bus.
Master receiver discovers
SMBus PEC Error
SR.PECERR is set.
SR.CCOMP not set.
CMDR.VALID remains set.
STOP automatically transmitted on bus.
CR.STOP is written by user
SR.STOP is set.
SR.CCOMP set.
CMDR.VALID remains set.
STOP transmitted on bus after current byte transf er has finished.
490
32072H–AVR32–10/2012
AT32UC3A3
23.9 User Interface
Note: 1. The reset values for these registers are device specific. Please refer to the Module Configuration section at the end of this
chapter.
Table 23-6. TWIM Register Memory Map
Offset Register Registe r Name Access Reset
0x00 Control Register CR Write-only 0x00000000
0x04 Clock Waveform Generator Reg ister CWGR Read/Write 0x00000000
0x08 SMBus Timing Register SMBTR Read/Write 0x00000000
0x0C Command Register CMDR Read/Write 0x00000000
0x10 Next Command Register NCMDR Read/Write 0x00000000
0x14 Receive Holding Register RHR Read-only 0x00000000
0x18 Transmit Hold ing Register THR Write-o nly 0x00000000
0x1C Statu s Register SR Read-only 0x000 00002
0x20 Interrupt Enable Register IER Write-only 0x00000000
0x24 Interrupt Disable Register IDR Write-only 0x00000000
0x28 Interrupt Mask Register IMR Read-only 0x00000000
0x2C Status Clear Register SCR Write-only 0x00000000
0x30 Parameter Register PR Read-only -(1)
0x34 Version Register VR Read-only -(1)
491
32072H–AVR32–10/2012
AT32UC3A3
23.9.1 Control Register
Name: CR
Access Type: Write-only
Offset: 0x00
Reset Value: 0x00000000
• STOP: Stop the Current Transfer
Writing a one to this bit terminates the current transfer, sending a STOP condition after the shifter has become idle. If there are
additional pending transfers, they will ha v e to be e xplicitly restarted by software after the ST OP condition has been successfully
sent.
Writing a zero to this bit has no effect.
• SWRST : Software Reset
If the TWIM master interface is enabled, writing a one to this bit resets the TWIM. All transfers are halted immediately, possibly
violating the bus semantics.
If the TWIM master interface is not enabled, it must first be enabled before writing a one to this bit.
Writing a zero to this bit has no effect.
• SMDIS: SMBus Disable
Writing a one to this bit disables SMBus mode.
Writing a zero to this bit has no effect.
• SMEN: SMBus Enable
Writing a one to this bit enables SMBus mode.
Writing a zero to this bit has no effect.
• MDIS: Master Disable
Writing a one to this bit disables the master interface.
Writing a zero to this bit has no effect.
• MEN: Master Enable
Writing a one to this bit enables the master interface.
Writing a zero to this bit has no effect.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
-------STOP
76543210
SWRST - SMDIS SMEN - - MDIS MEN
492
32072H–AVR32–10/2012
AT32UC3A3
23.9.2 Clock Waveform Generator Register
Name: CWGR
Access Type: Read/Write
Offset: 0x04
Reset Value: 0x00000000
• EXP: Clock Prescaler
Used to specify how to prescale the TWCK clock. Counters are prescaled according to the following formula
• DATA: Data Setup and Hold Cycl es
Clock cycles for data setup and hold count. Prescaled by CWGR.EXP. Used to time THD_DAT, TSU_DAT.
• STASTO: START and STOP Cycles
Clock cycles in clock high count. Prescaled by CWGR.EXP. Used to time THD_STA, TSU_STA, TSU_STO
• HIGH: Clock High Cycles
Clock cycles in clock high count. Prescaled by CWGR.EXP. Used to time THIGH.
• LOW: Clock Low Cyc les
Clock cycles in clock low count. Prescaled by CWGR.EXP. Used to time TLOW, TBUF.
31 30 29 28 27 26 25 24
- EXP DATA
23 22 21 20 19 18 17 16
STASTO
15 14 13 12 11 10 9 8
HIGH
76543210
LOW
fPRESCALER fCLK_TWIM
2EXP 1+()
--------------------------=
493
32072H–AVR32–10/2012
AT32UC3A3
23.9.3 SMBus Timing Register
Name: SMBTR
Access Type: Read/Write
Offset: 0x08
Reset Value: 0x00000000
• EXP: SMBus Timeout Clock Prescaler
Used to specify how to prescale the TIM and TLOWM counters in SMBTR. Counters are presca led according to the following
formula
• THMAX: Clock High Maximum Cycles
Clock cycles in clock high maximum count. Prescaled by SMBTR.EXP. Used for bus free detection. Used to time THIGH:MAX.
NOTE: Uses the prescaler specified by CWGR, NOT the prescaler specified by SMBTR.
• TLOWM: Master Clock Stretch Maximum Cycles
Clock cycles in master maximum clock stretch count. Prescaled by SMBTR.EXP. Used to time TLOW:MEXT
• TLOWS: Slave Clock Stretch Maximum Cycles
Clock cycles in slave maximum clock stretch count. Prescaled by SMBTR.EXP. Used to time TLOW:SEXT.
31 30 29 28 27 26 25 24
EXP ----
23 22 21 20 19 18 17 16
THMAX
15 14 13 12 11 10 9 8
TLOWM
76543210
TLOWS
fprescaled SMBus,
fCLKTWIM
2EXP 1+()
------------------------=
494
32072H–AVR32–10/2012
AT32UC3A3
23.9.4 Command Regi st er
Name: CMDR
Access Type: Read/Write
Offset: 0x0C
Reset Value: 0x00000000
• ACKLAST: ACK Last Master RX Byte
0: Causes the last byte in master receive mode (when NBYTES has reached 0) to be NACKed. This is the standard way of
ending a master receiver tr ansfer.
1: Causes the last byte in master receive mode (when NBYTES has reached 0) to be ACKed. Used for performing linked
transfers in master receiver mode with no STOP or REPEATED START between the subtransfers. This is needed when more
than 255 bytes are to be received in one single transmission.
• PECEN: Packet Error Checking Enable
0: Causes the transf er not to use PEC byte v erification. The PEC LFSR is still updated for e v ery bit transmitted or received. Must
be used if SMBus mode is disabled.
1: Causes the transfer to use PEC. PEC byte generation (if master transmitter) or PEC byte verification (if master receiver) will
be performed.
• NBYTES: Number of Data Bytes in Transfer
The number of data bytes in the transfer. After the sp ecified number of bytes have been transferred, a STOP condition is
transmitted if CMDR.STOP is one. In SMBus mode, if PEC is used, NBYTES in cl u de s th e PEC byte, i.e. there are NBYTES-1
data bytes and a PEC byte.
• VALID: CMDR Valid
0: Indicates that CMDR does not contain a valid command.
1: Indicates that CMDR contains a valid command. This bit is cleared when the command is finished.
• STOP: Send STOP Condition
0: Do not transmit a STOP condition af ter the data bytes have been transmitted.
1: Transmit a STOP condition after the data bytes have been transmitted.
• START: Send START Condition
0: The transfer in CMDR should not commence with a START or REPEATED START condition.
1: The transf er in CMDR should commence with a STAR T or REPEATED START condition. If the bus is free when the command
is executed, a START condition is used. If the bus is busy, a REPEATED START is used.
• REPSAME: Transfer is to Same Address as Previous Address
Only used in 10-bit addressing mode, always wri te to 0 in 7-bit addressing mode.
31 30 29 28 27 26 25 24
- - - - ACKLAST PECEN
23 22 21 20 19 18 17 16
NBYTES
15 14 13 12 11 10 9 8
VALID STOP START REPSAME TENBIT SADR[9:7]
76543210
SADR[6:0] READ
495
32072H–AVR32–10/2012
AT32UC3A3
Write this bit to one if the command in CMDR performs a repeated start to the same slav e address as addressed in the previous
transf er in order to enter master receiver mode.
Write this bit to zero otherwise.
• TENBIT : Ten Bit Addressing Mode
0: Use 7-bit addressing mode.
1: Use 10-bit addressing mode. Must not be used when the TWIM is in SMBus mode.
• SADR: Slave Address
Address of the slave involved in the transfer. Bits 9-7 are don’t care if 7-bit addressing is used.
• READ: Tr ansfer Direction
0: Allow the master to transmit data.
1: Allow the master to receive data.
496
32072H–AVR32–10/2012
AT32UC3A3
23.9.5 Next Command Register
Name: NCMDR
Access Type: Read/Write
Offset: 0x10
Reset Value: 0x00000000
This register is identical to CMDR. When the VALID bit in CMDR becomes 0, the content of NCMDR is copied into CMDR,
clearing the VALID bit in NCMDR. If the VALID bit in CMDR is cleared when NCMDR is written, the content is copied
immediately.
31 30 29 28 27 26 25 24
- - - - ACKLAST PECEN
23 22 21 20 19 18 17 16
NBYTES
15 14 13 12 11 10 9 8
VALID STOP START REPSAME TENBIT SADR[9:7]
76543210
SADR[6:0] READ
497
32072H–AVR32–10/2012
AT32UC3A3
23.9.6 Receive Holding Register
Name: RHR
Access Type: Read-only
Offset: 0x14
Reset Value: 0x00000000
• RXDATA: Received Data
When the RXRDY bit in the Status Register (SR) is one, this field contains a byte received from the TWI bus.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
RXDATA
498
32072H–AVR32–10/2012
AT32UC3A3
23.9.7 Transmit Holding Register
Name: THR
Access Type: Write-only
Offset: 0x18
Reset Value: 0x00000000
• TXDATA: Data to Transmit
Write data to be transferred on the TWI bus here.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
TXDATA
499
32072H–AVR32–10/2012
AT32UC3A3
23.9.8 Status Register
Name: SR
Access Type: Read-only
Offset: 0x1C
Reset Value: 0x00000002
• MENB: Master Interface Enable
0: Master interface is disabled.
1: Master interface is enabled.
• STOP: Stop Request Accepted
This bit is one when a STOP request caused by writing a one to CR.STOP has been accepted, and transfer has stopped.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
• PECERR: PEC Error
This bit is one when a SMBus PEC error occurred.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
•TOUT: Timeout
This bit is one when a SMBus timeout occurred.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
• SMBALERT: SMBus Alert
This bit is one when an SMBus Alert was received.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
• ARBLST: Arbitration Lost
This bit is one when the actual state of the SDA line did not correspo nd to the data driven onto it, indicating a higher-pr iority
transmission in progress by a different master.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
• DNAK: NAK in Data Phase Received
This bit is one when no ACK was received form slave durin g data transmission.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
• ANAK: NAK in Address Phase Received
This bit is one when no ACK was received from slave during address phase
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
• BUSFREE: Two-wire Bus is Free
This bit is one when activity has comple ted on the two-wire bus.
Otherwise, this bit is cleared.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
-------MENB
15 14 13 12 11 10 9 8
- STOP PECERR TOUT SMBALERT ARBLST DNAK ANAK
76543210
- - BUSFREE IDLE CCOMP CRDY TXRDY RXRDY
500
32072H–AVR32–10/2012
AT32UC3A3
• IDLE: Master Interface is Idle
This bit is one when no command is in progress, and no command waiting to be issued.
Otherwise, this bit is cleared.
• CCOMP: Command Complete
This bit is one when the current command has completed successfully.
This bit is zero if the command failed due to conditions such as a NAK receved from slave.
This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
• CRDY: Ready for More Commands
This bit is one when CMDR and/or NCMDR is ready to receive one or more commands.
This bit is cleared when this is no longer true.
• TXRDY: THR Data Ready
This bit is one when THR is ready for one or more data bytes.
This bit is cleared when this is no longer true (i.e. THR is full or transmission has stopped).
• RXRDY: RHR Data Ready
This bit is one when RX data are ready to be read from RHR.
This bit is cleared when this is no longer true.
501
32072H–AVR32–10/2012
AT32UC3A3
23.9.9 Interrupt Enable Register
Name: IER
Access Type: Write-only
Offset: 0x20
Reset Value: 0x00000000
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will set the corresponding bit in IMR
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
- - PECERR TOUT SMBALERT ARBLST DNAK ANAK
76543210
- - BUSFREE IDLE CCOMP CRDY TXRDY RXRDY
502
32072H–AVR32–10/2012
AT32UC3A3
23.9.10 Interrupt Disable Register
Name: IDR
Access Type: Write-only
Offset: 0x24
Reset Value: 0x00000000
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will clear the corresponding bit in IMR
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
- - PECERR TOUT SMBALERT ARBLST DNAK ANAK
76543210
- - BUSFREE IDLE CCOMP CRDY TXRDY RXRDY
503
32072H–AVR32–10/2012
AT32UC3A3
23.9.11 Interrupt Mask Register
Name: IMR
Access Type: Read-only
Offset: 0x28
Reset Value: 0x00000000
0: The corresponding interr upt is disabled.
1: The corresponding interrupt is enabled.
This bit is cleared when the corresponding bit in IDR is written to one.
This bit is set when the corresponding bit in IER is wri tten to one.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
- - PECERR TOUT SMBALERT ARBLST DNAK ANAK
76543210
- - BUSFREE IDLE CCOMP CRDY TXRDY RXRDY
504
32072H–AVR32–10/2012
AT32UC3A3
23.9.12 Status Clear Register
Name: SCR
Access Type: Write-only
Offset: 0x2C
Reset Value: 0x00000000
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will clear the corresponding bit in SR and the correspondi ng interrupt request.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
- STOP PECERR TOUT SMBALERT ARBLST DNAK ANAK
76543210
----CCOMP---
505
32072H–AVR32–10/2012
AT32UC3A3
23.9.13 Parameter Register (PR)
Name: PR
Access Type: Read-only
Offset: 0x30
Reset Value: -
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
--------
506
32072H–AVR32–10/2012
AT32UC3A3
23.9.14 Version Register (VR)
Name: VR
Access Type: Read-only
Offset: 0x34
Reset Value: -
• VARIANT: Variant Number
Reserved. No functionality associated.
•VERSION: Version Number
Version number of the module. No functionality associated.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
---- VARIANT
15 14 13 12 11 10 9 8
---- VERSION [11:8]
76543210
VERSION [7:0]
507
32072H–AVR32–10/2012
AT32UC3A3
23.10 Module Configuration
The specific configuration for each TWIM instance is listed in the following tables.The module
bus clocks listed here are connected to the system bus clocks according to the table in the
Power Manager section.
Table 23-7. Module Clock Name
Module name Clock name
TWIM0 CLK_TWIM0
TWIM1 CLK_TWIM1
Table 23-8. Register Reset Values
Register Reset Value
VR 0x00000100
PR 0x00000000
508
32072H–AVR32–10/2012
AT32UC3A3
24. Synchronous Serial Controller (SSC)
Rev: 3.2.0.2
24.1 Features •Provides serial synchronous communication links used in audio and telecom applications
•Independent receiver and transmitter, common clock divider
•Interfaced with two Peripheral DMA Controller channels to reduce processor overhead
•Configurable frame sync and data length
•Receiver and transmitter can be configured to start automatically or on detection of different
events on the frame sync signal
•Receiver and transmitter include a data signal, a cloc k signal and a frame synchronization signal
24.2 Overview The Synchronous Serial Controller (SSC) provides a synchronous communication link with
external devices. It supports many serial synchronous communication protocols generally used
in audio and telecom app lications such as I2S, Short Frame Syn c, Long Frame Sync, etc.
The SSC consists of a receiver, a tra nsmitter, and a common clock divider. Both th e receiver
and the transmitter interface with three signals:
• the TX_DATA/RX_DATA signal for data
• the TX_CLOCK/RX_CLOCK signal for the clock
• the TX_FRAME_SYNC/RX_FRAME_SYNC signal for the frame synchronization
The transfers can be programmed to start automatically or on different events detected on the
Frame Sync signal.
The SSC’s high-level of programmability and its two dedicated Peripheral DMA Controller chan-
nels of up to 32 bits permit a continuous high bit rate data transfer without processor
intervention.
Featuring connection to two Peripheral DMA Controller channels, the SSC permits interfacing
with low processor overhead to the following:
• CODEC’s in master or slave mode
• DAC through dedicated serial interface, particularly I2S
• Magnetic card reader
509
32072H–AVR32–10/2012
AT32UC3A3
24.3 Block Diagram
Figure 24-1. SSC Block Diagram
24.4 Application Block Diagram
Figure 24-2. SSC Application Block Diagram
SSC Interface
Peripheral DMA
Control ler
Peripheral Bus
Bridge
High
Speed
Bus
Peripheral
Bus
Power
Manager
CLK_SSC
I/O
Controller
Interrupt Control
SSC Interrupt
TX_FRAME_SYNC
RX_FRAME_
SYN
C
TX_CLOCK
RX_CLOCK
RX_DATA
TX_DATA
Test
Management
Line Interface
Interrupt
Management
Frame
Management
Time Slot
Management
SSC
Power
Management
CodecSerial AUDIO
OS or RTOS Driver
510
32072H–AVR32–10/2012
AT32UC3A3
24.5 I/O Lines Description
24.6 Product Dependencies
In order to use t his modu le, othe r p arts o f th e syst em must be conf igu red cor re ctly, as de scr ibed
below.
24.6.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with I/O lines.
Before using the SSC receiver, the I/O Controller must be configured to dedicate the SSC
receiver I/O lines to the SSC peripheral mode.
Before using the SSC transmitter, the I/O Controller must be configured to dedicate the SSC
transmitter I/O lines to the SSC peripheral mode.
24.6.2 Clocks The clock for the SSC bus interface (CLK_SSC) is generated by the Power Manager. This clock
is enabled at reset, and can be disabled in t he Power Ma nager. It is r ecommended to di sable the
SSC before disabling the clock, to avoid freezing the SSC in an undefined state.
24.6.3 Interrupts The SSC interrup t request line is connected to the interrupt contr oller. Using the SSC interrupt
requires the interrupt controller to be programmed first.
24.7 Functional Description
This chapter contains the functional description of the following: SSC functiona l block, clock
management, data framing format, start, tr ansmitter, receiver, and frame sync.
The receiver and the transmitter operate separately. However, they can work synchronously by
programming th e receiver to use t he transmit clock and/or to st art a data transfe r when transmis-
sion starts. Alternatively, this can be done by programming the transmitter to use the receive
clock and/or to start a data transfer when reception starts. The transmitter and the receiver can
be programmed to operate with the clock signals provided on either the TX_CLOCK or
RX_CLOCK pins. This allows the SSC to support many slave-mode data transfers. The maxi-
mum clock speed allowed on the TX_CLOCK and RX_CLOCK pins is CLK_SSC divided by two.
Table 24-1. I/O Lines Descrip tion
Pin Name Pin Description Type
RX_FRAME_SYNC Receiver Frame Synchro Input/Output
RX_CLOCK Receiver Cloc k Input/Output
RX_DATA Receiver Data Input
TX_FRAME_SYNC Transmitter Frame Synchro Input/Output
TX_CLOCK Transmitter Clock Input/Output
TX_DATA Transmitter Data Output
511
32072H–AVR32–10/2012
AT32UC3A3
Figure 24-3. SSC Functional Block Diagram
24.7.1 Clock Management
The transmitter clock can be generated by:
• an extern al clock received on the TX_CLOCK pin
• the receiver clock
• the internal clock divider
The receiver clock can be generated by:
• an external clock received on the RX_CLOCK pin
• the transmitter clock
• the internal clock divider
Furthermore, the transmitter block can generate an external clock on the TX_CLOCK pin, and
the receiver block can generat e an external clock on the RX_CLOCK pin.
This allows the SSC to support many Master and Slave Mode data transfer s.
Clock
Divider
User
Interface
Peripheral
Bus
CLK_SSC
Interrupt Control
Start
Selector Receive Shift Register
Receive Holding
Register
Receive Sync
Holding Register
DMA
Interrupt Controller
RX_FRAME_SYNC
RX_DATA
RX_CLOCK
Frame Sync
Controller
Clock Output
Controller
Receive Clock
Controller
Transmit Holding
Register
Transmit Sync
Holding Register
Transmit Shift Register
Frame Sync
Controller
Clock Output
Controller
Transmit Clock
Controller
Start
Selector
TX_FRAME_SYNC
RX_FRAME_SYNC
TX_CLOCK Input
Transmitter
TX_DMA
Load Shift
RX clock
TX clock
TX_CLOCK
TX_FRAME_SYNC
TX_DATA
Receiver
RX clock
RX_CLOCK
Input
TX clock
TX_FRAME_SYNC
RX_FRAME_SYNC
RX_DMA
Load Shift
512
32072H–AVR32–10/2012
AT32UC3A3
24.7.1.1 Clock divider
Figure 24-4. Divided Clock Block Diagram
The peripheral clock divider is determined by the 12-bit Clock Divider field (its maximal value is
4095) in the Clock Mode Register (CMR.DIV), allo wing a periphe ral clock division by up to 8190.
The divided clock is provided to both the receiver and transmitter. When this field is written to
zero, the clock divider is not used and remains inactive.
When CMR.DIV is written to a value equal to or greater than one, the divided clock has a fre-
quency of CLK_SSC divided by two times CMR.DIV. Each level of the divided clock has a
duration of the peripheral clock multiplied by CMR.DIV. This ensures a 50% duty cycle for the
divided clock regardless of whether the CMR.DIV value is even or odd.
Figure 24-5. Divided Clock Generation
24.7.1.2 Transmitter clock management
The transmitter clock is g enerated from the receiver clock, t he divider clock, or an external clock
scanned on the TX_CLOCK pin. The transmitter clock is selected by writing to the Transmit
Clock Selection field in the Transmit Clock Mode Register (TCMR.CKS). The transmit clock can
Table 24-2. Range of Clock Divider
Maximum Minimum
CLK_SSC / 2 CLK_SSC / 8190
CMR
/ 2
CLK_SSC Divided Clock
12-bit Counter
Clock Divider
CLK_SSC
Divided Clock
DIV = 1
CLK_SSC
Divided Clock
DIV = 3
Divided Clock Frequency = CLK_SSC/2
Divided Clock Frequency = CLK_SSC/6
513
32072H–AVR32–10/2012
AT32UC3A3
be inverted independently by writing a one to the Transmit Clock Inversion bit in TCMR
(TCMR.CKI).
The transmitter can also drive the TX_CLOCK pin continuously or be limited to the actua l data
transfer, depending on the Transmit Clock Output Mode Selection field in the TCMR register
(TCMR.CKO). The TCMR.CKI bit has no effect on the clock outputs.
Writing 0b10 to the TCMR.C KS field to select TX_CLOCK pi n and 0b001 to the TCMR.CKO field
to select Continuous Transmit Clock can lead to unpredictable results.
Figure 24-6. Transmitter Clock Management
24.7.1.3 Receiver clock management
The receiver clock is generated from the transmitter clock, the divider clock, or an external clock
scanned on the RX_CLOCK pin. The receive clock is selected by writing to the Receive Clock
Selection field in the Receive Clock Mode Register (RCMR.CKS). The receive clock can be
inverted independently by writing a one to the Receive Clock Inversion bit in RCMR
(RCMR.CKI).
The receiver can also drive the RX_CLOCK pin continuously or be limited to the actua l data
transfer, depending on the Receive Clock Outp ut Mode Selection field in the RCMR register
(RCMR.CKO). The RCMR.CKI bit has no effect on the clock outputs.
Writing 0b10 to the RCMR.CKS field to select RX_CLOCK pin and 0b001 to the RCMR.CKO
field to select Continuous Receive Clock can lead to unpredictable results.
TX_CLOCK
Receiver
Clock
Divider
Clock
CKO Data Transfer
Tri-state
Controller
INV
MUX
CKS
MUX
Tri-state
Controller
CKI CKG
Transmitter
Clock
Clock
Output
514
32072H–AVR32–10/2012
AT32UC3A3
Figure 24-7. Receiver Clock Management
24.7.1.4 Serial clock ratio considerations
The transmitter and the receiver can be programmed to operate with the clock signals provided
on either the TX_CLOCK or RX_CL OCK pins. This allows the SSC to supp or t man y slave -mode
data transfers. In this case, the maximum clock speed allowed on the RX_CLOCK pin is:
– CLK_SSC divided by two if RX_FRAME_SYNC is input.
– CLK_SSC divided by three if RX_FRAME_SYNC is output.
In addition, the maximum clock speed allowed on the TX_CLOCK pin is:
– CLK_SSC divided by six if TX_FRAME_SYNC is input.
– CLK_SSC divided by two if TX_FRAME_SYNC is output.
24.7.2 Transmitter Operations
A transmitted frame is trig gered by a start event an d can be followed by synchronization data
before data tran sm ission.
The start event is configured by writing to the TCMR register. See Section 24.7.4.
The frame synchronization is configured by writing to the Transmit Frame Mode Register
(TFMR). See Section 24.7.5 .
To transmit data, the transmitter uses a shift register clocked by the transmitter clock signal and
the start mode selected in the TCMR regist er. Data is written by the user to the Tra nsmit Holding
Register (THR) then transferred to the shift register according to the data format selected.
When both the THR and the transmit shift registers are empty, the Transmit Empty bit is set in
the Status Register (SR.TXEMPTY). When the THR register is transferred in the transmit shift
register, the Transmit Ready bit is set in the SR register (SR. TXREADY) and ad ditiona l data can
be loaded in the THR register.
Divider
Clock
RX_CLOCK
Transmitter
Clock
MUX Tri-state
Controller
CKO Data Transfer
INV
MUX
CKI
Tri-state
Controller
CKG
Receiver
Clock
Clock
Output
CKS
515
32072H–AVR32–10/2012
AT32UC3A3
Figure 24-8. Transmitter Block Diagram
24.7.3 Rece iv e r Oper at ions
A received frame is triggered by a start event and can be followed by synchronization data
before data tran sm ission.
The start event is configured by writing to the RCMR regist er. See Section 24.7.4.
The frame synchronization is configured by writing to the Receive Frame Mode Register
(RFMR). See Section 24.7.5.
The receiver uses a shift register clocked by the receiver clock signal and the start mode
selected in the RCMR register. The data is transferred from the shift register depending on the
data format selected.
When the receiver shift register is full, the SSC transfers this data in the Receive Holding Regis-
ter (RHR), the Receive Re ady bit is set in the SR register (SR.RXREADY) and the data can be
read in the RHR register. If another transfer occurs before a read of the RHR register, the
Receive Overrun bit is set in the SR register (SR. OVRUN) and the receiver shift reg ister is trans-
ferred to the RHR register.
TFMR.DATDEF
TFMR.MSBF 0
1
Transmit Shift Register
01
THR TSHR TFMR.FSLEN
TCMR.STTDLY
TFMR.FSDEN
TFMR.DATNB
CR.TXEN
CR.TXDIS
SR.TXEN
TX_DATA
TFMR.DATLEN
TCMR.STTDLY
TFMR.FSDEN
Start
Selector
RX_FRAME_SYNC
TX_FRAME_SYNC
Transmitter Clock
516
32072H–AVR32–10/2012
AT32UC3A3
Figure 24-9. Receiver Block Diagram
24.7.4 Start The transmitter and receiver can both be programmed to start their operations when an event
occurs, respectively in the Transmit Start Selection field of the TCMR register (TCMR.START)
and in the Receive Start Selection field of the RCMR register (RCMR.START).
Under the following cond itions the start event is independently programmable:
• Continuous: in this case, the transmission starts as soon as a word is written to the THR
register and the reception starts as soon as the receiver is enabled
• Synchronously with the transmitter/r eceiver
• On detection of a falling/rising edge on TX_FRAME_SYNC/RX_FRAME_SYNC
• On detection of a low/high level on TX_FRAME_SYNC/RX_FRAME_SYNC
• On detection of a level change or an edge on TX_FRAME_SYNC/RX_FRAME_SYNC
A start can be programmed in the same manner on either side of the Transmit/Receive Clock
Mode Register (TCMR/RCM R). Thus, the start could be on TX_F RAME_SYNC (transmit) or
RX_FRAME_SYNC (receive).
Moreover, the receiver can start when data is detected in the bit stream with the compare func-
tions. See Section 24.7.6 for more details on receive compare modes.
Detection on TX_FRAME_SYNC input/output is done by the Transmit Frame Sync Output
Selection field in the TFMR register (TFMR.FSOS). Similarly, detection on RX_FRAME_SYNC
input/output is done by the Receive Frame Output Sync Selection field in the RFMR register
(RFMR.FSOS).
Divider
Clock
RX_CLOCK
Transmitter
Clock
MUX Tri-state
Controller
CKO Data Transfer
INV
MUX
CKI
Tri-state
Controller
CKG
Receiver
Clock
Clock
Output
CKS
517
32072H–AVR32–10/2012
AT32UC3A3
Figure 24-10. Transmit Start Mode
Figure 24-11. Receive Pulse/Edge Start Modes
XB0B1
B1B0
B0 B1
B1B0
B0 B1 B0 B1
B0 B1B1
B0
X
X
X
X
X
TX_DATA (Output)
Start= Any Edge on TX_FRAME_SYNC
TX_DATA (Output)
Start= Level Change on TX_FRAME_SYNC
TX_DATA (Output)
Start= Rising Edge on TX_FRAME_SYNC
TX_DATA (Output)
Start= Falling Edge on TX_FRAME_SYNC
TX_DATA (Output)
Start= High Level on TX_FRAME_SYNC
TX_DATA (Output)
Start= Low Level on TX_FRAME_SYNC
TX_FRAME_SYNC (Input)
TX_CLOCK (Input)
STTDLY
STTDLY
STTDLY
STTDLY
STTDLY
STTDLY
RX_CLOCK
RX_FRAME_SYNC (Input)
RX_DATA (Input)
Start = High Level on RX_FRAME_SYNC
RX_DATA (Input)
Start = Falling Edge on RX_FRAME_SYNC
RX_DATA (Input)
Start = Rising Edge on RX_FRAME_SYNC
RX_DATA (Input)
Start = Level Change on RX_FRAME_SYNC
RX_DATA (Input)
Start = Any Edge on RX_FRAME_SYNC
RX_DATA (Input)
Start = Low Level on RX_FRAME_SYNC
X
X
X
X
X
XB0
B0
B0
B0
B0
B0
B0
B1 B1
B1
B1
B1
B1
B1
STTDLY
STTDLY
STTDLY
STTDLY
STTDLY
STTDLY
518
32072H–AVR32–10/2012
AT32UC3A3
24.7.5 Frame Sync Th e transmitter and receiver frame synchro pins, TX_FRAME_SYNC and RX_FRAME_SYNC,
can be programmed to generate different kinds of frame synchronization signals. The
RFMR.FSOS and TFMR.FSOS fields are used to select the required waveform.
• Programmable low or high levels during data transfer are supported.
• Programmable high leve ls before the start of data transfers or toggling are also supported.
If a pulse waveform is selected, in reception, the Receive Frame Syn c Length High Part and the
Receive Frame Sync Length fields in the RFMR register (RF MR.FSLENHI and RFMR.FSLEN)
define the lengt h of the pulse, from 1 bit time up to 256 bit time.
Similarly, in transmission, the Transmit Frame Sync Length High Part and the Transmit Frame
Sync Length fields in the TFMR register (TFMR.FSLENHI and TFMR.FSLEN) define the length
of the pulse, from 1 bit up to 256 bit time.
The periodicity of the RX_FRAME_SYNC and TX_FRAME_SYNC pulse outputs can be config-
ured respectively through the Receive Period Divider Selection field in the RCMR register
(RCMR.PERIOD) and the Transmit Period Divider Selection field in the TCMR register
(TCMR.PERIOD).
24.7.5.1 Frame sync data
Frame Sync Data transmits or receives a specific tag during the Frame Sync signal.
During the Frame Sync signal, the receiver can sample the RX_DATA line and store the data in
the Receive Sync Holding Register (RSHR) and the transmitter can transfer the Transmit Sync
Holding Register (TSHR) in the shifter register.
The data length to be sampled in reception during the Frame Sync signal shall be written to the
RFMR.FSLENHI and RFMR.FSLEN fields.
The data length to be shifted out in tran smission duri ng the Frame Sync signal shall be writte n to
the TFMR.FSLENHI and TFMR.FSLEN fields.
Concerning the Rece ive Frame Sync Data operatio n, if the Frame Sync Length is equ al to or
lower than the delay between the start event and the actual data reception, the data sampling
operation is performed in the RSHR through the receive shift register.
The Transmit Frame Sync o pe ratio n is pe rfor me d by the t ransmit te r only if the Fra me Sync Da ta
Enable bit in TFMR register (TFMR.FSDEN) is written to one. If the Frame Sync length is equal
to or lower than the delay between the start event and the actual data transmission, the normal
transmission has priori ty and the data contain ed in the TSHR is transf err ed in t he tra nsmit regis-
ter, then shifted out.
24.7.5.2 Frame sync edge detection
The Frame Sync Ed ge detection is configured by writing to the Fram e Sync Edge Detection bit in
the RFMR/TFMR registers (RFMR.FSEDGE and TFMR.FSEDGE). This sets the Receive Sync
Reception Pulse Length ((16 FSLENHI×) FSLEN 1) receive clock periods++=
Transmission Pulse Length ((16 FSLENHI×) FSLEN 1) transmit clock periods++=
519
32072H–AVR32–10/2012
AT32UC3A3
and Transmit Sync bits in the SR register (SR.RXSYN and SR.TXSYN) on frame synchro edge
detection (signals RX_FRAME_SYNC/TX_FRAME_SYNC).
24.7.6 Receive Compare Modes
Figure 24-12. Receive Compare Modes
24.7.6.1 Compare functions
Compare 0 can be one start event of the receiver. In this case, the receiver compares at each
new sample the last {RFMR.FSLENHI, RFMR.FSLEN} bits received to the {RFMR.FSLENHI,
RFMR.FSLEN} lower bits of the data contained in the Receive Compare 0 Register (RC0R).
When this start event is selected, the user can program the receiver to start a new data transfer
either by writing a new Compare 0, or by receiving continuously until Compare 1 occurs. This
selection is done with the Receive Stop Selection bit in the RCMR register (RCMR.STOP).
24.7.7 Data Framing Format
The data framing format of both the transmitter and the receiver are programmable through the
TFMR, TCMR, RFMR, and RCMR registers. In either case, the user can independently select:
• the event that starts the data transfer (RCMR.START and TCMR.START)
• the delay in number of bit periods between the start event and the first data bit
(RCMR.STTDLY and TCMR.STTDLY)
• the length of the data (RFMR.DATLEN and TFMR.DATLEN)
• the number of data t o be tr ansf e rred for each start event (RFMR.D ATNB and TFMR.DATLEN)
• the length of synchronization transferred for each start event (RFMR.FSLENHI,
RFMR.FSLEN, TFMR.FSLENHI, and TFMR.FSLEN)
• the bit sense: most or lowest significant bit first (RFMR.MSBF and TFMR.MSBF)
Additionally, the transmitter can be used to transfer synchronization and select the level driven
on the TX_DATA pin while not in data transfer operation. This is done respectively by writing to
the Frame Sync Data Enable and the Data Default Value bits in the TFMR register
(TFMR.FSDEN and TFMR.DATDEF).
RX_DATA
(Input)
RX_CLOCK
CMP0 CMP1 CMP2 CMP3
Start
{FSLENHI,FSLEN}
Up to 256 Bits
(4 in This Example)
STTDLY
Ignored
DATLEN
B2B0 B1
Table 24-3. Data Framing Format Registers
Transmitter Receiver Bit/Field Length Comment
TCMR RCMR PERIOD Up to 512 Frame size
TCMR RCMR START Start selection
TCMR RCMR STTDLY Up to 255 Siz e of tr ansmit start delay
520
32072H–AVR32–10/2012
AT32UC3A3
Figure 24-13. Transmit and Receive Frame Form at in Edge/Pulse Start Modes
Note: Example of input on falling edge of TX_FRAME_SYNC/RX_FRAME_SYNC.
Figure 24-14. Transmit Frame Format in Continuous Mode
Note: STTDLY is written to zero. In this e xample, THR is loaded twice. FSDEN v alue has no effect on the
transmission. SyncData cannot be output in conti nuous mode.
TFMR RFMR DATNB Up to 16 Number of words transmitted in
frame
TFMR RFMR DATLEN Up to 32 Size of word
TFMR RFMR {FSLENHI,FSLEN} Up to 256 Size of Synchro data register
TFMR RFMR MSBF Most significant bit first
TFMR FSDEN Enable send TSHR
TFMR DATDEF Data default value ended
Table 24-3. Data Framing Format Registers
Transmitter Receiver Bit/Field Length Comment
DATNB
DATLEN
Data
DataData
Data
Data Data Default
Default
Sync Data
Sync Data
Ignored
From DATDEF
Start
From DATDEF
DATLEN
To RHRTo RHR
From THR
From THR
From THR
From THR
From DATDEF
From DATDEF
Ignored
Default
Default
Sync Data
To RSHR
From TSHR
FSLEN
Start
TX_FRAME_SYNC
/
RX_FRAME_SYNC
TX_DATA
(If FSDEN = 1)
TX_DATA
(If FSDEN = 0)
RX_DATA
STTDLY
Sync Data
PERIOD
(1)
Start
Data Data
DATLEN
From THR
DATLEN
TX_DATA
Start: 1. TXEMPTY set to one
2. Write into the THR
From THR
Default
521
32072H–AVR32–10/2012
AT32UC3A3
Figure 24-15. Receive Frame Format in Continuous Mode
Note: STTDLY is written to zero.
24.7.8 Loop Mode The receiver can be programmed to receive transmissions from the transmitter. This is done by
writing a one to the Lo op Mode bit in RFMR r egister (RFMR.LOOP). In this case, RX_DATA is
connected to TX_DATA, RX_FRAME_SYNC is connected to TX_FRAME_SYNC and
RX_CLOCK is connected to TX_CLOCK.
24.7.9 Interrupt Most bits in the SR register have a corresponding bit in interrupt management registers.
The SSC can be programmed to generate an interrupt when it detects an event. The interrupt is
controlled by writing to the Interrupt Enable Register (IER) and Interrupt Disable Register (IDR).
These registers enable and disable, respectively, the corresponding interrupt by setting and
clearing the corresponding bit in the Interru pt Mask Register (IMR), which controls the genera-
tion of interrupts by asserting the SSC interrupt line conne cted to the interrupt controller.
Figure 24-16. Inte rr up t Bloc k D iag ra m
Data Data
To RHRTo RHR
DATLEN
DATLEN
RX_DATA
Start = Enable Receiver
IM R
IER IDR
Clear
Set
Interrupt
Control
SSC Interrupt
TXRDY
TXEMPTY
TXSYNC
Transmitter
Receiver
RXRDY
OVRUN
RXSYNC
522
32072H–AVR32–10/2012
AT32UC3A3
24.8 SSC Application Examples
The SSC can support several serial communication modes used in audio or high speed serial
links. Some standard applications are shown in the following figures. All seria l link applications
supported by the SSC are not listed here.
Figure 24-17. Audio Application Block Diagram
Figure 24-18. Code c App licatio n Bloc k D iag ra m
Clock SCK
Word Select WS
Data SD MSB
Left Channel
LSB MSB
Right Channel
Data SD
Word Select WS
Clock SCK
SSC
TX_CLOCK
TX_FRAME_SYNC
TX_DATA
RX_DATA
RX_FRAME_SYNC
RX_CLOCK
I2S
RECEIVER
SSC
Serial Data Clock (SCLK)
Frame sync (FSYNC)
Serial Data Out
Serial Data In
Serial Data Clock (SCLK)
Frame sync (FSYNC)
Serial Data Out
Serial Data In
Dstart Dend
First Time Slot
CODEC
TX_CLOCK
TX_FRAME_SYNC
TX_DATA
RX_DATA
RX_FRAME_SYNC
RX_CLOCK
523
32072H–AVR32–10/2012
AT32UC3A3
Figure 24-19. Time Slot Application Block Diagram
CODEC
First
Time Slot
CODEC
Second
Time Slot
Data in
Data Out
FSYNC
SCLK
Serial Data Clock (SCLK)
Frame sync (FSYNC)
Serial Data Out
Serial Data In
Dstart
First Time Slot Second Time Slot
Dend
SSC
TX_CLOCK
TX_FRAME_SYNC
TX_DATA
RX_DATA
RX_FRAME_SYNC
RX_CLOCK
524
32072H–AVR32–10/2012
AT32UC3A3
24.9 User Interface
Table 24-4. SSC Register Memory Map
Offset Register Register Name Access Reset
0x00 Control Register CR Write-only 0x00000000
0x04 Clock Mode Register CMR Read/Write 0x00000000
0x10 Receive Clock Mode Register RCMR Read/Write 0x00000000
0x14 Receive Frame Mode Register RFMR Read/Write 0x00000000
0x18 Transmit Clock Mode Register TCMR Read/Write 0x00000000
0x1C Transmit Frame Mode Register TFMR Read/Write 0x00000000
0x20 Receive Holding Register RHR Read-only 0x00000000
0x24 Transmit Holding Register THR Write-only 0x00000000
0x30 Receive Synchronizat i on Ho l din g R eg i ste r RSHR Read-only 0x00000000
0x34 Transmit Synchronization Hold ing Register TSHR Read/Write 0x00000000
0x38 Receive Compare 0 Register RC0R Read/Write 0x00000000
0x3C Receive Compare 1 Register RC1R Read/Write 0x00000000
0x40 Status Register SR Read-only 0x000000CC
0x44 Interrupt Enable Register IER Write-only 0x00000000
0x48 Interrupt Disable Register IDR Write-only 0x00000000
0x4C Interrupt Mask Register IMR Read-only 0x00000000
525
32072H–AVR32–10/2012
AT32UC3A3
24.9.1 Control Register
Name: CR
Access Type: Write-only
Offset: 0x00
Reset value: 0x00000000
• SWRST : Software Reset
1: Writing a one to this bit will perform a software reset. This software reset has priority on any other bit in CR.
0: Writing a ze ro to this bi t ha s no ef fect.
• TXDIS: Transmit Disable
1: Writing a one to this bit will disable the transmission. If a charact er is currently bei ng transmitted, the disable occurs at the end
of the current ch aracter transmi ssion .
0: Writing a ze ro to this bi t ha s no ef fect.
• TXEN: Transmit Enable
1: Writing a one to this bit will enable the transmission if the TXDIS bit is not written to one.
0: Writing a ze ro to this bi t ha s no ef fect.
• RXDIS: Receive Disable
1: Writing a one to this bi t will disable the reception. If a character is currently being received, the disable occurs at the end of
current character reception.
0: Writing a ze ro to this bi t ha s no ef fect.
• RXEN: Receive Enable
1: Writing a one to this bit will enables the reception if the RXDIS bit is not written to one.
0: Writing a ze ro to this bi t ha s no ef fect.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
SWRST-----TXDISTXEN
76543210
------RXDISRXEN
526
32072H–AVR32–10/2012
AT32UC3A3
24.9.2 Cl ock Mode Regi st er
Name: CMR
Access Type: Read/Write
Offset: 0x04
Reset value: 0x00000000
• DIV[11:0]: Clock Divider
The divided clock equals the CLK_SSC divided by two times DIV. The maximum bit rate is CLK_SSC/2. The minimum bit rate is
CLK_SSC/(2 x 4095) = CLK_SSC/8190.
The clock divider is not active when DIV equal s zero.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
- - - - DIV[11:8]
76543210
DIV[7:0]
Divided Clock CLK_SSC (⁄DIV 2)×=
527
32072H–AVR32–10/2012
AT32UC3A3
24.9.3 Rece iv e Clock Mode Re gi st er
Name: RCMR
Access Type: Read/Write
Offset: 0x10
Reset value: 0x00000000
• PERIOD: Receive Period Divider Selection
This field selects the divider to apply to the selected receive clock in order to generate a periodic Frame Sync Signal.
If equal to zero, no signal is generated.
If not equal to zero, a signal is generated each 2 x (PERIOD+1) receive clock periods.
• STTDLY: Receive Start Delay
If STTDLY is not zero, a delay of STTDLY clock cycles is inserted between the star t event and the actual start of reception.
When the receiver is programmed to start synchro nously with the transmitter, the delay is also applied.
Note: It is very important that STTDLY be written carefully. If STTDLY must be written, it should be don e in relation to Receive
Sync Data reception.
• STOP: Receive Stop Selection
1: After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare 1 is detected.
0: After completion of a data transfer when starting with a Compare 0, the receiver stops the data transfer and waits for a new
Compare 0.
31 30 29 28 27 26 25 24
PERIOD
23 22 21 20 19 18 17 16
STTDLY
15 14 13 12 11 10 9 8
---STOP START
76543210
CKG CKI CKO CKS
528
32072H–AVR32–10/2012
AT32UC3A3
• START: Receive Start Selection
• CKG: Receive Clock Gating Selection
• CKI: Receive Clock Inversion
CKI affects only the receive clock and not the output clock signal.
1: The data inputs (Data and Frame Sync signals) are sampled on receive clock rising edge. The Frame Sync signal output is
shifted out on receive clock falling edge.
0: The data inputs (Data and Frame Sync signals) are sampled on receive clock falling edge. The Frame Sync signal output is
shifted out on receive clock rising edge.
• CKO: Receive Clock Output Mode Selection
• CKS: Receive Clock Selection
START Receive Start
0Continuous, as soon as the receiver is enabled, and immediately after the end of
transfer of the previous data.
1Transmit start
2Detection of a low level on RX_FRAME_SYNC signal
3Detection of a high level on RX_FRAME_SYNC signal
4Detection of a falling edge on RX_FRAME_SYNC signal
5Detection of a rising edge on RX_FRAME_SYNC signal
6Detection of any level change on RX_FRAME_SYNC signal
7Detection of any edge on RX_FRAME_SYNC signal
8Compare 0
Others Reserved
CKG Receive Clock Gating
0None, continuous clock
1Receive Clock enabled only if RX_FRAME_SYNC is low
2Receive Clock enabled only if RX_FRAME_SYNC is high
3Reserved
CKO Receive Clock Output Mode RX_CLOCK pin
0None Input-only
1Continuous receive clock Output
2Receive clock only during data transfers Output
Others Reserved
CKS Selected Receiv e Clock
0Divided clock
1TX_CLOCK clock signal
2RX_CLOCK pin
3Reserved
529
32072H–AVR32–10/2012
AT32UC3A3
24.9.4 Receive Frame Mode Register
Name: RFMR
Access Type: Read/Write
Offset: 0x14
Reset value: 0x00000000
• FSLENHI: Receive Frame Sync Length High Part
The four MSB of the FSLEN field.
• FSEDGE: Receive Frame Sync Edge Detection
Deter m ines which edge on Frame Sync will generate the SR.RXSYN interrupt.
• FSOS: Receive Frame Sync Output Selection
• FSLEN: Receive Frame Sync Length
This field defines the length of the Receive F rame Sync signal and the number of bits sampled and stored in the RSHR register .
When this mode is selected by the RCMR.START field, it also determines the length of the sampled data to be compared to the
Compare 0 or Compare 1 register.
Note: The four most significant bits for this field are located in the FSLENHI field.
The pulse length is equal to ({FSLENHI,FSLEN} + 1) receive clock periods. Thus, if {FSLENHI,FSLEN} is zero, the Receive
Frame Sync signal is generated during one receive clock period.
31 30 29 28 27 26 25 24
FSLENHI - - - FSEDGE
23 22 21 20 19 18 17 16
- FSOS FSLEN
15 14 13 12 11 10 9 8
---- DATNB
76543210
MSBF - LOOP DATLEN
FSEDGE Frame Sync Edge Detection
0Po sitive edge detection
1Negative edge detection
FSOS Selected Receive Frame Sync Signal RX_FRAME_SYNC Pin
0None Input-only
1Negative Pulse Output
2Positiv e Pulse Output
3Driven Low during data transfer Output
4Driven High during data transfer Output
5Toggling at each start of data transfer Output
Others Reserved Undefined
530
32072H–AVR32–10/2012
AT32UC3A3
• DATNB: Data Number pe r Frame
This field defines the number of data words to be received after each transfer start, which is equal to (DATNB + 1).
• MSBF: Most Significant Bit First
1: The most significant bit of the data register is sampled first in the bit stream.
0: The lowest significant bit of the data register is sampled first in the bit stream.
• LOOP: Loop Mode
1: RX_DATA is driven by TX_DATA, RX_FRAME_SYNC is driven by TX_FRAME_SYNC and TX_CLOCK dr ives RX_CLOCK.
0: Nor mal operating mode.
• DATLEN: Data Length
The bit stream contains (DATLEN + 1) data bits.
This field also defines the transfer size perform ed by the Peripheral DMA Controller assig ned to the receiver.
DATLEN Transfer Size
0Forbidden value
1-7 Data transfer are in bytes
8-15 Data transfer are in halfwords
Others Data transfer are in words
531
32072H–AVR32–10/2012
AT32UC3A3
24.9.5 Transmit Clock Mode Register
Name: TCMR
Access Type: Read/Write
Offset: 0x18
Reset value: 0x00000000
• PERIOD: Tr ansmit Period Divider Selection
This field selects the divid er to apply to the selected transmit clock in order to generate a periodic Frame Sync Signal.
If equal to zero, no signal is generated.
If not equal to zero, a signal is generated each 2 x (PERIOD+1) transmit clock periods.
• STTDLY: Transmit Start Delay
If STTDLY is not zero, a delay of STTDLY clock cycles is inserted between the star t event and the actual start of transmission.
When the transmitter is programmed to start synchronously with the receiver, the delay is also applied.
Note: STTDLY must be written carefully, in relation to Transmit Sync Data transmission.
• START: Transmit Start Selection
31 30 29 28 27 26 25 24
PERIOD
23 22 21 20 19 18 17 16
STTDLY
15 14 13 12 11 10 9 8
- - - - START
76543210
CKG CKI CKO CKS
START Transmit Start
0Continuous, as soon as a word is written to the THR Register (if Transmit is enabled), and
immediately after the end of transfer of the previous data.
1Receive start
2Detection of a low level on TX_FRAME_SYNC signal
3Detection of a high level on TX_FRAME_SYNC signal
4Detection of a falling edge on TX_FRAME_SYNC signal
5Detection of a rising edge on TX_FRAME_SYNC signal
6Detection of any level change on TX_FRAME_SYNC signal
7Detection of any edge on TX_FRAME_SYNC signal
Others Reserved
532
32072H–AVR32–10/2012
AT32UC3A3
• CKG: Transmit Clock Gating Selection
• CKI: Transmit Cloc k Inversion
CKI affects only the Transmit Clock and not the output clock signal.
1: The data outputs (Data and F r ame Sync signals) are shifted out on transmit clock rising edge. The Fr ame sync signal input is
sampled on transmit clock falling edge.
0: The data outputs (Data and F rame Sync signals) are shifted out on transmit clock f alling edge. The Frame sync signal input is
sampled on transmit clock rising edge.
• CKO: Transmit Clock Output Mode Selection
• CKS: Transmit Clock Selection
CKG Transmit Clock Gating
0None, continuous clock
1Transmit Clock enabled only if TX_FRAME_SYNC is low
2Transmit Clock enabled only if TX_FRAME_SYNC is high
3Reserved
CKO Transmit Clock Output Mode TX_CLOCK pin
0None Input-only
1Continuous transmit clock Output
2Transmit clock only during data transfers Output
Others Reserved
CKS Selected Transmit Clock
0Divided Clock
1RX_CLOCK clock signal
2TX_CLOCK Pin
3Reserved
533
32072H–AVR32–10/2012
AT32UC3A3
24.9.6 Transmit Frame Mode Register
Name: TFMR
Access Type: Read/Write
Offset: 0x1C
Reset value: 0x00000000
• FSLENHI: Transmit Frame Sync Length High Part
The four MSB of the FSLEN field.
• FSEDGE: Transmit Frame Sync Edge Detection
Deter m ines which edge on Frame Sync will generate the SR.TXSYN interrupt.
• FSDEN: Transmit Frame Sync Data Enable
1: TSHR value is shifted out during the transmission of the Transmit Frame Sync signal.
0: The TX_DATA line is driven with the default value during the Transmit Frame Sync signal.
• FSOS: Transmit Frame Sync Output Selection
• FSLEN: Transmit Frame Sync Length
This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the TSHR register if
TFMR.FSDEN is equal to one.
Note: The four most significant bits for this field are located in the FSLENHI field.
31 30 29 28 27 26 25 24
FSLENHI - - - FSEDGE
23 22 21 20 19 18 17 16
FSDEN FSOS FSLEN
15 14 13 12 11 10 9 8
---- DATNB
76543210
MSBF - DATDEF DATLEN
FSEDGE Frame Sync Edge Detection
0Positive Edge Detection
1Negative Edge Detection
FSOS Selected Transmit Frame Sync Signal TX_FRAME_SYNC Pin
0None Input-only
1Negative Pulse Output
2Positive Pulse Output
3Driven Low during data transfer Output
4Driven High during data transfer Output
5Toggling at each start of data transfer Output
Others Reserved Undefined
534
32072H–AVR32–10/2012
AT32UC3A3
The pulse length is equal to ({FSLENHI,FSLEN} + 1) transmit clock periods, i.e., the pulse length can range from 1 to 256
transmit clock periods. If {FSLENHI,FSLEN} is zero, the Transmit Frame Sync signal is generated dur ing one transmit clock
period.
• DATNB: Data Number pe r Frame
This field defines the number of data words to be transferred after each transfer start, which is equal to (DATNB + 1).
• MSBF: Most Significant Bit First
1: The most significant bit of the data register is shifted out first in the bit stream.
0: The lowest significant bit of the data register is shifted out first in the bit stream.
• DATDEF: Data Default Value
This bit defines the le vel driven on the TX_D ATA pin while out of transmission.
Note that if the pin is defined as multi-drive by the I/O Controller, the pin is enabled only if the TX_DATA output is one.
1: The level driven on the TX_DATA pin while out of transmission is one.
0: The level driven on the TX_DATA pin while out of transmission is zero.
• DATLEN: Data Length
The bit stream contains (DATLEN + 1) data bits.
This field also defines the transfer size performed by the Peripheral DMA Controller assigned to the transmitter.
DATLEN Transfer Size
0Forbidden value (1-bit data length is not supported)
1-7 Data transfer are in bytes
8-15 Data transfer are in halfwords
Others Data transfer are in words
535
32072H–AVR32–10/2012
AT32UC3A3
24.9.7 Receive Holding Register
Name: RHR
Access Type: Read-only
Offset: 0x20
Reset value: 0x00000000
• RDAT: Receive Data
Right aligned regardless of the number of data bits defined by the RFMR.DATLEN field.
31 30 29 28 27 26 25 24
RDAT[31:24]
23 22 21 20 19 18 17 16
RDAT[23:16]
15 14 13 12 11 10 9 8
RDAT[15:8]
76543210
RDAT[7:0]
536
32072H–AVR32–10/2012
AT32UC3A3
24.9.8 Transmit Holding Register
Name: THR
Access Type: Write-only
Offset: 0x24
Reset value: 0x00000000
• TDAT: Transmit Data
Right aligned regardless of the number of data bits defined by the TFMR.DATLEN field.
31 30 29 28 27 26 25 24
TDAT[31:24]
23 22 21 20 19 18 17 16
TDAT[23:16]
15 14 13 12 11 10 9 8
TDAT[15:8]
76543210
TDAT[7:0]
537
32072H–AVR32–10/2012
AT32UC3A3
24.9.9 Receive Synchronization Holding Register
Name: RSHR
Access Type: Read-only
Offset: 0x30
Reset value: 0x00000000
• RSDAT: Receive Synchronization Data
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
RSDAT[15:8]
76543210
RSDAT[7:0]
538
32072H–AVR32–10/2012
AT32UC3A3
24.9.10 Transmit Sync hronization Holding Register
Name: TSHR
Access Type: Read/Write
Offset: 0x34
Reset value: 0x00000000
• TSD AT: Transmit Synchronization Data
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
TSDAT[15:8]
76543210
TSDAT[7:0]
539
32072H–AVR32–10/2012
AT32UC3A3
24.9.11 Receive Compare 0 Register
Name: RC0R
Access Type: Read/Write
Offset: 0x38
Reset value: 0x00000000
•CP0: Receive Compare Data 0
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
CP0[15:8]
76543210
CP0[7:0]
540
32072H–AVR32–10/2012
AT32UC3A3
24.9.12 Receive Compare 1 Register
Name: RC1R
Access Type: Read/Write
Offset: 0x3C
Reset value: 0x00000000
• CP1: Receive Compare Data 1
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
CP1[[15:8]
76543210
CP1[7:0]
541
32072H–AVR32–10/2012
AT32UC3A3
24.9.13 Status Register
Name: SR
Access Type: Read-only
Offset: 0x40
Reset value: 0x000000CC
• RXEN: Receive Enable
This bit is set when the CR.RXEN bit is written to one.
This bit is cleared when no data are being processed and the CR.RXDIS bit has been written to one.
• TXEN: Transmit Enable
This bit is set when the CR.TXEN bit is written to one.
This bit is cleared when no data are being processed and the CR.TXDIS bit has been written to one.
• RXSYN: Receive Sync
This bit is set when a Receive Sync has occurred.
This bit is cleared when the SR register is read.
• TXSYN: Transmit Sync
This bit is set when a Transmi t Sync has occurred.
This bit is cleared when the SR register is read.
• CP1: Compare 1
This bit is set when compare 1 has occurred.
This bit is cleared when the SR register is read.
• CP0: Compare 0
This bit is set when compare 0 has occurred.
This bit is cleared when the SR register is read.
• OVRUN: Receive Overrun
This bit is set when data has been loaded in the RHR register whi le previous data has not yet been read.
This bit is cleared when the SR register is read.
• RXRDY: Receive Ready
This bit is set when data has been received and loaded in the RHR register.
This bit is cleared when the RHR register is empty.
• TXEMPTY: Transmit Empty
This bit is set when the last data written in the THR register has been loaded in the TSR register and last data loaded in the TSR
register has been transmitted.
This bit is cleared when data remains in the THR register or is currently transmitted from the TSR register.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
- - - - - - RXEN TXEN
15 14 13 12 11 10 9 8
- - - - RXSYN TXSYN CP1 CP0
76543210
- - OVRUN RXRDY - - TXEMPTY TXRDY
542
32072H–AVR32–10/2012
AT32UC3A3
• TXRDY: Transmit Ready
This bit is set when the THR register is empty.
This bit is cleared when data has been loaded in the THR re gister and is waiting to be loaded in th e TSR register.
543
32072H–AVR32–10/2012
AT32UC3A3
24.9.14 Interrupt Enable Register
Name: IER
Access Type: Write-only
Offset: 0x44
Reset value: 0x00000000
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will set the corresponding bit in IMR.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
- - - - RXSYN TXSYN CP1 CP0
76543210
– – OVRUN RXRDY – – TXEMPTY TXRDY
544
32072H–AVR32–10/2012
AT32UC3A3
24.9.15 Interrupt Disable Register
Name: IDR
Access Type: Write-only
Offset: 0x48
Reset value: 0x00000000
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will clear the corresponding bit in IMR.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
- - - - RXSYN TXSYN CP1 CP0
76543210
– – OVRUN RXRDY – – TXEMPTY TXRDY
545
32072H–AVR32–10/2012
AT32UC3A3
24.9.16 Interrupt Mask Register
Name: IMR
Access Type: Read-only
Offset: 0x4C
Reset value: 0x00000000
0: The corresponding interr upt is disabled.
1: The corresponding interrupt is enabled.
A bit in this register is cleared when the corresponding bit in IDR is wr itten to one.
A bit in this register is set when the corresponding bit in IER is written to one.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
- - - - RXSYN TXSYN CP1 CP0
76543210
– – OVRUN RXRDY – – TXEMPTY TXRDY
546
32072H–AVR32–10/2012
AT32UC3A3
25. Universal Synchronous Asynchronous Receiver Transmitter (USART)
Rev: 4.2.0.6
25.1 Features •Configurable baud rate generator
•5- to 9-bit full-duplex, synchronous and asynchronous, serial communication
– 1, 1.5, or 2 stop bits in asynchronous mode, and 1 or 2 in synchronous mode
– Parity generatio n and error de tection
– Framing- and overrun error detection
– MSB- or LSB-first
– Optional break generation and detection
– Receiver frequency oversampling by 8 or 16 times
– Optional R TS-CT S hardware handshaking
– Optional DTR-DSR-DCD-RI modem signal management
– Receiver Time-out and transmitter Timeguard
– Optional Multidrop mode with address generation and detection
•RS485 with line dri ver control
•ISO7816, T=0 and T=1 protocols for Interfacing with smart card s
– , NACK handling, and customizable error counter
•IrDA modu lation and demodulation
– Communication at up to 115.2Kbit/s
•SPI Mode
– Master or slave
– Configurable serial clock phase and polarity
– CLK SPI serial clock frequency up to a quarter of the CLK_USART internal clock frequency
•LIN Mode
– Compliant with LIN 1.3 and LIN 2.0 specifications
– Master or slave
– Processing of Frames with up to 256 data bytes
– Configurable response data length, optionally defi ned automatically by the Identifier
– Self synchronization in slave no de config uratio n
– Automatic processing and verification of the “Break Field” and “Sync Field”
– The “Break Field” is detected even if it is partially superimposed with a data byte
– Optional, automatic identifier parity management
– Optional, automatic checksum management
– Supports both “Classic” and “Enhanced” checksum types
– Full LIN error checking and reporting
– Frame Slot Mode: the master allocates slots to scheduled frames automatically.
– Wakeup signal generati on
•Test Modes
– Automatic echo, remote- and local loopback
•Supports two Peripheral DMA Controller channels
– Buffer transfers without processor intervention
25.2 Overview The Universal Synchronous Asynchronous Receiver Transmitter (USART) provides a full
duplex, universal, synchronous/asyn chronous serial link. Da ta frame format is widely configu-
rable, including basic length, parity, and stop bit settings, maximizing standards support. The
receiver implements parity-, framing-, and overrun error detectio n, and can handle un-fixed
547
32072H–AVR32–10/2012
AT32UC3A3
frame lengths with the time-out feature. The USART supports several operating modes, provid-
ing an interface to RS485, LIN, and SPI buses, with ISO7816 T=0 and T=1 smart card slots,
infrared transceivers, and modem port connections. Communication with slow and remote
devices is eased by the tim eguard. Duplex multidrop communica tion is supported by address
and data differentiation through the parity bit. The hardware handshaking feature enables an
out-of-band flow control, automatically managing RTS and CTS pins. The Peripheral DMA Con-
troller connection enables memory transactions, and the USART supports chained buffer
management witho ut processor intervention . Automatic echo, remote- , and local loopback test
modes are also supported.
25.3 Block Diagram
Figure 25-1. USART Block Diagram
Peripheral DMA
Controller
Channel Channel
Interrupt
Controller
Power
Manager DIV
Receiver
Transmitter
Modem
Signals
Control
User
Interface
I/O
Controller
RXD
RTS
TXD
CTS
DTR
DSR
DCD
RI
CLK
BaudRate
Generator
USART
Interrupt
CLK_USART
CLK_USART/DIV
USART
Peripheral bus
548
32072H–AVR32–10/2012
AT32UC3A3
25.4 I/O Lines Description
25.5 Product Dependencies
In order to use t his modu le, othe r p arts o f th e syst em must be conf igu red cor re ctly, as de scr ibed
below.
25.5.1 I/O Lines The USART pins may be multiplexed with the I/O Controller lines. The user must first configure
the I/O Controller to assign these pins to their peripheral functions. Unused I/O lines may be
used for other purposes.
To prevent the TXD line from falling when the USART is disabled, the use of an internal pull-up
is required. If the ha rdwa re hand sh aking featu re or modem mode is used, th e int erna l pull- up on
RTS must also be enabled .
All the pins of the modems may or may not be implemented on the USART. On USARTs not
equipped with the cor responding pins, the associa ted contr ol bits and statuses have n o effect on
the behavior of the USART.
Table 25-1. SPI Operating Mode
PIN USART SPI Slave SPI Master
RXD RXD MOSI MISO
TXD TXD MISO MOSI
RTS RTS – CS
CTS CTS CS –
Table 25-2. I/O Lines Description
Name Descr iption Type Active Level
CLK Serial Clock I/O
TXD Transmit Serial Data
or Master Out Slave In (MOSI) in SPI master mode
or Master In Slave Out (MISO) in SPI slave mode Output
RXD Receive Serial Data
or Master In Slave Out (MISO) in SPI master mode
or Master Out Slave In (MOSI) in SPI slav e mode Input
RI Ring Indicator Input Low
DSR Data Set Ready Input Low
DCD Data Carrier Detect Input Low
DTR Data Terminal Ready Output Low
CTS Clear to Send
or Slave Select (NSS) in SPI slave mode Input Low
RTS Request to Send
or Slave Select (NSS) in SPI master mode Output Low
549
32072H–AVR32–10/2012
AT32UC3A3
25.5.2 Clocks The clock for the USART bus inte rf ace (CL K_U SART) is g ene ra ted b y the Po wer Man ager. T his
clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to dis-
able the USART before disabling the clock, to avoid freezing the USART in an undefined state.
25.5.3 Interrupts The USART interrupt request line is connected to the interrupt controller. Using the USART
interrupt requires the interrupt controller to be programmed first.
550
32072H–AVR32–10/2012
AT32UC3A3
25.6 Functional Description
25.6.1 USART Operating Modes
The USART can operate in several modes:
•Normal
• RS485, described in Section 25.6.5 ”RS485 Mode” on page 560
• Hardware handshaking, described in Section 25.6.6 ”Hardware Handshaking” on page 561
• Modem, described in Section 25.6.7 ”Modem Mode” on page 562
• ISO7816, described in Section 25.6.8 ”ISO7816 Mode” on page 563
• IrD A, described in Section 25.6.9 ”IrDA Mode” on page 566
• LIN Master, described in Section 25.6 .1 0 ”L IN Mo d e” on pa ge 56 8
• LIN Slave, describe d in Section 25.6.10 ”LIN Mode” on page 568
• SPI Master, described in Section 25.6.15 ”SPI Mode” on page 580
• SPI Slave, described in Section 25.6.15 ”SPI Mode” on page 580
The operating mode is selected by writing to t he Mode fiel d in the “Mod e Register ” (MR.MODE).
In addition, Synchronous or Asynchr onous mode is selected by writing to the Synchronous
Mode Select bit in MR (MR.SYNC). By d efault, MR. MODE and MR.SYNC are bot h zero, and the
USART operates in Norm al Asynchronous mode.
25.6.2 Basi c Opera t ion
To start using the USART, the user must perform the following steps:
1. Configure the baud rate by writing to the Baud Rate Generator Register (BRGR) as
described in ”Baud Rate Generator” on page 558
2. Select the operating mode by writing to the relevant fields in the Mode Regiser (MR)
3. Enable the transmitter and/or receiver, by writing a one to CR.TXEN and/or CR.RXEN
respectively
Table 25-3. MR.MODE
MR.MODE Mode of the USART
0x0 Normal
0x1 RS485
0x2 Hardware Handshaking
0x3 Modem
0x4 IS07816 Protocol: T = 0
0x6 IS07816 Protocol: T = 1
0x8 IrDA
0xA LIN Master
0xB LIN Slave
0xE SPI Master
0xF SPI Slave
Others Reserved
551
32072H–AVR32–10/2012
AT32UC3A3
4. Check that CSR.TXRDY and/or CSR.RXRDY is one before writing to THR and/or read-
ing from RHR respectively
25.6.2.1 Receiver and Transmitter Control
After a reset, the transceiver is disabled. The receiver/transmitter is enabled by writing a one to
the Receiver Enable/Transmitter Enable bit in the Control Register (CR.RXEN/CR.TXEN)
respectively. They may be enabled together and can be configured both before and after they
have been enabled. The user can reset the USART receiver/transmitter at any time by writing a
one to the Reset Receiver/Reset Transmitter bit (CR.RSTRX/CR.RSTTX) respectively. This
software reset clears status bits and resets internal state machines, im mediately halting any
communication. The user interface configuration registers will retain their values.
The user can disable the receiver/transmitter by writing a one to either the Receiver Disable, or
Transmitter Disable bit (CR.RXDIS, or CR.TXDIS). If the receiver is disabled during a character
reception, the USART will wait for the current character to be received before disabling. If the
transmitter is disabled during transmission, the USART will w ait until both the current character
and the character stored in the Transmitter Holding Register (THR) are transmitted before dis-
abling. If a timeguard has been implemented it will remain functional during the transmission.
25.6.2.2 Transmitter Operations
The transmitter operates equally in both Synchronous and Asynchronous operating modes
(MR.SYNC). One start bit, up to 9 data bits, an optional parity bit, and up to two stop bits are
successively shifted out on the TXD pin at each falling edge of the serial clock. The numb er of
data bits is selected by the Charac ter Length fi eld (MR.C HRL) and the 9-bit Chara cter Lengt h bit
in the Mode Registe r (MR.MODE9). Nine bit s are selected by writing a on e to MR.MODE9, over-
riding any value in MR.CHRL. The parity bit configuration is selected in the MR.PAR field. The
Most Significant Bit First bit (MR.MSBF) selects which data bit to send first. The number of stop
bits is selected by the MR.NBSTOP field. The 1.5 stop bit configuration is only supported in
asynchronous mode.
Figure 25-2. Character Transmit
The characters are sent by writing to the Character to be Transmitted field (THR.TXCHR). The
transmitter status can be read from the Transmitter Ready and Transmitter Empty bits in the
Channel Status Register (CSR.TXRDY/CSR.TXEMPTY). CSR.TXRDY is set when THR is
empty. CSR.TXEMPTY is set when both THR and the transmit shift register are empty (trans-
mission comp lete). An interrupt request is generated if the corre sponding bit in the Interr upt
Mask Register (IMR) is set (IMR.TXRDY/IMR.TXEMPTY). Both CSR.TXRDY and
CSR.TXEMPTY are cleared when the transmitter is disabled. CSR.TXRDY and CSR.TXEMPY
can also be cleared by writing a one to the Start Break bit in CR (CR.STTBRK). Writing a char-
acter to THR while CSR.TXRDY is zero has no effect and the written character will be lost.
D0 D1 D2 D3 D4 D5 D6 D7
TXD
Start
Bit Parity
Bit Stop
Bit
Example: 8-bit, Parity Enabled One Stop
Baud Rate
Clock
552
32072H–AVR32–10/2012
AT32UC3A3
Figure 25-3. Transmitter Status
25.6.2.3 Asy nc hron ous Re ce iver
If the USART is configured in an asynchrono us operating mod e (MR.SYNC is zero), the receiver
will oversample the RXD input line by either 8 or 16 times the Baud Rate Clock, as selected by
the Oversa mplin g Mo de bi t (MR .OVER). If the line is zero for half a bit p eriod (fo ur or eigh t con -
secutive samples, respectively), a start bit will be assumed, and the following 8th or 16th sample
will determine the logical value on the line, resulting in bit values being determined at the middle
of the bit period.
The number of data bits, endianess, parity mod e, and stop bits are selected by the same bits
and fields as for the transmitter (MR.CHRL, MR.MODE9, MR.MSBF, MR.PAR, and
MR.NBSTOP). The synchronization mechanism will only consider one stop bit, regardless of the
used protocol, and when the first stop bit has b een sampled, the receiver will automatically begin
looking for a new start bit, enabling resynchronization even if there is a protocol mismatch. Fig-
ure 25-4 and Figure 25-5 illustrate start bit detection and character reception in asynchronous
mode.
Figure 25-4. Asynchronous Start Bit Detection
D0 D1 D2 D3 D4 D5 D6 D7
TXD
Start
Bit Parity
Bit Stop
Bit
Baud Rate
Clock
Start
Bit
Write
THR
D0 D1 D2 D3 D4 D5 D6 D7 Parity
Bit Stop
Bit
TXRDY
TXEMPTY
Sampling
Clock (x16)
RXD
Start
Detection
Sampling
Baud Rate
Clock
RXD
Start
Rejection
Sampling
12345678
123456701234
123456789 10111213141516D0
Sampling
553
32072H–AVR32–10/2012
AT32UC3A3
Figure 25-5. Asynchronous Mode Character Reception
25.6.2.4 Synchronous Receiver
In synchronous mode (MR.SYNC is one), the receiver samples the RXD signal on each rising
edge of the Baud Rate Clock, as illustrated in Figure 25-6. If a low level is detected, it is consid-
ered as a start bit. Configuration bits and fields are the same as in asynchronous mode.
Figure 25-6. Synchronous Mode Character Reception
Figure 25-7. Receiver Status
25.6.2.5 Receiver Oper ations
When a character reception is completed, it is transferred to the Received Character field in the
Receive Holding Register (RHR.RXCHR), and the Receiver Ready bit in the Channel Status
Register (CSR.RXRDY) is set. An interrupt request is generated if the Receiver Ready bit in the
D0 D1 D2 D3 D4 D5 D6 D7
RXD
Parity
Bit Stop
Bit
Example: 8-bit, Parity Enabled
Baud Rate
Clock
Start
Detection 16
samples 16
samples 16
samples 16
samples 16
samples 16
samples 16
samples 16
samples 16
samples 16
samples
D0 D1 D2 D3 D4 D5 D6 D7
RXD
Start
Sampling
Parity Bit Stop Bit
Example: 8-bit, Parity Enabled 1 Stop
Baud Rate
Clock
D0 D1 D2 D3 D4 D5 D6 D7
RXD
Start
Bit Parity
Bit Stop
Bit
Baud Rate
Clock
Write
CR
RXRDY
OVRE
D0 D1 D2 D3 D4 D5 D6 D7
Start
Bit Parity
Bit Stop
Bit
RSTSTA = 1
Read
RHR
554
32072H–AVR32–10/2012
AT32UC3A3
Interrupt Mask Register ( IMR.RXRDY) is se t. If CSR.RXRDY is already set, RHR will be over-
written and the Overrun Error bit (CSR.OVRE) is set. An interrupt request is generated if the
Overrun Error bit in IMR is set. Reading R HR will clear CSR.RXRDY, and writing a one to the
Reset Status bit in the Control Register (CR.RSTSTA) will clear CSR.OVRE. Refer to Figure 25-
7.
25.6.3 Other Conside rations
25.6.3.1 Parity The USART supports five parity modes, selected by MR.PAR:
• Even parity
•Odd parity
• Parity f orced to zero (space)
• Parity forced to one (mark)
• No parity
The PAR field also enables the Multidrop mode, see ”Multidrop Mode” on page 555. If even par-
ity is selected (MR.PAR is 0x0), the parity bit will be zero if there is an even number of ones in
the data character, and one if there is an odd number. For odd parity the reverse applies. If
space or mark parity is chosen (MR.PAR is 0x2 or 0x3, respectively), the parity bit will always be
a zero or one, respectively. See Table 25 -4 .
The receiver will report parity errors in CSR.PARE, unless parity is disabled. An interrupt request
is generated if the PARE bit in the Interrupt Mask Register is set (IMR.PARE). Writing a one to
CR.RSTSTA will clear CSR.PARE. See Figure 25-8.
Figure 25-8. Parity Error
Table 25-4. Parity Bit Examples
Alphanum
Character Hex Bin
Parity Mode
Odd Even Mark Space None
A 0x41 0100 0001 1 0 1 0 -
V 0x56 0101 0110 1 0 1 0 -
R 0x52 0101 0010 0 1 1 0 -
D0 D1 D2 D3 D4 D5 D6 D7
RXD
Start
Bit Bad
Parity
Bit
Stop
Bit
Baud Rate
Clock
Write
CR
PARE
RXRDY
RSTSTA = 1
555
32072H–AVR32–10/2012
AT32UC3A3
25.6.3.2 Multidrop Mode
If MR.PAR is either 0x6 or 0x7, the USART runs in Multidrop mode. This mode differentiates
data and address characters. Data has the parity bit zero and addresses have a one. By writing
a one to the Send Address bit (CR.SENDA) the user will cause the next character written to THR
to be transmitted as an address. Receiving a character with a one as parity bit will report parity
error by setting CSR.PARE. An interrupt request is generated if the PARE bit in the Interrupt
Mask Register is set ( IMR.PARE).
25.6.3.3 Transmitter Timeguard
The timeguard feature enables t he USART to interf ace slow de vices by inse rting an idle state on
the TXD line in between two characters. This idle state corresp onds to a long stop bit, whose
duration is selected by the Timeguard Value field in the Transmitter Timeguard Register
(TTGR.TG). The transmitter will hold the TXD line high for TTGR.TG bit periods, in addition to
the number of stop bits. As illustrated in Figure 25-9, the behavior of TXRDY and TXEMPTY is
modified when TG has a non-zero value. If a pending character has been written to THR, the
CSR.TXRDY bit will not be set un til this characters start bit has been sent. CSR.TXEMPTY will
remain low until the timeguard transmission has completed.
Figure 25-9. Timeguard Opera tion
D0 D1 D2 D3 D4 D5 D6 D7
TXD
Start
Bit Parity
Bit Stop
Bit
B
aud Rate
Clock
Start
Bit
TG = 4
Write
THR
D0 D1 D2 D3 D4 D5 D6 D7 Parity
Bit Stop
Bit
TXRDY
T
XEMPTY
TG = 4
Table 25-5. Maximum Baud Rate Dependent Timeguard Durations
Baud Rate (bit/sec) Bit time (µs) Timeguard (ms)
1 200 833 212.50
9 600 104 26.56
14400 69.4 17.71
19200 52.1 13.28
28800 34.7 8.85
33400 29.9 7.63
56000 17.9 4.55
57600 17.4 4.43
115200 8.7 2.21
556
32072H–AVR32–10/2012
AT32UC3A3
25.6.3.4 Receiver Time-out
The Time-out Value field in the Receiver Time-out Register (RTOR.TO) enable s handling of vari-
able-length fra mes by detection of selectable idle durations on t he RXD line. The value written to
TO is loaded to a decremental counter, and unless it is zero, a time-out will occur when the
amount of inactive bit periods matches the initial counter value. If a time-out has not occurred,
the counter will reload and restart every time a new character arrives. A time-out sets the
Receiver Time-out bit in CSR (CSR.TIMEOUT). An interrupt request is generated if the Receiver
Time-out bit in the Interrupt Mask Register (IMR.TIMEOUT) is set. Cle aring TIMEOUT can be
done in two ways:
• Writing a one to the Start Time-out bit (CR.STTTO). This also aborts count down until the
next character has been receiv ed.
• Writing a one to the Reload and Start Time-out bit (CR.RETTO). This also reloads the
counter and restarts count down immedia tely.
Figure 25-10. Receiver Time-out Block Diagram
Table 25-6. Maximum Time-out Period
Baud Rate (bit/sec) Bit Time (µs) Time-out (ms)
600 1 667 109 225
1 200 833 54 613
2 400 417 27 306
4 800 208 13 653
9 600 104 6 827
14400 69 4 551
19200 52 3 413
28800 35 2 276
33400 30 1 962
56000 18 1 170
57600 17 1 138
200000 5 328
16-bit Time-out
Counter
0
TO
TIMEOUT
Baud Rate
Clock
=
Character
Received
RETTO
Load
Clock
16-bit
Value
STTTO
DQ
1
Clear
557
32072H–AVR32–10/2012
AT32UC3A3
25.6.3.5 Framing Error
The receiver is capable of detecting framing errors. A framing error has occurred if a stop bit
reads as zero. This can occur if the transmitter and receiver are not synchronized. A framing
error is reported by CSR.FRAME as soon as the error is detected, at the middle of the stop bit.
An interrupt request is generated if the Framing Error bit in the Interrupt Mask Register
(IMR.FRAME) is set. CSR.FRAME is clea re d by writin g a one to CR.RSTSTA.
Figure 25-11. Framing Error Status
25.6.3.6 Transmit Break
When CSR.TXRDY is set, the user can request the transmitter to generate a break condition on
the TXD line by writing a one to th e Star t Br eak bit (CR. ST TBRK). The break is t reat ed as a nor-
mal 0x00 character t ransmission, cle aring CSR. TXRDY and CSR.TXEMPT Y, but wit h zero es for
preambles, start, parity, stop, and time guard bits. Writing a one to the Stop Break bit (CR.STT-
BRK) will stop the genera tion of new brea k charact ers, and se nd ones for TG dur ation or at least
12 bit periods, ensuring that the receiver detects end of break, before resuming normal opera-
tion. Figure 25-12 illustrates CR.STTBRK and CR.STPBRK effect on the TXD line.
Writing to CR.STTBRK and CR.STPBRK simultaneously can lead to unpredictable results.
Writes to THR before a pending break has started will be ignored.
Figure 25-12. Break Transmission
D0 D1 D2 D3 D4 D5 D6 D7
RXD
Start
Bit Parity
Bit Stop
Bit
Baud Rate
Clock
Write
CR
FRAME
RXRDY
RSTSTA = 1
D0 D1 D2 D3 D4 D5 D6 D7
TXD
Start
Bit Parity
Bit Stop
Bit
Baud Rate
Clock
Write
CR
TXRDY
TXEMPTY
STPBRK = 1
STTBRK = 1
Break Transmission End of Break
558
32072H–AVR32–10/2012
AT32UC3A3
25.6.3.7 Re ceive Break
A break condition is assumed when incoming data, parity, and stop bits are zero. This corre-
sponds to a framing error, but CSR.FRAME will remain zero while the Break Received/End of
Break bit (CSR.RXBRK) is set. An interrupt request is generated if the Breadk Received/End of
Break bit in the Interrupt Mask Register is set (IMR.RXBRK). Writing a one to CR.RSTSTA will
clear CSR.RXBRK. An end of break will also set CSR.RXBRK, and is assumed when TX is high
for at least 2/16 o f a bit period in asynch ronous mode, or wh en a high level is sampled in syn-
chronous mode.
25.6.4 Baud Rate Gene rat or
The baud rate generator provides the bit period clock nam ed the Baud Rate Clock to both
receiver and transmitter. It is based on a 16-bit divider, which is specified in the Clock Divider
field in the Baud Rate Generator Register (BRGR.CD). A non-zero value enables the generator,
and if BRGR.CD is one, the divider is bypassed and inactive. The Clock Selection field in the
Mode Register (MR.USCLKS) selects clock source between:
• CLK_USART (internal clock, refer to Power Manager chapter for details)
• CLK_USART/DIV (a di vided CLK_USART, refer to Module Configuration section)
• CLK (external clock, available on the CLK pin)
If the external clock CLK is se lected, the duration of the low and high levels of the signal pro-
vided on the CLK pin must be at least 4. 5 times longer than those provided by CLK_USART.
Figure 25-13. Baud Rate Generator
25.6.4.1 Baud Rate in Asynchronous Mode
If the USART is configured to operate in asynchro nous mode (MR.SYNC is zero), the selected
clock is divided by the BRGR.CD value before it is provided to the receiver as a sampling clock.
Depending on the Oversampling Mode bit (MR.OVER) value, the clock is then divided by either
8 (MR.OVER=1), or 16 (MR.O VER=0). The baud rate is calculated with the following formula:
16-bit Counter
CD
USCLKS
CD
CLK_USART
CLK_USART/DIV
Reserved
CLK
SYNC
SYNC
USCLKS= 3
FIDI
OVER
Sampling
Divider
BaudRate
Clock
Sampling
Clock
1
0
0
CLK
0
1
2
3
>1
1
1
0
0
BaudRate SelectedClock
82 OVER–()CD()
------------------------------------------------=
559
32072H–AVR32–10/2012
AT32UC3A3
This gives a maximum baud rate of CLK_USART divided by 8, assuming that CLK_USART is
the fastest clock availa ble , an d th at MR.O VER is on e.
25.6.4.2 Baud Rate Calculation Example
Table 25-7 shows calcula tions based on the CD f ield t o ob ta in 38400 baud from dif f erent so ur ce
clock frequencies. This table also shows the actual resulting baud rate and error.
The baud rate is calculated with the following formula (MR.OVER=0):
The baud rate error is calculated with the following formula. It is not recommended to work with
an error higher than 5%.
25.6.4.3 Fractional Baud Rate in Asynchronous Mode
The baud rate generator has a limitation: the source frequency is always a multiple of the baud
rate. An approac h to this problem is to inte grate a high resolution frac tional N clock generator,
outputting fractional multiples of the reference source clock. This fractional part is selected with
Table 25-7. Baud Rate Example (OVER=0)
Source Clock (Hz) Expected Baud
Rate (bit/s) Calculation Result CD Actual Baud Rate (bit/s) Error
3 686 400 38 400 6.00 6 38 400.00 0.00%
4 915 200 38 400 8.00 8 38 400.00 0.00%
5 000 000 38 400 8.14 8 39 062.50 1.70%
7 372 800 38 400 12.00 12 38 400.00 0.00%
8 000 000 38 400 13.02 13 38 461.54 0.16%
12 000 000 38 400 19.53 20 37 500.00 2.40%
12 288 000 38 400 20.00 20 38 400.00 0.00%
14 318 180 38 400 23.30 23 38 908.10 1.31%
14 745 600 38 400 24.00 24 38 400.00 0.00%
18 432 000 38 400 30.00 30 38 400.00 0.00%
24 000 000 38 400 39.06 39 38 461.54 0.16%
24 576 000 38 400 40.00 40 38 400.00 0.00%
25 000 000 38 400 40.69 40 38 109.76 0.76%
32 000 000 38 400 52.08 52 38 461.54 0.16%
32 768 000 38 400 53.33 53 38 641.51 0.63%
33 000 000 38 400 53.71 54 38 194.44 0.54%
40 000 000 38 400 65.10 65 38 461.54 0.16%
50 000 000 38 400 81.38 81 38 580.25 0.47%
60 000 000 38 400 97.66 98 38 265.31 0.35%
BaudRate CLK_USART
CD 16⋅
-----------------------------------=
Error 1ExpectedBaudRate
ActualBaudRate
---------------------------------------------------
⎝⎠
⎛⎞
–=
560
32072H–AVR32–10/2012
AT32UC3A3
the Fractional Part field in BRGR (BRGR.FP), and is activated by giving it a non-zero value. The
resolution is one eighth of CD. The resulting baud rate is calculated using the following formula:
The modified architecture is shown in Figure 25-14.
Figure 25-14. Fractional Baud Rate Generator
25.6.4.4 Baud Rate in Synchronous and SPI Mode
If the USART is configured to operate in synchronous mode (MR.SYNC is one), the selected
clock is divided by BRGR.CD. This does not apply when the external clock CLK is selected.
When CLK is selected , the fr equen cy of the exte rnal clock m ust be at leas t 4.5 tim es lower th an
the system clock, and when either CLK or CLK_USART/DIV are selected, BRGR.CD must be
even to ensure a 50/50 duty cycle. If CLK_USART is selected, the generator ensures this
regardless of value.
25.6.5 RS485 Mode The USART feature s an RS485 mode, supporting line driver control. This supplements nor mal
synchronous and asynchronous mode by driving the RTS pin high when the transmitter is oper-
ating. The RTS pin level is the inverse of the CSR.TXEMPTY value. The RS485 mode is
enabled by writing 0x1 to MR.MODE. A typical connection to a RS485 bus is shown in Figure
25-15.
BaudRate SelectedClock
82 OVER–()CD FP
8
-------+
⎝⎠
⎛⎞
⎝⎠
⎛⎞
--------------------------------------------------------------------=
USCLKS CD Modulus
Control
FP
FP
CD
glitch-free
logic
16-bit Counter
OVER SYNC
Sampling
Divider
CLK_USART
CLK_USART/DIV
Reserved
CLK
CLK
BaudRate
Clock
Sampling
Clock
SYNC
USCLKS = 3
>1
1
2
3
0
0
1
0
1
1
0
0
BaudRate SelectedClock
CD
--------------------------------------=
561
32072H–AVR32–10/2012
AT32UC3A3
Figure 25-15. Typical Connection to a RS485 Bus
If a timeguard has been configured the RTS pin will remain high for the duration specified in TG,
as shown in Figure 25-16.
Figure 25-16. Example of RTS Drive with Timeguard Enabled
25.6.6 Hardware Handshaking
The USART features an out-of-band hardware handshaking flow control mechanism, imple-
mentable by connecting the RTS and CTS pins with the remote device, as shown in Figure 25-
17.
Figure 25-17. Connection with a Remote Device for Hardware Handshaking
USART
RTS
TXD
RXD
Differential
Bus
D0 D1 D2 D3 D4 D5 D6 D7
TXD
Start
Bit Parity
Bit Stop
Bit
Baud Rate
Clock
TG = 4
Write
THR
TXRDY
TXEMPTY
RTS
USART
TXD
CTS
Remote
Device
RXD
TXDRXD
RTS
RTS
CTS
562
32072H–AVR32–10/2012
AT32UC3A3
Writing 0x2 to the MR.MODE field configures the USART to operate in hardware handshaking
mode. The receiver will drive its RTS pin high when disabled or when the Reception Buffer Full
bit (CSR.RXBUFF) is set by the Buffer Full signal from the Peripheral DMA controller. If the
receiver RTS pin is high, the transmitter CTS pin will also be high and only the active character
transmissions will be completed. Allocating a new buffer to the DMA controller by clearing
RXBUFF, will drive the RTS pin low, allowing the transmitter to resume transmission. Detected
level changes on the CTS pin are reported by the CTS Input Change bit in the Channel Status
Register (CSR.CTSIC). An interrupt request is generated if the Input Change bit in the Interrupt
Mask Register is set. CSR.CTSIC is cleared when reading CSR.
Figure 25-18 illustrates receiver functionality, and Figure 25-19 illustrates transmitter
functionality.
Figure 25-18. Receiver Behavior when Operating with Hardware Handshaking
Figure 25-19. Transmitter Behavior when Operating with Hardware Handshaking
25.6.7 Modem Mode The USART features a modem mode, supporting asynchronous communication with the follow-
ing signal pins: Data Terminal Ready (DTR), Data Set Ready (DSR), Request to Send (RTS),
Clear to Send (CTS), Data Carrier Detect (DCD), and Ring Indicator (RI). Modem mode is
enabled by writing 0x3 to MR.MODE. The USART will behave as a Data Terminal Equipment
(DTE), controlling DTR and RTS, while detecting level changes on DSR, DCD, CTS, and RI.
Table 25-8 shows USART signal pin s with the correspo nding standardize d modem connections.
RTS
R
XBUFF
Write
CR
RXEN = 1
RXD RXDIS = 1
CTS
TXD
Table 25-8. Circuit References
USART Pin V.24 CCITT Direction
TXD 2 103 From terminal to modem
RTS 4 105 From terminal to modem
DTR 20 1 08.2 From terminal to modem
RXD 3 104 From modem to terminal
CTS 5 106 From terminal to modem
563
32072H–AVR32–10/2012
AT32UC3A3
The DTR pin is controlled by the DTR enable and disable bits in CR (CR.DTREN and
CR.DTRDIS). Writing a one to CR.DTRDIS drives DTR high, and writing a one to CR.DTREN
drives DTR low. The RTS pin is controlled automatically.
Detected level changes are reported by the respective Input Change bits in CSR (CSR.RIIC,
CSR.DSRIC, CSR.DCDIC, and CSR.CTSIC). An interrupt request is generated if the corre-
sponding bit in the Interrupt Mask Register is set. The Input Change bits in CSR are
automatically cleared when CSR is read. When the CTS pin goes high, the USART will wait for
the transmitter to comple te any o ngo ing chara cte r tra nsmission bef ore au to matically disab ling it .
25.6.8 ISO7 816 M ode The USART features an ISO7816 compat ible mode, enablin g interfacing with smart ca rds and
Security Access Modules (SAM) through an ISO7816 compliant link. T=0 and T=1 protocols, as
defined in the ISO7816 standard, are supported. The ISO7816 mode is selected by writing the
value 0x4 (T=0 protocol) or 0x6 (T=1 protocol) to MR.MODE.
25.6.8.1 ISO 7 81 6 M od e Overview
ISO7816 specifies half duplex communication on one bidirectional line. The baud rate is a frac-
tion of the clock provide d by the master on the CLK pin (see ”Bau d Rate Generator” on page
558). The USART connects to a smart card as shown in Figu re 25-20. The TXD pin is bidirec-
tional and is routed to the receiver when the transmitter is disabled. Having both receiver and
transmitter enabled simultaneously may lead to unpredictable result s.
Figure 25-20. USART (Master) Connected to a Smart Card
In both T=0 and T=1 modes, the character format is fixed to eight data bits, and one or two stop
bits, regardless of CHRL, MODE9, and CHMODE values. Parity according to specification is
even. If the inverse transmission format is used, where payload data bits are transmitted
inverted on the I/O line, the user can use odd parity and perform an XOR o n data headed to
THR and coming from RHR.
25.6.8.2 Baud Rate in ISO 7816 Mode
The ISO7816 specification defines the bit rate with the following formula:
where:
DSR 6 107 From terminal to modem
DCD 8 109 From terminal to modem
RI 22 125 From terminal to mo dem
Table 25-8. Circuit References
USART Pin V.24 CCITT Direction
CLK
TXD
USART
CLK
I/O
Smart
Card
BDi
Fi
------f×=
564
32072H–AVR32–10/2012
AT32UC3A3
• B is the bit rate
• Di is the bit-rate adjustment factor
• Fi is the clock frequency division factor
• f is the ISO7816 clock frequency (Hz)
Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 25-9.
Fi is a binary value encoded on a 4-bit field, named FI, as represented in Table 25-1 0 .
Table 25-11 shows the resulting Fi/Di ratio, which is the ratio between the ISO7816 clock and
the Baud Rate Clock.
The clock selected by MR.USCLKS can be output on the CLK pin to feed the smart card clock
inputs. To output the clock, the user must write a one to the Clock Output Select bit in MR
(MR.CLKO). The clock is divided by BRGR.CD before it is output on the CLK pin. If CLK is
selected as clock source in MR.USCLKS, the clock can not be output on the CLK pin.
The selected clock is divided by the FI Over DI Ratio Value field in the FI DI Ratio Register
(FIDI.FI_DI_RATIO), which can be up to 2047 in ISO7816 mode. This will be rounded off to an
integral so the user has to se lect a FI_DI_RATIO value that comes as close as possible to the
expected Fi/Di ratio. The FI_DI_RATIO reset value is 0x174 (372 in decimal) and is the most
common divider be tween the ISO7816 clock and bit ra te (Fi=3 72, Di=1). Fi gure 25- 21 shows the
relationship between the Elementary Time Unit (ETU), corresponding to a bit period, and the
ISO 7816 clock.
Table 25-9. Binary and Decimal Values for Di
DI field 0001 0010 0011 0100 0101 0110 1000 1001
Di (decimal)1 2 4 8 163212 20
Table 25-10. Binary and Decimal Values for Fi
FI field 0000 0001 0010 0011 01 00 0101 0110 1001 1010 1011 1100 1101
Fi (decimal 372 372 558 744 1116 1488 1860 512 768 1024 1536 2048
Table 25-11. Possible Values for the Fi/Di Ratio
Fi 372 558 744 1116 1488 1860 512 768 1024 1536 2048
Di=2 186 279 372 558 744 930 256 384 512 768 1024
Di=4 93 139.5 186 279 372 465 128 192 256 384 512
Di=8 46.5 69.75 93 139.5 186 232.5 64 96 128 192 256
Di=16 23.25 34.87 46.5 69.75 93 116.2 32 48 64 96 128
Di=32 11.62 17.43 23.25 34.87 46.5 58.13 16 24 32 48 64
Di=12 31 46.5 62 93 124 155 42.66 64 85.33 128 170.6
Di=20 18.6 27.9 37.2 55.8 74.4 93 25.6 38.4 51.2 76.8 102.4
565
32072H–AVR32–10/2012
AT32UC3A3
Figure 25-21. Elem en tary T ime Unit (ET U)
25.6.8.3 Protocol T=0In T=0 protoc ol, a c haracte r is made up of on e star t bit, eight data bits, one parity bit, and a two
bit period guard time . Duri ng t he guard time , th e line will be high if the receiver does not signal a
parity error, as shown in Figure 25-22. The receiver signals a parity error, aka non-acknowledge
(NACK), by pulling the line low for a bit period within the guard time, resulting in the total charac-
ter length be ing incre mente d by one, see Figu re 25- 23. The USART will not load data to RHR if
it detects a parity error, and will set PARE if it receives a NACK.
Figure 25-22. T=0 Protocol without Parity Error
Figure 25-23. T=0 Protocol with Parity Error
25.6.8.4 Protocol T=1In T=1 protocol, the character resembles an asynchronous format with only one stop bit. The
parity is generated when transmitting and checked when receivin g. Parity errors set PARE.
25.6.8.5 Re ceive Error Counter
The USART receiver keeps count of up to 255 errors in the Number Of Errors field in the Num-
ber of Error Register (NER.NB_ERRORS). Reading NER automatically clears NB_ERRORS.
25.6.8.6 Rece ive NACK Inhibi t
The USART can be configured to ignore parity errors by writing a one to the Inhibit Non
Acknowledge bit (MR.INACK). Erroneous characters will be treated as if they were ok, not gen-
erating a NACK, loaded to RHR, and raising RXRDY.
1 ETU
FI_DI_RATIO
ISO7816 Clock Cycles
ISO7816 Clock
on CLK
ISO7816 I/O Line
on TXD
D0 D1 D2 D3 D4 D5 D6 D7
RXD
Parity
Bit
Baud Rate
Clock
Start
Bit Guard
Time 1 Next
Start
Bit
Guard
Time 2
D0 D1 D2 D3 D4 D5 D6 D7
I/O
Parity
Bit
Baud Rate
Clock
Start
Bit Guard
Time 1 Start
Bit
Guard
Time 2 D0 D1
Error
Repetition
566
32072H–AVR32–10/2012
AT32UC3A3
25.6.8.7 Transmit Character Repetition
The USART can be configured to automatically re-send a character if it receives a NACK. Writ-
ing a non-zero value to MR.MAX_ITERATION will enable and determine the number of
consecutive re-transmissions. If the number of unsuccessful re-transmissions equals
MAX_ITERATION, the itera tion bit (CSR.ITER) is set. An interrupt request is gene rated if the
ITER bit in the Interr up t M as k Reg ist er (IM R.ITER) is set. Writin g a o ne to th e Rese t It er at ion bit
(CR.RSTIT) will clear CSR.ITER.
25.6.8.8 Disable Successive Receive NACK
The receiver can limit the number of consecutive NACKs to the value in MR.MAX_ITERATION.
This is enabled by writing a one to t he Disab le Successive NACK bit (MR.DSNACK). If the num-
ber of NACKs is about to exceed MR.MAX_ITERATION, the character will instead be accepted
as valid and CSR.ITER is set.
25.6.9 IrDA Mode The USART features an IrDA mode, supporting asynchronous, half-duplex, point-to-point wire-
less communication. It embeds the modulator and demodulator, allowing for a glueless
connection to the infrared transceivers, as shown in Figure 25-24. The IrDA mode is enabled by
writing 0x8 to M R.MODE. This activates the Ir DA specification v1.1 compliant modem. Data
transfer speeds ranging from 2.4Kbit/s to 115.2Kbit/s are supported and the character format is
fixed to one start bit, eight data bits, and one stop bit.
Figure 25-24. Connection to IrDA Transceivers
The receiver and th e transmitter must be exclusively enabled or disabled, accor ding to the direc-
tion of the transmissio n. To receive IrDA signals, the following needs to be done:
• Disable TX and enable RX.
• Configure the TXD pin as an I/O , outputting z ero to a v oid LED activation. Disable the inte rnal
pull-up for improved power consumption.
• Receive data.
IrDA
Transceivers
RXD RX
TXD
TX
USART
Demodulator
Modulator
Receiver
Transmitter
567
32072H–AVR32–10/2012
AT32UC3A3
25.6.9.1 Ir DA Modulation
The RZI modulation scheme is use d, where a zero is represented by a light pulse 3/16 of a bit
period, and no pulse to represent a one. Some examples of signal pulse duration are shown in
Table 25-12.
Figure 25-25 shows an example of character transmission.
Figure 25-25. IrDA Modulation
25.6.9.2 Ir DA Baud Rate
As the IrDA mode shares some logic with the ISO7816 mode, the FIDI.FI_DI_RATIO field must
be configured correctly. See Section “25.6.16” on pa ge 5 83. Table 25-13 shows some examples
of BRGR.CD value s, baud r ate err or, and p ulse durat ion. No te that the maximal acceptable e rror
rate of ±1.87% must be met.
Table 25-12. IrDA Pulse Duration
Baud Rate Pulse Duration (3/16)
2.4 Kbit/s 78.13 µs
9.6 Kbit/s 19.53 µs
19.2 Kbit/s 9.77 µs
38.4 Kbit/s 4.88 µs
57.6 Kbit/s 3.26 µs
115.2 Kbit/s 1.63 µs
Bit Period Bit Period
3
16
Start
Bit Data Bits Stop
Bit
00
000
111 1
1
Transmitter
Output
TXD
Table 25-13. IrDA Baud Rate Error
Peripheral Clock Baud Rate CD Baud Rate Error Pulse Time
3 686 400 115 200 2 0.00% 1.63
20 000 000 115 200 11 1.38% 1.63
32 768 000 115 200 18 1.25% 1.63
40 000 000 115 200 22 1.38% 1.63
3 686 400 57 600 4 0.00% 3.26
20 000 000 57 600 22 1.38% 3.26
32 768 000 57 600 36 1.25% 3.26
40 000 000 57 600 43 0.93% 3.26
568
32072H–AVR32–10/2012
AT32UC3A3
25.6.9.3 Ir DA Demodulator
The demodulator depends on an 8-bit down counter loaded with the value in the IRDA_Filter
field in the IrDA Filter Register (IFR.IRDA_FILTER). When a falling edge on RXD is detected,
the counte r star ts decr ement ing at CLK_ USART speed . If a rising edge on RXD is de tecte d , the
counter stops and is relo aded wit h t he I rD Filt er value . If no risin g ed ge has b een de tect ed when
the counter reache s zero, the receiver input is pulled low d uring one bit period, see Figure 25-
26. Writing a one to the Infrared Receive Line Filter bit (MR.FILTER), enables a noise filter that,
instead of using just one sample, will choose the majority value from three consecutive samples.
Figure 25-26. IrDA Demodulator Operations
25.6.10 LIN Mode The USART features a Local Interco nnect Network (LIN) 1.3 and 2.0 compliant mode , embed-
ding full error checking and reporting, automatic frame processing with up to 256 data bytes,
customizable respon se data lengths, and requ iring minimal CPU resources. The LIN m ode is
enabled by writing 0xA (maste r) or 0xB (slave) to MR.MODE.
3 686 400 38 400 6 0.00% 4.88
20 000 000 38 400 33 1.38% 4.88
32 768 000 38 400 53 0.63% 4.88
40 000 000 38 400 65 0.16% 4.88
3 686 400 19 200 12 0.00% 9.77
20 000 000 19 200 65 0.16% 9.77
32 768 000 19 200 107 0.31% 9.77
40 000 000 19 200 130 0.16% 9.77
3 686 400 9 600 24 0.00% 19.53
20 000 000 9 600 130 0.16% 19.53
32 768 000 9 600 213 0.16% 19.53
40 000 000 9 600 260 0.16% 19.53
3 686 400 2 400 96 0.00% 78.13
20 000 000 2 400 521 0.03% 78.13
32 768 000 2 400 853 0.04% 78.13
Table 25-13. IrDA Baud Rate Error (Continued)
Peripheral Clock Baud Rate CD Baud Rate Error Pulse Time
CLK_USART
RXD
Counter
Value
Receiver
Input
654 63
Pulse
Rejected
26453210
Pulse
Accepted
Driven Low During 16 Baud Rate Clock Cycles
569
32072H–AVR32–10/2012
AT32UC3A3
25.6.10.1 Modes of Operation
Changing LIN mode after initial configuration must be followed by a tran scei ve r so ftwar e r eset in
order to avoid unpredictable behavior.
25.6.10.2 Receiver and Transmitter Control
See Section “25.6.2.1” on page 551.
25.6.10.3 Baud Rate Configuration
The LIN nodes b aud rate is configu red in the Baud Rate Generato r Register (BRG R), See Sec-
tion “25.6 .4.1” on page 558.
25.6.10.4 Character Transmission and Reception
See ”Transmitter Operations” on page 551, and ”Receiver Operations” on page 553.
25.6.10.5 Header Transmission (Master Node Configuration)
All LIN frames start with a header sent by the master. As soon as the identifier has been written
to the Identifier Character field in the LIN Identifier Register (LINIR.IDCHR), C SR.TXRDY is
cleared and the header is sent. The header consists of a Break field, a Sync field, and an Identi-
fier field. CSR.TXRDY is set when the identifier has been transferred into the transmitters shift
register. An interrupt request is generated if IMR.TXRDY is set.
The Break field consists of 13 dominant bits (the break) and one recessive bit (the break delim-
iter). The Sync field consists of a start bit, th e Sync byte (the character 0x55), and a stop bit,
refer to Figure 25-29. The Identifier field contains the Identifier as written to LINIR.IDCHR. The
identifier parity bits can be generated automatically (see Section 25.6.10.8).
Figure 25-27. Header Transmission
See also ”Master Node Configuration” on page 574.
25.6.10.6 Header Reception (Slave Node Configuration)
The USART stays idle until it detects a break field, consisting of at least 11 consecutive domi-
nant bits (zeroes) on the bus. The Sync field is used to synchronize the baud rate (see Section
25.6.10.7). IDCHR is updated and the LIN Identifier bit (CSR.LINIR) is set when the Identifier
has been received. An interrupt request is generated if the Lin Identifier bit in the Interrupt Mask
Register (IMR.LINIR) is set. The Identifier parity bits can be automatically checked (see Section
25.6.10.8). Writing a one to CR.RSTSTA will clear CSR.LINIR.
TXD
Baud Rate
Clock
Start
Bit
Write
LINIR
10101010
TXRDY
Stop
Bit Start
Bit ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7Break Field
13 dominant bits (at 0)
Stop
Bit
Break
Delimiter
1 recessive bit
(at 1)
Synch Byte = 0x55
LINIR ID
570
32072H–AVR32–10/2012
AT32UC3A3
Figure 25-28. Header Reception
See also ”Slave Node Configuration” on page 576.
25.6.10.7 Slave Node Synchronization
Synchronization is only done by the slave. If the Sync byte is not 0x55, an Inconsistent Sync
Field error is generated, and the LIN Inconsistend Sync Field Error bit in CSR (CSR.LINISFE) is
set. An interrupt request is ge nerated if the LINISFE bi t in IMR is set. CSR. LINISFE is cleared by
writing a one to CR.RSTSTA. The time between falling edges is measured by a 19-bit counter,
driven by the sampling clock (see Section 25.6.4).
Figure 25-29. Sync Field
The counter starts when th e Sync field start bit is detecte d, and continues for e ight bit periods.
The 16 most significant bits (counter value divided by 8) becomes the new clock divider
(BRGR.CD), and the three least significant bits (the remainder) becomes the new fractional part
(BRGR.FP).
Figure 25-30. Slave Node Synchronization
The synchronization accuracy depends on:
Break Field
13 dominant bits (at 0)
Break
Delimiter
1 recessive bit
(at 1)
Start
Bit 10101010
Stop
Bit
Start
Bit ID0 ID1 ID2 ID4ID3 ID6ID5 ID7 Stop
Bit
Synch Byte = 0x55
Baud Rate
Clock
RXD
Write US_CR
With RSTSTA=1
US_LINIR
LINID
Start
bit Stop
bit
Synch Field
8 Tbit
2 Tbit 2 Tbit 2 Tbit 2 Tbit
RXD
Baud Rate
Clock
LINIDRX
Synchro Counter 000_0011_0001_0110_1101
BRGR
Clcok Divider (CD) 0000_0110_0010_1101
BRGR
Fractional Part (FP) 101
Initial CD
Initial FP
Reset
Start
Bit 10101010
Stop
Bit Start
Bit ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7Break Field
13 dominant bits (at 0)
Stop
Bit
Break
Delimiter
1 recessive bit
(at 1)
Synch Byte = 0x55
571
32072H–AVR32–10/2012
AT32UC3A3
• The theoretical slav e node clock fre quency; nominal clock fre quency (FNom)
• The baud rate
• The oversampling mode (OVER=0 => 16x, or OVER=1 => 8x)
The following formula is used to calculate synchronization deviation, where FSLAVE is the real
slave node clock frequency, an d FTOL_UNSYNC is the diff erence between FNom and FSLAVE. Accord-
ing to the LIN specification, FTOL_UNSYNCH may not exceed ±15%, and the bit rates between two
nodes must be within ±2% of each other, resulting in a maximal BaudRate_deviation of ±1%.
Minimum nominal clock frequency with a fractional part:
Examples:
• Baud rate = 20 kbit/s, OVER=0 (Oversampling 16 x) => FNom(min) = 2.64 MHz
• Baud rate = 20 kbit/s, OVER=1 (Oversampling 8x) => FNom(min) = 1.47 MHz
• Baud rate = 1 kbit/ s, OVER=0 (Oversampling 16x) => FNom(min) = 132 kHz
• Baud rate = 1 kbit/s, OVER=1 (Ov ersampling 8x) => FNom(min) = 74 kHz
If the fractio nal pa rt is n ot used, the synchr oniza tio n accura cy is much lo wer. T he 16 most signi f-
icant bits, added with the first least significant bit, becomes the new clock divider (CD). The
equation of the baud rate deviation is the same as above, but the constants are:
Minimum nominal cloc k frequency without a fractional part:
Examples:
• Baud rate = 20 kbit/s, OVER=0 (Oversampling 16 x) => FNom(min) = 19.12 MHz
• Baud rate = 20 kbit/s, OVER=1 (Oversampling 8x) => FNom(min) = 9.71 MHz
• Baud rate = 1 kbit/ s, OVER=0 (Oversampling 16x) => FNom(min) = 956 kHz
• Baud rate = 1 kbit/s, OVER=1 (Ov ersampling 8x) => FNom(min) = 485 kHz
25.6.10.8 Identifier Parity
An identifier field consists of two sub-fields; the identifier and its parity. Bits 0 to 5 are assigned
to the identifier, while bits 6 and 7 are assigned to parity. Automatic parity management is
BaudRate_deviation 100 α[ 8 2 OVER–()β+]BaudRate××× 8F
SLAVE
×
---------------------------------------------------------------------------------------------------
×
⎝⎠
⎛⎞
%=
BaudRate_deviation 100 α[ 8 2 OVER–()β+]BaudRate×××
8FTOL_UNSYNC
100
------------------------------------
⎝⎠
⎛⎞
xFNom
×
---------------------------------------------------------------------------------------------------
×
⎝⎠
⎜⎟
⎜⎟
⎜⎟
⎛⎞
%=
0,5–α+0,5 -1 β+1<<≤≤
FNom min() 100 0,5 8 2 OVER–()×× 1+[]BaudRate×
815–
100
----------1+
⎝⎠
⎛⎞
×1%×
-------------------------------------------------------------------------------------------------------
×
⎝⎠
⎜⎟
⎜⎟
⎜⎟
⎛⎞
Hz=
4–α+4 -1 β+1<<≤≤
FNom min() 100 48 2OVER–()×× 1+[]Baudrate×
815–
100
----------1+
⎝⎠
⎛⎞
×1%×
-----------------------------------------------------------------------------------------------
×
⎝⎠
⎜⎟
⎜⎟
⎜⎟
⎛⎞
Hz=
572
32072H–AVR32–10/2012
AT32UC3A3
enabled by default, and can be disabled by writing a one to the Parity Disable bit in the LIN
Mode register (LINMR.PARDIS).
• LINMR.PARDIS=0: During header transmission, the parity bits are computed and in the shift
register the y repla ce bits 6 and 7 from LI NIR.IDCHR. During header rece ption, th e parity bits
are checked and can generate a LIN Identifi er Parity Error (see Section 25.6.10.13). Bits 6
and 7 in LINIR.IDCHR read as zero when receiving.
• LINMR.PARDIS=1: During header transmission, all the bit s in LINIR.IDCHR are sent on the
bus. During header reception, all the bits in LINIR.IDCHR are updated with the received
Identifier.
25.6.10.9 Node Action After an identifier transaction, a LIN response mode must be selected. This is done in the Node
Action field (LINMR.N ACT). Below a re some r esponse mode s exemplifie d in a sma ll LIN cluste r:
• Response, from master to slave1:
Master: NACT=PUBLISH
Slave1: NACT=SUBSCRIBE
Slave2: NACT=IGNOR E
• Response, from slave1 to master:
Master: NACT=SUBSCRIBE
Slave1: NACT=PUBLISH
Slave2: NACT=IGNOR E
• Response, from slave1 to slave2:
Master: NACT=IGNORE
Slave1: NACT=PUBLISH
Slave2: NACT=SUBSCRIBE
25.6.10.10 LIN Response Data Length
The response data length is the number of data fields (byt es), excluding the checksum.
Figure 25-31. Response Data Length
The response data length can be configured, either by the user, or automatically by bits 4 and 5
in the Identifier (LINIR.IDCHR), in accordance to LIN 1.1. The user selects one of these modes
by writing to the Data Length Mode bit (LINMR.DLM):
• LINMR.DLM=0: the response data lengt h is configured b y the user b y writing to the 8- bit Data
Length Control field (LINMR.DLC). The response data length equals DLC + 1 bytes.
User configuration: 1 - 256 data fields (DLC+1)
Identifier configuration: 2/4/8 data fields
Sync
Break Sync
Field Identifier
Field Checksum
Field
Data
Field Data
Field Data
Field Data
Field
573
32072H–AVR32–10/2012
AT32UC3A3
• LINMR.DLM=1: the response data length is defined by the Identifier (LINIR.IDCHR) bits
according to the table below.
25.6.10.11 Checksum The last frame field is the checksum. It is configured by the Checksum Type (LINMR.CHKTYP),
and the Checksum Disable (LINMR.CHKDIS) bits. CSR.TXRDY will not be set after the last THR
data write if enabled. Writing a one to LINMR.CHKDIS will disable the automatic checksum gen-
eration/checking, and the user may send/check this last byte manually, disguised as a normal
data. The checksum is an inverted 8-bit sum with carry, either:
• Ov er all data b ytes , called a classic checksum. This is used for LIN 1.3 compliant sla v es , a nd
automatically managed when CHKDIS=0, and CHKTYP=1.
• Over all data bytes and the protected identifier, called an enhanced checksum. This is used
for LIN 2.0 compliant slaves, and automatically managed when CHKDIS=0, and CHKTYP=0.
25.6.10.12 Frame Slot Mode
A LIN master can be configured to use frame slots with a pre-defined minimum length. This
Frame Slot mode is enabled by default, and is disabled by writing a one to the Frame Slot Mode
Disable bit (LIN MR.FSDIS). The Frame Slot mode will not allow CSR.TXRDY to be set after a
frame transfer until the entire frame slot duration has elapsed, in effect preventing the master
from sending a new header. The LIN Transfer Complete bit (CSR.LINTC) will still be set after the
checksum has been sent. An interrupt is generated if the LIN Transfer Complete bit in the Inter-
rupt Mask Register (IMR.LIN TC) is set. Writing a one to CR.RSTSTA clears CSR.LINTC.
Figure 25-32. Frame Slot Mode with Automatic Checksum
Table 25-14. Response Data Length if DLM = 1
LINIR.IDCHR[5] LINIR.IDCHR[4] Response Data Length [bytes]
00 2
01 2
10 4
11 8
Break Synch Protected
Identifier Data N Checksum
Header
Inter-
frame
space
Response
space
Frame
Frame slot = TFrame_Maximum
Response
TXRDY
Write
THR
Write
LINID
Data 1 Data 2 Data 3
Data3
Data N-1
Data N
Frame Slot Mode
Disabled Frame Slot Mode
Enabled
LINTC
Data 1
574
32072H–AVR32–10/2012
AT32UC3A3
The minimum frame slot size is d eter mined b y TFr ame_M aximum, and calcula ted below (all val-
ues in bit periods):
• T Header_Nominal = 34
• TFrame_Maximum = 1.4 x (THeader_Nominal + TResponse_Nominal + 1)
Note: The term “+1” leads to an integer result for TFrame_Max (LIN Specifi c ation 1.3)
If the Checksum is sent (CHKDIS=0):
• TResponse_Nominal = 10 x (NData + 1)
• TFrame_Maximum = 1.4 x (34 + 10 x (DLC + 1 + 1) + 1)
• TFrame_Maximum = 77 + 14 x DLC
If the Checksum is not sent (CHKDIS=1):
• TResponse_Nominal = 10 x NData
• TFrame_Maximum = 1.4 x (34 + 10 x (DLC + 1) + 1)
• TFrame_Maximum = 63 + 14 x DLC
25.6.10.13 LIN Errors This section describes the errors generated in LIN mode, and the coresponding error bits in
CSR. The error bits are cleared by writing a one to CR.RSTSTA. An interrupt request is gener-
ated if the corresponding bit in the Interrupt Mask Register (IMR) is set. This bit is set by writing
a one to the corresponding bit in the Interrupt Enable Register (IER).
• Slave Not Responding Error (CSR.LINSNRE)
– This error is gen erated if no valid message appears within the TFrame_Maximum
time frame slot, while the USART is expecting a response from another node
(NACT=SUBSCRIBE).
• Checksum Error (CSR.LINCE)
– This error is generated if the received checksum is wrong. This error can only be
generat ed if the checksum feature is enabled (CHKDIS=0).
• Identifier Parity Error (CSR.LINIPE)
– This error is gen erated if the identifier parity is wrong. This error can only be
generated if parity is enabled (PARDIS=0).
• Inconsistent Sync Field Error (CSR.LINISFE)
– This error is generated in slave mode if the Sync Field characte r received is not
0x55. Synchronization procedure is aborted.
• Bit Error (CSR.LINBE)
– This error is generated if the value tr ansmitted by the USART on Tx differs from the
value sampled on Rx. If a bit error is detected, the transm ission is aborted at the
next byte border.
25.6.11 LIN Frame Handling
25.6.11.1 Master Node Configuration
• Configure the baud rate by writing to BRGR.CD and BRGR.FP
• Configure the frame transfer by writing to the LINMR fields NACT, PARDIS, CHKDIS,
CHKTYPE, DLM, FSDIS, and DLC
• Select LIN mode and master node by writing 0xA to MR.MODE
575
32072H–AVR32–10/2012
AT32UC3A3
• Write a one to CR.TXEN and CR.RXEN to enable both transmitter and receiver
• Wait until CSR.TXRDY is one
• Send the header b y writing to LINIR.IDCHR
The following procedure depends on the LINMR.NACT setting:
• Case 1: LINMR.NACT is 0x0 (PUBLISH, the USART transmits the response)
– Wait until CSR.TXRDY is one
– Send a byte by writing to THR.TXCHR
– Repeat the two previous steps until there is no more data to send
– Wait until CSR.LINTC is one
– Check f or LIN errors
• Case 2: LINMR.NACT is 0x1 (SUBSCRIBE, the USART receives the response)
– Wait until CSR.RXRDY is one
– Read RHR.RXCHR
– Repeat the two previous steps until there is no more data to read
– Wait until CSR.LINTC is one
– Check f or LIN errors
• Case 3: LINMR.NACT is 0x2 (IGNORE, the USART is not concerned by a response)
– Wait until CSR.LINTC is one
– Check f or LIN errors
Figure 25-33. Master Node Configuration, LINMR.NACT is 0x0 (PUBLISH)
Frame
Break Synch Protected
Identifier Data 1 Data N Checksum
TXRDY
Write
THR
Write
LINIR
Data 1 Data 2 Data 3
Data N-1
Data N
RXRDY
Header
Inter-
frame
space
Response
space
Frame slot = TFrame_Maximum
Response
Data3
LINTC
FSDIS=1 FSDIS=0
576
32072H–AVR32–10/2012
AT32UC3A3
Figure 25-34. Master Node Configuration, LINMR.NACT is 0x1 (SUBSCRIBE)
Figure 25-35. Master Node Configuration, LINMR.NACT is 0x2 (IGNORE)
25.6.11.2 Slave Node Configuration
• Configure the baud rate by writing to BRGR.CD and BRGR.FP
• Configure the frame tr ansf er by writing to LINMR fields NA CT, PARDIS, CHKDIS, CHKTYPE,
DLM, and DLC
• Select LIN mode and slave node by writing 0xB to MR.MODE
• Write a one to CR.TXEN and CR.RXEN to enable both transmitter and receiver
• Wait until CSR.LINIR is one
• Chec k f or CSR.LINISFE and CSR.LINPE errors, clear errors and CSR.LINIR by writing a one
to CR.RSTSTA
• Read LINIR.IDCHR
IMPORTANT: If LINMR.NACT is 0x 0 (PUBLISH), and this field is a lready correct, the LINM R
register must still be written with this value in order to set CSR.TXRDY, and to request the corre-
sponding Peripheral DMA Controller write transfer.
Break Synch Protected
Identifier Data 1 Data N Checksum
TXRDY
Read
RHR
Write
LINIR
Data 1
Data N-1
Data N-1
RXRDY
Data NData N-2
Header
Inter-
frame
space
Response
space
Frame
Frame slot = TFrame_Maximum
Response
Data3
LINTC
FSDIS=0FSDIS=1
TXRDY
Write
LINIR
RXRDY
LINTC
Break Synch Protected
Identifier Data 1 Data N Checksum
Data N-1
Header
Inter-
frame
space
Response
space
Frame
Frame slot = TFrame_Maximum
Response
Data3
FSDIS=1 FSDIS=0
577
32072H–AVR32–10/2012
AT32UC3A3
The different LINMR.NACT settings result in the sam e procedure as for the master node, see
page 574.
Figure 25-36. Slave Node Configuration, LINMR.NACT is 0x0 (PUBLISH)
Figure 25-37. Slave Node Configuration, LINMR.NACT is 0x1 (SUBSCRIBE)
Figure 25-38. Slave Node Configuration, LINMR.NACT is 0x2 (IGNORE)
25.6.12 LIN Frame Handling With The Peripheral DMA Controller
The USART can be us ed together with the Periph eral DMA Controller in order to t ransfer data
without processor intervention. The Peripheral DMA Controller uses the CSR.TXRDY and
Break Synch Protected
Identifier Data 1 Data N Checksum
TXRDY
Write
THR
Read
LINID
Data 1 Data 3
Data N-1
Data N
RXRDY
LINIDRX
Data 2
LINTC
TXRDY
Read
RHR
Read
LINID
RXRDY
LINIDRX
LINTC
Break Synch Protected
Identifier Data 1 Data N Checksum
Data 1
Data N-1
Data N-1 Data NData N-2
T
XRDY
Read
RHR
Read
LINID
R
XRDY
L
INIDRX
L
INTC
Break Synch Protected
Identifier Data 1 Data N ChecksumData N-1
578
32072H–AVR32–10/2012
AT32UC3A3
CSR.RXRDY bits to trigger one byt e writes or reads. It always wr ites to THR, and it alw a ys reads
RHR.
25.6.12.1 Master Node Configuration
The Peripheral DMA Controller Mode bit (LINMR.PDCM) allows the user to select configuration:
• LINMR.PDCM=0: LIN configuration must be written to LINMR, it is not stored in the write
buffer.
• LINMR.PDCM=1: LIN configuration is written by t he Peripheral DMA Controller to THR, and
is stored in the write buffer. Since data transfer size is a byte, the transfer is split into two
accesses. The first writes the NA CT, PARDIS , CHKDIS, CHKTYP, DLM and FSDIS bits in the
LINMR register, while the second writes the LINMR.DLC field. If LINMR.NACT=PUBLISH,
the write buffer will also contain the Identifier.
When LINMR.NACT=SUBSCRIBE, the read buffer conta ins the data.
Figure 25-39. Master Node with Peripheral DMA Controller (LINMR.PDCM=0)
|
|
|
|
RXRDY
TXRDY
Peripheral
bus
USART LIN
CONTROLLER DATA 0
DATA N
|
|
|
|
READ BUFFER
NODE ACTION = PUBLISH NODE ACTION = SUBSCRIBE
Peripheral DMA
Controller
RXRDY
Peripheral
bus
DATA 0
DATA 1
DATA N
WRITE BUFFER
Peripheral DMA
Controller
USART LIN
CONTROLLER
579
32072H–AVR32–10/2012
AT32UC3A3
Figure 25-40. Master Node with Peripheral DMA Controller (LINMR.PDCM=1)
25.6.12.2 Slave Node Configuration
In this mode, the Pe ripheral DMA Controller transfe rs only data. The user reads the Ident ifier
from LINIR, and selects LIN mode by writing to LINMR. When NACT=PUBLISH the data is in the
write buffer, while the read buffer contains the data when NACT=SUBSCRIBE.
IMPORTANT: If in slave mode, LINMR.NACT is already configured correc tly as PUBLISH, the
LINMR register must still be written with this value in order to set CSR.TXRDY, and to request
the corresponding Peripheral DMA Controller write transfer.
Figure 25-41. Slave Node with Peripheral DMA Controller
25.6.13 Wake-up Request
Any node in a sleep ing LIN cluster may request a wake-up. By writing to the Wakeup Signal
Type bit (LINMR.WKUPTYP), the user can choose to send either a LIN 1.3 (WKUPTYP is one )
or a LIN 2.0 (WKUPTYP is zero) co mpliant wakeup request. Writing a one to the Send LIN
Wakeup Signal bit (CR.LINWKUP) , transmit s a wakeup, and when completed, sets CSR.LINTC.
|
|
|
|
|
|
|
|
NACT
PARDIS
CHKDIS
CHKTYP
DLM
FSDIS
DLC
IDENTIFIER
DATA 0
DATA N
WRITE BUFFER
RXRDY
Peripheral
bus
DLC
IDENTIFIER
DATA 0
DATA N
WRITE BUFFER
RXRDY
READ BUFFER
NODE ACTION = PUBLISH NODE ACTION = SUBSCRIBE
Peripheral DMA
Controller
Peripheral DMA
Controller
USART LIN
CONTROLLER
NACT
PARDIS
CHKDIS
CHKTYP
DLM
FSDIS
USART LIN
CONTROLLER
TXRDY
Peripheral
bus
|
|
|
|
|
|
|
|
DATA 0
DATA N
RXRDY
Per ipheral
Bus
READ BUFFER
NACT = SUBSCRIBE
DATA 0
DATA N
TXRDY
Per ipheral
bus
WRITE BUFFER
USART LIN
CONTROLLER USART LIN
CONTROLLER
Peripheral DMA
Controller
Peripheral DMA
Controller
580
32072H–AVR32–10/2012
AT32UC3A3
According to LIN 1.3, the wakeup request should be generated with the character 0x80 in order
to impose eight successive dominant bit s.
According to LIN 2.0, t he wakeup reque st is issued by forcing th e bus into t he dominant state for
250µs to 5ms. Sending the character 0xF0 does this, regardless of baud rate.
• Baud rate max = 20 kbit/s -> one bit period = 50µs -> five bit periods = 250µs
• Baud rate min = 1 kbit/s -> one bit period = 1ms -> five bit periods = 5ms
25.6.14 Bus Idle Time-out
LIN bus inactivity should eventually cause slaves to time out and enter sleep mode. LIN 1.3
specifies this to 25000 bit periods, whilst LIN 2.0 specifies 4 seconds. For the time-o ut counter
operation see Section 25.6.3.4 ”Receiver Time-out” on page 556.
25.6.15 SPI Mode The USART features a Serial Peripher al Interface (SPI) link compliant mode, supportin g syn-
chronous, full-duplex communication in both master and slave mode. Writing 0xE (master) or
0xF (slave) to MR.MODE will enable this mode. An SPI in master mode controls the data flow to
and from the other SPI devices, which are in slave mode. It is possible to let devices take turns
being masters (aka multi-master protocol), and one master may shift data simultaneously into
several slaves, but only one slave may respond at a time. A slave is selected when its slave
select (NSS) signal h as been ra ised by the mast er. The USART ca n only ge nerate one NSS sig-
nal, and it is possible to use standard I/O lines to address more than one slave.
25.6.15.1 Modes of Operation
The SPI system consists of two data lines and two control lines:
• Master Out Slave In (MOSI): This line supplies the data shifted from master to slave. In
master mode this is connected to TXD, and in slave mode to RXD.
• Master In Slave Out (MISO): This line supplies the data shifted from slave to master. In
master mode this is connected to RXD, and in slave mode to TXD.
• Serial Clock (CLK): This is controlled by the master. One period per bit transmission. In both
modes this is connected to CLK.
• Slave Select (NSS): This control line allows the master to select or deselect a slave. In
master mode this is connected to RTS, and in slave mode to CTS.
Changing SPI mode after initial configuration must be followed by a transceiver software reset in
order to avoid unpredictable behavior.
Table 25-15. Receiver Time-out Values (RTOR.TO)
LIN Specification Baud Rate Time-out period TO
2.0
1 000 bit/s
4s
4 000
2 400 bit/s 9 600
9 600 bit/s 38 400
19 200 bit/s 76 800
20 000 bit/s 80 000
1.3 - 25 000 bit periods 25 000
581
32072H–AVR32–10/2012
AT32UC3A3
25.6.15.2 Baud Rate The baud rate generator operates as described in ”Baud Rate in Synchronous and SPI Mode”
on page 560, with the following requirements:
In SPI Master Mode:
• External clock CLK must no t be selected as clock (the Clock Selection field (MR.USCLKS)
must not equal 0x3).
• The USART must drive the CLK pin (MR.CLKO must be one).
• The BRGR.CD field must be at least 0x4.
• If the internal divided clock, CLK_USART/DIV, is selected (MR.USCLKS is one), the value in
BRGR.CD must be even, ensuring a 50:50 duty cycle.
In SPI Slave Mode:
• The frequency of the external clock CLK must be at least four times lower than the system
clock.
25.6.15.3 Data TransferUp to nine data bits are successively shifted out on the TXD pin at each edge. There are n o
start, parity, or stop bits, and MSB is always sent first. The SPI Clock Polarity (MR.CPOL), and
SPI Clock Phase (MR.CPHA) bits configure CLK by selecting the edges upon which bits are
shifted and sampled, resulting in four non-inter operable protocol modes, see Table 25-16. If
MR.CPOL is zero, the inactive state value of CLK is logic level zero, and if MR.CPOL is one, the
inactive state value of CLK is logic level one. If MR.CPHA is z ero, data is change d on the lead-
ing edge of CLK, and captured on the following edge of CLK. If MR.CPHA is one, data is
captured on the leading edge of CLK, and changed on the following edge of CLK. A mas-
ter/slave pair must use the same configuration, and the master must be reconfigured if it is to
communicate with slaves using different configurations. See Figures 25-42 and 25-43.
Table 25-16. SPI Bus Protocol Modes
MR.CPOL MR.CPHA SPI Bus Protocol Mode
01 0
00 1
11 2
10 3
582
32072H–AVR32–10/2012
AT32UC3A3
Figure 25-42. SPI Transfer Format (CPHA=1, 8 bits per transfer)
Figure 25-43. SPI Transfer Format (CPHA=0, 8 bits per transfer)
25.6.15.4 Receiver and Transmitter Control
See ”Manchester Encoder” on page 583, and ”Receiver Status” on page 553.
25.6.15.5 Character Transmission and Reception
In SPI master mode, the slave sele ct line (NSS) is asser ted lo w one b i t per iod befor e t he st ar t of
transmission, and released high one bit period after every character transmission. A delay for at
least three bit periods is always inserted in between characters. In order to address slave
devices supporting the Chip Select Active After Transfer (CSAAT) mode, NSS can be forced low
by writing a one to the Force SPI Chip Select bit (CR.RTSEN/FCS). Releasing NSS when FCS
is one is only possible by writing a one to the Release SPI Chip Select bit (CR.RTSDIS/RCS).
CLK cycle (for reference)
CLK
(CPOL= 1)
MOSI
SPI Master ->TXD
SPI Slave ->RXD
MISO
SPI Master ->RXD
SPI Slave ->TXD
NSS
SPI Master ->RTS
SPI Slave ->CTS
MSB
MSB
1
CLK
(CPOL= 0)
35678
LSB
1234
6
65
54321LSB
24
CLK cycle (for reference)
CLK
(CPOL= 0)
CLK
(CPOL= 1)
MOSI
SPI Master -> TXD
SPI Slave -> RXD
MISO
SPI Master -> RXD
SPI Slave -> TXD
NSS
SPI Master -> RTS
SPI Slave -> CTS
MSB 6 5
MSB 6 5
4
43
32
21
1LSB
LSB
87654321
583
32072H–AVR32–10/2012
AT32UC3A3
In SPI slave mode, a low level on NSS for at least one bit period will allow the slave to initiate a
transmission or reception. The Underrun Error bit (CSR.UNRE) is set if a charact er must be se nt
while THR is empty, and TXD will be high during character transmission, as if 0xFF was being
sent. An interrupt request is generated if the Underrun Error bit in the Interrupt Mask Register
(IMR.UNRE) is set. If a new character is written to THR it will be sent correctly during the next
transmission slot. Writing a one to CR.RSTSTA will clear CSR.UNRE. To ensure correct behav-
ior of the receiver in SPI slave mode, the master device sending the frame must ensure a
minimum delay of one bit period in between each character transmission.
25.6.15.6 Receiver Time-out
Receiver Time-outs are not possib le in SPI mode as the Baud Rate Clock is only active durin g
data transfers.
25.6.16 Manchester Encoder/Decoder
Writing a one to the Manchester Encoder/Decoder bit in the Mode Register (MR.MAN) enables
the Manchester Encoder/Decoder. When the Manchester Encoder/Decoder is used, characters
transmitted through the USART are encoded in Manchester II Biphase format. Depending on
polarity con figuration, select ed by the Tr ansmission Manchester Polarity bit in the Manchester
Configuration Register (MAN.TX_MOPL), a logic level (zero or one) is transmitted as the transi-
tion from high-to-low or low-to-high during the middle of each bit period. This consumes twice
the bandwidth of th e simpler NRZ co ding sch emes, bu t the receiver has mo re error cont rol since
the expected input has a transition at every mid-bit period.
25.6.16.1 Manchest e r Encoder
An example of a Manchester encoded sequence is the byte 0xB1 (10110001) being encoded to
10 01 10 10 01 01 01 10, assuming default encoder polarity. Figure 25-44 illustrates this coding
scheme.
Figure 25-44. NRZ to Manchester Encoding
A Manchester encoded character can be preceded by both a preamble sequence and a start
frame delimiter. Th e pr eamble seque nce is a pre -d efi ned pat t ern with a configur ab le l en gth f rom
1 to 15 bit p eriods . If th e pr eam ble le ngth is zer o, the pre amb le w avefo rm is not ge ner ated . The
preamble length is selected by writing to the T ransmitter Preamble Length field (MAN.TX_PL).
The available preamble sequence patterns are:
• ALL_ONE
• ALL_ZERO
•ONE_ZERO
•ZERO_ONE
and are selected by writing to the Transmitter Preamble Pattern field (MAN.TX_PP). Figure 25-
45 illustrates the supported patterns.
NRZ
encoded
data
Manchester
encoded
data
10110001
Txd
584
32072H–AVR32–10/2012
AT32UC3A3
Figure 25-45. Preamble Patterns, Default Polarity Assumed
The Start Frame Delimiter Selector bit (MR.ONEBIT) configures the Manchester start bit pattern
following the preamble. If MR.ONEBIT is one, a Manchester encoded zero is transmitted to indi-
cate that a ne w chara cter is a bout to be se nt. If MR.ONEBI T is zero, a synchronizatio n pat tern is
sent for the duration of three bit periods to inaugurate the new character. The sync pattern wave-
form by itself is an invalid Manchester encoding, since the transition only occurs at the middle of
the second bit period.
The Manchester Synchronization Mode bit (MR.MODSYNC) selects sync pattern, and this also
defines if the cha racter is data (MODSYNC=0) with a zero to one transition, or a command
(MODSYNC=1) with a one to zero transition. When direct memory access is used, the sync pat-
tern can be updated on-the-fly with a modified character located in memory. To enable this
mode the Variable Synchronization of Command/Data Sync Start Frame Delimiter bit
(MR.VAR_SYNC) must be written to one. In this case, MODSYNC is bypassed and
THR.TXSYNH selects the sync type to be included. Figure 25-46 illustrates supported patterns.
Manchester
encoded
data Txd SFD DATA
8 bit width "ALL_ONE" Preamble
Manchester
encoded
data Txd SFD DATA
8 bit width "ALL_ZERO" Preamble
Manchester
encoded
data Txd SFD DATA
8 bit width "ZERO_ONE" Preamble
Manchester
encoded
data Txd SFD DATA
8 bit width "ONE_ZERO" Preamble
585
32072H–AVR32–10/2012
AT32UC3A3
Figure 25-46. Start Frame Delimiter
Manchester Drift Compensation
The Drift Compensation bit (MAN.DRIFT) enables a hardware drift compensation and recovery
system that allows for sub-optimal clock drifts without further user intervention. Drift compensa-
tion is only available in 16x oversampling mode (MR.OVER is zero). If the RXD event is one 16th
clock cycle from the expected edge, it is considered as normal jitter and no corrective action will
be taken. If the ev ent is two to fou r 16th’s early, the current period will be shortened by a 16th. If
the event is two to three 16 th’s after the expected edge, the current period will be prolonged by a
16th.
Figure 25-47. Bit Resynchronization
25.6.16.2 Manchester Decoder
The Manchester decoder can detect selectable preamble sequences and start frame delimiters.
The Receiver Manchester Polarity bit in the “Manchester Configuration Register”
(MAN.RX_MPOL) selects input stream polarity. The Receiver Preamble Length field
(MAN.RX_PL) specifies the length characteristics of detectable preambles. If MAN.RX_PL is
zero, the preamble pattern detection will be disabled. The Receiver Preamble Pattern field
(MAN.RX_PP) selects the pattern to be detected. See Figure 25-45 for available preamble pat-
terns. Figure 25-48 illustrates two types of Manchester preamble pattern mismatches.
Manchester
encoded
data Txd
SFD
DATA
One bit start frame delimiter
Preamble Length
is set to 0
Manchester
encoded
data Txd
SFD
DATA
Command Sync
start frame delimiter
Manchester
encoded
data Txd
SFD
DATA
Data Sync
start frame delimiter
RXD
Oversampling
16x Clock
Sampling
point
Expected edge
Tolerance
Synchro.
Jump Sync
Jump
Synchro.
Error
Synchro.
Error
586
32072H–AVR32–10/2012
AT32UC3A3
The Manchester endec uses the same Start Frame Delimiter Selector (MR.ONEBIT) for both
encoder and decoder. If ONEBIT is one, only a Manchester encoded zero will be accepted as a
valid start frame delimiter. If ONEBIT is zero, a data or command sync pattern will be expected.
The Received Sync bit in the Receive Holding Register (RHR.RXSYNH) will be zero if the last
character received is a data sync, and a one if it is a command sync.
Figure 25-48. Preamble Pattern Mismatch
The receiver samples the RXD line in continuos bit period quarters, making the smallest time
frame in which to assume a bit value three quarters. A start bit is assumed if RXD is zero during
one of these quarters, see Figure 25-49.
Figure 25-49. Asynchronous Start Bit Detection
If a valid preamble pattern or start frame delimiter is detected, the receiver continues decoding
with the same synchronization. If a non-valid preamble pattern or a start frame delimiter is
detected, the receiver re-synchronizes at the next valid edge. When a valid start sequence has
been detected, the decoded data is passed to the USART and the user will be notified of any
incoming Manchester en coding violations by the Manchester Error bit (CSR.MANERR). An inter-
rupt request is generated if one of the Manchester Error bits in the Interrupt Mask Register
(IMR.MANE or IMR.MANEA) is set. CSR.MANERR is cleared by writing a one to the Reset Sta-
tus bits in the Control Register (CR.RSTSTA). A violation occurs when there is no transition in
the middle of a bit period. See Figure 25-50 for an illustration of a violation causing the Man-
chester Error bit to be set.
Manchester
encoded
data Txd SFD DATA
Preamble Length is set to 8
Preamble Mismatch
invalid pattern
Preamble Mismatch
Manchester coding error
Manchester
encoded
data Txd
1234
Sampling
Clock
(16 x)
Start
Detection
587
32072H–AVR32–10/2012
AT32UC3A3
Figure 25-50. Manchester Error
25.6.16.3 Radio Interface: Manchester Endec Application
This section describes low data rate, full duplex, dual frequency, RF systems integrated with a
Manchester endec, that support ASK and/or FSK modulation schemes. See Figure 25-51.
Figure 25-51. Manchester Encoded Characters RF Transmission
To transmit downstream, encoded data is sent serially to the RF modulator and then through
space to the RF receiver. To receive, another frequency carrier is used and the RF demodulator
does a bit-checking search for valid patterns before it switches to a receiving mode and forwards
data to the decoder . Defining preambles to help distinguish between noise and valid data has to
be done in conjun ction with t he RF module, and may some times be filter ed away fr om the endec
stream. Using the ASK modulation scheme, a one is transmitted as an RF signal at the down-
stream frequency, while a zero is transmitted as no signal. See Figure 25-52. The FSK
modulation scheme uses two different frequencies to transmit data. A one is sent as a signal on
one frequency, and a zero on the other. See Figure 25-53.
Manchester
encoded
data Txd
SFD
Preamble Length
is set to 4
Elementary character bit time
Manchester
Coding Error
detected
sampling points
Preamble subpacket
and Start Frame Delimiter
were successfully
decoded
Entering USART character area
LNA
VCO
RF filter
Demod
control bi-dir
line
PA
RF filter
Mod
VCO
control
Manchester
decoder
Manchester
encoder
USART
Receiver
USART
Emitter
ASK/FSK
Upstream Receiver
ASK/FSK
downstream transmitter
Upstream
Emitter
Downstream
Receiver
Serial
Configuration
Interface
Fup frequency Carrier
Fdown frequency Carrier
588
32072H–AVR32–10/2012
AT32UC3A3
Figure 25-52. ASK Modulator Output
Figure 25-53. FSK Modulator Output
25.6.17 Tes t M odes The internal loopback feature ena bles on-board diagnostics, and allows the USART to operate
in three different test modes, with reconfigured pin functionality, as shown below.
25.6.17.1 Normal Mode
During normal operation, a receiver RXD pin is connected t o a transmitter TXD pin.
Figure 25-54. Normal Mode Configuration
25.6.17.2 Automatic Echo Mode
Automatic echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it
is also sent to the TXD pin, as shown in Fig ure 25-55. Transmitter configuration has no effect.
Manchester
encoded
data
default polarity
unipolar output Txd
ASK Modulator
Output
Uptstream Frequency F0
NRZ stream 10 0 1
Manchester
encoded
data
default polarity
unipolar output
Txd
FSK Modulator
Output
Uptstream Frequencies
[F0, F0+offset]
NRZ stream 10 0 1
Receiver
Transmitter
RXD
TXD
589
32072H–AVR32–10/2012
AT32UC3A3
Figure 25-55. Automatic Echo Mode Configuration
25.6.17.3 Local Loopback Mode
Local loopback mode connects the output of the transmitter directly to the input of the receiver,
as shown in Figure 25-56. The TXD and RXD pins are not used. The RXD pin has no effect on
the receiver and the TXD pin is continuously driven high, as in idle state.
Figure 25-56. Local Loopback Mode Configura tion
25.6.17.4 Remote Loopback Mode
Remote loopback mode connects the RXD pin to the TXD pin, as shown in Figure 25-57. The
transmitter and the receiver are disabled and have no effect. This mode allows bit-by-bit
retransmission.
Figure 25-57. Remote Loopback Mode Configuration
25.6.18 Interrupts
Receiver
Transmitter
RXD
TXD
Receiver
Transmitter
RXD
TXD
1
Receiver
Transmitter
RXD
TXD
1
–– MANEA
23 22 21 20 19 18 17 16
– – – MANE CTSIC DCDIC DSRIC RIIC
15 14 13 12 11 10 9 8
LINTC LINIR NACK RXBUFF – ITER/UNRE TXEMPTY TIMEOUT
590
32072H–AVR32–10/2012
AT32UC3A3
The USART has the following interrupt sources:
• LINSNRE: LIN Slave Not Responding Error
– A LIN Slave Not Responding Error has been detect ed
• LINCE: LIN Checksum Error
– A LIN Checksum Error has been detected
• LINIPE: LIN Identifier Parity Error
– A LIN Ident ifier Parity Error has been detected
• LINISFE: LIN Inconsistent Sync Field Error
– The USART is configured as a Slave node and a LIN Inconsistent Sync Field Error
has been detected since the last RSTSTA.
• LINBE: LIN Bit Error
– A Bit Error has been detected since the last RSTSTA.
• MANERR: Manchester Error
– At least one Manchester error has been detected since the last RSTSTA.
• CTSIC: Clear to Send Input Change Flag
– At least one change has been detected on the CTS pin since the last CSR read.
• DCDIC: Data Carrier Detect Input Change Flag
– A change has been detected on the DCD pin
• DSRIC: Data Set Ready Input Change Flag
– A change has been detected on the DSR pin
• RIIC: Ring Indicato r In put Cha n ge Flag
– A change has been detected on the RI pin
• LINTC: LIN Transfer Completed
– A LIN tr ansfer has been completed
• LINIDR: LIN Identifier
– A LIN Identifier has been sent (master) or received (slave)
• NACK: Non Acknowledge
– At least one Non Acknowledge has been detected
• RXBUFF: Reception Buffer Full
– The Buffer Full signal from the Peripheral DMA Controller chan nel is active.
• ITER/UNRE: Max number of Repetitions Reached or SPI Underrun Error
– IF USAR T d oes not oper ate in SPI slav e mode: Maximum number of repetit ions has
been reached since the last RSTSTA.
– If USAR T oper ates in SPI sl a v e mode: At least one SPI und errun error has occurred
since the last RSTSTA.
• TXEMPTY: Transmitter Empty
– There are no characters in neither THR, nor in the tr ansmit shift register.
• TIMEOUT: Receiver Time-out
76543210
PARE FRAME OVRE – – RXBRK TXRDY RXRDY
591
32072H–AVR32–10/2012
AT32UC3A3
– There has been a time-out since the last Start Time-out command.
• PARE: Parity Error
– Either at least one pa rity error has been detected, or the parity bit is a one in
multidrop mode, since the last RSTSTA.
• FRAME: Framing Error
– At least one stop bit has been found as low since the last RSTSTA.
• OVRE: Overrun Error
– At least one o verrun error has occurred since the last RSTSTA.
• RXBRK: Break Received/End of Break
– Break received or End of Break detected since the last RSTSTA.
• TXRDY: Transmitter Ready
– There is no character in the THR.
• RXRDY: Receiver Ready
– At least one complete character has been received and RHR has not yet been read.
An interrupt source will set a corresponding bit in the Channel Status Register (CSR). The inter-
rupt sources will ge nerate an interrupt request if the corresponding bit in the Interrupt Mask
Register (IMR) is set. The interrupt sou rces are ORed toge ther to form one inter rupt request.
The USART will generate an interrupt request if at least one of the bits in IMR is set. Bits in IMR
are set by writing a one to the corresponding bit in the Interrupt Enable Register (IER), and
cleared by writing a one to the corresponding bit in the Interrupt Disable Register (IDR). The
interrupt reque st rem ains active until th e co rrespondin g bit in CSR is clea red. Th e cleari ng of t he
bits in CSR is described in ”Channel Status Register” on page 602. Because all the interrupt
sources are ORed together, the interrupt request from the USART will remain active until all the
bits in CSR are cleared.
25.6.19 Using the Peripheral DMA Controller
25.6.20 Write Protection Registers
To prevent single software errors from corrupting USART behavior, certain address spaces can
be write-protected by writing the correct Write Protect KEY and writing a one to the Write Protect
Enable bit in the Write Protect Mode Register (WPMR.WPKEY and WPMR.WPEN). Disabling
the write protection is done by writing the correct key to WPMR.WPKEY and a zero to
WPMR.WPEN.
Write attempts to a write-protected re gister are detected and the Write Protect Violation Status
bit in the Write Protect Status Register (WPSR.WPVS) is set. The Write Protect Violation Source
field (WPSR.WPVSRC) indicates the target register. Writing the correct key to the Write Protect
KEY bit (WPMR.WPKEY) clears WPSR. WPVSRC and WPSR.WPVS.
The protected registers are:
•”Mode Register” on page 596
•”Baud Rate Genera tor Register” on page 607
•”Receiver Time-out Register” on page 609
•”Transmitter Time guard Register” on page 610
•”FI DI Ratio Register” on page 611
•”IrDA Filter Register” on page 613
592
32072H–AVR32–10/2012
AT32UC3A3
•”Manchester Configuration Register” on page 614
593
32072H–AVR32–10/2012
AT32UC3A3
25.7 User Interface
Note: 1. Values in the Version Register vary with the version of the IP block implementation.
Table 25-17. USART Register Memory Map
Offset Register Name Access Reset
0x00 Control Register CR Write-only 0x00000000
0x04 Mode Register MR Read-write 0x00000000
0x08 Interrupt Enable Register IER Write-on ly 0x00000000
0x0C Interrupt Disable Register IDR Write-only 0x00000000
0x010 Interrupt Mask Register IMR Read-only 0x00000000
0x14 Channel Status Register CSR Read-only 0x00000000
0x18 Receiver Holding Register RHR Read-only 0x00000000
0x1C Transmitter Holding Register THR Write-only 0x00000000
0x20 Baud Rate Generator Register BRGR Read-write 0x00000000
0x24 Receiver Time-out Register RTOR Read-write 0x00000000
0x28 Transmitter Timeguard Register TTGR Read-write 0x00000000
0x40 FI DI Ratio Register FIDI Read-write 0x00000174
0x44 Number of Errors Register NER Read-only 0x00000000
0x4C IrDA Filter Register IFR Read-write 0x00000000
0x50 Manchester Configuration Register MAN Read-write 0x30011004
0x54 LIN Mode Register LINMR Read-write 0x00000 000
0x58 LIN Ide ntifier Register LINIR R ead-write 0x00000000
0xE4 Write Protect Mode Register WPMR Read-write 0x00000000
0xE8 Write Protect Status Register WPSR Read-only 0x00000000
0xFC Version Register VERSION Read-only -(1)
594
32072H–AVR32–10/2012
AT32UC3A3
25.7.1 Control Register
Name: CR
Access Type: Write-only
Offset: 0x00
Reset Value: 0x00000000
• LINWKUP: Send LIN Wakeup Signal
Writing a zero to this bit has no effect.
Writing a one to this bit will send a wakeup signal on the LIN bus.
• LINABT: Abort LIN Transmission
Writing a zero to this bit has no effect.
Writing a one to this bit will abort the current LIN transmission.
• RTSDIS/RCS: Request to Send Disable/Release SPI Chip Sele ct
Writing a zero to this bit has no effect.
Writing a one to this bit when USART is not in SPI master mode drives RTS high.
Writing a one to this bit when USART is in SPI master mode releases NSS (RTS pin).
• RTSEN/FCS: Request to Send Enable/Force SPI Chip Select
Writing a zero to this bit has no effect.
Writing a one to this bit when USART is not in SPI master mode drives RTS low.
Writing a one to this bit when USART is in SPI master mode forces NSS (RTS pin) low, even if USART is not transmitting, in
order to address SPI slave devices supporting the CSAAT Mode (Chip Select Active After Transfer).
• DTRDIS: Data Terminal Ready Disable
Writing a zero to this bit has no effect.
Writing a one to this bit drives DTR high.
• DTREN: Data Terminal Ready Enable
Writing a zero to this bit has no effect.
Writing a one to this bit drives DTR low.
• RETTO: Rearm Time-out
Writing a zero to this bit has no effect.
Writing a one to this bit reloads the time-out counter and clears CSR.TIMEOUT.
• RSTNACK: Reset Non Acknowledge
Writing a zero to this bit has no effect.
Writing a one to this bit clears CSR.NACK.
• RSTIT: Reset Iterations
Writing a zero to this bit has no effect.
Writing a one to this bit clears CSR.ITER if ISO7816 is enabled (MR.MODE is 0x4 or 0x6)
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
– – LINWKUP LINABT RTSDIS/RCS RTSEN/FCS DTRDIS DTREN
15 14 13 12 11 10 9 8
RETTO RSTNACK RSTIT SENDA STTTO STPBRK STTBRK RSTSTA
76543210
TXDIS TXEN RXDIS RXEN RSTTX RSTRX – –
595
32072H–AVR32–10/2012
AT32UC3A3
• SENDA: Send Address
Writing a zero to this bit has no effect.
Writing a one to this bit will in multidrop mode send the next character written to THR as an address.
• STTTO: Start Time-out
Writing a zero to this bit has no effect.
Writing a one to this bit will abort any current time-out count down, and trigg er a new count down when the next character has
been received. CSR.TIMEOUT is also cleared.
• STPBRK: Stop Break
Writing a zero to this bit has no effect.
Writing a one to this bit will stop the generation of break signal characters, and then send ones for TTGR.TG duration, or at least
12 bit per iods. No effect if no break is being transmitted.
• STTBRK: Start Brea k
Writing a zero to this bit has no effect.
Writing a one to this bit will start transmission of break characters when current characters present in THR and the transmit shift
register have been sent. No effect if a break signal is already being generated. CSR.TXRDY and CSR.TXEMPTY will be
cleared.
• RSTSTA: Reset Status Bits
Writing a zero to this bit has no effect.
Writing a one to this bit will clear the following bits in CSR: PARE, FRAME, OVRE, MANERR, LINBE, LINISFE, LINIPE, LINCE,
LINSNRE, LINTC, LINIR, UNRE, and RXBRK.
•TXDIS: Transmitter Disable
Writing a zero to this bit has no effect.
Writing a one to this bit disables the transmitter.
•TXEN: Transmitter Enable
Writing a zero to this bit has no effect.
Writing a one to this bit enables the transmitter if TXDIS is zero.
•RXDIS: Receiver Disable
Writing a zero to this bit has no effect.
Writing a one to this bit disables the receiver.
•RXEN: Receiver Enable
Writing a zero to this bit has no effect.
Writing a one to this bit enables the receiver if RXDIS is zero.
•RSTTX: Reset Transmitter
Writing a zero to this bit has no effect.
Writing a one to this bit will reset the transmitter.
•RSTRX: Reset Receiver
Writing a zero to this bit has no effect.
Writing a one to this bit will reset the receiver.
596
32072H–AVR32–10/2012
AT32UC3A3
25.7.2 Mode Register
Name: MR
Access Type: Read-write
Offset: 0x04
Reset Value: 0x00000000
This register can only be written if write protection is disabled in the “Write Protect Mode Register” (WPMR.WPEN is zero).
• ONEBIT : Start Frame Delimiter Selector
0: The start frame delimiter is a command or data sync, as defined by MODSYNC.
1: The start frame delimiter is a normal start bit, as defin ed by MODSYNC.
• MODSYNC: Manchester Synchronization Mode
0: The manchester start bit is either a 0-to-1 transition, or a data sync.
1: The manchester start bit is either a 1-to-0 transition, or a command sync.
• MAN: Manchester Encoder/Decoder Enable
0: Manchester endec is disabled.
1: Manchester endec is enabled.
• FILTER: Infrared Receive Line Filter
0: The USART does not filter the receive line.
1: The USART filters the receive line by doing three consecutive samples and uses the majority value.
• MAX_ITERATION
This field determines the number of acceptable consecutive NACKs when in protocol T=0.
• VAR_SYNC: Variable Synchronization of Command/Data Sync Start Frame Delimiter
0: Sync pattern according to MODSYNC.
1: Sync pattern according to THR.TXSYNH.
• DSNACK: Disable Successive NACK
0: NACKs are handled as normal, un less disabled by INACK.
1: The receiver restricts the amount of consecutive NACKs by MAX_ITERATION v alue . If MAX_ITERATION=0 no NA CK will be
issued and the first erroneous message is accepted as a valid ch aracter, setting CSR.ITER.
• INACK: Inhibit Non Acknowledge
0: The NACK is generated.
1: The NACK is not generated.
• OVER: Oversampling Mode
0: Oversampling at 16 times the baud rate.
1: Oversampling at 8 times the baud rate.
• CLKO: Clock Output Select
0: The USART does not drive the CLK pin.
1: The USART drives the CLK pin unless USCLKS selects the external clock.
31 30 29 28 27 26 25 24
ONEBIT MODSYNC MAN FILTER – MAX_ITERATION
23 22 21 20 19 18 17 16
– VAR_SYNC DSNACK INACK OVER CLKO MODE9 MSBF/CPOL
15 14 13 12 11 10 9 8
CHMODE NBSTOP PAR SYNC/CPHA
76543210
CHRL USCLKS MODE
597
32072H–AVR32–10/2012
AT32UC3A3
• MODE9: 9-bit Character Length
0: CHRL defines character length.
1: 9-bit character length.
• MSBF/CPOL: Bit Order or SPI Clock Polarity
If USART does not operate in SPI Mode:
MSBF=0: Least Significant Bit is sent/received first.
MSBF=1: Most Significant Bit is sent/received first.
If USART operates in SPI Mode, CPOL is used with CPHA to produce the required clock/data relationship between devices.
CPOL=0: The inactive state value of CLK is logic level zero.
CPOL=1: The inactive state value of CLK is logic level one.
• CHMODE: Channel Mode
• NBSTOP: Number of Stop Bits
• PAR: Parity Type
• SYNC/CPHA: Synchronous Mode Select or SPI Clock Phase
If USART does not operate in SPI Mode (MR.MODE is not equal to 0xE or 0xF):
SYNC = 0: USART operates in Asynchronous mode.
SYNC = 1: USART operates in Synchronous mode.
If USART operates in SPI Mode, CPHA determines which edge of CLK causes data to chang e and whi c h edge causes data to
be captured. CPHA is used with CPOL to produce the required clock/data relationship between master and slave devices.
CPHA = 0: Data is changed on the leading edge of CLK and captured on the following edge of CLK.
Table 25-18.
CHMODE Mode Description
0 0 Normal Mode
0 1 Automatic Echo. Receiver input is connected to the TXD pin.
1 0 Local Loopback. Transmitter output is connected to the Receiver input.
1 1 Remote Loopback. RXD pin is internally connected to the TXD pin.
Table 25-19.
NBSTOP Asynchronous (SYNC=0) Synchronous (SYNC=1)
0 0 1 sto p bit 1 stop bit
0 1 1.5 sto p bits Reserved
1 0 2 stop bits 2 stop bits
1 1 Reserved Reserved
Table 25-20.
PAR Parity Type
0 0 0 Even parity
001Odd parity
0 1 0 Parity forced to 0 (Space)
0 1 1 Parity forced to 1 (Mark)
1 0 x No parity
1 1 x Multidrop mode
598
32072H–AVR32–10/2012
AT32UC3A3
CPHA = 1: Data is captured on the leading edge of CLK and changed on the following edge of CLK.
• CHRL: Character Length.
• USCLKS: Clock Selection
Note: 1. The value of DIV is device dependent. Please refer to the Module Configuration section at the end of this chapter.
•MODE
Table 25-21.
CHRL Character Length
0 0 5 bits
0 1 6 bits
1 0 7 bits
1 1 8 bits
Table 25-22.
USCLKS Selected Clock
0 0 CLK_USART
0 1 CLK_USART/DIV(1)
10Reserved
11
CLK
Table 25-23.
MODE Mode of the USART
0000Normal
0001RS485
0010Hardware Handshaking
0011Modem
0100IS07816 Protocol: T = 0
0110IS07816 Protocol: T = 1
1000IrDA
1010LIN Master
1011LIN Slave
1110SPI Master
1111SPI Slave
Others Reserved
599
32072H–AVR32–10/2012
AT32UC3A3
25.7.3 Interrupt Enable Register
Name: IER
Access Type: Write-only
Offset: 0x08
Reset Value: 0x00000000
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will set the corresponding bit in IMR.
• LINSNRE: LIN Slave Not Responding Error
• LINCE: LIN Checksum Error
• LINIPE: LIN Identi fier Parity Error
• LINISFE: LIN Inco nsistent Sync Field Error
• LINBE: LIN Bit Error
• MANEA/MANE: Manchester Error
• CTSIC: Clear to Send Input Change Flag
• DCDIC: Data Carrier Detect Input Change Flag
• DSRIC: Data Set Ready Input Change Flag
• RIIC: Ring Indicator Inpu t Change Flag
• LINTC: LIN Transfer Completed
• LINIDR: LIN Identifier
• NACK: Non Acknowledge
• RXBUFF: Reception Buffer Full
• ITER/UNRE: Max number of Repetitions Reached or SPI Underrun Error
• TXEMPTY: Transmitter Empty
• TIMEOUT: Receiver Time-out
• PARE: Parity Error
• FRAME: Framing Error
• OVRE: Overrun Error
• RXBRK: Break Received/End of Break
• TXRDY: Transmitter Ready
• RXRDY: Receiver Ready
For backward compatibility the MANE bit has been duplicated to the MANEA bit position. Writing either one or the other has
the same effec t. The co rr esponding bit in CSR and the co rr esp o nd in g inte rr u pt re qu e st ar e na m ed MANERR.
31 30 29 28 27 26 25 24
– – LINSNRE LINCE LINIPE LINISFE LINBE MANEA
23 22 21 20 19 18 17 16
– – – MANE CTSIC DCDIC DSRIC RIIC
15 14 13 12 11 10 9 8
LINTC LINIR NACK RXBUFF – ITER/UNRE TXEMPTY TIMEOUT
76543210
PARE FRAME OVRE – – RXBRK TXRDY RXRDY
600
32072H–AVR32–10/2012
AT32UC3A3
25.7.4 Interrupt Disable Register
Name: IDR
Access Type: Write-only
Offset: 0x0C
Reset Value: 0x00000000
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will clear the corresponding bit in IMR.
• LINSNRE: LIN Slave Not Responding Error
• LINCE: LIN Checksum Error
• LINIPE: LIN Identi fier Parity Error
• LINISFE: LIN Inco nsistent Sync Field Error
• LINBE: LIN Bit Error
• MANEA/MANE: Manchester Error
• CTSIC: Clear to Send Input Change Flag
• DCDIC: Data Carrier Detect Input Change Flag
• DSRIC: Data Set Ready Input Change Flag
• RIIC: Ring Indicator Inpu t Change Flag
• LINTC: LIN Transfer Completed
• LINIDR: LIN Identifier
• NACK: Non Acknowledge
• RXBUFF: Reception Buffer Full
• ITER/UNRE: Max number of Repetitions Reached or SPI Underrun Error
• TXEMPTY: Transmitter Empty
• TIMEOUT: Receiver Time-out
• PARE: Parity Error
• FRAME: Framing Error
• OVRE: Overrun Error
• RXBRK: Break Received/End of Break
• TXRDY: Transmitter Ready
• RXRDY: Receiver Ready
For backward compatibility the MANE bit has been duplicated to the MANEA bit position. Writing either one or the other has
the same effec t. The co rr esponding bit in CSR and the co rr esp o nd in g inte rr u pt re qu e st ar e na m ed MANERR.
31 30 29 28 27 26 25 24
– – LINSNRE LINCE LINIPE LINISFE LINBE MANEA
23 22 21 20 19 18 17 16
– – – MANE CTSIC DCDIC DSRIC RIIC
15 14 13 12 11 10 9 8
LINTC LINIR NACK RXBUFF – ITER/UNRE TXEMPTY TIMEOUT
76543210
PARE FRAME OVRE – – RXBRK TXRDY RXRDY
601
32072H–AVR32–10/2012
AT32UC3A3
25.7.5 Interrupt Mask Register
Name: IMR
Access Type: Read-only
Offset: 0x10
Reset Value: 0x00000000
0: The corresponding interr upt is disabled.
1: The corresponding interrupt is enabled.
A bit in this register is cleared when the corresponding bit in IDR is wr itten to one.
A bit in this register is set when the corresponding bit in IER is written to one.
• LINSNRE: LIN Slave Not Responding Error
• LINCE: LIN Checksum Error
• LINIPE: LIN Identi fier Parity Error
• LINISFE: LIN Inco nsistent Sync Field Error
• LINBE: LIN Bit Error
• MANEA/MANE: Manchester Error
• CTSIC: Clear to Send Input Change Flag
• DCDIC: Data Carrier Detect Input Change Flag
• DSRIC: Data Set Ready Input Change Flag
• RIIC: Ring Indicator Inpu t Change Flag
• LINTC: LIN Transfer Completed
• LINIDR: LIN Identifier
• NACK: Non Acknowledge
• RXBUFF: Reception Buffer Full
• ITER/UNRE: Max number of Repetitions Reached or SPI Underrun Error
• TXEMPTY: Transmitter Empty
• TIMEOUT: Receiver Time-out
• PARE: Parity Error
• FRAME: Framing Error
• OVRE: Overrun Error
• RXBRK: Break Received/End of Break
• TXRDY: Transmitter Ready
• RXRDY: Receiver Ready
For backward compatibility the MANE bit has been duplicated to the MANEA bit position. Reading either one or the other
has the same effect. The corresponding bit in CSR and the corresponding interrupt request are named MANERR.
31 30 29 28 27 26 25 24
– – LINSNRE LINCE LINIPE LINISFE LINBE MANEA
23 22 21 20 19 18 17 16
– – – MANE CTSIC DCDIC DSRIC RIIC
15 14 13 12 11 10 9 8
LINTC LINIR NACK RXBUFF – ITER/UNRE TXEMPTY TIMEOUT
76543210
PARE FRAME OVRE – – RXBRK TXRDY RXRDY
602
32072H–AVR32–10/2012
AT32UC3A3
25.7.6 Channel Status Register
Name: CSR
Access Type: Read-only
Offset: 0x14
Reset Value: 0x00000000
• LINSNRE: LIN Slave Not Responding Error
0: No LIN Slave Not Responding Error has been detected since the last RSTSTA.
1: A LIN Slave Not Responding Error has been detected since the last RSTSTA.
This bit is cleared by writing a one to CR.RSTSTA.
• LINCE: LIN Checksum Error
0: No LIN Checksum Error has been detected since the last RSTSTA .
1: A LIN Checksum Error has been detected since the last RSTSTA.
This bit is cleared by writing a one to CR.RSTSTA.
• LINIPE: LIN Identi fier Parity Error
0: No LIN Identifier Parity Error has been detected since the last RSTSTA.
1: A LIN Identifier Parity Error has been detected since the last RSTSTA.
This bit is cleared by writing a one to CR.RSTSTA.
• LINISFE: LIN Inco nsistent Sync Field Error
0: No LIN Inconsistent Sync Field Error has been detected since the last RSTSTA
1: The USAR T is configured as a Sla v e node and a LIN Inconsistent Sync Field Error has been detected since the last RSTSTA.
This bit is cleared by writing a one to CR.RSTSTA.
• LINBE: LIN Bit Error
0: No Bit Error has been detected since the last RSTSTA.
1: A Bit Error has been detected since the last RSTSTA.
This bit is cleared by writing a one to CR.RSTSTA.
• MANERR: Manchester Error
0: No Manchester error has been detected since the last RSTSTA.
1: At least one Manchester error has been detected since the last RSTSTA.
• CTS: Image of CTS Input
0: CTS is low.
1: CTS is high.
• DCD: Image of DCD Input
0: DCD is low.
1: DCD is high.
• DSR: Image of DSR Input
0: DSR is low.
31 30 29 28 27 26 25 24
– – LINSNRE LINCE LINIPE LINISFE LINBE MANERR
23 22 21 20 19 18 17 16
CTS DCD DSR RI CTSIC DCDIC DSRIC RIIC
15 14 13 12 11 10 9 8
LINTC LINIR NACK RXBUFF – ITER/UNRE TXEMPTY TIMEOUT
76543210
PARE FRAME OVRE – – RXBRK TXRDY RXRDY
603
32072H–AVR32–10/2012
AT32UC3A3
1: DSR is high.
• RI: Image of RI Input
0: RI is low.
1: RI is high.
• CTSIC: Clear to Send Input Change Flag
0: No change has been detected on the CTS pin since th e last CSR read.
1: At least one change has been detected on the CTS pin since the last CSR read.
This bit is cleared when reading CSR.
• DCDIC: Data Carrier Detect Input Change Flag
0: No change has been detected on the DCD pin since the last CSR read.
1: At least one change has been detected on the DCD pin since the last CSR read.
This bit is cleared when reading CSR.
• DSRIC: Data Set Ready Input Change Flag
0: No change has been detected on the DSR pin since the last CSR read.
1: At least one change has been detected on the DSR pin since the last CSR read.
This bit is cleared when reading CSR.
• RIIC: Ring Indicator Inpu t Change Flag
0: No change has been detected on the RI pin since the last CSR read.
1: At least one change has been detected on the RI pin since the last CSR read.
This bit is cleared when reading CSR.
• LINTC: LIN Transfer Completed
0: The USART is either idle or a LIN transfer is ongoing.
1: A LIN transfer has been completed since the last RSTSTA.
This bit is cleared by writing a one to CR.RSTSTA:
• LINIR: LIN Identifier
0: No LIN Identifier has been sent or received.
1: A LIN Identifier has been sent (master) or received (slave), since the last RSTSTA.
This bit is cleared by writing a one to CR.RSTSTA:
• NACK: Non Acknowledge
0: No Non Acknowledge has been detected since the last RSTNACK.
1: At least one Non Acknowledge has been detected since the last RSTNACK.
This bit is cleared by writing a one to CR.RSTNACK.
• RXBUFF: Reception Buffer Full
0: The Buffer Full signal from the Peripheral DMA Controller channel is inactive.
1: The Buffer Full signal from the Peripheral DMA Controller channel is active.
• ITER/UNRE: Max Number of Repetitions Reached or SPI Underrun Error
If USART operates in SPI Slave Mode:
UNRE = 0: No SPI underrun error has occurred since the last RSTSTA.
UNRE = 1: At least one SPI underrun error has occurred since the last RSTSTA.
If USART does not operate in SPI Sla ve Mode , no functionality is associated to UNRE. The bit will behav e as ITER if the USART
is in ISO7816 mode:
ITER = 0: Maximum number of repetitions has not been reached since the last RSTSTA.
ITER = 1: Maximum number of repetitions has been reached since the last RSTSTA.
This bit is cleared by writing a one to CR.RSTSTA.
• TXEMPTY: Transmitter Empty
0: The tran smi tter is either disabled or there are characters in THR, or in the transmit shift register.
1: There are no characters in neither THR, nor in the transmit shift register.
This bit is cleared by writing a one to CR.STTBRK.
• TIMEOUT: Receiver Time-out
0: There has not been a time-out since the last Start Time-out command (CR.STTTO), or RTOR.TO is zero.
1: There has been a time-out since the last Start Time-out command.
This bit is cleared by writing a one to CR.STTTO or CR.RETTO.
604
32072H–AVR32–10/2012
AT32UC3A3
• PARE: Parity Error
0: Either no parity error has been detected, or the parity bit is a zero in multidrop mode, since the last RSTSTA.
1: Either at least one parity error has been detected, or the parity bit is a one in multidrop mode, since the last RSTSTA.
This bit is cleared by writing a one to CR.RSTSTA.
• FRAME: Framing Error
0: No stop bit has been found as low since the last RSTSTA.
1: At least one stop bit has been found as low since the last RSTSTA .
This bit is cleared by writing a one to CR.RSTSTA.
• OVRE: Overrun Error
0: No overrun error has occurred since the last RSTSTA.
1: At least one overrun error has occurred since the last RSTSTA.
This bit is cleared by writing a one to CR.RSTSTA.
• RXBRK: Break Received/End of Break
0: No Break received or End of Break detected since the la st RSTSTA.
1: Break received or End of Break detected since the last RSTSTA.
This bit is cleared by writing a one to CR.RSTSTA.
• TXRDY: Transmitter Ready
0: The transmitter is either disabled, or a character in THR is waiting to be transferred to the transmit shift register, or an
STTBRK command has been requeste d. As soon as the transmitter is enabled, TXRDY is set.
1: There is no character in the THR.
This bit is cleared by writing a one to CR.STTBRK.
• RXRDY: Receiver Ready
0: The receiver is either disabled, or no complete character has been received since the last read of RHR. If characters were
being received when the receiver was disabled, RXRDY is set when the receiver is enabled.
1: At least one complete character has been received and RHR has not yet been read.
This bit is cleared when the Receive Holding Register (RHR) is read.
605
32072H–AVR32–10/2012
AT32UC3A3
25.7.7 Receiver Holding Register
Name: RHR
Access Type: Read-only
Offset: 0x18
Reset Value: 0x00000000
Reading this register will clear the CSR.RXRDY bit.
• RXSYNH: Received Sync
0: Last character received is a data sync.
1: Last character received is a command sync.
• RXCHR: Received Character
Last received character.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
RXSYNH ––––––RXCHR[8]
76543210
RXCHR[7:0]
606
32072H–AVR32–10/2012
AT32UC3A3
25.7.8 Transmitter Holding Register
Name: THR
Access Type: Write-only
Offset: 0x1C
Reset Value: 0x00000000
• TXSYNH: Sync Field to be transmitted
0: If MR.VARSYNC is one, the next character sent is encoded as data, and the start frame delimiter is a data sync.
1: If MR.VARSYNC is one, the ne xt character sent is encoded as a command, and the start frame delimiter is a command sync.
• TXCHR: Character to be Transmitted
If TXRDY is zero this field contains the next character to be transmitted.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
TXSYNH ––––––TXCHR[8]
76543210
TXCHR[7:0]
607
32072H–AVR32–10/2012
AT32UC3A3
25.7.9 Baud Rate Generator Re gister
Name: BRGR
Access Type: Read-write
Offset: 0x20
Reset Value: 0x00000000
This register can only be written if write protection is disabled in the “Write Protect Mode Register” (WPMR.WPEN is ze ro).
• FP: Fractional Part
0: Fractional divide r is disabled.
1 - 7: Baud rate resolution, defined by FP x 1/8.
•CD: Clock Divider
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––– FP
15 14 13 12 11 10 9 8
CD[15:8]
76543210
CD[7:0]
Table 25-24. Baud Rate in Asynchronous Mode (MR.SYNC is 0)
CD OVER = 0 OVER = 1
0 Baud Rate Clock Disabled
1 to 65535
Table 25-25. Baud Rate in Synchronous Mode (MR.SYNC is 1) and SPI Mode(MR.MODE is 0xE or 0xF)
CD Baud Rate
0 Baud Rate Clock Disabled
1 to 65535
Baud Rate Selected Clock
16 CD⋅
----------------------------------------=
Baud Rate Selected Clock
8CD⋅
----------------------------------------=
Baud Rate Selected Clock
CD
----------------------------------------=
608
32072H–AVR32–10/2012
AT32UC3A3
Table 25-26. Baud Rate in ISO7816 Mode
CD Baud Rate
0 Baud Rate Clock Disabled
1 to 65535
Baud Rate Selected Clock
FI_DI_RATIO CD⋅
-------------------------------------------------=
609
32072H–AVR32–10/2012
AT32UC3A3
25.7.10 Receiver Time-out Register
Name: RTOR
Access Type: Read-write
Offset: 0x24
Reset Value: 0x00000000
This register can only be written if write protection is disabled in the “Write Protect Mode Register” (WPMR.WPEN is ze ro).
• TO: Time-out Value
0: The receiver Time-out is disabled.
1 - 131071: The receiver Time-out is enabled and the time-out delay is TO x bit period.
Note that the size of the TO counter is de vice dependent, please refer to the Module Configuration section.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––––TO[16]
15 14 13 12 11 10 9 8
TO[15:8]
76543210
TO[7:0]
610
32072H–AVR32–10/2012
AT32UC3A3
25.7.11 Transmitter Timeguard Register
Name: TTGR
Access Type: Read-write
Offset: 0x28
Reset Value: 0x00000000
This register can only be written if write protection is disabled in the “Write Protect Mode Register” (WPMR.WPEN is ze ro).
• TG: Timeguard Value
0: The transmitter Timeguard is disabled.
1 - 255: The transmitter timeguard is enabled and the timeguard delay is TG bit periods.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
TG
611
32072H–AVR32–10/2012
AT32UC3A3
25.7.12 FI DI Ratio Register
Name: FIDI
Access Type: Read-write
Offset: 0x40
Reset Value: 0x00000174
This register can only be written if write protection is disabled in the “Write Protect Mode Register” (WPMR.WPEN is ze ro).
• FI_DI_RATIO: FI Over DI Ratio Value
0: If ISO7816 mode is selected, the baud rate generator does not generate a signal.
1 - 2047: If ISO7816 mode is selected, the baud rate is the clock provided on CLK divided by FI_DI_RATIO.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––– FI_DI_RATIO[10:8]
76543210
FI_DI_RATIO[7:0]
612
32072H–AVR32–10/2012
AT32UC3A3
25.7.13 Number of Errors Register
Name: NER
Access Type: Read-only
Offset: 0x44
Reset Value: 0x00000000
• NB_ERRORS: Number of Errors
Total number of errors that occurred during an ISO7816 transfer. Thi s register is automatica lly cleared when read.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
NB_ERRORS
613
32072H–AVR32–10/2012
AT32UC3A3
25.7.14 IrDA Filter Register
Name: IFR
Access Type: Read-write
Offset: 0x4C
Reset Value: 0x00000000
This register can only be written if write protection is disabled in the “Write Protect Mode Register” (WPMR.WPEN is ze ro).
• IRDA_FILTER: IrDA Filter
Configures the IrDA demodulator filter.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
IRDA_FILTER
614
32072H–AVR32–10/2012
AT32UC3A3
25.7.15 Manchester Configuration Register
Name: MAN
Access Type: Read-write
Offset: 0x50
Reset Value: 0x30011004
This register can only be written if write protection is disabled in the “Write Protect Mode Register” (WPMR.WPEN is ze ro).
• DRIFT: Drift cCompensation
0: The USART can not recover from a clock drift.
1: The USART can recover from clock drift (only available in 16x oversampling mode).
• RX_MPOL: Receiver Manchester Polarity
0: Zeroes are encoded as zero-to-one transitions, and ones are encoded as a one-to-zero transitions.
1: Zeroes are encoded as one-to-zero transitions, and ones are encoded as a zero-to-one transitions.
• RX_PP: Receiver Preamble Pattern detected
• RX_PL: Receiver Preamble Length
0: The receiver preamble pattern detection is disabled.
1 - 15: The detected preamble length is RX_PL bit periods.
• TX_MPOL: Transmitter Manchester Polarity
0: Zeroes are encoded as zero-to-one transitions, and ones are encoded as a one-to-zero transition s.
1: Zeroes are encoded as one-to-zero transitions, and ones are encoded as a zero-to-one transitions.
31 30 29 28 27 26 25 24
– DRIFT 1 RX_MPOL – – RX_PP
23 22 21 20 19 18 17 16
–––– RX_PL
15 14 13 12 11 10 9 8
– – – TX_MPOL – – TX_PP
76543210
–––– TX_PL
Table 25-27.
RX_PP Preamble Pattern default polarity assumed (RX_MPOL field not set)
0 0 ALL_ONE
0 1 ALL_ZERO
10ZERO_ONE
11ONE_ZERO
615
32072H–AVR32–10/2012
AT32UC3A3
• TX_PP: Transmitter Preamble Pattern
• TX_PL: Transmitter Preamble Length
0: The transmitter preamble pattern generation is disabled.
1 - 15: The preamble length is TX_PL bit periods.
Table 25-28.
TX_PP Preamble Pattern default polarity assumed (TX_MPOL field not set)
0 0 ALL_ONE
0 1 ALL_ZERO
10ZERO_ONE
11ONE_ZERO
616
32072H–AVR32–10/2012
AT32UC3A3
25.7.16 LIN Mode Register
Name: LINMR
Access Type: Read-write
Offset: 0x54
Reset Value: 0x00000000
• PDCM: Peripheral DMA Contr oller Mode
0: The LIN mode register is not wri t ten by the Per ipheral DMA Controller.
1: The LIN mode register, except for this bit, is written by the Peripheral DMA Controller.
• DLC: Data Length Control
0 - 255: If DLM=0 this field defines the response data length to DLC+1 bytes.
• WKUPTYP: Wakeup Signal Type
0: Writing a one to CR.LINWKUP will send a LIN 2.0 wakeup signal.
1: Writing a one to CR.LINWKUP will send a LIN 1.3 wakeup signal.
• FSDIS: Frame Slot Mode Disable
0: The F rame Slot mode is enabled.
1: The Frame Slot mode is di sa bled.
• DLM: Data Length Mode
0: The response data length is defined by DLC.
1: The response data length is defined by bits 4 and 5 of the Identifier (LINIR.IDCHR).
• CHKTYP: Checksum Type
0: LIN 2.0 “Enhanced” checksum
1: LIN 1.3 “Classic” checksum
• CHKDIS: Checksum Disable
0: Checksum is automatically computed and sent when master, an d checked when slave.
1: Checksum is not computed and sent, nor checked.
• PARDIS: Parity Disable
0: Identifier parity is automaticall y computed and sent when master, and checked when slave.
1: Identifier parity is not computed and sent, nor checked.
• NACT: LIN Node Action
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––––––PDCM
15 14 13 12 11 10 9 8
DLC
76543210
WKUPTYP FSDIS DLM CHKTYP CHKDIS PARDIS NACT
Table 25-29.
NACT Mode Description
0 0 PUBLISH: The USART transmits the response.
617
32072H–AVR32–10/2012
AT32UC3A3
0 1 SUBSCRIBE: The USART receives the response.
1 0 IGNORE: The USART does not transmit and does not receive the response.
11Reserved
Table 25-29.
618
32072H–AVR32–10/2012
AT32UC3A3
25.7.17 LIN Identifier Registe r
Name: LINIR
Access Type: Read-write or Read-only
Offset: 0x58
Reset Value: 0x00000000
• IDCHR: Identifier Character
If USART is in LIN master mode, the IDCHR field is read-write, and its value is the Identifier character to be transmitted.
If USART is in LIN slave mode, the IDCHR field is read-only, and its value is the last received Identifier character.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
IDCHR
619
32072H–AVR32–10/2012
AT32UC3A3
25.7.18 Write Protect Mode Register
Register Name: WPMR
Access Type: Read-write
Offset: 0xE4
Reset Value: See Table 25-17
• WPKEY: Write Protect KEY
Has to be written to 0x555341 (“USA” in ASCII) in order to successfully write WPEN. This bit always reads as zero. Writing the
correct key to this field clears WPSR.WPVSRC and WPSR.WPVS.
• WPEN: Write Protect Enable
0: Write protection disabled.
1: Write protection enabled.
Protects the registers:
•”Mode Register” on page 596
•”Baud Rate Generator Register” on page 607
•”Receiver Time-out Register” on page 609
•”Transmitter Timeguard Register” on page 610
•”FI DI Ratio Register” on page 611
•”IrDA Filter Register” on page 613
•”Manchester Configuration Register” on page 614
31 30 29 28 27 26 25 24
WPKEY[23:16]
23 22 21 20 19 18 17 16
WPKEY[15:8]
15 14 13 12 11 10 9 8
WPKEY[7:0]
76543210
-------WPEN
620
32072H–AVR32–10/2012
AT32UC3A3
25.7.19 Write Protect Status Register
Register Name: WPSR
Access Type: Read-only
Offset: 0xE8
Reset Value: See Table 25-17
• WPVSRC: Write Protect Violation Source
If WPVS is one, this field indicates which write-protected register wa s unsuccessfully written to , either by address offset or code.
• WPVS: Write Protect Violation Status
0: No write protect violation has occurred since the last WPSR read.
1: A write protect violati on has occurred since the last WPSR read.
Note: Reading WPSR automatically clears all fields. Writing the correct key to WPSR.WPKEY clears all fields.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
WPVSRC[15:8]
15 14 13 12 11 10 9 8
WPVSRC[7:0]
76543210
-------WPVS
621
32072H–AVR32–10/2012
AT32UC3A3
25.7.20 Version Register
Name: VERSION
Access Type: Read-only
Offset: 0xFC
Reset Value: -
•MFN
Reserved. No functionality associated.
• VERSION
Version of the modul e. No functionality associated.
26.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
---- MFN
15 14 13 12 11 10 9 8
---- VERSION[11:8]
76543210
VERSION[7:0]
622
32072H–AVR32–10/2012
AT32UC3A3
26.1 Module Configuration
The specific configuration for each USART instance is listed in the following tables.The module
bus clocks listed here are connected to the system bus clocks according to the table in the Sys-
tem Bus Clock Connections section.
26.1.1 Clock Connections
Each USART can be connected to an internally divided clock:
Table 26-1. Module Configuration
Feature
USART0
USART2
USART3 USART1
SPI Logic Implemented Impl emented
LIN Logic Implemented Implemented
Manchester Logic Not Implemented Implemented
Modem Logic Not Implemented Implemented
IRDA Logic Not Implemen ted Implemented
RS485 Logic Not Implemented Implemented
Fractional Baudrate Imple mented Implemented
ISO7816 Not Implemen ted Implemented
DIV value for divided CLK_USART 8 8
Receiver Time-out Counter Size
(Size of the RTOR.TO field) 8-bits 17-bits
Table 26-2. Module Clock Name
Module name Clock name Description
USAR T0 CLK_USART0 Peripheral Bus clock from the PBA clock domain
USAR T1 CLK_USART1 Peripheral Bus clock from the PBA clock domain
USAR T2 CLK_USART2 Peripheral Bus clock from the PBA clock domain
USAR T3 CLK_USART3 Peripheral Bus clock from the PBA clock domain
Table 26-3. USART Clock Connections
USART Source Name Connection
0
Internal CLK_DIV
PBA Clock / 8 (CLK_PBA_USART_DIV)
1 PBA Clock / 8 (CLK_PBA_USART_DIV)
2 PBA Clock / 8 (CLK_PBA_USART_DIV)
3 PBA Clock / 8 (CLK_PBA_USART_DIV)
623
32072H–AVR32–10/2012
AT32UC3A3
26.1.2 Register Reset Values
Table 26-4. Register Reset Values
Register Reset Value
VERSION 0x00000420
624
32072H–AVR32–10/2012
AT32UC3A3
27. Hi-Speed USB Interface (USBB)
Rev: 3.2.0.18
27.1 Features •Compatible with the USB 2.0 specification
•Supports High (480Mbit/s), Full (12Mbit/s) and Low (1.5Mbit/s) speed Device and Embedded Host
•eight pipes/en dp oints
•2368bytes of Embedded Dual-Por t RAM (DPRAM) for Pipes/Endpoi nts
•Up to 2 memory banks per Pipe/Endpoint (Not for Control Pipe/Endpoint)
•Flexible Pipe/Endpoint configuration and manageme nt with dedicate d DMA channels
•On-Chip UTMI transceiver including Pull-Ups/Pull-downs
•On-Chip pad including VBUS analog comparator
27.2 Overview The Universal Serial Bus (USB) MCU device complies with the Universal Serial Bus (USB) 2.0
specification, in all speeds.
Each pipe/endpoint can be configured in one of several transfer types. It can be associated with
one or more banks of a dual-port RAM (DPRAM) used to store the current data payload. If sev-
eral banks are used (“pin g-pong” mode ), then one DPRAM ba nk is read or writte n by the CPU or
the DMA while the other is read or written by the USBB core. This feature is mandatory for iso-
chronous pipes/endpoints.
Table 27-1 on page 624 describes the hardware configuration of the USB MCU device.
The theoretical maximal pipe/endpoint configuration (3648bytes) exceeds the real DPRAM size
(2368bytes). The user needs to be aware of this when configuring pipes/endpoints. To fully use
the 2368bytes of DPRAM, the user could for example use the configuration described inTable
27-2 on page 624.
Table 27-1. Description of USB Pipes/Endpoints
Pipe/Endpoint Mnemonic Max. Size Max. Nb. Banks DMA Type
0 PEP0 64 bytes 1 N Control
1 PEP1 512 bytes 2 Y Isochronous/Bulk/Interrupt/Control
2 PEP2 512 bytes 2 Y Isochronous/Bulk/Interrupt/Control
3 PEP3 512 bytes 2 Y I sochronous/Bulk/Interrupt
4 PEP4 512 bytes 2 Y Isochronous/Bulk/Interrupt/Control
5 PEP5 512 bytes 2 Y Isochronous/Bulk/Interrupt/Control
6 PEP6 512 bytes 2 Y Isochronous/Bulk/Interrupt/Control
7 PEP7 512 bytes 2 Y Isochronous/Bulk/Interrupt/Control
Table 27-2. Example of Configuration of Pipes/Endpoints Using the Whole DPRAM
Pipe/Endpoint Mnemonic Size Nb. Banks
0PEP064 bytes1
625
32072H–AVR32–10/2012
AT32UC3A3
27.3 Block Diagram
The USBB provides a har dware device to interf ace a USB link to a dat a flow stored in a dual- port
RAM (DPRAM).
The UTMI transceiver requires an external 12MHz clock as a reference to its internal 480MHz
PLL. The internal 480MHz PLL is used to clock an internal DLL module to recover the USB dif-
ferential data at 480Mbit/s.
Figure 27-1. USBB Block Diagram
1 PEP1 512 bytes 2
2 PEP2 512 bytes 2
3 PEP3 256 bytes 1
Table 27-2. Example of Configuration of Pipes/Endpoints Using the Whole DPRAM
Pipe/Endpoint Mnemonic Size Nb. Banks
HSB Mux
Slave
Master
HSB
PB
DMA
HSB0
HSB1
Slave
Local HSB
Slave
Interface
User
Interface
USB
2.0 Core
DPRAM
PEP
Allocation
USB_VBUS
DMFS
DPFS
USB_ID
USB_VBOF
I/O
Controller
UTMI DMHS
DPHS
Master
GCLK_USBB
626
32072H–AVR32–10/2012
AT32UC3A3
27.4 Application Block Diagram
Depending on the USB operating mode (device-only, reduced-host modes) and the power
source (bus-powered or self-powered), there are different typical hardware implementations.
27.4.1 Device Mode
27.4.1.1 Bus-Powered device
Figure 27-2. Bus-Powered Device Application Block Diagram
USB
2.0 Core
USB_VBUS
DMFS
DPFS
USB_ID
USB_VBOF
I/O
Controller
UTMI DMHS
DPHS
USB
Connector
VBus
D-
D+
ID
GND
39 ohms
39 ohms
3.3 V
Regulator
VDD
627
32072H–AVR32–10/2012
AT32UC3A3
27.4.1.2 Se lf-Powered device
Figure 27-3. Self-powered Device Application Block Diagram
27.4.2 Host Mode
Figure 27-4. Host Application Block Diagram
USB
2.0 Core
USB_VBUS
DMFS
DPFS
USB_ID
USB_VBOF
I/O
Controller
UTMI DMHS
DPHS
USB
Connector
VBus
D-
D+
ID
GND
39 ohms
39 ohms
USB
2.0 Core
USB_VBUS
DMFS
DPFS
USB_ID
USB_VBOF
I/O
Controller
UTMI DMHS
DPHS
USB
Connector
VBus
D-
D+
ID
GND
39 ohms
39 ohms
5V DC/DC
Generator
VDD
628
32072H–AVR32–10/2012
AT32UC3A3
27.5 I/O Lines Description
Table 27-3. I/O Lines Description
PIn Name Pin Description Type Active Level
USB_VBOF USB VBus On/Off: Bus Power Control Port Output VBUSPO
USB_VBUS VBus: Bus Power Measurement Port Input
DMFS FS Data -: Full-Speed Differential Data Line - Port Input/Output
DPFS FS Data +: Full-Speed Differential Data Line + Po rt Input/Output
DMHS HS Data -: Hi-Speed Differential Data Line - Port Input/Output
DPHS H S Data +: Hi-Speed Differential Data Line + Port Input/Output
USB_ID USB Identification: Mini Connector Identificati on Port Inp ut Low: Mini-A plug
High Z: Mini-B plu g
629
32072H–AVR32–10/2012
AT32UC3A3
27.6 Product Dependencies
In order to use t his modu le, othe r p arts o f th e syst em must be conf igu red cor re ctly, as de scr ibed
below.
27.6.1 I/O Lines The USB_VBOF and USB_ID pins are multiplexed with I/O Controlle r lines and may also be
multiplexed with lines of other peripherals. In order to use them with the USB, the user must first
configure the I/O Controller to assign them to their USB peripheral functions.
If USB_ID is u sed, the I/O Controller must be configured to enable the internal pull-up resistor of
its pin.
If USB_VBOF or USB_ID is not used by the application, the corresponding pin can be used for
other purposes by the I/O Controller or by other perip herals.
27.6.2 Clocks The clock for the USBB bus interface (CLK_USBB) is generated by the Power Manager. This
clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to dis-
able the USBB before disabling the clock, to avoid freezing the USBB in an undefined state.
The UTMI transceive r needs a 12MHz clock as a clock reference for its inte rnal 480MHz PLL.
Before using the USB, the user must ensure that this 12MHz clock is ava ilable. The 12 M Hz
input is connected to a Ge neric Clock (GCLK_USBB) provided by the Power Manager.
27.6.3 Interrupts The USBB interrupt request line is connected to the interrupt controller. Using the USBB inter-
rupt requires the interrupt controller to be programmed first.
630
32072H–AVR32–10/2012
AT32UC3A3
27.7 Functional Description
27.7.1 USB General Operation
27.7.1.1 Introduction After a hard ware reset, the USBB is disabled. When enabled, the USBB runs either in device
mode or in host mode according to the ID detection.
If the USB_ID pin is not conn ected to ground, the USB_ID Pin State bit in the General Status
register (USBSTA.ID) is set (the internal pull-up resistor of the USB_ID pin must be enabled by
the I/O Controller) and device mode is engaged.
The USBSTA.ID bit is cleared when a low level has been de tected on the USB_ID pin. Host
mode is then engaged.
27.7.1.2 Power-On and rese t
Figure 27-5 on page 630 describes the USBB main states.
Figure 27-5. General States
After a hardware reset, the USBB is in the Reset state. In this state:
• The macro is disabled. The USBB Enable bit in the General Control register
(USBCON.USBE) is zero.
• The macro clock is stopped in orde r to m inimize pow er consu mptio n. Th e Freeze USB Cloc k
bit in USBCON (USBON.FRZCLK) is set.
• The UTMI is in suspend mode.
• The internal states and registers of the device and host modes are reset.
• The DPRAM is not cleared and is accessible.
• The USBSTA.ID bit and the VBus Level bit in the UBSTA (UBSTA.VBUS) reflect the states of
the USB_ID and USB_VBUS input pins.
• The OTG Pad Enable (OTGPADE) bit, the VBus Polarity (VBUSPO) bit, the FRZCLK bit, the
USBE bit, the USB_ID Pin Enable (UIDE) bit, the USBB Mode (UIMOD) bit in USBCON, and
the Low-Speed Mode Force bit in the Device General Control (UDCON.LS) register can be
written by softw are, so that the user can pro gram pads an d speed bef ore enab ling the macro,
but their value is only taken into account once the macro is ena bled and unfrozen.
Device
Reset
USBE = 0
<any
other
state>
USBE = 1
ID = 1
Macro off:
USBE = 0
Clock stopped:
FRZCLK = 1
USBE = 0
Host
USBE = 0
HW
RESET
USBE = 1
ID = 0
631
32072H–AVR32–10/2012
AT32UC3A3
After writing a one to USBCON.USBE, the USBB enters the Device or the Host mode (according
to the ID detection) in idle state.
The USBB can be disabled at any time by writing a zero to USBCON.USBE. In fact, writing a
zero to USBCON.USBE acts as a hardware reset, except that the OTGPADE, VBUSPO,
FRZCLK, UIDE, UIMOD and, LS bits are not reset.
27.7.1.3 Interrupts One interrupt vector is assigned to the USB interface. Figure 27-6 on page 632 shows the struc-
ture of the USB interrupt system.
632
32072H–AVR32–10/2012
AT32UC3A3
Figure 27-6. Interrupt Syst em
See Section 27.7 .2 .1 9 an d Section 27.7.3.13 for further details about de vice a nd host interr up ts.
There are two kinds of general interrupts: processing, i.e. their generation is part of the normal
processing, and exception, i.e. errors (not related to CPU exceptions).
USBCON.IDTE
USBSTA.IDTI
USBSTA.VBUSTI
USBCON.VBUSTE
USBSTA.SRPI
USBCON.SRPE
USBSTA.VBERRI
USBCON.VBERRE
USBSTA.BCERRI
USBCON.BCERRE
USBSTA.ROLEEXI
USBCON.ROLEEXE
USBSTA.HNPERRI
USBCON.HNPERRE
USBSTA.STOI
USBCON.STOE
USB General
Interrupt
USB Device
Interrupt
USB Host
Interrupt
USB
Interrupt
Asynchronous interrupt source
UDINTE.SUSPE
UDINT.SUSP
UDINT.SOF
UDINTE.SOFE
UDINT.EORST
UDINTE.EORSTE
UDINT.WAKEUP
UDINTE.WAKEUPE
UDINT.EORSM
UDINTE.EORSME
UDINT.UPRSM
UDINTE.UPRSME
UDINT.EPXINT
UDINTE.EPXINTE
UDINT.DMAXINT
UDINTE.DMAXINTE
UHINTE.DCONNIE
UHINT.DCONNI
UHINT.DDISCI
UHINTE.DDISCIE
UHINT.RSTI
UHINTE.RSTIE
UHINT.RSMEDI
UHINTE.RSMEDIE
UHINT.RXRSMI
UHINTE.RXRSMIE
UHINT.HSOFI
UHINTE.HSOFIE
UHINT.HWUPI
UHINTE.HWUPIE
UHINT.PXINT
UHINTE.PXINTE
UHINT.DMAXINT
UHINTE.DMAXINTE
UECONX.TXINE
UESTAX.TXINI
UESTAX.RXOUTI
UECONX.RXOUTE
UESTAX.RXSTPI
UECONX.RXSTPE
UESTAX.UNDERFI
UECONX.UNDERFE
UESTAX.NAKOUTI
UECONX.NAKOUTE
UESTAX.NAKINI
UECONX.NAKINE
UESTAX.OVERFI
UECONX.OVERFE
UESTAX.STALLEDI
UECONX.STALLEDE
UESTAX.CRCERRI
UECONX.CRCERRE
UESTAX.SHORTPACKET
UECONX.SHORTPACKETE
UESTAX.DTSEQ=MDATA & UESTAX.RXOUTI
UECONX.MDATAE
UPCONX.RXINE
UPSTAX.RXINI
UPSTAX.TXOUTI
UPCONX.TXOUTE
UPSTAX.TXSTPI
UPCONX.TXSTPE
UPSTAX.UNDERFI
UPCONX.UNDERFIE
UPSTAX.PERRI
UPCONX.PERRE
UPSTAX.NAKEDI
UPCONX.NAKEDE
UPSTAX.OVERFI
UPCONX.OVERFIE
UPSTAX.RXSTALLDI
UPCONX.RXSTALLDE
UPSTAX.CRCERRI
UPCONX.CRCERRE
UPSTAX.SHORTPACKETI
UPCONX.SHORTPACKETIE
UPSTAX.NBUSYBK
UPCONX.NBUSYBKE
UDDMAX_CONTROL.EOT_IRQ_EN
UDDMAX_STATUS.EOT_STA
UDDMAX_STATUS.EOCH_BUFF_STA
UDDMAX_CONTROL.EOBUFF_IRQ_EN
UDDMAX_STATUS.DESC_LD_STA
UDDMAX_CONTROL.DESC_LD_IRQ_EN
UHDMAX_CONTROL.EOT_IRQ_EN
UHDMAX_STATUS.EOT_STA
UHDMAX_STATUS.EOCH_BUFF_STA
UHDMAX_CONTROL.EOBUFF_IRQ_EN
UHDMAX_STATUS.DESC_LD_STA
UHDMAX_CONTROL.DESC_LD_IRQ_EN
USB Device
Endpoint X
Interrupt
USB Host
Pipe X
Interrupt
USB Device
DMA Channel X
Interrupt
USB Host
DMA Channel X
Interrupt
UDINTE.MSOFE
UDINT.MSOF
UESTAX.HBISOINERRI
UECONX.HBISOINERRE
UESTAX.HBISOFLUSHI
UECONX.HBISOFLUSHE
UESTAX.DTSEQ=DATAX & UESTAX.RXOUTI
UECONX.DATAXE
UESTAX.TRANSERR
UECONX.TRANSERRE
UESTAX.NBUSYBK
UECONX.NBUSYBKE
633
32072H–AVR32–10/2012
AT32UC3A3
The processing general interrupts are:
• The ID Transition Interrupt (IDTI)
• The VBus Transitio n In te rrupt (VBUSTI)
• The Role Exchange Interrupt (ROLEEXI)
The exception general interrupts are:
• The VBus Error Interrupt (VBERRI)
• The B-Connection Error Interrupt (BCERRI)
• The Suspend Time-Out Interrupt (STOI)
27.7.1.4 MCU Power modes
•Run mode
In this mode, all MCU clocks can run, including the USB clock.
•Idle mode
In this mode, the CPU is halted, i.e. the CPU clock is stopped. The Idle mode is entered what-
ever the state of the USBB. The MCU wakes up on any USB interrupt.
•Froz en mode
Same as the Idle mode, except that the HSB module is stopped, so the USB DMA, which is an
HSB master, can not be used. Moreover, the USB DMA must be stopped before entering this
sleep mode in order to avoid erratic behavior. The MCU wakes up on any USB interrupt.
•Standby, Stop, DeepStop and Static modes
Same as the Frozen mode, except that the USB generic clock and other clocks are stopped, so
the USB macro is frozen. Only the asynchronous USB interrupt sources can wake up the MCU
in these modes (1). The Power Manager (PM) may ha ve to be configured to enable asynchro-
nous wake up from USB. The USB module must be frozen by writing a one to the FRZCLK bit.
Note: 1. When entering a sleep mode deeper or eq ual to DeepStop, the VBus asynchronous interrupt can not be triggered beca use
the bandgap voltage reference is off. Thus this interrupt should be di sabled (USBCON.VBUSTE = 0).
•USB clock frozen
In the run, idle and frozen MCU modes, the USBB can be frozen when the USB line is in the sus-
pend mode, by writing a one to the FRZCLK bit, what reduces power consumption.
In deeper MCU power modes (from StandBy mode), the USBC must be frozen.
In this case, it is still possible to access the following elements, but only in Run mode:
• The OTGPADE, VBUSPO, FRZCLK, USBE, UIDE, UIMOD and LS bits in the USBCON
register
• The DPRAM (through the USB Pipe/Endpoint n FIFO Data (USBFIFOnDATA) registers, but
not through USB bus transfers which are frozen)
634
32072H–AVR32–10/2012
AT32UC3A3
Moreover, when FRZCLK is written to one, only the asynchronous interrupt sources may trigger
the USB interrupt:
• The ID Transition Interrupt (IDTI)
• The VBus Transitio n In te rrupt (VBUSTI)
• The Wake-up Interrupt (WAKEUP)
• The Host Wake-up Interrupt (HWUPI)
•USB Suspend mode
In peripheral mode, the Suspend Interrupt bit in the Device Global Interrupt register
(UDINT.SUSP)indicates that the USB line is in the suspend mode. In this case, the transceiver
is automatically set in suspend mode to reduce the consumption.Th e 480MHz internal PLL is
stopped. The USBSTA.CLKUSABLE bit is cleared.
27.7.1.5 Speed control
•Device mode
When the USB interf ace is in device mode, t he speed sele ction (full-speed or high-spe ed) is per-
formed automatically by the USBB during the USB reset according to the host speed capability.
At the end of the USB reset, the USBB enables or disables high-speed terminations and pull-up.
It is possible to restraint the USBB to full-speed or low-speed mode by handling the LS and the
Speed Configuration (SPDCONF) bits in UDCON.
•Host mode
When the USB interface is in host mode, internal pull-down resistors are connected on both D+
and D- and the interface detects the speed of the conne cted device, which is reflected by the
Speed Status (SPEED) field in USBSTA.
27.7.1.6 DPRAM management
Pipes and endpo ints can only be a llocated in ascendin g order (from the pipe/endpoint 0 to the
last pipe/endpoint to be allocated). The user shall therefore con figure them in the same order.
The allocation of a pipe/end point n starts when the Endp oint Memory Allocate bit in the Endpo int
n Configuration register (U ECFGn.ALLOC) is written to one. Then, the h ardware allocates a
memory area in the DPRAM and inserts it between the n-1 and n+1 pipes/endpoints. The n+1
pipe/endpoint memory window slides up and its data is lost. Note that the following pipe/end-
point memory windows (from n+2) do not slide.
Disabling a pipe, by writing a zero to the Pipe n Enable bit in the Pipe Enable/Reset register
(UPRST.PENn), or disabling an endpoint, by writing a zero to the Endpoint n Enable bit in the
Endpoint Enable/Reset register (UERST.EPENn), resets neither the UECFGn.ALLOC bit nor its
configuration (the Pipe Banks (PBK) field, the Pipe Size (PSIZE) field, the Pipe Token (PTO-
KEN) field, the Pipe Type (PTYPE) field, the Pipe Endpoint Number (PEPNUM) field, and the
Pipe Interrupt Requ est Frequency (INTFRQ) field in the Pipe n Configuration ( UPCFGn) regis-
ter/the Endpoint Banks (EPBK) field, the Endpoint Size (EPSIZE) field, the Endpoint Direction
(EPDIR) field, and the Endpoint Type (EPTYPE) field in UECFGn).
635
32072H–AVR32–10/2012
AT32UC3A3
To free its memory, the user shall write a zero to the UECFGn.ALLOC bit. The n+1 pipe/end-
point memory window then slides down and its data is lost. Note that the following pipe/endpoint
memory windows (from n+2) does not slide.
Figure 27-7 on page 635 illustrates the allocation and reorganization of the DPRAM in a typical
example.
Figure 27-7. Allocation and Reorgan ization of the DPRAM
1. The pipes/endpoints 0 to 5 are enabled, configured and allocated in ascending order.
Each pipe/endpoint then owns a memory area in the DPRAM.
2. The pipe/endpoint 3 is disabled, but its memory is kept allocated by the controller.
3. In order to free its memory, its ALLOC bit is written to zero. The pipe/endpoint 4 mem-
ory window slides down, but the pipe/endpoint 5 does not move.
4. If the user chooses to reconfigure the pipe/endpoint 3 with a larger size, the controller
allocates a memory area after the pipe/endpoint 2 memory area and automatically
slides up the pip e/endpo int 4 m emory window. The pipe/endpoint 5 doe s not mov e and
a memory conflict appears as the memory windows of the pipes/endpoints 4 and 5
overlap. The data of these pipes/endpoints is potentially lost.
Note that:
• There is no way the data of the pipe/endpoint 0 can be lost (except if it is de-allocated) as
memory allocation and de-allocation may affect only higher pipes/ endpoints.
• Deactivating then reactivating a same pipe/endpoint with the same configuration only
modifies temporarily the controller DPRAM pointer and size for this pipe/endpoint, but
nothing change s in the DPRAM, so higher endpoin ts seem to not ha v e be en mo v ed and their
data is preserve d as f ar a s nothing has be en written or receiv ed into them while changing th e
allocation state of the first pipe/endpoint.
• When the user write a one to the ALLOC bit, the Configuration OK Status bit in the Endpoint
n Status register (UESTAn.CFGOK) is set only if the configur ed size and number of banks
are correct compared to their maximal allowed values for the endpoint and to the maximal
Free Memory
PEP0
PEP1
PEP2
PEP3
PEP4
PEP5
U(P/E)RST.(E)PENn = 1
U(P/E)CFGn.ALLOC = 1
Free Memory
PEP0
PEP1
PEP2
PEP4
PEP5
Free Memory
PEP0
PEP1
PEP2
PEP4
PEP5
Pipe/Endpoint 3
Disabled
Pipe/Endpoint 3
Memory Freed
Free Memory
PEP0
PEP1
PEP2
PEP3 (larger size)
PEP5
Pipe/Endpoint 3
Activated
PEP4 Lost Memory
PEP4 Conflict
U(P/E)RST.(E)PEN3 = 0
PEP3
(ALLOC stays at 1)
U(P/E)CFG3.ALLOC = 0 U(P/E)RST.(E)PEN3 = 1
U(P/E)CFG3.ALLOC = 1
Pipes/Endpoints 0..5
Activated
636
32072H–AVR32–10/2012
AT32UC3A3
FIFO size (i.e. the DPRAM size), so the value of CFGOK does not consider memory
allocation conflicts.
27.7.1.7 Pad SuspendFigure 27-8 on page 636 shows the pad behavior.
Figure 27-8. Pad Behavior
• In the Idle state, the pad is put in low power consumption mode, i.e., the differential receiver
of the USB pad is off, and internal pull-do wn with strong v alue(15 K) are set in both DP/DM to
avoid floating lines.
• In the Active state, the pad is working.
Figure 27-9 on page 636 illustrates the pad events leading to a PAD state change.
Figure 27-9. Pad Events
The SUSP bit is set and the Wake-Up Interrupt (WAKEU P) bit in UDINT is cleared when a USB
“Suspend” state has been detected on the USB bus. This event automatically puts the USB pad
in the Idle state. The detection of a non-idle event sets WAKEUP, clears SUSP and wakes up
the USB pad.
Idle
Active
USBE = 1
& DETA CH = 0
& Suspend
USBE = 0
| DETACH = 1
| Suspend
SUSP
Suspend detected Cleared on wake-up
Wake-up detected Cleared by software to acknowledge the interrupt
WAKEUP
PAD State
Active
Idle
Active
637
32072H–AVR32–10/2012
AT32UC3A3
Moreover, the pa d goes to the Id le state if the macro is disabled or if the DETACH bit is written to
one. It returns to the Active state when USBE is written to one and DETACH is written to zero.
27.7.1.8 Plug-In detection
The USB connection is det ected from the USB_VBUS pad. Fig ure 27- 10 on page 63 7 shows the
architectur e of the plu g- i n detector.
Figure 27-10. Plug-In Detection Input Block Diagram
The control logic of the USB_VBUS pad out puts two signals:
• The Session_valid signal is high when the voltage on the USB_VBUS pad is higher than or
equal to 1.4V.
• The Va_Vbus_valid signal is high when the voltage on the USB_VBUS pad is higher than or
equal to 4.4V.
In device mode, the USBSTA.VBUS bit follows the Session_valid comparator output:
• It is set when the voltage on the USB_VBUS pad is higher than or equal to 1.4V.
• It is cleared when the voltage on the VBUS pad is lower than 1.4V.
In host mode, the USBSTA.VBUS bit follows an hysteresis based on Session_valid and
Va_Vbus_valid:
• It is set when the voltage on the USB_VBUS pad is higher than or equal to 4.4V.
• It is cleared when the voltage on the USB_VBUS pad is lower than 1.4V.
The VBus Transition interrupt (VBUSTI) bit in USBSTA is set on each transition of the USB-
STA.VBUS bit.
The USBSTA.VBUS bit is effective whether the USBB is enabled or not.
27.7.1.9 ID detection Figure 27-11 on page 638 shows how the ID transitions are detected.
VBUSTI
USBSTA
USB_VBUS VBUS
USBSTA
GND
VDD
Pad Logic
Logic
Session_valid
Va_Vbus_valid
RPU
RPD
VBus_pulsing
VBus_discharge
638
32072H–AVR32–10/2012
AT32UC3A3
Figure 27-11. ID Detection Input Block Diagram
The USB mode (device or host) can be either detected from the USB_ID pin or software
selected by writing to the UIMOD bit, according to the UIDE bit. This allows the USB_ ID pin to be
used as a general purpose I/O pin even when the USB interface is enabled.
By default, the USB_ID pin is selected (UIDE is written to one) and the USBB is in device mode
(UBSTA.ID is one), what corresponds to the case where no Mini-A plug is connected, i.e. no
plug or a Mini-B plug is connected and the USB_ID pin is kept high by the internal pull-up resis-
tor from the I/O Controller (which must be enabled if USB_ID is used).
The ID Transition Interrupt (IDTI) bit in USBSTA is set on each transition of the ID bit, i.e. when a
Mini-A plug (host mode) is connected or disconnected. This does not occur when a Mini-B plug
(device mode) is connected or disconnected.
The USBSTA.ID bit is effective whether the USBB is enabled or not.
RPU
UIMOD
USBCON
USB_ID ID
USBSTA
VDD
UIDE
USBCON
1
0IDTI
USBSTA
I/O Controller
639
32072H–AVR32–10/2012
AT32UC3A3
27.7.2 USB Device Operation
27.7.2.1 Introduction In device mode, the USBB supports hi- full- and low-speed data transfers.
In addition to the default control endpoint, seven endpoints are provided, which can be config-
ured with the types isoch ronous, bulk or interrupt, as described in .Table 27-1 on page 624.
The device mode starts in th e Idle state, so the pad consumption is red uced to the minimum.
27.7.2.2 Power-On and rese t
Figure 27-12 on page 639 describes the USBB device mode main states.
Figure 27-12. Device Mode States
After a hardware reset, the USBB device mode is in the Reset state. In this state:
• The macro clock is stop ped in order to minimize power consumption (FRZCLK is written to
one).
• The internal registers of the device mode are reset.
• The endpoint banks are de-allocated.
• Neither D+ nor D- is pulled up (DETACH is written to one).
D+ or D- will be pulled up according to the selected speed as soon as the DETACH bit is written
to zero and VBus is presen t. See “Device mode” for further details.
When the USBB is enabled (USBE is written to one) in device mode (ID is one), its device mode
state goes to the Idle state with minimal power consumption. This do es not require the USB
clock to be activated.
The USBB device mode can be disabled and reset at any time by disabling the USBB (by writing
a zero to USBE) or when host mode is engaged (ID is zero).
27.7.2.3 USB rese t The USB bus reset is managed by hardware. It is initiated by a connected host.
When a USB reset is detected on the USB line, the following operations are performed by the
controller:
• All the endpoints are disabled, except the default control endpoint.
Reset
Idle
H W
RESET
USBE = 0
| ID = 0
<any
other
state>
USBE = 0
| ID = 0
U SBE = 1
& ID = 1
640
32072H–AVR32–10/2012
AT32UC3A3
• The default control endpoint is reset (see Section 27.7 .2 .4 for more details).
• The data toggle sequence of the default control endpoint is cleared.
• At the end of the reset process, the End of Reset (EORST) bit in UDINT interrupt is set.
• During a reset, the USBB automatically switches to the Hi-Speed mode if the host is Hi-
Speed capable (the reset is called a Hi-Speed reset). The user should observe the
USBSTA.SPEED field to know the speed running at the end of the reset (EORST is one).
27.7.2.4 En dp o int re se t
An endpoint can be reset at any time by writing a one to the Endpo int n Reset (EPRSTn) bit in
the UERST register. This is recommended before using a n endpoint upon hardware reset or
when a USB bus reset has been received. This resets:
• The internal state machine of this endpoint.
• The receive and transmit bank FIFO counters.
• All the registers of this endpoint (UECFGn, UESTAn, the Endpoint n Control (UECONn)
register), except its configuration (ALLOC, EPBK, EPSIZE, EPDIR, EPTYPE) and the Data
Toggle Sequence (DTSEQ) field of the UESTAn register.
Note that the interrupt sources located in the UESTAn register are not cleared when a USB bus
reset has been received.
The endpoint configuration remains active and the endpoint is still enabled.
The endpoint reset may be associated with a clear of the data toggle sequence as an answer to
the CLEAR_FEATURE USB request. Th is can be achieved by writing a one to the Reset Data
Toggle Set bit in the Endpoint n Control Set register (UECONnSET .RSTDTS).(This will set the
Reset Data Toggle (RSTD) bit in UECONn).
In the end, the user h as to wr ite a zer o t o the EPRSTn b it t o com plete t he rese t o per at ion and to
start using the FI FO.
27.7.2.5 En dp o int ac tivation
The endpoint is maintained inactive and reset (see Section 27 .7.2 .4 for more details) as long as
it is disabled (EPENn is written to zero). DTSEQ is also reset.
The algorithm repre sented on Fig ure 27- 13 on page 64 1 must be followed in order to activate an
endpoint.
641
32072H–AVR32–10/2012
AT32UC3A3
Figure 27-13. Endpoint Activation Algorithm
As long as the endpoint is not correctly configured (CFGOK is zero), the controller does not
acknowledge the packets sent by the host to this endpoint.
The CFGOK bit is set only if the configured size and number of banks are correct compared to
their maximal allowed values for the endpoint (see Table 27-1 on page 624) and to the maximal
FIFO size (i.e. the DPRAM size).
See Section 27.7 .1 .6 for more details about DPRAM manag ement.
27.7.2.6 Address setup
The USB device address is set up according to the USB protocol.
• After all kinds of resets, the USB device address is 0.
• The host starts a SETUP transaction with a SET_ADDRESS(addr) request.
• The user write this address to the USB Address (UADD) field in UDCON, and write a zero to
the Address Enable (ADDEN) bit in UDCON, so the actual address is still 0.
• The user sends a zero-length IN packet from the control endpoint.
• The user enables the recorded USB device address by writing a one to ADDEN.
Once the USB device address is configured, the controller filters the packets to only accept
those targeting th e address stored in UADD.
UADD and ADDEN shall not be written all at once.
UADD and ADDEN are cleared:
• On a hardware rese t.
• When the USBB is disabled (USBE written to zero).
• When a USB reset is detected.
When UADD or ADDEN is cleared, the default device address 0 is used.
Endpoint
Activation
CFGOK ==
1?
ERROR
Yes
Endpoint
Activated
Enable the endpoint.
EPENn = 1
Test if the endpoint configuration is correct.
UECFGn
EPTYPE
EPDIR
EPSIZE
EPBK
ALLOC
Configure the endpoint:
- type
- direction
- size
- number of banks
Allocate the configured DPRAM banks.
No
642
32072H–AVR32–10/2012
AT32UC3A3
27.7.2.7 Su sp en d an d wake-up
When an idle USB bus state has been detected for 3ms, the controller set the Suspend (SUSP)
interrupt bit in UDINT. T he user may then write a one to the FRZC LK bit to reduce power con-
sumption. The MCU can also enter the Idle or Frozen sleep mode to lower again power
consumption.
To recover from the Suspend mode , the user shall wait for the Wake- Up (WAKEUP) interrupt bit ,
which is set when a non-idle event is detected, then write a zero to FRZCLK.
As the WAKEUP in terr upt bit in UDINT is set when a non-idle event is detected, it can occur
whether the controller is in the Suspend mode or not. The SUSP and WAKEUP interrupts are
thus independent of each other except that one bit is cleared when the other is set.
27.7.2.8 Detach The reset value of the DETACH bit is one.
It is possible to initiate a device re-enumeration simply by writing a one then a zero to DETACH.
DETACH acts on the pull-up connections of the D+ and D- pads. See “Device mode” for further
details.
27.7.2.9 Remote wake-up
The Remote Wake- Up request (also known as Upstre am Resume) is the only one the device
may send on its own initiative, but the device should have beforehand been allowed to by a
DEVICE_REMOTE_WAKEUP request from the host.
• First, the USBB must have detected a “Suspend” state on the bus, i.e. the Remote Wake-Up
request can only be sent after a SUSP interrupt has been set.
• The user may then write a one to the Remote W ake-Up (RMWKUP) bit in UDCON to send an
upstream resume to the host for a remote wake-up. This will automatically be done by the
controller after 5ms of inactivity on the USB bus.
• When the controller sends the upstream resume, the Upstream Resume (UPRSM) interrupt
is set and SUSP is cleared.
• RMWKUP is cleared at the end of the upstream resume.
• If the controller detects a valid “End of Resume” signal from the host, the End of Resume
(EORSM) interrupt is set.
27.7.2.10 STALL request
For each endpoint, the STALL management is performed using:
• The STALL Request (STALLRQ) bit in UECONn to initiate a STALL request.
• The STALLed Interrupt (STALLEDI) bit in UESTAn is set when a STALL handshake has be en
sent.
To answer the next request with a STALL handshake, STALLRQ has to be set by writing a one
to the STALL Request Set (STALLRQS) bit. All following requests will be discarded (RXOU TI,
etc. will not be set) and handshaked with a STALL until the STALLRQ bit is cleared, what is
done when a new SETUP packet is received (fo r contr ol endpoints) or wh en the STALL Req uest
Clear (STALLRQC) bit is written to one.
Each time a STALL handshake is sent, the STALLEDI bit is set by the USBB and the EPnINT
interrupt is set.
643
32072H–AVR32–10/2012
AT32UC3A3
•Special considerations for control endpoints
If a SETUP packet is received into a control endpoint for which a STALL is requested, the
Received SETUP Interrupt (RXSTPI) bit in UESTAn is set and STALLRQ and STALLEDI are
cleared. The SETUP has to be ACKed.
This management simplifies the enumeration process management. If a command is not sup-
ported or contains an error, the user requests a STALL and can return to the main task, waiting
for the next SETUP reques t.
•STALL handshake and r etry mechanism
The retry mechanism has priority over the STALL handshake. A STALL handshake is sent if the
STALLRQ bit is set and if th ere is no retry required.
27.7.2.11 Management of control endpoints
•Overview
A SETUP request is always ACKed. When a new SETUP packet is received, the RXSTPI is set,
but not the Received OUT Data Interrupt (RXOUTI) bit.
The FIFO Control (FIFOCON) bit in UECONn and the Read/Write Allowed (RWALL) bit in
UESTAn are irrelevant for control endpoints. The user shall therefore never use them on these
endpoints. When read, their value are always zero.
Control endpoint s are managed using:
• The RXSTPI bit which is set when a new SETUP packet is received and which shall be
cleared by firmware to acknowledge the packet and to free the bank.
• The RXOUTI bit which is set when a ne w OUT packet is received and which shall be cleared
by firmware to acknowledge the packet and to free the bank.
• The Transmitted IN Data Interrupt (TXINI) bit which is set when the current bank is ready to
accept a ne w IN packet and which shall be cleared by firmware to send the packet.
•Control write
Figure 27-14 on pa ge 644 shows a control wr ite transact ion. During the st atus stage, the con trol-
ler will not necessarily send a NAK on the first IN token:
• If the user knows the exact number of descriptor bytes that must be read, it can then
anticipate the status stage and send a zero-length packet after th e next IN tok en.
• Or it can read the bytes and wait for the NAKed IN Interrupt (NAKINI) which tells that all the
byt es have been sent by the host and that the transaction is now in the status stage.
644
32072H–AVR32–10/2012
AT32UC3A3
Figure 27-14. Control Write
•Control read
Figure 27-15 on page 644 shows a control read transactio n. The USBB has to manage the
simultaneous write requests from the CPU and the USB host.
Figure 27-15. Control Read
A NAK handshake is always generated on the first status stage command.
When the controller detects the status stage, all the data written by the CPU are lost and clear-
ing TXINI has no effect.
The user checks if the transmission or the reception is complete.
The OUT retry is always ACKed. This reception sets RXOUTI and TXINI. Handle this with the
following software algorithm:
set TXINI
wait for RXOUTI OR TXINI
if RXOUTI, then clear bit and return
if TXINI, then continue
Once the OUT status stage has been received, the USBB waits for a SETUP request. The
SETUP request has priority over any other request and has to be ACKed. This means that any
other bit should be cleared and the FIFO reset when a SETUP is received.
The user has to take care of the fact that the byte counter is reset when a zero-length OUT
packet is received.
SETUP
RXSTPI
RXOUTI
TXINI
USB Bus
HW SW
OUT
HW SW
OUT
HW SW
IN IN
NAK
SW
DATASETUP STATUS
SETUP
RXSTPI
RXOUTI
TXINI
USB Bus
HW SW
IN
HW SW
IN OUT OUT
NAK
SW
SW
HW
Wr Enable
HOST
Wr Enable
CPU
DATASETUP STATUS
645
32072H–AVR32–10/2012
AT32UC3A3
27.7.2.12 Management of IN endpoints
•Overview
IN packets are sent by the USB device controller upon IN requests from the host. All the data
can be written wh ich acknowledges or not the bank when it is full.
The endpoint must be configured first.
The TXINI bit is set at the same time as FIFOCON when the current bank is free. This triggers
an EPnINT interrupt if the Transmitted IN Data Interrupt Enable (TXINE) bit in UECONn is one.
TXINI shall be cleared by software (by writing a one to the Transmitted IN Data Interrupt Enable
Clear bit in the Endpoint n Co ntrol Clear register (UECONnCLR.TXINIC)) to acknowledge the
interrupt, what has no effect on the endpoint FIFO.
The user then writes into the FIFO (see ”USB Pipe/Endpoint n FIFO Data Register (USBFIFOn-
DATA)” on page 747) and write a one to the FIFO Control Clear (FIFOCONC) bit in
UECONnCLR to clear the FIFOCON bit. This allows the USBB to send the data . If the IN end-
point is composed of multiple banks, this also switches to the next bank. The TXINI and
FIFOCON bits are updated in accordance with the status of the next bank.
TXINI shall always be clea red before clearing FIFOCON.
The RWALL bit is set when the current bank is not full, i.e. the software can write further data
into the FIFO.
Figure 27-16. Example of an IN Endpoint with 1 Data Bank
IN DATA
(bank 0) ACK
TXINI
FIFOCON
HW
write dat a to CPU
BANK 0 SW
SW SW
SW
IN
NAK
write data to CPU
BANK 0
646
32072H–AVR32–10/2012
AT32UC3A3
Figure 27-17. Example of an IN Endpoint with 2 Data Banks
•Detailed description
The data is written, following the next flow:
• When the bank is empty, TXINI and FIFOCON are set, what triggers an EPnINT interrupt if
TXINE is one.
• The user acknowledges the int errupt by clearing TXINI.
• The user writes the data into the current bank by using the USB Pipe/Endpoint nFIFO Data
virtual segment (see ”USB Pipe/Endpoint n FIFO Data Regist er (USBFI FOnDAT A)” on page
747), until all the data frame is written or the bank is full (in which case RW ALL is cleared and
the Byte Count (BYCT) field in UESTAn reaches the endpoint size).
• The user allows the controller to send the bank and switches to the next bank (if any) by
clearing FIFOCON.
If the endpoint uses several banks, the current one can be written while the previous one is
being read by the host. Then, when the user clears FIFOCON, the following ban k may already
be free and TXINI is set immediately.
An “Abort” stage can be produced when a zero-length OUT packet is received during an IN
stage of a control or isochronous IN transaction. The Kill IN Bank (KILLBK) bit in UECONn is
used to kill the last written bank. The best way to manage this abort is to apply the algorithm rep-
resented on Figure 27-18 on page 647. See ”Endpoint n Control Register” on page 706 to have
more details abou t th e KILL BK bit .
IN DATA
(bank 0) ACK
TXINI
FIFOCON write data to CPU
BANK 0 SW
SW SW
SW
IN DATA
(bank 1) ACK
write data to CPU
BANK 1
SW
HW
write dat a t o CPU
BANK0
647
32072H–AVR32–10/2012
AT32UC3A3
Figure 27-18. Abort Algorithm
27.7.2.13 Management of OUT endpoints
•Overview
OUT packets are sent by the host. All the data can be read which acknowled ges or no t the ba nk
when it is empty.
The endpoint must be configured first.
The RXOUTI bit is set at the same time as FIFOCON when the current bank is full. This triggers
an EPnINT interrupt if the Received OUT Data Interrupt Enable (RXOUTE) bit in UECONn is
one.
RXOUTI shall be cleared by soft ware (by writing a one to the Received OUT Data Interrupt Clear
(RXOUTIC) bit) to acknowledge the interru pt, what has no effect on the endpoin t FIFO.
The user th en re ads fr om th e F IF O (se e ”USB Pipe /En dpoint n FI FO Da ta Reg ist er ( USBF IFOn-
DATA)” on page 747) and clears the FIFOCON bit to free the bank. If the OUT endpoint is
composed of multiple banks, this also switches to the next bank. The RXOUTI and FIFOCON
bits are updated in accordance with the status of the next bank.
RXOUTI shall always be cleared before clearing FIFOCON.
The RWALL bit is set when the current ban k is not empt y, i.e . the so f tware ca n re ad furt h er da ta
from the FIFO.
Endpoint
Abort
Abort Done
Abort is based on the fact
that no bank is busy, i.e.,
that nothing has to be sent
Disable the TXINI interrupt.
EPRSTn = 1
NBUSYBK
== 0?
Yes
TXINEC = 1
No
KILLBKS = 1
KILLBK
== 1?
Yes
Kill the last written bank.
Wait for the end of the
procedure
No
648
32072H–AVR32–10/2012
AT32UC3A3
Figure 27-19. Example of an OUT Endpoint with one Data Bank
Figure 27-20. Example of an OUT Endpoint with two Data Banks
•Detailed description
The data is read, following the next flow:
• When the bank is full, RXOUTI and FIFOCON are set, what triggers an EPnINT in terrupt if
RXOUTE is one.
• The user acknowledges the interrupt by writing a one to RXOUTIC in order to clear RXOUTI.
• The user can read the byte count of the cur re nt bank f ro m BYCT to know how many byte s to
read, rather than polling RWALL.
• The user reads the data from the curren t bank by using the USBFIFOnDATA register (see
”USB Pipe/Endpoint n FIFO Data Register (USBFIFOnDATA)” on page 747), until all the
e xpected data fr ame is read or t he bank is empty (in which case R W ALL is cleared and BYCT
reaches zero).
• The user frees the bank and switches to the next bank (if any) by clearing FIFOCON.
If the endpoint uses several banks, the current one can be read while the following one is being
written by the host. Then, when the user clears FIFOCON, the following bank may already be
ready and RXOUTI is set imm ediately.
In Hi-Speed mode, the PING and NYET protocol is handled by the USBB. For single bank, a
NYET handshake is always sent to the host (on Bulk-out transaction) to indicate that the current
packet is acknowledged but there is no room for the next one. For double bank, the USBB
OUT DATA
(bank 0) ACK
RXOUTI
FIFOCON
HW
OUT DATA
(bank 0) ACK
HW
SW
SW
SW
read data from CPU
BANK 0 read data from CPU
BANK 0
NAK
OUT DATA
(bank 0) ACK
RXOUTI
FIFOCON
HW
OUT DATA
(bank 1) ACK
SW
SW
read data from CPU
BANK 0
HW
SW
read data from CPU
BANK 1
649
32072H–AVR32–10/2012
AT32UC3A3
responds to the OUT/DATA transaction with an ACK handshake when the en dpoint accepted
the data successf ully and has room for another data payload (the second bank is free).
27.7.2.14 Underflow This error exists only for isochronous IN/OUT endpoints. It set the Underflow Interrupt
(UNDERFI) bit in UESTAn, what triggers an EPnINT interrupt if the Underflow Interrupt Enable
(UNDERFE) bit is one.
An underflow can occur during I N stage if the host at tempts to read from an empt y bank. A zero-
length packet is then automatically sent by the USBB.
An underflow can not occur during OUT stage on a CPU action, since the user may read only if
the bank is not empty (RXOUTI is one or RWALL is one).
An underflow can also occur during OUT stage if the host sends a packet while the bank is
already full. Typically, the CPU is not fast enough. The packet is lost.
An underflow can not occu r during IN stage on a CPU action, since the user ma y wr ite only if t he
bank is not full (TXINI is one or RWALL is one).
27.7.2.15 Overflow This error exists for all endpoint types. It set the Overflow interrupt (OVERFI) bit in UESTAn,
what triggers an EPnINT interrupt if the Overflow Interrupt Enable (OVERFE) bit is one.
An overflow can occur during OUT sta ge if t he host attem pts to wr ite into a ban k that is too smal l
for the packet. The packet is acknowledged and the RXOUTI bit is set as if no overflow had
occurred. The bank is filled with all the first bytes of the packet that fit in.
An overflow can not occur during IN stage on a CPU action, since the user may write only if the
bank is not full (TXINI is one or RWALL is one).
27.7.2.16 HB IsoIn error
This error exists only f or high-bandwidth isochr onous IN endpoints if t he high-bandwidth isochr o-
nous feature is supported by the device (see the UFEATURES register for this).
At the end of the micro- fr ame, if at lea st on e packe t h as been sent to t he host , if less ban ks than
expected has been validated (by clearing the FIFOCON) for this micro-frame, it set the
HBISOINERRORI bit in UESTAn, what triggers an EPnINT interrupt if the High Band width Iso-
chronous IN Error Inter rupt Enable (HBISOINERRORE) bit is one.
For instance, if the Number of Transaction per MicroFrame for Isochronous Endpoint
(NBTRANS field in UECFGn is three (three transactions per micro-frame), only two banks are
filled by the CPU (three expected) for the current micro-frame. Then, the HBISOINERRI interrupt
is generated at the end of the micro-frame. Note that an UNDERFI interrupt is also generated
(with an automatic zero-length-packet), except in the case of a missing IN token.
27.7.2.17 HB IsoFlush This err or exists only for high -bandwidth isochrono us IN endpoints if the hig h-bandwidth isochro-
nous feature is supported by the device (see the UFEATURES register for this).
At the end of the micr o- frame , if at lea st on e pa cket ha s been sent t o the ho st, if th ere is mi ssing
IN token during this micro-frame, th e bank(s) destine d to this micro-fra me is/are flushed out to
ensure a good data synchronization between the host and the device.
650
32072H–AVR32–10/2012
AT32UC3A3
For instance, if NB TRANS is three (t hree tra nsactions p er micro- frame), if on ly the first IN toke n
(among 3) is well received by the USBB, then the two last banks will be discarded.
27.7.2.18 CRC error This error exists only for isochronous OUT endpoints. It set the CRC Erro r Inte rrupt (CRCERRI )
bit in UESTAn, what triggers an EPnINT interrupt if the CRC Error Interrupt Enable (CRCERRE)
bit is one.
A CRC error can occur during OUT stage if the USBB detects a corrupted received packet. The
OUT packet is stored in the bank as if no CRC error had occurred (RXOUTI is set).
27.7.2.19 Interrupts See the str uct ur e of the USB devic e inte rr u pt sys te m on Figure 27-6 on page 632.
There are two kinds of device interrupts: processing, i.e. their generation is part of the normal
processing, and exception, i.e. errors (not related to CPU exceptions).
•Global interrupts
The processing device gl obal interrupts are:
• The Suspend (SUSP) interrupt
• The Start of Frame (SOF) interrupt with no frame number CRC error (the Frame Number
CRC Error (FNCERR) bit in the Device Frame Number (UDFNUM) register is zero)
• The Micro Start of Frame (MSOF) interrupt with no CRC error.
• The End of Reset (EORST) interrupt
• The Wake-Up (WAKEUP) interrupt
• The End of Resume (EORSM) interrupt
• The Upstream Resume (UPRSM) interrupt
• The Endpoint n (EPnINT) interrupt
• The DMA Channel n (DMAnINT) interrupt
The exception device global interrupts are:
• The Start of Frame (SOF) interrupt with a frame number CRC error (FNCERR is one)
• The Micro Start of Frame (MSOF) interrupt with a CRC error
•Endpoint interrupts
The processing device endpoint interrupts are:
• The Transmitted IN Data Interrupt (TXINI)
• The Received OUT Data Interrupt (RXOUTI)
• The Received SETUP Interrupt (RXSTPI)
• The Short Packet (SHORTPACKET) interrupt
• The Number of Busy Banks (NBUSYBK) interrupt
• The Received OUT isochronous Multiple Data Interrupt (MDATAI)
• The Received OUT isochronous DataX Interrupt (DATAXI)
The exception device endpoint interrupts are:
• The Underflow Interrupt (UNDERFI)
651
32072H–AVR32–10/2012
AT32UC3A3
• The NAKed OUT Interrupt (NAKOUTI)
• The High-bandwidth isochronous IN error Interrupt (HBISOINERRI) if the high-bandwidth
isochronous feature is supported by the device (see the UFEATURES register for this)
• The NAKed IN Interrupt (NAKINI )
• The High-bandwidth isochr onous IN Flush error Interrupt (HBISOFLUSHI) if the high-
bandwidth isochrono us feat ure is sup ported by the device ( see the UFEATURES r egist er for
this)
• The Overflow Interrupt (OVERFI)
• The STALLed Interrupt (STALLEDI)
• The CRC Error Interrupt (CRCERRI)
• The Transact ion error ( ERRORTRANS) interrupt if the high- bandwidth isochr onous feature is
supported by the device (see the UFEATURES register for this)
•DMA interrupts
The processing device DMA interrupts are:
• The End of USB Transfer Status (EOTSTA) interrupt
• The End of Channel Buffer Status (EOCHBUFFSTA) interrupt
• The Descriptor Loaded Status (DESCLDSTA) interrupt
There is no exception device DMA interrupt.
27.7.2.20 Test Modes When written to one, the UDCON.TSTPCKT bit switches the USB device controller in a “test
packet”mode:
The transceiver repeatedly transmit the packet stored in the current bank. TSTPCKT must be
written to zero to exit the “test-packet” mode. The endpoint shall be reset by software after a
“test-packet” mode.
This enables the testing of rise and falling times, eye patterns, jitter, and any other dynamic
waveform specifications.
The flow control used to send the packets is as follows:
• TSTPCKT=1;
• Store data in an endpoint bank
• Write a zero to FifoCON bit
To stop the test-packet mode, just write a zero to the TSTPCKT bit.
652
32072H–AVR32–10/2012
AT32UC3A3
27.7.3 USB Host Operation
27.7.3.1 Description of pipes
For the USBB in host mode, the term “pipe” is used instead of “endpoint” (used in device mode).
A host pipe corresponds to a device endpoint, as described by the Figure 27-2 1 on page 652
from the USB specification.
Figure 27-21. USB Communication Flow
In host mode, the USBB associates a pipe to a device endpoint, considering the device configu-
ration descriptors.
27.7.3.2 Power-On and rese t
Figure 27-22 on page 652 describes the USBB host mode main states.
Figure 27-22. Host Mode States
After a hardware reset, the USBB host mode is in the Reset state.
When the USBB is enabled (USBE is one) in host mode (ID is zero), its host mode state goes to
the Idle state. In this state, the controller waits for device connection with minimal power con-
Ready
Idle
Device
Disconnection
<any
other
state>
Device
Connection
Macro off
Clock stopped
Device
Disconnection
Suspend
SOFE = 1
SOFE = 0
653
32072H–AVR32–10/2012
AT32UC3A3
sumption. The USB pad should be in the Idle state. Once a device is connected, the macro
enters the Ready state, what does not require the USB clock to be activated.
The controller enters the Suspend state when the USB bus is in a “Suspend” state, i.e., when
the host m ode do es not ge nerat e the “Star t of Fr ame ( SOF)”. In th is st ate, t he USB con sumption
is minimal. The host mode exits the Suspend state when starting to generate the SOF over the
USB line.
27.7.3.3 Device detection
A device is detected by the USBB host mode when D+ or D- is no longer tied low, i.e., when the
device D+ or D- pull-up resistor is connected. To enable this detection, the host controller has to
provide the VBus power supply to the device by setting the VBUSRQ bit (by writing a one to the
VBUSRQS bit).
The device disconnect ion is detected by the host controller when both D+ and D- are pulled
down.
27.7.3.4 USB rese t The USBB sends a USB bus reset when the user write a one to the Send USB Reset bit in the
Host General Control register (UHCON.RESET). The USB Reset Sent Interrupt bit in the Host
Global Interrupt register (UHINT.RSTI ) is set when the USB reset has been sent . In t his case, all
the pipes are disabl ed and de-allocated.
If the bus was pr eviously in a “S uspend” sta te (t he Start of Fra me Gen erat ion En ab le (SOFE) bit
in UHCON is zero), the USBB automatically switches it to the “Resume” state, the Host Wake-
Up Interrupt (HWUPI) bit in UHINT is set and the SOFE bit is set in order to generate SOFs or
micro SOFs immediately af ter the USB reset.
At the end of the reset, the user should check the USBSTA.SPEED field to know the speed run-
ning according to the peripheral capability (LS.FS/HS)
27.7.3.5 Pip e rese t A pipe can b e reset at any tim e by writing a one to the Pipe n Reset ( PRSTn) bit in the UPRST
register. This is recommend ed before using a pipe upon har dware reset or when a USB bus
reset has been sen t. Th is re se ts:
• The internal state machine of this pipe
• The receive and transmit bank FIFO counters
• All the registers of this pipe ( UPCFGn, UPSTAn, UPCONn), e xcept its configuration (ALLOC ,
PBK, PSIZE, PTOKEN, PTYPE, PEPNUM, INTFRQ in UPCFGn) and its Data Toggle
Sequence field in the Pipe n Status register (UPSTAn.DTSEQ).
The pipe configuration remains active and the pipe is still enabled.
The pipe reset may be associated with a clear of the data toggle sequence. This can be
achieved by setting the Reset Data Toggle bit in the Pipe n Control register (UPCONn.RSTDT)
(by writing a one to the Reset Data Toggle Set bit in the Pipe n Control Set register
(UPCONnSET.RSTDTS)).
In the end, the user has to write a zero to the PRSTn bit to complete the reset operation and to
start using the FI FO.
654
32072H–AVR32–10/2012
AT32UC3A3
27.7.3.6 Pip e act ivation
The pipe is maintained inactive and reset (see Section 27.7.3.5 for more details) as long as it is
disabled (PENn is zero). The Data Toggle Sequence field (DTSEQ) is also reset.
The algorithm represented on Figure 27 -23 on page 654 must be followed in order to activate a
pipe.
Figure 27-23. Pipe Activation Algorithm
As long as the pipe is not correctly configured (UPSTAn.CFGOK is zero), the controller can not
send packets to the device through this pipe.
The UPSTAn.CFGOK bit is set only if the configured size and number of banks are correct com-
pared to their maximal allowed values for the pipe (see Table 27-1 on page 624) and to the
maximal FIFO size (i.e. the DPRAM size).
See Section 27.7 .1 .6 for more details about DPRAM manag ement.
Once the pipe is co rrectl y conf igured (UPSTAn.CFGOK is zero), only the PTOKEN and INTFRQ
fields can be written by software. INTFRQ is meaningless for non-interrupt pipes.
When starting an enumeration, the user gets the device descriptor by sending a
GET_DESCRIPTOR USB request. This descriptor contains the maximal packet size of the
device default control endpoint (bMaxPacketSize0) and the user re-configures the size of the
default control pipe with this size parameter.
27.7.3.7 Address setup
Once the device has answered the first host req uests with t he defaul t device addr ess 0, the host
assigns a new addr ess to the d evice. The host contr oller has t o se nd an USB rese t to the device
and to send a SET_ADDRESS(addr) SETUP request with the new address to be used by the
device. Once th is SETUP transa ctio n is ove r, the user write s the n ew address into the USB Host
Address for Pipe n field in the USB Host Device Address register (UHADDR.UHADDRPn). All
following requests, on all pipes, will be performed using this new address.
Pipe
Activation
CFGOK ==
1?
ERROR
Yes
Pipe Activated
Enable the pipe.
PENn = 1
Test if the pipe configuration is
correct.
UPCFGn
INTFRQ
PEPNUM
PTYPE
PTOKEN
PSIZE
PBK
ALLOC
Configure the pipe:
- interrupt request frequency
- endpoint number
- type
- size
- number of banks
Allocate the configured DPRAM banks.
No
655
32072H–AVR32–10/2012
AT32UC3A3
When the host contro ller sends an USB reset, the UHADDRPn field is reset b y hardware and the
following host requests will be performed using the default device address 0.
27.7.3.8 Remote wake-up
The controller hos t mode enters the Suspend st ate when the UHCON.SOFE bit is wr itten to
zero. No more “Start of Frame” is sent on the USB bus and the USB device enters the Suspend
state 3ms later.
The device awakes the host by sending an Upstream Resume (Remote Wake-Up feature).
When the host controller detects a non-idle sta te on th e USB bus, it se t the Host Wake- Up inte r-
rupt (HWUPI) bit in UHINT. If the non-idle bus state corresponds to an Upstream Resume (K
state), the U pstre am Re sume Re ceive d Inter rupt (RXRSMI) bit in UHINT is set. The user has to
generate a Downstream Resume within 1ms and for at least 20ms by writing a one to the Send
USB Resume (RESUME) bit in UHCON. It is mandatory to write a one to UHCON.SOFE before
writing a one to UHCON.RESUME to enter the Ready state, else UHCON.RESUME will have no
effect.
27.7.3.9 Management of control pipes
A control transaction is composed of three stages:
• SETUP
• Data (IN or OUT)
• Status (OUT or IN)
The user has to change the pipe token according to each stage.
For the control pipe, and only for it, each token is assigned a specific initial data toggle
sequence:
• SETUP: Data0
• IN: Data1
• OUT: Data1
27.7.3.10 Management of IN pipes
IN packets are sent by the USB device controller upon IN requests from the host. All the data
can be read which acknowledges or not the bank when it is empty.
The pipe must be configured first.
When the host requires data from the device, the user has to select beforehand the IN request
mode with the IN Request Mode bit in the Pipe n IN Request register (UPINRQn.INMODE):
• When INMODE is written to zero, the USBB will perform (INRQ + 1) IN requests before
freezing the pipe.
• When INMODE is written to one, the USBB will perf orm IN requests endlessly when the pipe
is not frozen by the user.
The generation of IN requests starts when the pipe is unfrozen (the Pipe Freeze (PFREEZE)
field in UPCONn is zero).
The Received IN Data In te rr u pt (R XINI ) bit in UPSTAn is set at the sam e time as the FIFO Con -
trol (FIF OCON) bit in UPCONn when the curr ent bank is full. This triggers a PnINT interrupt if the
Received IN Data Interrupt Enable (RXINE) bit in UPCONn is one.
656
32072H–AVR32–10/2012
AT32UC3A3
RXINI shall be cleared by software (by writing a one to the Received IN Data Interrupt Clear bit
in the Pipe n Control Clear register(UPCONnCLR.RXINIC)) to acknowledge the interrupt, what
has no effe ct on the pipe FIFO.
The user th en re ads fr om th e F IF O (se e ”USB Pipe /En dpoint n FI FO Da ta Reg ist er ( USBF IFOn-
DATA)” on page 747) and clears the FIFOCON bit (by writing a one to the FIFO Control Clear
(FIFOCONC) bit in UPCONnCLR) to free the bank. If the IN p ipe is co mpose d of mu lt iple ban ks,
this also switches to the next bank. Th e RXINI and FIFOCON bits are updated in accordance
with the status of the next bank.
RXINI shall always be cleared before clearing FIFOCON.
The Read/Write Allowed (RWALL) bit in UPSTAn is set when the current bank is not empty, i.e.,
the software can read further data from the FIFO.
Figure 27-24. Example of an IN Pipe with 1 Data Bank
Figure 27-25. Example of an IN Pipe with 2 Data Banks
27.7.3.11 Management of OUT pipes
OUT packets are sent by the host. All the da ta can be written which acknowledges or not the
bank when it is full.
The pipe must be configured and unfrozen first.
IN DATA
(bank 0) ACK
RXINI
FIFOCON
HW
IN DATA
(bank 0) ACK
HW
SW
SW
SW
read data from CPU
BANK 0
read data from CPU
BANK 0
IN DATA
(bank 0) ACK
RXINI
FIFOCON
HW
IN DATA
(bank 1) ACK
SW
SW
read data from CPU
BANK 0
HW
SW
read data from CPU
BANK 1
657
32072H–AVR32–10/2012
AT32UC3A3
The Transmitted OUT Data Interrupt (TXOUTI) bit in UPSTAn is set at the same time as FIFO-
CON when the current bank is free. This triggers a PnINT interrupt if the Transmitted OUT Data
Interrupt Enab le (TXOUTE) bit in UPCONn is one.
TXOUTI shall be cleared by software (by writing a one to the Transmitted OUT Data Interrupt
Clear (TXOUTIC) bit in UPCONnCLR) to acknowle dge the interrupt, what has no effect on the
pipe FIFO.
The user then writes into the FIFO (see ”USB Pipe/Endpoint n FIFO Data Register (USBFIFOn-
DATA)” on page 747) and clears the FIFOCON bit to allow the USBB to send the data. If the
OUT pipe is composed of multiple banks, this also switches to the next bank. The TXOUTI and
FIFOCON bits are updated in accordance with the status of the next bank.
TXOUTI shall always be cleared before clearing FIFOCON.
The UPSTAn.RWALL bit is set when the current bank is not full, i.e., the software can write fur-
ther data into the FIFO.
Note that if the user decides to switch to the Suspend state (by writing a zero to the
UHCON.SOFE bit) while a bank is ready to be sent, the USBB automatically exits this state and
the bank is sent.
Note that in High-Speed operating mode, the host controller automatically manages the PING
protocol to maximize the USB bandwidth. The user can tune the PING protocol by handling the
Ping Enable (PINGEN) bit and the bInterval Parameter for the Bulk-Out/Ping Transaction
(BINTERVALL) field in UPCFGn. See the Section 27.8.3.12 for more details.
Figure 27-26. Example of an OUT Pipe with one Data Bank
OUT DATA
(bank 0) ACK
TXOUTI
FIFOCON
HW
write dat a to CPU
BANK 0 SW
SW SW
SW
OUT
write dat a to CPU
BANK 0
658
32072H–AVR32–10/2012
AT32UC3A3
Figure 27-27. Example of an OUT Pipe with two Data Banks and no Bank Switching Delay
Figure 27-28. Example of an OUT Pipe with two Data Banks and a Bank Switching Delay
27.7.3.12 CRC error This error exists only for isochronous IN pipes. It set the CRC Error Interrup t (CRCERRI) bit,
what triggers a PnINT interrupt if then the CRC Error Interrupt Enable (CRCERRE) bit in
UPCONn is one.
A CRC error can occur during IN stage if the USBB detects a corrupted received packet. The IN
packet is stored in the bank as if no CRC error had occurred (RXINI is set).
27.7.3.13 Interrupts See the structure of the USB host interrupt system on Figure 27-6 on page 632.
There are two kinds of host interrupts: processing, i.e. their generation is part of the normal pro-
cessing, and exception, i.e. errors (not related to CPU exceptions).
•Global interrupts
The processing host global interrupts are:
• The Device Connection Interrupt (DCON N I)
• The Device Disconnection Interrupt (DDISCI)
OUT DATA
(bank 0) ACK
TXOUTI
FIFOCON write data to CPU
BANK 0 SW
SW SW
SW
write data to CPU
BANK 1
SW
HW
write data to CPU
BANK0
OUT DATA
(bank 1) ACK
OUT DATA
(bank 0) ACK
TXOUTI
FIFOCON write data to CPU
BANK 0 SW
SW SW
SW
OUT DATA
(bank 1) ACK
write data to CPU
BANK 1
SW
HW
write data to CPU
BANK0
659
32072H–AVR32–10/2012
AT32UC3A3
• The USB Reset Sent Inter rupt (RSTI )
• The Downstream Resume Sent Interrupt (RSMEDI)
• The Upstream Res um e Rece ived Interr up t (RX R SM I)
• The Host Start of Frame Interrupt (HSOFI)
• The Host Wake-Up Interrupt (HWUPI)
• The Pipe n Interrupt (PnINT)
• The DMA Channel n Interrupt (DMAnINT)
There is no exception host global interrup t.
•Pipe interrupts
The processing host pipe interrupts are:
• The Received IN Data Interru pt (R XINI )
• The Transmitted OUT Data Interrupt (TXOUTI)
• The Transmitted SETUP Interrupt (TXSTPI)
• The Short Packet Interrupt (SHORTPACKETI)
• The Number of Busy Banks (NBUSYBK) interrupt
The exception host pipe interrupts are:
• The Underflow Interrupt (UNDERFI)
• The Pipe Error Interrupt (PERRI)
• The NAKed Interrupt (NAKEDI)
• The Overflow Interrupt (OVERFI)
• The Received STALLed Interrupt (RXSTALLDI)
• The CRC Error Interrupt (CRCERRI)
•DMA interrupts
The processing host DMA interrupts are:
• The End of USB Transfer Status (EOTSTA) interrupt
• The End of Channel Buffer Status (EOCHBUFFSTA) interrupt
• The Descriptor Loaded Status (DESCLDSTA) interrupt
There is no exception host DMA interrupt.
660
32072H–AVR32–10/2012
AT32UC3A3
27.7.4 USB DMA Operation
27.7.4.1 Introduction USB packe ts of any length may be transferred when required by the USBB. These transfers
always feature sequential addressing. These two characteristics mean that in case of high
USBB throughput, both HSB ports will benefit from “incrementing burst of unspecified length”
since the average access latency of HSB slaves can then be reduced.
The DMA uses word “incrementing burst of unspecified length” of up to 256 beats for both data
transfers and channel d escri ptor lo ading. A burst may la st o n the HSB busses f or the d urat ion of
a whole USB packe t tr ansfer , unless other wise br oken by the HSB arb itrat ion or t he HSB 1kbyte
boundary crossing.
Packet data HSB bursts may be locked on a DMA buff er ba sis for drastic o vera ll HSB bus ban d-
width performance boost with paged memories. This is because these memories row (or bank)
changes, which are very clock-cycle consuming, will then likely not occur or occur once instead
of dozens of times during a single big USB packet DMA transfer in case other HSB masters
address the memory. This me ans up to 128 words single cycle unbroken HSB bursts for bulk
pipes/endpoints and 256 words single cycle unbroken bursts for isochronous pipes/endpoints.
This maximal burst length is then controlled by the lowest programmed USB pipe/endpoint size
(PSIZE/EPSIZE) and the Channel Byte Length (CHBYTELENGTH) field in the Device DMA
Channel n Control (UDDMAnCONTROL) register.
The USBB average throughput may be up to nearly 53 Mbyte/s. Its average access latency
decreases as burst length increases due to the zero wait-state side effect of unchanged
pipe/endpoint. Word access allows reducing the HSB ban dwidth required for the USB by four
compared to native byte access. If at least 0 wait-state word burst capability is also provided by
the other DMA HSB bus slaves, each of both DMA HSB busses need less than 60% bandwidth
allocation for full USB bandwidth usage at 33MHz, and less than 30% at 66MHz.
661
32072H–AVR32–10/2012
AT32UC3A3
Figure 27-29. Example of DMA Chained List
27.7.4.2 DMA Channel descriptor
The DMA channel tran sfer descriptor is loaded from the memory.
Be careful with the alignment of this buffer.
The structure of the DMA channel transfer descriptor is defined by three parameters as
described below:
• Offset 0:
– The address must be aligned: 0xXXXX0
– DMA Channel n Next Descriptor Address Register: DMAnNXTDESCADDR
• Offset 4:
– The address must be aligned: 0xXXXX4
– DMA Channel n HSB Address Register: DMAnADDR
• Offset 8:
– The address must be aligned: 0xXXXX8
– DMA Channel n Control Register: DMAnCONTROL
27.7.4.3 Pr ogramming a cha n el:
Each DMA transfer is unidirectionnal. Direction depends on the type of the associated endpoint
(IN or OUT).
Three registers, the UDDMAnNEXTDESC, the UDDMAnADDR and UDDMAnCONTROL need
to be programmed to set up wether single or multiple transfer is used.
The following example refers to OUT endpoint. For IN endpoint, the programming is symmetric.
Data Buffer 1
Data Buffer 2
Data Buffer 3
Memory Area
Transfer Descriptor
Next Descriptor Address
HSB Address
Control
Transfer Descriptor
Transfer Descriptor
USB DMA Channel X Registers
(Current Transf er Descriptor)
Next Descriptor Address
HSB Address
Control
NULL
Status
Next Descriptor Address
HSB Address
Control Next Descriptor Address
HSB Address
Control
662
32072H–AVR32–10/2012
AT32UC3A3
•Single-block transfer programming example for OUT transfer :
The following sequence may be used:
• Configure the targerted endpoint (source) as OUT type, a nd set the automa tic bank s witching
for this endpoint in the UECFGn register to handle multiple OUT packet.
• Write the starting destination address in the UDDMAnADDR register.
• There is no need to program the UDDMAnNEXTDESC register.
• Program the channel byte length in the UDDMAnCONTROL register.
• Program the UDDMAnCONTROL according to Row 2 as shown in Figure 27-6 on page 714
to set up a single block transfer.
The UDDMAnSTATUS.CHEN bit is set indicating that the dma channel is enable.
As soon as an OUT packet is stored inside the endpoint, the UDDMAnSTATUS.CHACTIVE bit
is set to one, indicating that the DMA channel is transfering data from the endpoint to the desti-
nation address until the endpoint is empty or the channel byte length is reached. Once the
endpoint is empty, the UDDMAnSTATUS.CHACTIVE bit is cleared.
Once the DMA channel is completed (i.e : the channel byte length is reached), after one or mul-
tiple processed OUT packet, the UDDMAnCONTROL.CHEN bit is cleared. As a consequence,
the UDDMAnSTATUS.CHEN bit is also cleared, and the UDDMAnSTATUS.EOCHBUFFSTA bit
is set indicating a end of dma channel. If the UDDMAnCONTROL.DMAENDEN bit was set, the
last endpoint bank will be properly released even if there are some residual datas inside, i.e:
OUT packet truncation at the end of DMA buffer when the dma channel byte lenght is not an
integral multip le of the end po i nt size.
•Programming example for single-block dma transfer with automatic closure for OUT transfer :
The idea is to automatically close the DMA transfer at the end of the OUT transaction (received
short packet). The following sequence may be used:
• Configure the targerted endpoint (source) as OUT type, a nd set the automa tic bank s witching
for this endpoint in the UECFGn register to handle multiple OUT packet.
• Write the starting destination address in the UDDMAnADDR register.
• There is no need to program the UDDMAnNEXTDESC register.
• Program the channel byte length in the UDDMAnCONTROL register.
• Set the BUFFCLOSEINEN bit in the UDDMAnCONTROL register.
• Program the UDDMAnCONTROL according to Row 2 as shown in Figure 27-6 on page 714
to set up a single block transfer.
As soon as an OUT packet is stored inside the endpoint, the UDDMAnSTATUS.CHACTIVE bit
is set to one, indicating that the DMA channel is transfering data from the endpoint to the desti-
nation address until the endpoint is empty. Once the endpoint is empty, the
UDDMAnSTATUS.CHACTIVE bit is cleared.
After one or multiple processed OUT packet, the DMA channel is completed after sourcing a
short packet. Then, the UDDMAnCONTROL.CHEN bit is cleared. As a consequence, after a few
cycles latency, the UDDMAnSTATUS.CHEN bit is also cleared, and the UDDMAnSTA-
TUS.EOTSTA bit is set indicating that the DMA was closed by a end of USB transaction.
663
32072H–AVR32–10/2012
AT32UC3A3
•Progr amming example for multi-block dma transfer : run and link at end of buf fer
The idea is to run f irst a single block tran sfer followed automatically by a linked list of DMA. The
following sequ ence may be used:
• Configure the targerted endpoint (source) as OUT type, a nd set the automa tic bank s witching
for this endpoint in the UECFGn register to handle multiple OUT packet.
• Set up the chain of linked list of de scripor in memory. Each descriptor is compos ed of 3 items
: channel ne xt descriptor add ress , channel de stinat ion address and ch annel contro l. The last
descriptor should be programmed according to row 2 as shown in Figure 27-6 on page 714.
• Write the starting destination address in the UDDMAnADDR register.
• Program the UDDMAnNEXTDESC register.
• Program the channel byte length in the UDDMAnCONTROL register.
• Optionnaly set the BUFFCLOSEINEN bit in the UDDMAnCONTROL register.
• Program the UDDMAnCONTROL according to Row 4 as shown in Figure 27-6 on page 714.
The UDDMAnSTATUS.CHEN bit is set indicating that the dma channel is enable.
As soon as an OUT packet is stored inside the endpoint, the UDDMAnSTATUS.CHACTIVE bit
is set to one, indicating that the DMA channel is transfering data from the endpoint to the desti-
nation address until the endpoint is empty or the channel byte length is reached. Once the
endpoint is empty, the UDDMAnSTATUS.CHACTIVE bit is cleared.
Once the first DMA channel is completed (i.e : the channel byte length is reached), after one or
multiple proces sed OUT packet, the UDDMAnCONTROL.CHEN bit is cleared. As a c onse-
quence, the UDDMAnSTATUS.CHEN bit is also cleared, and the
UDDMAnSTATUS.EOCHBUFFSTA bit is set indicating a end of dma channel. If the UDDMAn-
CONTROL.DMAENDEN bit was set, the last endpoint bank will be properly released even if
there are some residual datas inside, i.e: OUT packet truncation at the end of DMA buffer when
the dma channel byte lenght is not an integral multiple of the endpoint size. Note that the
UDDMAnCONTROL.LDNXTCH bit remains to one indicating that a linked descriptor will be
loaded.
Once the new descriptor is loaded from the UDDMAnNEXTDESC memory address, the UDDM-
AnSTATUS.DESCLDSTA bit is set, and the UDDMAnCONTROL register is updated from the
memor y. As a consequence, the UDDMAnSTATUS.CHEN bit is set, and the UDDMAnSTA-
TUS.CHACTIVE is set as soon as the endpoint is ready to be sourced by the DMA (received
OUT data packet).
This sequence is repeated until a last linked descriptor is processed. The last descriptor is
detected accord ing to row 2 as shown in Figure 27-6 on page 714.
At the end of the last descriptor, the UDDMAnCONTROL.C HEN bit is cleared. As a conse-
quence, after a few cycles latency, the UDDMAnSTATUS.CHEN bit is also cleared.
•Progr amming example for multi-block dma transfer : load next descriptor now
The idea is to directly run first a linked list of DMA. The following sequence may be used: The
following sequ ence may be used:
• Configure the targerted endpoint (source) as OUT type, a nd set the automa tic bank s witching
for this endpoint in the UECFGn register to handle multiple OUT packet.
664
32072H–AVR32–10/2012
AT32UC3A3
• Set up the chain of linked list of de scripor in memory. Each descriptor is compos ed of 3 items
: channel ne xt descriptor add ress , channel de stinat ion address and ch annel contro l. The last
descriptor should be programmed according to row 2 as shown in Figure 27-6 on page 714.
• Program the UDDMAnNEXTDESC register.
• Program the UDDMAnCONTROL according to Row 3 as shown in Figure 27-6 on page 714.
The UDDMAnSTATUS.CHEN bit is 0 and the UDDMAnSTATUS.LDNXTCHDESCEN is set indi-
cating that the DMA channel is pending until the endpoint is ready (received OUT packet) .
As soon as an OUT packet is stored inside the endpoint, the UDDMAnSTATUS.CHACTIVE bit
is set to one. Then after a few cycle latency, the new descriptor is loaded from the memory and
the UDDMAnSTATUS.DESCLDSTA is set.
At the end of this DMA (for instance when the channel byte length has reached 0), the
UDDMAnCONTROL.CHEN bit is cleared, and then the UDDMAnSTATUS.CH EN bit is also
cleared. If the UDDMAnCONTROL.LDNXTCH value is one, a new descriptor is loaded.
This sequence is repeated until a last linked descriptor is processed. The last descriptor is
detected accord ing to row 2 as shown in Figure 27-6 on page 714.
At the end of the last descriptor, the UDDMAnCONTROL.C HEN bit is cleared. As a conse-
quence, after a few cycles latency, the UDDMAnSTATUS.CHEN bit is also cleared.
665
32072H–AVR32–10/2012
AT32UC3A3
27.8 User Interface
Table 27-4. USBB Register Memory Map
Offset Register Name Access Reset Value
0x0000 Device General Control Register UDCON Read/Write 0x00000100
0x0004 Device Global Interrupt Register UDINT Read-Only 0x00000 000
0x0008 Device Global Interrupt Clear Register UDINTCLR Write-Only 0x00000000
0x000C Device Global Interrupt Set Register UDINTSET Write-Only 0x00000000
0x0010 Device Global Interrupt Enable Register UDINTE Read-Only 0x00000000
0x0014 Device Global Interrupt Enable Clear Register UDINTECLR Write-Only 0x00000000
0x0018 Device Global Interrupt Enable Set Register UDINTESET Write-Only 0x00000 000
0x001C Endpoint Enable/Reset Register UERST Read/Write 0x00000000
0x0020 Device Frame Number Register UDFNUM Read-Only 0x00000 000
0x0100 Endpoint 0 Configuration Register UECFG0 Read/Write 0x00002000
0x0104 Endpoint 1 Configuration Register UECFG1 Read/Write 0x00002000
0x0108 Endpoint 2 Configuration Register UECFG2 Read/Write 0x00002000
0x010C Endpoint 3 Configuration Register UECFG3 Read/Write 0x00002000
0x0110 Endpoint 4 Configuration Register UECFG4 Read/Write 0x00002000
0x0114 Endpoint 5 Configuration Register UECFG5 Read/Write 0x00002000
0x0118 Endpoint 6 Configuration Register UECFG6 Read/Write 0x00002000
0x011C Endpoint 7Configuration Register UECFG7 Read/Write 0x00002000
0x0130 Endpoint 0 Status Register UESTA0 Read-Only 0x00000100
0x0134 Endpoint 1 Status Register UESTA1 Read-Only 0x00000100
0x0138 Endpoint 2 Status Register UESTA2 Read-Only 0x00000100
0x013C Endpoint 3 Status Register UESTA3 Read-Only 0x00000100
0x0140 Endpoint 4 Status Register UESTA4 Read-Only 0x00000100
0x0144 Endpoint 5 Status Register UESTA5 Read-Only 0x00000100
0x0148 Endpoint 6 Status Register UESTA6 Read-Only 0x00000100
0x014C Endpoint 7Status Register UESTA7 Read-Only 0x00000100
0x0160 Endpoint 0 Status Clear Register UESTA0CLR Write-Only 0x00000000
0x0164 Endpoint 1 Status Clear Register UESTA1CLR Write-Only 0x00000000
0x0168 Endpoint 2 Status Clear Register UESTA2CLR Write-Only 0x00000000
0x016C Endpoint 3 Status Clear Register UESTA3CLR Write-Only 0x00000000
0x0170 Endpoint 4 Status Clear Register UESTA4CLR Write-Only 0x00000000
0x0174 Endpoint 5 Status Clear Register UESTA5CLR Write-Only 0x00000000
0x0178 Endpoint 6 Status Clear Register UESTA6CLR Write-Only 0x00000000
0x017C Endpoint 7 Status Clear Register UESTA7CLR Write-Only 0x00000000
0x0190 Endpoint 0 Status Set Register UESTA0SET Write-Only 0x00000000
0x0194 Endpoint 1 Status Set Register UESTA1SET Write-Only 0x00000000
666
32072H–AVR32–10/2012
AT32UC3A3
0x0198 Endpoint 2 Status Set Register UESTA2SET Write-Only 0x00000000
0x019C Endpoint 3 Status Set Register UESTA3SET Write-Only 0x00000000
0x01A0 Endpoint 4 Status Set Register UESTA4SET Write-Only 0x00000000
0x01A4 Endpoint 5 Status Set Register UESTA5SET Write-Only 0x00000000
0x01A8 Endpoint 6 Status Set Register UESTA6SET Write-Only 0x00000000
0x01AC Endpoint 7 Status Set Register UESTA7SET Write-Only 0x00000000
0x01C0 Endpoint 0 Control Register UECON0 Read-Only 0x00000000
0x01C4 Endpoint 1 Control Register UECON1 Read-Only 0x00000000
0x01C8 Endpoint 2 Control Register UECON2 Read-Only 0x00000000
0x01CC Endpoint 3 Control Register UECON3 Read-Only 0x00000000
0x01D0 Endpoint 4 Control Register UECON4 Read-Only 0x00000000
0x01D4 Endpoint 5 Control Register UECON5 Read-Only 0x00000000
0x01D8 Endpoint 6 Control Register UECON6 Read-Only 0x00000000
0x01DC Endpoint 7 Control Register UECON7 Read-Only 0x00000000
0x01F0 Endpoint 0 Control Set Register UECON0SET Write-Only 0x00000000
0x01F4 Endpoint 1 Control Set Register UECON1SET Write-Only 0x00000000
0x01F8 Endpoint 2 Control Set Register UECON2SET Write-Only 0x00000000
0x01FC Endpoint 3 Control Set Register UECON3SET Write-Only 0x00000000
0x0200 Endpoint 4 Control Set Register UECON4SET Write-Only 0x00000000
0x0204 Endpoint 5 Control Set Register UECON5SET Write-Only 0x00000000
0x0208 Endpoint 6 Control Set Register UECON6SET Write-Only 0x00000000
0x020C Endpoint 7 Control Set Register UECON7SET Write-Only 0x00000000
0x0220 Endpoint 0 Control Clear Register UECON0CLR Write-Only 0x00000000
0x0224 Endpoint 1 Control Clear Register UECON1CLR Write-Only 0x00000000
0x0228 Endpoint 2 Control Clear Register UECON2CLR Write-Only 0x00000000
0x022C Endpoint 3 Control Clear Register UECON3CLR Write-Only 0x00000000
0x0230 Endpoint 4 Control Clear Register UECON4CLR Write-Only 0x00000000
0x0234 Endpoint 5 Control Clear Register UECON5CLR Write-Only 0x00000000
0x0238 Endpoint 6 Control Clear Register UECON6CLR Write-Only 0x00000000
0x023C Endpoint 7 Control Clear Register UECON7CLR Write-Only 0x00000000
0x0310 Device DMA Channel 1 Next Descriptor
Address Register UDDMA1
NEXTDESC Read/Write 0x00000000
0x0314 Device DMA Channel 1 HSB Address Register UDDMA1
ADDR Read/Write 0x00000000
0x0318 Device DMA Channel 1 Control Register UDDMA1
CONTROL Read/Write 0x00000000
Table 27-4. USBB Register Memory Map
Offset Register Name Access Reset Value
667
32072H–AVR32–10/2012
AT32UC3A3
0x031C Device DMA Channel 1 Status Register UDDMA1
STATUS Read/Write 0x00000000
0x0320 Device DMA Channel 2 Next Descriptor
Address Register UDDMA2
NEXTDESC Read/Write 0x00000000
0x0324 Device DMA Channel 2 HSB Address Register UDDMA2
ADDR Read/Write 0x00000000
0x0328 Device DMA Channel 2 Control Register UDDMA2
CONTROL Read/Write 0x00000000
0x032C Device DMA Channel 2 Status Register UDDMA2
STATUS Read/Write 0x00000000
0x0330 Device DMA Channel 3 Next Descriptor
Address Register UDDMA3
NEXTDESC Read/Write 0x00000000
0x0334 Device DMA Channel 3 HSB Address Register UDDMA3
ADDR Read/Write 0x00000000
0x0338 Device DMA Channel 3 Control Register UDDMA3
CONTROL Read/Write 0x00000000
0x033C Device DMA Channel 3 Status Register UDDMA3
STATUS Read/Write 0x00000000
0x0340 Device DMA Channel 4 Next Descriptor
Address Register UDDMA4
NEXTDESC Read/Write 0x00000000
0x0344 Device DMA Channel 4 HSB Address Register UDDMA4
ADDR Read/Write 0x00000000
0x0348 Device DMA Channel 4 Control Register UDDMA4
CONTROL Read/Write 0x00000000
0x034C Device DMA Channel 4 Status Register UDDMA4
STATUS Read/Write 0x00000000
0x0350 Device DMA Channel 5 Next Descriptor
Address Register UDDMA5
NEXTDESC Read/Write 0x00000000
0x0354 Device DMA Channel 5 HSB Address Register UDDMA5
ADDR Read/Write 0x00000000
0x0358 Device DMA Channel 5 Control Register UDDMA5
CONTROL Read/Write 0x00000000
0x035C Device DMA Channel 5 Status Register UDDMA5
STATUS Read/Write 0x00000000
0x0360 Device DMA Channel 6 Next Descriptor
Address Register UDDMA6
NEXTDESC Read/Write 0x00000000
0x0364 Device DMA Channel 6 HSB Address Register UDDMA6
ADDR Read/Write 0x00000000
0x0368 Device DMA Channel 6 Control Register UDDMA6
CONTROL Read/Write 0x00000000
0x036C Device DMA Channel 6 Status Register UDDMA6
STATUS Read/Write 0x00000000
0x0370 Device DMA Channel 7 Next Descriptor
Address Register UDDMA7
NEXTDESC Read/Write 0x00000000
Table 27-4. USBB Register Memory Map
Offset Register Name Access Reset Value
668
32072H–AVR32–10/2012
AT32UC3A3
0x0374 Device DMA Channel 7 HSB Address Register UDDMA7
ADDR Read/Write 0x00000000
0x0378 Device DMA Channel 7 Control Register UDDMA7
CONTROL Read/Write 0x00000000
0x037C Device DMA Channel 7Status Register UDDMA7
STATUS Read/Write 0x00000000
0x0400 Host General Control Register UHCON Read/Write 0x00000000
0x0404 Host Global Interrup t Reg ister UHINT Read-Only 0x00000000
0x0408 Host Global Interrupt Clear Register UHINTCLR Write-Only 0x00000000
0x040C Host Global Interrupt Set Register UHINTSET Write-Only 0x00000000
0x0410 Host Global Interrupt Enable Register UHINTE Read-Only 0x00000000
0x0414 Host Global Interrupt Enable Clear Register UHINTECLR Write-Only 0x00000000
0x0418 Host Global Interrupt Enable Set Register UHINTESET Write-Only 0x00000000
0x0041C Pipe Enable/Reset Register UPRST Read/Write 0x00000000
0x0420 Host Frame Number Register UHFNUM Read/Write 0x00000000
0x0424 Host Address 1 Register UHADDR1 Read/Write 0x00000000
0x0428 Host Address 2 Register UHADDR2 Read/Write 0x00000000
0x0500 Pipe 0 Configuration Register UPCFG0 Read/Write 0x00000000
0x0504 Pipe 1 Configuration Register UPCFG1 Read/Write 0x00000000
0x0508 Pipe 2 Configuration Register UPCFG2 Read/Write 0x00000000
0x050C Pipe 3 Configuration Register UPCFG3 Read/Write 0x00000000
0x0510 Pipe 4 Configuration Register UPCFG4 Read/Write 0x00000000
0x0514 Pipe 5 Configuration Register UPCFG5 Read/Write 0x00000000
0x0518 Pipe 6 Configuration Register UPCFG6 Read/Write 0x00000000
0x051C Pipe 7 Configuration Register UPCFG7 Read/Write 0x00000000
0x0530 Pipe 0 Status Register UPSTA0 Read-Only 0x00000000
0x0534 Pipe 1 Status Register UPSTA1 Read-Only 0x00000000
0x0538 Pipe 2 Status Register UPSTA2 Read-Only 0x00000000
0x053C Pipe 3 Status Register UPSTA3 Read-Only 0x00000000
0x0540 Pipe 4 Status Register UPSTA4 Read-Only 0x00000000
0x0544 Pipe 5 Status Register UPSTA5 Read-Only 0x00000000
0x0548 Pipe 6 Status Register UPSTA6 Read-Only 0x00000000
0x054C Pipe 7Status Register UPSTA7 Read-Only 0x00000000
0x0560 Pipe 0 Status Clear Register UPSTA0CLR Write-Only 0x00000000
0x0564 Pipe 1 Status Clear Register UPSTA1CLR Write-Only 0x00000000
0x0568 Pipe 2 Status Clear Register UPSTA2CLR Write-Only 0x00000000
0x056C Pipe 3 Status Clear Register UPSTA3 CLR Write-Only 0x00000000
Table 27-4. USBB Register Memory Map
Offset Register Name Access Reset Value
669
32072H–AVR32–10/2012
AT32UC3A3
0x0570 Pipe 4 Status Clear Register UPSTA4CLR Write-Only 0x00000000
0x0574 Pipe 5 Status Clear Register UPSTA5CLR Write-Only 0x00000000
0x0578 Pipe 6 Status Clear Register UPSTA6CLR Write-Only 0x00000000
0x057C Pipe 7 Status Clear Register UPSTA7 CLR Write-Only 0x00000000
0x0590 Pipe 0 Status Set Register UPSTA0SET Write-Only 0x00000000
0x0594 Pipe 1 Status Set Register UPSTA1SET Write-Only 0x00000000
0x0598 Pipe 2 Status Set Register UPSTA2SET Write-Only 0x00000000
0x059C Pipe 3 Status Set Register UPSTA3SET Write-Only 0x00000000
0x05A0 Pipe 4 Status Set Register UPSTA4SET Write-On ly 0x00000000
0x05A4 Pipe 5 Status Set Register UPSTA5SET Write-On ly 0x00000000
0x05A8 Pipe 6 Status Set Register UPSTA6SET Write-On ly 0x00000000
0x05AC Pipe 7 Status Set Registe r UPSTA7SET Write-Only 0x00000000
0x05C0 Pipe 0 Control Register UPCON0 Read-Only 0x00000000
0x05C4 Pipe 1 Control Register UPCON1 Read-Only 0x00000000
0x05C8 Pipe 2 Control Register UPCON2 Read-Only 0x00000000
0x05CC Pipe 3 Control Register UPCON3 Read-Only 0x00000000
0x05D0 Pipe 4 Control Register UPCON4 Read-Only 0x00000000
0x05D4 Pipe 5 Control Register UPCON5 Read-Only 0x00000000
0x05D8 Pipe 6 Control Register UPCON6 Read-Only 0x00000000
0x05DC Pipe 7 Control Register UPCON7 Read-Only 0x00000000
0x05F0 Pipe 0 Control Set Register UPCON0SET Write-Only 0x00000 000
0x05F4 Pipe 1 Control Set Register UPCON1SET Write-Only 0x00000 000
0x05F8 Pipe 2 Control Set Register UPCON2SET Write-Only 0x00000 000
0x05FC Pipe 3 Control Set Register UPC ON3SET Write-Only 0x00000000
0x0600 Pi pe 4 Control Set Register UPCON4SET Write-Only 0x00000000
0x0604 Pi pe 5 Control Set Register UPCON5SET Write-Only 0x00000000
0x0608 Pi pe 6 Control Set Register UPCON6SET Write-Only 0x00000000
0x060C Pipe 7 Control Set Register UPCON7SET Write-Only 0x00000000
0x0620 Pipe 0 Control Clear Register UPCON0CLR Write-Only 0x00000000
0x0624 Pipe 1 Control Clear Register UPCON1CLR Write-Only 0x00000000
0x0628 Pipe 2 Control Clear Register UPCON2CLR Write-Only 0x00000000
0x062C Pipe 3 Control Clear Register UPCON3CLR Write-Only 0x00000000
0x0630 Pipe 4 Control Clear Register UPCON4CLR Write-Only 0x00000000
0x0634 Pipe 5 Control Clear Register UPCON5CLR Write-Only 0x00000000
0x0638 Pipe 6 Control Clear Register UPCON6CLR Write-Only 0x00000000
0x063C Pipe 7 Control Clear Register UPCON7CLR Write-Only 0x00000000
Table 27-4. USBB Register Memory Map
Offset Register Name Access Reset Value
670
32072H–AVR32–10/2012
AT32UC3A3
0x0650 Pi pe 0 IN Request Register UPINRQ0 Read/Write 0x00000000
0x0654 Pi pe 1 IN Request Register UPINRQ1 Read/Write 0x00000000
0x0658 Pi pe 2 IN Request Register UPINRQ2 Read/Write 0x00000000
0x065C Pipe 3 IN Request Register UPINRQ3 Read/Write 0x00 000000
0x0660 Pi pe 4 IN Request Register UPINRQ4 Read/Write 0x00000000
0x0664 Pi pe 5 IN Request Register UPINRQ5 Read/Write 0x00000000
0x0668 Pi pe 6 IN Request Register UPINRQ6 Read/Write 0x00000000
0x066C Pipe 7 IN Request Register UPINRQ7 Read/Write 0x00 000000
0x0680 Pipe 0 Error Register UPERR0 Read/Write 0x00000000
0x0684 Pipe 1 Error Register UPERR1 Read/Write 0x00000000
0x0688 Pipe 2 Error Register UPERR2 Read/Write 0x00000000
0x068C Pipe 3 Error Register UPERR3 Read/Write 0x00000000
0x0690 Pipe 4 Error Register UPERR4 Read/Write 0x00000000
0x0694 Pipe 5 Error Register UPERR5 Read/Write 0x00000000
0x0698 Pipe 6 Error Register UPERR6 Read/Write 0x00000000
0x069C Pipe 7 Error Register UPERR7 Read/Write 0x00000000
0x0710 Host DMA Channel 1 Next Descriptor Address
Register UHDMA1
NEXTDESC Read/Write 0x00000000
0x0714 Host DMA Channel 1 HSB Address Register UHDMA1
ADDR Read/Write 0x00000000
0x0718 Host DMA Channel 1 Control Register UHDMA1
CONTROL Read/Write 0x00000000
0x071C Host DMA Channel 1 Status Register UHDMA1
STATUS Read/Write 0x00000000
0x0720 Host DMA Channel 2 Next Descriptor Address
Register UHDMA2
NEXTDESC Read/Write 0x00000000
0x0724 Host DMA Channel 2 HSB Address Register UHDMA2
ADDR Read/Write 0x00000000
0x0728 Host DMA Channel 2 Control Register UHDMA2
CONTROL Read/Write 0x00000000
0x072C Host DMA Channel 2 Status Register UHDMA2
STATUS Read/Write 0x00000000
0x0730 Host DMA Channel 3 Next Descriptor Address
Register UHDMA3
NEXTDESC Read/Write 0x00000000
0x0734 Host DMA Channel 3 HSB Address Register UHDMA3
ADDR Read/Write 0x00000000
0x0738 Host DMA Channel 3 Control Register UHDMA3
CONTROL Read/Write 0x00000000
0x073C Host DMA Channel 3Status Register UHDMA3
STATUS Read/Write 0x00000000
Table 27-4. USBB Register Memory Map
Offset Register Name Access Reset Value
671
32072H–AVR32–10/2012
AT32UC3A3
0x0740 Host DMA Channel 4 Next Descriptor Address
Register UHDMA4
NEXTDESC Read/Write 0x00000000
0x0744 Host DMA Channel 4 HSB Address Register UHDMA4
ADDR Read/Write 0x00000000
0x0748 Host DMA Channel 4 Control Register UHDMA4
CONTROL Read/Write 0x00000000
0x074C Host DMA Channel 4 Status Register UHDMA4
STATUS Read/Write 0x00000000
0x0750 Host DMA Channel 5 Next Descriptor Address
Register UHDMA5
NEXTDESC Read/Write 0x00000000
0x0754 Host DMA Channel 5 HSB Address Register UHDMA5
ADDR Read/Write 0x00000000
0x0758 Host DMA Channel 5 Control Register UHDMA5
CONTROL Read/Write 0x00000000
0x075C Host DMA Channel 5 Status Register UHDMA5
STATUS Read/Write 0x00000000
0x0760 Host DMA Channel 6 Next Descriptor Address
Register UHDMA6
NEXTDESC Read/Write 0x00000000
0x0764 Host DMA Channel 6 HSB Address Register UHDMA6
ADDR Read/Write 0x00000000
0x0768 Host DMA Channel 6 Control Register UHDMA6
CONTROL Read/Write 0x00000000
0x076C Host DMA Channel 6 Status Register UHDMA6
STATUS Read/Write 0x00000000
0x0770 Host DMA Channel 7 Next Descriptor Address
Register UHDMA7
NEXTDESC Read/Write 0x00000000
0x0774 Host DMA Channel 7 HSB Address Register UHDMA7
ADDR Read/Write 0x00000000
0x0778 Host DMA Channel 7 Control Register UHDMA7
CONTROL Read/Write 0x00000000
0x077C Host DMA Channel 7 Status Register UHDMA7
STATUS Read/Write 0x00000000
0x0800 General Control Register USBCON Read/Write 0x03004000
0x0804 General Status Register USBSTA Read-Only 0x00000400
0x0808 General Status Clear Register USBSTACLR Write-Only 0x00000000
0x080C General Status Set Register USBSTASET Write-Only 0x00000000
0x0818 IP Version Register UVERS Read-Only -(1)
0x081C IP Features Register UFEATURES Read-Only -(1)
0x0820 IP PB Address Si ze Register UADDRSIZE Read-Only -(1)
0x0824 IP Name Registe r 1 UNAME1 Read-Only -(1)
0x0828 IP Name Registe r 2 UNAME2 Read-Only -(1)
0x082C USB Finite State Machine Status Register USBFSM Read-Only 0x00000009
Table 27-4. USBB Register Memory Map
Offset Register Name Access Reset Value
672
32072H–AVR32–10/2012
AT32UC3A3
Note: 1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter.
Table 27-5. USB HSB Memory Map
Offset Register Name Access Reset Value
0x00000 -
0x0FFFC Pipe/Endpoint 0 FIFO Data Register USB
FIFO0DATA Read/Write Undefined
0x10000 -
0x1FFFC Pipe/Endpoint 1 FIFO Data Register USB
FIFO1DATA Read/Write Undefined
0x20000 -
0x2FFFC Pipe/Endpoint 2 FIFO Data Register USB
FIFO2DATA Read/Write Undefined
0x30000 -
0x3FFFC Pipe/Endpoint 3 FIFO Data Register USB
FIFO3DATA Read/Write Undefined
0x40000 -
0x4FFFC Pipe/Endpoint 4 FIFO Data Register USB
FIFO4DATA Read/Write Undefined
0x50000 -
0x5FFFC Pipe/Endpoint 5 FIFO Data Register USB
FIFO5DATA Read/Write Undefined
0x60000 -
0x6FFFC Pipe/Endpoint 6 FIFO Data Register USB
FIFO6DATA Read/Write Undefined
0x70000 -
0x7FFFC Pipe/Endpoint 7 FIFO Data Register USB
FIFO7DATA Read/Write Undefined
673
32072H–AVR32–10/2012
AT32UC3A3
27.8.1 USB General Registers
27.8.1.1 General Control Register
Name: USBCON
Access Type: Read/Write
Offset: 0x0800
Reset Value: 0x03004000
• UIMOD: USBB Mode
This bit has no effect when UIDE is one (USB_ID input pin activated).
0: The module is in USB host mode.
1: The module is in USB device mode.
This bit can be written even if USBE is zero or FRZCLK is on e . Disabling the USBB (by writing a zero to the USBE bit) does not
reset this bit.
• UIDE: USB_ID Pin Enable
0: The USB mode (device/host) is se lected from the UIMOD bit.
1: The USB mode (device/host) is selected from the USB_ID input pin.
This bit can be written even if USBE is zero or FRZCLK is on e . Disabling the USBB (by writing a zero to the USBE bit) does not
reset this bit.
• UNLOCK: Timer Access Unlock
1: The TIMPAGE and TIMVALUE fields ar e un l o cked.
0: The TIMPA G E and TIMVALUE fields are locked.
The TIMPAGE and TIMVALUE fields can always be read, whatever the value of UNLOCK.
• TIMPAGE: Timer Page
This field contains the page value to access a special timer register.
• TIMVALUE: Timer Value
This field selects the timer value that is written to the special time register selected by TIMPAGE. See Section 27.7.1.8 for
details.
• USBE: USBB Enable
Writing a zero to this bit will reset the USBB, disable the USB transceiver and, disable the USBB clock inputs. Unless explicitly
stated, all registers then will become read-o nly and will be reset.
1: The USBB is enabled.
0: The USBB is disabled.
31 30 29 28 27 26 25 24
------UIMODUIDE
23 22 21 20 19 18 17 16
- UNLOCK TIMPAGE - - TIMVALUE
15 14 13 12 11 10 9 8
USBE FRZCLK VBUSPO OTGPADE VBUSHWC
76543210
STOE ROLEEXE BCERRE VBERRE VBUSTE IDTE
674
32072H–AVR32–10/2012
AT32UC3A3
This bit can be written even if FRZCLK is one.
• FRZCLK: Freeze USB Clock
1: The clock input are disabled (the resume detection is still active).This reduces power consumption. Unless explicitly stated, all
registers then become read-only.
0: The clock inputs are enabled.
This bit can be written even if USBE is zero. Disabling the USBB (by writing a zero to the USBE bit) does not reset this bit, but
this freezes the clock inputs whatever its value.
• VBUSPO: VBus Polarity
1: The USB_VBOF output signal is inverted (active low).
0: The USB_VBOF output signal is in its default mode (active high).
To be generic. May be useful to control an external VBus power module.
This bit can be written even if USBE is zero or FRZCLK is one. Disabling the USBB (by writing a zero to the USBE bit) does not
reset this bit.
• OTGPADE: OTG Pa d Enable
1: The OTG pad is enabled.
0: The OTG pad is disabled.
This bit can be written even if USBE is zero or FRZCLK is one. Disabling the USBB (by writing a zero to the USBE bit) does not
reset this bit.
• VBUSHWC: VBus Hardware Control
1: The hardware control over the USB_VBOF output pin is disabled.
0: The hardware control ov er the USB_VBOF output pin is enab led. The USBB resets the USB_VBOF output pin when a VB US
problem occurs.
• STOE: Suspend Ti me-Out Interrupt Enable
1: The Suspend Time-Out Interrupt (STOI) is enabled.
0: The Suspend Time-Out Interrupt (STOI) is disabled.
• ROLEEXE: Role Exchange Interrupt Enable
1: The Role Exchange Interrupt (ROLEEXI) is enabled.
0: The Role Exchange Interrupt (ROLEEXI) is disabled.
• BCERRE: B-Connection Error Interrupt Enable
1: The B-Connection Error Interr upt (BCERRI) is enabled.
0: The B-Connection Error Interr upt (BCERRI) is disabled.
• VBERRE: VBus Error Interrupt Enable
1: The VBus Error Interrupt (VBERRI) is enabled.
0: The VBus Error Interrupt (VBERRI) is disabled.
• VBUSTE: VBus Transition Interrupt Enable
1: The VBus Transition Interrupt (VBUSTI) is enabled.
0: The VBus Transition Interrupt (VBUSTI) is disabled.
• IDTE: ID Transition Interrupt Enable
1: The ID Transition interrupt (IDTI) is enabled.
0: The ID Transition interrupt (IDTI) is disabled.
675
32072H–AVR32–10/2012
AT32UC3A3
27.8.1.2 General Status Register
Register Name: USBSTA
Access Type: Read-Only
Offset: 0x0804
Reset Value: 0x00000400
• CLKUSABLE: UTMI Clock Usable
This bit is set when the UTMI 30MHz is usable .
This bit is cleared when the UTMI 30MHz is not usable.
• SPEED: Speed Status
This field is set according to the controller speed mode..
• VBUS: VBus Level
This bit is set when the VBus line level is high.
This bit is cleared when the VBus line level is low.
This bit can be used in either device or host mode to monitor the USB bus connecti on state of the application.
• ID: USB_ID Pin State
This bit is cleared when the USB_ID level is low, even if USBE is zero.
This bit is set when the USB_ID level is high, e vent if USBE is zero.
• VBUSRQ: VBus Request
This bit is set when the USBSTASET.VBUSRQS bit is written to one.
This bit is cleared when the USBSTACLR.VBUSRQC bit is written to one or when a VBus error o ccurs and VBUSHWC is z e ro.
1: The USB_VBOF output pin is driven high to enable the VBUS power supply generation.
0: The USB_VBOF output pin is driven low to disable the VBUS power supply gene ration.
This bit shall only be used in host mode.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
- CLKUSABLE SPEED VBUS ID VBUSRQ -
76543210
STOI ROLEEXI BCERRI VBERRI VBUSTI IDTI
SPEED Speed Status
0 0 Full-Speed mode
1 0 Low-Speed mode
0 1 High-Speed mode
11Reserved
676
32072H–AVR32–10/2012
AT32UC3A3
• STOI: Suspend Time-Out Int errup t
This bit is set when a time-out error (more than 200ms) has been detected after a suspend. This triggers a USB interrupt if
STOE is one.
This bit is cleared when the UBSTACLR.STOIC bit is written to one.
This bit shall only be used in host mode.
• ROLEEXI: Role Exchange Interrupt
This bit is set when the USBB has successfully switched its mode because of an negotiation (host to device or device to host).
This triggers a USB interrupt if ROLEEXE is one.
This bit is cleared when the UBSTACLR.ROLEEXIC bit is written to one.
• BCERRI: B-Connection Error Interrupt
This bit is set when an error occurs during the B-connection. This triggers a USB inte rrupt if BCERRE is one.
This bit is cleared when the UBSTACLR.BCERRIC bit is wr itten to one.
This bit shall only be used in host mode.
• VBERRI: VBus Error Interrupt
This bit is set when a VBus drop has been detected. This triggers a USB interrupt if VBERRE is one.
This bit is cleared when the UBSTACLR.VBERRIC bit is written to one.
This bit shall only be used in host mode.
If a VBus problem occurs, then the VBERRI interrupt is generated even if the USBB does not go to an error state because of
VBUSHWC is one.
• VBUSTI: VBus Transition Interrupt
This bit is set when a transition (high to low, low to high) has been detected on the USB_VBUS pad. This trigge rs an USB
interrupt if VBUSTE is one.
This bit is cleared when the UBSTACLR.VBUSTIC bit is written to one.
This interrupt is generated even if the clock is frozen by the FRZCLK bit.
• IDTI: ID Transition Interrupt
This bit is set when a transition (high to low, low to high) has been detected on the USB_ID input pin. This triggers an USB
interrupt if IDTE is one.
This bit is cleared when the UBSTACLR.IDTIC bit is written to one.
This interrupt is generated even if the clock is frozen by the FRZCLK bit or pad is disable by USBCON.OTGPADE or the USBB
module is disabled by USBCON.USBE.
677
32072H–AVR32–10/2012
AT32UC3A3
27.8.1.3 General Status Clear Register
Register Name: USBSTACLR
Access Type: Write-Only
Offset: 0x0808
Read Value: 0x00000000
Writing a one to a bit in this register will clear the corresponding bit in UBSTA.
Writing a zero to a bit in this register has no effect.
This bit alw ays reads as zero.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
------VBUSRQC-
76543210
STOIC ROLEEXIC BCERRIC VBERRIC VBUSTIC IDTIC
678
32072H–AVR32–10/2012
AT32UC3A3
27.8.1.4 General Status Set Register
Register Name: USBSTASET
Access Type: Write-Only
Offset: 0x080C
Read Value: 0x00000000
Writing a one to a bit in this register will set the corresponding bit in UBSTA, what may be useful for test or debug purposes.
Writing a zero to a bit in this register has no effect.
This bit alw ays reads as zero.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
------VBUSRQS-
76543210
STOIS ROLEEXIS BCERRIS VBERRIS VBUSTIS IDTIS
679
32072H–AVR32–10/2012
AT32UC3A3
27.8.1.5 Version Re gist er
Register Name: UVERS
Access Type: Read-Only
Offset: 0x0818
Read Value: -
• VARIANT: Variant Number
Reserved. No functionality associated.
• VERSION: Version Number
Version number of the module. No functionality associated.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
---- VARIANT
15 14 13 12 11 10 9 8
- - - - VERSION[11:8]
76543210
VERSION[7:0]
680
32072H–AVR32–10/2012
AT32UC3A3
27.8.1.6 Features Register
Register Name: UFEATURES
Access Type: Read-Only
Offset: 0x081C
Read Value: -
• ENHBISOn: High Bandwidth Isochronous Feature for Endpoint n
1: The high bandwidth isochronous is supported.
0: The high bandwidth isochronous is not supported.
• DATABUS: Data Bus 16-8
1: The UTMI data bus is a 16-bit data path at 30MHz.
0: The UTMI data bus is a 8-bit data path at 60MHz.
• BYTEWRITEDPRAM: DPRAM Byte-Write Capability
1: The DPRAM is natively byte-write capable.
0: The DPRAM byte write lanes have shadow logic implemented in the USBB IP interface.
• FIFOMAXSIZE: Maximal FIFO Size
This field indicates the maximal FIFO size, i.e., the DPRAM size:
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
ENHBISO7 ENHBISO6 ENHBISO5 ENHBISO4 ENHBISO3 ENHBISO2 ENHBISO1 DATABUS
15 14 13 12 11 10 9 8
BYTEWRITE
DPRAM FIFOMAXSIZE DMAFIFOWORDDEPTH
76543210
DMABUFFE
RSIZE DMACHANNELNBR EPTNBRMAX
FIFOMAXSIZE Maximal FIFO Siz e
0 0 0 < 256 bytes
0 0 1 < 512 bytes
0 1 0 < 1024 bytes
0 1 1 < 2048 bytes
1 0 0 < 4096 bytes
1 0 1 < 8192 bytes
1 1 0 < 16384 bytes
1 1 1 >= 16384 bytes
681
32072H–AVR32–10/2012
AT32UC3A3
• DMAFIFOWORDDEPTH: DMA FIFO Depth in Words
This field indicates the DMA FIFO dep th controller in words:
• DMABUFFERSIZE: DMA Buff er Size
1: The DMA buffer size is 24bits.
0: The DMA buffer size is 16bits.
• DMACHANNELNBR: Number of DMA Channels
This field indicates the number of hardware-implemented DMA channels:
• EPTNBRMAX: Maximal Number of Pipes/Endpoints
This field indicates the number of hardware-implemented pipes/endpoints:
DMAFIFOWORDDEPTH DMA FIFO Depth in Wo rds
000016
00011
00102
...
111115
DMACHANNELNBR Number of DMA Channels
000Reserved
0011
0102
...
1117
EPTNBRMAX Maximal Number of Pipes/ Endpoints
000016
00011
00102
...
111115
682
32072H–AVR32–10/2012
AT32UC3A3
27.8.1.7 Address Size Register
Register Name: UADDRSIZE
Access Type: Read-Only
Offset: 0x0820
Read Value: -
• UADDRSIZE: IP PB Address Size
This field indicates the size of the PB address space reserved for the USBB IP interface.
31 30 29 28 27 26 25 24
UADDRSIZE[31:24]
23 22 21 20 19 18 17 16
UADDRSIZE[23:16]
15 14 13 12 11 10 9 8
UADDRSIZE[15:8]
76543210
UADDRSIZE[7:0]
683
32072H–AVR32–10/2012
AT32UC3A3
27.8.1.8 Na m e Reg ist er 1
Register Name: UNAME1
Access Type: Read-Only
Offset: 0x0824
Read Value: -
• UNAME1: IP Name Part One
This field indicates the first part of the ASCII-encoded name of the USBB IP.
31 30 29 28 27 26 25 24
UNAME1[31:24]
23 22 21 20 19 18 17 16
UNAME1[23:16]
15 14 13 12 11 10 9 8
UNAME1[15:8]
76543210
UNAME1[7:0]
684
32072H–AVR32–10/2012
AT32UC3A3
27.8.1.9 Na m e Reg ist er 2
Register Name: UNAME2
Access Type: Read-Only
Offset: 0x0828
Read Value:
• UNAME2: IP Name Part Two
This field indicates the se cond part of the ASCII-encoded name of the USBB IP.
31 30 29 28 27 26 25 24
UNAME2[31:24]
23 22 21 20 19 18 17 16
UNAME2[23:16]
15 14 13 12 11 10 9 8
UNAME2[15:8]
76543210
UNAME2[7:0]
685
32072H–AVR32–10/2012
AT32UC3A3
27.8.1.10 Finite State Machine Status Register
Register Name: USBFSM
Access Type: Read-Only
Offset: 0x082C
Read Value: 0x00000009
• DRDSTATE
This field indicates the state of the USBB.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
- - - - DRDSTATE
DRDSTATE Description
0 a_idle state: this is the start state for A-devices (when the ID pin is 0)
1a_wait_vrise: In this state, the A-device waits for the voltage on VBus to rise above the A-
device VBus Valid threshold (4.4 V).
2 a_wait_bcon: In this state, the A-device waits for the B-device to signal a connection.
3 a_host: In this state, the A-device that operates in Host mode is operational.
4 a_suspend: The A-device operating as a host is in the suspend mode.
5 a_peripheral: The A-device operates as a peripheral.
6a_wait_vfall: In this state, the A-device waits for the voltage on VBus to drop below the A-
device Session Valid threshold (1.4 V).
7a_vbus_err: In this state, the A-device waits for recovery of the over-current condition that
caused it to enter this state.
8 a_wait_discharge: In this state, the A-device waits f or the data usb line to discharge (100 us).
9 b_idle: this is the start state for B-device (when the ID pin is 1).
10 b_peripheral: In this state, the B-device acts as the peripheral.
11 b_wait_begin_hnp: In this state, the B-de vice is in suspend mode and waits until 3 ms before
initiating the HNP protocol if requested.
12 b_wait_discharge: In this state, the B-de vice waits for the data usb line to discharge (100 us)
before becoming Host.
686
32072H–AVR32–10/2012
AT32UC3A3
13 b_wait_acon: In this state, the B-device waits for the A-de vice to signal a connect before
becoming B-Host.
14 b_host: In thi s state, the B-device acts as the Host.
15 b_srp_init: In this state, the B-device attempts to sta rt a session using the SRP protocol.
DRDSTATE Description
687
32072H–AVR32–10/2012
AT32UC3A3
27.8.2 USB Device Registers
27.8.2.1 Device General Control Register
Register Name: UDCON
Access Type: Read/Write
Offset: 0x0000
Reset Value: 0x00000100
• OPMODE2: Specific Operational mode
1: The UTMI transceiver is in the «disable bit stuffing and NRZI encoding» operational mode for test purpose.
0: The UTMI transceiver is in normal operation mode.
• TSTPCKT: Test packet mode
1: The UTMI tr a ns c ei ver generates test packets for test purpose.
0: The UTMI transceiver is in normal operation mode.
•TSTK: Test mode K
1: The UTMI transceiver generates high-speed K state for test pur pose.
0: The UTMI transceiver is in normal operation mode.
• TSTJ: Test mode J
1: The UTMI transceiver generates high-speed J state for test pur pose.
0: The UTMI transceiver is in normal operation mode.
• LS: Low-Speed Mode Force
1: The lo w - speed mode is active.
0: The full-spe e d mo de is act i ve.
This bit can be written even if USBE is zero or FRZCLK is on e . Disabling the USBB (by writing a zero to the USBE bit) does not
reset this bit.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
-------OPMODE2
15 14 13 12 11 10 9 8
TSTPCKT TSTK TSTJ LS SPDCONF RMWKUP DETACH
76543210
ADDEN UADD
688
32072H–AVR32–10/2012
AT32UC3A3
• SPDCONF: Speed Configuration
This field contains the peripheral speed.
• RMWKUP: Remote Wake-Up
Writing a one to this bit will send an upstream resume to the host for a remote wake-up.
Writing a zero to this bit has no effect.
This bit is cleared when the USBB receive a USB reset or once the upstream resume has been sent.
• DETACH: Detach
Writing a one to this bit will physically detach the device (disconnect internal pull-up resistor from D+ and D-).
Writing a zero to this bit will reconnect the device.
• ADDEN: Address Enable
Writing a one to this bit will activate the UADD field (USB address).
Writing a zero to this bit has no effect.
This bit is cleared when a USB reset is received.
• UADD: USB Address
This field contains the device address.
This field is cleared when a USB reset is received.
SPDCONF Speed
00
Normal mode: the perip heral starts in full-speed mode and performs a high-speed reset to
switch to the high-speed mode if the host is high-speed capable.
0 1 reserved, do not use this configuration
1 0 reserved, do not use this configuration
1 1 Full-speed: the peripheral remains in full-speed mode whatever is the host speed capability.
689
32072H–AVR32–10/2012
AT32UC3A3
27.8.2.2 Device Global Interrupt Register
Register Name: UDINT
Access Type: Read-Only
Offset: 0x0004
Reset Value: 0x00000000
• DMAnINT: DMA Channel n Interrupt
This bit is set when an interrupt is triggere d by the DMA channel n. This triggers a USB interrupt if DMAnINTE is one.
This bit is cleared when the UDDMAnSTATUS interrupt source is cleared.
• EPnINT: Endp oint n Interrupt
This bit is set when an interrupt is triggered by the endpoint n (UESTAn, UECONn). This triggers a USB interrupt if EPnINTE is
one.
This bit is cleared when the interr upt source is ser v iced.
• UPRSM: Upstream Resume Interrupt
This bit is set when the USBB sends a resume signal called “Upstream Resume”. This triggers a USB interrupt if UPRSME is
one.
This bit is cleared when the UDINTCLR.UPRSMC bit is written to one to acknowledge the interrupt (USB clock inputs must be
enabled before).
• EORSM: End of Resume Interrupt
This bit is set when the USBB detects a valid “End of Resume” signal initiated by the host. This triggers a USB interrupt if
EORSME is one.
This bit is cleared when the UDINTCLR.EORSMC bit is written to one to acknowledge the interrupt.
• WAKEUP: Wake-Up Interrupt
This bit is set when the USBB is reactivated by a filtered non-idl e signal from the lines (not by an upstream resume). This
triggers an interrupt if WAKEUPE is one.
This bit is cleared when the UDINTCLR.WAKEUPC bit is written to one to ackno wledge the interrupt (USB clock inputs must be
enabled before).
This bit is cleared when the Suspend (SUSP) interrupt bit is set.
This interrupt is generated even if the clock is frozen by the FRZCLK bit.
• EORST: End of Reset Interrupt
This bit is set when a USB “End of Reset” has been detected. This triggers a USB interrupt if EORSTE is one.
This bit is cleared when the UDINTCLR.EORSTC bit is written to one to acknowledge the interrupt.
31 30 29 28 27 26 25 24
DMA7INT DMA6INT DMA5INT DMA4INT DMA3INT DMA2INT DMA1INT -
23 22 21 20 19 18 17 16
- - - - EP7INT EP6INT EP5INT EP4INT
15 14 13 12 11 10 9 8
EP3INT EP2INT EP1INT EP0INT - - - -
76543210
- UPRSM EORSM WAKEUP EORST SOF MSOF SUSP
690
32072H–AVR32–10/2012
AT32UC3A3
• SOF: Start of Frame Interrupt
This bit is set when a USB “Start of F r ame” PID (SOF) has been detected (ev ery 1 ms). This triggers a USB interrupt if SOFE is
one. The FNUM field is updated. In High-speed mode, the MFNUM field is cleared.
This bit is cleared when the UDINTCLR.SOFC bit is written to one to acknowledge the interrupt.
• MSOF: Micro Start of Frame Interrupt
This bit is set in High-speed mode when a USB “Micro Start of Frame” PID (SOF) has been detected (every 125 us). This
triggers a USB interrupt if MSOFE is one. The MFNUM field is updated. The FNUM field is unchanged.
This bit is cleared when the UDINTCL R.MSOFC bit is written to one to acknowledge the interrupt.
• SUSP: Suspend Interrupt
This bit is set when a USB “Suspend” idle bus state has been detected for 3 frame per iods (J state for 3 ms). This triggers a
USB interrupt if SUSPE is one.
This bit is cleared when the UDINTCL R.SUSPC bit is written to one to acknowledge the interrupt.
This bit is cleared when the Wake-Up (WAKEUP) interrupt bit is set.
691
32072H–AVR32–10/2012
AT32UC3A3
27.8.2.3 Device Global Interrupt Clear Register
Register Name: UDINTCLR
Access Type: Write-Only
Offset: 0x0008
Read Value: 0x00000000
Writing a one to a bit in this register will clear the corresponding bit in UDINT.
Writing a zero to a bit in this register has no effect.
This bit alw ays reads as zero.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
- UPRSMC EORSMC WAKEUPC EORSTC SOFC MSOFC SUSPC
692
32072H–AVR32–10/2012
AT32UC3A3
27.8.2.4 Device Global Interrupt Set Register
Register Name: UDINTSET
Access Type: Write-Only
Offset: 0x000C
Read Value: 0x00000000
Writing a one to a bit in this register will set the corresponding bit in UDINT, what may be useful for test or debug purposes.
Writing a zero to a bit in this register has no effect.
This bit alw ays reads as zero.
31 30 29 28 27 26 25 24
DMA7INTS DMA6INTS DMA5INTS DMA4INTS DMA3INTS DMA2INTS DMA1INTS -
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
- UPRSMS EORSMS WAKEUPS EORSTS SOFS MSOFS SUSPS
693
32072H–AVR32–10/2012
AT32UC3A3
27.8.2.5 Device Global Interrupt Enable Register
Register Name: UDINTE
Access Type: Read-Only
Offset: 0x0010
Reset Value: 0x00000000
1: The corresponding interrupt is enabled.
0: The corresponding interr upt is disabled.
A bit in this register is set when the corresponding bit in UDINTESET is written to one.
A bit in this register is cleared when the corresponding bit in UDINTECLR is written to one.
31 30 29 28 27 26 25 24
DMA7INTE DMA6INTE DMA5INTE DMA4INTE DMA3INTE DMA2INTE DMA1INTE -
23 22 21 20 19 18 17 16
- - - - EP7INTE EP6INTE EP5INTE EP4INTE
15 14 13 12 11 10 9 8
EP3INTE EP2INTE EP1INTE EP0INTE - - - -
76543210
- UPRSME EORSME WAKEUPE EORSTE SOFE MSOFE SUSPE
694
32072H–AVR32–10/2012
AT32UC3A3
27.8.2.6 Device Global Interrupt Enable Clear Register
Register Name: UDINTECLR
Access Type: Write-Only
Offset: 0x0014
Read Value: 0x00000000
Writing a one to a bit in this register will clear the corresponding bit in UDINTE.
Writing a zero to a bit in this register has no effect.
This bit alw ays reads as zero.
31 30 29 28 27 26 25 24
DMA7INTEC DMA6INTEC DMA5INTEC DMA4INTEC DMA3INTEC DMA2INTEC DMA1INTEC -
23 22 21 20 19 18 17 16
- - - - EP7INTEC EP6INTEC EP5INTEC EP4INTEC
15 14 13 12 11 10 9 8
EP3INTEC EP2INTEC EP1INTEC EP0INTEC - - - -
76543210
- UPRSMEC EORSMEC WAKEUPEC EORSTEC SOFEC MSOFEC SUSPEC
695
32072H–AVR32–10/2012
AT32UC3A3
27.8.2.7 Device Global Interrupt Enable Set Register
Register Name: UDINTESET
Access Type: Write-Only
Offset: 0x0018
Read Value: 0x00000000
Writing a one to a bit in this register will set the corresponding bit in UDINTE.
Writing a zero to a bit in this register has no effect.
This bit alw ays reads as zero.
31 30 29 28 27 26 25 24
DMA7INTES DMA6INTES DMA5INTES DMA4INTES DMA3INTES DMA2INTES DMA1INTES -
23 22 21 20 19 18 17 16
- - - - EP7INTES EP6INTES EP5INTES EP4INTES
15 14 13 12 11 10 9 8
EP3INTES EP2INTES EP1INTES EP0INTES - - - -
76543210
- UPRSMES EORSMES WAKEUPES EORSTES SOFES MSOFES SUSPES
696
32072H–AVR32–10/2012
AT32UC3A3
27.8.2.8 Endpoint Enable/Reset Register
Register Name: UERST
Access Type: Read/Write
Offset: 0x001C
Reset Value: 0x00000000
• EPRSTn: Endpoint n Reset
Writing a one to this bit will reset the endpoint n FIFO prior to any other operation, upon hardware reset or when a USB bus
reset has been received. This resets the endpoint n registers (UECFGn, UESTAn, UECONn) but not the endpoint configuration
(ALLOC, EPBK, EPSIZE, EPDIR, EPTYPE).
All the endpoint mechanism (FIFO counter, reception, transmission, etc.) is reset apart from the Data Toggle Sequence field
(DTSEQ) which can be cleared by setting the RSTDT bit (by writing a one to the RSTDTS bit).
The endpoint configuration remains active and the endpoint is still enabled.
Writing a zero to this bit will complete the reset op eration and start using the FIFO.
This bit is cleared upon receiving a USB reset.
• EPENn: Endpoint n Enable
1: The endpoint n is enabled.
0: The endpoint n is disabled, what forces the endpoint n state to inactiv e (no ans wer to USB requests) and resets the endpoint
n registers (UECFGn, UESTAn, UECONn) but not the endpoint configuration (ALLOC, EPBK, EPSIZE, EPDIR, EPTYPE).
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
EPRST7 EPRST6 EPRST5 EPRST4 EPRST3 EPRST2 EPRST1 EPRST0
15 14 13 12 11 10 9 8
--------
76543210
EPEN7 EPEN6 EPEN5 EPEN4 EPEN3 EPEN2 EPEN1 EPEN0
697
32072H–AVR32–10/2012
AT32UC3A3
27.8.2.9 Device Frame Number Register
Register Name: UDFNUM
Access Type: Read-Only
Offset: 0x0020
Reset Value: 0x00000000
• FNCERR: Frame Number CRC Error
This bit is set when a corrupted frame number (or micro-frame number) is received. This bit and the SOF (or MSOF) interrupt bit
are updated at the same time.
This bit is cleared upon receiving a USB reset.
• FNUM: Frame Number
This field contains the 11-bit frame number information. It is provided in the last received SOF packet.
This field is cleared upon receiving a USB reset.
FNUM is updated even if a corrupted SOF is received.
• MFNUM: Micro Frame Number
This field contains the 3-bit micro frame number information. It is provided in the last received MSOF packet.
This field is cleared at the beginning of each start of frame (SOF interrupt) or upon receiving a USB reset.
MFNUM is updated even if a corrupted MSOF is received.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
FNCERR - FNUM[10:5]
76543210
FNUM[4:0] MFNUM
698
32072H–AVR32–10/2012
AT32UC3A3
27.8.2.10 Endpoint n Configuration Register
Register Name: UECFGn, n in [0..7]
Access Type: Read/Write
Offset: 0x0100 + (n * 0x04)
Reset Value: 0x00000000
• NBTRANS: Number of transaction per microframe f or isochronous endpoint
This field shall be written to the number of transaction per microframe to perform high-bandwidth isochronous transfer
This field can be written only for endpoint that have this capability (see UFEATURES register, ENHBISOn bit). This field is 0
otherwise.
This field is irrelevant for non-isochronous endpoint. Look at the UFEATURES register to know if the high-bandwidth
isochronous featur e is supported by the device..
• EPTYPE: Endpoint Type
This field shall be written to select the endpoint type:
This field is cleared upon receiving a USB reset.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
- NBTRANS EPTYPE - AUTOSW EPDIR
76543210
- EPSIZE EPBK ALLOC -
NBTRANS Number of transaction
0 0 reserved to endpoint that does not have the high-bandwidth isochronous capability.
0 1 def ault value: one transaction p er micro-frame .
1 0 2 transactions per micro-frame. This endpoint should be configured as double-bank.
11
3 transactions per micro-frame. This endpoint should be configured as triple-bank if
supported (see Table 27-1 on page 624).
EPTYPE Endpoint Type
0 0 Control
0 1 Isochronous
10Bulk
1 1 Interrupt
699
32072H–AVR32–10/2012
AT32UC3A3
• AUTOSW: A u tomatic Switch
This bit is cleared upon receiving a USB reset.
1: The automatic bank switching is enabled.
0: The automatic bank switching is disabled.
• EPDIR: Endpoint Direction
This bit is cleared upon receiving a USB reset.
1: The endpoint direction is IN (nor for control endpoints).
0: The endpoint direction is OUT.
• EPSIZE: Endpoint Size
This field shall be written to select the size of each endpoint bank. The maximum size of each endpoint is specified in Table 27-
1 on page 624.
This field is cleared upon receiving a USB reset (except for the endpoint 0).
• EPBK: Endpoint Banks
This field shall be written to select the number of banks for the endpoint:
For control endpoints, a single-bank endpoint (0b00) shall be selected.
This field is cleared upon receiving a USB reset (except for the endpoint 0).
• ALLOC: Endpoint Memory Allocate
Writing a one to this bit will allocate the endpoint memory. The user should check the CFGOK bit to know whether the allocation
of this endpoint is correct.
Writing a zero to this bit will free the endpoint memory.
This bit is cleared upon receiving a USB reset (except for the endpoint 0).
EPSIZE Endpoint Size
0 0 0 8 bytes
00116 bytes
01032 bytes
01164 bytes
1 0 0 128 bytes
1 0 1 256 bytes
1 1 0 512 bytes
EPBK Endpoint Banks
0 0 1 (single-bank endpoint)
0 1 2 (double-bank endpoint)
1 0 3 (triple-bank endpoint) if supported (see Table 27-1 on page 624).
11Reserved
700
32072H–AVR32–10/2012
AT32UC3A3
27.8.2.11 Endpoint n Status Register
Register Name: UESTAn, n in [0..7]
Access Type: Read-Only 0x0100
Offset: 0x0130 + (n * 0x04)
Reset Value: 0x00000100
•BYCT: Byte Count
This field is set with the byte count of the FIFO.
F or IN endpoints, incremented after each byte written by the software into the endpoint and decremented after each byte sent to
the host.
For OUT endpoints, incremented after each byte received from the host and decremented after each byte read by the software
from the endpoint.
This field may be updated one clock cycle after the RWALL bit changes, so the user should not poll this field as an interru pt bit.
• CFGOK: Configu ration OK Status
This bit is updated when the ALLOC bit is written to one.
This bit is set if the endpoint n number of banks (EPBK) and size (EPSIZE) are correct compared to the maximal allowed
number of banks and size for this endpoin t an d to the maximal FIFO size (i.e. the DPRAM size).
If this bit is cleared, the user shall rewrite correct values to the EPBK and EPSIZE fields in the UECFGn register.
• CTRLDIR: Control Direction
This bit is set after a SETUP packet to indicate that the following packet is an IN packet.
This bit is cleared after a SETUP packet to indicate that the following packet is an OUT packet.
Writi ng a zero or a one to this bit has no effect.
• RWALL: Read/Write Allowed
This bit is set for IN endpoints when the current bank is not full, i.e., the user can write further data into the FIFO.
This bit is set for OUT endpoints when the current bank is not empty, i.e., the user can read further data from the FIFO.
This bit is never set if STALLRQ is one or in case of erro r.
This bit is cleared otherwise.
This bit shall not be used for control endpoints.
31 30 29 28 27 26 25 24
- BYCT
23 22 21 20 19 18 17 16
BYCT - CFGOK CTRLDIR RWALL
15 14 13 12 11 10 9 8
CURRBK NBUSYBK - ERRORTRANS DTSEQ
76543210
SHORT
PACKET STALLEDI/
CRCERRI OVERFI NAKINI/
HBISOFLUSHI NAKOUTI/
HBISOINERRI RXSTPI/
UNDERFI RXOUTI TXINI
701
32072H–AVR32–10/2012
AT32UC3A3
• CURRBK: Current Bank
This bit is set for non-control endp oints, to indicate the current bank:
This field may be updated one clock cycle after the RWALL bit changes, so the user should not poll this field as an interru pt bit.
• NBUSYBK: Number of Busy Banks
This field is set to indicate the number of busy banks:
For IN endpo ints, it indicates the number of banks filled by the user and ready for IN transfer. When all banks are free, this
triggers an EPnINT interrupt if NBUSYBKE is one.
For OUT endpoints, it indicates the number of banks filled by OUT transactions from the host. When all banks are busy, this
triggers an EPnINT interrupt if NBUSYBKE is one.
When the FIFOCON bit is cleared (by writing a one to the FIFOCONC bit) to validate a new bank, this field is updated two or
three clock cycles later to calculate the address of the next bank.
An EPnINT interrupt is triggered if:
- for IN endpoint, NBUSYBKE is one and all the banks are free.
- for OUT endpoint, NBUSYBKE is one and all the banks are busy.
• ERRORTRANS: High-bandwid th isochronous OUT en dp oi nt tran sactio n error Interrupt
This bit is set when a transaction error occurs during the current micro-frame (the data toggle sequencing does not respect the
usb 2.0 standard). This triggers an EPnINT interrupt if ERRORTRANSE is one.
This bit is set as long as the current bank (CURRBK) belongs to the bad n-transactions (n=1,2 or 3) transferred during the
micro-frame. Shall be cleared by software by clearing (at least once) the FIFOCON bit to switch to the bank that belongs to the
ne xt n-transactions (next micro-frame).
Look at the UFEATURES register to know if the high-bandwidth isochr onous feature is supported by the de vice.
• DTSEQ: Data Toggle Sequence
This field is set to indicate the PID of the current bank:
For IN transfers, it indicate s the data toggle sequence that will be used for the next packet to be sent. This is not relative to the
current bank.
CURRBK Current Bank
00Bank0
01Bank1
1 0 Bank2 if supported (see Table 27-1 on page 624).
11Reserved
NBUSYBK Number of Busy Banks
0 0 0 (all banks free)
011
102
1 1 3 if supported (see Table 27-1 on page 624).
DTSEQ Data Toggle Sequence
00Data0
01Data1
1 0 Data2 (for high-bandwidth isochronous endpoint)
1 1 MData (for high-bandwidth isochronous endpoint)
702
32072H–AVR32–10/2012
AT32UC3A3
For OUT transfers, this value indicates the last data toggle sequen ce received on the current bank.
By default DTSEQ is 0b01, as if the last data toggle sequence was Data1, so the next sent or expected data toggle sequence
should be Data0.
For High-band width isochronous endpoint, an EPnINT interrupt is triggered if:
- MDATAE is one and a MData packet has been received (DTSEQ=MData and RXOUTI is one).
- DATAXE is one and a Data0/1/2 packet has been received (DTSEQ=Data0/1/2 and RXOUTI is one)
Look at the UFEATURES register to know if the high-bandwidth isochr onous feature is supported by the de vice.
• SHORTPACKET: Short Packet Interrupt
This bit is set for non-control OUT endpoints, when a short packet has been received.
This bit is set for non-control IN endpoints, a short packet is transmitted upon ending a DMA transfer, thus signaling an end of
isochronous frame or a bulk or interrupt end of transfer, this only if the End of DMA Buffer Output Enable (DMAENDEN) bit and
the Automatic Switch (AUTOSW) bit are written to one.
This triggers an EPnINT inte rrupt if SHORTPACKETE is one.
This bit is cleared when the SHORTPACKETC bit is written to one. This will acknowledge the interrupt.
• STALLEDI: STALLed Interrupt
This bit is set to signal that a STALL handshake has been sent. To do that, the softw are has to set the STALLRQ bit (b y writing a
one to the STALLRQS bit). This triggers an EPnINT interr upt if STALLEDE is one.
This bit is cleared when the STALLEDIC bit is written to one. This will acknowledge the interrupt.
• CRCERRI: CRC Error Interrupt
This bit is set to signal that a CRC error has been detected in an isochronous OUT endpoint. The OUT packet is stored in the
bank as if no CRC error had occurred. This triggers an EPnINT interrupt if CRCERRE is one.
This bit is cleared when the CRCERRIC bit is written to one. This will acknowledge the interrupt.
• OVERFI: Overflow Interrupt
This bit is set when an overflow error occurs. This triggers an EPnINT interrupt if OVERFE is one.
For all endpoint types, an overflow can occur during OUT stage if the host attempts to wr ite into a bank that is too small for the
pack et. The packet is ac knowledged and the RXOUTI bit is set as if no overflow had occurred. The bank is filled with all the first
bytes of the packet that fit in.
This bit is cleared when the OVERFIC bit is written to one. This will acknowledge the interrupt.
• NAKINI: NAKed IN Interrupt
This bit is set when a NAK handshake has been sent in response to an IN request from the host. This triggers an EPnINT
interrupt if NAKINE is one.
This bit is cleared when the NAKINIC bit is wr itten to one. This will acknowledge the interrupt.
• HBISOFLUSHI: High Bandwidth Isochronous IN Flush Interrupt
This bit is set, f or High-bandwidth isochronous IN endpoint (with NBTRANS=2 or 3), at the end of the micro-frame, if less than N
transaction has been completed by the USBB without underflow error. This may occur in case of a missing IN token. In this
case, the bank are flushed out to ensure the data synchronization between the host and the device. This triggers an EPnINT
interrupt if HBISOFLUSHE is one.
This bit is cleared when the HBISOFLUSHIC bit is written to one. This will acknowledge the interrupt.
Look at the UFEATURES register to know if the high-bandwidth isochr onous feature is supported by the de vice.
• NAKOUTI: NAKed OUT Interrupt
This bit is set when a NAK handshake has been sent in response to an OUT request from the host. This triggers an EPnINT
interrupt if NAKOUTE is one.
This bit is cleared when the NAKOUTIC bit is written to one. This will acknowledge the interrupt.
• HBISOINERRI: High bandwidth isochronous IN Underflow Error Interrupt
This bit is set, for High-bandwidth isochronous IN endpoint (with NBTRANS=2 or 3), at the end of the microframe, if less than N
bank was written by the cpu within this micro-frame. This triggers an EPnINT interrupt if HBISOINE RRE is one.
This bit is cleared when the HBISOINERRIC bi t is written to one. This will acknowledge the interrupt.
Look at the UFEATURES register to know if the high-bandwidth isochr onous feature is supported by the de vice.
• UNDERFI: Underflow Interrupt
This bit is set, for isochronous IN/OUT endpoints, when an underflow error occurs. This triggers an EPnINT interrupt if
UNDERFE is one.
703
32072H–AVR32–10/2012
AT32UC3A3
An underflow can occur during IN stage if the host attempts to read from an empty bank. A zero-length packet is then
automatically sent by the USBB.
An underflow can also occur during OUT stage if the host sends a packet while the bank is already full. Typically, the CPU is not
fast enough. The packet is lost.
Shall be cleared by writing a one to the UNDERFIC bit. Th is will acknowledge the interr upt.
This bit is inactive (cleared) for bulk and interrupt IN/OUT endpoints and it means RXSTPI for control endpoints.
• RXSTPI: Received SETUP Interrupt
This bit is set, for control endpoints, to signal that the current bank contains a new valid SETUP pac k et. This triggers an EPnINT
interrupt if RXSTPE is one.
Shall be cleared by writing a one to the RXSTPIC bit. This will acknowledge the interrupt and free the bank.
This bit is inactive (cleared) for bulk and interrupt IN/OUT endpoints and it means UNDERFI f or isochronous IN/OUT endpoints.
• RXOUTI: Received OUT Data Interrupt
This bit is set, for control endpoints, when the current bank contains a bulk OUT pac ket (data or status stage). This triggers an
EPnINT interrupt if RXOUTE is one.
Shall be cleared for control end points, by writing a one to the RXOUTIC bit. This will acknowledge the interrupt and free the
bank.
This bit is set for isochronous, bulk and, interrupt OUT endpoints, at the same time as FIFOCON when the current bank is full.
This triggers an EPnINT interrupt if RXOUTE is one.
Shall be cleared for isochronous, b ulk and, interrupt OUT endpoints, by writing a one to the RXOUTIC bit. This will acknowledge
the interrupt, what has no effect on the endpoint FIFO.
The user then reads from the FIFO and clears the FIFOCON bit to free the bank. If the OUT endpoint is composed of multiple
banks, this also s witches to the next bank. The RXOUTI and FIFOCON bits are set/cleared in accordance with the status of the
next bank.
RXOUTI shall always be cleared before clearing FIFOCON.
This bit is inactive (cleared) for isochronous, b ulk and interrupt IN endpoints.
• TXINI: Transmitted IN Data Interrupt
This bit is set f or control endpoints, when the current bank is ready to accept a new IN pack et. This triggers an EPnINT interrupt
if TXINE is one.
This bit is cleared when the TXINIC bit is written to one. This will acknowledge the interrupt and send the packet.
This bit is set for isochronous, bulk and interrupt IN endpoints, at the same time as FIFOCON whe n the current bank is free.
This triggers an EPnINT interrupt if TXINE is one.
This bit is cleared when the TXINIC bit is written to one. This will acknowledge the interrupt, what has no effect on the endpoint
FIFO.
The user then writes into the FIFO and clears the FIFOCON bit to allow the USBB to send the data. If the IN endpoint is
composed of multiple banks, this also switches to the next bank. The TXINI and FIFOCON bits are set/cleared in accordance
with the status of the next bank.
TXINI shall always be cleared before clearing FIFOCON.
This bit is inactive (cleared) for isochronous, b ulk and interrupt OUT endpoints.
704
32072H–AVR32–10/2012
AT32UC3A3
27.8.2.12 Endpoint n Status Clear Register
Register Name: UESTAnCLR, n in [0..7]
Access Type: Write-Only
Offset: 0x0160 + (n * 0x04)
Read Value: 0x00000000
Writing a one to a bit in this register will clear the corresponding bit in UESTA.
Writing a zero to a bit in this register has no effect.
This bit alw ays reads as zero.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
SHORT
PACKETC STALLEDIC/
CRCERRIC OVERFIC NAKINIC/
HBISOFLUSHIC NAKOUTIC/
HBISOINERRIC RXSTPIC/
UNDERFIC RXOUTIC TXINIC
705
32072H–AVR32–10/2012
AT32UC3A3
27.8.2.13 Endpoint n Status Set Register
Register Name: UESTAnSET, n in [0..7]
Access Type: Write-Only
Offset: 0x0190 + (n * 0x04)
Read Value: 0x00000000
Writing a one to a bit in this register will set the corresponding bit in UESTA, what may be useful for test or debug purposes.
Writing a zero to a bit in this register has no effect.
This bit alw ays reads as zero.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
- - - NBUSYBKS - - -
76543210
SHORT
PACKETS STALLEDIS/
CRCERRIS OVERFIS NAKINIS/
HBISOFLUSHIS NAKOUTIS/
HBISOINERRIS RXSTPIS/
UNDERFIS RXOUTIS TXINIS
706
32072H–AVR32–10/2012
AT32UC3A3
27.8.2.14 Endpoint n Control Register
Register Name: UECONn, n in [0..7]
Access Type: Read-Only
Offset: 0x01C0 + (n * 0x04)
Reset Value: 0x00000000
• STALLRQ: STALL Request
This bit is set when the STALLRQS bit is written to one. This will request to send a STALL handshake to the host.
This bit is cleared when a new SETUP packet is received or when the STALLRQC bit is written to zero.
• RSTDT: Reset Data Toggle
This bit is set when the RSTDTS bit is written to one. This will clear the data toggle sequence, i.e., set to Data0 the data toggle
sequence of the next sent (IN endpoints) or received (OUT endpoints) packet.
This bit is cleared instantaneously.
The user does not have to wait for this bit to be cleared.
• NYETDIS: NYET token disable
This bit is set when the NYETDISS bit is written to one. This will send a ACK handshake inste ad of a NYET handshake in high-
speed mode.
This bit is cleared when the NYETDISC bit is written to one.This will let the USBB handling the high-speed handshake follo wing
the usb 2.0 standard.
• EPDISHDMA: Endpoint Interrupts Disable HDMA Request Enable
This bit is set when the EPDISHDMAS is written to one. This will pause the on-going DMA channel n transf er on any Endpoint n
interrupt (EPnINT), whatever the state of the Endpoint n Interrupt Enable bit (EPnINTE).
The user then has to ackno wledge or to disable the interrupt source (e.g. RXOUTI) or to clear the EPDISHDMA bit (b y writing a
one to the EPDISHDMAC bit) in order to comp lete the DMA transfer.
In ping-pong mode, if the interrupt is associated to a new system-bank packet (e.g. Bank1) and the current DMA transfer is
running on the previous packet (Bank0), then the previous-packet DMA transfer completes normally, but the new-packet DMA
transfer will not start (not requested).
If the interrupt is not associated to a new system-bank packet (NAKINI, NAKOUTI, etc.), then the request cancellation may
occur at any time and may imme diately pause the current DMA transfer.
This may be used for example to identify erroneous packets, to prevent them from being transferred into a buffer, to complete a
DMA transfer by software after reception of a short packet, etc.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
- - - - STALLRQ RSTDT NYETDIS EPDISHDMA
15 14 13 12 11 10 9 8
- FIFOCON KILLBK NBUSYBKE - ERRORTRANSE DATAXE MDATAE
76543210
SHORT
PACKETE STALLEDE/
CRCERRE OVERFE NAKINE/
HBISOFLUSHE NAKOUTE/
HBISOINERRE RXSTPE/
UNDERFE RXOUTE TXINE
707
32072H–AVR32–10/2012
AT32UC3A3
• FIFOCON: FIFO Control
For control endpoi nts:
The FIFOCON and RWALL bits are irrelevant. The software shall therefore never use them on these endpoints. When read,
their value is always 0.
For IN endpo ints:
This bit is set when the current bank is free, at the same time as TXINI.
This bit is cleared (by writing a one to the FIFOCONC bit) to send the FIFO data and to switch to the next bank.
For OUT endpoints:
This bit is set when the current bank is full, at the same time as RXOUTI.
This bit is cleared (by writing a one to the FIFOCONC bit) to free the current bank and to switch to the next bank.
• KILLBK: Kill IN Bank
This bit is set when the KILLBKS bit is written to one. This will kill the last written bank.
This bit is cleared by hardware after the completion of the “kill packet procedure”.
The user shall wait for this bit to be cleared before trying to process another IN packet.
Caution: The bank is cleared when the “kill packet” procedure is completed by the USBB core :
If the bank is really killed, the NBUSYBK field is decremented.
If the bank is not “killed” but sent (IN transfer), the NBUSYBK field is decremented and the TXINI flag is set. This specific case
can occur if at the same time an IN token is coming and the user wants to kill this bank.
Note : If two banks are ready to be sent, the above specific case can not occur, because the first bank is sent (IN transf er) while
the last bank is killed.
• NBUSYBKE: Number of Busy Banks Interrupt Enable
This bit is set when the NBUSYBKES bit is written to one. This will enable the Number of Busy Banks interrupt (NBUSYBK).
This bit is cleared when the NBUSYBKEC bit is written to zero. This will disable the Number of Busy Banks interrupt
(NBUSYBK).
• ERRORTRANSE: Transaction Error Interrupt Enable
This bit is set when the ERRORTRANSES bit is written to one. This will enable the transaction error interrupt (ERRORTRANS).
This bit is cleared when the ERRORTRANSEC bit is written to one. This will disable the transaction error interrupt
(ERRORTRANS).
• DATAXE: DataX Interrupt Enable
This bit is set when the D ATAXES bit is written to one. This will enable the DATAX interrupt. (see DTSEQ bits)
This bit is cleared when the DATAXEC bit is written to one. This will disable the DATAX interrupt.
• MDATAE: MData Interrupt Enable
This bit is set when the MDATAES bit is written to one. This will enable the Multiple D ATA interrupt. (see DTSEQ bits)
This bit is cleared when the MDATAEC bit is written to one. This will disable the Multiple DATA interrupt.
• SHORTPACKETE: Short Packet Interrupt Enable
This bit is set when the SHORTPACKETES bit is written to one. This will enable the Short Packet interrupt (SHORTPACKET).
This bit is cleared when the SHORTPACKETEC bit is written to one. This will disable the Short Packet interrupt
(SHORTPACKET).
• STALLEDE: STALLed Interrupt Enable
This bit is set when the STALLEDES bit is written to one. This will enable the STALLed interrupt (STALLEDI).
This bit is cleared when the STALLEDEC bit is written to one. This will disable the STALLed interrupt (STALLEDI).
• CRCERRE: CRC Error Interrupt Enable
This bit is set when the CRCERRES bit is written to one. This will enable the CRC Error interrupt (CRCERRI).
This bit is cleared when the CRCERREC bit is wr itten to one. This will disable the CRC Error interrupt (CRCERRI).
• OVERFE: Overflow Interrupt Enable
This bit is set when the OVERFES bit is written to one. This will enable the Overflow interrupt (OVERFI).
This bit is cleared when the OVERFEC bit is writte n to one. This will disable the Overflow interrupt (OVERFI).
• NAKINE: NAKed IN Interrupt Enable
This bit is set when the NAKINES bit is written to one. This will enable the NAKed IN interrupt (NAKINI).
This bit is cleared when the NAKINEC bit is written to one. This will disable the NAKed IN interrupt (NAKINI).
• HBISOFLUSHE : High Bandwidth Isochronous IN Flush Interrupt Enable
This bit is set when the HBISOFLUSHES bit is written to one. This will enable the HBISOFLUSHI interrupt.
708
32072H–AVR32–10/2012
AT32UC3A3
This bit is cleared when the HBISOFLUSHEC bit disable th e H BISOFLUSHI interrupt.
Look at the UFEATURES register to know if the high-bandwidth isochr onous feature is supported by the de vice.
• NAKOUTE: NAKed OUT Interrupt Enable
This bit is set when the NAKOUTES bit is written to one. This will enable the NAKed OUT interrupt (NAKOUTI).
This bit is cleared when the NAKOUTEC bit is writte n to one. This will disable the NAKed OUT interrupt (NAKOUTI).
• HBISOINERRE: High Bandwidth Isochronous IN Error Interrupt Enable
This bit is set when the HBISOINERRES bit is written to one. This will enable the HBISOINERRI interrupt.
This bit is cleared when the HBISOINERREC bit disable the HBISOINERRI interrupt.
Look at the UFEATURES register to know if the high-bandwidth isochr onous feature is supported by the de vice.
• RXSTPE: Received SETUP Interrupt Enable
This bit is set when the RXSTPES bit is written to one. This will enable the Received SETUP interrupt (RXSTPI).
This bit is cleared when the RXSTPEC bit is wr itten to one. This will disable the Received SETUP interrupt (RXSTPI).
• UNDERFE: Underflow Interrupt Enable
This bit is set when the UNDERFES bit is written to one. This will enable the Underflow interrupt (UNDERFI).
This bit is cleared when the UNDERFEC bit is written to one. This will disable the Underflow interrupt (UNDERFI).
• RXOUTE: Received OUT Data Interrupt Enable
This bit is set when the RXOUTES bit is written to one. This will enable the Received OUT Data interrupt (RXOUT).
This bit is cleared when the RXOUTEC bit is wri tten to one. This will disable the Received OUT Data interrupt (RXOUT).
• TXINE: Transmitted IN Data Interrupt Enable
This bit is set when the TXINES bit is written to one. This will enable the Transmitted IN Data interr upt (TXINI).
This bit is cleared when the TXINEC bit is written to one. This will disable the Transmitted IN Data interrupt (TXINI).
709
32072H–AVR32–10/2012
AT32UC3A3
27.8.2.15 Endpoint n Control Clear Register
Register Name: UECONnCLR, n in [0..7]
Access Type: Write-Only
Offset: 0x0220 + (n * 0x04)
Read Value: 0x00000000
Writing a one to a bit in this register will clear the corresponding bit in UECONn.
Writing a zero to a bit in this register has no effect.
This bit alw ays reads as zero.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
- - - - STALLRQC - NYETDISC EPDISHDMAC
15 14 13 12 11 10 9 8
- FIFOCONC - NBUSYBKEC -ERRORTRANSEC DATAXEC MDATEC
76543210
SHORT
PACKETEC STALLEDEC/
CRCERREC OVERFEC NAKINEC/
HBISOFLUSHEC NAKOUTEC/
HBISOINERREC RXSTPEC/
UNDERFEC RXOUTEC TXINEC
710
32072H–AVR32–10/2012
AT32UC3A3
27.8.2.16 Endpoint n Control Set Register
Register Name: UECONnSET, n in [0..7]
Access Type: Write-Only
Offset: 0x01F0 + (n * 0x04)
Read Value: 0x00000000
Writing a one to a bit in this register will set the corresponding bit in UECONn.
Writing a zero to a bit in this register has no effect.
This bit alw ays reads as zero.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
- - - - STALLRQS RSTDTS NYETDISS EPDISHDMAS
15 14 13 12 11 10 9 8
- - KILLBKS NBUSYBKES -ERRORTRANSES DATAXES MDATES
76543210
SHORT
PACKETES STALLEDES/
CRCERRES OVERFES NAKINES/
HBISOFLUSHES NAKOUTES/
HBISOINERRES RXSTPES/
UNDERFES RXOUTES TXINES
711
32072H–AVR32–10/2012
AT32UC3A3
27.8.2.17 Device DMA Channel n Next Descriptor Address Register
Register Name: UDDMAnNEXTDESC, n in [1..7 ]
Access Type: Read/Write
Offset: 0x0310 + (n - 1) * 0x10
Reset Value: 0x00000000
• NXTDESCADDR: Next Descriptor Address
This field contains the bits 31:4 of the 16-byte aligned address of the next channel descriptor to be processed.
This field is written either or by descriptor loading.
31 30 29 28 27 26 25 24
NXTDESCADDR[31:24]
23 22 21 20 19 18 17 16
NXTDESCADDR[23:16]
15 14 13 12 11 10 9 8
NXTDESCADDR[15:8]
76543210
NXTDESCADDR[7:4] - - - -
712
32072H–AVR32–10/2012
AT32UC3A3
27.8.2.18 Device DMA Channel n HSB Address Register
Register Name: UDDMAnADDR, n in [1..7]
Access Type: Read/Write
Offset: 0x0314 + (n - 1) * 0x10
Reset Value: 0x00000000
• HSBADDR: HSB Address
This field determines the HSB bus current address of a channel transfer.
The address written to the HSB address bus is HSBADDR rounded down to the nearest word-aligned address, i.e.,
HSBADDR[1:0] is considered as 0b00 since only word accesses are perf ormed.
Channel HSB start and end addresses may be aligned on any byte boundary.
The user may write this field only when the Channel Enabled bit (CHEN) of the UDDMAnSTATUS register is cleared.
This field is updated at the end of the address phase of the current access to the HSB bus . It is incremented of the HSB access
byte-width.
The HSB access width is 4 bytes, or less at packet start or end if the start or end address is not aligned on a word boundary.
The packet start address is either the channel start address or the next channel address to be accessed in the channel buffer.
The packet end address is either the channel end address or the latest channel address accessed in the channel buffer.
The channel start address is written or loaded from the descriptor , whereas the channel end address is either determined by the
end of buffer or the end of USB transfer if the Buffer Close Input Enable bit (BUFFCLOSEINEN) is set.
31 30 29 28 27 26 25 24
HSBADDR[31:24]
23 22 21 20 19 18 17 16
HSBADDR[23:16]
15 14 13 12 11 10 9 8
HSBADDR[15:8]
76543210
HSBADDR[7:0]
713
32072H–AVR32–10/2012
AT32UC3A3
27.8.2.19 Device DMA Channel n Control Register
Register Name: UDDMAnCONTROL, n in [1..7]
Access Type: Read/Write
Offset: 0x0318 + (n - 1) * 0x10
Reset Value: 0x00000000
• CHBYTELENGTH: Channel Byte Length
This field determines the total number of bytes to be transfe rred for this buffer.
The maximum channel transfer size 64kB is reached when this field is zero (default value).
If the transfer size is unknown, the transfer end is controlled by the peripheral and this field should be written to zero.
This field can be written or descriptor loading only after the UDDMAnSTATUS .CHEN bit has been cleared, otherwise this field is
ignored.
• BURSTLOCKEN: Burst Lock Enable
1: The USB data burst is lock ed for maximum optimization of HSB busses bandwidth usage and maximization of fly-b y duration.
0: The DMA never locks the HSB access.
• DESCLDIRQEN: Descriptor Loaded Interrupt Enable
1: The Descriptor Loaded interrupt is enabled.This interrupt is generated when a Descriptor has been loaded from the system
bus.
0: The Descriptor Loaded interrupt is disabled.
• EOBUFFIRQEN : End of Buffer Interrupt Enable
1: The end of buffer interrupt is enabled.This interrupt is generated when the channel byte count reaches zero.
0: The end of buffer interrupt is disabled.
• EOTIRQEN: End of USB Transfer Interrupt Enable
1: The end of usb OUT data transfer interrupt is enabled. This interrupt is generated only if the BUFFCLOSEINEN bit is set.
0: The end of usb OUT data transfer interrupt is disabled.
• DMAENDEN: End of DMA Buffer Output Enable
Writing a one to this bit will properly complete the usb transfer at the end of the dma transfer.
For IN endpoint, it means that a short packet (but not a Zero Length Packet) will be sent to the USB line to properly closed the
usb transfer at the end of the dma transfer.
For OUT endpoint, it means that all the banks will be properly released. (NBUSYBK=0) at the end of the dma transfer.
31 30 29 28 27 26 25 24
CHBYTELENGTH[15:8]
23 22 21 20 19 18 17 16
CHBYTELENGTH[7:0]
15 14 13 12 11 10 9 8
--------
76543210
BURSTLOCKEN DESCLDIRQEN EOBUFFIRQEN EOTIRQEN DMAENDEN BUFFCLOSE
INEN LDNXTCH
DESCEN CHEN
714
32072H–AVR32–10/2012
AT32UC3A3
• BUFFCLOSEINEN: Buffer Close Input Enable
For Bulk and Interrupt endpoint, writing a one to this bit will automatically close the current DMA transfer at the end of the USB
OUT data transfer (received short packet).
For Full-speed Isochronous, it does not make sense, so BUFFCLOSEINEN should be left to zero.
F or high-speed OUT isochronous, it may mak e sense. In that case, if BUFFCLOSEINEN is written to one, the current DMA
transf er is closed when the received PID packet is not MDATA.
Writing a zero to this bit to disable this feature.
• LDNXTCHDESCEN: Load Next Channel Descriptor Enable
1: the channel controller loads the next descriptor after the end of the current transfer, i.e. when the UDDMAnSTATUS.CHEN bit
is reset.
0: no channel register is loaded after the end of the channel transfer.
If the CHEN bit is written to zero, the next descriptor is immediately loaded upon transfer request (endpoint is free for IN
endpoint, or endpoint is full for OUT endpoint).
Table 27-6. DMA Channel Control Command Summary
• CHEN: Channel Enable
Writing this bit to zero will disabled the DMA cha nnel and no transfer will occur upon request. If the LDNXTCHDESCEN bit is
written to zero, the channel is frozen and the channel registers may then be read and/or written reliably as soon as both
UDDMAnSTATUS.CHEN and CHACTIVE bits are zero.
Writing this bit to one will set the UDDMAnSTATUS.CHEN bit and enable DMA channel data transfer . Then any pending request
will start the transfer. This may be used to start or resume any requested transfer.
This bit is cleared when the chann el source bus is disabled at end of buffer. If the LDNXTCHDESCEN bit has been cleared by
descri ptor loading, the user will have to write to one the corresponding CHEN bit to start the described transfer, if needed.
If a channel request is currently serviced when this bit is zero, the DMA FIFO buffer is drained until it is empty, then the
UDDMAnSTATUS.CHEN bit is cleared.
If the LDNXTCHDESCEN bit is set or after this bit clearing, then the currently loaded descriptor is skipped (no data transfer
occurs) and the next descriptor is immediately loaded.
LDNXTCHDES
CEN CHEN Current Bank
0 0 stop now
0 1 Run and stop at end of buffer
1 0 Load next descriptor now
1 1 Run and link at end of buffer
715
32072H–AVR32–10/2012
AT32UC3A3
27.8.2.20 Device DMA Channel n Status Register
Register Name: UDDMAnSTATUS, n in [1..7]
Access Type: Read/Write
Offset: 0x031C + (n - 1) * 0x10
Reset Value: 0x00000000
• CHBYTECNT: Channel Byte Count
This field contains the current number of bytes still to be transferred for this buffer.
This field is decremented at each dma access.
This field is reliable (stable) only if the CHEN bit is zero.
• DESCLDSTA: Descriptor Loaded Status
This bit is set when a Descriptor has been loaded from the HSB bus.
This bit is cleared when read by the user.
• EOCHBUFFSTA: End of Ch annel Buffer Status
This bit is set when the Channel Byte Count counts down to zero.
This bit is automati cally cleared when read by software.
• EOTSTA: End of USB Transfer Status
This bit is set when the completion of the usb data transfer has closed the dma transfer. It is valid only if
UDDMAnCONTROL.BUFFCLOSEINEN is one. Note that for OUT endpoint, if the UECFGn.A UTOSW is set, any received zero-
length-packet will be cancelled by the DMA, and the EOTSTA will be set whatever the UDDMAnCONTROL.CHEN bit is.
This bit is automati cally cleared when read by software.
• CHACTIVE: Channel Active
0: the DMA channel is no longer trying to source the packet data.
1: the DMA channel is currently trying to source packet data, i.e. selected as the highest-priority requesting channel. When a
pack et transf er cannot be completed due to an EOCHBUFFSTA, this bit sta ys set during the next channel descriptor load (if any)
and potentially until USB packet transf er completion, if allowed b y the ne w descriptor.
When programming a DMA by descriptor (Load next descriptor now), the CHACTIVE bit is set only once the DMA is run ning
(the endpoint is free for IN transaction, the endpoint is full f or OUT transaction).
• CHEN: Channel Enabled
This bit is set (after one cycle latency) when the L.CHEN is written to one or when the descriptor is loaded.
This bit is cleared when any transfer is ended either due to an elapsed byte count or a USB device initiated transfer end.
31 30 29 28 27 26 25 24
CHBYTECNT[15:8]
23 22 21 20 19 18 17 16
CHBYTECNT[7:0]
15 14 13 12 11 10 9 8
--------
76543210
-DESCLD
STA EOCHBUFF
STA EOTSTA - - CHACTIVE CHEN
716
32072H–AVR32–10/2012
AT32UC3A3
0: the DMA channel no longer transfers data, and may load the next descri ptor if the UDDMAnCONTROL.LDNXTCHDESCEN
bit is zero.
1: the DMA channel is currently enabled and transfers data upon request.
If a channel request is currently serviced when the UDDMAnCONTROL.CHEN bit is written to zero, the DMA FIFO buffer is
drained until it is empty, then this status bit is cleared.
717
32072H–AVR32–10/2012
AT32UC3A3
27.8.3 USB Host Registers
27.8.3.1 Host General Control Register
Register Name: UHCON
Access Type: Read/Write
Offset: 0x0400
Reset Value: 0x00000000
• SPDCONF: Speed Configuration
This field contains the host speed capab ility.
• RESUME: Send USB Resume
Writing a one to this bit will generate a USB Resume on the USB bus.
This bit is cleared when the USB Resume has been sent or when a USB reset is requested.
Writing a zero to this bit has no effect.
This bit should be written to one only when the start of frame generation is enable. (SOFE bit is one).
• RESET: Send USB Reset
Writing a one to this bit will generate a USB Reset on the USB bus.
This bit is cleared when the USB Reset has been sent.
It may be useful to write a zero to this bit when a device disconnection is detected (UHINT.DDISCI is one) whereas a USB Reset
is being sent.
• SOFE: Start of Frame Generation Enable
Writing a one to this bit will generate SOF on the USB bus in full speed mode and keep alive in low speed mode.
Writing a zero to this bit will disable the SOF generation and to leave the USB bus in idle state.
This bit is set when a USB reset is requested or an upstream resume interrupt is detected (UHINT.RXRSMI).
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
- - SPDCONF - RESUME RESET SOFE
76543210
--------
SPDCONF Speed
00
Normal mode: the host start in full-speed mode and perform a high-speed reset to switch to
the high-speed mode if the downstream peripheral is high-speed capable.
0 1 reserved, do not use this configuration
1 0 reserved, do not use this configuration
1 1 Full-speed: the host remains to full-speed mode whatever is the peripheral speed capability.
718
32072H–AVR32–10/2012
AT32UC3A3
27.8.3.2 Ho st Glo bal Int er rupt Register
Register Name: UHINT
Access Type: Read-Only
Offset: 0x0404
Reset Value: 0x00000000
• DMAnINT: DMA Channel n Interrupt
This bit is set when an interrupt is triggere d by the DMA channel n. This triggers a USB interrupt if the corresponding
DMAnINTE is one (UHINTE register).
This bit is cleared when the UHDMAnSTATUS interrupt source is cleared.
• PnINT: Pipe n Interrupt
This bit is set when an interrupt is triggered by the endpoint n (UPSTAn). This triggers a USB interrupt if the corresponding pipe
interrupt enable bit is one (UHINTE register).
This bit is cleared when the interr upt source is ser ved.
• HWUPI: Host Wake-Up Interrupt
This bit is set when the host controller is in the suspend mode (SOFE is zero) and an upstream resume from the peripheral is
detected.
This bit is set when the host controller is in the suspend mode (SOFE is zero) and a peripheral disconnection is detected.
This bit is set when the host controller is in the Idle state (USBSTA.VB USRQ is zero, no VBus is generated).
This interrupt is generated even if the clock is frozen by the FRZCLK bit.
• HSOFI: Host Star t of Frame Interrupt
This bit is set when a SOF is issued by the Host controller. This tr iggers a USB interrupt when HSOFE is one. When using the
host controller in low speed mode, this bit is also set when a keep-alive is sent.
This bit is cleared when the HSOFIC bit is written to one.
• RXRSMI: Upstream Resume Received Interrupt
This bit is set when an Upstream Resume has been received from the Device.
This bit is cleared when the RXRSMIC is written to one.
• RSMEDI: Downstream Resume Sent Interrupt
This bit set when a Downstream Resume has been sent to the Device.
This bit is cleared when the RSMEDIC bit is written to one.
• RSTI: USB Reset Sent Interrupt
This bit is set when a USB Reset has been sent to the device.
This bit is cleared when the RSTIC bit is wri tten to one.
31 30 29 28 27 26 25 24
DMA7INT DMA6INT DMA5INT DMA4INT DMA3INT DMA2INT DMA1INT -
23 22 21 20 19 18 17 16
-------
15 14 13 12 11 10 9 8
P7INT P6INT P5INT P4INT P3INT P2INT P1INT P0INT
76543210
- HWUPI HSOFI RXRSMI RSMEDI RSTI DDISCI DCONNI
719
32072H–AVR32–10/2012
AT32UC3A3
• DDISCI: Device Discon n ec tion Interrupt
This bit is set when the device has been removed from the USB bus.
This bit is cleared when the DDISCIC bit is written to one.
• DCONNI: Device Connection Interrupt
This bit is set when a new device has been connected to the USB bus.
This bit is cleared when the DCONNIC bit is written to one.
720
32072H–AVR32–10/2012
AT32UC3A3
27.8.3.3 Ho st Glob al Int errupt Clear Regis ter
Register Name: UHINTCLR
Access Type: Write-Only
Offset: 0x0408
Read Value: 0x00000000
Writing a one to a bit in this register will clear the corresponding bit in UHINT.
Writing a zero to a bit in this register has no effect.
This bit alw ays reads as zero.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
- HWUPIC HSOFIC RXRSMIC RSMEDIC RSTIC DDISCIC DCONNIC
721
32072H–AVR32–10/2012
AT32UC3A3
27.8.3.4 Ho st Glob al Int errupt Set Reg iste r
Register Name: UHINTSET
Access Type: Write-Only
Offset: 0x040C
Read Value: 0x00000000
Writing a one to a bit in this register will set the corresponding bit in UHINT, what may be useful for test or debug purposes.
Writing a zero to a bit in this register has no effect.
This bit alw ays reads as zero.
31 30 29 28 27 26 25 24
DMA7INTS DMA6INTS DMA5INTS DMA4INTS DMA3INTS DMA2INTS DMA1INTS -
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
- HWUPIS HSOFIS RXRSMIS RSMEDIS RSTIS DDISCIS DCONNIS
722
32072H–AVR32–10/2012
AT32UC3A3
27.8.3.5 Host Global Interrupt Enable Register
Register Name: UHINTE
Access Type: Read-Only
Offset: 0x0410
Reset Value: 0x00000000
• DMAnINTE: DMA Channel n Interrupt Enable
This bit is set when the DMAnINTES bit is written to one. This will enable the DMA Channel n Interrupt (DMAnINT).
This bit is cleared when the DMAnINTEC bit is written to one. This will disable the DMA Channel n Interrupt (DMAnINT).
• PnINTE: Pipe n Inte rrupt Enable
This bit is set when the PnINTES bit is written to one. This will enable the Pipe n Interrupt (PnINT).
This bit is cleared when the PnIN TEC bit is written to one. This will disable the Pipe n Interrupt (PnINT).
• HWUPIE: Host Wake-Up Interrupt Enable
This bit is set when the HWUPIES bit is written to one. This will enable the Host Wake-up Interrupt (HWUPI).
This bit is cleared when the HWUPIEC bit is written to one. This will disable the Host Wake-up Interrupt (HWUPI).
• HSOFIE: Host Start of Frame Interrupt Enable
This bit is set when the HSOFIES bit is written to one. This will enable the Host Start of Frame interrupt (HSOFI).
This bit is cleared when the HSOFIEC bit is written to one. This will disable the Host Start of Frame interrupt (HSOFI).
• RXRSMIE: Upstream Resume Received Interrupt Enable
This bit is set when the RXRSMIES bit is written to one. This will enable the Upstream Resume Received interrupt (RXRSMI).
This bit is cleared when the RXRSMIEC bit is wr itten to one. This will disable the Downstream Resume interrupt (RXRSMI).
• RSMEDIE: Downstream Resume Sent Interrupt Enable
This bit is set when the RSMEDIES bit is written to one. This will enable the Downstream Resume interrupt (RSMEDI).
This bit is cleared when the RSMEDIEC bit is wr itten to one. This will disable the Downstream Resume interrupt (RSMEDI).
• RSTIE: USB Reset Sent Interrupt Enable
This bit is set when the RSTIES bit is written to one. This will enable the USB Reset Sent interrupt (RSTI).
This bit is cleared when the RSTIEC bit is written to one. This will disable the USB Reset Sent interrupt (RSTI).
• DDISCIE: Device Disconnection Interrupt Enable
This bit is set when the DDISCIES bit is written to one. This will enable the Device Disconnection interrupt (DDISCI).
This bit is cleared when the DDISCIEC bit is written to one. This will disable the Device Disconnection interrupt (DDISCI).
• DCONNIE: Device Connection Interrupt Enable
This bit is set when the DCONNIES bit is written to one. This will enable the Device Connection interrupt (DCONNI).
This bit is cleared when the DCONNIEC bit is written to one. This will disable the Device Connection interrupt (DCONNI).
31 30 29 28 27 26 25 24
DMA7INTE DMA6INTE DMA5INTE DMA4INTE DMA3INTE DMA2INTE DMA1INTE -
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
P7INTE P6INTE P5INTE P4INTE P3INTE P2INTE P1INTE P0INTE
76543210
- HWUPIE HSOFIE RXRSMIE RSMEDIE RSTIE DDISCIE DCONNIE
723
32072H–AVR32–10/2012
AT32UC3A3
27.8.3.6 Host Global Interrupt Enable Clear Register
Register Name: UHINTECLR
Access Type: Write-Only
Offset: 0x0414
Read Value: 0x00000000
Writing a one to a bit in this register will clear the corresponding bit in UHINTE.
Writing a zero to a bit in this register has no effect.
This bit alw ays reads as zero.
31 30 29 28 27 26 25 24
DMA7INTEC DMA6INTEC DMA5INTEC DMA4INTEC DMA3INTEC DMA2INTEC DMA1INTEC -
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
P7INTEC P6INTEC P5INTEC P4INTEC P3INTEC P2INTEC P1INTEC P0INTEC
76543210
- HWUPIEC HSOFIEC RXRSMIEC RSMEDIEC RSTIEC DDISCIEC DCONNIEC
724
32072H–AVR32–10/2012
AT32UC3A3
27.8.3.7 Ho st Glob al Int errupt Enable Set Register
Register Name: UHINTESET
Access Type: Write-Only
Offset: 0x0418
Read Value: 0x00000000
Writing a one to a bit in this register will set the corresponding bit in UHINT.
Writing a zero to a bit in this register has no effect.
This bit alw ays reads as zero.
31 30 29 28 27 26 25 24
DMA7INTES DMA6INTES DMA5INTES DMA4INTES DMA3INTES DMA2INTES DMA1INTES -
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
P7INTES P6INTES P5INTES P4INTES P3INTES P2INTES P1INTES P0INTES
76543210
- HWUPIES HSOFIES RXRSMIES RSMEDIES RSTIES DDISCIES DCONNIES
725
32072H–AVR32–10/2012
AT32UC3A3
27.8.3.8 Host Frame Number Register
Register Name: UHFNUM
Access Type: Read/Write
Offset: 0x0420
Reset Value: 0x00000000
• FLENHIGH: Frame Length
In Full speed mode, this field contains the 8 high-order bits of the 16-bit internal frame counter (at 30MHz, counter length is
30000 to ensure a SOF generation every 1 ms).
In High speed mode, this field contains the 8 high-order bits of the 16-bit internal frame counter (at 30MHz, counter length is
3750 to ensure a SOF generation eve ry 125 us).
• FNUM: Frame Number
This field contains the current SOF number.
This field can be written. In this case, the MFNUM field is reset to zero.
• MFNUM: Micro Frame Number
This field contains the current Micro Frame number (can vary from 0 to 7) updated every 125us.
When operating in full-speed mode, this field is tied to zero.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
FLENHIGH
15 14 13 12 11 10 9 8
- - FNUM[10:5]
76543210
FNUM[4:0] MFNUM
726
32072H–AVR32–10/2012
AT32UC3A3
27.8.3.9 Host Address 1 Register
Register Name: UHADDR1
Access Type: Read/Write
Offset: 0x0424
Reset Value: 0x00000000
• UHADDRP3: USB Host Address
This field contains the address of the Pipe3 of the USB Device.
This field is cleared when a USB reset is requested.
• UHADDRP2: USB Host Address
This field contains the address of the Pipe2 of the USB Device.
This field is cleared when a USB reset is requested.
• UHADDRP1: USB Host Address
This field contains the address of the Pipe1 of the USB Device.
This field is cleared when a USB reset is requested.
• UHADDRP0: USB Host Address
This field contains the address of the Pipe0 of the USB Device.
This field is cleared when a USB reset is requested.
31 30 29 28 27 26 25 24
- UHADDRP3
23 22 21 20 19 18 17 16
- UHADDRP2
15 14 13 12 11 10 9 8
- UHADDRP1
76543210
- UHADDRP0
727
32072H–AVR32–10/2012
AT32UC3A3
27.8.3.10 Host Address 2 Register
Register Name: UHADDR2
Access Type: Read/Write
Offset: 0x0428
Reset Value: 0x00000000
• UHADDRP7: USB Host Address
This field contains the address of the Pipe7 of the USB Device.
This field is cleared when a USB reset is requested.
• UHADDRP6: USB Host Address
This field contains the address of the Pipe6 of the USB Device.
This field is cleared when a USB reset is requested.
• UHADDRP5: USB Host Address
This field contains the address of the Pipe5 of the USB Device.
This field is cleared when a USB reset is requested.
• UHADDRP4: USB Host Address
This field contains the address of the Pipe4 of the USB Device.
This field is cleared when a USB reset is requested.
31 30 29 28 27 26 25 24
- UHADDRP7
23 22 21 20 19 18 17 16
- UHADDRP6
15 14 13 12 11 10 9 8
- UHADDRP5
76543210
- UHADDRP4
728
32072H–AVR32–10/2012
AT32UC3A3
27.8.3.11 Pipe Enable/Reset Register
Register Name: UPRST
Access Type: Read/Write
Offset: 0x0041C
Reset Value: 0x00000000
• PRSTn: Pipe n Reset
Writing a one to this bit will reset the Pipe n FIFO.
This resets the endpoint n registers (UPCFGn, UPSTAn, UPCONn) but not the endpoint configuration (ALLOC , PBK, PSIZE,
PTOKEN, PTYPE, PEPNUM, INTFRQ).
All the endpoint mechanism (FIFO counter, reception, transmission, etc.) is reset apart from the Data Toggle management.
The endpoint configuration remains active and the endpoint is still enabled.
Writing a zero to this bit will complete the reset operation and allow to start using the FIFO.
• PENn: Pipe n Enable
Writing a one to this bit will enable the Pipe n.
Writing a zero to this bit will disable the Pipe n, what forces the Pipe n state to inactive and resets the pipe n registers (UPCFGn,
UPSTAn, UPCONn) but not the pipe configuration (ALLOC, PBK, PSIZE).
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
PRST7 PRST6 PRST5 PRST4 PRST3 PRST2 PRST1 PRST0
15 14 13 12 11 10 9 8
--------
76543210
PEN7 PEN6 PEN5 PEN4 PEN3 PEN2 PEN1 PEN0
729
32072H–AVR32–10/2012
AT32UC3A3
27.8.3.12 Pipe n Configuration Register
Register Name: UPCFGn, n in [0..7]
Access Type: Read/Write
Offset: 0x0500 + (n * 0x04)
Reset Value: 0x00000000
• INTFRQ: Pipe Interrupt Request Freq uency
This field contains the maximum value in millisecond of the polling period for an Interrupt Pipe.
This value has no effect for a non-Interrupt Pipe.
This field is cleared upon sending a USB reset.
• BINTERVAL: bInterval parameter for the Bulk-Out/Ping transaction
This field contains the Ping/Bulk-out per iod.
If BINTERVA L>0 and PINGEN=1, one PING token is sent every BINTERVAL micro-frame until it is ACKed by the peripheral.
If BINTERVAL=0 and PINGEN=1, multiple consecutive PING token is sent in the same micro-frame until it is ACKed.
If BINTERVA L>0 and PINGEN=0, one OUT token is sent every BINTERVAL micro-frame until it is ACKed by the peripheral.
If BINTERVA L=0 and PINGEN=0, multiple consecutive OUT token is sent in the same micro-frame until it is ACKed.
This value must be in the range from 0 to 255.
• PINGEN: Ping Enable
This bit is relevant for High-speed Bulk-out transaction only (including the control data stage and the control status stage).
Writing a zero to this bit will disable the ping protocol.
Writing a one to this bit will enable the ping mechanism according to the usb 2.0 standard.
This bit is cleared upon sending a USB reset.
• PEPNUM: Pipe Endpoint Number
This field contains the number of the endpoint targeted by the pipe. This value is from 0 to 15.
This field is cleared upon sending a USB reset.
• PTYPE: Pipe Type
This field contains the pipe type.
31 30 29 28 27 26 25 24
INTFRQ/BINTERVAL
23 22 21 20 19 18 17 16
- - - PINGEN PEPNUM
15 14 13 12 11 10 9 8
- - PTYPE - AUTOSW PTOKEN
76543210
- PSIZE PBK ALLOC -
PTYPE Pipe Type
0 0 Control
730
32072H–AVR32–10/2012
AT32UC3A3
This field is cleared upon sending a USB reset.
• AUTOSW: A u tomatic Switch
This bit is cleared upon sending a USB reset.
1: The automatic bank switching is enabled.
0: The automatic bank switching is disabled.
• PTOKEN: Pipe Token
This field contains the endpoint token.
• PSIZE: Pipe Size
This field contains the size of each pipe bank.
This field is cleared upon sending a USB reset.
• PBK: Pipe Banks
This field contains the number of banks for the pipe.
For control endpoi nts, a single-bank pipe (0b00) should be selected.
This field is cleared upon sending a USB reset.
0 1 Isochronous
10Bulk
1 1 Interrupt
PTOKEN Endpoint Direction
00 SETUP
01 IN
10 OUT
11 reserved
PSIZE Endpoint Size
0 0 0 8 bytes
00116 bytes
01032 bytes
01164 bytes
1 0 0 128 bytes
1 0 1 256 bytes
1 1 0 512 bytes
1 1 1 1024 bytes
PBK Endpoint Banks
0 0 1 (single-bank pipe)
0 1 2 (double-bank pipe)
1 0 3 (triple-bank pipe) if supported (see Table 27-1 on page 624).
11Reserved
PTYPE Pipe Type
731
32072H–AVR32–10/2012
AT32UC3A3
• ALLOC: Pipe Memory Allocate
Writing a one to this bit will allocate the pipe memory.
Writing a zero to this bit will free the pipe memor y.
This bit is cleared when a USB Reset is requested.
Refer to the DPRAM Management chapter for more details.
732
32072H–AVR32–10/2012
AT32UC3A3
27.8.3.13 Pipe n Status Register
Register Name: UPSTAn, n in [0..7]
Access Type: Read-Only
Offset: 0x0530 + (n * 0x04)
Reset Value: 0x00000000
• PBYCT: Pipe Byte Count
This field contains the byte count of the FIFO.
For OUT pipe, incremented after ea ch byte written by the user into the pipe and decremented after each byte sent to the
peripheral.
For IN pipe, incremented after each byte received from the peripheral and decremented after each byte read by the user from
the pipe.
This field may be updated 1 clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt bit.
• CFGOK: Configu ration OK Status
This bit is set/cleared when the UPCFGn.ALLOC bit is set.
This bit is set if the pipe n number of banks (UPCFGn.PBK) and size (UPCFGn.PSIZE) are correct compared to the maximal
allowed number of banks and size for this pipe and to the maximal FIF O size (i.e., th e DPRAM size).
If this bit is cleared, the user should rewrite correct values ot the PBK and PSIZE field in the UPCFGn register.
• RWALL: Read/Write Allowed
For OUT pipe, this bit is set when the current bank is not full, i.e., the software can write further data into the FIFO.
For IN pipe, this bit is set when the current bank is not empty, i.e., the software can read further data from the FIFO.
This bit is cleared otherwise.
This bit is also cleared when the RXSTALL or the PERR bit is one.
• CURRBK: Current Bank
For non-control pipe, this field indicates the number of the current bank.
31 30 29 28 27 26 25 24
- PBYCT[10:4]
23 22 21 20 19 18 17 16
PBYCT[3:0] - CFGOK - RWALL
15 14 13 12 11 10 9 8
CURRBK NBUSYBK - - DTSEQ
76543210
SHORT
PACKETI RXSTALLDI/
CRCERRI OVERFI NAKEDI PERRI TXSTPI/
UNDERFI TXOUTI RXINI
CURRBK Current Bank
00Bank0
733
32072H–AVR32–10/2012
AT32UC3A3
This field may be updated 1 clock cycle after the RWALL bit changes, so the user shall not poll this field as an interrupt bit.
• NBUSYBK: Number of Busy Banks
This field indicates the number of busy bank.
For OUT pipe, this field indicates the number of busy ba nk(s), filled by the user, ready for OUT transfer. When all banks are
busy, this triggers an PnINT interrupt if UPCONn.NBUSYBKE is one.
F or IN pipe, this field indicates the n umber of b usy bank(s) filled b y IN transaction from the De vice . When all banks are free, this
triggers an PnINT interrupt if UPCONn.NBUSYBKE is one.
• DTSEQ: Data Toggle Sequence
This field indicates the data PID of th e current bank.
For OUT pipe, this field indicates the data toggle of the next packet that will be sent.
F or IN pipe, this field indicates the data toggle of the received pac ket stored in the current bank.
• SHORTPACKETI: Short Packet Interrupt
This bit is set when a short packet is received by the host controller (packet length inferior to the PSIZE programmed field).
This bit is cleared when the SHORTPACKETIC bit is written to one.
• RXSTALLDI: Received STALLed Interrupt
This bit is set, for all endpoints but isochronous, when a STALL handshake has been received on the current bank of the pipe.
The Pipe is automatically frozen. This triggers an interrupt if the RXSTALLE bit is one.
This bit is cleared when the RXSTALLDIC bit is written to one.
• CRCERRI: CRC Error Interrupt
This bit is set, for isochronous endpoint, when a CRC error occurs on the current bank of the Pipe. This triggers an interrupt if
the TXSTPE bit is one.
This bit is cleared when the CRCERRIC bit is written to one.
• OVERFI: Overflow Interrupt
This bit is set when the current pipe has received more data than the maximum length of the current pipe. An interrupt is
triggered if the OVERFIE bit is one.
This bit is cleared when the OVERFIC bit is written to one.
• NAKEDI: NAKed Interrupt
This bit is set when a NAK has been receiv ed on the current bank of the pipe. This triggers an interrupt if the NAKEDE bit is one.
01Bank1
1 0 Bank2 if supported (see Table 27-1 on page 624).
11Reserved
NBUSYBK Number of busy bank
0 0 All banks are free.
0 1 1 busy bank
1 0 2 busy banks if supported (see Table 27-1 on page 624 ).
11reserved
DTSEQ Data toggle sequence
00Data0
01Data1
10reserved
11reserved
CURRBK Current Bank
734
32072H–AVR32–10/2012
AT32UC3A3
This bit is cleared when the NAKEDIC bit written to one.
• PERRI: Pipe Error Interrupt
This bit is set when an error occurs on the current bank of the pipe. This triggers an inte rrupt if the PERRE bit is set. Refers to
the UPERRn register to determine the source of the error.
This bit is cleared when the error source bit is cleared.
• TXSTPI: Transmitted SETUP Interrupt
This bit is set, for Control endpoints, when the current SETUP bank is free and can be filled. This triggers an interrupt if the
TXSTPE bit is one.
This bit is cleared when the TXSTPIC bit is wr itten to one.
• UNDERFI: Underflow Interrupt
This bit is set, for isochronous and Interrupt IN/OUT pipe, when an error flow occurs. This triggers an interrupt if the UNDERFIE
bit is one.
This bit is set, for Isochronous or interr upt OUT pipe, when a transaction underflow occurs in the current pipe. (the pipe can’t
send the OUT data pack et in time because the current bank is not ready). A zero-length-packet (ZLP) will be sent instead of.
This bit is set, for Isochronous or interrupt IN pipe, when a transaction flow error occurs in the current pipe. i.e , the current ba nk
of the pipe is not free whereas a new IN USB packet is received. This packet is not stored in the bank. For Interrupt pipe, the
overflowed packet is ACKed to respect the USB standard.
This bit is cleared when the UNDERFIEC bit is written to one.
• TXOUTI: Transmitted OUT Data Interrupt
This bit is set when the current OUT bank is free and can be filled. This triggers an interrupt if the TXOUTE bit is one.
This bit is cleared when the TXOUTIC bit is written to one.
• RXINI: Received IN Data Interrupt
This bit is set when a new USB message is store d in th e current bank of the pipe. This triggers an interrupt if the RXINE bit is
one.
This bit is cleared when the RXINIC bit is wr itten to one.
735
32072H–AVR32–10/2012
AT32UC3A3
27.8.3.14 Pipe n Status Clear Register
Register Name: UPSTAnCLR, n in [0..7]
Access Type: Write-Only
Offset: 0x0560 + (n * 0x04)
Read Value: 0x00000000
Writing a one to a bit in this register will clear the corresponding bit in UPSTAn.
Writing a zero to a bit in this register has no effect.
This bit alw ays reads as zero.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
SHORT
PACKETIC
RXSTALLDI
C/
CRCERRIC OVERFIC NAKEDIC - TXSTPIC/
UNDERFIC TXOUTIC RXINIC
736
32072H–AVR32–10/2012
AT32UC3A3
27.8.3.15 Pipe n Status Set Regist er
Register Name: UPSTAnSET, n in [0..7]
Access Type: Write-Only
Offset: 0x0590 + (n * 0x04)
Read Value: 0x00000000
Writing a one to a bit in this register will set the corresponding bit in UPSTAn, what may be useful for test or debug purposes.
Writing a zero to a bit in this register has no effect.
This bit alw ays reads as zero.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
- - - NBUSYBKS - - - -
76543210
SHORT
PACKETIS RXSTALLDIS/
CRCERRIS OVERFIS NAKEDIS PERRIS TXSTPIS/
UNDERFIS TXOUTIS RXINIS
737
32072H–AVR32–10/2012
AT32UC3A3
27.8.3.16 Pipe n Control Regis ter
Register Name: UPCONn, n in [0..7]
Access Type: Read-Only
Offset: 0x05C0 + (n * 0x04)
Reset Value: 0x00000000
• RSTDT: Reset Data Toggle
This bit is set when the RSTDTS bit is written to one. This will reset the Data Toggle to its initial value f or the current Pipe.
This bit is cleared when proceed.
• PFREEZE: Pipe Freeze
This bit is set when the PFREEZES bit is written to one or when the pipe is not configured or when a STALL handshake has
been received on this Pipe or when an error occurs on the Pipe (PERR is one) or when (INRQ+1) In requests have been
processed or when after a Pipe reset (UPRST.PRSTn rising) or a Pipe Enable (UPRST.PEN rising). This will Freeze the Pipe
requests generation.
This bit is cleared when the PFREEZEC bit is written to one. This will enable the Pipe request generation.
• PDISHDMA: Pipe Interrupts Disable HDMA Request Enable
See the UECONn.EPDISHDMA bit description.
• FIFOCON: FIFO Control
For OUT and SETUP Pipe:
This bit is set when the current bank is free, at the same time than TXOUTI or TXSTPI.
This bit is cleared when the FIFOCONC bit is written to one. This will send the FIFO data and switch the bank.
For IN Pipe:
This bit is set when a new IN message is stored in the current bank, at the same time than RXINI.
This bit is cleared when the FIFOCONC bit is written to one. This will free the current bank and switch to the next bank.
• NBUSYBKE: Number of Busy Banks Interrupt Enable
This bit is set when the NBUSYBKES bit is written to one.This will enable the Transmitted IN Data interrupt (NBUSYBKE).
This bit is cleared when the NBUSYBKEC bit is written to one. This will disable the Transmitted IN Data interr upt (NBUSYBKE).
• SHORTPACKETIE: Short Packet Interrupt Enable
This bit is set when the SHORTPACKETES bit is written to one. This will enable the Transmitted IN Data IT (SHORTPACKETIE).
This bit is cleared when the SHORTPACKETEC bit is written to one. This will disable the Transmitted IN Data IT
(SHORTPACKETE).
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
- - - - - RSTDT PFREEZE PDISHDMA
15 14 13 12 11 10 9 8
- FIFOCON - NBUSYBKE - - - -
76543210
SHORT
PACKETIE RXSTALLDE/
CRCERRE OVERFIE NAKEDE PERRE TXSTPE/
UNDERFIE TXOUTE RXINE
738
32072H–AVR32–10/2012
AT32UC3A3
• RXSTALLDE: Received STALLed Interrupt Enable
This bit is set when the RXSTALLDES bit is written to one. This will enable the Transmitted IN Data interr upt (RXSTALLDE).
This bit is cleared when the RXSTALLDEC bit is written to one. This will disable the Transmitte d IN Data interrupt
(RXSTALLDE).
• CRCERRE: CRC Error Interrupt Enable
This bit is set when the CRCERRES bit is written to one. This will enable the Transmitted IN Data interrupt (CRCERRE).
This bit is cleared when the CRCERREC bit is wr itten to one. This will disable the Transmitted IN Data interrupt (CRCERRE).
• OVERFIE: Overflow Interrupt Enable
This bit is set when the OVERFIES bit is written to one. This will enable the Transmitted IN Data interrupt (OVERFIE).
This bit is cleared when the OVERFIEC bit is written to one. This will disable the Transmitted IN Data interrupt (OVERFIE).
• NAKEDE: NAKed Interrupt Enable
This bit is set when the NAKEDES bit is written to one. This will enable the Transmitted IN Data interrupt (NAKEDE).
This bit is cleared when the NAKEDEC bit is written to one. This will disable the Transmitted IN Data interrupt (NAKEDE).
• PERRE: Pipe Error Interrupt Enable
This bit is set when the PERRES bit is written to one. This will enable the Transmi tted IN Data interrupt (PERRE).
This bit is cleared when the PERREC bit is written to one. This will disable the Transmitted IN Data interrupt (PERRE).
• TXSTPE: Transmitted SETUP Interrupt Enable
This bit is set when the TXSTPES bit is written to one. This will enable the Transmitted IN Data interrupt (TXSTPE).
This bit is cleared when the TXSTPEC bit is written to one. This will disable the Transmitted IN Data interrupt (TXSTPE).
• UNDERFIE: Underflow Interrupt Enable
This bit is set when the UNDERFIES bit is written to one. This will enable the Transmitted IN Data interrupt (UNDERFIE).
This bit is cleared when the UNDERFIEC bit is written to one. This will disable the Tr ansmitted IN Data interrupt (UNDERFIE).
• TXOUTE: Transmitted OUT Data Interrupt Enable
This bit is set when the TXOUTES bit is written to one. This will enable the Transmitted IN Data interrupt (TXOUTE).
This bit is cleared when the TXOUTEC bit is written to one. This will disable the Transmitted IN Data interrupt (TXOUTE).
• RXINE: Received IN Data Interrupt Enable
This bit is set when the RXINES bit is written to one. This will enable the Transmitted IN Data interrupt (RXINE).
This bit is cleared when the RXINEC bit is written to one. This will disable the Transmitted IN Data interrupt (RXINE).
739
32072H–AVR32–10/2012
AT32UC3A3
27.8.3.17 Pipe n Control Clear Register
Register Name: UPCONnCLR, n in [0..7]
Access Type: Write-Only
Offset: 0x0620 + (n * 0x04)
Read Value: 0x00000000
Writing a one to a bit in this register will clear the corresponding bit in UPCONn.
Writing a zero to a bit in this register has no effect.
This bit alw ays reads as zero.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
- - - - - - PFREEZEC PDISHDMAC
15 14 13 12 11 10 9 8
- FIFOCONC - NBUSYBKEC ----
76543210
SHORT
PACKETIEC RXSTALLDEC/
CRCERREC OVERFIEC NAKEDEC PERREC TXSTPEC/
UNDERFIEC TXOUTEC RXINEC
740
32072H–AVR32–10/2012
AT32UC3A3
27.8.3.18 Pipe n Control Set Register
Register Name: UPCONnSET, n in [0..7]
Access Type: Write-Only
Offset: 0x05F0 + (n * 0x04)
Read Value: 0x00000000
Writing a one to a bit in this register will set the corresponding bit in UPCONn.
Writing a zero to a bit in this register has no effect.
This bit alw ays reads as zero.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
- - - - - RSTDTS PFREEZES PDISHDMAS
15 14 13 12 11 10 9 8
---
NBUSYBKES ----
76543210
SHORT
PACKETIES RXSTALLDES/
CRCERRES OVERFIES NAKEDES PERRES TXSTPES/
UNDERFIES TXOUTES RXINES
741
32072H–AVR32–10/2012
AT32UC3A3
27.8.3.19 Pipe n IN Request Registe r
Register Name: UPINRQn, n in [0..7]
Access Type: Read/Write
Offset: 0x0650 + (n * 0x04)
Reset Value: 0x00000000
• INMODE: IN Request Mode
Writing a one to this bit will allow the USBB to perform infinite IN requests when the Pipe is not frozen.
Writing a zero to this bit will perform a pre-defined number of IN requests. This number is the INRQ field.
• INRQ: IN Request Number before Freeze
This field contains the number of IN transactions before the USBB freezes the pipe. The USBB will perform (INRQ+1) IN
requests before to freeze the Pipe. This counter is automatically decreased by 1 each time a IN request has been successfully
performed.
This register has no effect when the INMODE bit is one (infinite IN requests generation till the pipe is not frozen).
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
-------INMODE
76543210
INRQ
742
32072H–AVR32–10/2012
AT32UC3A3
27.8.3.20 Pipe n Error Register
Register Name: UPERRn, n in [0..7]
Access Type: Read/Write
Offset: 0x0680 + (n * 0x04)
Reset Value: 0x00000000
• COUNTER: Error Counter
This field is incremented each time an error occurs (CRC16, TIMEOUT, PID, DATAPID or DATATGL).
This field is cleared when receiving a good usb packet without any error.
When this field reaches 3 (i.e., 3 consecutive errors), this pipe is automatically frozen (UPCONn.PFREEZE is set).
Writi ng 0b00 to this field will clear the counter.
• CRC16: CRC16 Error
This bit is set when a CRC16 error has been detected.
Writing a zero to this bit will clear the bit.
Writing a one to this bit has no effect.
• TIMEOUT: Time-Out Error
This bit is set when a Time-Out error has been detected.
Writing a zero to this bit will clear the bit.
Writing a one to this bit has no effect.
•PID: PID Error
This bit is set when a PID error has been detected.
Writing a zero to this bit will clear the bit.
Writing a one to this bit has no effect.
• DATAPID: Data PID Error
This bit is set when a Data PID error has been detected.
Writing a zero to this bit will clear the bit.
Writing a one to this bit has no effect.
• DATATGL: Data Toggle Error
This bit is set when a Data Toggle error has been detected.
Writing a zero to this bit will clear the bit.
Writing a one to this bit has no effect.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
- COUNTER CRC16 TIMEOUT PID DATAPID DATATGL
743
32072H–AVR32–10/2012
AT32UC3A3
27.8.3.21 Host DMA Channel n Next Descr iptor Address Register
Register Name: UHDMAnNEXTDESC, n in [1..7 ]
Access Type: Read/Write
Offset: 0x0710 + (n - 1) * 0x10
Reset Value: 0x00000000
Same as Section 27.8.2.17.
31 30 29 28 27 26 25 24
NXTDESCADDR[31:24]
23 22 21 20 19 18 17 16
NXTDESCADDR[23:16]
15 14 13 12 11 10 9 8
NXTDESCADDR[15:8]
76543210
NXTDESCADDR[7:4] - - - -
744
32072H–AVR32–10/2012
AT32UC3A3
27.8.3.22 Host DMA Channel n HSB Address Register
Register Name: UHDMAnADDR, n in [1..7]
Access Type: Read/Write
Offset: 0x0714 + (n - 1) * 0x10
Reset Value: 0x00000000
Same as Section 27.8.2.18.
31 30 29 28 27 26 25 24
HSBADDR[31:24]
23 22 21 20 19 18 17 16
HSBADDR[23:16]
15 14 13 12 11 10 9 8
HSBADDR[15:8]
76543210
HSBADDR[7:0]
745
32072H–AVR32–10/2012
AT32UC3A3
27.8.3.23 USB Host DMA Channel n Control Register
Register Name: UHDMAnCONTROL, n in [1..7]
Access Type: Read/Write
Offset: 0x0718 + (n - 1) * 0x10
Reset Value: 0x00000000
Same as Section 27.8.2.19.
(just replace the IN endpoint term by OUT endpoint, and vice-versa)
31 30 29 28 27 26 25 24
CHBYTELENGTH[15:8]
23 22 21 20 19 18 17 16
CHBYTELENGTH[7:0]
15 14 13 12 11 10 9 8
--------
76543210
BURSTLOC
KEN DESCLD
IRQEN EOBUFF
IRQEN EOTIRQEN DMAENDEN BUFFCLOSE
INEN LDNXTCHD
ESCEN CHEN
746
32072H–AVR32–10/2012
AT32UC3A3
27.8.3.24 USB Host DMA Channel n Status Register
Register Name: UHDMAnSTATUS, n in [1..7]
Access Type: Read/Write
Offset: 0x071C + (n - 1) * 0x10
Reset Value: 0x00000000
Same as Section 27.8.2.20.
31 30 29 28 27 26 25 24
CHBYTECNT[15:8]
23 22 21 20 19 18 17 16
CHBYTECNT[7:0]
15 14 13 12 11 10 9 8
--------
76543210
-DESCLD
STA EOCHBUFFS
TA EOTSTA - - CHACTIVE CHEN
747
32072H–AVR32–10/2012
AT32UC3A3
27.8.4 USB Pipe/Endpoint n FIFO Data Register (USBFIFOnDATA)
The application has access to the physical DPRAM reserved for the Endpoint/Pipe through a
64KB virtual address space. The application can access anywhere in the virtual 64KB segment
(linearly or fixedly) as the DPRAM Fifo address increment is fully handled by hardware. Byte,
half-word and word access are supported. Data should be access in a big-endian way.
For instance, if th e ap p lication wants to write into the Endpoint/Pipe3, it can access anyw here in
the USBFIFO3DATA HSB segment address. i.e : an ac cess to the 0x30000 offset, is strictly
equivalent to an access to the 0x3FFFC offset.
Note that the virtual address space size (64KB) has nothing to do with the Endpoint/Pipe size.
Disabling the USBB (by writing a zero to the USBE bit) does not reset the DPRAM.
748
32072H–AVR32–10/2012
AT32UC3A3
27.9 Module Configuration
The specific configuration for the USBB instance is listed in the following tables. The module bus
clocks listed here are connected to the system bus clocks. Please refer to the Power Manager
chapter for details.
Table 27-7. Module Clock Name
Module name Clock name Clock name
USBB CLK_USBB_HSB CLK_USBB_PB
Table 27-8. Register Reset Values
Register Reset Value
UVERS 0x00000320
UFEATURES 0x00014478
UADDRSIZE 0x00001000
UNAME1 0x48555342
UNAME2 0x004F5447
749
32072H–AVR32–10/2012
AT32UC3A3
28. Timer/Counter (TC)
Rev: 2.2.3.3
28.1 Features •Three 16-bit Timer Counter channels
•A wide range of functions inc l ud ing:
– Frequency measurement
– Event counting
– Interval measurement
– Pulse generation
–Delay timing
– Pulse width modulation
– Up/down capabilities
•Each channel is user-configurable and contai ns :
– Thr ee external clock inputs
– Five internal clock inputs
– Two multi-purpose input/o utput signals
•Internal interrupt signal
•Two global registers that act on all three TC channels
28.2 Overview The Timer Counter (TC) includes three identical 16-bit Timer Counter channels.
Each channel can be independently programmed to perform a wide range of functions including
frequency measurement, event counting, interval measurement, pulse generation, delay timing,
and pulse width modulation.
Each channel has three external clock inputs, five internal clock inputs, an d two multi-purpos e
input/output signals which can be configured by the user. Each channel drives an internal inter-
rupt signal which can be programmed to generate processor interrupts.
The TC block has two global registers which act upon all three TC channels.
The Block Control Register (BCR) allows the three channels to be started simultaneously with
the same instruction.
The Block Mode Register (BMR) defines the external clock inputs for each channel, allowing
them to be chained.
750
32072H–AVR32–10/2012
AT32UC3A3
28.3 Block Diagram
Figure 28-1. TC Block Diagram
28.4 I/O Lines Description
28.5 Product Dependencies
In order to use t his modu le, othe r p arts o f th e syst em must be conf igu red cor re ctly, as de scr ibed
below.
28.5.1 I/O Lines The pins used for interfacing the compliant externa l devices may be multiplexed with I/O lines.
The user must fi rst p rog ram t he I/ O Cont ro ller to assign th e TC p ins t o the ir p eri phe ra l funct ions.
I/O
Co n t r o l l e r
TC2XC2S
INT0
INT1
INT2
TIOA0
TIOA1
TIOA2
TIOB0
TIOB1
TIOB2
XC2
TCLK0
TCLK1
TCLK2
TCLK0
TCLK1
TCLK2
TCLK0
TCLK1
TCLK2
TIOA1
TIOA2
TIOA0
TIOA2
TIOA1
Interrupt
Controller
CLK0
CLK1
CLK2
A0
B0
A1
B1
A2
B2
Timer Count er
TIOB
TIOA
TIOB
SYNC
TIMER_CLOCK1
TIOA
SYNC
SYNC
TIOA
TIOB
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
XC1
XC0
XC0
XC2
XC1
XC0
XC1
XC2
Timer/Counter
Channel 2
Timer/Counter
Channel 1
Timer/Counter
Channel 0
TC1XC1S
TC0XC0S
TIOA0
Table 28-1. I/O Lines Descrip tion
Pin Name Description Type
CLK0-CLK2 External Clock Input Input
A0-A2 I/O Line A Input/Output
B0-B2 I/O Line B Input/Output
751
32072H–AVR32–10/2012
AT32UC3A3
28.5.2 Power Management
If the CPU enters a sleep mode that disables clocks used by the TC, the TC will stop functioning
and resume operation after the system wakes up from sleep mode.
28.5.3 Clocks The clock for the TC bus interface (CLK_TC) is generated by the Power Manager. This clock is
enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the
TC before disabling the clock, to avoid freezing the TC in an undefined state.
28.5.4 Interrupts The TC interrupt request line is connected to the interrupt controller. Using the TC interrupt
requires the interrupt controller to be programmed first.
28.5.5 Debug Operation
The Timer Counter clocks are frozen during debug operation, unless the OCD system keeps
peripherals runnin g in debug operation.
28.6 Functional Description
28.6.1 TC DescriptionThe three channels of the Timer Counter are independent and identical in operation. The regis-
ters for channel programming are listed in Figure 28-3 on page 766.
28.6.1.1 Ch ann el I/O Signal s
As described in Figure 28-1 on page 750, each Channel has the following I/O signals.
28.6.1.2 16-bit counter
Each channel is organized around a 16-bit counter. The valu e of the counter is incremented at
each positive edge of the selected clock. When the counter has reached the value 0xFFFF and
passes to 0x0000, an overflo w occurs and the Cou nter Overflo w Status bit in th e Chan nel n Sta-
tus Register (SRn.COVFS) is set.
The current value of the counter is accessible in real time by reading the Channel n Counter
Value Register (CVn). The counter can be reset by a trigger. In this case, the counter value
passes to 0x0000 on the next valid edge of the selected clock.
Table 28-2. Channel I/O Signals Description
Block/Channel Signal Name Description
Channel Signal
XC0, XC1, XC2 External Clock Inputs
TIOA Capture mode: Timer Counter Input
Waveform mode: Timer Counter Output
TIOB Capture mode: Timer Counter Input
Waveform mode: Timer Counter Input/Output
INT Interrupt Sign al Output
SYNC Synchronization Input Signal
752
32072H–AVR32–10/2012
AT32UC3A3
28.6.1.3 Clock selection
At block level, input clock signals of each channel can eithe r be connected to the exter nal inputs
TCLK0, TCLK1 or TCLK2, or be connected to the configurable I/O signa ls A0, A1 or A2 for
chaining by writing to the BMR register. See Figure 28-2 on page 752.
Each channel can independe ntly select an internal or external clock source for its counter:
• Internal clock signals: TIMER_CLOCK1, TIMER_CLOCK2, TIMER_CLOCK3,
TIMER_CLOCK4, TIMER_CL OCK5. See the Mo dule Configur ation Chap ter f or details about
the connection of these clock sources.
• External clock signals: XC0, XC1 or XC2. See the Module Configuration Chapter for details
about the connect ion of these clock sources.
This selection is made by the Clock Selection field in the Channel n Mode Register
(CMRn.TCCLKS).
The selected clock can be inverted wi th the Clock Invert bit in CMRn (CMRn.CLKI). This allows
counting on the opposite edges of the clock.
The burst function allows the clock to be va lidated when an external signal is high. The Burst
Signal Selection field in the CMRn register (CMRn.BURST) defines this signal.
Note: In all cases, if an external clock is used, the duration of each of its levels must be longer than the
CLK_TC period. The external clock frequency must be at least 2.5 times lower than the CLK_TC.
Figure 28-2. Clock Selection
28.6.1.4 Clock controlThe clock of each counter can be controlled in two different ways: it can be enabled/disabled
and started/stopped. See Figure 28-3 on pag e 753.
TIMER_CLOCK5
XC2
TCCLKS
CLKI
BURST
1
Selected
Clock
XC1
XC0
TIMER_CLOCK4
TIMER_CLOCK3
TIMER_CLOCK2
TIMER_CLOCK1
753
32072H–AVR32–10/2012
AT32UC3A3
• The clock can be enabled or disabled by the user by writing to the Counter Clock
Enable/Disable Command bits in the Channel n Clock Control Register (CCRn.CLKEN and
CCRn.CLKDIS). In Capt ure mode it can be disab led by an RB load e vent if the Counter Cloc k
Disable with RB Loading bit in CMRn is written to one (CMRn.LDBDIS). In W aveform mode,
it can be disabled by an RC Compare event if the Counter Clock Disable with RC Compare
bit in CMRn is written to one (CMRn.CPCDIS). When disabled, the start or the stop actions
have no effect: only a CLKEN command in CCRn can re -enable the clock. When the clock is
enabled, the Clock Enabling Status bit is set in SRn (SRn.CLKSTA).
• The clock can also be started or stopped: a trigger (software, synchro, external or compare)
always starts the clock. In Capture mod e the cloc k can be stopped b y an RB load event if th e
Counter Cloc k Stopp ed with RB Loadin g bit in CMRn is written to one (CMRn.LDBSTOP). In
Waveform mode it can be stopped by an RC compare event if the Counter Clock Stopped
with RC Compare bit in CMRn is written to one (CMRn.CPCSTOP). The start and the stop
commands have effect only if the clock is enabled.
Figure 28-3. Clock Control
28.6.1.5 TC operating modes
Each channel can independently operate in two different modes:
• Capture mode provides measurement on signals.
• Waveform mode provides wave generation.
The TC operating mode selection is done by writing to the Wave bit in the CCRn register
(CCRn.WAVE).
In Capture mode, TIOA and TIOB are configured as inputs.
In Waveform mode, TIOA is always configured to be an output and TIOB is an output if it is not
selected to be the external trigger.
QS
R
S
R
Q
CLKSTA CLKEN CLKDIS
Stop
Event
Disable
Counter
Clock
Selected
Clock Trigger
Event
754
32072H–AVR32–10/2012
AT32UC3A3
28.6.1.6 Trigger A trigger resets the counter and starts the counter clock. Three types of triggers are common to
both modes, and a f ourth external trigger is available to each mode.
The following trigge rs are common to both modes:
• Software Trigger: each channel has a software trigger, available by writing a one to the
Software Trigger Command bit in CCRn (CCRn.SWTRG).
• SYNC: each channel has a synchronizat ion signal SYNC . When asserted, this signal has the
same effect as a softwa re trigger. The SYNC signals of all channels are asserted
simultaneously by writing a one to the Synchro Command bit in the BCR register
(BCR.SYNC).
• Compare RC Trigger: RC is implemented in each channe l and can provide a trigger when the
counter value matches the RC value if the RC Compare Trigger Enable bit in CMRn
(CMRn.CPCTRG) is written to one.
The channel can also be configured to have an external trigger. In Capture mode, the external
trigger signa l can be selected betwee n TIOA and TIOB. In Waveform mode, an ext ernal event
can be programmed to be one of the following signals: TIOB, XC0, XC1, or XC2. This external
event can then be programmed to perform a trigger by writing a one to the External Event Trig-
ger Enable bit in CMRn (CMRn.ENETRG).
If an external trigger is used, the duration of the pulses must be longer than the CLK_TC period
in order to be detected.
Regardless of the trigger used, it will be taken into account at the following active edge of the
selected clock. This means that the counter value can be read differently from zero just after a
trigger, especially when a low frequency signal is selected as the clock.
28.6.2 Capture Operating Mode
This mode is entered by writing a zero to the CMRn.WAVE bit.
Capture mode allows the TC channel to perform measurements such as pulse timing, fre-
quency, period, duty cycle and phase on TIOA and TIOB signals which are considered as
inputs.
Figure 28 -4 on pag e 756 shows the configuration of the TC channel when programmed in Cap-
ture mode.
28.6.2.1 Ca pt ur e re gis te rs A and B
Registers A and B (RA and RB) ar e used as capture registers. This mean s that they can be
loaded with the counter value when a programmable event occurs on the signal TIOA.
The RA Loading Selection f ield in CMRn (CMRn. LDRA) defines the TIOA edge f or the loading of
the RA register, and the RB Loading Selection field in CMRn (CMRn.LDRB) defines the TIOA
edge for the load ing of the RB register.
RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since
the last loading of RA.
RB is loaded only if RA has been loaded since the last trigger or the last loading of RB.
Loading RA or RB before the read of the last value loaded sets the Load Overrun Status bit in
SRn (SRn.LOVRS). In this case, the old value is overwritten.
755
32072H–AVR32–10/2012
AT32UC3A3
28.6.2.2 Trigger conditions
In addition t o the SYNC signa l, the soft ware tr igger and the RC co mpare t rigger, an ext ernal tr ig-
ger can be defined.
The TIOA or TIOB External Trigger Selection bit in CMRn (CM Rn.ABETRG) selects TIOA or
TIOB input signal as an external trigge r. The External Trigger Edge Selection bit in CMRn
(CMRn.ETREDG) defines the edge (rising, falling or both) detected to generate an external trig-
ger. If CMRn.ETRGEDG is zero (none), the external trigger is disabled.
756
32072H–AVR32–10/2012
AT32UC3A3
Figure 28-4. Capture M od e
TIMER_CLOCK1
XC0
XC1
XC2
TCCLKS
CLKI
QS
R
S
R
Q
CLKSTA CLKEN CLKDIS
BURST
TIOB
Capture
Register A Compare RC =
16-bit
Counter
ABETRG
SWTRG
ETRGEDG CPCTRG
IMR
Trig
LDRBS
LDRAS
ETRGS
SR
LOVRS
COVFS
SYNC
1
MTIOB
TIOA
MTIOA
LDRA
LDBSTOP
If RA is not Loaded
or RB is Loaded If RA is Loaded
LDBDIS
CPCS
INT
Edge
Det ect or
LDRB
CLK OVF
RESET
Timer/Counter Channel
Edge
Detector
Edge
Detector
Capture
Register B
Register C
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
757
32072H–AVR32–10/2012
AT32UC3A3
28.6.3 Waveform Operating Mode
Waveform operating mode is entered by writing a one to the CMRn.WAVE bit.
In Waveform operating mode the TC channel generates one or two PWM signals with the same
frequency and independently programmable duty cycles, or generates different types of one-
shot or repetitive pulses.
In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used
as an external event.
Figure 28-5 on pag e 758 shows the configuration of the TC channel when programmed in
Waveform operating mode.
28.6.3.1 Waveform selection
Depending on the Waveform Selection field in CMRn (CMRn.WAVSEL), the behavior of CVn
varies.
With any selection, RA, RB and RC can all be used as compare registers.
RA Compare is used to co ntro l th e T IO A out put, RB Comp ar e is used to cont rol t he TIOB outp ut
(if correctly configured) and RC Compare is used to control TIOA and/or TIOB outputs.
758
32072H–AVR32–10/2012
AT32UC3A3
Figure 28-5. Waveform Mode
TCCLKS
CLKI
QS
R
S
R
Q
CLKSTA CLKEN CLKDIS
CPCDIS
BURST
TIOB
Register A
Compare RC =
CPCSTOP
16-bit
Counter
EEVT
EEVTEDG
SYNC
SWTRG
ENETRG
WAVSEL
IMR
Trig
ACPC
ACPA
AEEVT
ASWTRG
BCPC
BCPB
BEEVT
BSWTRG
TIOA
MTI OA
TIOB
MTIOB
CPAS
COVFS
ETRGS
SR
CPCS
CPBS
CLK
OVF
RESET
Output ControllerOutput Contr oller
INT
1
Ed g e
Det e ct o r
Timer/Counter Channel
TIMER_CLOCK1
XC0
XC1
XC2
WAVSEL
Register B Register C
Compare RB =Compare RA =
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
759
32072H–AVR32–10/2012
AT32UC3A3
28.6.3.2 WAVSEL = 0When CMRn.WAVSEL is zero, the value of CVn is incremented from 0 to 0xFFFF. Once
0xFFFF has been reached, the value of CVn is reset. Incrementation of CVn starts again and
the cycle continues. See Figure 28-6 on page 759.
An external event trigger or a software trigger can reset the value of CVn. It is important to note
that the trigger may occur at any time. See Figure 28-7 on page 760.
RC Compare canno t be programmed to gene rate a trigger in this co nfiguration. At the same
time, RC Compare can sto p the counter clock (CMRn.CPCSTOP = 1) an d/or disabl e the counter
clock (CMRn.CPCDI S = 1).
Figure 28-6. WAVSEL= 0 Without Trigger
Time
Counter Value
RC
RB
RA
TIOB
TIOA
Counter cleared by compare match with
0xFFFF
0xFFFF
Waveform Examples
760
32072H–AVR32–10/2012
AT32UC3A3
Figure 28-7. WAVSEL= 0 With Trigger
28.6.3.3 WAVSEL = 2When CMRn.WAVSEL is two, the value of CVn is incremented from zero to the value of RC,
then automatically reset on a RC Compare. Once the value of CVn has been reset, it is then
incremented and so on. See Figure 28-8 on page 761.
It is important to note that CVn can be reset at any time by an external event or a software trig-
ger if both are programmed correctly. See Figure 28-9 on page 761.
In addition, RC C ompare can stop the counter clock (CMRn.CPC STOP) and/or disable the
counter clock (CMRn.CPCDIS = 1).
Time
Counter Value
RC
RB
RA
TIOB
TIOA
Counter cleared by compare match with 0xFFFF
0xFFFF
Waveform Examples
Counter cleared by trigger
761
32072H–AVR32–10/2012
AT32UC3A3
Figure 28-8. WAVSEL = 2 Without Trigger
Figure 28-9. WAVSEL = 2 With Trigger
28.6.3.4 WAVSEL = 1When CMRn.WAVSEL is one, the value of CVn is incremented from 0 to 0xFFFF. Once 0xFFFF
is reached, the value of CVn is decreme nted to 0, then re-incremented to 0xFFFF and so on.
See Figure 28-10 on page 762.
Time
Counter Value
RC
RB
RA
TIOB
TIOA
Counter cleared by compare match
with RC
0xFFFF
Waveform Examples
Time
Counter V alue
R
C
R
B
R
A
TIOB
TIOA
Counter cleared by compare match with RC
0xFFFF
Waveform Examples
Counter cleared by trigger
762
32072H–AVR32–10/2012
AT32UC3A3
A trigger such as an ex tern al even t or a sof tware trigger can modify CVn at any time. If a trigger
occurs while CVn is incrementing, CVn then decrements. If a trigger is received while CVn is
decrementing, CVn then increments. See Figure 28-11 on page 762.
RC Compare cannot be pr ogrammed to generate a trigger in this configuration.
At the same time, RC Compare can stop the counter clock (CMRn.CPCSTOP = 1) and/or dis-
able the counter clock (CMRn.CPCDIS = 1).
Figure 28-10. WAVSEL = 1 Without Trigger
Figure 28-11. WAVSEL = 1 With Trigger
Time
Counter Value
RC
RB
RA
TIOB
TIOA
Counter decremented by compare match
with 0xFFFF
0xFFFF
Waveform Examples
Time
Counter Value
TIOB
TIOA
Counter decremented by compare match with 0xFFFF
0xFFFF
Waveform Examples
Counter decremented by trigger
RC
RB
RA
Counter incremented by trigger
763
32072H–AVR32–10/2012
AT32UC3A3
28.6.3.5 WAVSEL = 3When CMRn.W AVSEL is three, the value of CVn is incremen ted from zero to RC. Once RC is
reached, the value of CVn is decremented to zero, then re-incremented to RC and so on. See
Figure 28-12 on page 763.
A trigger such as an ex tern al even t or a sof tware trigger can modify CVn at any time. If a trigger
occurs while CVn is incrementing, CVn then decrements. If a trigger is received while CVn is
decrementing, CVn then increments. See Figure 28-13 on page 764.
RC Compare can stop the counter clock (CMRn.CPCSTOP = 1) and/or di sable the count er clock
(CMRn.CPCDIS = 1).
Figure 28-12. WAVSEL = 3 Without Trigger
Time
Counter Value
RC
RB
RA
TIOB
TIOA
Counter cleared by compare match with RC
0xFFFF
Waveform Examples
764
32072H–AVR32–10/2012
AT32UC3A3
Figure 28-13. WAVSEL = 3 With Trigger
28.6.3.6 External event/trigger conditions
An external event can be programmed to be detected on one of the clo ck sources (XC0, XC1,
XC2) or TIOB. The external event selected can then be used as a trigger.
The External Event Selection field in CM Rn (CMRn.EEVT) selects the external trigger. The
External Event Edge Selection field in CMRn (CMRn.EEVTEDG) defines the trigger edge for
each of the possible external triggers (rising, falling or both). If CMRn.EEVTEDG is written to
zero, no external event is defined.
If TIOB is defined as an external event signal (CMRn.EEVT = 0), TIOB is no longer used as an
output and the compare register B is not used to generate waveforms and subsequently no
IRQs. In this case the TC channel can only generate a waveform on TIOA.
When an external event is defined, it can be used as a trigger by writing a one to the
CMRn.ENETRG bit.
As in Capture mode, the SYNC signal and the sof tware t rigge r ar e also ava ilable as tri gge rs. RC
Compare can also be used as a trigger depending on the CMRn.WAVSEL field.
28.6.3.7 Output controller
The output contr oller defines the output level ch anges on TIOA and TIOB followin g an event.
TIOB control is used only if TIOB is defined as output (not as an external event).
The following events control TIOA and TIOB:
• software trigger
• external event
• RC compare
RA compare controls TIOA and RB compare controls TIOB. Each of these events can be pro-
grammed to set, clear or toggle the output as defined in the following fields in CMRn:
• RC Compare Effect on TIOB (CMRn.BCPC)
Time
Counter Value
TIOB
TIOA
Counter decremented by compare match
with RC
0xFFFF
Waveform Examples
RC
RB
RA
Counter decremented by trigger
Counter incremented by trigger
765
32072H–AVR32–10/2012
AT32UC3A3
• RB Compare Effect on TIOB (CMRn.BCPB)
• RC Compare Effect on TIOA (CMRn.ACPC)
• RA Compare Effect on TIOA (CMRn.ACPA)
766
32072H–AVR32–10/2012
AT32UC3A3
28.7 User Interface
Table 28-3. TC Register Memory Map
Offset Register Register Name Access Reset
0x00 Channel 0 Control Register CCR0 Write-only 0x00000000
0x04 Channel 0 Mode Register CMR0 Read/Write 0x00000000
0x10 Channel 0 Counter Valu e CV0 Read-only 0x00000000
0x14 Channel 0 Register A RA0 Read/Write(1) 0x00000000
0x18 Channel 0 Register B RB0 Read/Write(1) 0x00000000
0x1C Channel 0 Register C RC0 Read/Write 0x00000000
0x20 Channel 0 Status Register SR0 Read-only 0x00000000
0x24 Interrupt Enable Register IER0 Write-only 0x00 000000
0x28 Channel 0 Interr upt Disable Register IDR0 Write-only 0x00000000
0x2C Channel 0 Interrupt Mask Register IMR0 Read-only 0x00000000
0x40 Channel 1 Control Register CCR1 Write-only 0x00000000
0x44 Channel 1 Mode Register CMR1 Read/Write 0x00000000
0x50 Channel 1 Counter Valu e CV1 Read-only 0x00000000
0x54 Channel 1 Register A RA1 Read/Write(1) 0x00000000
0x58 Channel 1 Register B RB1 Read/Write(1) 0x00000000
0x5C Channel 1 Register C RC1 Read/Write 0x00000000
0x60 Channel 1 Status Register SR1 Read-only 0x00000000
0x64 Channel 1 Interrupt Enable Register IER1 Write-only 0x00000000
0x68 Channel 1 Interr upt Disable Register IDR1 Write-only 0x00000000
0x6C Channel 1 Interrupt Mask Register IMR1 Read-only 0x00000000
0x80 Channel 2 Control Register CCR2 Write-only 0x00000000
0x84 Channel 2 Mode Register CMR2 Read/Write 0x00000000
0x90 Channel 2 Counter Valu e CV2 Read-only 0x00000000
0x94 Channel 2 Register A RA2 Read/Write(1) 0x00000000
0x98 Channel 2 Register B RB2 Read/Write(1) 0x00000000
0x9C Channel 2 Register C RC2 Read/Write 0x00000000
0xA0 Channel 2 Status Register SR2 Read-only 0x00000000
0xA4 Channel 2 Interrupt Enable Register IER2 Write-only 0x00000000
0xA8 Channel 2 Interrupt Disable Register IDR2 Write-only 0x00000000
0xAC Channel 2 Interrupt Mask Register IMR2 Read-only 0x00000000
0xC0 Block Control Register BCR Write-only 0x00000000
0xC4 Block Mode Register BMR Read/Write 0x00000000
0xF8 F eatures Register FEATURES Read-only -(2)
0xFC Version Register VERSION Read-only -(2)
767
32072H–AVR32–10/2012
AT32UC3A3
Notes: 1. Read-only if CMRn.WAVE is zero.
2. The reset values are device specific. Please refer to the Module Configuration section at the
end of this chapter.
768
32072H–AVR32–10/2012
AT32UC3A3
28.7.1 Channel Control Register
Name: CCR
Access Type: Write-only
Offset: 0x00 + n * 0x40
Reset Value: 0x00000000
• SWTRG: Software Trigger Command
1: Writing a one to this bit will perform a software trigger: the counter is reset and the clock is started.
0: Writing a ze ro to this bi t ha s no ef fect.
• CLKDIS: Counter Cloc k D i s able Command
1: Writing a one to thi s bit will disable the clock.
0: Writing a ze ro to this bi t ha s no ef fect.
• CLKEN: Counter Clock Enab le Command
1: Writing a one to this bit will enable the clock if CLKDIS is not one.
0: Writing a ze ro to this bi t ha s no ef fect.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
- - - - - SWTRG CLKDIS CLKEN
769
32072H–AVR32–10/2012
AT32UC3A3
28.7.2 Channel Mode Register: Capture Mode
Name: CMR
Access Type: Read/Write
Offset: 0x04 + n * 0x40
Reset Value: 0x00000000
• LDRB: RB Loading Sel ection
• LDRA: RA Loading Sel ection
•WAVE
1: Capture mode is disabled (Waveform mode is enabled).
0: Capture mode is enabled.
• CPCTRG: RC Compare Trigger Enable
1: RC Compare resets the counter and starts the counter clock.
0: RC Compare has no effect on the counter and its clock.
• ABETRG: TIOA or TIOB External Trigger Selection
1: TIOA is used as an extern al trigger.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
- - - - LDRB LDRA
15 14 13 12 11 10 9 8
WAVE CPCTRG - - - ABETRG ETRGEDG
76543210
LDBDIS LDBSTOP BURST CLKI TCCLKS
LDRB Edge
0 none
1 rising edge of TIOA
2 falling edge of TIOA
3 each edge of TIOA
LDRA Edge
0 none
1 rising edge of TIOA
2 falling edge of TIOA
3 each edge of TIOA
770
32072H–AVR32–10/2012
AT32UC3A3
0: TIOB is used as an external tr igger.
• ETRGEDG: External Trigger Edge Selection
• LDBDIS: Counter Clock Disable with RB Loading
1: Counter clock is disabled when RB load ing occurs.
0: Counter clock is not disabled when RB loadi ng occurs.
• LDBSTOP: Counter Clock Stopped with RB Loading
1: Counter clock is stopped when RB loading occurs.
0: Counter clock is not stopped when RB loading occurs.
• BURST: Burst Signal Selection
• CLKI: Clock Invert
1: The counter is incremented on falling edge of the clock.
0: The counter is incremented on rising edge of the clock.
• TCCLKS: Clock Selection
ETRGEDG Edge
0 none
1 ri s ing edge
2 falling edge
3 each edge
BURST Burst Signal Selection
0 The clock is not gated by an external signal
1 XC0 is ANDed with the selected clock
2 XC1 is ANDed with the selected clock
3 XC2 is ANDed with the selected clock
TCCLKS Clock Selected
0TIMER_CLOCK1
1TIMER_CLOCK2
2TIMER_CLOCK3
3TIMER_CLOCK4
4TIMER_CLOCK5
5XC0
6XC1
7XC2
771
32072H–AVR32–10/2012
AT32UC3A3
28.7.3 Channel Mode Register: Waveform Mode
Name: CMR
Access Type: Read/Write
Offset: 0x04 + n * 0x40
Reset Value: 0x00000000
• BSWTRG: Software Trigger Effect on TIOB
• BEEVT: External Event Effect on TIOB
31 30 29 28 27 26 25 24
BSWTRG BEEVT BCPC BCPB
23 22 21 20 19 18 17 16
ASWTRG AEEVT ACPC ACPA
15 14 13 12 11 10 9 8
WAVE WAVSEL ENETRG EEVT EEVTEDG
76543210
CPCDIS CPCSTOP BURST CLKI TCCLKS
BSWTRG Effect
0 none
1set
2clear
3 toggle
BEEVT Effect
0 none
1set
2clear
3 toggle
772
32072H–AVR32–10/2012
AT32UC3A3
• BCPC: RC Compare Effect on TIOB
• BCPB: RB Compare Effect on TIOB
• ASWTRG: Software Trigger Effect on TIOA
• AEEVT: External Event Effect on TIOA
• ACPC: RC Compare Effect on TIOA
BCPC Effect
0 none
1set
2clear
3 toggle
BCPB Effect
0 none
1set
2clear
3 toggle
ASWTRG Effect
0 none
1set
2clear
3 toggle
AEEVT Effect
0 none
1set
2clear
3 toggle
ACPC Effect
0 none
1set
2clear
3 toggle
773
32072H–AVR32–10/2012
AT32UC3A3
• ACPA: RA Compare Effect on TIOA
•WAVE
1: Waveform mode is enabled.
0: Waveform mode is disabled (Capture mode is enabled).
• WAVSEL: W aveform Selection
• ENETRG: External Event Trigger Enable
1: The external event resets the counter and starts the counter clock.
0: The e xternal event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA
output.
• EEVT: External Event Selection
Note: 1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates wav eforms and subse-
quently no IRQs.
• EEVTEDG: External Event Edge Selection
• CPCDIS: Counter Clock Disable with RC Compare
1: Counter clock is disabled when coun ter reaches RC.
0: Counter clock is not disabled when counter reaches RC.
ACPA Effect
0 none
1set
2clear
3 toggle
WAVSEL Effect
0 UP mode without automatic trigger on RC Compare
1 UPDOWN mode without automatic trigger on RC Compare
2 UP mode with automatic trigger on RC Compare
3 UPDOWN mode with automatic trigger on RC Compare
EEVT Signal selected as external event TIOB Direction
0 TIOB input(1)
1 XC0 output
2 XC1 output
3 XC2 output
EEVTEDG Edge
0none
1 rising ed ge
2 falling edge
3 each edge
774
32072H–AVR32–10/2012
AT32UC3A3
• CPCSTOP: Counter Clock Stopped with RC Compare
1: Counter clock is stopped when counter reaches RC.
0: Counter clock is not stopped when counter reaches RC.
• BURST: Burst Signal Selection
• CLKI: Clock Invert
1: Counter is incremented on falling edge of the clock.
0: Counter is incremented on rising edge of the clock.
• TCCLKS: Clock Selection
BURST Burst Signal Selection
0 The clock is not gated by an external signal.
1 XC0 is ANDed with the selected clock.
2 XC1 is ANDed with the selected clock.
3 XC2 is ANDed with the selected clock.
TCCLKS Clock Selected
0TIMER_CLOCK1
1TIMER_CLOCK2
2TIMER_CLOCK3
3TIMER_CLOCK4
4TIMER_CLOCK5
5XC0
6XC1
7XC2
775
32072H–AVR32–10/2012
AT32UC3A3
28.7.4 Channel Counter Value Register
Name: CV
Access Type: Read-only
Offset: 0x10 + n * 0x40
Reset Value: 0x00000000
•CV: Counter Value
CV contains the counter value in real time.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
CV[15:8]
76543210
CV[7:0]
776
32072H–AVR32–10/2012
AT32UC3A3
28.7.5 Channel Register A
Name: RA
Access Type: Read-only if CMRn.WAVE = 0, Read/Write if CMRn.WAVE = 1
Offset: 0x14 + n * 0X40
Reset Value: 0x00000000
• RA: Register A
RA contains the Register A value in real time.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
RA[15:8]
76543210
RA[7:0]
777
32072H–AVR32–10/2012
AT32UC3A3
28.7.6 Channel Register B
Name: RB
Access Type: Read-only if CMRn.WAVE = 0, Read/Write if CMRn.WAVE = 1
Offset: 0x18 + n * 0x40
Reset Value: 0x00000000
• RB: Register B
RB contains the Register B value in real time.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
RB[15:8]
76543210
RB[7:0]
778
32072H–AVR32–10/2012
AT32UC3A3
28.7.7 Channel Register C
Name: RC
Access Type: Read/Write
Offset: 0x1C + n * 0x40
Reset Value: 0x00000000
• RC: Register C
RC contains the Register C value in real time.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
RC[15:8]
76543210
RC[7:0]
779
32072H–AVR32–10/2012
AT32UC3A3
28.7.8 Channel Status Register
Name: SR
Access Type: Read-only
Offset: 0x20 + n * 0x40
Reset Value: 0x00000000
Note: Reading the Status Register will also clear the interrupt bit for the corresponding interrupts.
• MTIOB : TIOB Mirror
1: TIOB is high. If CMRn.WAVE is zero, this means that TIOB pin is high. If CMRn.WAVE is one, this means that TIOB is driven
high.
0: TIOB is low. If CMRn.WAVE is zero, this means that TIOB pin is low. If CMRn.WAVE is one, this means that TIOB is driven
low.
• MTIOA: TIOA Mirror
1: TIOA is high. If CMRn.WAVE is zero , this means that TIOA pin is high. If CMRn.W AVE is one, this means that TIOA is driven
high.
0: TIOA is low. If CMRn.WAVE is zero, this means that TIOA pin is low. If CMRn.WAVE is one, this means that TIOA is driven
low.
• CLKSTA: Clock Enabling Status
1: This bit is set when the clock is enabled.
0: This bit is cleared when the clock is disabled.
• ETRGS: External Trigger Status
1: This bit is set when an external trigger has occurred.
0: This bit is cleared when the SR register is read.
• LDRBS: RB Loading Stat us
1: This bit is set when an RB Load has occurred and CMRn.WAVE is zero.
0: This bit is cleared when the SR register is read.
• LDRAS: RA Loading Stat us
1: This bit is set when an RA Load has occurred and CMRn.WAVE is zero.
0: This bit is cleared when the SR register is read.
• CPCS: RC Compare Status
1: This bit is set when an RC Compare has occurred.
0: This bit is cleared when the SR register is read.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
- - - - - MTIOB MTIOA CLKSTA
15 14 13 12 11 10 9 8
--------
76543210
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS
780
32072H–AVR32–10/2012
AT32UC3A3
• CPBS: RB Compare Status
1: This bit is set when an RB Compare has occurred and CMRn.WAVE is one.
0: This bit is cleared when the SR register is read.
• CPAS: RA Compare Status
1: This bit is set when an RA Compare has occurred and CMRn.WAVE is one.
0: This bit is cleared when the SR register is read.
• LOVRS: Load Overrun Status
1: This bit is set when RA or RB have been loaded at least twice without any read of the corresponding register and
CMRn.WAVE is zero.
0: This bit is cleared when the SR register is read.
• COVFS: Counter Overflow Status
1: This bit is set when a counter overflow has occurred.
0: This bit is cleared when the SR register is read.
781
32072H–AVR32–10/2012
AT32UC3A3
28.7.9 Channel Interrupt Enable Register
Name: IER
Access Type: Write-only
Offset: 0x24 + n * 0x40
Reset Value: 0x00000000
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will set the corresponding bit in IMR.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS
782
32072H–AVR32–10/2012
AT32UC3A3
28.7.10 Channel Interrupt Disable Register
Name: IDR
Access Type: Write-only
Offset: 0x28 + n * 0x40
Reset Value: 0x00000000
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will clear the corresponding bit in IMR.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS
783
32072H–AVR32–10/2012
AT32UC3A3
28.7.11 Channel Interrupt Mask Register
Name: IMR
Access Type: Read-only
Offset: 0x2C + n * 0x40
Reset Value: 0x00000000
0: The corresponding interr upt is disabled.
1: The corresponding interrupt is enabled.
A bit in this register is cleared when the corresponding bit in IDR is wr itten to one.
A bit in this register is set when the corresponding bit in IER is written to one.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS
784
32072H–AVR32–10/2012
AT32UC3A3
28.7.12 Block Control Register
Name: BCR
Access Type: Write-only
Offset: 0xC0
Reset Value: 0x00000000
• SYNC: Synchro Command
1: Writing a one to this bit asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
0: Writing a ze ro to this bi t ha s no ef fect.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
-------SYNC
785
32072H–AVR32–10/2012
AT32UC3A3
28.7.13 Block Mode Register
Name: BMR
Access Type: Read/Write
Offset: 0xC4
Reset Value: 0x00000000
• TC2XC2S: External Clock Signal 2 Selection
• TC1XC1S: External Clock Signal 1 Selection
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
- - TC2XC2S TC1XC1S TC0XC0S
TC2XC2S Signal Connected to XC2
0TCLK2
1none
2TIOA0
3TIOA1
TC1XC1S Signal Connected to XC1
0TCLK1
1none
2TIOA0
3TIOA2
786
32072H–AVR32–10/2012
AT32UC3A3
• TC0XC0S: External Clock Signal 0 Selection
TC0XC0S Signal Connected to XC0
0TCLK0
1none
2TIOA1
3TIOA2
787
32072H–AVR32–10/2012
AT32UC3A3
28.7.14 Featu re s Reg i st er
Name: FEATURES
Access Type: Read-only
Offset: 0xF8
Reset Value: -
• BRPBHSB: Bridge type is PB to HSB
1: Bridge type is PB to HSB.
0: Bridge type is not PB to HSB.
• UPDNIMPL: Up/down is implemented
1: Up/down counter capability is implemented.
0: Up/down counter capability is not implemented.
• CTRSIZE: Counter size
This field indicates the size of the counter in bits.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
-------
15 14 13 12 11 10 9 8
- - - - - - BRPBHSB UPDNIMPL
76543210
CTRSIZE
788
32072H–AVR32–10/2012
AT32UC3A3
28.7.15 Version Register
Name: VERSION
Access Type: Read-only
Offset: 0xFC
Reset Value: -
• VARIANT: Variant number
Reserved. No functionality associated.
• VERSION: Version number
Version number of the module. No functionality associated.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
---- VARIANT
15 14 13 12 11 10 9 8
- - - - VERSION[11:8]
76543210
VERSION[7:0]
789
32072H–AVR32–10/2012
AT32UC3A3
28.8 Module Configuration
The specific configuration for each TC instance is listed in the following tables.The module bus
clocks listed here are connected to the system bus clocks according to the table in the Power
Manager section.
28.8.1 Clock Connections
Each Timer/Counte r channel can independe ntly select an interna l or ext ernal clo ck source fo r its
counter:
Table 28-4. Module Clock Name
Module name Clock name
TC0 CLK_TC0
TC1 CLK_TC1
Table 28-5. Timer/Counte r In te rn al Clock Connect ions
Name Connection
TIMER_CLOCK1 32 KHz clock
TIMER_CLOCK2 PBA Clock / 2
TIMER_CLOCK3 PBA Clock / 8
TIMER_CLOCK4 PBA Clock / 32
TIMER_CLOCK5 PBA Clock / 128
790
32072H–AVR32–10/2012
AT32UC3A3
29. Analog-to-Digital Converter (ADC)
Rev: 2.0.0.1
29.1 Features •Integrated multiplexer offering up to eight independent analog inputs
•Individual enable and disable of each channel
•Hardware or software trigger
– External trigger pin
–Timer counter outputs (corresponding TIOA trigger)
•Peripheral DMA Controller support
•Possibility of ADC timings configuration
•Sleep mode and con version sequencer
– Automatic wake up on trigger and ba ck to sleep mode after conversi on s of all enabled
channels
29.2 Overview The Analog-to- Digital Converter (ADC) is based on a Successive Approximation Register (S AR)
10-bit ADC. It also integrates an 8-to-1 analog multiplexer, making possible the analog-to-digital
conversions of 8 analog lines. The conversions extend from 0V to VDDANA.
The ADC supports an 8-bit or 10-bit resolution mode, and conversion results are reported in a
common register for all channels, as well as in a channel-dedicated register. Software trigger,
external trigger on risin g edge of the TRIGGER pin, or intern al triggers from timer counter out -
put(s) are configurable.
The ADC also integr ates a sleep mode and a co nversion sequen cer and connects with a Periph-
eral DMA Controller channel. These features reduce both power consumption and processor
intervention.
Finally, the user can configure ADC timings, such as startup time and sample & hold time.
791
32072H–AVR32–10/2012
AT32UC3A3
29.3 Block Diagram
Figure 29-1. ADC Block Diagram
29.4 I/O Lines Description
29.5 Product Dependencies
In order to use t his modu le, othe r p arts o f th e syst em must be conf igu red cor re ctly, as de scr ibed
below.
29.5.1 I/O Lines The TRIGG E R pin may be sh ar ed with ot he r pe rip h er al func t ion s thr o ug h th e I/O Con tro lle r.
Table 29-1. ADC Pins Description
Pin Name Description
VDDANA Analog pow er supply
AD[0] - AD[7] Analog input channels
TRIGGER External trigger
AD-
AD-
AD-
Dedicated
Analog
Inputs
AD-
AD-
AD-
Analog Inputs
Multiplexed
With I/O lines
GND
VDDANA
TRIGGER
Trigger
Selection
VREF
Successive
Approximation
Register
Analog-to-Digital
Converter
User
Interface
Control
Logic
ADC
Timer
Counter
Channels
ADC Interrupt Interrupt
Controller
Peripheral
DMA
Controller
High Speed
Bus (HSB)
Peripheral Bridge
Peripheral Bus
(PB)
I/O
Controller
792
32072H–AVR32–10/2012
AT32UC3A3
29.5.2 Power Management
In sleep mode, the ADC clock is automatically stopped after each conversion. As the logic is
small and the ADC cell can be put into sleep mode, the Power Manager has no effect on the
ADC behavior.
29.5.3 Clocks The clock for the ADC bus inter face (CLK _ADC) is ge ner ated by t he Power Ma nager . This clock
is enabled at reset, and can be disabled in t he Power Ma nager. It is r ecommended to di sable the
ADC before disabling the clock, to avoid freezing the ADC in an undefined state.
The CLK_ADC clock frequency must be in line with the ADC characteritics. Refer to Electrical
Characteristics section for details.
29.5.4 Interrupts The ADC interrupt request line is connected to the interrup t controller. Using the ADC interrupt
requires the interrupt controller to be programmed first.
29.5.5 Analog Inputs The analog input pins can be multiplexed with I/O lines. In this case, the assignment of the ADC
input is automatically done as soon as the corresponding I/O is configured through the I/O con-
toller. By default, after reset, the I/O line is configured as a logic input.
29.5.6 Timer TriggersTimer Counters may or may not be used as hardware triggers depending on user requirements.
Thus, some or all of the timer counters may be non-connected.
29.6 Functional Description
29.6.1 Analog-to-digital Conversion
The ADC uses the ADC Clock to perfor m conversi ons. Conver ting a si ngle anal og value to a 10-
bit digital data requires sample and hold clock cycles as defined in the Sample and Hold Time
field of the Mode Register (MR.SHTIM) and 10 ADC Clock cycles. The ADC Clock frequency is
selected in the Prescaler Rate Selection field of the MR register (M R. PRESCA L) .
The ADC Clock range is between CLK_ADC/2, if the PRESCAL field is 0, an d CL K_ ADC/ 128, if
the PRESCAL field is 63 (0 x3 F). The PRESCAL f ield m ust be wr itten in o rd er t o provide an ADC
Clock frequency according to the parameters given in the Electrical Character istics chapter.
29.6.2 Conversion Reference
The conversion is perf orme d o n a full r ange be twee n 0 V an d the r efer ence volt age connect ed to
VDDANA. Analog inpu t values betw een t hese voltages are converted to digital values based on
a linear conversion.
29.6.3 Conversion Resolution
The ADC support s 8-bit or 10-b it reso luti ons. Th e 8- bit sele ct ion is pe rf ormed by writ ing a one to
the Resolution bit in the MR re gister (MR.LOWRES). By default, after a reset, the resolution is
the highest and the Converted Data field in the Channel Data Registers (CDRn.DATA) is fully
used. By writing a one to the LOWRES bit, the ADC switches in the lowest resolution and the
conversion results can be read in the eight lowest signific ant bits of the Ch annel Dat a Registers
(CDRn). The two highest bits of the DATA field in the corresponding CDRn register will be read
793
32072H–AVR32–10/2012
AT32UC3A3
as zero. The two highest bits of the Last Data Conver te d fiel d in th e Last Conve rted Data Regi s-
ter (LCDR.LDATA) will be read as zero too.
Moreover, when a Peri pher al DMA ch ann el is conne cted to t he ADC, a 10-bi t r esolut ion se ts t he
transfer request size to 16-bit. Writing a one to the LOWRES bit automatically switches to 8-bit
data transfers. In this case, the destination buffers are optimized.
29.6.4 Conversion Results
When a conversion is complete d, the resulting 10 -bit digital value is stored in the CDR register of
the current channel and in the LCDR register. Channels are enabled by writing a one to the
Channel n Enable bit (CHn) in the CHER register.
The corresponding channel End of Conversion bit in the Status Register (SR.EOCn) and the
Data Ready bit in the SR register (SR.DRDY) are set. In the case of a connected Peripheral
DMA channel, DRDY rising triggers a data transfer request. In any case, either EOC or DRDY
can trigger an inte rrupt.
Reading one of the CDRn registers clears the corresponding EOC bit. Reading LCDR clears the
DRDY bit and the EOC bit cor responding to the last converted channel.
Figure 29-2. EOCn and DRDY Flag Behavior
Read LCDR
Write CR
With START=1
Read CDRn
Write CR
With START=1
CHn(CHSR)
EOCn(SR)
DRDY(SR)
Conversion Time Conversion Time
794
32072H–AVR32–10/2012
AT32UC3A3
If the CDR register is not read before further incoming data is converted, the corresponding
Overrun Error bit in the SR register (SR.OVREn) is set.
In the same way, new data converted when DRDY is high sets the General Overrun Error bit in
the SR register (SR.GOVRE).
The OVREn and GOVRE bits are automatically cleared when the SR register is read.
Figure 29-3. GOVRE and OVREn Flag Behavior
Warning: If the corresponding channel is disabled during a conversion or if it is disabled and
then reenabled during a conversion, its associated data and its corresponding EOC and OVRE
flags in SR are unpredictable.
Read SR
Data C
Data C
Data B
Data B
Data A
Data AUndefined Data
Undefined Data
Undefined Data
LCDR
CRD0
CH1(CHSR)
CH0(CHSR)
TRIGGER
CRD1
EOC0(SR)
EOC1(SR)
GOVRE(SR)
DRDY(ASR)
OVRE0(SR)
Read CDR0
Read CDR1
Conversion
Conversion
Conversion
795
32072H–AVR32–10/2012
AT32UC3A3
29.6.5 Conversion Triggers
Conversions of the active analog channels are started with a software or a hardware trigger. The
software trigger is provided by writing a one to the START bit in the Control Register
(CR.START).
The hardware trigger can be one of the TIOA outputs of the Timer Counter channels, or the
external trigger input of the ADC (TRIGGER). The hardware trigger is selected with the Trigger
Selection field in the Mode Register (MR.TRIGSEL). The selected hardware trigger is enabled
by writing a one to the Trigger Enable bit in the Mode Register (MR.TRGEN).
If a hardware trigger is selected, the start of a conversion is detected at each rising edge of the
selected signal. I f one of the TIOA outputs is sele cted, th e corr esponding Timer Counter cha nnel
must be programmed in Waveform Mode.
Only one start comman d is necessar y to initiat e a conversion seq uence on all the ch ann els. The
ADC hardware logic automatically performs the conversions on the active channels, then waits
for a new req uest. The Channel Enable (CHER) and Channel Disable (CHDR) Registers enable
the analog channels to be enabled or disabled independently.
If the ADC is used with a Peripheral DMA Controller, only the transfers of converted data from
enabled channels are performed and the resulting data buffers should be interpreted
accordingly.
Warning: Enabling hardware triggers does not disable the software trigger functionality. Thus, if
a hardware trigger is selected, the start of a con version can be initiated eith er by the hardware or
the software trigger.
29.6.6 Sleep Mode and Conversion Sequencer
The ADC Sleep Mode ma ximi zes powe r savin g by automatically deactivating the ADC when it is
not being used for co nversio ns. Sleep Mode is select ed by wr iting a on e to the Sleep Mode b it in
the Mode Register (MR.SLEEP).
The SLEEP mode is a utomatically managed by a conversion sequencer, which can automati-
cally process the conversions of all channels at lowest power consumption.
When a start conversion request occurs, the ADC is automatically activated. As the analog cell
requires a start-up t ime, the lo gic waits during this ti me and starts the conversion on the enabled
channels. When all conversio ns are complet e, the ADC is d eactivated u ntil the n ext trigge r. Trig-
gers occurring during the sequence are not taken into account.
The conversion sequencer allows automatic processing with minimum processor intervention
and optimized power consumption. Conversion sequences can be performed periodically using
a Timer/Counter output. The periodic acquisition of several samples can be pro cessed automat-
ically without any intervention of the processor thanks to the Peripheral DMA Controller.
Note: The reference voltage pins always remain connected in normal mode as in sleep mode.
796
32072H–AVR32–10/2012
AT32UC3A3
29.6.7 ADC Timings Each ADC has its own minimal startup time that is defined through the Start Up Time field in the
Mode Register (MR.STARTUP). This startup time is given in the Electrical Characteristics
chapter.
In the same way, a minimal sample and hold time is necessary for the ADC to guarantee the
best converted final value between two channels selection. This time has to be defined through
the Sample and Hold Time field in the Mode Register (MR.SHTIM). This time dep ends on the
input impedance of t he analog input , but also on the output im pedance of the d river providing the
signal to the analog input, as there is no input buffer amplifier.
29.6.8 Conversion Performances
For performance an d electrical characteristics of the ADC, see the Electrica l Characteristics
chapter.
797
32072H–AVR32–10/2012
AT32UC3A3
29.7 User Interface
Note: 1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter.
Table 29-2. ADC Register Memory Map
Offset Register Name Access Reset State
0x00 Control Register CR Write-only 0x00000000
0x04 Mode Register MR Read/Write 0x00000000
0x10 Channel Enable Register CHER Write-only 0x00000000
0x14 Channel Disable Register CHDR Write-only 0x00000000
0x18 Channel Status Register CHSR Read-only 0x00000000
0x1C Status Register SR Read-only 0x000C 0000
0x20 Last Converted Data Register LCDR Read-only 0x000000 00
0x24 Interrupt Enable Register IER Write-only 0x00000000
0x28 Interrupt Disable Register IDR Write-only 0x00000000
0x2C Interrupt Mask Register IMR Read-only 0x00000000
0x30 Channel Data Register 0 CDR0 Read-only 0x00000000
... ...(if implemented) ... ... ...
0x4C Channel Data Register 7(if implemented) CDR7Read-only 0x00000000
0xFC Version Register VERSION Read-only - (1)
798
32072H–AVR32–10/2012
AT32UC3A3
29.7.1 Control Register
Name: CR
Access Type: Write-only
Offset: 0x00
Reset Value: 0x00000000
• START: Start Con version
Writi ng a one to this bit will begin an analog-to- digital conversion.
Writing a zero to this bit has no effect.
This bit always reads zero.
• SWRST : Software Reset
Writing a one to this bit will reset the ADC.
Writing a zero to this bit has no effect.
This bit always reads zero.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
––––––STARTSWRST
799
32072H–AVR32–10/2012
AT32UC3A3
29.7.2 Mode Register
Name: MR
Access Type: Read/Write
Offset: 0x04
Reset Value: 0x00000000
• SHTIM: Sample & Hold Time
Sample & Hold Time = (SHTIM+3) / ADCClock
• STARTUP: Start Up Time
Startup Time = (STARTUP+1) * 8 / ADCClock
This Time should respect a minimal value. Refer to Electrical Characteristics section for details.
• PRESCAL: Prescaler Rate Selection
ADCClock = CLK_ADC / ( (PRESCAL+1) * 2 )
• SLEEP: Sleep Mode
1: Sleep Mode is selected.
0: Nor mal Mode is selected.
• LOWRES: Resolution
1: 8-bit resolution is selected.
0: 10-bit resolution is selected.
• TRGSEL: Trigger Selection
• TRGEN: Trigge r Enable
1: The hardware trigger selected by the TRGSEL field is enabled.
0: The hardware triggers are disabled. Starting a con version is only possib l e by softwa re.
31 30 29 28 27 26 25 24
–––– SHTIM
23 22 21 20 19 18 17 16
–STARTUP
15 14 13 12 11 10 9 8
PRESCAL
76543210
– – SLEEP LOWRES TRGSEL TRGEN
TRGSEL Selected TRGSEL
0 0 0 Internal Trigger 0, depending of chip integration
0 0 1 Internal Trigger 1, depending of chip integration
0 1 0 Internal Trigger 2, depending of chip integration
0 1 1 Internal Trigger 3, depending of chip integration
1 0 0 Internal Trigger 4, depending of chip integration
1 0 1 Internal Trigger 5, depending of chip integration
1 1 0 External trigger
800
32072H–AVR32–10/2012
AT32UC3A3
29.7.3 Channel Enable Register
Name: CHER
Access Type: Write-only
Offset: 0x10
Reset Value: 0x00000000
• CHn: Channel n Enable
Writi ng a one to these bits will set the correspon ding bit in CHSR.
Writing a zero to these bits has no effect.
These bits always read a zero.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
801
32072H–AVR32–10/2012
AT32UC3A3
29.7.4 Channel Disable Register
Name: CHDR
Access Type: Write-only
Offset: 0x14
Reset Value: 0x00000000
• CHn: Channel n Disable
Writing a one to these bits will clear the corresponding bit in CHSR.
Writing a zero to these bits has no effect.
These bits always read a zero.
Warning: If the corresponding channel is disabled during a conversion or if it is disabled then reenabled during a conv ersion, its
associated data and its corresponding EOC and OVRE flags in SR are unpredictable.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
802
32072H–AVR32–10/2012
AT32UC3A3
29.7.5 Channel Status Register
Name: CHSR
Access Type: Read-only
Offset: 0x18
Reset Value: 0x00000000
• CHn: Channel n Status
These bits are set when the corresponding bits in CHER is written to one.
These bits are cleared when the corresponding bits in CHDR is written to one.
1: The corresponding channel is enabled.
0: The corresponding channel is disabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
––––––––
76543210
CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0
803
32072H–AVR32–10/2012
AT32UC3A3
29.7.6 Status Register
Name: SR
Access Type: Read-only
Offset: 0x1C
Reset Value: 0x000C0000
• RXBUFF: RX Buffer Full
This bit is set when the Buffer Full signal fro m the Peripheral DMA is active.
This bit is cleared when the Buffer Full signal from the Receive Peripheral DMA is inactive .
• ENDRX: End of RX Buffer
This bit is set when the End Receive signal from the P e ripheral DMA is active .
This bit is cleared when the End Receive signal from the Peripheral DMA is inactive.
• GOVRE: General Overrun Error
This bit is set when a General Overrun Error has occurred.
This bit is cleared when the SR register is read.
1: At least one General Overrun Error has occurred since the last read of the SR register.
0: No General Overrun Error occurred since the last read of the SR register.
• DRDY: Data Ready
This bit is set when a data has been converted and is available in the LCDR register.
This bit is cleared when the LCDR register is read.
0: No data has been converted since the last read of the LCDR register.
1: At least one data has been converted and is available in the LCDR register.
• OVREn: Overrun Error n
These bits are set when an overrun error on the corresponding channel has occurred (if implemen ted).
These bits are cleared when the SR register is read.
0: No overrun error on the corresponding channel (if implemented) since the last read of SR.
1: There has been an overrun error on the corresponding channel (if implemented) since the last read of SR.
• EOCn: End of Conversion n
These bits are set when the corresponding conversion is complete.
These bits are cleared when the corresponding CDR or LCDR reg isters are read.
0: Corresponding analog channel (if implemented) is disabled, or the conversion is not finished.
1: Corresponding analog channel (if implemen ted) is enabled and conversion is complete.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––RXBUFFENDRXGOVREDRDY
15 14 13 12 11 10 9 8
OVRE7 OVRE6 OVRE5 OVRE4 OVRE3 OVRE2 OVRE1 OVRE0
76543210
EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0
804
32072H–AVR32–10/2012
AT32UC3A3
29.7.7 Las t Co nverted Dat a Re gi st er
Name: LCDR
Access Type: Read-only
Offset: 0x20
Reset Value: 0x00000000
• LDATA: Last Data Converted
The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion
is completed.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––– LDATA[9:8]
76543210
LDATA[7:0]
805
32072H–AVR32–10/2012
AT32UC3A3
29.7.8 Interrupt Enable Register
Name: IER
Access Type: Write-only
Offset: 0x24
Reset Value: 0x00000000
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will set the corresponding bit in IMR.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––RXBUFFENDRXGOVREDRDY
15 14 13 12 11 10 9 8
OVRE7 OVRE6 OVRE5 OVRE4 OVRE3 OVRE2 OVRE1 OVRE0
76543210
EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0
806
32072H–AVR32–10/2012
AT32UC3A3
29.7.9 Interrupt Disable Register
Name: IDR
Access Type: Write-only
Offset: 0x28
Reset Value: 0x00000000
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will clear the corresponding bit in IMR.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––RXBUFFENDRXGOVREDRDY
15 14 13 12 11 10 9 8
OVRE7 OVRE6 OVRE5 OVRE4 OVRE3 OVRE2 OVRE1 OVRE0
76543210
EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0
807
32072H–AVR32–10/2012
AT32UC3A3
29.7.10 Interrupt Mask Register
Name: IMR
Access Type: Read-only
Offset: 0x2C
Reset Value: 0x00000000
0: The corresponding interr upt is disabled.
1: The corresponding interrupt is enabled.
A bit in this register is cleared when the corresponding bit in IDR is wr itten to one.
A bit in this register is cleared when the corresponding bit in IER is written to one.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––RXBUFFENDRXGOVREDRDY
15 14 13 12 11 10 9 8
OVRE7 OVRE6 OVRE5 OVRE4 OVRE3 OVRE2 OVRE1 OVRE0
76543210
EOC7 EOC6 EOC5 EOC4 EOC3 EOC2 EOC1 EOC0
808
32072H–AVR32–10/2012
AT32UC3A3
29.7.11 Channel Data Register
Name: CDRx
Access Type: Read-only
Offset: 0x2C-0x4C
Reset Value: 0x00000000
• DATA: Converted Data
The analog-to-digital conversion data is placed into this register at the end of a conversion and remains until a new conversion
is completed. The Convert Data Register (CDR) is only loaded if the corresponding analog channel is enabled.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––––––
15 14 13 12 11 10 9 8
–––––– DATA[9:8]
76543210
DATA[7:0]
809
32072H–AVR32–10/2012
AT32UC3A3
29.7.12 Version Register
Name: VERSION
Access Type: Read-only
Offset: 0xFC
Reset Value: –
• VARIANT: Variant Number
Reserved. No functionality associated.
• VERSION: Version Number
Version number of the module. No functionality associated.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
–––– VARIANT
15 14 13 12 11 10 9 8
–––– VERSION[11:8]
76543210
VERSION[7:0]
810
32072H–AVR32–10/2012
AT32UC3A3
29.8 Module Configuration
The specific configura tion for the ADC instance is listed in the following tables.
Table 29-3. Module configuration
Feature ADC
ADC_NUM_CHANNELS 8
Internal Tr igger 0 TIOA Ouput A of the Timer Counter 0 Channel 0
Internal Tr igger 1 TIOB Ouput B of the Timer Counter 0 Channel 0
Internal Tr igger 2 TIOA Ouput A of the Timer Counter 0 Channel 1
Internal Tr igger 3 TIOB Ouput B of the Timer Counter 0 Channel 1
Internal Tr igger 4 TIOA Ouput A of the Timer Counter 0 Channel 2
Internal Tr igger 5 TIOB Ouput B of the Timer Counter 0 Channel 2
Table 29-4. Module Clock Name
Module name Clock name
ADC CLK_ADC
Table 29-5. Register Reset Values
Module name Reset Value
VERSION 0x00000200
811
32072H–AVR32–10/2012
AT32UC3A3
30. HSB Bus Performance Monitor (BUSMON)
Rev 1.0.0.0
30.1 Features •Allo ws performance monitoring of High Speed Bus master interfaces
– Up to 4 masters can be monitored
– Periphera l Bus access to monitor registers
•The following is monitored
– Data tran sfer cycles
– Bus stall cycles
– Maximum access latency for a single transfer
•A u tomatic hand lin g of event overflow
30.2 Overview BUSMON allows the user to measure the activity and stall cycles on the High Speed Bus (HSB).
Up to 4 device-specific masters can be measured. Each of these masters is part of a measure-
ment channel. Which masters tha t are connected to a channel is device-specific. Devices may
choose not to implement all channels.
30.3 Block Diagram
Figure 30-1. BUSMON Block Diagram
Registers
Master A
Master B
Master C
Master D
Slave 0
Registers
Master E
Master F
Master G
Master H
Slave 1
Registers
Master I
Master J
Master K
Master L
Slave 2
Registers
Master M
Master N
Master O
Master P
Slave 3
Control
Peripheral Bus Interface
Channel 0
Channel 1
Channel 2
Channel 3
812
32072H–AVR32–10/2012
AT32UC3A3
30.4 Product Dependencies
In order to use t his modu le, othe r p arts o f th e syst em must be conf igu red cor re ctly, as de scr ibed
below.
30.4.1 Clocks The clock for the BUSMON bus interface (CLK_BUSMON) is generated by the Power Manager.
This clock is enab led at re set and can be disab led in the Power Mana ger. It is reco mmen ded to
disable the BUSMON before disa bling th e clock, to avoi d fre ezing the BUSMON in an undef ined
state.
30.5 Functional Description
Three different parameters can be measured by each channel:
• The number of data transfer cycles since last channel reset
• The number of stall cycles since last channel reset
• The maximum cont inu ous n umber of sta ll cycles since last chann el reset (Th is approximates
the max latency in the transfers.)
These measurements can be extracted by software and used to generate indicators for bus
latency, bus load and maximum bus lat ency.
Each of the counters have a fixed width, and may therefore overflow. When overflow is encoun-
tered in either the Channel n Data Cycles (DATAn) register or the Channel n Stall Cycles
(STALLn) register of a channel, all registers in the channel are reset. This behavior is altered if
the Channel n Overflow Freeze (CHnOF) bit is set in the Control (CONTROL) register. If this bit
is written to one, the channel registers are frozen when either DATAn or STALLn reaches its
maximum value. This simplifies one-shot readout of the counter values.
The registers can also be manually reset by writing to the CONTROL register. The Channeln
Max Initiation Latency (LATn) register is saturating, when its max c ount is reached, it will be set
to its maximum value. The LATn register is reset whene ver DATAn and STALLn are reset.
A counter must manually be en abled by writing to the CONTROL register.
813
32072H–AVR32–10/2012
AT32UC3A3
30.6 User interface
Note: 1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter.
Table 30-1. BUSMON Register Memory Map
Offset Register Register Name Acces s Reset
0x00 Control register CONTROL Read/Write 0x00000000
0x10 Channel0 Data Cycles register DATA0 Read 0x00000000
0x14 Channel0 Stall Cycles register STALL0 Read 0x00000000
0x18 Channel0 Max Initiation Latency register LAT0 Read 0x00000000
0x20 Channel1 Data Cycles register DATA1 Read 0x00000000
0x24 Channel1 Stall Cycles register STALL1 Read 0x00000000
0x28 Channel1 Max Initiation Latency register LAT1 Read 0x00000000
0x30 Channel2 Data Cycles register DATA2 Read 0x00000000
0x34 Channel2 Stall Cycles register STALL2 Read 0x00000000
0x38 Channel2 Max Initiation Latency register LAT2 Read 0x00000000
0x40 Channel3 Data Cycles register DATA3 Read 0x00000000
0x44 Channel3 Stall Cycles register STALL3 Read 0x00000000
0x48 Channel3 Max Initiation Latency register LAT3 Read 0x00000000
0x50 Parameter register PARAMETER Read -(1)
0x54 Version register VERSION Read -(1)
814
32072H–AVR32–10/2012
AT32UC3A3
30.6.1 Control Register
Name: CONTROL
Access Type: Read/Write
Offset: 0x00
Reset Value: 0x00000000
• CHnRES: Channel Counter Reset
Writting a one to this bit will reset the counter in the channel n.
Writting a z e ro to thi s bi t ha s no effect.
This bit alw ays reads as zero.
• CHnOF: Channel Overflow Freeze
1: All channel n registers are frozen just before DATA or STALL overflows.
0: The channel n registers are reset if DATA or STALL overflows.
• CHnEN: Channel Enabled
1: The channel n is enabled.
0: The channel n is disabled.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
----CH3RESCH2RESCH1RESCH0RES
15 14 13 12 11 10 9 8
----CH3OFCH2OFCH1OFCH0OF
76543210
-- --CH3ENCH2ENCH1ENCH0EN
815
32072H–AVR32–10/2012
AT32UC3A3
30.6.2 Channel n Data Cycles Register
Name: DATAn
Access Type: Read-Only
Offset: 0x10 + n*0x10
Reset Value: 0x00000000
•DATA:
Data cycles counted since the last reset.
31 30 29 28 27 26 25 24
DATA[31:24]
23 22 21 20 19 18 17 16
DATA[23:16]
15 14 13 12 11 10 9 8
DATA[15:8]
76543210
DATA[7:0]
816
32072H–AVR32–10/2012
AT32UC3A3
30.6.3 Channel n Stall Cycles Register
Name: STALLn
Access Type: Read-Only
Offset: 0x14 + n*0x10
Reset Value: 0x00000000
•STALL:
Stall cycles counted since the last reset.
31 30 29 28 27 26 25 24
STALL[31:24]
23 22 21 20 19 18 17 16
STALL[23:16]
15 14 13 12 11 10 9 8
STALL[15:8]
76543210
STALL[7:0]
817
32072H–AVR32–10/2012
AT32UC3A3
30.6.4 Channel n Max Transfer Initiation Cycles Register
Name: LATn
Access Type: Read-Only
Offset: 0x18 + n*0x10
Reset Value: 0x00000000
•LAT:
This field is cleared whenever the DATA or STALL register is reset.
Maximum transfer initiation cycles counted since the last reset.
This counter is saturating.
31 30 29 28 27 26 25 24
LAT[31:24]
23 22 21 20 19 18 17 16
LAT[23:16]
15 14 13 12 11 10 9 8
LAT[15:8]
76543210
LAT[7:0]
818
32072H–AVR32–10/2012
AT32UC3A3
30.6.5 Parameter Register
Name: PARAMETER
Access Type: Read-only
Offset: 0x50
Reset Value: -
• CHnIMP: Channel Implementation
1: The corresponding channel is implemented.
0: The corresponding channel is not imple m ented.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
- - - - CH3IMPL CH2IMPL CH1IMPL CH0IMPL
819
32072H–AVR32–10/2012
AT32UC3A3
30.6.6 Version Register
Name: VERSION
Access Type: Read-only
Offset: 0x54
Reset Value: -
• VARIANT: Variant Number
Reserved. No functionality associated.
• VERSION: Version Number
Version number of the module. No functionality associated.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
---- VARIANT
15 14 13 12 11 10 9 8
- - - - VERSION[11:8]
76543210
VERSION[7:0]
820
32072H–AVR32–10/2012
AT32UC3A3
30.7 Module Configuration
Table 30-2. Register Reset Values
Register Reset Value
VERSION 0x00000100
PARAMETER 0x0000000F
821
32072H–AVR32–10/2012
AT32UC3A3
31. MultiMedia Card Interface (MCI)
Rev. 4.1.0.0
31.1 Features •Compatible with Multimedia Card specification version 4.3
•Compatible with SD Memory Card specification version 2.0
•Compatible with SDIO specification version 1.1
•Compatible with CE-ATA specification 1.1
•Cards clock rate up to master clock divided by two
•Boot Operation Mode support
•High Speed mode support
•Embedded power management to slow down clock rate when not used
•Supports 2
– Each slot for either a MultiMediaCard bus (up to 30 cards) or an SD Memory Card
•Support for stream, block and multi-block data read and write
•Supports connection to DMA Controller
– Minimizes processor intervention for large buffer transfers
•Built in FIFO (from 16 to 256 bytes) with large memory aperture supporting incr emental access
•Support for CE-ATA completion cignal disable command
•Protection a gainst une x pected mo difi cati on on-the-Fly of the configuration reg isters
31.2 Overview The Multimedia Card Interface (MCI) supports the MultiMedia Card (MMC) specification V4.3,
the SD Memory Card specification V2.0, the SDIO V1.1 specificationand CE-ATA specification
V1.1.
The MCI includes a Command Register (CMDR), Response Registers (RSPRn), da ta register s,
time-out counters and error detection logic that automatically handle the transmission of com-
mands and, when required, the reception of the associated responses and data with a limited
processor overhead.
The MCI supports stream, block and multi block data read and write, and is compatible with the
DMA Controller, minimizing processor intervention for large buffers transfers.
The MCI operates at a rate of up to CLK_MCI divided by 2 and supports the interfacing of 2.
Each slot may be used to interface with a MultiMediaCard bus (up to 30 Cards) or with a SD
Memory Card. On ly one slot can be selected at a t ime (slots ar e multiplexed). The SDCard/SDIO
Slot Selection field in the SDCard/SDIO Register (SDCR.SDCSEL) performs this selection.
The SD Memory Card communication is based on a 9-pin interface (clock, command, four data
and three power lines) and the MultiMedia Card on a 7-pin to 13-pin nterface (clock, command,
one to eight data, three power lines and one reserved for future use).
The SD Memory Card interf ace also suppor ts MultiM edia Card oper ations. The ma in diffe rences
between SD and MultiMedia Cards are the initialization process and the bus topology.
MCI fully supports CE-ATA Revision 1.1, built o n th e MMC System specif ica ti on V4.0. The mod-
ule includes dedicated hardware to issue the command completion signal and capture the host
command comp let i on sign al disable.
822
32072H–AVR32–10/2012
AT32UC3A3
31.3 Block Diagram
Figure 31-1. MCI Block Diagram
Figure 31-2. Application Block Diagram
CMD
CLK
DATA
I/O
controller
DMA Controller
MCI Interface
Interrupt Control
MCI Interrupt
CLK_MCI
Power
Manager
Peripheral
Bus
Peripheral Bus Brigde
123456
MMC
7
1
9
2345 768
SDCard
Physical Layer
MCI Interface
Application Layer
Ex: File System, Audio, Security, etc
910 1213 8
823
32072H–AVR32–10/2012
AT32UC3A3
31.4 I/O Lines Description
31.5 Product Dependencies
In order to use t his modu le, othe r p arts o f th e syst em must be conf igu red cor re ctly, as de scr ibed
below.
31.5.1 Power Management
If the CPU enters a sleep mode that disables clocks used by the MCI, the MCI will stop function-
ing and resume operation after the system wakes up from sleep mode.
31.5.2 I/O Lines The pins used for interfacing the MultiMedia Cards or SD Cards ma y be multiplexed with GPIO
lines. User must first program the I/O controller to assign the peripheral functions to MCI pins.
31.5.3 Clocks The clock for the MCI bus interface (CLK_MCI) is generated by the Power Manager. This clock
is enabled at reset, and can be disabled in t he Power Ma nager. It is r ecommended to di sable the
MCI before disabling the clock, to avoid fr eezing the MCI in an undefined state.
31.5.4 Interrupt The MCI interrupt request line is connected to the interrupt controller. Using the MCI interrupt
requires the interrupt controller to be programmed first.
31.6 Functional Description
31.6.1 Bus Topology
Figure 31-3. Multimedia Memory Card Bus Topology
Table 31-1. I/O Lines Description
Pin Name Pin Description Type (1)
1. PP: Push/Pull, OD : Open Drain
Comments
CMD[1:0] Command/Response Input/Output/
PP/OD CMD of a MMC or SDCard/SDIO
CLK Clock Input/Output CLK of a MMC or SD Card/SDIO
DATA[7:0] Data 0..7 of Slot A Input/Output/PP DAT[0..7] of a MMC
DAT[0..3] of a SD Card/SDIO
DATA[15:8] Data 0..7 of Slot B Input/Output/PP DAT[0..7] of a MMC
DAT[0..3] of a SD Card/SDIO
123456
MMC
7
910 1213 8
824
32072H–AVR32–10/2012
AT32UC3A3
The MultiMedia Card communication is based on a 13-pin serial bus interface. It has three com-
munication lines and four supply lines.
Notes: 1. I: Input, O: Output, PP: Push/Pull, OD: Open Drain.
Figure 31-4. MMC Bus Connections (One Slot)
Figure 31-5. SD Memory Card Bus Topology
Table 31-2. Bus Topology
Pin
Number Name Type(1) Description MCI Pin Name(2)
(Slot z)
1 DAT[3] I/O/PP Data DATAz[3]
2 CMD I/O/PP/OD Command/response CMDz
3 VSS1 S Supply voltage ground VSS
4 VDD S Supply voltage VDD
5 CLK I/O Clock CLK
6 VSS2 S Supply voltage ground VSS
7 DAT[0] I/O/PP Data 0 DATAz[0]
8 DAT[1] I/O/PP Data 1 DATAz[1]
9 DAT[2] I/O/PP Data 2 DATAz[2]
10 DAT[4] I/O/PP Data 4 DATAz[4]
11 DAT[5] I/O/PP Data 5 DATAz[5]
12 DAT[6] I/O/PP Data 6 DATAz[6]
13 DAT[7] I/O/PP Data 7 DATAz[7]
CLK
DATA[0]
CMD
MCI
123456
MMC2
7
910 1213 8
11
123456
MMC3
7
910 1213 8
11
123456
MMC1
7
910 1213 8
11
12 43 5678
9SDCARD
825
32072H–AVR32–10/2012
AT32UC3A3
The SD Memory Card bus includes the signals listed in Table 31-3 on page 825.
Notes: 1. I: input, O: output, PP: Push Pull, OD: Open Drain.
Figure 31-6. SD Card Bus Connections with One Slot
Figure 31-7. SD Card Bus Connections with Two Slots
Table 31-3. SD Memory Card Bus Signals
Pin
Number Name Type(1) Description MCI Pin Name (2)
(Slot z)
1 CD/DAT[3] I/O/PP Card detect/ Data line Bit 3 DATAz[3]
2 CMD PP Command/response CMDz
3 VSS1 S Supply voltage ground VSS
4 VDD S Supply voltage VDD
5 CLK I/O Clock CLK
6 VSS2 S Supply voltage ground VSS
7 DAT[0] I/O/PP Data line Bit 0 DATAz[0]
8 DAT[1] I/O/PP Data line Bit 1 or Interrupt DATAz[1]
9 DAT[2] I/O/PP Data line Bit 2 DATAz[2]
2
9345678
SDCARD
1
CMD
CLK
DATA[3:0]
523 61478
9
SDCARD1
523 61478
9
SDCARD2
DATA[7:4]
CMD[0]
CLK
DATA[3:0]
CMD[1]
CLK
826
32072H–AVR32–10/2012
AT32UC3A3
Figure 31-8. Mixing MultiMedia and SD Memory Cards with Two Slots
When the MCI is configured to operate with SD memory cards, the width of the data bus can be
selected in the SDCard /SDIO Bus Width field in the SDCR register (SDCR.SDCBUS). See Sec-
tion “31.7 .4” on page 847. for details.
In the case of multimedia cards, only the data line 0 is used. The other data lines can be use d as
independent GPIOs.
When more than one card (MMC or SD) is plugged to the device, it is strongly recommended to
connect each card’s clock to a dedicate MCI CLK pin of the device. Otherwise, Compliance to
specifications is not guaranteed.
31.6.2 MultiMedia Card Operations
After a power-on reset, the cards are initialized by a special message-based MultiMedia Card
bus protocol. Each message is represented by one of the following tokens:
• Command: a command is a token that starts an operation . A command is sent from t he host
either to a single card (addressed command) or to all connected cards (broadcast
command). a command is transferred serially on the CMD line.
• Response: a response is a token which is sent from an addressed card or (synchronously)
from all connecte d cards to the host as an answer to a previously received command. A
response is transferred serially on the CMD line.
• Data: data can be transferred from the card to the host or vice versa. Data is transferred via
the data line.
Card addressing is implemented using a session address assigned during the initialization
phase by the bus controller to all currently connected cards. Their unique CID number identifies
individual cards.
4
9
23156
78
SDCARD
DATA[7:0]
CMD[0]
CLK
DATA[11:8]
CMD[1]
123456
MMC1
7
910 1213 8
11
123456
MMC2
7
910 1213 8
11
123456
MMC3
7
910 1213 8
11
CLK
827
32072H–AVR32–10/2012
AT32UC3A3
The structure of commands, responses and data blocks is described in the MultiMedia-Card
System Specification. Refer also to Table 31-5 on page 828.
MultiMediaCard bus data transfers are composed of these tokens.
There are different types of opera tions. Addressed operations always contain a command and a
response token. In addition, some operations ha ve a data token; the o thers transfer their infor-
mation direc tly within the co mman d or r espons e stru ctur e. In th is case , no d ata t oken is pr esen t
in an operation. The bits on the DAT and the CMD lines are transferred synchronous to the MCI
clock (CLK).
Two types of data transfer commands are defined:
• Sequential commands: these commands initiate a continuous data stream. They are
terminated only when a stop command follows on the CMD line. This mode reduces the
command overhead to an absolute minimum.
• Block-oriented commands: these commands send a data block succeeded by CRC bits.
Both read and write operations allow either single or multiple block transmission. A multiple
block transmission is terminated when a stop command follows on the CMD line similarly to the
sequential read or when a multiple block transmission has a pre-defined block count (See Sec-
tion “31.6 .3” on page 829.).
The MCI provides a set of reg isters to perform the entire range of MultiMedia Card operations.
31.6.2.1 Command - Response Operation
After reset, t he MCI is d isa bled a nd beco mes valid af ter set ting th e M ulti-M edia Int erfa ce En able
bit in the Control Register (CR.MCIEN).
The Power Save Mode Enable bit in the CR register (CR.PWEN) saves power by dividing the
MCI clock (CLK) by 2PWSDIV + 1 when the bus is inactive. The Power Saving Divider field locates
in the Mode Register (MR.PWSDIV).
The two bits, Read Proof Enable and Write Proo f Enable in the MR regist er (MR.RDPROOF and
MR.WRPROOF) allow stopping the MCI Clock (CLK) during read or write access if the internal
FIFO is full. This will guarantee data integrity, not bandwidth.
All the timings for MultiMedia Card are defined in the MultiMediaCard System Specification.
The two bus modes (open drain and push/pull) needed to process all the operations are defined
in the Command Register (CMDR). The CMDR register allows a command to be carried out.
For example, to perform an ALL_SEND_CID command
Table 31-4. ALL_SEND_CID command
Host Command NID Cycles CID
CMD S T Content CRC E Z ****** Z S T Content Z Z Z
828
32072H–AVR32–10/2012
AT32UC3A3
The command ALL_SEND_CID and the fields and values for CMDR register are described in
Table 31-5 on page 828 and Table 31-6 on page 828.
Note: bcr means broadcast command with response.
The Argument Register (ARGR) contains the argument field of the command.
To send a command, the user must perform the following steps:
• Set the ARGR register with the command argument.
• Set the CMDR register (see Table 31-6 on page 828).
The command is sent immediately after writing the command register.
As soon as the command register is written, then th e Command Rea dy bit in the Status Register
(SR.CMDRDY) is cleared.
It is released and the end of the card response.
If the command requires a response, it can be read in the Response Registers (RSPRn). The
response size can be from 48 bits up to 136 bits depending on the command. The MCI embeds
an error detect ion to prevent any corrupted data during the transfer.
The following flowchart shows how to send a command to the card and read the response if
needed. In this example, the status register bits are polled but setting the appropriate bits in the
Interrupt Enable Register (IER) allows using an interrupt method.
Table 31-5. ALL_SEND_CID Command Description
CMD Index Type Argument Resp Abbreviation Command
Description
CMD2 bcr [31:0] stuff bits R2 ALL_SEND_CID
Asks all cards to
send their CID
numbers on the
CMD line
Table 31-6. Fields and Values for the CMDR register
Field Value
CMDNB (command number) 2 (CMD2)
RSPTYP (response type) 2 (R2: 136 bits response)
SPCMD (special command) 0 (not a special command)
OPCMD (open drain command) 1
MAXLAT (max latency for command to
response) 0 (NID cycles ==> 5 cycles)
TRCMD (transfer command) 0 (No transfer)
TRDIR (transfer direction) X (available only in transfer command)
TRTYP (transfer type) X (available only in transfer command)
IOSPCMD (SDIO special command) 0 (not a special command)
829
32072H–AVR32–10/2012
AT32UC3A3
Figure 31-9. Command/Response Functional Flow Diagram
Note: 1. If the command is SEND_OP_COND, the CRC error bit is always present (refer to R3
response in the MultiMedia Card specification).
31.6.3 Data Transfer Operation
The MultiMedia Card allows several read/write operations (single block, multiple blocks, stream,
etc.). These kind of transfers can be selected setting the Transfer Type field in the CMDR regis-
ter (CMDR.TRTYP) .
These operations ca n be done using the features of the DMA Controller.
In all cases, the Data Block Length must be defined either in the Data Block Length field in the
MR register (MR.BLKLEN)), or in the Block Register (BLKR). This field determines the size of
the data block.
Set the command argument
ARGR = Argument(1)
Set the command
CMD = Command
Read the SR register
0
Yes
1
SR.CMDRDY
Wait for SR.CMDRY bit set
to one
Check error bits in the
SR register(1) Status error bits?
RETURN OK
RETURN ERROR(1)
Read response if required
830
32072H–AVR32–10/2012
AT32UC3A3
Consequent to MMC Specification 3.1, two types of multiple block read (or write) transactions
are defined (the host can use either one at any time):
• O pen-ended/Infinite Multiple block read (or write):
The number of bl ocks for th e read (o r write) multiple blo ck operat ion is not defined. The ca rd
will continuously transfer (or program) data blocks until a stop transmission command is
received.
• Multiple block read (or write) with pre-defined block count (since version 3.1 and higher):
The card will transfer (or program) the requested number of data blocks and terminate the trans-
action. The stop comman d is no t requ ire d at t he end of t his type of mult iple blo ck read (o r write ),
unless terminated with an error. In order to start a multiple block read (o r write) with pre-defin ed
block count, the host must correctly set the BLKR register. Otherwise the card will start an open-
ended multiple block read. The MMC/SDIO Block Count - SDIO Byte Count field in the BLKR register
(BLKR.BCNT) defines the number of blocks to transfer (from 1 to 65535 blocks). Wr iting zero to
this field corresponds to an infinite block transfer.
31.6.4 Read/Write Operation
The following flowchart shows how to read a single block with or without use of DMA Controller
facilities. In this example (see Figure 31-10 on pa ge 831), a polling method is used to wait for the
end of read. Similarly, the user can con fig ur e the I ER re giste r to t r igge r an int er rupt at the end of
read.
831
32072H–AVR32–10/2012
AT32UC3A3
Figure 31-10. Read Functional Flow Diagram
Note: 1. It is assumed that this command has been correctly sent (see Figure 31-9 on page 829).
2. This field is also accessible in the BLKR register.
Write a one in the DMA.DMAEN bit
Write the BlockLenght in the MR.BLKLEN field(2)
Send SELECT/DESELECT_CARD
Command(1) to select the card
Send SET_BLOCKLEN command(1)
No Yes
Read with DMA
Write a zero in the DMA.DMAEN bit
Write the BlockLenght in the MR.BLKLEN field(2)
Write the block count in the BLKR.BCNT field (if
necessary)
Read data in the RDR register
Number of words to read =
Number of words to read -1
Send READ_SINGLE_BLOCK
command(1)
Configure the DMA channel X
write the Data Adress in the DMA Controller
write the (MR.BLKLEN)/4 for Transfer Size
in the DMA Controller
Number of words to read = (MR.BLKLEN)/4
Number of words to read = 0 ?
Yes
No
Yes
Yes
Read the SR register
SR.XFRDONE = 0 ?
No
RETURN
Read the SR register
SR.RXRDY = 0 ?
No
RETURN
Send READ_SINGLE_BLOCK
command(1)
832
32072H–AVR32–10/2012
AT32UC3A3
In write operation, the Padding Value bit in the MR register (MR.PADV) is used to define the
padding value when writing non-multiple block size. When the MR.PADV is zero, then 0x00
value is used when padd ing data, otherwise 0xFF is used.
Write a one in the DMA Hardware Handshaking Enable bit in the DMA Configuration Register
(DMA.DMAEN) enables DMA transfer.
The following flowchart shows how to write a single block with or without use of DMA facilities
(see Figure 31-11 on page 83 3). Polling or interrupt method can be use d to wait for the end of
write according to the contents of the Interrupt Mask Register (IMR).
833
32072H–AVR32–10/2012
AT32UC3A3
Figure 31-11. Write Functional Flow Diagram
Note: 1. It is assumed that this command has been correctly sent (see Figure 31-9 on page 829).
2. This field is also accessible in BLKR register.
Write using DMA
No Yes
Yes
Write a zero in the DMA.DMAEN bit
Write the BlockLenght in the MR.BLKLEN field(2)
Write the block count in the BLKR.BCNT field (if
necessary)
Number of words to write = BlockLength/4
Number of words to write = 0 ?
No
No
Yes
Read the SR register
SR.TXRDY = 0 ?
Write Data to transmit in the TDR register
Number of words to write =
Number of words to write - 1
RETURN
RETURN
Yes
No
Read the SR register
SR.NOTBUSY = 0 ?
Enable the DMA channel X
Write a one in the DMA.DMAEN bit
Write the BlockLenght in the MR.BLKLEN field(2)
Send SELECT/DESELECT_CARD
Command(1) to select the card
Send SET_BLOCKLEN command(1)
Send WRITE_SINGLE_BLOCK
command(1)
Send WRITE_SINGLE_BLOCK
command(1)
Configure the DMA channel X
write the Data Adress in the DMA Controller
write the (MR.BLKLEN)/4 for Transfer Size in the
DMA Controller
834
32072H–AVR32–10/2012
AT32UC3A3
The following flowchart shows how to manage a multiple write block transfer with the DMA Con-
troller (see Figure 31-12 on page 835). Polling or interrupt method can be used to wait for the
end of write according to the contents of the IMR register.
835
32072H–AVR32–10/2012
AT32UC3A3
Figure 31-12. Multiple Write Functional Flow Diagram
Note: 1. It is assumed that this command has been correctly sent (see Figure 31-9 on page 829).
2. This field is also accessible in BLKR register.
Send SELECT/DESELECT_CARD
Command(1) to select the card
Send SET_BLOCKLEN command(1)
No
Read the SR register
SR.BLKE = 0 ?
Enable the DMA channel X
Write a zero in the DMA.DMAEN bit
Write the block lenght in the MR.BLKLEN field(2)
Write the block count in the BLKR.BCNT field (if
necessary)
Send WRITE_MULTIPLE_BLOCK command(1)
Configure the DMA channel X
write the Data Adress in the DMA Controller
write the (MR.BLKLEN)/4 for Transfer Size in the
DMA Controller
Yes
Send STOP_TRANSMISSION command(1)
SR.NOTBUSY = 0 ?
Yes
No
RETURN
836
32072H–AVR32–10/2012
AT32UC3A3
31.6.4.1 WRITE_SINGLE_BLOCK operation using DMA Controller
1. Wait unt il the current command execution has successfully terminated.
c. Check that the Transfer Done bit in the SR register (SR.XFRDONE) is set
2. Write the block length in the card. This value defines the value block_lenght.
3. Write the MR.BLKLEN with block_lenght value.
4. Configure the DMA Channel in the DMA Controller.
5. Write the DMA register with the following fields:
– Write the dma_offset to the DMA Write Buffer Offset field (DMA.OFFSET).
– Write the DMA Channel Read and Write Chunk Size field (DMA.CHKSIZE).
– Write a one to he DMA.DMAEN bit to enable DMA hardw are handshaking in the
MCI.
6. Write a one to the DMA Transfer done bit in IER register (IER.DMADONE).
7. Issue a WRITE_SINGLE_BLOCK command.
8. Wait for DMA Transfer done bit in SR register (SR.DMADONE) is set.
31.6.4.2 READ_SINGLE_BLOCK operation using DMA Controller
1. Wait unt il the current command execution has successfully terminated.
d. Check that the SR.XFRDONE bit is set.
2. Write the block length in the card. This value defines the value block_lenght.
3. Write the MR.BLKLEN with block_lenght value.
4. Configure the DMA Channel in the DMA Controller.
5. Write the DMA register with the following fields:
– Write zero to the DMA.OFFSET field.
– Write the DMA.CHKSIZE fi eld.
– Write to one the DMA.DMAEN bit to enable DMA hardware handshaking in the MCI.
6. Write a one to the IER.DMADONE bit.
7. Issue a READ_SINGLE_BLOCK command.
8. Wait for SR.DMADONE bit is set.
31.6.4.3 WRITE_MULTIPLE_BLOCK
1. Wait unt il the current command execution has successfully terminated.
a. Check that the SR.XFRDONE bit is set.
2. Write the block length in the card. This value defines the value block_lenght.
3. Write the MR.BLKLEN with block_lenght value.
4. Progr am the DMA Controller to use a list of descriptors. Each descriptor transfers one
bl ock of data.
5. Progr am the DMA register with the following fields:
– Write the dma_offset in the DMA.OFFSET field.
– Write the DMA.CHKSIZE fi eld.
– Write a one to the DMA.DMAEN bit to ena ble DMA hardware handshaking in the
MCI.
6. Write a one to the IER.DMADONE bit.
7. Issue a WRITE_MULTIPLE_BLOCK command.
8. Wait for DMA chained buffer transfer complete interrupt.
837
32072H–AVR32–10/2012
AT32UC3A3
31.6.4.4 READ_MULTIPLE_BLOCK
1. Wait unt il the current command execution has successfully terminated.
a. Check that the SR.CMDRDY and the SR.NOTBUSY are set.
2. Write the block length in the card. This value defines the value block_lenght.
3. Write the MR.BLKLEN with block_lenght value.
4. Program the DMA Controller to use a list of descriptors.
5. Write the DMA register with the following fields:
– Write zero to the DMA.OFFSET.
– Write the DMA.CHKSIZE.
– Write a one to the DMA.DMAEN bit to ena ble DMA hardware handshaking in the
MCI.
6. Write a one to the IER.DMADONE bit.
7. Issue a READ_MULTIPLE_BLOCK command.
8. Wait for DMA end of chained buffer transfer interrupt.
31.6.5 SD/SDIO Card Operation
The MCI allows processing of SD Memory (Secure Digital Memory Card) and SDIO (SD Input
Output) Card commands.
SD/SDIO cards are based on the MultiMedia Card (MMC) format, but are physically slightly
thicker and feature higher data transfer rates, a lock switch on the side to prevent accidental
overwriting and security features. The physical form factor, pin assignment and data transfer
protocol are forward-compatible with the MultiMedia Card with some additions. SD slots can
actually be used for more than flash memory cards. Devices that support SDIO can use small
devices designed for the SD form factor, such as GPS receivers, Wi-Fi or Bluetooth adapters,
modems, barcode readers, IrDA adapters, FM radio tuners, RFID readers, digital cameras a nd
more.
SD/SDIO is covered by numerous patents and trademarks, and licensing is only available
through the Secure Digital Card Association.
The SD/SDIO Card communication is based on a nine-pin interface (Clock, Command,
four Data and three Power lines). The communication protocol is defined as a part of this speci-
fication. The main difference between the SD/SDIO Card and the MultiMedia Card is the
initialization process.
The SD/SDIO Card Register (SDCR) allows selection of the Card Slot (SDCSEL) and the data
bus width (SDCBUS).
The SD/SDIO Card bus allows dynamic configuration of the number of data lines. After power
up, by defa u lt, t he SD /SDI O Card uses on ly DAT[0] for da ta tr an sfer. After initia liza tio n, th e h o st
can change the bus width (number of active data lines).
31.6.5.1 SDI O Dat a Transfer Type
SDIO cards may transfer data in either a multi-byte (1 to 512 bytes) or an optional block format
(1 to 511 blocks), while the SD memory cards are fixed in the block transfer mode. The
CMDR.TRTYP field allows to choose between SDIO Byte or SDIO Block transfer.
The number of bytes/blocks to transfer is set through the BCNT field in the BLKR register. In
SDIO Block mode, the field BLKLEN must be set to the data block size while th is field is not
used in SDIO Byte mode.
838
32072H–AVR32–10/2012
AT32UC3A3
An SDIO Card can have multiple I/O or co mbined I/O and mem ory (called Combo Card). Within
a multi-function SDIO or a Combo card, there are multiple devices (I/O and memory) that share
access to the SD bus. In order to allow the sha ring of access to the host amo ng multiple devices,
SDIO and combo card s can implement the optiona l concept of suspend/resume ( Refer to the
SDIO Specification for more details). To send a suspend or a resume command, the host must
set the SDIO Special Command field in CMDR register (CMDR.IOSPCMD).
31.6.5.2 SDI O Int er rupts
Each function within an SDIO o r Combo card may implement interrupts (Refer to the SDIO
Specification for more details). In order to allow the SDIO card to in terrupt the host, an in terrupt
function is added to a pin on the DAT[1] line to signal the card’s interrupt to the ho st. An SDIO
interrupt on each slot can be enabled in the IER register. The SDIO interrupt is sampled regard-
less of the currently selected slot.
31.6.6 CE-ATA Operation
CE-ATA maps the streamlined ATA command set onto the MMC interface. The ATA task file is
mapped onto MMC register space.
CE-ATA utilizes five MMC commands:
• GO_IDLE_STATE (CMD0): used for hard reset.
• STOP_TRANSMISSION (CMD12): causes the ATA command currently executing to be
aborted.
• FAST_IO (CMD39): Used for single register access to the ATA taskfile registers, eight bit
access only.
• RW_MULTIPLE_REGISTERS (CMD60): used to issue an ATA command or to access the
control/status registers.
• RW_MULTIPLE_BLOCK (CMD61): used to transfer data f or an ATA command.
CE-ATA utilizes the same MMC command sequences for initialization as traditional MMC
devices.
31.6.6.1 Executing an ATA Polling Command
1. Issue READ_DMA_EXT with RW_MULTIPLE_REGISTER (CMD60) for eightkB of
DATA.
2. Read the ATA status register until DRQ is set.
3. Issue RW_MULTIPLE_BLOCK (CMD61) to tr ansfer DATA.
4. Read the ATA status register until DRQ && BSY are set to 0.
31.6.6.2 Executing an ATA Interrupt Command
1. Issue READ_DMA_EXT with RW_MULTIPLE_REGISTER (CMD60) for eightkB of
DATA with the IEN field written to z e ro to ena ble the command completion signal in th e
device.
2. Issue RW_MULTIPLE_BLOCK (CMD61) to tr ansfer DATA.
3. Wait for Completion Signal Received Interrupt.
31.6.6.3 Aborting an ATA Command
If the host needs to abort an ATA command prior to the completion signal it must send a special
command to avoid potential collision on the command line. The Special Command field of
839
32072H–AVR32–10/2012
AT32UC3A3
CMDR register (CMDR.SPCMD) must be set to three to issue the CE-ATA completion Signal
Disable Command.
31.6.6.4 CE-ATA Error Recovery
Several methods of ATA comman d failure may occur, including:
• No response to an MMC command, such as RW_MULTIPLE_REGISTER (CMD60).
• CRC is invalid for an MMC command or response.
• CRC16 is invalid for an MMC data packet.
• ATA Status register reflects an error by setting the ERR bit to one.
• The command completion signal does not arrive within a host specified time out period.
Error conditions are expected to happen infrequently. Thus, a robust error recovery mechanism
may be used for each error event. The recommended error recovery procedure after a time-out
is:
• Issue the command completion signal disable if IEN was clear ed to zero and the
RW_MULTIPLE_BLOCK (CMD61) response has been received.
• Issue STOP_TRANSMISSION (CMD12) and successfully receive the R1 response.
• Issue a software reset to the CE-ATA device using FAST_IO (CMD39).
If STOP_TRANMISSION (CMD12) is successful, then the device is again ready for ATA com-
mands. However, if the error recovery procedure does not work as expected or there is another
time-out, the next step is to issue GO_IDLE_STATE (CMD0) to the device. GO_IDLE_STATE
(CMD0) is a hard reset to the device and completely resets all device states.
Note that after issu ing GO_IDLE_STATE ( CMD0), a ll device initialization need s t o be com pleted
again. If the CE-ATA device completes all MMC commands correctly but fails the ATA command
with the ERR bit set in the ATA Status register, no error recovery action is required. The ATA
command itself failed implying that the device could not complete the action requested, how-
ever, there was no co mmunication or protocol failu re. After the device signals an error by setting
the ERR bit to one in the ATA Status register, the host may attempt to retry the command.
31.6.7 MCI Boot Operation Mode
In boot op eration mod e, the p rocessor can r ead boot data f rom the slave (MMC device) by keep-
ing the CMD line low after power-on before issuing CMD1. The data can be read from either
boot area or user area depending on register setting.
31.6.7.1 Boot Procedure, processor mode
1. Configure MCI2 data bus width programming SDCBUS Field in t he MCI_SDCR regis-
ter. The BOOT_BUS_WIDTH field located in the device Extended CSD register must
be set accordingly.
2. Set the bytecount to 512 bytes and the blockcount to the desired number of block, writ-
ing BLKLEN and BCNT fields of the MCI_BLKR Register.
3. Issue the Boot Operation Reque st command by writing to the MCI_CMDR register with
SPCMD field set to BOOTREQ, TRDIR set to READ and TRCMD set to “start data
transfer”.
4. The BOOT_ACK field located in the MCI_CMDR register must be set to one, if th e
BOO T_ACK field of the MMC de vice loca ted in the Extended CSD register is set to one .
5. Host processor can copy boot data sequentialy as soon as the RXRDY flag is asserted.
840
32072H–AVR32–10/2012
AT32UC3A3
6. When Data transfer is completed, host processor shall terminate the boot stream by
writing the MCI_CMDR register with SPCMD field set to BOOTEND.
31.6.7.2 Boot Procedure, dma mode
1. Configure MCI2 data bus width programming SDCBUS Field in t he MCI_SDCR regis-
ter. The BOOT_BUS_WIDTH field in the device Extended CSD register must be set
accordingly.
2. Set the bytecount to 512 bytes and the blockcount to the desired number of block, writ-
ing BLKLEN and BCNT fields of the MCI_BLKR Register.
3. Enable DMA transfer in the MCI_DMA register.
4. Configure DMA controller, program the total amount of dat a to be transferred and
enable the relevant channel.
5. Issue the Boot Operation Reque st command by writing to the MCI_CMDR register with
SPCND set to BOOTREQ, TRDIR set to READ and TRCMD set to “start data transfer”.
6. DMA controller copies the boot partition to the memory.
7. When DMA transfer is completed, host processor shall terminate the boot stream by
writing the MCI_CMDR register with SPCMD field set to BOOTEND.
31.6.8 MCI Transfer Done Timings
31.6.8.1 Definition The SR.XFRDO NE bit indicate s ex act l y when th e re ad or write se qu en ce is finish ed .
31.6.8.2 Read AccessDur ing a read access, the SR.XFRDONE bit behaves as shown in Figure 31-13 on page 840.
Figure 31-13. SR.XFRDONE During a Read Access
CMD line
MCI read CMD Card response
CMDRDY flag
Data
1st Block Last Block
Not busy flag
XFRDONE flag
The CMDRDY flag is released 8 t
bit
lafter the end of the card response.
841
32072H–AVR32–10/2012
AT32UC3A3
31.6.8.3 Write AccessDuring a write access, the SR.XFRDONE bit behaves as shown in Figure 31-14 on page 841.
Figure 31-14. SR.XFRDONE During a Write Access
31.7 User Interface
Table 31-7. MCI Register Memory Map
Offset Register Name Access Reset
0x000 Control Register CR Write-only 0x00000000
0x004 Mode Register MR Read-write 0x00000000
0x008 Data Time-out Register DTOR Read-write 0x00000000
0x00C SD/SDIO Card Register SDCR Read-write 0x00000000
0x010 Argument Register ARGR Read-write 0x00000000
0x014 Command Register CMDR Write-only 0x00000000
0x018 Block Register BLKR Read-write 0x00000000
0x01C Completion Signal Time-out Register CSTOR Read-write 0x00000000
0x020 Response Register RSPR Read-only 0x00000000
0x024 Response Register RSPR1 Read-only 0x00000000
0x028 Response Register RSPR2 Read-only 0x00000000
0x02C Response Register RSPR3 Read-only 0x00000000
0x030 Receive Data Register RDR Read-only 0x00000000
0x034 Transmit Data Register TDR Write-only 0x00000000
0x040 Status Register SR Read-only 0x0C000025
CMD line
MCI writeCMD Card response
CMDRDY flag
Data bus - D0
1st Block
Not busy flag
XFRDONE flag
The CMDRDY flag is released 8 t
bit
lafter the end of the card response.
Last Block
D0
1st Block Last Block
D0 is tied by the card
D0 is released
842
32072H–AVR32–10/2012
AT32UC3A3
0x044 Interrupt Enable Register IER Write-only 0x00000000
0x048 Interrupt Disable Register IDR Write-only 0x00000000
0x04C Interrupt Mask Register IMR Read-only 0x00000000
0x050 D MA Con figuration Register DMA Read-write 0x00000000
0x054 Configuration Register CFG Read-write 0x000 00000
0x0E4 Wr ite Protection Mode Register WPMR Read-write 0x00000000
0x0E8 Wr ite Protection Status Register WPSR Read-only 0x00000000
0x0FC Versi on Register VERSION Read -only - (1)
0x200-0x3FFC FIFO Memory Aperture – Read-write 0x00000000
1. The re set value are device specific. Please refer to the Module Configuration section at the end of this chapter.
Table 31-7. MCI Register Memory Map
Offset Register Name Access Reset
843
32072H–AVR32–10/2012
AT32UC3A3
31.7.1 Control Register
Name: CR
Access Type: Write-only
Offset: 0x000
Reset Value: 0x00000000
• SWRST : Software Reset
Writing a one to this bit will reset the MCI interface.
Writing a zero to this bit has no effect.
• IOWAITDIS: SDIO Read Wait Disable
Writing a one to this bit will disable the SDIO Read Wait Operation.
Writing a zero to this bit has no effect.
• IOWAITEN: SDIO Read Wait Enable
Writing a one to this bit will enable the SDIO Read Wait Operation.
Writing a zero to this bit has no effect.
• PWSDIS: Power Save Mode Disabl e
Writing a one to this bit will disable the Power Saving Mode.
Writing a zero to this bit has no effect.
• PWSEN: Power Save Mode Enable
Writing a one to this bit and a zero to PWSDIS will enable the Power Saving Mode.
Writing a one to this bit and a one to PWSDIS will disable the Power Saving Mode.
Writing a zero to this bit has no effect.
Warning: Before enabling this mode, the user must write a value different from 0 to the PWSDIV field.
• MCIDIS: Multi-Media Interface Disable
Writing a one to this bit will disable the Multi-Media Interface.
Writing a zero to this bit has no effect.
• MCIEN: Multi-Media Interface Enable
Writing a one to this bit and a zero to MCIDIS will enable the Multi-Media Interface.
Writing a one to this bit and a one to MCIDIS will disable the Multi-Media Interface.
Writing a zero to this bit has no effect.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
SWRST - IOWAITDIS IOWAITEN PWSDIS PWSEN MCIDIS MCIEN
844
32072H–AVR32–10/2012
AT32UC3A3
31.7.2 Mode Register
Name: MR
Access Type: Read-write
Offset: 0x004
Reset Value: 0x00000000
• BLKLEN[15:0]: Data Block Length
This field determines the size of the data block.
This field is also accessible in the BLKR register.
If FBYTE bit is zero, the BLKEN[1:0] field must be written to 0b00
Notes: 1. In SDIO Byte mode, BLKLEN field is not used.
2. BLKLEN should be written to one before sending the data transfer command. Otherwise,
Overrun may occur even if RDPROOF bit is one.
• PADV: Padding Value
0: 0x00 value is used when padding data in write transfer.
1: 0xFF value is used when padding data in write transfer.
PADV is used only in manual transfer.
• FBYTE: Force Byte Transfer
Enabling Force Byte Transfer allows byte transfers, so that transfer of blocks with a size different from modulo 4 can be
supported.
Warning: BLKLEN value depends on FBYTE.
Writing a one to this bit will enable the Force Byte Transfer.
Writing a zero to this bit will disable the Force Byte Transfer.
• WRPROOF Write Proof Enable
Enabling Write Proof allows to stop the MCI Clock (CLK) during write access if the internal FIFO is full. This will guarantee data
integrity, not bandwidth.
Writing a one to this bit will enable the Write Proof mode.
Writing a zero to this bit will disable the Write Proof mode.
• RDPROOF Read Proof Enable
Enabling Read Proof allows to stop the MCI Cloc k (CLK) during read access if the internal FIFO is full. This will guarantee data
integrity, not bandwidth.
Writing a one to this bit will enable the Read Proof mode.
Writing a zero to this bit will disable the Read Proof mode.
31 30 29 28 27 26 25 24
BLKLEN[15:8]
23 22 21 20 19 18 17 16
BLKLEN[7:0]
15 14 13 12 11 10 9 8
- PADV FBYTE WRPROOF RDPROOF PWSDIV
76543210
CLKDIV
845
32072H–AVR32–10/2012
AT32UC3A3
• PWSDIV: Power Saving Divider
Multimedia Card Interface clock is divided by 2(PWSDIV) + 1 when entering Power Saving Mode.
Warning: This value must be different from zero before enabling the Power Save Mode in the CR register (CR.PWSEN).
• CLKDIV: Clock Divider
The Multimedia Card Inte rface Clock (CLK) is CLK_MCI divided by (2*(CLKDIV+1)).
846
32072H–AVR32–10/2012
AT32UC3A3
31.7.3 Data Time-out Register
Name: DTOR
Access Type: Read/Write
Offset: 0x008
Reset Value: 0x00000000
These two fields determine the maximum number of CLK_MCI cycles that the MCI waits between two data block transfers.
It is equal to (DTOCYC x Multiplier).
If the data time-out defined by DTOCYC and DTOMUL has been exceeded, the Data Time-out Error bit in the SR register
(SR.DTOE) is set.
• DTOMUL: Data Time-out Multiplier
Multiplier is defined by DTOMU L as shown in the following table
• DTOCYC: Data Time-out Cycle Number
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
-DTOMUL DTOCYC
DTOMUL Multiplier
01
116
2128
3256
4 1024
5 4096
6 65536
7 1048576
847
32072H–AVR32–10/2012
AT32UC3A3
31.7.4 SDCard/SDIO Register
Name: SDCR
Access Type: Read/Write
Offset: 0x00C
Reset Value: 0x00000000
• SDCBUS: SDCard/SDIO Bus Width
• SDCSEL: SDCard/SDIO Slot
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
SDCBUS – – – – SDCSEL
SDCBUS BUS WIDTH
01 bit
1Reserved
2 4 bits
3 8 bits
SDCSEL SDCard/SDIO Slot
0 Slot A is selected.
1 Slot B is selected.
2 Reserved.
3 Reserved.
848
32072H–AVR32–10/2012
AT32UC3A3
31.7.5 Argument Register
Name: ARGR
Access Type: Read/Write
Offset: 0x010
Reset Value: 0x00000000
• ARG[31:0]: Command Argument
this field contains the argument field of the command.
31 30 29 28 27 26 25 24
ARG[31:24]
23 22 21 20 19 18 17 16
ARG[23:16]
15 14 13 12 11 10 9 8
ARG[15:8]
76543210
ARG[7:0]
849
32072H–AVR32–10/2012
AT32UC3A3
31.7.6 Command Register
Name: CMDR
Access Type: Write-only
Offset: 0x014
Reset Value: 0x00000000
This register is write-protected while SR.CMDRDY is zero. If an interrupt command is sent, this register is only writable by an
interrupt response (SPCMD field). This means that the current command execution cannot be interru pted or modified.
• BOOT_ACK: Boot Operation Acknowledge
The master can choose to receive the boot acknowledge from the slave when a Boot Request command is isssued.
Writi ng a one to this bit indicates that a Boot acknolwedge is expected within a programmable amount of time defined with
DTOMUL and DTOCYC fields located in the DTOR register. If the acknowledge pattern is not received then an acknowledge
timeout error is raised. If the acknowledge patte rn is corrupted then an acknowledge pattern error is set.
• ATACS: ATA with Command Completion Signal
Writing a one to this bit will configure ATA completion signal within a programmed amount of time in Completion Signal Time-out
Register (CSTOR).
Writing a zero to this bit will configure no ATA completion signal.
• IOSPCMD: SDIO Special Command
31 30 29 28 27 26 25 24
- - - - BOOTACK ATACS IOSPCMD
23 22 21 20 19 18 17 16
- - TRTYP TRDIR TRCMD
15 14 13 12 11 10 9 8
- - - MAXLAT OPDCMD SPCMD
76543210
RSPTYP CMDNB
IOSPCMD SDIO Special Command Type
0 Not a SDIO Special Comma nd
1 SDIO Suspend Command
2 SDIO Resume Command
3Reserved
850
32072H–AVR32–10/2012
AT32UC3A3
• TRTYP: Transfer T ype
• TRDIR: Transfer Direction
Writing a zero to this bit will configure the transfer direction as write transfer.
Writi ng a one to this bit will configure the transfer direction as read transfer.
• TRCMD: Transfer Command
• MAXLAT: Max Latency for Command to Response
Writing a zero to this bit will configure a 5-cycle max latency.
Writing a one to this bit will configure a 64-cycle max latency.
• OPDCMD: Open Drain Command
Writing a zero to this bit will configure the push-pull command.
Writing a one to this bit will configure the open-drain command.
• SPCMD: Special Command
TRTYP Transfer Type
0 MMC/SDCard Single Block
1 MMC/SDCard Multiple Block
2 MMC Stream
3 Reserved
4 SDIO Byte
5SDIO Block
others Reserved
TRCMD Trans fer Type
0 No data transfer
1 Start data transfer
2 Stop data tran s fer
3 Reserved
SPCMD Command
0 Not a special CMD.
1Initialization CMD:
74 clock cycles for initialization sequence.
2Synchronized CMD:
Wait for the end of the current data block transfer before sending the pending command.
3
CE-ATA Completion Signal disable Command.
The host cancels the ability for the device to return a command completion signal on the
command line.
4Interrupt command:
Corresponds to the Interrupt Mode (CMD40).
5Interrupt response:
Corresponds to the Interrupt Mode (CMD40).
others Reserved
851
32072H–AVR32–10/2012
AT32UC3A3
• RSPTYP: Response Type
• CMDNB: Command Number
The Command Number to transmit.
RSP Response Type
0 No response.
1 48-bit response.
2 136-bit response.
3 R1b response type
852
32072H–AVR32–10/2012
AT32UC3A3
31.7.7 Bl ock Register
Name: BLKR
Access Type: Read/Write
Offset: 0x018
Reset Value: 0x00000000
• BLKLEN: Data Block Length
This field determines the size of the data block.
This field is also accessible in the MR register.
If MR.FBYTE bit is zero, the BLKEN[17:16] field must be written to 0b00
Notes: 1. In SDIO Byte mode, BLKLEN field is not used.
2. BLKLEN should be specified before sending the data transfer command. Otherwise, Overrun
may occur (even if MR.RDPROOF bit is set).
• BCNT: MMC/SDIO Block Count - SDIO Byte Count
This field determines the number of data byte(s) or block(s) to transfer.
The transfer data type and the authorized values for BCNT field are determined by CMDR.TRTYP field:
Warning: In SDIO Byte and Block modes, writing to the sev en last bits of BCNT field is forbidden and ma y lead to unpredictable
results.
31 30 29 28 27 26 25 24
BLKLEN[15:8]
23 22 21 20 19 18 17 16
BLKLEN[7:0]
15 14 13 12 11 10 9 8
BCNT[15:8]
76543210
BCNT[7:0]
TRTYP Type of Transfer BCNT Authorized Values
0 MMC/SDCard Multiple Block From 1 to 65535: Value 0 corresponds to an infinite block transfer.
2 SDIO Byte From 1 to 512 bytes: Value 0 corresponds to a 512-byte transfer.
Values from 0x200 to 0xFFFF are forbidden.
3SDIO Block From 1 to 511 blocks: Value 0 corresponds to an infinite block transfer.
Values from 0x200 to 0xFFFF are forbidden.
Others - Reserved.
853
32072H–AVR32–10/2012
AT32UC3A3
31.7.8 Completion Signal Time-out Register
Name: CSTOR
Access Type: Read-write
Offset: 0x01C
Reset Value: 0x00000000
These two fields determines the maximum number of CLK_MCI cycles that the MCI waits between two data block transfers. Its
value is calculated by (CSTOCYC x Multiplier).
These two fields also determine the maximum number of CLK_MCI cycles that the MCI waits between the end of the data
transfer and the assertion of the completion signal. The data transfer comprises data phase and the optional busy phase. If a
non-DATA ATA command is issued, the MCI starts waiting immediately after the end of the response until the completion signal.
If the data time-out defined by CSTOCYC and CSTOMUL has been exceeded, the Completion Signal Time-out Error bit in the
SR register (SR.CSTOE) is set.
• CSTOMUL: Completion Signal Time-out Multiplier
Multiplier is defined by CSTOMUL as shown in the following table:
• CSTOCYC: Completion Signal Time-out Cycle Number
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
- CSTOMUL CSTOCYC
CSTOMUL Multiplier
01
116
2128
3256
4 1024
5 4096
6 65536
7 1048576
854
32072H–AVR32–10/2012
AT32UC3A3
31.7.9 Response Register n
Name: RSPRn
Access Type: Read-only
Offset: 0x020 + 0*0x04
Reset Value: 0x00000000
• RSP[31:0]: Response
The response register can be read by N access(es) at the same RSPRn or at consecutive addresses (0x20 + n*0x04).
N depends on the size of the response.
31 30 29 28 27 26 25 24
RSP[31:24]
23 22 21 20 19 18 17 16
RSP[23:16]
15 14 13 12 11 10 9 8
RSP[15:8]
76543210
RSP[7:0]
855
32072H–AVR32–10/2012
AT32UC3A3
31.7.10 Receive Data Register
Name: RDR
Access Type: Read-only
Offset: 0x030
Reset Value: 0x00000000
• DATA[31:0]: Data to Read
The last data received.
31 30 29 28 27 26 25 24
DATA[31:24]
23 22 21 20 19 18 17 16
DATA[23:16]
15 14 13 12 11 10 9 8
DATA[15:8]
76543210
DATA[7:0]
856
32072H–AVR32–10/2012
AT32UC3A3
31.7.11 Transmit Data Register
Name: TDR
Access Type: Write-only
Offset: 0x034
Reset Value: 0x00000000
• DATA[31:0]: Data to Write
The data to send.
31 30 29 28 27 26 25 24
DATA[31:24]
23 22 21 20 19 18 17 16
DATA[23:16]
15 14 13 12 11 10 9 8
DATA[15:8]
76543210
DATA[7:0]
857
32072H–AVR32–10/2012
AT32UC3A3
31.7.12 Status Register
Name: SR
Access Type: Read-only
Offset: 0x040
Reset Value: 0x0C000025
• ACKRCVE: Boot Operation Acknowledge Error
This bit is set when a corrupted Boot Acknowlegde signal has been received.
This bit is cleared by reading the SR register.
• ACKRCV: Boot Operation Acknowledge Received
This bit is set when a Boot acknowledg e signal has been received.
This bit is cleared by reading the SR register.
• UNRE: Underrun Error
This bit is set when at least one eight-bit data has been sent without vali d i nformation (not written).
This bit is cleared when sending a new data transfer command if the Flow Error bit reset control mode in Configuration Register
(CFG.FERRCTRL) is zero or when reading the SR register if CFG.FERRCTRL is one.
• OVRE: Overrun Error
This bit is set when at least one 8-bit received data has been lost (not read).
This bit is cleared when sending a new data transfer command if CFG.FERRCTRL is zero, or when readi ng the SR register if
CFG.FERRCTRL is one.
• XFRDONE: Transfer Done
This bit is set when the CR register is ready to operate and the data bus is in the idle state.
This bit is cleared when a transfer is in progress.
• FIFOEMPTY: FIFO empty
This bit is set when the FIFO is empty.
This bit is cleared when the FIFO contains at least one byte.
• DMADONE: DMA Transfer done
This bit is set when the DMA buffer transfer is completed.
This bit is cleared when reading the SR register.
• BLKOVRE: DMA Block Overrun Error
This bit is set when a new block of data is received and the D MA controller has not started to move the current pending block.
This bit is cleared when reading the SR register.
31 30 29 28 27 26 25 24
UNRE OVRE ACKRCVE ACKRCV XFRDONE FIFOEMPTY DMADONE BLKOVRE
23 22 21 20 19 18 17 16
CSTOE DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE
15 14 13 12 11 10 9 8
TXBUFE RXBUFF CSRCV SDIOWAIT - - SDIOIRQB SDIOIRQA
76543210
ENDTX ENDRX NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY
858
32072H–AVR32–10/2012
AT32UC3A3
• CSTOE: Completion Signal Time-out Error
This bit is set when the completion signal time-out defined by the CSTOR.CSTOCYC field and the CSTOR.CSTOMUL field is
reached.
This bit is cleared when reading the SR register.
• DTOE: Data Time-out Error
This bit is set when the data time-out defined by the DTOR.DTOCYC field and the DTOR.DTOMUL field is reached.
This bit is cleared when reading the SR register.
• DCRCE: Data CRC Error
This bit is set when a CRC16 error is detected in the last data block.
This bit is cleared when reading the SR register.
• RTOE: Response Time-out Error
This bit is set when the response time-out defined by the CMDR.MAXLAT bit is reached.
This bit is cleared when writing the CMDR register.
• RENDE: Response End Bit Error
This bit is set when the end bit of the response is not detected.
This bit is cleared when writing the CMDR register.
• RCRCE: Response CRC Error
This bit is set when a CRC7 error is detected in the response.
This bit is cleared when writing the CMDR register.
• RDIRE: Response Direction Error
This bit is set when the direction bit from card to host in the response is not detected.
This bit is cleared when writing the CMDR register.
• RINDE: Response Index Error
This bit is set when a mismatch is detected between the command index sent and the response index received.
This bit is cleared when writing the CMDR register.
• TXBUFE: TX Buffer Empty Status
This bit is set when the DMA Tx Buffer is empty.
This bit is cleared when the DMA Tx Buffer is not empty.
• RXBUFF: RX BU ffer Full Status
This bit is set when the DMA Rx Buffer is full.
This bit is cleared when the DMA Rx Buffer is not full.
• CSRCV: CE-ATA Completion Signal Received
This bit is set when the device issues a command completion signal on the command line.
This bit is cleared when reading the SR register.
• SDIOWAIT: SDIO Read Wait Operation Status
This bit is set when the data bus has entered IO wait state.
This bit is cleared when normal bus operation.
• SDIOIRQB: SDIO Interrupt for Slot B
This bit is cleared when reading the SR register.
This bit is set when a SDIO interrupt on Slot B occurs.
• SDIOIRQA: SDIO Interrupt for Slot A
This bit is set when a SDIO interrupt on Slot A occurs.
This bit is cleared when reading the SR register.
• ENDTX: End of RX Buffer
This bit is set when the DMA Controller transmission is finished.
This bit is cleared when the DMA Controller transmission is not finished.
• ENDRX: End of RX Buffer
This bit is set when the DMA Controller reception is finished.
This bit is cleared when the DMA Controller recep tio n is not finished.
• NOTBUSY: MCI Not Busy
This bit must be used only for write operations.
859
32072H–AVR32–10/2012
AT32UC3A3
A block write operation uses a simple busy signalling of the write operation duration on the data (DAT[0]) line: during a data
transfer block, if the card does not have a free data receiv e b uffer, the card indicates this condition by pulling down the data line
(DAT[0]) to LOW. The card stops pulling down the data line as soon as at least one rece ive buffer for the defined data transfer
block length becomes free.
The NOTBUSY bit allows to deal with these different states.
1: MCI is ready for new data transfer.
0: MCI is not ready for new data transfer.
This bit is cleared at the end of the card response.
This bit is set when the busy state on the data line is ended. This corresponds to a free internal data receive buffer of the card.
Refer to the MMC or SD Specification for more details concerning the busy behavior.
• DTIP: Data Transfer in Progress
This bit is set when the current data transfer is in progress.
This bit is cleared at the end of the CRC16 calculation
1: The current data transfer is still in progress.
0: No data transfer in progress.
• BLKE: Data Bloc k Ended
This bit must be used only for Write Operations.
This bit is set when a data block transf er has ended.
This bit is cleared when reading SR.
1: a data block transfer has ended, including the CRC16 Status transmission, the bit is set for each transmitted CRC Status.
0: A data block transfer is not yet finished.
Refer to the MMC or SD Specification for more details concerning the CRC Statu s.
• TXRDY: Transmit Ready
This bit is set when the last data written in the TDR register has been transferred.
This bit is cleared the last data written in the TDR register has not yet been transferred.
• RXRDY: Receiver Ready
This bit is set when the data has been received since the last read of the RDR register.
This bit is cleared when the data has not yet been received since the last read of the RDR register.
• CMDRDY: Command Ready
This bit is set when the last command has been sent.
This bit is cleared when writing the CMDR register
860
32072H–AVR32–10/2012
AT32UC3A3
31.7.13 Interrupt Enable Register
Name: IER
Access Type: Write-only
Offset: 0x044
Reset Value: 0x00000000
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will set the corresponding bit in IMR.
31 30 29 28 27 26 25 24
UNRE OVRE ACKRCVE ACKRCV XFRDONE FIFOEMPTY DMADONE BLKOVRE
23 22 21 20 19 18 17 16
CSTOE DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE
15 14 13 12 11 10 9 8
TXBUFF RXBUFF CSRCV SDIOWAIT - - SDIOIRQB SDIOIRQA
76543210
ENDTX ENDRX NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY
861
32072H–AVR32–10/2012
AT32UC3A3
31.7.14 Interrupt Disable Register
Name: IDR
Access Type: Write-only
Offset: 0x048
Reset Value: 0x00000000
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will clear the corresponding bit in IMR.
31 30 29 28 27 26 25 24
UNRE OVRE ACKRCVE ACKRCV XFRDONE FIFOEMPTY DMADONE BLKOVRE
23 22 21 20 19 18 17 16
CSTOE DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE
15 14 13 12 11 10 9 8
TXBUFF RXBUFF CSRCV SDIOWAIT - - SDIOIRQB SDIOIRQA
76543210
ENDTX ENDRX NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY
862
32072H–AVR32–10/2012
AT32UC3A3
31.7.15 Interrupt Mask Register
Name: IMR
Access Type: Read-only
Offset: 0x04C
Reset Value: 0x00000000
0: The corresponding interr upt is disabled.
1: The corresponding interrupt is enabled.
A bit in this register is cleared when the corresponding bit in IDR is wr itten to one.
A bit in this register is set when the corresponding bit in IER is written to one.
31 30 29 28 27 26 25 24
UNRE OVRE ACKRCVE ACKRCV XFRDONE FIFOEMPTY DMADONE BLKOVRE
23 22 21 20 19 18 17 16
CSTOE DTOE DCRCE RTOE RENDE RCRCE RDIRE RINDE
15 14 13 12 11 10 9 8
TXBUFF RXBUFF CSRCV SDIOWAIT - - SDIOIRQB SDIOIRQA
76543210
ENDTX ENDRX NOTBUSY DTIP BLKE TXRDY RXRDY CMDRDY
863
32072H–AVR32–10/2012
AT32UC3A3
31.7.16 DMA Configuration Register
Name: DMA
Access Type: Read/Write
Offset: 0x050
Reset Value: 0x00000000
• DMAEN: DMA Hardware Handshaking Enable
1: DMA Interface is enabled.
0: DMA interface is disabled.
To avoid unpredictable behavior, DMA hardware handshaking must be disabled when CPU transfers are performed.
To a v oid data losses , the DMA register should be initialized bef ore sending the data transf er command. This is also illustrated in
Figure 31-10 on page 831 or Figure 31-11 on page 833
• CHKSIZE: DMA Channel Read and Write Chunk Size
The CHKSIZE field indicates the number of data available when the DMA chunk transfer request is asserted.
• OFFSET: DMA Write Buffer Offset
This field indicates the number of discarded bytes when the DMA writes the first word of the transfer.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
-------DAMEN
76543210
- CHKSIZE - - OFFSET
CHKSIZE value Number of data transferred
0 1 Only available if FIFO_SIZE>= 16 bytes
1 4 Only available if FIFO_SIZE>= 32 bytes
2 8 Only available if FIFO_SIZE>= 64 bytes
3 16 Only availa ble if FIFO_SIZE>= 128 bytes
4 32 Only availa ble if FIFO_SIZE>= 256 bytes
others - Reserved
864
32072H–AVR32–10/2012
AT32UC3A3
31.7.17 Configuration Register
Name: CFG
Access Type: Read/Write
Offset: 0x054
Reset Value: 0x00000000
• LSYNC: Synchronize on the last block
1: The pending command is sent at the end of the block transfer when the transfer length is not infinite. (block count shall be
diff erent from zero)
0: The pending command is sent at the end of the current data block.
This register needs to configured before sending the data transfer command.
• HSMODE: High Speed Mode
1: The host controller outputs command line and data lines on the rising edge of the card clock. The Host driver shall check the
high speed support in the card registers.
0: Default bus timing mode.
• FERRCTRL: Flow Error bit reset control mode
1: When an underflow/overflow condition bit is set, reading SR resets the bit.
0: When an underflow/overflow condition bit is set, a new Write/Read command is needed to reset the bit.
• FIFOMODE: MCI Internal FIFO control mode
1: A write transfer starts as soon as one da ta is written into the FIFO.
0: A write transfer starts when a sufficien t amount of data is written into the FIFO.
When the block length is greater than or equal to 3/4 of the MCI internal FIFO size, then the write transfe r starts as soon as half
the FIFO is filled. When the block length is greater than or equal to half the internal FIFO size, then the write transfer starts as
soon as one quarter of the FIFO is filled. In other cases, the transfer starts as soon as the total amount of data is written in the
internal FIFO.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
---LSYNC---HSMODE
76543210
- - - FERRCTRL - - - FIFOMODE
865
32072H–AVR32–10/2012
AT32UC3A3
31.7.18 Write Protect Mode Register
Name: WPMR
Access Type: Read/Write
Offset: 0x0E4
Reset Value: 0x00000000
• WPKEY[23:0]: Write Protect ion Key password
This field should be written at value 0x4D4349 (ASCII code for “MCI”).
Writing any other value in this field has no effect.
• WPEN: Write Protection Enable
1: This bit enables the Write Protection if WPKEY corresponds.
0: This bit disables the Write Protection if WPKEY corresponds.
31 30 29 28 27 26 25 24
WPKEY[23:16]
23 22 21 20 19 18 17 16
WPKEY[15:8]
15 14 13 12 11 10 9 8
WPKEY[7:0]
76543210
-------WPEN
866
32072H–AVR32–10/2012
AT32UC3A3
31.7.19 Write Protect Status Register
Name: WPSR
Access Type: Read-only
Offset: 0x0E8
Reset Value: 0x00000000
• WPVSRC[15:0]: Write Protection Violation Source
This field contains address where the violation access occurs.
• WPVS: Write Protection Violation Status
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
WPVSRC[15:8]
15 14 13 12 11 10 9 8
WPVSRC[7:0]
76543210
---- WPVS
WPVS Definition
0No Write Protection Violation occurred since the last read of this
register (WPSR)
1Write Protection detected unauthorized attempt to write a control
register had occurred (since the last read.)
2Software reset had been performed while Write Protection was
enabled (since the last read).
3Both Write Protection violation and software reset with Write
Protection enabled had occurred since the last read.
others Reserved
867
32072H–AVR32–10/2012
AT32UC3A3
31.7.20 Version Register
Name: VERSION
Access: Read-only
Offset: 0x0FC
Reset Value: -
• VARIANT: Variant Number
Reserved. No functionality associated.
• VERSION: Version Number
Version number of the module. No functionality associate
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
----- VARIANT
15 14 13 12 11 10 9 8
- - - - VERSION[11:8]
76543210
VERSION[7:0]
868
32072H–AVR32–10/2012
AT32UC3A3
31.7.21 FIFO Memory Apert ure
Name: -
Access: Read/Write
Offset: 0x200 - 0x3FFC
Reset Value: 0x000000000
• DATA[31:0]:Data to read or Data to write
31 30 29 28 27 26 25 24
DATA[31:24]
23 22 21 20 19 18 17 16
DATA[23:16]
15 14 13 12 11 10 9 8
DATA[15:8]
76543210
DATA[7:0]
869
32072H–AVR32–10/2012
AT32UC3A3
31.8 Module Configuration
The specific configuration fo r the MCI instance is listed in the following tables.The module bus
clocks listed here are connected to the system bus clocks according to the table in the Power
Manager section.
Table 31-8. Module Clock Name
Module name Clock name
MCI CLK_MCI
Table 31-9. Parameter Value
Name Value
FIFO_SIZE 128
Table 31-10. Register Reset Values
Register Reset Value
VERSION 0x00000410
870
32072H–AVR32–10/2012
AT32UC3A3
32. Memory Stick Interface (MSI)
Rev: 2.1.0.0
32.1 Features •Memory Stick ver. 1.x & Memory Stick PRO support
•Memory Stick serial clock (serial mode: 20 MHz max., parallel mode: 40 MHz max.)
•Data transmit/receive FIFO of 64 bits x 4
•16 bits CRC circuit
•DMACA transfer support
•Card insertion/removal detection
32.2 Overview The Memory Stick Interface (MSI) is a host controller that supports Memory Stick Version 1.X
and Memory Stick PRO.
The communication protocol with the Memory Stick is started by write from the CPU to the com-
mand register. When the pro toco l fin ish es, t he CPU is noti fi ed that th e pr otocol has en ded by an
interrupt request. When the protocol is started and enters the data transfer state, data is
requested by issuing a DMA tr ansfer request (via DMACA) or an interru pt request to the CPU.
The RDY time out time when the handshake state (BS2 in read protocol, BS3 for write protocol)
is established in communication with the Memory Stick can be designated as the number of
Memory Stick transfer clocks. When a time out occ urs, the CPU is notified that the protoc ol has
ended due to a time ou t er ro r by an interrupt requ e st.
CRC circuit can be set off for test mode purpose. When CRC is off, CRC is not added to the data
transmitted to the Memory Stick.
An interrupt re quest can also b e issued to the CPU when a Memory Stick is insert ed or removed.
Figure 32-1. Read packet
RDY/BSY CRCDATATPC INTINT
BS0 BS1 BS2 BS3 BS0
BS
SDIO / DATA[3:0]
SCLK
Memory Stick Host Memory Stick
871
32072H–AVR32–10/2012
AT32UC3A3
Figure 32-2. Write packet
32.3 Block Diagram
Figure 32-3. MSI block diagram
32.4 Product Dependencies
32.4.1 GPIO SCLK, DATA[3..0], BS & INS are I/O lines, multiplexed with oth er I/O lines. The I/O controller
must be configured so that MSI can drive these I/O lines.
32.4.2 Power Manager
MSI is clocked through the Power Manager (PM), thus programmer must first configure the PM
to enable the CLK_MSI clock.
RDY/BSYCRCDATATPC INTINT
BS0 BS1 BS2 BS3 BS0
BS
SDIO / DATA[3:0]
SCLK
Memory Stick Host Memory Stick
Data buffer
MS I/F
FIFO
64 x 4
÷Registers PB
CLK_MSI
DATA3
DATA2
DATA1
SDIO / DATA0
SCLK
INS
BS
872
32072H–AVR32–10/2012
AT32UC3A3
32.4.3 Interrupt Controller
MSI interrupt line is connected to the Interrupt Controller. In order to handle interrupts, Interrupt
Controller(INTC) must be programmed before configuring MSI.
32.4.4 DMA Controller (DMACA)
Handshake signals are connected to DMACA. In order to accelerate transfer from/to flash card,
DMACA must be programmed before using MSI.
32.5 Connection to a Memory Stick
The Memory Stick serial clock (SCLK) is maximum 20 MHz in serial mode, and maxi-
mum 40 MHz in parallel mode. SCLK is derived from peripheral clock (CLK_MSI) :
f_SCLK = f_CLK_MSI / [2*(CLKDIV+1)] where CLKDIV = {0..255}.
Pin DATA[1] is a power supply for some Memory Stick version, so leaving the pull-
down resistor connected may result in wasteful current consumption. User should leave
the DATA[1] pin pull-down open when Memory Stick Ver. 1.x is inserted.
Table 32-1. Memory Stick pull-down configuration
Figure 32-4. Memory Stick pull-down overview
Memory Stick 1.x Memor y Stick PRO
Memory Stick inserted Pull-down open Pull-down enabled
Memory Stick removed Pull-down enabled Pull-down enabled
873
32072H–AVR32–10/2012
AT32UC3A3
32.6 Functional Description
32.6.1 Reset Operation
An internal reset (initialization of the internal registers and operating sequence) is performed
when PB reset is active or by setting S YS.RST= 1. RST bit is cleared to 0 after the internal reset
is completed.
The protocol currently being execu ted stops, and the internal operatin g sequence is initialized.
In addition, the FIFO is set to the empty state (SR.EMP=1, SR.FUL=0).
However, when the host controller is reset during communication with the Memory Stick, the
resulting bus state may differ from the Memory Stick. Therefore, when reset is performed during
communica tion , als o po we r- on -r es et the Memory Stick.
Internal regist ers are initiali zed t o their initial value. However, some bits in f ollowing r egisters a re
not affected by RST bit :
• SYS : CLKDIV[7:0],
• ISR : all bits but DRQ,
•SR : ISTA,
• IMR : all bits.
32.6.2 Commun ication with the Memory Stick
An example of communication with the Memory Stick is shown below. This example shows the
case when Transfer Protocol Command (TPC) SET_CMD is executed.
– Enabl e PEND and MSINT interrupt requests (write PEND=1, MSINT=1 in IER).
– Set FIFO direction to “CPU to MS” (write FDIR=1 in SYS).
– Write the command data to the FIFO (write DAT).
– Write the TPC and the data transfer size to the command register to start the
protocol (write CMD).
– After the prot ocol ends, an interrupt request is output from the host controller
(PEND=1 in ISR). To ac kno wledge this interrupt request, CPU must clear the source
of interrupt by writing PEND=1 in ISCR.
– Some TPC commands require additional time to be executed by Memory Stick
therefore INT can appear later after protocol end. After INT generation, an interrupt
request is output from the host controller (MSINT=1 in ISR). To acknowledge this
interrupt request, CPU must clear the source of interrupt by writing MSINT=1 in
ISCR.
When the command register is written, the communication protocol with the Memory Stick starts
and data transmit/receive is performed.
The data transfe r d irect ion is d et ermine d fro m TPC[ 3]. Whe n TPC[3] =0 , th e r ead prot ocol is pe r-
formed, and when TPC[3]=1, the write protocole is performed. When TPC[3] and FDIR bit differ,
the TPC[3] value is reflected to system register bit FDIR when the protocol starts.
FIFO can be written after protocol start therefore data must be written each time ISR.DRQ=1.
Even when the data is less than 8 bytes, always read and wr ite 8 bytes of data. All interr upt
874
32072H–AVR32–10/2012
AT32UC3A3
sources can be cleared by setting corresponding bit in ISCR but DRQ which is cleared once
FIFO has been rea d /written.
Figure 32-5. Communication example
32.6.3 Parallel Interface Mode Setting Procedure
Host controller supports parallel mode and must be set to parallel interface mode after t he Mem-
ory Stick.
– Identify the Mem ory Stick media and confirm it is a Memory Stick PR O. For Memory
stick med ia identification, see “Memory Stick Standard Format Specifications ver.
1.X Appendix D” or “Memory Stick Standard Format Specifications ver. 2.0
Application Notes 1.3 Medi a Identification Process”.
– Set the Memory Stick to parallel interface mode by executing TPC comman ds
SET_R/W_REG_ADRS then WRITE_REG to set System Parameter bit PAM=1.
– Write SRAC=0 and REI=0 to the system register (SYS) to switch host controller to
parallel interface mode.
– Change serial clock (SCLK) while communication is not being performed with the
Memory Stic k.
FIFO direction setting
Write to FIFO
TPC setting
Interrupt wait
MSSYS register
MSDAT register
MSCMD register
Protocol start
FDIR=1
CMD
TPC = SET_CMD
CPU MSI
Communication
with Memory Stick
Protocol end
MSISCR register
Interrupt enable MSIER register
PEND=1, MSINT=1
MSISR.PEND=1
Interrupt clear
PEND=1
Interrupt wait
Interrupt clear
MS INT wait
INT from
Memory Stick
INT received
MSISR.MSINT=1
MSISCR register
MSINT=1
875
32072H–AVR32–10/2012
AT32UC3A3
Figure 32-6. Interface mode switching sequence
32.6.4 Data transfer re quests
After the communication protocol with the Memory Stick starts, a data transfer request is
asserted to the CPU (DRQ bit in ISR) and to DMACA (internal signals), until data transfer of the
amount indicated by DSZ (CMD) is finished. However, the data transfer request stops when the
internal FIFO becomes either empty or full.
Like CPU, DMACA uses Peripheral Bus to access FIFO so it is not recommended to access MSI
registers during transfer. It is also not reco mmende d to enable DRQ inter rupt because ISR.DRQ
bit is automatically cleared when FIFO is accessed.
DMACA channel should be configured first and the data size should be a multiple of 64 bits
(FIFO size is 4 * 64bits).
32.6.5 Interrupts The interrupt sources of MSI are :
• PEND : protocol command ended without error.
• DRQ : data request, FIFO is full or empty.
• MSINT : interrupt received from Memory Stick.
• CRC : protocol ended with CRC error.
• TOE : protocol ended with time out error.
• CD : card detected (inserted or removed).
Each interrupt so ur ce can be en ab led in In te rr up t En ab le r eg iste r ( IER) an d dis ab led in In te rr up t
Disable register (IDR). The enable status is read in Interrupt Mask register (IMR). The status of
WRITE_REG TPC
system parameter
(PAM bit)
SET_R/W_REG_ADRS TPC
Set Parallel Interface Mode
(MSSYS.SRAC=0, MSSYS.REI=0)
Serial Interface Mode
(MSSYS.SRAC=1, MSSYS.REI=1)
Error
OK
Change SCLK
(MSSYS.CLKDIV[7:0]=X)
876
32072H–AVR32–10/2012
AT32UC3A3
the interrupt source, even if the interrupt is masked, can be read in ISR.
DRQ interrupt request is cleared by reading (reception) or writing (transmission) FIFO, other
interrupt reque st s are cleare d by writin g 1 to th e co rrespo ndin g bit in In te rrupt Sta tus Clea r Reg-
ister (ISCR).
32.6.6 OCD mode There is no OC D mode for MSI.
32.7 User Interface
Table 32-2. MSI Register Memory Map
Offset Register Name Access Reset State
0x0000 Command register CMD Read/Write 0x00000000
0x0004 Data register DAT Read/Write 0x4C004C00
0x0008 Status register SR Read Only 0x00001020
0x000C System register SYS Read/Write 0x00004015
0x0010 Interrupt Status register ISR Read Only 0x00000000
0x0014 Interrupt Status Clear register ISCR Write Only 0x00000000
0x0018 Interrupt Enable register IER Write Only 0x00000000
0x001C Interrupt Disable register IDR Write Only 0x00000000
0x0020 Interrupt Mask register IMR Read Only 0x00000000
0x0024 Version register VERSION Read Only 0x00000210
877
32072H–AVR32–10/2012
AT32UC3A3
32.7.1 Command register
Name : CMD
Access Type : Read/Write
Offset : 0x00
Reset Value : 0x00000000
•TPC : Transfer Protocol Code.
TPC[3] indicates the tra nsfer direction of data (1:write packet, 0:read packet)
•DSL : Data Select.
0 : Data is transmitted to and received from Memory Stick using the internal FIFO.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
TPC - DSL DSZ
76543210
DSZ
code (dec) TPC Description
2READ_LONG_DATA Transfer data f rom Data Buffer (512 bytes)
3READ_SHORT_DATA Transfer data from Data Buffer (32~256 bytes)
4 READ_REG Read from a registe r
7GET_INT Read from an INT register
8 SET_R/W_REG_ADRS Set an address of READ_REG/WRITE_REG
9 EX_SET_CMD Set command and parameters
11 WRITE_REG Write to a register
12 WRITE_SHORT_DATA Transfer data to Data Buffer (32~256 bytes)
13 WRITE_LONG_DATA Transfer data to Data Buffer (512 bytes)
14 SET_CMD Set command
other - Banned for use
878
32072H–AVR32–10/2012
AT32UC3A3
1 : Reserved.
•DSZ : Data size.
Length can be set from 1 byte to 1024 bytes. However, 1024 bytes is set when DSZ=0 .
879
32072H–AVR32–10/2012
AT32UC3A3
32.7.2 Data register
Name : DAT
Access Type : Read/Write
Offset : 0x04
Reset Value : 0x4C004C00
This register is used to acces internal FIFO.
Even when the data is less than 8 bytes, always read and write 8 bytes of data.
31 30 29 28 27 26 25 24
DATA
23 22 21 20 19 18 17 16
DATA
15 14 13 12 11 10 9 8
DATA
76543210
DATA
880
32072H–AVR32–10/2012
AT32UC3A3
32.7.3 Status register
Name : SR
Access Type : Read Only
Offset : 0x08
Reset Value : 0x00001020
•ISTA : Insertion Status. It reflects the Memory Stick card presence. This is the inverse of INS pin.
0 : No card.
1 : Card is inserted.
•RDY : Ready. RDY go es to 1 when the protocol ends. This bi t bit is cleared to 0 by write to the command register.
0 : Command receive disabl ed due to communication with the Memory Stick.
1 : Command received or protocol ended.
•EMP : FIFO Empty. This bit is set to 1 by writing system register bit FCLR=1.
0 : FIFO contains data.
1 : FIFO is empty.
•FUL : FIFO Full. This bit is cleared to 0 by writing system register bit FCLR=1.
0 : FIFO has empty space.
1 : FIFO is full.
•CED : MS Command End.
In parallel mode, this bit reflects the CED bit in the status register of a Memory Stick (INT). Indicates the end of a
command executed with SET_CMD TPC. In serial mode, this bit is always 0. It is cleared to 0 by writing to the command
register (CMD).
•ERR : Memory Stick Error.
In parallel mode, th is bit ref lect s the ERR bit in the stat us re gister of a Memor y Stick ( INT). It indicates t he occur ence
of an error. In serial mode, this bit is always 0. It is cleared to 0 by writing to the command register (CMD).
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
-------ISTA
15 14 13 12 11 10 9 8
---RDY----
76543210
- - EMP FUL CED ERR BRQ CNK
881
32072H–AVR32–10/2012
AT32UC3A3
•BRQ : MS Data Buffer Request.
In parallel mode, this bit reflects the BREQ bit in the status register of a Memory Stick (INT). It indicates that a host
has requested to access a Memory Sticks page buffer.In serial mode, this bit is always 0. It is cleared to 0 by writing to the
command register (CMD).
•CNK : MS Command No Acknowledge.
In parallel mode, this bit reflects the CMDNK bit in the status register of a Memory Stick (INT). It indicates that the
command cannot be executed. In serial mode, this bit is always 0. It is cleared to 0 by writing to the command register
(CMD).
882
32072H–AVR32–10/2012
AT32UC3A3
32.7.4 System register
Name : SYS
Access Type : Read/Write
Offset : 0x0C
Reset Value : 0x00004015
•CLKDIV : Clock Division.
Write this field to change SCLK frequency = CLK_MSI / (2*(CLKDIV+1)).
•RST : Reset. When RST is written, internal synchronous reset is performed.
0 : This bit is cleared to 0 after the internal reset is completed.
1 : Writing a 1 starts reset operation.
•SRAC : Serial Access Mode. The SRAC cannot be changed during protocol execution.
0 : Write this bit to 0 to set parallel mode.
1 : Write this bit to 1 to set serial mode.
•NOCRC : No CRC computation.
0 : Write 0 to enable CRC ou tput . Dur ing read pr otocol, the CRC che ck is perfo rmed as usua l re gardle ss of NO CRC.
1 : Write 1 to disa ble CRC output. When NOCRC=1, the write protocol is executed without adding the CRC data.
•FCLR : FIFO clear.
Write 1 to initialize FIFO data. This bit is cleared af ter the FIFO is initialized.
•FDIR : FIFO direction.
0 : Write 0 to set the FIFO direction to transmit.
1 : Write 1 to set the FIFO direction to receive.
•REI : Rising Edge Input. When setting parallel mode, set REI=0. This setting cannot be ch anged during protocol execution.
0 : Write 0 to sample data at the falling edge of SCLK.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
CLKDIV
15 14 13 12 11 10 9 8
RST SRAC - NOCRC - - FCLR FDIR
76543210
- - - REI REO BSY
883
32072H–AVR32–10/2012
AT32UC3A3
1 : Write 1 to sa mple data at the rising edge of SCLK.
•REO : Rising Edge output. This bit is used when not fixed hold time by the side of the Memory Stick in parallel
communication. This setting cannot be changed during protocol execution.
0 : Write 0 to synchronize outputs with the falling edge of SCLK.
1 : Write 1 to synchronize outputs with the rising edge of SCLK.
•BSY : Busy Count. This is the maximum BSY wait time until the RDY signal is output from the Memory Stick.
0 : Write a value to configure time out = BSY * 4 SCLK.
1 : Write 0 to disable time out detection.
884
32072H–AVR32–10/2012
AT32UC3A3
32.7.5 Interrupt Status register
Name : ISR
Access Type : Read Only
Offset : 0x10
Reset Value : 0x00000000
•CD : Card Detection.
0 : No card detected. This bit is cleared when the correponding bit in ISCR is set to 1.
1 : This bit is set to 1 when a Memory Stick card is inserted or removed.
•TOE : Time Out Error.
0 : This bit is cleared to 0 when the corresponding bit in ISCR it set to 1.
1 : This bit is set to 1 when protol ended with time out error.
•CRC : CRC error.
0 : No CRC error. This bit is cleared when the corresponding bit in ISCR is set to 1.
1 : This bit is set when protocol ends with CRC error.
•MSINT : Memory Stick interruption.
0 : This bit is cleared to 0 when the corresponding bit in ISCR is set to 1.
1 : This bit is set to 1 when an interrupt request INT is received from Memory Stick.
•DRQ : Data request, FIFO is full (reception) or empty (transmission).
0 : This bit is cleared to 0 when data access is no more required.
1 : This bit is set to 1 when data access is required (read or write).
•PEND : Protocol End.
0 : This bit is cleared to 0 when the corresponding bit in ISCR is set to 1.
1 : This bit is set to 1 when protol ended witout error.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
- - CD TOE CRC MSINT DRQ PEND
885
32072H–AVR32–10/2012
AT32UC3A3
32.7.6 Interrupt Status Clear register
Name : ISCR
Access Type : Write Only
Offset : 0x14
Reset Value : 0x00000000
•CD : Card Detection clear bit.
0 : Writing 0 has no effect.
1 : Writing 1 clears corresponding bit in ISR.
•TOE : Time Out Error clear bit.
0 : Writing 0 has no effect.
1 : Writing 1 clears corresponding bit in ISR.
•CRC : CRC error clear bit.
0 : Writing 0 has no effect.
1 : Writing 1 clears corresponding bit in ISR.
•MSINT : Memory Stick interruption clear bit.
0 : Writing 0 has no effect.
1 : Writing 1 clears corresponding bit in ISR.
•PEND : Protocol End c lear bit.
0 : Writing 0 has no effect.
1 : Writing 1 clears corresponding bit in ISR.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
- - CD TOE CRC MSINT - PEND
886
32072H–AVR32–10/2012
AT32UC3A3
32.7.7 Interrupt Enable register
Name : IER
Access Type : Write Only
Offset : 0x18
Reset Value : 0x00000000
•CD : Card Detection interrupt enable.
0 : Writing 0 has no effect.
1 : Writing 1 set to 1 corresponding bit in IMR.
•TOE : Time Out Error interrupt enable.
0 : Writing 0 has no effect.
1 : Writing 1 set to 1 corresponding bit in IMR.
•CRC : CRC error interrupt enable.
0 : Writing 0 has no effect.
1 : Writing 1 set to 1 corresponding bit in IMR.
•MSINT : Memory Stick interrupt enable.
0 : Writing 0 has no effect.
1 : Writing 1 set to 1 corresponding bit in IMR.
•DRQ : Data Request interrupt enable.
0 : Writing 0 has no effect.
1 : Writing 1 set to 1 corresponding bit in IMR.
•PEND : Protocol End interrupt enable.
0 : Writing 0 has no effect.
1 : Writing 1 set to 1 corresponding bit in IMR.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
- - CD TOE CRC MSINT DRQ PEND
887
32072H–AVR32–10/2012
AT32UC3A3
32.7.8 Interrupt Disable register
Name : IDR
Access Type : Write Only
Offset : 0x1C
Reset Value : 0x00000000
•CD : Card Detection interrupt disable.
0 : Writing 0 has no effect.
1 : Writing 1 clears to 0 corresponding bit in IMR.
•TOE : Time Out Error interrupt disable.
0 : Writing 0 has no effect.
1 : Writing 1 clears to 0 corresponding bit in IMR.
•CRC : CRC error interrupt disable.
0 : Writing 0 has no effect.
1 : Writing 1 clears to 0 corresponding bit in IMR.
•MSINT : Memory Stick interrupt disable.
0 : Writing 0 has no effect.
1 : Writing 1 clears to 0 corresponding bit in IMR.
•DRQ : Data Request interrupt disable.
0 : Writing 0 has no effect.
1 : Writing 1 clears to 0 corresponding bit in IMR.
•PEND : Protocol End interrupt disable.
0 : Writing 0 has no effect.
1 : Writing 1 clears to 0 corresponding bit in IMR.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
- - CD TOE CRC MSINT DRQ PEND
888
32072H–AVR32–10/2012
AT32UC3A3
32.7.9 Interrupt Mask register
Name : IMR
Access Type : Read Only
Offset : 0x20
Reset Value : 0x00000000
•CD : Card Detection interrupt mask.
0 : Interrupt is disabled.
1 : Interrupt is enabled.
•TOE : Time Out Error interrupt mask.
0 : Interrupt is disabled.
1 : Interrupt is enabled.
•CRC : CRC error interrupt mask.
0 : Interrupt is disabled.
1 : Interrupt is enabled.
•MSINT : Memory Stick interrupt mask.
0 : Interrupt is disabled.
1 : Interrupt is enabled.
•DRQ : Data Request interrupt mask.
0 : Interrupt is disabled.
1 : Interrupt is enabled.
•PEND : Protocol End interrupt mask.
0 : Interrupt is disabled.
1 : Interrupt is enabled.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
- - CD TOE CRC MSINT DRQ PEND
889
32072H–AVR32–10/2012
AT32UC3A3
32.7.10 Version Register
Name : VERSION
Access Type : Read Only
Offset : 0x24
Reset Value : 0x00000210
•VARIANT: Variant Number
Reserved. No functionality associated.
•VERSION : Version Number
Version number of the module. No functionality associated.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
---- VARIANT
15 14 13 12 11 10 9 8
---- VERSION[11:8]
76543210
VERSION[7:0]
890
32072H–AVR32–10/2012
AT32UC3A3
33. Advanced Encryption Standard (AES)
Rev: 1.2.3.1
33.1 Features •Compliant with FIPS Publication 197, Advanced Encryption Standard (AES)
•128-bit/19 2 - bi t/2 5 6-bit cryptographic key
•12/14/16 clock cycles encryption/decryption processing time with a 128-bit/192-bit/256 -bit
cryptographic key
•Support of the five standard modes of operation specified in the NIST Special Publication 800-
38A, Recommendation for Block Cipher Modes of Operation - Methods and Techniques:
– Electronic Code Book (ECB)
– Cipher Block Chaining (CBC)
– Cipher Feedback (CFB)
– Output Feedback (OFB)
– Counter (CTR)
•8-, 16-, 32-, 64- and 128-bit data size possible in CFB mode
•Last output data mode allows optimized Message Authentication Code (MAC) generation
•Hardware counter measures against differential power analysis attacks
•Connection to DMA Controller capabilities optimizes data transfers for all operatin g mo des
33.2 Overview The Advanced Encryption Standard (AES) is compliant with the American FIPS (Federal Infor-
mation Processing Standard) Publication 197 specification.
The AES suppor ts all five confidentiality modes of operation for symmetrical key block cipher
algorithms (ECB, CBC, OFB, CFB and CTR), as specified in the NIST Special Publication 800-
38A Recommendation. It is compatible with all these modes via DMA Controller, minimizing pro-
cessor intervention for large buffer transfers.
The 128-bit/192-bit/256-bit key is stored in write-only four/six/eight 32-bit KEY Word Registers
(KEYWnR) which are all write-only registers.
The 128-bit input data and initialization vector (for some modes) are each stored in 32-bit Input
Data Registers (IDATAnR) and in Initialization Vector Registers (VnR) which are all write-only
registers.
As soon as the initialization vector, the input data and the key are configured, the encryp -
tion/decryption process may be started. Then the encrypted/decrypted data is ready to be read
out on the four 32-bit Output Data Registers (ODATAnR) or through the DMA Controller.
33.3 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
33.3.1 Power Management
If the CPU enters a sleep mode that disables clocks used by the AES, the AES will stop function-
ing and resume operation after the system wakes up from sleep mode.
891
32072H–AVR32–10/2012
AT32UC3A3
33.3.2 Clocks The clock for the AES bus interface (CLK_AES) is generated by the Pow er Manager. This clock
is enabled at reset, and can be disabled in t he Power Ma nager. It is r ecommended to di sable the
AES before disabling the clock, to avoid freezing the AES in an undefined state.
33.3.3 Interrupts The AES interrupt request line is connected to the interrupt controller. Using the AES interrupt
requires the interrupt controller to be programmed first.
33.4 Functional Description
The AES specifies a FIPS-approved cryptographic algorithm that can be used to protect elec-
tronic data. The AES algorithm is a symmetric block cipher that can en crypt (encipher) and
decrypt (decipher) information.
Encryption converts data to an unintelligible form called ciphertext. Decrypting the ciphertext
converts the data back into its original form, called pla intext. The Processing Mode bit in the
Mode Register (MR.CIPHER) allows selection between the encryption and the decryption
processes.
The AES is capable of using cryptographic keys of 128/192/256 bits to encrypt and decrypt data
in blocks of 128 bits. This 128-bit/192-bit/256-bit key is defined in the KEYWnR Registers
(KEYWnR).
The input to the encryp tion pr ocesses of the CBC, CF B, and OFB mod es includes, in addi tion to
the plaintext, a 128-bit data block called the initialization vector, which must be writing in the Ini-
tialization Vector Registers (IVnR). The initialization vector is used in an initial step in the
encryption of a messa ge and in the co rr espo nding decr yptio n of t he messag e. The IVRnR regis-
ters are also used in th e CTR mode to set the counter value.
33.4.1 Operation Modes
The AES supports the following modes of operation:
• ECB: Electronic Code Book
• CBC: Cipher Block Chaining
• OFB: Output Feedback
• CFB: Cipher Feedback
– CFB8 (CFB where the length of the data segment is 8 bits)
– CFB16 (CFB wh er e th e len gt h of th e da ta seg me n t is 16 bits )
– CFB32 (CFB wh er e th e len gt h of th e da ta seg me n t is 32 bits )
– CFB64 (CFB wh er e th e len gt h of th e da ta seg me n t is 64 bits )
– CFB128 (CFB where the length of the data segment is 128 bits)
•CTR: Counter
The data pre-processing, post-processing and chaining for the concerned modes are automati-
cally perform ed. Refer to the NIST Special Publication 800-38A Recommendation for more
complete information.
These modes are selected by writing the Operation Mode field in the Mode Register
(MR.OPMOD).
In CFB mode, five data size are possible (8 bits, 16 bits, 32 bits, 64 bits or 128 bits).
892
32072H–AVR32–10/2012
AT32UC3A3
These sizes are selected by writing the Cipher Feedback Data Size field in the MR register
(MR.CFDS).
33.4.2 Start Modes The Start Mode field in the MR register (MR.SMOD) allows selection of the encryption (or
decryption) start mode.
33.4.2.1 Manual mode
The sequence is as follows:
• Write the 128-bit/192-bit/256-bit key in the KEYWnR registers.
• Write the initialization vector (or counter) in the IVnR registers.
Note: The Initialization Vector Registers concern all modes except ECB.
• Write the Data Ready bit in the Interrupt Enable Register (IER.DATRDY), depending on
whether an interrupt is required or not at the end of processing.
• Write the data to be encrypted/decrypted in the authorized Input Data Registers (IDATAnR).
Note: In 64-bit CFB mode, writing to IDATA3R and IDATA4R registers is not allowed and may lead to
errors in processing.
Note: In 32-bit, 16-bit and 8-bit CFB modes, writing to IDATA2R, IDATA3R and IDATA4R registers is not
allowed and may lead to errors in processing.
• Write the START bit in the Control Register (CR.START) to begin the encryption or the
decryption pr ocess.
• When the processing completes, the DATRDY bit in the Interrupt Status Register
(ISR.DATRDY) is set.
• If an interrupt has been enabled b y writing the IER.DATRDY bit, the interrupt line of the AES
is activated.
• When the software reads one of the Out pu t Data Reg ist ers (ODATAxR), the ISR.DATRDY bit
is cleared.
33.4.2.2 Automatic mode
The automatic mode is similar to the manual one, except that in this mode, as soon as the cor-
rect number of IDATAnR Registers is written, processing is automatically started without any
action in the CR register.
Table 33-1. Authorized In pu t Dat a Reg ist er s
Operation Mode IDATAnR to Write
ECB All
CBC All
OFB All
128-bit CFB All
64-bit CFB IDATA1R and IDATA2R
32-bit CFB IDATA1R
16-bit CFB IDATA1R
8-bit CFB IDATA1R
CTR All
893
32072H–AVR32–10/2012
AT32UC3A3
33.4.2.3 DMA mode The DMA Co ntroller can be used in asso ciation with the AES to perform an e ncryption/decryp-
tion of a buffe r without any action by the software during processing.
In this starting mode, the type of the data transfer (byte, halfword or word) depends on the oper-
ation mode.
The sequence is as follows:
• Write the 128-bit/192-bit/256-bit key in the KEYWnR registers.
• Write the initialization vector (or counter) in the IVnR registers.
Note: The Initialization Vector Registers concern all modes except ECB.
• Configure a channel of the DMA Controller with source address (data buffer to
encrypt/decrypt) and destination address set to register IDATA1R (index is automatically
incremented and rolled ov er to write IDATAnR). Then configure a second channel with source
address set to ODATA1R (index is automatically increme nted and rolled over to read
ODATAnR) and destination addr ess to write processed data.
Note: Transmit and receive buffers can be identical.
• Enable the DMA Controller in transmission and reception to start the processing.
• The processing complet ion should be monitored with the DMA Controller.
33.4.3 Last Output Data Mode
This mode is used to generate cryptographic checksums on data (MAC) by means of cipher
block chaining encrypti on algorithm (CBC-MAC algorithm for example).
After each end of encryption/decryption, the output data is available either on the ODATAnR
registers for manua l and automati c mode or at the address specif ied in the receive buf fer pointer
for DMA mode.
The Last Output Data bit in the Mode Register (MR.LOD) allows retrieval of only the last data of
several encryption/decryption processes.
Therefore, there is no need to define a read buffer in DMA mode.
This data is only available on the Output Data Registers (ODATAnR).
Table 33-2. Data Transfer Type for the Different Operation Modes
Operation Mode Data Transfer Type (DMA)
ECB word
CBC word
OFB word
CFB 128-bit word
CFB 64-bit word
CFB 32-bit word
CFB 16-bit halfword
CFB 8-bit byte
CTR word
894
32072H–AVR32–10/2012
AT32UC3A3
33.4.3.1 Manual and automatic modes
• When MR.LOD is zero
The ISR.DATRDY bit is cleared when at least one of the ODATAnR registers is read.
Figure 33-1. Manual and Automatic Modes when MR.LOD is zero
If the user does not want to read the output data registers between each encryption/decryption,
the ISR.DATRDY bit will not be cleared. If the ISR.DATRDY bit is not cleared, the user cannot
know the end of the following encryptions/decryptions.
• When MR.LOD is one
The ISR.DATRDY bit is cleared when at least one IDATAnR register is writt en, so before th e
start of a new transfer. No more ODATAnR register reads are necessary between consecutive
encryptions/decryptions.
Figure 33-2. Manual and Automatic Mode s when MR.LOD is one
33.4.3.2 DMA mode • when MR.LOD is zero
The end of the encryption/decryption should be monitored with the DMA Controller.
Write CR.START (Manual mode)
Or
Write IDATAnR register(s) (Auto mode)
ISR.DATRDY
Encryption or Decryption Process
Read ODATAnR register(s)
Write IDATAnR register(s)
Encryption or Decryption Process
Write CR.START(Manual mode)
or
Write IDATAnR register(s) (Auto mode)
ISR.DATRDY
895
32072H–AVR32–10/2012
AT32UC3A3
Figure 33-3. DMA Mode when MR.LOD is zero
• when MR.LOD is one
The user must first wait for the DMA Controller Interrupt, then for ISR.DATRDY to ensure that
the encryption/decryption is completed.
In this case, no receive buffers are required.
The output data is only available in ODATAnR registers.
Figure 33-4. DMA Mode when MR.LOD is one
Following table summarizes the different cases.
Note: 1. Depending on the mode, there are other ways of clearing the DATRDY.ISR bit. See the Interrupt Status Register (ISR)
definition.
Warning: In DMA mode, reading to the ODATAnR registers before the last data transfer may lead to unpredictable results.
DMA Controller Interrupt
Multiple encryption or decryption processes
Enable DMA Controller Channels (Receive and Transmit Channels)
Enable DMA Controller Channels (only Transmit Channel)
ISR.DATRDY
Multiple Encryption or Decryption Processes
DMA Controller Interrupt
Table 33-3. Last Output Mode Behavior versus Start Modes
Manual and Automatic Modes DMA Mode
MR.LOD = 0 MR.LOD = 1 MR.LOD = 0 MR.LOD = 1
ISR.DA TRDY bit Clearing
Condition(1) At least one ODATAnR
register must be read At least one IDATAnR
register must be written Not used Managed by the DMA
Controller
Encrypted/Decrypted
Data Result Location In ODATAnR registers In ODATAnR registers
At the address
specified in the
configuration of
DMA Controller
In ODATAnR registers
End of
Encryption/Decryption ISR.DATRDY ISR.DATRDY DMA Controller
Interrupt
DMA Controller
Interrupt then
DATRDY.ISR
896
32072H–AVR32–10/2012
AT32UC3A3
33.4.4 Security Features
33.4.4.1 Countermeasures
The AES also features hardware countermeasures that can be useful to protect data against Di f-
ferential Power Analysis (DPA) attacks.
These countermeasures can be enabled through the Countermeasure Type field in the MR reg-
ister (MR.CTYPE). This field is write-only, and all changes to it are taken into account if, at the
same time, the Countermeasure Ke y field in the Mode Register (MR.CKEY) is correctly written
(see the Mode Register (MR) d escription in Section 33.5.2).
Note: Enabling countermeasures has an impact on the AES encryption/decryption throug hput.
By default, all the coun termeasures are enabled.
The best throughput is achieved with all the countermeasures disabled. On the other hand, the
best protection is achieved with all of them enabled.
The Random Number Generator Seed Loading bit in the CR register (CR.LOADSEED) allows a
new seed to be loaded in the embedded random number generator used for the different
countermeasures.
33.4.4.2 Unspecified register access detection
When an unspecified register access occurs, the Unspecified Register Detection Status bit in
the ISR registe r (ISR.URAD) is set to one. Its s ource is then reported in the Unspecified Register
Access Type field in the ISR register (ISR.URAT). Only the last unspecified register access is
available through the ISR.URAT field.
Several kinds of unspecified register accesses can occur when:
• Writing the IDATAnR registers during the data processing in DMA mode
• Reading the ODATAnR registers during data processing
• Writing the MR register during data pr ocessing
• Reading the ODATAnR registers during sub-keys generation
• Writing the MR register during sub-keys generation
• Reading an write-only regis te r
The ISR.URAD bit and t he ISR.URAT f ield can o nly be reset b y the Softwa re Reset b it in t he CR
register (CR.SWRST).
897
32072H–AVR32–10/2012
AT32UC3A3
33.5 User Interface
Note: 1. The reset value are device specific. Please refer to the Module Configuration section at the end of this chapter.
Table 33-4. AES Register Memory Map
Offset Register Register Name Access Reset
0x00 Control Register CR Write-only 0x00000000
0x04 Mode Register MR Read/Write 0x00000000
0x10 Interrupt Enable Register IER Write-only 0x00000000
0x14 Interrupt Disable Register IDR Write-only 0x00000000
0x18 Interrupt Mask Register IMR Read-only 0x00000000
0x1C Interrupt Status Register ISR Read-only 0x0000001E
0x20 Key Word 1 Register KEYW1R Write-only 0x00000000
0x24 Key Word 2 Register KEYW2R Write-only 0x00000000
0x28 Key Word 3 Register KEYW3R Write-only 0x00000000
0x2C Key Word 4 Register KEYW4R Write-only 0x00000000
0x30 Key Word 5 Register KEYW5R Write-only 0x00000000
0x34 Key Word 6 Register KEYW6R Write-only 0x00000000
0x38 Key Word 7 Register KEYW7R Write-only 0x00000000
0x3C Key Word 8 Register KEYW8R Write-only 0x00000000
0x40 Input Data 1 Register IDATA1R Write-only 0x00000000
0x44 Input Data 2 Register IDATA2R Write-only 0x00000000
0x48 Input Data 3 Register IDATA3R Write-only 0x00000000
0x4C Input Data 4 Register IDATA4R Write-only 0x00000000
0x50 Output Data 1 Register ODATA1R Read-only 0x00000000
0x54 Output Data 2 Register ODATA2R Read-only 0xC01F0000
0x58 Output Data 3 Register ODATA3R Read-only 0x00000000
0x5C Output Data 4 Register ODATA4R Read-only 0x00000000
0x60 Initialization Vector 1 Register IV1R Wri te-o nly 0x00000000
0x64 Initialization Vector 2 Register IV2R Wri te-o nly 0x00000000
0x68 Initialization Vector 3 Register IV3R Wri te-o nly 0x00000000
0x6C Initialization Ve ctor 4 Register IV4R Write-only 0x00000000
0xFC Version Register VR Read-only -(1)
898
32072H–AVR32–10/2012
AT32UC3A3
33.5.1 Control Register
Name: CR
Access Type: Write-only
Offset: 0x00
Reset Value: 0x00000000
• LOADSEED: Random Number Generator Seed Loading
Writing a one to this bit will load a new seed in the embedded random number generator used for the different
countermeasures.
writing a zero to this bit has no effect.
• SWRST : Software Reset
Writing a one to this bit will reset the AES.
writing a zero to this bit has no effect.
• START: Start Processing
Writing a one to this bit will start manual encryption/decryption process.
writing a zero to this bit has no effect.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
- - - - - - - LOADSEED
15 14 13 12 11 10 9 8
-------SWRST
76543210
-------START
899
32072H–AVR32–10/2012
AT32UC3A3
33.5.2 Mode Register
Name: MR
Access Type: Read/Write
Offset: 0x04
Reset Value: 0x00000000
• CTYPE: Countermeasure Type
All the countermeasures are enabled by default.
CTYPE field is write-only and can only be modified if CKEY is correctly set.
31 30 29 28 27 26 25 24
- - - CTYPE
23 22 21 20 19 18 17 16
CKEY - CFBS
15 14 13 12 11 10 9 8
LOD OPMOD KEYSIZE SMOD
76543210
PROCDLY - - - CIPHER
CTYPE Description
XXXX0Countermeasure type 1 is disabled
XXXX1
Add random spurious power consumption during some configuration
settings
X X X 0 X Countermeasure type 2 is disabled
X X X 1 X Add randomly 1 cycle to processing.
X X 0 X X Countermeasure type 3 is disabled
X X 1 X X Add randomly 1 cycle to processing (other version)
X 0 X X X Countermeasure type 4 is disabled
X 1 X X X Add randomly up to /13/15 cycles (for /192/256-bit k ey) to processing
0XXXXCountermeasure type 5 is disabled
1XXXX
Add random spurious power consumption during processing
(recommended with DMA access)
900
32072H–AVR32–10/2012
AT32UC3A3
• CKEY: Countermeasure Key
Writing the value 0xE to this field allows the CTYPE field to be modified.
Writi ng another value to this field has no effect.
This bit alw ays reads as zero.
• CFBS: Cipher Feedback Data Size
• LOD: Last Output Data Mode
Writing a one to this bit will enabled the LOD mode.
Writing a zero to this bit will disabled the LOD mode.
These mode is described in the Table 33-3 on page 895.
• OPMOD: Operation Mode
• KEYSIZE: Key Size
CFBS Description
0 128-bit
1 64-bit
2 32-bit
3 16-bit
48-bit
Others Reserved
OPMOD Description
0 ECB: Electronic Cod e Bo ok mode
1 CBC: Cipher Block Chaining mode
2 OFB: Output Feedback mode
3 CFB: Cipher Feedback mode
4 CTR: Counter mode
Others Reserved
KEYSIZE Description
0 AES Key Size is 128 bits
1 AES Key Size is 192 bits
Others AES Key Size is 256 bits
901
32072H–AVR32–10/2012
AT32UC3A3
• SMOD: Start Mode
• PROCDLY: Processing Delay
The processing time represents the number of clock cycles that the AES needs in order to perform one encr yption/decr y ption
with no countermeasures activated:
The best performance is achieved with PROCDLY equal to 0.
Writing a value to this field will update the processing time.
Reading this field will give the current processing delay.
• CIPHER: Processing Mode
0: Decr ypts data is enabled.
1: Encrypts data is enabled.
SMOD Description
0 Manual mode
1 Automatic mode
2
DMA mode
• LOD = 0: The encrypted/decrypted data are a v ailab le at the address sp ecified in the
configur ation of DMA Controller.
• LOD = 1: The encrypted/decrypted data are available in the ODATAnR registers.
3 Reserved
Processing Time 12 PROCDLY 1+()×=
902
32072H–AVR32–10/2012
AT32UC3A3
33.5.3 Interrupt Enable Register
Name: IER
Access Type: Write-only
Offset: 0x10
Reset Value: 0x00000000
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will set the corresponding bit in IMR.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
-------URAD
76543210
-------DATRDY
903
32072H–AVR32–10/2012
AT32UC3A3
33.5.4 Interrupt Disable Register
Name: IDR
Access Type: Write-only
Offset: 0x14
Reset Value: 0x00000000
Writing a zero to a bit in this register has no effect.
Writing a one to a bit in this register will clear the corresponding bit in IMR.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
-------URAD
76543210
-------DATRDY
904
32072H–AVR32–10/2012
AT32UC3A3
33.5.5 Interrupt Mask Register
Name: IMR
Access Type: Read-only
Offset: 0x18
Reset Value: 0x00000000
0: The corresponding interr upt is disabled.
1: The corresponding interrupt is enabled.
A bit in this register is cleared when the corresponding bit in IDR is wr itten to one.
A bit in this register is set when the corresponding bit in IER is written to one.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
-------URAD
76543210
-------DATRDY
905
32072H–AVR32–10/2012
AT32UC3A3
33.5.6 Interrupt Status Register
Name: ISR
Access Type: Read-only
Offset: 0x1C
Reset Value: 0x0000001E
• URAT: Unspecified Register Access Type:
Only the last Unspecified Register Access Type is available through the URAT field.
This field is reset to 0 when SWRST bit in the Control Register is wr itten to one.
• URAD: Unspecified Register Acce ss Detection Status
This bit is set when at least one unspecified register access has been detected since the last software reset.
This bit is cleared when SWRST bit in the Control Register is set to one.
•
•
•
•
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
URAT - - - URAD
76543210
-------DATRDY
URAT Description
0 The IDATAnR register during th e data processing in DMA mode.
1 The ODATAnR register read during the data processing.
2 The MR register written during the data processing.
3 The ODATAnR register read during the sub-keys generation.
4 The MR register written during the sub-keys generation.
5 Write-only register read access.
Others Reserved
906
32072H–AVR32–10/2012
AT32UC3A3
• DATRDY: Data Ready
This bit is set/clear as described in the Table 33-3 on page 895.
This bit is also cleared when SWRST bit in the Control Register is set to one.
907
32072H–AVR32–10/2012
AT32UC3A3
33.5.7 Key Word n Register
Name: KEYWnR
Access Type: Write-only
Offset: 0x20 +(n-1)*0x04
Reset Value: 0x00000000
• KEYWn[31:0]: Key Word n
Writing the 128-bit/192-bit/256-bit cryptographic key used for enc ryption/decr y ption in the four/six/eight 32-bit K ey Word
registers.
KEYW1 corresponds to the first word of the key and respective ly KEYW4/KEYW6/KEYW8 to the last one.
This field always read as zero to prevent the key from being read by another application.
31 30 29 28 27 26 25 24
KEYWn[31:24]
23 22 21 20 19 18 17 16
KEYWn[23:16]
15 14 13 12 11 10 9 8
KEYWn[15:8]
76543210
KEYWn[7:0]
908
32072H–AVR32–10/2012
AT32UC3A3
33.5.8 Input Data n Register
Name: IDATAnR
Access Type: Write-only
Offset: 0x40 + (n-1)*0x04
Reset Value: 0x00000000
• IDATAn[31:0]: Input Data Word n
Writi ng the 128-bit data block used for encryption/decryption in the four 32-bit Input Data registers.
IDATA1 corresponds to the first word of the data to be encrypted/decrypted, and IDATA4 to the last one.
This field always read as zero to prevent the input data from being read by another application.
31 30 29 28 27 26 25 24
IDATAn[31:24]
23 22 21 20 19 18 17 16
IDATAn[23:16]
15 14 13 12 11 10 9 8
IDATAn[15:8]
76543210
IDATAn[7:0]
909
32072H–AVR32–10/2012
AT32UC3A3
33.5.9 Output Data n Register
Name: ODATAnR
Access Type: Read-only
Offset: 0x50 + (n-1)*0x04
Reset Value: 0x00000000
• ODATAn[31:0]: Output Data n
Reading the four 32-bit ODATAnR give the 128-bit data block that has been encrypted/decrypted.
ODATA1 corresponds to the first word, ODATA4 to the last one.
31 30 29 28 27 26 25 24
ODATAn[31:24]
23 22 21 20 19 18 17 16
ODATAn[23:16]
15 14 13 12 11 10 9 8
ODATAn[15:8]
76543210
ODATAn[7:0]
910
32072H–AVR32–10/2012
AT32UC3A3
33.5.10 Initialization Vector n Register
Name: IVnR
Access Type: Write-only
Offset: 0x60 + (n-1)*0x04
Reset Value: 0x00000000
• IVn[31:0]: Initialization Vector n
The four 32-bit Initialization Vector registers set the 128-bit Initialization Vector data block that is used by some modes of
operation as an additional initial input:
IV1 corresponds to the first word of the Initialization Vector, IV4 to the last one.
This field is always read as zero to prevent the Initialization Vector from being read by another application.
31 30 29 28 27 26 25 24
IVn[31:24]
23 22 21 20 19 18 17 16
IVn[23:16]
15 14 13 12 11 10 9 8
IVn[15:8]
76543210
IVn[7:0]
MODE(OPMODE. Description
CBC,OFB, CFB initialization vector
CTR counter value
ECB not used, must not be written
911
32072H–AVR32–10/2012
AT32UC3A3
33.5.11 Version Register
Name: VERSION
Access Type: Read-only
Offset: 0xFC
Reset Value: -
• VARIANT: Variant Number
Reserved. No functionality associated.
• VERSION[11:0]
Version number of the module. No functionality associated.
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
---- VARIANT
15 14 13 12 11 10 9 8
- - - - VERSION[11:8]
76543210
VERSION[7:0]
912
32072H–AVR32–10/2012
AT32UC3A3
33.6 Module Configuration
The specific configuration for each AES instance is listed in the following tables.The module bus
clocks listed here are connected to the system bus clocks according to the table in the System
Bus Clock Connections section.
Table 33-5. Module clock name
Module name Clock name
AES CLK_AES
Table 33-6. Register Reset Values
Register Reset Value
VERSION 0x00000123
913
32072H–AVR32–10/2012
AT32UC3A3
34. Audio Bitstream DAC (ABDAC)
Rev: 1.0.1.1
34.1 Features •Digital Stereo DAC
•Oversampled D/A conversion architecture
– Oversampling ratio fixed 128x
– FIR equalizati on filter
– Digital interpolation fil ter: Co mb4
– 3rd Order Sigma-Delta D/A converters
•Digital bitstream outputs
•Parallel interface
•Connected to DMA Controller for background transfer without CPU intervention
34.2 Overview The Audio Bitstream DAC converts a 16-bit sample value to a digital bitstream with an average
value proportional to the sample value. Two channels are supported, making the Audio Bit-
stream DAC particularly suitable for ster eo audio. Each channel has a pair of complementary
digital outputs, DATAn and DATANn, which can be connected to an external high input imped-
ance amplifier.
The output DATAn an d DATANn should be as ideal as possible before filter ing, to achieve the
best SNR and THD quality. The outputs can be connected to a class D amplifier output stage to
drive a speaker directly, or it can be low pass filtered and connected to a high input impedance
amplifier. A simple 1st order low pass filt er th at filter s all the frequ encie s above 50kHz should be
adequate when a pplying the signal to a speaker or a band limited amplifier, as the speaker or
amplifier will act as a filter and remove high frequency components from the signal. In some
cases high frequen cy co mpo nents m i ght b e f olded do wn in to t he aud ible ra ng e, and in t hat ca se
a higher order f ilter is require d. For performance m easurements on d igital equipm ent a minimum
of 4th order low pass filter should be used. This is to prevent aliasing in the measurements.
For the best performance when not using a class D amplifier approach, the two outputs DATAn
and DATANn, should be applied to a differential stage amplifier, as this will increase the SNR
and THD.
914
32072H–AVR32–10/2012
AT32UC3A3
34.3 Block Diagram
Figure 34-1. ABDAC Block Diagram
34.4 I/O Lines Description
34.5 Product Dependencies
In order to use t his modu le, othe r p arts o f th e syst em must be conf igu red cor re ctly, as de scr ibed
below.
34.5.1 I/O Lines The output pins used f or t he ou tput bit str ea m fro m t he Aud io Bit str eam DAC may b e multip lexed
with IO lines.
Before using the Audio Bitstream DAC, the I/O Controller must be configured in order for the
Audio Bitstream DAC I/O lines to be in Audio Bitstream DAC peripheral mode.
Table 34-1. I/O Lines Description
Pin Name Pin Description Type
DATA0 Output from Audio Bitstream DAC Channel 0 Output
DATA1 Output from Audio Bitstream DAC Channel 1 Output
DATAN0 Inve rted output from Audio Bitstream DAC Channel 0 Output
DATAN1 Inve rted output from Audio Bitstream DAC Channel 1 Output
Clock Generator
Equalization FIR COMB
(INT=128)
Sigma-Delta
DA-MOD
Equalization FIR COMB
(INT=128)
Sigma-Delta
DA-MOD
bit_clk
DATA0
DATA1
GCLK_ABDAC
sample_clk
CHANNEL0[15:0]
Audio Bitstream DAC
PM
User Interface
CHANNEL1[15:0]
915
32072H–AVR32–10/2012
AT32UC3A3
34.5.2 Clocks The CLK_ABDAC to the Audi o Bitstr eam DAC is gener ated by the Power Ma nager (PM). Befo re
using the Audio Bitstream DAC, the user must ensure that the Audio Bitstream DAC clock is
enabled in the Power Manager.
The ABDAC needs a separate clock for the D/A conversion operation. This clock,
GCLK_ABDAC should be set up in the Generic Clock register in the Power Manager and its fre-
quency must be as follow:
where fs is the samping rate of the data stream to convert. For fs= 48kHz this means that the
GCLK_ABDAC clock must have a frequency of 12.288MHz.
The two clocks, CLK_ABDAC and GCLK_ABDAC, must be in phase with each other.
34.5.3 Interrupts The ABDAC interrupt request line is connected to the interrupt controller. Using the ABDAC
interrupt requires the interrupt controller to be programmed first.
34.6 Functional Description
34.6.1 How to Initialize the Module
In order to use the Audio Bitstream DAC the prod uct dependencies given in Section 34.5 on
page 914 must be resolved. Particular attention should be given to the configuration of clocks
and I/O lines in order to ensure correct operation of the Audio Bitstream DAC.
The Audio Bitstream DAC is enabled by writing a one to the enable bit in the Audio Bitstream
DAC Control Register (CR.EN).
The Transmit Ready Interrupt Status bit in the Interrupt Status Register (ISR.TXREADY) will be
set whenever the ABDAC is read y to re ce ive a new samp le. A new samp le valu e should b e writ-
ten to SDR before 256 ABDAC clock cycles, or an underrun will occur, as indicated by the
Underrun Interrupt Status bit in ISR (ISR.UND ERRUN). ISR is cleared w hen read, or w hen writ-
ing one to the corresponding bits in the Interrupt Clear Register (ICR).
34.6.2 Data Format The input data format is two’s complement. Two 16-bit sample values for channel 0 and 1 can
be written to the least and most significant halfword of the Sample Data Register (SDR),
respectively.
An input value of 0x7FFF will result in an output voltage of approximately:
An Input value of 0x8000 will result in an output value of approximately:
fGCLK 256 fS
×=
VOUT 0x7FFF()
38
128
----------VDDIO 38
128
----------33,⋅ 0≈98V,=⋅≈
VOUT 0x8000()
90
128
----------VDDIO 90
128
----------33,⋅ 2≈32V,=⋅≈
916
32072H–AVR32–10/2012
AT32UC3A3
If one want to get coherence between the sign of the input data and the output voltage one can
use the DATAN signal or invert the sign of the input data by software.
34.6.3 Data SwappingWhen the SWAP bit in the ABDAC Control Register (CR.SWAP) is written to one, writing to the
Sample Data Register (SDR) will cause the values written to the C HANNEL0 and CHANNEL1
fields to be swapped.
34.6.4 Peripheral DMA Controller
The Audio Bitstream DAC is connected to the Peripheral DMA Controller. The Peripheral DMA
Controller c an be programmed t o automatically transfer s amples to the Audio Bitst ream DAC
Sample Data Register (SDR) when the Audio Bitstream DAC is ready for new sa mples. In this
case only the CR.EN bit needs to be set in the Audio Bitstream DAC module. This enables the
Audio Bitstream DAC to operate without any CPU intervention such as polling the Interrupt Sta-
tus Register (ISR ) or using interrupts. See the Peripheral DMA Con troller documentation for
details on how to setup Per ipheral DMA transfers.
34.6.5 Construction The Audio Bitstream DAC is constructed of two 3rd order Sigma-Delta D/A converter with an
oversampling ratio of 128. The samples are upsampl ed with a 4th order Sinc interpolation filter
(Comb4) before bein g applied to the Sigma-Delta Modulator. In order to compensate for the
pass band frequency response of the interpolation filter and flatten the overall frequency
response, the input to the interpolation filter is first filtered with a simple 3-tap FIR filter.The total
frequency response of the Equali zatio n FIR f ilte r and th e int erpo lat ion filte r is give n in Figure 34-
2 on page 917. The digital output bitstreams from the Sigma-Delta Modulators should be low-
pass filtered to remove high frequency noise insert ed by the modulation process.
34.6.6 Equalization Filter
The equalization filter is a simple 3-tap FIR filter. The purpose of this filter is to compensate for
the pass band frequency response of the sinc interpolation filter. The equalization filter makes
the pass band response more flat and moves the -3dB corner a little higher.
34.6.7 Interpolation Filter
The interpolation filter interpolates from fs to 128fs. This f i lt er is a 4thorder Casc ad e d Integrat or -
Comb filter, and the basic building blocks of this filter is a comb part and an integrator part.
34.6.8 Sigma-Delta Modulat or
This part is a 3rdorder Sigma-Delta Modulator consisting of three differentiators (delta blocks),
three integrators (sigma blocks) and a one bit q uantizer. The purpose of the integrators is to
shape the noise, so that the noise is reduced in the band of interest and increased at the higher
frequencies, where it can be filtered.
917
32072H–AVR32–10/2012
AT32UC3A3
34.6.9 Frequency Response
Figure 34-2. Frequency Respon se, EQ-FIR+COMB4
012345678910
x 10
4
-60
-50
-40
-30
-20
-10
0
10
Frequenc y [F s]
A m plitude [dB ]
918
32072H–AVR32–10/2012
AT32UC3A3
34.7 User Interface
Table 34-2. ABDAC Register Memory Map
Offset Register Register Name Access Reset
0x00 Sample Data Register SDR Read/Write 0x00000000
0x08 Control Register CR Read/Write 0x00000000
0x0C Interrupt Mask Register IMR Read-only 0x00000000
0x10 Interrupt Enable Register IER Write-only 0x00000000
0x14 Interrupt Disable Register IDR Write-only 0x00000000
0x18 Interrupt Clear Register ICR Write-only 0x00000000
0x1C Interrupt Status Register ISR Read-only 0x00000000
919
32072H–AVR32–10/2012
AT32UC3A3
34.7.1 Sample Data Register
Name: SDR
Access Type: Read/Write
Offset: 0x00
Reset Value: 0x00000000
• CHANNEL1: Sample Data for Channel 1
signed 16-bit Sample Data for channel 1.
• CHANNEL0: Signed 16-bit Sample Data for Channel 0
signed 16-bit Sample Data for channel 0.
31 30 29 28 27 26 25 24
CHANNEL1[15:8]
23 22 21 20 19 18 17 16
CHANNEL1[7:0]
15 14 13 12 11 10 9 8
CHANNEL0[15:8]
76543210
CHANNEL0[7:0]
920
32072H–AVR32–10/2012
AT32UC3A3
34.7.2 Control Register
Name: CR
Access Type: Read/Write
Offset: 0x08
Reset Value: 0x00000000
•EN: Enable Audio Bitstream DAC
1: The module is enabled.
0: The module is disabled.
•SWAP: Swap Channels
1: The swap of CHANNEL0 and CHANNEL1 samples is enabled.
0: The swap of CHANNEL0 and CHANNEL1 samples is disabled.
31 30 29 28 27 26 25 24
ENSWAP------
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
--------
921
32072H–AVR32–10/2012
AT32UC3A3
34.7.3 Interrupt Mask Register
Name: IMR
Access Type: Read-only
Offset: 0x0C
Reset Value: 0x00000000
1: The corresponding interrupt is enabled.
0: The corresponding interr upt is disabled.
A bit in this register is set when the corresponding bit in IER is written to one.
A bit in this register is cleared when the corresponding bit in IDR is wr itten to one.
31 30 29 28 27 26 25 24
--TXREADYUNDERRUN----
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
--------
922
32072H–AVR32–10/2012
AT32UC3A3
34.7.4 Interrupt Enable Register
Name: IER
Access Type: Write-only
Offset: 0x10
Reset Value: 0x00000000
Writing a one to a bit in this register will set the corresponding bit in IMR.
Writing a zero to a bit in this register has no effect.
31 30 29 28 27 26 25 24
--TXREADYUNDERRUN----
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
--------
923
32072H–AVR32–10/2012
AT32UC3A3
34.7.5 Interrupt Disable Register
Name: IDR
Access Type: Write-only
Offset: 0x14
Reset Value: 0x00000000
Writing a one to a bit in this register will clear the corresponding bit in IMR.
Writing a zero to a bit in this register has no effect.
31 30 29 28 27 26 25 24
--TXREADYUNDERRUN----
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
--------
924
32072H–AVR32–10/2012
AT32UC3A3
34.7.6 Interrupt Clear Register
Name: ICR
Access Type: Write-only
Offset: 0x18
Reset Value: 0x00000000
Writing a one to a bit in this register will clear the corresponding bit in ISR and the corresponding interrupt request.
Writing a zero to a bit in this register has no effect.
31 30 29 28 27 26 25 24
--TXREADYUNDERRUN----
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
--------
925
32072H–AVR32–10/2012
AT32UC3A3
34.7.7 Interrupt Status Register
Name: ISR
Access Type: Read-only
Offset: 0x1C
Reset Value: 0x00000000
•TXREADY: TX Ready Interrupt Status
This bit is set when the Audio Bitstream DAC is ready to receive a new data in SDR.
This bit is cleared when the Audio Bitstream DAC is not ready to receive a new data in SDR.
•UNDERRUN: Underrun Interrupt Status
This bit is set when at least one Audio Bitstream DAC Underrun has occurred since the last time this bit was cleared (by reset or
by writing in ICR).
This bit is cleared when no Audio Bitstream DAC Underrun has occurred since the last time this bit was cleared (by reset or by
writing in IC R).
31 30 29 28 27 26 25 24
--TXREADYUNDERRUN----
23 22 21 20 19 18 17 16
--------
15 14 13 12 11 10 9 8
--------
76543210
--------
926
32072H–AVR32–10/2012
AT32UC3A3
35. Programming and Debugging
35.1 Overview General descriptio n of progr amming and debug fea tures, bl ock diagram an d introd uction of main
concepts.
35.2 Service Access Bus
The AVR32 architecture of fe rs a common int e rface f or acce ss t o On-Chip Debug , pro gra mming,
and test functions. These are mapped on a common bus called the Service Access Bus (SAB),
which is linked to the JT AG por t thro ug h a bu s ma st er mo du le , whic h a lso h an d les sy nchroniza-
tion between the debugger and SAB clocks.
When accessing the SAB through the debugger there are no limitations on debugger frequency
compared to ch ip fr equ en cy, alt hough t her e must be an a ctive syste m clock in ord er for t h e SAB
accesses to complete. If the system clock is switched off in sleep mod e, activity on the debugg er
will restart the system clock automatically, without waking the device from sleep. Debuggers
may optimize the transfer rate by adjusting the frequency in relation to the system clock. This
ratio can be measured with debug protocol specific instructions.
The Service Access Bus uses 36 address bits to address memory or registers in any of the
slaves on the bus. The bus supports sized accesses of bytes (8 bits), halfwords (16 bits), or
words (32 bits). All accesses must be aligned to the size of the access, i.e. halfword accesses
must have the lowest address bit clear ed, and word accesse s must have the two lowest address
bits cleared.
35.2.1 SAB address map
The Service Access Bus (SAB) gives the user access to the internal address space and other
features through a 36 bits ad dress space. The 4 MSBs identify the slave number, while the 32
LSBs are decoded within the slave’s address space. The SAB slaves ar e shown in Table 35-1
on page 926.
35.2.2 SAB security restrictions
The Service Access bus can be restricted by internal security measures. A short description of
the security measures are found in the table below.
Table 35-1. SAB Slaves, addresses and descriptions.
Slave Address [35:32] Description
Unallocated 0x0 Intentionally unallocated
OCD 0x1 OCD registers
HSB 0x4 HSB memor y space, as seen by the CPU
HSB 0x5 Alternative mapping for HSB space, for compatibility with
other 32-bit AVR devices.
Memory Service
Unit 0x6 Memory Service Unit registers
Reserved Other Unused
927
32072H–AVR32–10/2012
AT32UC3A3
35.2.2.1 Security measure and control location
A security measure is a mechanism to either block or allow SAB access to a certain address or
address range. A security measur e is enabled or disabled by one or several control signals. This
is called the control location for t he security measure.
These securit y measures can be used to pr event an end user from re ading out the code pro -
grammed in the flash, for instance .
Below follows a more in depth description of what locations are accessible when the security
measures are active.
Table 35-2. SAB Security measures.
Security measure Control Location Descriptio n
Security bit FLASHC security
bit set Progr amming and debugging not possible , very restricted
access.
User code
programming FLASHC UPROT
+ security bit set
Restri cts all access except parts of the flash and the flash
controller for programming user code. Debuggin g is not
possible unless an OS running from the secure part of the
flash supports it.
Table 35-3. Security bit SAB restrictions
Name Address start Address end Access
OCD DCCPU,
OCD DCEMU,
OCD DCSR 0x100000110 0x100000118 Read/Write
User page 0x580800000 0x581000000 Read
Other accesses - - Blocked
Table 35-4. User code programming SAB restrictions
Name Address start Address end Access
OCD DCCPU,
OCD DCEMU,
OCD DCSR 0x100000110 0x100000118 Read/Write
User page 0x580800000 0x581000000 Read
FLASHC PB
interface 0x5FFFE0000 0x5FFFE0400 Read/Write
FLASH pages
outside
BOOTPROT
0x580000000 +
BOOTPROT size 0x580000000 + Flash size Read/Write
Other accesses - - Blocked
928
32072H–AVR32–10/2012
AT32UC3A3
35.3 On-Chip Debug (OCD)
Rev: 1.4.2.1
35.3.1 Features •Debug interface in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0) Class 2+
•JTAG acces s to all on-chip debug function s
•Advanced program, data, o w nership, and watchpoint trace supported
•NanoTrace JTAG-based trace access
•Au xiliary port for high-speed trace information
•Hardware support for 6 program and 2 data breakpoints
•Unlimited number of software breakpoints supported
•A utomatic CRC ch e ck of memory regions
35.3.2 Overview Debu gging on the AT32UC3A3 is facilitated by a powerful On-Chip Debug (OCD) system. The
user accesses this through an external debug too l which connects to the JTAG p ort and the Aux-
iliary (AUX) port. The AUX port is primarily used for trace functions, and a JTAG-based
debugger is sufficient for basic debugging.
The debug system is based on the Nexus 2.0 standard, class 2+, which includes:
• Basic run-time control
• Program breakpoints
• Data breakpoints
•Program trace
• Ownership trace
• Data trace
In addition to the mandatory Nexus debug features, the AT32UC3A3 implements several useful
OCD features, such as:
• Debug Communicati on Channel between CPU and JTAG
• Run-time PC monitoring
• CRC checking
• NanoTrace
• Software Quality Assurance (SQA) support
The OCD features are controlled by OCD registers, which can be accessed by JTAG when the
NEXUS_ACCESS JTAG instruction is loaded. The CPU can also access OCD registers directly
using mtdr/mfdr instructions in any privileged mode. The OCD registers are implemented based
on the recommenda tions in the Ne xus 2.0 standard, and are detailed in t he AVR32UC Technical
Reference Manual.
929
32072H–AVR32–10/2012
AT32UC3A3
35.3.3 Block Diagram
Figure 35-1. On-Chip Debug Block Diagram
35.3.4 JTAG-based Debug Features
A debugger can control all OCD features by writing OCD registers over the JTAG interface.
Many of these d o not depe nd on out put on t he AUX por t, allowing a JTAG-based de bugger to be
used.
A JTAG-based debugg er sh ould co nnect t o t he d evice th ro ugh a st anda rd 10- pin I DC con nect or
as described in the AVR32UC Technical Reference Manual.
On-Chip Debug
JTAG
Debug PC
Debug
Instruction
CPU
Breakpoints
Program
Trace Data Trace Ownership
Trace
WatchpointsTransmit Queue
AUX
JTAG
Internal
SRAM
Service Access Bus
Memory
Service
Unit
HSB Bus Matrix Memories and
peripherals
930
32072H–AVR32–10/2012
AT32UC3A3
Figure 35-2. JTAG-based Debugger
35.3.4.1 Debug Communication Channel
The Debug Communication Channel (DCC) consists of a pair OCD registers with associated
handshake logic, accessible to both CPU and JTAG. The registers can be used to exchange
data between the CPU and the JTAG master, both runtime as well as in debug mode.
35.3.4.2 breakpoints One of the most fundamental debug features is the ability to halt the CPU, to examine registers
and the state of the system. This is accomplished by breakpoints, of which many types are
available:
• Unconditional breakpoints are set by writing OCD registers by JTAG, halting the CPU
immediately.
• Program breakpoints halt the CPU when a specific address in the program is executed.
• Data breakpoints halt the CPU when a specific memory address is read or written, allowing
variables to be watched.
• Software breakpoints halt the CPU when the breakpoint instruction is executed.
When a breakpoint triggers, the CPU enters debug mode, and the D bit in the Status Register is
set. This is a privileged mode with dedicated return address and return status registers. All privi-
leged instructions are permitted. Debug mode can be entered as either OCD mode, running
instructions from JTAG, or monitor mode, running instr uctions from program memory.
AVR32
JTAG-based
debug tool
PC
JTAG
10-pin IDC
931
32072H–AVR32–10/2012
AT32UC3A3
35.3.4.3 OCD mode When a br eakpoint triggers, the CPU enters OCD mode, an d instructions are fetch ed from the
Debug Instruction OCD register. Each time this register is written by JTAG, the instruction is
executed, allowing the JTAG to execute CPU instructions directly. Th e JTAG master can e.g.
read out the register file by issu ing mtdr instructions to the CPU, writing each register to th e
Debug Communication Channel OCD registers.
35.3.4.4 monitor mode
Since the OCD registers are directly accessible by the CPU, it is possible to build a software-
based debugger that runs on the CPU itself. Setting the Monitor Mode bit in the Development
Control registe r causes the CPU t o enter monit or mode instea d of OCD mode wh en a breakpo int
triggers. Monitor mode is similar to OCD mode, except that instructions are fetched from the
debug exception vector in regular program memory, in stead of issued by JTAG.
35.3.4.5 program counter monitoring
Normally, the CPU would need to be halted for a JTAG-based debugger to examine the current
PC value. However, the AT32UC3A3 provides a Debug Program Counter OCD register, where
the debugger can continuously read the current PC without affecting the CPU. This allows the
debugger to generate a simple statistic of the time spent in various areas of the code, easing
code optimization.
35.3.5 Memory Service Unit
The Memory Ser vice Unit (MSU) is a block de dicated to test and debu g functionality. It is con-
trolled through a dedicated set of registers addressed through the MEMORY_SERVICE JTAG
command.
35.3.5.1 Cyclic Redundancy Check (CRC)
The MSU can be used to automatically calculate the CRC of a block of data in memory. The
OCD will then read out each word in the specified memory block and report the CRC32-v alue in
an OCD register.
35.3.5.2 NanoTrace The MSU additionally supports NanoTrace. This is an AVR32-specific feature, in which trace
data is output to memory instead of the AUX port. This allows the trace data to be extracted by
JTAG MEMORY_ACCESS, enabling trace features for JTAG-based debuggers. The user must
write MSU registers to conf igure t he ad dress an d size of the memory bl ock to be used for Nano-
Trace. The NanoTrace buffer can be anywhere in the physical address range, in cluding inte rnal
and external RAM, th roug h an EBI, if present . Th is area may not be used by the app lication ru n-
ning on the CPU.
35.3.6 AUX-based Debug Features
Utilizing the Auxiliary (AUX) port gives access to a wide range of advanced debug features. Of
prime importance are th e trace features, which allow an external de bugger to rece ive continuous
information on the program execution in the CPU. Additionally, Event In and Event Out pins
allow external events to be correlated with the program flow.
The AUX port contains a number of pins, as shown in Table 35-5 on page 932. These are multi-
plexed with I/O Controller lines, and must explicitly be enabled by writing OCD registers before
the debug session starts. The AUX port is mapped to two different locations, selectable by OCD
Registers, minimizing the chance that the AUX port will need to be shared with an application.
932
32072H–AVR32–10/2012
AT32UC3A3
Debug tools utilizing the AUX port should connect to the device through a Nexus-compliant Mic-
tor-38 connector, as described in the AVR32UC Technical Reference manual. This connector
includes the JTAG signals and the RESET_N pin, giving full access to the programming and
debug featur es in the device.
Figure 35-3. AUX+JTAG based Debugger
35.3.6.1 trace operation
Trace features a re enable d by writ ing OCD registe rs by JTAG. Th e OCD ext racts t he trace infor-
mation from the CPU, compresses this information and formats it into variable-length messages
according to the Nexu s standa rd. The messages are buff ered in a 16-fra me transm it queue , and
are output on the AUX port one frame at a time.
Table 35-5. Auxiliary Port Signals
Signal Direction Description
MCKO Output Trace data output clock
MDO[5:0] Output Trace data output
MSEO[1:0] Output Trace frame control
EVTI_N Input Event In
EVTO_N Output Event Out
AVR32
AUX+JTAG
debug tool
JTAG
AUX
high speed
Mictor38
Trace buffer
PC
933
32072H–AVR32–10/2012
AT32UC3A3
The trace features can be configured to be very selective, to reduce the bandwidth on the AUX
port. In case the transmit queue overflows, error messages are produced to indicate loss of
data. The transmit queue module can opt ionally be conf igured to halt t he CPU when a n overfl ow
occurs, to prevent the loss of messages, at the expense of longer run-time for the program.
35.3.6.2 program trace
Program trace allows the debugger to continuously monitor the program execution in the CPU.
Program trace messages are generate d for every bra nch in the program, and contains com-
pressed information, which allows the debugger to correlate the message with the source code
to identify the branch instruction and target address.
35.3.6.3 data trace Data trace outputs a message every time a specific location is read or written. The message
contains information about the type (rea d/write) and size of the access, as well as th e address
and data of the accessed location. The AT32UC3A3 contains two data trace channels, each of
which are controlled by a pair of OCD registers which determine the range of addresses (or sin-
gle address) which should produce data trace messages.
35.3.6.4 ownership trace
Program and data trace operate on virtual addresses. In cases where an operating system runs
several processes in overlapp ing virtual memor y segments, th e Ownership Trace featu re can be
used to identify the process switch. When the O/S activates a process, it will write the process ID
number to an OCD regist er, which produces an Ownership Trace Message, allowing the debug-
ger to switch context fo r the subsequent pro gram and data trace messages. As the use of this
feature depends on the software running on the CPU, it can also be used to extract other types
of information from the system.
35.3.6.5 watchpoint messages
The breakpoint modules no rmally used to generate program and data breakpoints can also be
used to generate Watchpoint messages, allowing a debugger to monitor program and data
events without ha lting the CPU. Watchpoints can be enabled independently of breakpoints, so a
breakpoint module can optionally halt the CPU when the trigger condition occurs. Data trace
modules can also be configured to produce watchpoint messages instead of regular data trace
messages.
35.3.6.6 Event In and Event Out pins
The AUX port also contains an Event In pin (EVTI_N) and an Event Out pin (EVTO_N). EVTI_N
can be used to trig ge r a bre akpo int when an exte rn al even t occu rs. It can also be used to t rigger
specific program and data trace synchronization messages, allowing an external event to be
correlated to the program flow.
When the CPU enters debug mode, a Debug Status message is transmitted on the trace port.
All trace messages can be timestamped when they are received by the debug tool. However,
due to the latency of the transmit queue buffering, the timestamp will not be 100% accurate. To
improve this, EVTO_N can toggle every time a message is inserted into the transmit qu eue,
allowing trace messages to be timestamped precisely. EVTO_N can also toggle when a break-
point module trigger s, or when the CPU enters debug mode, fo r any reason. This can be use d to
measure precisely when the respective internal event occurs.
934
32072H–AVR32–10/2012
AT32UC3A3
35.3.6.7 Software Quality Analysis (SQA)
Software Qu ality Analysis ( SQA) deals w ith two impo rtant issu es regardin g embedde d softwar e
development. Code coverage involves identifying untested parts of the embedded code, to
improve test procedures and thus the quality of the released software. Performance analysis
allows the developer to precisely quantify the time spent in various parts of the code, allowing
bottlenecks to be identified and optimized.
Program trace must be used to a ccomplish these t asks withou t in stru men ting ( alter ing) the code
to be examined. However, traditional pro gram trace cannot reconstruct the current PC value
without correlating the trace information with the source code, which cannot be done on-the-fly.
This limits program trace to a relatively short time segment, determined by the size of the trace
buffer in the debug tool.
The OCD system in AT32UC3A3 extends program trace with SQ A capabilities, allowing the
debug tool to re co nstru ct th e PC value on -t he-fly. Code coverage and performance analysis can
thus be reported for an unlimited execution sequence.
935
32072H–AVR32–10/2012
AT32UC3A3
35.4 JTAG and Boundary-scan (JTAG)
Rev: 2.0.0.4
35.4.1 Features •IEEE1149.1 compliant JTAG Interface
•Boundary-scan Chain for board-level testing
•Direct memory access and programming capabilities through JTAG Interface
35.4.2 Overview The JTAG Interface offers a four pin programming and debug solution, including boundary-scan
support for board-level testing.
Figure 35-4 on page 936 shows how the JTAG is connected in an 32-bit AVR device. The TAP
Controller is a state machine controlled by the TCK and TMS signals. The TAP Controller
selects either the JTAG Instruction Register or one of several Data Registers as the scan chain
(shift register) between the TDI-input and TDO-output.
The Instruction Register holds JTAG instructions controlling the behavior of a Data Register. The
Device Identification Regi ster, Bypass Register , and the bou ndary- scan chain are t he Data Re g-
isters used for board-level testing. The Reset Register can be used to keep the device reset
during test or programming.
The Service Access Bus (SAB) interface contains address and data registers for the Service
Access Bus, which gives access to On-Chip Debug, programming, and other functions in the
device. The SAB offers several modes of access to the address and data registers, as described
in Section 35.4.10 .
Section 35.5 lists the supported JTAG instructions, wit h references to the description in this
document.
936
32072H–AVR32–10/2012
AT32UC3A3
35.4.3 Block Diagram
Figure 35-4. JTAG and Boundary-scan Access
35.4.4 I/O Lines Description
35.4.5 Pro duct Dependencies
In order to use t his modu le, othe r p arts o f th e syst em must be conf igu red cor re ctly, as de scr ibed
below.
Table 35-6. I/O Line Description
Pin Name Pin Description Type Active Level
TCK Test Clock Input. Fully asynchronous to system clock frequency. Input
TMS Test Mode Select, sampled on rising TCK. Input
TDI Test Data In, sampled on rising TCK. Input
TDO Test Data Out, driven on falling TCK. Output
32-bit AVR device
JTAG data registers
TAP
Controller
Instruction Register
Device Identification
Register
By-pass Register
Reset Register
Service Access Bus
interface
Boundary Scan Chain
Pins and analog blocks
Data register
scan enable
JTAG Pins
Boundary scan enable
2nd JTAG
device
JTAG master
TDITDO
Part specific registers
...
TDO TDITMS
TMS
TCK
TCK
Instruction register
scan enable
SAB Internal I/O
lines
JTAG
TMS
TDI
TDO
TCK
937
32072H–AVR32–10/2012
AT32UC3A3
35.4.5.1 Power Management
When an instruction that accesses the SAB is loaded in the instruction register, before entering
a sleep mode, the system clocks are not switched off to allow debugging in sleep modes. This
can lead to a program behaving differently when debugging.
35.4.5.2 Clocks The JTAG Interface uses the external TCK pin as clock source. This clock must be provided by
the JTAG master.
Instructions that use the SAB bus requires the internal main clock to be running.
35.4.6 JTAG InterfaceThe JTAG Interface is accessed through the dedicated JTAG pins shown in Table 35-6 on page
936. The TMS control line navigates the TAP controller, as shown in Figure 35-5 on page 938.
The TAP controller manages the serial access to the JTAG Instruction and Data registers. Data
is scanned into the selected instruction or data register on TDI, and out of the register on TDO,
in the Shift-IR and Shift-DR states, respectively. The LSB is shifted in and o u t first. TDO is high-
Z in other states than Shift-IR and Shift-DR.
The device implements a 5-bit Instruction Register (IR). A number of public JTAG instructions
defined by the JTAG standard are supported, as described in Section 35.5.2, as well as a num-
ber of 32-bit AVR-specific private JTAG instructions described in Section 35.5.3. Each
instruction selects a specific data register for the Shift-DR path, as described for each
instruction.
938
32072H–AVR32–10/2012
AT32UC3A3
Figure 35-5. TAP Controller State Diagram
Test-Logic-
Reset
Run-Test/
Idle
Select-DR
Scan
Select-IR
Scan
Capture-DR Capture-IR
Shift-DR Shift-IR
Exit1-DR Exit1-IR
Pause-DR Pause-IR
Exit2-DR Exit2-IR
Update-DR Update-IR
0
1 1
1
0
0
1
0
1
1
0
0
1
0
1
1
1
0
11
00
11
0
1
0
0 0
0
0
1
939
32072H–AVR32–10/2012
AT32UC3A3
35.4.7 How to Initialize the Module
Independent of the initial state of the TAP Controller, the Test-Logic-Reset state can always be
entered by holding TMS high for 5 TCK clock periods. This sequence should always be applied
at the start of a JTAG session to bring the TAP Controller into a define d state before applying
JTAG commands. Applying a 0 on TMS for 1 TCK period brings the TAP Controller to the Run-
Test/Idle sta te, which is the starting point for JTAG op erations.
35.4.8 Typical Sequence
Assuming Run-Test/Idle is the presen t state, a typical scenario for using the JTAG Interface
follows.
35.4.8.1 Sca nnin g in JTAG Instruction
At the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of TCK to enter the Shift
Instruction Register (Shi ft-IR) state. While in this state, shift the 5 bits of th e JTAG instructions
into the JTAG instructio n register from the TDI input at the rising edge of TCK. During shifting,
the JTAG outputs status bits on TDO, refer to Section 35.5 for a descr iption of th ese. The T MS
input must be held lo w during input of the 4 LSBs in o rder to remain in the Shift-IR state. The
JTAG Instruction selects a particular Data Register as path between TDI and TDO and controls
the circuitry surrounding the selected Data Register.
Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched
onto the par allel output from the shif t register path in the Update -IR state. The Exit-IR, Pa use-IR,
and Exit2-IR states are only used for navigating the state machine.
Figure 35-6. Scanning in JTAG Instruction
35.4.8.2 Scanning in/out Data
At the TMS input, apply the sequence 1, 0, 0 at the rising edges of TCK to enter the Shift Data
Register (Shift-DR) state. While in this state, up lo ad the selected Data Re gister (selecte d b y the
present JTAG instruction in the JTAG Instruction Register) from the TDI input at the rising edge
of TCK. In order to remain in the Shift-DR state, t he TMS inpu t m ust b e held low. Wh ile the Da ta
Register is shifted in from the TDI pin, the parallel inputs to the Data Register captured in the
Capture-DR state is shif ted out on the TDO pin.
TCK
TAP State TLR RTI SelDR SelIR CapIR ShIR Ex1IR UpdIR RTI
TMS
TDI Instruction
TDO ImplDefined
940
32072H–AVR32–10/2012
AT32UC3A3
Apply the TMS sequence 1, 1, 0 to re-enter the Ru n-Test/Idle state. If the selected Data Register
has a latched parallel-output, the latching takes place in the Update-DR state. The Exit-DR,
Pause-DR, and Exit2-DR states are only used for navigating the state machine.
As shown in the state diagram, the Run-Test/Idle state need not be entered betwe en selecting
JTAG instruction and using Data Registers.
35.4.9 Boundary-scan
The boundary-scan chain has the capability of driving and observing the logic levels on the digi-
tal I/O pins, as well as the boundary between digital and analog logic for analog circuitry having
off-chip connections. At system level, all ICs having JTAG capabilities are connected serially by
the TDI/TDO signals to form a long shift register. An external controller sets up the devices to
drive values at their output pins, and observe the input values received from other devices. The
controller compares the received data with the expected result. In this way, boundary-scan pro-
vides a mechanism for testing interconnections and integrity of components on Printed Circuits
Boards by using the 4 TAP signals only.
The four IEEE 1149.1 defined mandatory JTAG instructions IDCODE, BYPASS, SAMPLE/PRE-
LOAD, and EXTEST can be used for testing the Printed Circuit Board. Initial scanning of the
data register path will show the ID-code of the device, since IDCODE is the default JTAG
instruction. It may be desirable to have the 32-bit AVR device in reset during test mode. If not
reset, inputs to the device may be determined by the scan operations, and the internal software
may be in an undetermined state when exiting the test mode. If needed, the BYPASS instruction
can be issued to make the shortest possible scan chain through the device. The device can be
set in the reset state either by pulling the external RESETn pin low, or issuing the AVR_RESET
instruction with appropriate setting of the Reset Data Register.
The EXTEST instruction is used for sampling external pins and lo ading output pins with data.
The data from the output latch will be driven out on the pins as soon as the EXTEST instruction
is loaded into the JTAG IR-register. Therefore, the SAMPLE/PRELOAD should also be used for
setting initial value s to the scan r ing, to avoid da maging the board when issuing the EXT EST
instruction for the first tim e. SAMPLE/PRELOAD can also be used for taking a snapshot of the
external pins duri ng normal operation of the part.
When using the JTAG Interface for boundary-scan, the JTAG TCK clock is independent of the
internal chip clock. The internal chip clock is not required to run during boundary-scan
operations.
NOTE: For pins connected to 5V lines care should be taken to not drive the pins to a logic one
using boundary-scan, as this will create a current flowing from the 3,3V driver to the 5V pull-up
on the line. Optionally a series resistor can be added between the line and the pin to reduce the
current.
Details about the boundary-scan chain can be found in the BSDL file for the device. This can be
found on the Atmel website.
35.4.10 Service Access Bus
The AVR32 architecture of fe rs a common int e rface f or acce ss t o On-Chip Debug , pro gra mming,
and test functions. These are mapped on a common bus called the Service Access Bus (SAB),
which is linked to the JTAG through a bus master module, which also handles synchronization
between the TCK and SAB clocks.
941
32072H–AVR32–10/2012
AT32UC3A3
For more information about the SAB and a list of SAB slaves see the Service Access Bus
chapter.
35.4.10.1 SAB Address Mode
The MEMORY_SIZED_ACCESS instruction allows a sized read or write to any 36-bit address
on the bus. MEMORY_WORD_ACCESS is a shorthand in struction for 32-bit accesses to any
36-bit address, while the NEXUS_ACCESS instruction is a Nexus-compliant shorthand instruc-
tion for accessing the 32-bit OCD registers in the 7-bit address space reserved for these. These
instructions require two passes through the Shift-DR TAP state: one for the address and control
information , an d on e for da ta .
35.4.10.2 Block Transfer
To increase the transfer rate, consecutive memory accesses can be accomplished by the
MEMORY_BLOCK_ACCESS instruction, which only requires a single pass through Shift-DR for
data transfer only. The address is automatically incremented according to the size of the last
SAB transfer.
35.4.10.3 Canceling a SAB Access
It is possible to abort an ongoing SAB access by the CANCEL_ACCESS instruction, to avoid
hanging the bus due to an extremely slow slave.
35.4.10.4 Busy Reporting
As the time taken to perform an access may vary depending on system activity and current chip
frequency, all the SAB access JTAG instructions can return a busy indicator. This indicates
whether a delay needs to be inserted, or an operation needs to be repeated in order to be suc-
cessful. If a new access is requested while the SAB is busy, the request is ignored.
The SAB becomes busy when:
• Entering Update-DR in the address phase of any read operation, e.g., after scanning in a
NEXUS_ACCESS address with the read bit set.
• Entering Update-DR in the data phase of any write operation, e.g., afte r scanning in data for
a NEXUS_ACCESS write.
• Entering Update-DR during a MEMORY_BLOCK_A CCESS.
• Entering Update-DR after scanning in a counter value for SYNC.
• Entering Update-IR after scanning in a MEMORY_BLOCK_ACCESS if the pre v ious access
was a r ead and data was scanned after scanning the address.
The SAB becomes ready again when:
• A read or write operation completes.
• A SYNC countdown completed.
• A operation is cancelled by the CANCEL_ACCESS instruction.
What to do if the busy bit is set:
• During Shift-IR: The new instruction is selected, but the previous operation has not yet
completed and will continue (unless the new instruction is CANCEL_ACCESS). You may
continue shifting the same instruction until the busy bit clears, or start shifting data. If shifting
data, you must be prepared that the data shift may also report busy.
• During Shift-DR of an address: The ne w address is ignored. The SAB sta ys in address mode ,
so no data must be shifted. Repeat the address unt il the busy bit clears.
942
32072H–AVR32–10/2012
AT32UC3A3
• During Shift-DR of read data: The read data is invalid. The SAB stays in data mode. Repeat
scanning until the busy bit clears.
• During Shift-DR of write data: The write data is ignore d. The SAB sta ys in data mode . Repeat
scanning until the busy bit clears.
35.4.10.5 Error Reporting
The Service Access Bus may not be able to complete all accesses as re quested. This may be
because the address is invalid, the addressed area is read-only or cannot handle byte/halfword
accesses, or because the chip is set in a protected mode where only limited accesses are
allowed.
The error bit is updated when an access completes, and is cleared when a new access starts.
What to do if the error bit is set:
• During Shift -IR : Th e new instr u ct ion is selec ted . Th e last operatio n pe rfor m ed using th e old
instruction did not complete successfully.
• During Shift-DR of an address: The previous operation failed. The new address is accepted.
If the read bit is set, a read operation is started.
• During Shift-DR of read data: The read operation failed, and the read data is invalid.
• During Shift-DR of write data: The previous write operation failed. The new d ata is accepted
and a write operation st arted. This should only occur during b loc k writes or stream writes. No
error can occur between scanning a write address and the following write data.
• While polling with CANCEL_ACCESS: The pre vious access was ca ncelled. It ma y or ma y not
have actually completed.
• After power-up: The error bit is set afte r power up, but there has been no previous SAB
instruction so this error can be discarded.
35.4.10.6 Protected Reporting
A protected status may be reported during Shift-IR or Shift-DR. This indicates that the security
bit in the Flash Controller is set and that the chip is locked for access, according to Section
35.5.1.
The protected sta te is reported when:
• The Flash Controller is under reset. This can be due to the AVR_RESET command or the
RESET_N line.
• The Flash Controller has not read the security bit from the flash yet (This will take a a few
ms). Happens after the Flash Controller reset has been released.
• The security bit in the Flash Controller is set.
What to do if the protected bit is set:
• Release all active AVR_RESET domains, if any.
• Release the RESET_N line.
• Wait a few ms for the security bit to clear. It can be set temporarily due to a reset.
• P erf orm a CHIP_ERASE to clear the security bit. NOTE: This will erase all the contents of the
non-v olatile memory.
943
32072H–AVR32–10/2012
AT32UC3A3
35.5 JTAG Instruction Summary
The implemented JTAG instructions in the 32-bit AVR are shown in the table below.
35.5.1 Security Restrictions
When the security fuse in the Flash is programmed, the following JTAG instructions are
restricted:
• NEXUS_ACCESS
• MEMORY_WORD_ACCESS
• MEMORY_BLOCK_ACCESS
• MEMORY_SIZED_ACCESS
For description of what memory locations remain accessible, please refer to the SAB address
map.
Full access to these instructions is re-enabled when the security fuse is erased by the
CHIP_ERASE JTAG instruction.
Note that the security bit will read as programmed and block these instructions also if the Flash
Controller is statically reset.
Table 35-7. JTAG Instruction Summary
Instruction
OPCODE Instruction Description
0x01 IDCODE Sele ct the 32-bit Device Identification register as data register.
0x02 SAMPLE_PRELOAD Take a snapshot of external pin values without affecting system operation.
0x03 EXTEST Select boundary-scan chain as data register for testing circuitry external to
the device.
0x04 IN TEST Select boundary-scan chain for internal testing of the device.
0x06 CLAMP Bypass device through Bypass register, while driving outputs from boundary-
scan register.
0x0C AVR_RESET Apply or remove a static reset to the device
0x0F CHIP_ERASE Erase the device
0x10 NEXUS_ACCESS Select the SAB Address and Data registers as data register for the TAP. The
registers are accessed in Nexus mode.
0x11 MEMORY_WORD_ACCESS Select the SAB Address and Data registers as data register for the TAP.
0x12 MEMORY_BLOCK_ACCESS Sele ct the SAB Data register as data register for the TAP. The address is
auto-incremented.
0x13 CANCEL_ACCESS Cancel an ongoing Nexus or Memory access.
0x14 MEMORY_SERVICE Select the SAB Address and Data registers as data register for the TAP. The
registers are accessed in Memory Service mode.
0x15 MEMORY_SIZED_ACCESS Select the SAB Address and Data registers as data register for the TAP.
0x17 SYNC Synchronization counter
0x1C HALT Halt the CPU for safe programming.
0x1F BYPASS Bypass this device through the bypass register.
Others N/A Acts as BYPASS
944
32072H–AVR32–10/2012
AT32UC3A3
Other security mechanisms can also restrict these functions. If such mechanisms are present
they are listed in the SAB address map section.
35.5.1.1 Notation Table 35-9 on page 944 shows bit patterns to be shift ed in a format like "peb01". Each character
corresponds to one bit, and eight bits are grouped together for readability. The least significant-
bit is always shift ed firs t, and t he mo st signific an t bit shifte d last. The sym bols used are shown in
Table 35-8.
In many cases, it is not required to shift all bits through the data register. Bit patterns are shown
using the full width of the shift register, but the suggested or required bits are emphasized using
bold text. I.e. given the pattern "aaaaaaar xxxxxxxx xxxxxxxx xxxxxxxx xx", the shift register is
34 bits, but the test or debug unit may choose to shift only 8 bits "aaaaaaar".
The following describes how to interpret the fields in the instructio n description tables:
Table 35-8. Symbol Description
Symbol Description
0 Constant low value - always reads as zero.
1 Constant high value - always reads as one.
a An address bit - always scanned with the least significant bit first
bA busy bit. Reads as one if the SAB w as busy, or z ero if it was not. See Secti on 35.4.10. 4 for
details on how the busy re po rting works.
d A data bit - always scanned with the least significant bit first.
eAn error bit. Reads as one if an error occurred, or zero if not. See Section 35.4.10.5 for
details on how the error reporting works.
pThe chip protected bit. Some devices may be set in a protected state where access to chip
internals are severely restricted. See the documentation for the specific device for details.
On devices without this possib ility, this bit always reads as zero.
r A direction bit. Set to one to request a read, set to zero to request a write.
s A size bit. The size encoding is described where used.
x A do n’t care bit. Any value can be shifted in, and output data should be ignored.
Table 35-9. Instruction Description
Instruction Description
IR input value
Shows the bit pattern to shift into IR in the Shift-IR state in order to select this
instruction. The pattern is show both in binary and in he xadecimal form for
convenience.
Example: 10000 (0x10)
IR output value Shows the bit pattern shifted out of IR in the Shift-IR state when this instruction is
active.
Example: peb01
945
32072H–AVR32–10/2012
AT32UC3A3
35.5.2 Public JTAG Instructions
The JTAG standard defines a number of public JTAG instructions. These instructions are
described in the sections below.
35.5.2.1 IDCODE This instruction selects the 32 bit Device Identification register (DID) as Data Register. The DID
register consists of a version number, a device number, and the manufacturer code chosen by
JEDEC. This is the default instruction after a JTAG reset. Details about the DID register can be
found in the module configuration section at the end of this chapter.
Starting in Run-Test/Idle, the Device Identification register is accessed in the following way:
1. Select the IR Scan path.
2. In Capture-IR: The IR output value is latched into the shift register.
3. In Shift-IR: The instruction register is shifted by the TCK input.
4. Return to Run-Test/Idle.
5. Select the DR Scan path.
6. In Capture-DR: The IDCODE value is latched into the shift register.
7. In Shift-DR: The IDCODE scan chain is shifted by the TCK input.
8. Return to Run-Test/Idle.
35.5.2.2 SAMPLE_PRELOAD
This instruction takes a snap-shot of the input/output pins without affecting the system operation,
and pre-loading the scan chain without updating the DR-latch. The boundary-scan chain is
selected as Data Regi ster.
Starting in Run-Test/Idle, the Device Identification register is accessed in the following way:
DR Size Shows the number of bits in the data register chain when thi s instruction is acti ve.
Example: 34 bits
DR input value
Shows which bit pattern to shift into the data register in the Shift-DR state when this
instruction is active. Multiple such lines may exist, e.g., to distinguish between
reads and writes.
Example: aaaaaaar xxxxxxxx xxxxxxxx xxxxxxxx xx
DR output value
Shows the bit pattern shifted out of the data register in the Shift-DR state when this
instruction is active. Multiple such lines may exist, e.g., to distinguish between
reads and writes.
Example: xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb
Table 35-9. Instruction Description (Continued)
Instruction Description
Table 35-10. IDCODE Details
Instructions Details
IR input value 00001 (0x01)
IR output value p0001
DR Size 32
DR input value xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
DR output value Device Identification Register
946
32072H–AVR32–10/2012
AT32UC3A3
1. Select the IR Scan path.
2. In Capture-IR: The IR output value is latched into the shift register.
3. In Shift-IR: The instruction register is shifted by the TCK input.
4. Return to Run-Test/Idle.
5. Select the DR Scan path.
6. In Capture-DR: The Data on the external pins are sampled into the boundary-scan
chain.
7. In Shift-DR: Th e boun d ary-scan chain is shifted by the TCK input.
8. Return to Run-Test/Idle.
35.5.2.3 EXTEST This instruction selects the b oun dary-scan cha i n as Data Re giste r for test ing circuitr y ex tern al to
the 32-bit AVR package. The contents of the latched outputs of the boundary-scan chain is
driven out as soon as the JTAG IR-register is loaded with the EXTEST instruction.
Starting in Run-Test/Idle, the EXTEST instruction is accessed the following way:
1. Select the IR Scan path.
2. In Capture-IR: The IR output value is latched into the shift register.
3. In Shift-IR: The instruction register is shifted by the TCK input.
4. In Update-IR: The data from the boundary-scan chain is applied to the output pins.
5. Return to Run-Test/Idle.
6. Select the DR Scan path.
7. In Capture-DR: The data on the external pins is sampled into the boundary-scan chain.
8. In Shift-DR: Th e boun d ary-scan chain is shifted by the TCK input.
9. In Update-DR: The data from the scan chain is applied to the output pins.
10. Return to Run-Test/ Idle.
Table 35-11. SAMPLE_PRELOAD Details
Instructions Details
IR input value 00010 (0x02)
IR output value p0001
DR Size Depending on boundary-sca n chain, see BSDL-file.
DR input value Depending on boundary-scan chain, see BSDL-file.
DR output value Dependin g on boundary-scan chain, see BSDL-file.
Table 35-12. EXTEST Details
Instructions Details
IR input value 00011 (0x03)
IR output value p0001
DR Size Depending on boundary-sca n chain, see BSDL-file.
DR input value Depending on boundary-scan chain, see BSDL-file.
DR output value Dependin g on boundary-scan chain, see BSDL-file.
947
32072H–AVR32–10/2012
AT32UC3A3
35.5.2.4 INTEST This instruction selects the boundary-scan chain as Data Regist er for testing internal logic in the
device. The logic in puts are determined b y the boundary-scan chain, and the logic outputs are
captured by t he bounda ry-scan chain. The device output pins are driven f rom the boundary-scan
chain.
Starting in Run-Test/Idle, the INTEST instruction is access ed the following way:
1. Select the IR Scan path.
2. In Capture-IR: The IR output value is latched into the shift register.
3. In Shift-IR: The instruction register is shifted by the TCK input.
4. In Update-IR: The data from the boundary-scan chain is applied to the inte rnal logic
inputs.
5. Return to Run-Test/Idle.
6. Select the DR Scan path.
7. In Capture-DR: The data on the internal logic is sampled into the boundary-scan chain.
8. In Shift-DR: Th e boun d ary-scan chain is shifted by the TCK input.
9. In Update-DR: The data from the boundary-scan chain is applied to internal logic
inputs.
10. Return to Run-Test/ Idle.
35.5.2.5 CLAMP This instruction selects the Bypass register as Data Register. The device output pins are driven
from the boundary-scan chain.
Starting in Run- Test/Idle, the CLAMP instruction is accessed the following way:
1. Select the IR Scan path.
2. In Capture-IR: The IR output value is latched into the shift register.
3. In Shift-IR: The instruction register is shifted by the TCK input.
4. In Update-IR: The data from the boundary-scan chain is applied to the output pins.
5. Return to Run-Test/Idle.
6. Select the DR Scan path.
7. In Capture-DR: A logic ‘0’ is loaded into the Bypass Register.
8. In Shift-DR: Data is scanned from TDI to TDO through the Bypass register .
Table 35-13. INTEST Details
Instructions Details
IR input value 00100 (0x04)
IR output value p0001
DR Size Depending on boundary-sca n chain, see BSDL-file.
DR input value Depending on boundary-scan chain, see BSDL-file.
DR output value Dependin g on boundary-scan chain, see BSDL-file.
948
32072H–AVR32–10/2012
AT32UC3A3
9. Return to Run-Test/Idle.
35.5.2.6 BYPASS This instruction selects the 1-bit Bypass Register as Data Re gist er .
Starting in Run- Test/Idle, the CLAMP instruction is accessed the following way:
1. Select the IR Scan path.
2. In Capture-IR: The IR output value is latched into the shift register.
3. In Shift-IR: The instruction register is shifted by the TCK input.
4. Return to Run-Test/Idle.
5. Select the DR Scan path.
6. In Capture-DR: A logic ‘0’ is loaded into the Bypass Register.
7. In Shift-DR: Data is scanned from TDI to TDO through the Bypass register .
8. Return to Run-Test/Idle.
35.5.3 Private JTAG Instructions
The 32-bit AVR defines a number of private JTAG instructions, not defined by the JTAG stan-
dard. Each instruction is briefly described in text, with details following in table form.
35.5.3.1 NEXUS_ACCESS
This instruction allows Nexus-compliant access to the On-Chip Debug registers through the
SAB. The 7-bit register index, a read/write control bit, and the 32-bit data is accessed through
the JTAG port.
The data register is alternately interpreted by the SAB as an address register and a data regis-
ter. The SAB starts in address mode after the NEXUS_ACCESS instruction is selected, and
toggles betwee n address and data mode ea ch time a data scan completes with th e busy bit
cleared.
NOTE: The polarity of the direction bit is inverse of the Nexus standard.
Table 35-14. CLAMP Details
Instructions Details
IR input value 00110 (0x06)
IR output value p0001
DR Size 1
DR input value x
DR output value x
Table 35-15. BYPASS Details
Instructions Details
IR input value 11111 (0x1F)
IR output value p0001
DR Size 1
DR input value x
DR output value x
949
32072H–AVR32–10/2012
AT32UC3A3
Starting in Run-Test/Idle, OCD registers are accessed in the following way:
1. Select the IR Scan path.
2. In Capture-IR: The IR output value is latched into the shift register.
3. In Shift-IR: The instruction register is shifted by the TCK input.
4. Return to Run-Test/Idle.
5. Select the DR Scan path.
6. In Shift-DR: Scan in the direction bit (1=read, 0=write) and the 7-bit address for the
OCD register.
7. Go to Update-DR and re-enter Select-DR Scan.
8. In Shift-DR: For a read operation, sca n out the contents of the ad dressed register . For a
write operation, scan in the new contents of th e register.
9. Return to Run-Test/Idle.
For any operation, the full 7 bits of the address must be provided. For write operations, 32 data
bits must be provided, or the result will be undefined. For read ope rations, shifting may be termi-
nated once the required number of bits have been acquired.
35.5.3.2 MEMORY_SERVICE
This instruction allows access to registers in an optional Memory Service Unit. The 7-bit register
index, a read/write control bit, and the 32-bit da ta is accessed through the JTAG port.
The data register is alternately interpreted by the SAB as an address register and a data regis-
ter. The SAB starts in address mode after the MEMORY_SERVICE instruction is selected, and
toggles betwee n address and data mode ea ch time a data scan completes with th e busy bit
cleared.
Starting in Run-Test/Idle, Memory Service registers are accessed in the following way:
1. Select the IR Scan path.
2. In Capture-IR: The IR output value is latched into the shift register.
3. In Shift-IR: The instruction register is shifted by the TCK input.
4. Return to Run-Test/Idle.
5. Select the DR Scan path.
6. In Shift-DR: Scan in the direction bit (1=read, 0=write) and the 7-bit address for the
Memory Service register.
Table 35-16. NEXUS_ACCESS Details
Instructions Details
IR input value 10000 (0x10)
IR output value peb01
DR Size 3 4 bits
DR input value (Address phase) aaaaaaar xxxxxxxx xxxxxxxx xxxxxxxx xx
DR input value (Data read phase) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xx
DR input value (Data write phase) dddddddd dddddddd dddddddd dddddddd xx
DR output value (Address phase) xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb
DR output value (Data read phase) eb dddddddd dddddddd dddddddd dddddddd
DR output value (Data write phase) xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb
950
32072H–AVR32–10/2012
AT32UC3A3
7. Go to Update-DR and re-enter Select-DR Scan.
8. In Shift-DR: For a read operation, sca n out the contents of the ad dressed register . For a
write operation, scan in the new contents of th e register.
9. Return to Run-Test/Idle.
For any operation, the full 7 bits of the address must be provided. For write operations, 32 data
bits must be provided, or the result will be undefined. For read ope rations, shifting may be termi-
nated once the required number of bits have been acquired.
35.5.3.3 MEMORY_SIZED_ACCESS
This instruction allows acce ss to the entire Service Access Bus data area. Data is accesse d
through a 36-bit byte index, a 2-bit size, a direction bit, and 8, 16, or 32 bits of data. Not all units
mapped on the SAB bus may support all sizes of accesses, e.g., some may only support word
accesses.
The data register is alternately interpreted by the SAB as an address register and a data regis-
ter. The SAB starts in address mode after the MEMORY_SIZED_ACCESS instruction is
selected, and toggles between address and data mode each time a data scan completes with
the busy bit cleared.
Table 35-17. MEMORY_SERVICE Details
Instructions Details
IR input value 10100 (0x14)
IR output value peb01
DR Size 3 4 bits
DR input value (Address phase) aaaaaaar xxxxxxxx xxxxxxxx xxxxxxxx xx
DR input value (Data read phase) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xx
DR input value (Data write phase) dddddddd dddddddd dddddddd dddddddd xx
DR output value (Address phase) xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb
DR output value (Data read phase) eb dddddddd dddddddd dddddddd dddddddd
DR output value (Data write phase) xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb
951
32072H–AVR32–10/2012
AT32UC3A3
The size field is encoded as i Table 35-18.
Starting in Run-Test/Idle, SAB data is accessed in the following way:
1. Select the IR Scan path.
2. In Capture-IR: The IR output value is latched into the shift register.
3. In Shift-IR: The instruction register is shifted by the TCK input.
4. Return to Run-Test/Idle.
5. Select the DR Scan path.
6. In Shift-DR: Scan in the direct ion bit (1=r ead, 0=write), 2- bit access siz e, and the 36 -bit
address of the data to access.
7. Go to Update-DR and re-enter Select-DR Scan.
8. In Shift-DR: For a read operation, scan out the contents of the addressed area. For a
write operation, scan in t he new contents of the area.
9. Return to Run-Test/Idle.
For any operation, the full 36 bi ts of the address must be provided. For write operations, 32 data
bits must be provided, or the result will be undefined. For read ope rations, shifting may be termi-
nated once the required number of bits have been acquired.
Table 35-18. Size Field Semantics
Size field value Access size Data alignment
00 Byte (8 bits)
Address modulo 4 : data alignment
0: dddddddd xxxxxxxx xxxxxxxx xxxxxxxx
1: xxxxxxxx dddddddd xxxxxxxx xxxxxxxx
2: xxxxxxxx xxxxxxxx dddddddd xxxxxxxx
3: xxxxxxxx xxxxxxxx xxxxxxxx dddddddd
01 Halfword (16 bits)
Address modulo 4 : data alignment
0: dddddddd dddddddd xxxxxxxx xxxxxxxx
1: Not allowed
2: xxxxxxxx xxxxxxxx dddddddd dddddddd
3: Not allowed
10 Word (32 bits)
Address modulo 4 : data alignment
0: dddddddd dddddddd dddddddd dddddddd
1: Not allowed
2: Not allowed
3: Not allowed
11 Reserved N/A
Table 35-19. MEMORY_SIZED_ACCESS Details
Instructions Details
IR input value 10101 (0x15)
IR output value peb01
DR Size 3 9 bits
DR input value (Address phase) aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa aaaassr
DR input value (Data read phase) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxx
DR input value (Data write phase) dddddddd dddddddd dddddddd dddddddd xxxxxxx
952
32072H–AVR32–10/2012
AT32UC3A3
35.5.3.4 MEMORY_WORD_ACCESS
This instruction allows acce ss to the entire Service Access Bus data area. Data is accesse d
through the 34 MSB of the SAB address, a direction bit, and 32 bits of data. This instruction is
identical to MEMORY_SIZED_ACCESS except that it always does word sized accesses. Th e
size field is implied, and the two lowest address bits are removed and not scanned in.
Note: This instruction was previously known as MEMORY_ACCESS, and is provided for back-
wards compatibility.
The data register is alternately interpreted by the SAB as an address register and a data regis-
ter. The SAB starts in address mode after the MEMORY_WORD_ACCESS instruction is
selected, and toggles between address and data mode each time a data scan completes with
the busy bit cleared.
Starting in Run-Test/Idle, SAB data is accessed in the following way:
1. Select the IR Scan path.
2. In Capture-IR: The IR output value is latched into the shift register.
3. In Shift-IR: The instruction register is shifted by the TCK input.
4. Return to Run-Test/Idle.
5. Select the DR Scan path.
6. In Shift-DR: Scan in the direction bit (1=read, 0=write) and the 34-bit address of the
data to access.
7. Go to Update-DR and re-enter Select-DR Scan.
8. In Shift-DR: For a read operation, scan out the contents of the addressed area. For a
write operation, scan in t he new contents of the area.
9. Return to Run-Test/Idle.
For any operation, the full 34 bi ts of the address must be provided. For write operations, 32 data
bits must be provided, or the result will be undefined. For read ope rations, shifting may be termi-
nated once the required number of bits have been acquired.
DR output value (Address phase) xxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb
DR output value (Data read phase) xxxxxeb dddddddd dddddddd dddddddd dddddddd
DR output value (Data write phase) xxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb
Table 35-19. MEMORY_SIZED_ACCESS Details (Continued)
Instructions Details
Table 35-20. MEMORY_WORD_ACCESS Details
Instructions Details
IR input value 10001 (0x11)
IR output value peb01
DR Size 3 5 bits
DR input value (Address phase) aaaaaaaa aaaaaaaa aaaaaaaa aaaaaaaa aar
DR input value (Data read phase) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxx
DR input value (Data write phase) dddddddd dddddddd dddddddd dddddddd xxx
953
32072H–AVR32–10/2012
AT32UC3A3
35.5.3.5 MEMORY_BLOCK_ACCESS
This instruction allows access to the entire SAB data area. Up to 32 bits of data is accessed at a
time, while the address is sequentially incremented from the previously used address.
In this mode, the SAB address, size, and access direction is not provided with each access.
Instead, the previous address is auto-incremented depending on the specified size and the pre-
vious operation repeated. The address must be set up in advance with
MEMORY_SIZE_ACCESS or MEMORY_WORD_ACCESS. It is allowed, but not required, to
shift data after shifting the address.
This instruction is pr ima rily intend ed to spee d up larg e qua ntit ies of sequen ti al wo rd accesses. It
is possible to use it also for byte and halfword accesses, but the overhead in this is case much
larger as 32 bits must still be shifted for each access.
The following sequence should be used:
1. Use the MEMOR Y_SIZE_A CCESS or MEMOR Y_WORD_A CCESS to read or write the
first location.
2. Return to Run-Test/Idle.
3. Select the IR Scan path.
4. In Capture-IR: The IR output value is latched into the shift register.
5. In Shift-IR: The instruction register is shifted by the TCK input.
6. Return to Run-Test/Idle.
7. Select the DR Scan path. The address will now have incremented by 1, 2, or 4 (corre-
sponding to the next byte, halfword, or word location).
8. In Shift-DR: For a read ope ration , scan out the contents of the next addressed location.
For a write operation, scan in the new contents of the next addressed location.
9. Go to Update-DR.
10. If the block access is not complete, return to Select-DR Scan and repeat the access.
11. If the block access is complete, return to Run-Test/Idle.
For write operations, 32 data bits must be provided, or the result will be undefined. For read
operations, shifting may be terminated once the required number of bits have been acquired.
DR output value (Address phase) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xeb
DR output value (Data read phase) xeb dddddddd dddddddd dddddddd dddddddd
DR output value (Data write phase) xxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb
Table 35-20. MEMORY_WORD_ACCESS Details (Continued)
Instructions Details
Table 35-21. MEMORY_BLOCK_ACCESS Details
Instructions Details
IR input value 10010 (0x12)
IR output value peb01
DR Size 3 4 bits
DR input value (Data read phase) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xx
954
32072H–AVR32–10/2012
AT32UC3A3
The overhead using block word access is 4 cycles per 32 bits of data, resulting in an 88% tr ans-
fer efficiency, or 2.1 MBytes per second with a 20 MHz TCK frequency.
35.5.3.6 CANCEL_ACCESS
If a very slow memory location is accessed during a SAB memory access, it could take a very
long time until the busy bit is cleared, and the SAB becomes ready for the next oper ation. The
CANCEL_ACCESS instruction provides a possibility to abort an ongoing transfer and report a
timeout to the JTAG master.
When the CANCEL_ACCESS instruction is selected, the current access will be terminated as
soon as possible. There are no guarantees about how long this will take, as the hardware may
not always be able to cancel the access immediately. The SAB is ready to respond to a new
command when the busy bit clears.
Starting in Run-Test/Idle, CANCEL_ACCESS is accessed in the following way:
1. Select the IR Scan path.
2. In Capture-IR: The IR output value is latched into the shift register.
3. In Shift-IR: The instruction register is shifted by the TCK input.
4. Return to Run-Test/Idle.
35.5.3.7 SYNC This instructio n allows externa l debugger s and test ers to measure t he ratio bet ween the exter nal
JTAG clock and the internal system clock. The SYNC data register is a 16-bit counter that
counts down to zero using the internal system clock. Th e busy bit stays high until the cou nter
reaches zero.
Starting in Run-Test/Idle, SYNC instruction is used in the following way:
1. Select the IR Scan path.
2. In Capture-IR: The IR output value is latched into the shift register.
3. In Shift-IR: The instruction register is shifted by the TCK input.
4. Return to Run-Test/Idle.
5. Select the DR Scan path.
DR input value (Data write phase) dddddddd dddddddd dddddddd dddddddd xx
DR output value (Data read phase) eb dddddddd dddddddd dddddddd dddddddd
DR output value (Data write phase) xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb
Table 35-21. MEMORY_BLOCK_ACCESS Details (Continued)
Instructions Details
Table 35-22. CANCEL_ACCESS Details
Instructions Details
IR input value 10011 (0x13)
IR output value peb01
DR Size 1
DR input value x
DR output value 0
955
32072H–AVR32–10/2012
AT32UC3A3
6. Scan in an 16-bit counter value.
7. Go to Update-DR and re-enter Select-DR Scan.
8. In Shift-DR: Scan out the busy bit, and until the busy bit clears goto 7.
9. Calculate an approximation to the internal clock speed using the elapsed time and the
counter value.
10. Return to Run-Test/ Idle.
The full 16-bit co unter value must b e provided when sta rting the sync h operation, or the r esult
will be undefined. When reading status, shifting may be terminated once the required number of
bits have been acquired.
35.5.3.8 AVR_RESETThis instruction allows a debugger or tester to directly control separate reset domains inside the
chip. The shift register contains one bit for each controllable reset domain. Setting a bit to one
resets that domain and holds it in reset. Setting a bit to zero releases the reset for that domain.
The AVR_RESET instruction can be used in the following way:
1. Select the IR Scan path.
2. In Capture-IR: The IR output value is latched into the shift register.
3. In Shift-IR: The instruction register is shifted by the TCK input.
4. Return to Run-Test/Idle.
5. Select the DR Scan path.
6. In Shift-DR: Scan in the value corresponding to the reset domains the JTAG master
want s to reset into the data register.
7. Return to Run-Test/Idle.
8. Stay in run test idle for at least 10 TCK clock cycles to let the reset propagate to the
system.
See the device specific documentation for the number of reset domains, and what these
domains are.
For any operation, all bits must be provided or the result will be undefined.
Table 35-23. SYNC_ACCESS Details
Instructions Details
IR input value 10111 (0x17)
IR output value peb01
DR Size 1 6 bits
DR input value dddddddd dddddddd
DR output value xxxxxxxx xxxxxxeb
Table 35-24. AVR_RESET Details
Instructions Details
IR input value 01100 (0x0C)
IR output value p0001
956
32072H–AVR32–10/2012
AT32UC3A3
35.5.3.9 CHIP_ERASE
This instruction allows a programmer to completely erase all nonvolatile memories in a chip.
This will also clear any security bits that are set, so the device can be accessed normally. In
devices without non-volatile memories this instruction does nothing, and appears to complete
immediately.
The erasing of non-volatile memories starts as soon as the CHIP_ERASE instruction is selected.
The CHIP_ERASE instruction selects a 1 bit bypass data register.
A chip erase operat ion should be performed as:
1. Reset the system and stop the CPU from executin g.
2. Select the IR Scan path.
3. In Capture-IR: The IR output value is latched into the shift register.
4. In Shift-IR: The instruction register is shifted by the TCK input.
5. Check the busy bit that was scanned out during Shift-IR. If the busy bit was set goto 2.
6. Return to Run-Test/Idle.
35.5.3.10 HALT This instruction allows a programme r to easily stop the CPU to ensure that it doe s not execute
invalid code during programming.
This instruction select s a 1-bit ha lt re gist er. Set ting th is bit to one re set s the device an d halt s the
CPU. Setting this bit to zero resets the device and rele ases the CPU to run normally. The value
shifted out from the data register is one if the CPU is halted.
The HALT instruction can be used in the following way:
1. Select the IR Scan path.
2. In Capture-IR: The IR output value is latched into the shift register.
3. In Shift-IR: The instruction register is shifted by the TCK input.
4. Return to Run-Test/Idle.
5. Select the DR Scan path.
DR Size Device specific.
DR input value Device specific.
DR output value Device specific.
Table 35-24. AVR_RESET Details (Continued)
Instructions Details
Table 35-25. CHIP_ERASE Details
Instructions Details
IR input value 01111 (0x0F)
IR output value p0b01
Where b is the busy bit.
DR Size 1 bit
DR input value x
DR output value 0
957
32072H–AVR32–10/2012
AT32UC3A3
6. In Shift-DR: Scan in the v alue 1 to halt the CPU, 0 to start CPU execution.
7. Return to Run-Test/Idle.
Table 35-26. HALT Details
Instructions Details
IR input value 11100 (0x1C)
IR output value p0001
DR Size 1 bit
DR input value d
DR output value d
958
32072H–AVR32–10/2012
AT32UC3A3
35.5.4 JTAG Data Registers
The following device specific registers can be selected as JTAG scan chain depending on the
instruction loaded in the JTAG Instruction Register. Additional registers exist, but are implicitly
described in the functional description of the relevant instructions.
35.5.4.1 Device Identification Register
The Device Identification Re gister contains a unique identifier for each p roduct. The register is
selected by the IDCODE instruction, which is the default instruction after a JTAG reset.
•Device specific ID codes
The different dev ice configurations have different JTAG ID co des, as shown in Table 35-27.
Note that if the flash controller is statically reset, the ID code will be undefined.
MSB LSB
Bit 31 28 27 12 11 1 0
Device ID Revision Part Number Manufacturer ID 1
4 bits 16 bits 11 bits 1 bit
Revision This is a 4 bit numb er iden tifying the revision of the component.
Rev A = 0x0, B = 0x1, etc.
Part Number The part number is a 16 bit code identifying the component.
Manufacturer ID The Manufacturer ID is a 11 bit code identifying the manufacturer.
The JTAG manufacturer ID for ATMEL is 0x01F.
Table 35-27. Device and JTAG ID
Device name JTAG ID code (r is the revision number)
AT32UC3A3256S 0xr202003F
AT32UC3A3128S 0xr202103F
AT32UC3A364S 0xr202203F
AT32UC3A3256 0xr202603F
AT32UC3A3128 0xr202703F
AT32UC3A364 0xr202803F
AT32UC3A4256S 0xr202903F
AT32UC3A4128S 0xr202a03F
AT32UC3A464S 0xr202b03F
AT32UC3A4256 0xr202c03F
AT32UC3A128 0xr202d03F
AT32UC3A64 0xr202e03F
959
32072H–AVR32–10/2012
AT32UC3A3
35.5.4.2 Reset register
The reset register is selected by the AVR_RESET instruction and contains one bit for each reset
domain in the device. Setting each bit to one will keep that domain reset until the bit is cleared.
Note: This register is primarily intended for compatibility with other 32-bit AVR devices. Certain
operations may not function correctly when parts of the system are reset. It is generally recom-
mended to only write 0x11111 or 0x00000 to these bits to ensure no unintended side effects
occur.
35.5.4.3 Boundary-Scan Chain
The Boundary-Scan Chain has the capability of driving and observing the logic levels on the dig-
ital I/O pins, as well as d riving a nd ob serving t he lo gic levels between the digita l I/O pins and the
internal logic. Typically, output value, output enable, and input data are all available in the
boundary scan chain.
The boundary scan chain is described in the BDSL (Boundary Scan Description Language) file
available at the Atm e l web site.
LSB
Bit 43210
Device ID OCD APP RESERVED RESERVED CPU
CPU CPU
APP HSB and PB buses
OCD On-Chip Debug logic and registers
RSERVED No effect
960
32072H–AVR32–10/2012
AT32UC3A3
36. Electrical Characteristics
36.1 Absolute Maximum Ratings*
Operating Temperature.................................... -40°C to +85°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Storage Temperature..................................... -60°C to +150°C
Voltage on Input Pin
with respect to Ground ........................................-0.3V to 3.6V
Maximum Operating Voltage (VDDCORE)..................... 1.95V
Maximum Operating Voltage (VDDIO).............................. 3.6V
Total DC Output Current on all I/O Pin
for TQFP144 package ................................................. 370 mA
for TFBGA144 package............................................... 370 mA
961
32072H–AVR32–10/2012
AT32UC3A3
36.2 DC Characteristics
The following characteristics are applicab le to the operating temperature ran ge: TA= -40 °C to 85°C, unless otherwise
specified and are certified for a junction temperature up toTJ=100°C.
Table 36-1. DC Characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
VVDDIO DC Supply Peripheral I/Os 3.0 3.6 V
VVDDANA DC Analog Supply 3.0 3.6 V
VIL Input Low-level Voltage
All I/O pins except TWCK, TWD,
RESET_N, TCK, TDI -0.3 +0.8 V
TWCK, TWD VVDDIO
x0.7 VVDDIO
+0.5 V
RESET_N, TCK, TDI +0.8V V
VIH Input High-level Voltage All I/O pins except TWCK, TWD 2.0 3.6 V
TWCK, TWD V
VOL Output Low-level Voltage IOL = -2mA for Pin drive x1
IOL = -4mA for Pin drive x2
IOL = -8mA for Pin drive x3 0.4 V
VOH Output High-level Voltage IOH = 2mA f or Pin drive x1
IOH = 4mA for Pin drive x2
IOH = 8mA for Pin drive x3
VVDDIO
-0.4 V
ILEAK Input Leakage Current Pullup resistors disabled 0 .0 5 1 µA
CIN Input Capacitance 7pF
RPULLUP Pull-up Resistance All I/O pins except RESET_N, TCK,
TDI, TMS 91525KΩ
RESET_N, TCK, TDI, TMS 5 25 KΩ
IO
Output Current
Pin drive 1x
Pin drive 2x
Pin drive 3x
2.0
4.0
8.0
mA
ISC Static Current On VVDDIN = 3.3V,
CPU in static mode TA = 25°C 30 µA
TA = 85°C 175 µA
962
32072H–AVR32–10/2012
AT32UC3A3
36.2.1 I/O Pin Output Level Typical Characteristics
Figure 36-1. I/O Pin drive x2 Output Low Level Voltage (VOL) vs. Source Current
Figure 36-2. I/O Pin drive x2 Output High Leve l Voltage (VOH) vs. Source Current
36.3 I/O pin Characteristics
These parameters are given in the following conditions:
•V
DDCORE = 1.8V
•V
DDIO = 3.3V
• Ambient Temperature = 25°C
VddIo = 3.3V
90
25
-45
0
0,2
0,4
0,6
0,8
1
1,2
1,4
1,6
1,8
0 5 10 15 20
Load current [mA ]
Voltage [V
VddIo = 3.3V
90
25
-45
0
0,5
1
1,5
2
2,5
3
3,5
0 5 10 15 20
Load current [mA ]
Voltage [
V
963
32072H–AVR32–10/2012
AT32UC3A3
36.4 Regulator characteristics
Table 36-2. Normal I/O Pin Characteristics
Symbol Parameter Conditions drive x2 drive x2 drive x3 Unit
fMAX Output frequency
10pf 40 66 100 MHz
30pf 18.2 35.7 61.6 MHz
60pf 7.5 18.5 36.3 MHz
tRISE Rise time
10pf 2.7 1.4 0.9 ns
30pf 6.9 3.5 1.9 ns
60pf 13.4 6.7 3.5 ns
tFALL Fall time
10pf 3.2 1.7 0.9 ns
30pf 8.6 4.3 2.26 ns
60pf 16.5 8.3 4.3 ns
Table 36-3. Electrical Characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
VVDDIN Supply voltage (input) 3.0 3.3 3.6 V
VVDDCORE Supply voltage (output) 1.75 1.85 1.95 V
IOUT Maximum DC output current VVDDIN = 3.3V 100 mA
Table 36-4. Decoupling Requirements
Symbol Parameter Conditions Typ. Technology Unit
CIN1 Input Regulator Capacitor 1 1 NPO nF
CIN2 Input Regulator Capacitor 2 4.7 X7R µF
COUT1 Output Regulator Capacitor 1 470 NPO pF
COUT2 Output Regulator Capacitor 2 2.2 X7R µF
964
32072H–AVR32–10/2012
AT32UC3A3
36.5 Analog characteristics
36.5.1 ADC
36.5.2 BOD
Table 36-7 describes the values of the BODLEVEL field in the flash FGPFR register.
Table 36-8 describes the values of the BOD33.LEVEL field in the PM module
Table 36-5. Electrical Characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
VVDDANA Analog Power Supply 3.0 3.6 V
Table 36-6. Decoupling Requirements
Symbol Parameter Conditions Typ. Technology Unit
CVDDANA Power Supply Capacitor 100 NPO nF
Table 36-7. 1.8V BOD Level Values
Symbol Parameter Value Conditions Min. Typ. Max. Unit
BODLEVEL
00 1111b 1.79 V
01 0111b 1.70 V
01 1111b 1.61 V
10 0111b 1.52 V
Table 36-8. 3.3V BOD Level Values
Symbol Parameter Value Conditions Min. Typ. Max. Unit
BOD33LEVEL
Reset value 2.71 V
1011 2.27 V
1010 2.37 V
1001 2.46 V
1000 2.56 V
0111 2.66 V
0110 2.76 V
0101 2.86 V
0100 2.96 V
0011 3.06 V
0010 3.15 V
0001 3.25 V
0000 3.35 V
965
32072H–AVR32–10/2012
AT32UC3A3
36.5.3 Reset Sequence
Table 36-9. BOD Timing
Symbol Parameter Conditions Min. Typ. Max. Unit
TBOD Minimum time with VDDCORE <
VBOD to detect power failure Falling VDDCORE from 1.8V to 1.1V 300 800 ns
Table 36-10. Elect rical Cha racter i stics
Symbol Parameter Conditions Min. Typ. Max. Unit
VDDRR VDDIN/VDDIO rise rate to ensure
power-on-reset 0.8 V/ms
VPOR+
Rising threshold voltage: voltage up
to which device is k ept under reset by
POR on rising VDDIN Rising VDDIN: VRESTART -> VPOR+ 2.7 V
VPOR-
Falling threshold voltage: voltage
when POR resets device on falling
VDDIN Falling VDDIN: 3.3V -> VPOR- 2.7 V
VRESTART
On falling VDDIN, voltage must go
down to this value before supply can
rise again to ensure reset signal is
released at VPOR+
Falling VDDIN: 3.3V -> VRESTART 0.2 V
TSSU1
Time for Cold System Startup: Time
for CPU to fetch its first instruction
(RCosc not calibrated) 480 960 µs
TSSU2
Time f or Hot System Startup: Time for
CPU to fetch its first instruction
(RCosc calibrated) 420 µs
966
32072H–AVR32–10/2012
AT32UC3A3
Figure 36-3. MCU Cold Start-Up
Figure 36-4. MCU Cold Start-Up RESET_N Externally Driven
Figure 36-5. MCU Hot Start-Up
VBOD33LEVEL
VDDIN
VDDIO
Internal
MCU Reset
TSSU1
Internal
BOD33 Reset
RESET_N
VRESTART
VBOD33LEVEL
VBOD33LEVEL
VDDIN
VDDIO
Internal
MCU Reset
TSSU1
Internal
BOD33 Reset
RESET_N
VRESTART
VBOD33LEVEL
VDDIN
VDDIO
Internal
MCU Reset
TSSU2
RESET_N
BOD Reset
WDT Reset
967
32072H–AVR32–10/2012
AT32UC3A3
36.5.4 RESET_N Characteristics
Table 36-11. RESET_N Waveform Parameters
Symbol Parameter Conditions Min. Typ. Max. Unit
tRESET RESET_N minimum pulse width 10 ns
968
32072H–AVR32–10/2012
AT32UC3A3
36.6 Power Consumption
The values in Table 36-12 and Ta ble 36-13 on page 970 are measu red values of power con-
sumption with operating conditions as follows:
•VDDIO = 3.3V
•TA = 25°C
•I/Os are configured in input, pull-up enabled.
Figure 36-6. Measurement Setup
These figures represent the power consumption measured on the power supplies
Internal
Voltage
Regulator
Amp0
VDDANA
VDDIO
VDDIN
VDDCORE
GNDPLL
GNDCORE
969
32072H–AVR32–10/2012
AT32UC3A3
36.6.1 Power Consumtion for Different Sleep Modes
Notes: 1. Core frequency is generated from XIN0 using the PLL.
Table 36-12. Power Consumption for Different Sleep Modes
Mode Conditions(1) Typ. Unit
Active
- CPU running a recursive Fibonacci Algorithm from flash and clocked from PLL0
at f MHz.
- Flash High Speed mode disable (f < 66 MHz)
- Voltage regulator is on.
- XIN0: external clock. Xin1 Stopped. XIN32 stopped.
- All peripheral clocks activated with a division by 8.
- GPIOs are inactive with internal pull-up, JTAG unconnected with external
pullup and Input pins are connected to GND
0.626xf(MHz)+2.257 mA/MHz
Same conditions with Flash High Speed mode enable (66< f < 84 MHz) 0.670xf(MHz)+2.257 mA/MHz
Same conditions with Flash High Speed mode disable at 60 MHz 40 mA
Idle See Active mode conditions 0.349xf(MHz)+0.968 mA/MHz
Same conditions at 60 MHz 21.8 mA
Frozen See Active mode conditions 0.098xf(MHz)+1.012 mA/MHz
Same conditions at 60 MHz 6.6 mA
Standby See Active mode conditions 0.066xf(MHz)+1.010 mA/MHz
Same conditions at 60 MHz 4.6 mA
Stop
- CPU running in sleep mode
- XIN0, Xin1 and XIN32 are stopped.
- All peripheral clocks are desactived.
- GPIOs are inactive with internal pull-up, JTAG unconnected with external
pullup and Input pins are connected to GND.
96 µA
Deepstop See Stop mode conditions 54 µA
Static
TA = 25 °C
CPU is in static mode
GPIOs on internal pull-up
All peripheral clocks de-activated
DM and DP pins connected to ground
XIN0, Xin1 and XIN32 are stopped
on Amp0 31 µA
970
32072H–AVR32–10/2012
AT32UC3A3
Table 36-13. Typical Cuurent Consumption by Peripheral
Peripheral Typ. Unit
ADC 7
µA/MHz
AES 80
ABDAC 10
DMACA 70
EBI 23
EIC 0.5
GPIO 37
INTC 3
MCI 40
MSI 10
PDCA 20
SDRAM 5
SMC 9
SPI 6
SSC 10
RTC 5
TC 8
TWIM 2
TWIS 2
USART 10
USBB 90
WDT 2
971
32072H–AVR32–10/2012
AT32UC3A3
36.7 System Clock Characteristics
These parameters are given in the following conditions:
•V
DDCORE = 1.8V
36.7.1 CPU/HSB Clock Characteristics
36.7.2 PBA Clock Characteristics
36.7.3 PBB Clock Characteristics
Table 36-14. Core Clock Waveform Parameters
Symbol Parameter Conditions Min. Typ. Max. Unit
1/(tCPCPU) CPU Clo ck Frequency -40°C < Ambient Temperature < 70°C 84 MHz
1/(tCPCPU) CPU Clo ck Frequency -40°C < Ambient Temperature < 85°C 66 MHz
Table 36-15. PBA Clock Waveform Parameters
Symbol Parameter Conditions Min. Typ. Max. Unit
1/(tCPPBA) PBA Clock Frequency -40°C < Ambient Temperature < 70°C 84 MHz
1/(tCPPBA) PBA Clock Frequency -40°C < Ambient Temperature < 85°C 66 MHz
Table 36-16. PBB Clock Waveform Parameters
Symbol Parameter Conditions Min. Typ. Max. Unit
1/(tCPPBB) PBB Clock Frequency -40°C < Ambient Temperature < 70°C 84 MHz
1/(tCPPBB) PBB Clock Frequency -40°C < Ambient Temperature < 85°C 66 MHz
972
32072H–AVR32–10/2012
AT32UC3A3
36.8 Oscillator Characteristics
The following characteristics are applicable to the operating temperature range: TA = -40°C to 85°C and worst case of
power supply, unless otherwise specified.
36.8.1 Slow Clock RC Oscillator
36.8.2 32 KHz Oscillator
Note: 1. CL is the equivalent load capacitance.
Table 36-17. RC Oscillator Frequency
Symbol Parameter Conditions Min. Typ. Max. Unit
FRC RC Oscillator Frequency
Calibration point: TA = 85°C 115.2 1 16 KHz
TA = 25°C 112 KHz
TA = -40°C 105 108 KHz
Table 36-18. 32 KHz Oscillator Characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
1/(tCP32KHz) Oscillator Frequency External clock on XIN32 30 MHz
Crystal 32 76 8 Hz
CL Equivalent Load Capacitance 6 12.5 pF
ESR Crystal Equivalent Series Resistance 100 KΩ
tST Startup Time CL = 6pF(1)
CL = 12.5pF(1) 600
1200 ms
tCH XIN32 Clock High Half-period 0.4 tCP 0.6 tCP
tCL XIN32 Clock Low Half-period 0.4 tCP 0.6 tCP
CIN XIN32 Input Capacitance 5pF
IOSC Current Consumption Active mode 1.8 µA
Standby mode 0.1 µA
973
32072H–AVR32–10/2012
AT32UC3A3
36.8.3 Main Oscillators
36.8.4 Phase Lock Loop (PLL0, PLL1)
36.8.5 USB Hi-Speed Phase Lock Loop
Table 36-19. Main Oscillators Characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
1/(tCPMAIN) Oscillator Frequency External clock on XIN 50 MHz
Crystal 0.4 20 MHz
CL1, CL2 Internal Load Capacitance (CL1 = CL2)7pF
ESR Crystal Equivalent Series Resistance 75 Ω
Duty Cycle 405060%
tST Startup Time
f = 400 KHz
f = 8 MHz
f = 16 MHz
f = 20 MHz
25
4
1.4
1
ms
tCH XIN Clock High Half-period 0.4 tCP 0.6 tCP
tCL XIN Clock Low Half-period 0.4 tCP 0.6 tCP
CIN XIN Input Capacitance 7 pF
IOSC Current Consumption
Active mode at 400 KHz. Gain = G0
Active mode at 8 MHz. Gain = G1
Active mode at 16 MHz. Gain = G2
Active mode at 20 MHz. Gain = G3
30
45
95
205
µA
Table 36-20. PLL Characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
FOUT VCO Output Frequency 80 240 MHz
FIN Input Frequency (after input divider) 4 16 MHz
IPLL Current Consumption Active mode (Fout=80 MHz) 250 µA
Active mode (Fout= 240 MHz) 600 µA
Table 36-21. PLL Characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
FOUT VCO Output Frequency 480 MHz
FIN Input Frequency 12 MHz
Delta FIN
Input F requency Accuracy (applicable
to Clock signal on XIN or to Quartz
tolerance) -500 +500 ppm
IPLL Current Consumption Active mode @480MHz @1.8V 2.5 mA
974
32072H–AVR32–10/2012
AT32UC3A3
36.9 ADC Characteristics
Table 36-22. Channel Conversion Time and ADC Clock
Parameter Conditions Min. Typ. Max. Unit
ADC Clock Frequency 10-bit resolution mode 5 MHz
8-bit resolution mode 8 MHz
Startup Time Return from Idle Mode 20 µs
Track and Hold Acquisition Time 600 ns
Conversion Time ADC Clock = 5 MHz 2 µs
ADC Clock = 8 MHz 1.25 µs
Throughput Rate ADC Clock = 5 MHz 384 (1)
1. Corresponds to 13 clock cycles: 3 clock cycles for track and hold acquisition time and 10 clock cycles for conversion.
kSPS
ADC Clock = 8 MHz 533 (2)
2. Corresponds to 15 clock cycles: 5 clock cycles for track and hold acquisition time and 10 clock cycles for conversion.
kSPS
Table 36-23. ADC Power Consumption
Parameter Conditions Min. Typ. Max. Unit
Current Consumption on VDDANA (1)
1. Including internal reference input current
On 13 samples with ADC clock = 5 MHz 1.25 mA
Table 36-24. Analog Inputs
Parameter Conditions Min. Typ. Max. Unit
Input Voltage Range 0 VDDANA V
Input Leakage Current 1µA
Input Capacitance 7pF
Input Resistance 350 850 Ohm
Table 36-25. Transfer Characteristics in 8-bit mode
Parameter Conditions Min. Typ. Max. Unit
Resolution 8Bit
Absolute Accuracy ADC Clock = 5 MHz 0.8 LSB
ADC Clock = 8 MHz 1.5 LSB
Integral Non-linearity ADC Clock = 5 MHz 0.35 0.5 LSB
ADC Clock = 8 MHz 0.5 1.5 LSB
Differential Non-linearity ADC Clock = 5 MHz 0.3 0.5 LSB
ADC Clock = 8 MHz 0.5 1.5 LSB
Offset Error ADC Clock = 5 MHz -1.5 1.5 LSB
Gain Error ADC Clock = 5 MHz -0.5 0.5 LSB
975
32072H–AVR32–10/2012
AT32UC3A3
36.10 USB Transceiver Characteristics
36.10.1 Electrical Charact eristics
36.10.2 Static Power Consumption
36.10.3 Dynamic Power Consumption
Table 36-26. Transfer Characteristics in 10-bit mode
Parameter Conditions Min. Typ. Max. Unit
Resolution 10 Bit
Absolute Accuracy ADC Clock = 5 MHz 3 LSB
Integral Non-linearity ADC Clock = 5 MHz 1.5 2 LSB
Differential Non-linearity ADC Clo ck = 5 MHz 1 2 LSB
ADC Clock = 2.5 MHz 0.6 1 LSB
Offset Error ADC Clock = 5 MHz -2 2 LSB
Gain Error ADC Clo ck = 5 MHz -2 2 LSB
Table 36-27. Electrical Parameters
Symbol Parameter Conditions Min. Typ. Max. Unit
REXT Recommended External USB Series
Resistor In series with each USB pin with
±5% 39 Ω
RBIAS VBIAS External Resistor (1)
1. The USB on-chip buffers comply with the Universal Serial Bus (USB) v2.0 standard. All AC parameters related to these buf-
fers can be found within the USB 2.0 electrical specifications.
±1% 6810 Ω
CBIAS VBIAS External Capcitor 10 pF
Table 36-28. Static Power Consumption
Symbol Parameter Conditions Min. Typ. Max. Unit
IBIAS Bias current consumption on VBG 1 µA
IVDDUTMI
HS Transceiver and I/O current
consumption 8µA
FS/HS Transceiver and I/O current
consumption
If cable is connected, add 200µA
(typical) due to Pull-up/Pull-down
current consumption 3µA
Table 36-29. Dynami c Power Consumption
Symbol Parameter Conditions Min. Typ. Max. Unit
IBIAS Bias current consumption on VBG 0.7 0.8 mA
976
32072H–AVR32–10/2012
AT32UC3A3
IVDDUTMI
HS Transceiver current consumption HS transmission 47 60 mA
HS Transceiver current consumption HS reception 18 27 mA
FS/HS Transceiver current
consumption FS transmission 0m cable (1) 46mA
FS/HS Transceiver current
consumption FS transmission 5m cable 26 30 mA
FS/HS Transceiver current
consumption FS reception 3 4.5 mA
1. Includi ng 1 mA due to Pull-up/Pull-down current consumption.
34.5.5 USB High Speed Design Guidelines
In order to facilitate hardware design, Atmel provides an application note on www.atmel.com.
Table 36-29. Dynami c Power Consumption
Symbol Parameter Conditions Min. Typ. Max. Unit
977
32072H–AVR32–10/2012
AT32UC3A3
36.11 EBI Timings
36.11.1 SMC Signals These timings are given for worst case process, T = 85⋅C, VDDIO = 3V and 40 pF load
capacitance.
Note: 1. The maximum frequency of the SMC interface is the same as the max frequency for the HSB.
Note: 1. hold length = total cycle duration - setup duration - pulse duration. “hold length” is for “ncs rd hold length” or “nrd hold length”.
Table 36-30. SMC Clock Signal
Symbol Parameter Max.(1) Unit
1/(tCPSMC) SMC Controller Clock Frequency 1/(tcpcpu)MHz
Table 36-31. SMC Read Signals with Hold Settings
Symbol Parameter Min. Unit
NRD Controlled (READ_MODE = 1)
SMC1Data Setup before NRD High 12 ns
SMC2Data Hold after NRD High 0 ns
SMC3NRD High to NBS0/A0 Change(1) nrd hold length * tCPSMC - 1.3 ns
SMC4NRD High to NBS1 Change(1) nrd hold length * tCPSMC - 1.3 ns
SMC5NRD High to NBS2/A1 Change(1) nrd hold length * tCPSMC - 1.3 ns
SMC7NRD High to A2 - A23 Change(1) nrd hold length * tCPSMC - 1.3 ns
SMC8NRD High to NCS Inactive(1) (nrd hold length - ncs rd hold length) * tCPSMC - 2.3 ns
SMC9NRD Pulse Width nrd pulse length * tCPSMC - 1.4 ns
NRD Controlled (READ_MODE = 0)
SMC10 Data Setup before NCS High 11.5 ns
SMC11 Data Hold after NCS High 0 ns
SMC12 NCS High to NBS0/A0 Change(1) ncs rd hold length * tCPSMC - 2.3 ns
SMC13 NCS High to NBS0/A0 Change(1) ncs rd hold length * tCPSMC - 2.3 ns
SMC14 NCS High to NBS2/A1 Change(1) ncs rd hold length * tCPSMC - 2.3 ns
SMC16 NCS High to A2 - A23 Change(1) ncs rd hold length * tCPSMC - 4ns
SMC17 NCS High to NRD Inactive(1) ncs rd hold length - nrd hold length)* tCPSMC - 1.3 ns
SMC18 NCS Pulse Width ncs rd pulse length * tCPSMC - 3.6 ns
978
32072H–AVR32–10/2012
AT32UC3A3
Note: 1. hold length = total cycle duration - setup duration - pulse duration. “hold length” is for “ncs wr hold length” or “nwe hold
length"
Table 36-32. SMC Read Signals with no Hold Settings
Symbol Parameter Min. Unit
NRD Controlled (READ_MODE = 1)
SMC19 Data Setup before NRD High 13.7 ns
SMC20 Data Hold after NRD High 1 ns
NRD Controlled (READ_MODE = 0)
SMC21 Data Setup before NCS High 13.3 ns
SMC22 Data Hold after NCS High 0 ns
Table 36-33. SMC Write Signals with Hold Settings
Symbol Parameter Min. Unit
NRD Controlled (READ_MODE = 1)
SMC23 Data Out Valid bef ore NWE High (nwe pulse length - 1) * tCPSMC - 0.9 ns
SMC24 Data Out Valid after NWE High(1) nwe hold len gth * tCPSMC - 6 ns
SMC25 NWE High to NBS0/A0 Change(1) nwe hold length * tCPSMC - 1.9 ns
SMC26 NWE High to NBS1 Change (1) nwe hold length * tCPSMC - 1.9 ns
SMC29 NWE High to A1 Change(1) nwe hold length * tCPSMC - 1.9 ns
SMC31 NWE High to A2 - A23 Change(1) nwe hold length * tCPSMC - 1.7 ns
SMC32 NWE High to NCS Inactive(1) (nwe hold length - ncs wr hold length)* tCPSMC - 2.9 ns
SMC33 NWE Pulse Width nwe pulse length * tCPSMC - 0.9 ns
NRD Controlled (READ_MODE = 0)
SMC34 Data Out Valid before NCS High (ncs wr pulse length - 1)* tCPSMC - 4.6 ns
SMC35 Data Out Valid after NCS High(1) ncs wr hold length * tCPSMC - 5.8 ns
SMC36 NCS High to NWE Inactive(1) (ncs wr hold length - nwe hold length)* tCPSMC - 0.6 ns
Table 36-34. SMC Write Signals with No Hold Settings (NWE Controlled only)
Symbol Parameter Min. Unit
SMC37 NWE Rising to A2-A25 Valid 5.4 ns
SMC38 NWE Rising to NBS0/A0 Valid 5 ns
SMC39 NWE Rising to NBS1 Chang e 5 ns
SMC40 NWE Rising to A1/NBS2 Change 5 ns
SMC41 NWE Rising to NBS3 Chang e 5 ns
SMC42 NWE Rising to NCS Rising 5.1 ns
979
32072H–AVR32–10/2012
AT32UC3A3
Figure 36-7. SMC Signals for NCS Controlled Accesses.
SMC43 Data Out Valid bef ore NWE Rising (nwe pulse length - 1) * tCPSMC - 1.2 ns
SMC44 Data Out Valid after NWE Rising 5 ns
SMC45 NWE Pulse Width nwe pulse length * tCPSMC - 0.9 ns
Table 36-34. SMC Write Signals with No Hold Settings (NWE Controlled only)
Symbol Parameter Min. Unit
NRD
NCS
D0 - D15
NWE
A2-A25
A0/A1/NBS[3:0]
SMC34 SMC35
SMC10 SMC11
SMC16
SMC15
SMC22
SMC21
SMC17
SMC18
SMC14
SMC13
SMC12
SMC18
SMC17
SMC16
SMC15
SMC14
SMC13
SMC12
SMC18
SMC36
SMC16
SMC15
SMC14
SMC13
SMC12
980
32072H–AVR32–10/2012
AT32UC3A3
Figure 36-8. SMC Signals for NRD and NRW Controlled Accesses.
36.11.2 SDRAM Signals
These timings are given for 10 pF load on SDCK and 40 pF on other signals.
Note: 1. The maximum frequency of the SDRAMC interface is the same as the max frequency for the HSB.
NRD
NCS
D0 - D15
NWE
A2-A25
A0/A1/NBS[3:0]
SMC7
SMC19 SMC20 SMC43
SMC37
SMC42 SMC8
SMC1 SMC2 SMC23 SMC24
SMC32
SMC7
SMC8
SMC6
SMC5
SMC4
SMC3
SMC9
SMC41
SMC40
SMC39
SMC38
SMC45
SMC9
SMC6
SMC5
SMC4
SMC3
SMC33
SMC30
SMC29
SMC26
SMC25
SMC31
SMC44
Table 36-35. SDRAM Clock Signal.
Symbol Parameter Conditions Min. Max.(1) Unit
1/(tCPSDCK) SDRAM Controller Clock Frequency 1/(tcpcpu)MHz
Table 36-36. SDRAM Clock Signal
Symbol Parameter Conditions Min. Max. Unit
SDRAMC1SDCKE High before SDCK Rising Edge 7.4 ns
SDRAMC2SDCKE Low after SDCK Rising Edge 3.2 ns
SDRAMC3SDCKE Low before SDCK Rising Edge 7 ns
SDRAMC4SDCKE High after SDCK Rising Edge 2.9 ns
SDRAMC5SDCS Low before SDCK Rising Edge 7.5 ns
SDRAMC6SDCS High after SDCK Rising Edge 1.6 ns
SDRAMC7RAS Low before SDCK Rising Edge 7.2 ns
SDRAMC8RAS High after SDCK Rising Edge 2.3 ns
SDRAMC9SDA10 Change before SDCK Rising Edge 7.6 ns
SDRAMC10 SDA10 Change after SDCK Rising Edge 1.9 ns
SDRAMC11 Address Change before SDCK Rising Edge 6.2 ns
SDRAMC12 Address Change after SDCK Rising Edge 2.2 ns
981
32072H–AVR32–10/2012
AT32UC3A3
SDRAMC13 Bank Change before SDCK Rising Edge 6.3 ns
SDRAMC14 Bank Change after SDCK Rising Edge 2.4 ns
SDRAMC15 CAS Low before SDCK Rising Edge 7.4 ns
SDRAMC16 CAS High after SDCK Rising Edge 1.9 ns
SDRAMC17 DQM Change before SDCK Rising Edge 6.4 ns
SDRAMC18 DQM Change after SDCK Rising Edge 2.2 ns
SDRAMC19 D0-D15 in Setup before SDCK Rising Edge 9 ns
SDRAMC20 D0-D15 in Hold after SDCK Rising Edge 0 ns
SDRAMC23 SDWE Low before SDCK Rising Edge 7.6 ns
SDRAMC24 SDWE High after SDCK Rising Edge 1.8 ns
SDRAMC25 D0-D15 Out Valid before SDCK Rising Edge 7.1 ns
SDRAMC26 D0-D15 Out Valid after SDCK Rising Edge 1.5 ns
Table 36-36. SDRAM Clock Signal
Symbol Parameter Conditions Min. Max. Unit
982
32072H–AVR32–10/2012
AT32UC3A3
Figure 36-9. SDRAMC Signals relative to SDCK.
RAS
A0 - A9,
A11 - A13
D0 - D15
Read
SDCK
SDA10
D0 - D15
to Write
SDRAMC1
SDCKE
SDRAMC2SDRAMC3SDRAMC4
SDCS
SDRAMC5SDRAMC6SDRAMC5SDRAMC6SDRAMC5SDRAMC6
SDRAMC7SDRAMC8
CAS
SDRAMC15 SDRAMC16 SDRAMC15 SDRAMC16
SDWE
SDRAMC23 SDRAMC24
SDRAMC9SDRAMC10
SDRAMC9SDRAMC10
SDRAMC9SDRAMC10
SDRAMC11 SDRAMC12 SDRAMC11 SDRAMC12
SDRAMC11 SDRAMC12
BA0/BA1
SDRAMC13 SDRAMC14 SDRAMC13 SDRAMC14 SDRAMC13 SDRAMC14
SDRAMC17 SDRAMC18
SDRAMC17 SDRAMC18
DQM0 -
DQM3
SDRAMC19 SDRAMC20
SDRAMC25 SDRAMC26
983
32072H–AVR32–10/2012
AT32UC3A3
36.12 JTAG Characteristics
36.12.1 JTAG Interface Signals
Table 36-37. JTAG Interface Timing Specif ication
Symbol Parameter Conditions (1)
1. VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40pF
Min. Max. Unit
JTAG0TCK Low Half-period 6 ns
JTAG1TCK High Half-period 3 ns
JTAG2TCK Period 9ns
JTAG3TDI, TMS Setup bef o re TCK High 1 ns
JTAG4TDI, TMS Hold after TCK High 0 ns
JTAG5TD O Hold Time 4 ns
JTAG6TCK Low to TDO Valid 6ns
JTAG7Device Inputs Setup Time ns
JTAG8Device Inputs Hold Time ns
JTAG9Device Outputs Hold Time ns
JTAG10 TCK to Device Outputs Valid ns
984
32072H–AVR32–10/2012
AT32UC3A3
Figure 36-10. JTAG Interface Signals
36.13 SPI Characteristics
Figure 36-11. SPI Master mode with (CPOL= NCPHA= 0) or (CPOL= NCPHA= 1)
TCK
JTAG9
TMS/TDI
TDO
Device
Outputs
JTAG5
JTAG4
JTAG3
JTAG
0JTAG1
JTAG2
JTAG10
Device
Inputs
JTAG8
JTAG7
JTAG6
SPCK
MISO
MOSI
SPI2
SPI0SPI1
985
32072H–AVR32–10/2012
AT32UC3A3
Figure 36-12. SPI Master mode with (CPOL= 0 and NCPHA= 1) or (CPO L= 1 and NCPHA= 0)
Figure 36-13. SPI Slave mode with (CPOL= 0 and NCPHA= 1) or (CPOL= 1 and NCPHA= 0)
Figure 36-14. SPI Slave mode with (CPOL= NCPHA= 0) or (CPOL= NCPHA= 1)
SPCK
MISO
MOSI
SPI5
SPI3SPI4
SPCK
MISO
MOSI
SPI6
SPI7SPI8
SPCK
MISO
MOSI
SPI9
SPI10 SPI11
986
32072H–AVR32–10/2012
AT32UC3A3
36.14 MCI The High Speed MultiMedia Card Interface (MCI) supports the MultiMedia Card (MMC) Sp ecifi-
cation V4.2, the SD Memory Card Specification V2.0, the SDIO V1.1 specification and CE-ATA
V1.1.
Table 36-38. SPI Timings
Symbol Parameter Conditions (1)
1. 3.3V domain: VVDDIO from 3.0V to 3.6V, maximum external capacitor = 40 pF
Min. Max. Unit
SPI0MISO Setup time before SPCK rises
(master) 3.3V domain 22 +
(tCPMCK)/2 (2)
2. tCPMCK: Master Clock period in ns.
ns
SPI1MISO Hold time after SPCK rises
(master) 3.3V domain 0 ns
SPI2SPCK rising to MOSI Delay
(master) 3.3V domain 7 ns
SPI3MISO Setup time before SPCK falls
(master) 3.3V domain 22 +
(tCPMCK)/2 (3)
3. tCPMCK: Master Clock period in ns.
ns
SPI4MISO Hold time after SPCK falls
(master) 3.3V domain 0 ns
SPI5SPCK f alling to MOSI Delay
master) 3.3V domain 7 ns
SPI6SPCK f alling to MISO Delay
(slave) 3.3V domain 26.5 ns
SPI7MOSI Setup time before SPCK rises
(slave) 3.3V domain 0 ns
SPI8MOSI Hold time after SPCK rises
(slave) 3.3V domain 1.5 ns
SPI9SPCK rising to MISO Delay
(slave) 3.3V domain 27 ns
SPI10 MOSI Setup time before SPCK falls
(slave) 3.3V domain 0 ns
SPI11 MOSI Hold time after SPCK falls
(slave) 3.3V domain 1 ns
987
32072H–AVR32–10/2012
AT32UC3A3
36.15 Flash Memory Characteristics
The following table gives the device maximum operating frequency depending on the field FWS
of the Flash FSR register. This field defines the number of wait states required to access the
Flash Memory. Flash operating frequency equals the CPU/HSB frequency.
Table 36-39. Flash Operating Freq ue n cy
Symbol Parameter Conditions Min. Typ. Max. Unit
FFOP Flash Operating Frequency
FWS = 0
High Speed Read Mode Disable
-40°C < Ambient Temperature < 85°C 36 MHz
FWS = 1
High Speed Read Mode Disable
-40°C < Ambient Temperature < 85°C 66 MHz
FWS = 0
High Speed Read Mode Enable
-40°C < Ambient Temperature < 70°C 42 MHz
FWS = 1
High Speed Read Mode Enable
-40°C < Ambient Temperature < 70°C 84 MHz
Table 36-40. Parts Programming Time
Symbol Parameter Conditions Min. Typ. Max. Unit
TFPP Page Programming Time 5 ms
TFFP Fuse Programming Time 0.5 ms
TFCE Chip erase Time 8ms
Table 36-41. Flash Parameters
Symbol Parameter Conditions Min. Typ. Max. Unit
NFARRAY Flash Array Write/Erase cycle 100K cycle
NFFUSE General Pur pose Fuses write cycle 1000 cycle
TFDR Flash Data Retention Time 15 year
988
32072H–AVR32–10/2012
AT32UC3A3
37. Mechanical Characteristics
37.1 Thermal Considerations
37.1.1 Thermal Data Table 37-1 summarizes the thermal resistance data depending on the package.
37.1.2 Junction Temperature
The average chip-junction temperature, TJ, in °C can be obtained from the following:
1.
2.
where:
•θJA = package thermal resistance, Junction-to-ambient (°C/W), provided in Table 37-1 on
page 988.
•θJC = package thermal resistance, Junction-to-ca se thermal resistance (°C/W), provided in
Table 37-1 on page 988.
•θHEAT SINK = cooling device thermal resistance (°C/W), pro vided in the device datasheet.
•P
D = device power consumption (W) estimated from data provided in the section ”Regulator
characteristics” on page 963.
•T
A = ambient temperature (°C).
From the first equation, the user can derive the estimated lifetime of the chip and decide if a
cooling device is necessary or not. If a cooling device is to be fitted on the chip, the second
equation shou ld be used to compute the resulting average chip-junction temperature TJ in °C.
Table 37-1. Thermal Resistance Data
Symbol Parameter Condition Package Typ Unit
θJA Junction-to-ambient thermal resistance Still Air TQFP144 40 .3 °C/W
θJC Junction-to-case thermal resistance TQFP144 9.5
θJA Junction-to-ambient thermal resistan ce Still Air TFBGA144 28.5 °C/W
θJC Junction-to-case thermal resistance TFBGA144 6.9
θJA Junction-to-ambient thermal resistan ce Still Air VFBGA100 31.1 °C/W
θJC Junction-to-case thermal resistance VFBGA100 6.9
TJTAPDθJA
×()+=
TJTAP(Dθ( HEATSINK
×θ
JC))++=
989
32072H–AVR32–10/2012
AT32UC3A3
37.2 Package Drawings
Figure 37-1. TFBGA 144 package drawing
990
32072H–AVR32–10/2012
AT32UC3A3
Figure 37-2. LQFP-14 4 pa ckage drawing
Table 37-2. Device and Package Maximum Weight
1300 mg
Table 37-3. Package Characteristics
Moisture Sensitivity Level MSL3
Table 37-4. Package Reference
JEDEC Drawing Reference MS-026
JESD97 Classification E3
991
32072H–AVR32–10/2012
AT32UC3A3
Figure 37-3. VFBGA-100 package drawing
992
32072H–AVR32–10/2012
AT32UC3A3
37.3 Soldering Profile
Table 37-5 gives the recommended soldering profile from J-STD-20.
Note: It is recommended to apply a soldering temperature higher than 250°C.
A maximum of three reflow passes is allowed per component.
Table 37-5. Soldering Profile
Profile Feature Green Package
Average Ramp-up Rate (217°C to Peak) 3°C/Second max
Preheat Temperature 175°C ±25°C 150-200°C
Time Maintained Above 217°C 60-150 seconds
Time within 5°C of Actual Peak Temperature 30 seconds
Pe ak Temperature Range 260 (+0/-5°C)
Ramp-down Rate 6°C/Second max.
Time 25°C to Peak Temperature 8 minutes max
993
32072H–AVR32–10/2012
AT32UC3A3
38. Ordering Information
Device Ordering Code Package Conditioning Temperature Oper a ting
Range
AT32UC3A3256S AT32UC3A3256S-ALUT 144-lead LQFP Tray Industrial (-40⋅C to 85⋅C)
AT32UC3A3256S-ALUR 144-lead LQFP Reels Indu strial (-40⋅C to 85⋅C)
AT32UC3A3256S-CTUT 144-ball TFBGA Tray Industr ial (-40⋅C to 85⋅C)
AT32UC3A3256S-CTUR 144-ball TFBGA Reels Industrial (-40⋅C to 85⋅C)
AT32UC3A3256 AT32UC3A3256-ALUT 144-lead LQFP Tray Industrial (-40⋅C to 85⋅C)
AT32UC3A3256-ALUR 144-lead LQFP Reels Industrial (-4 0⋅C to 85⋅C)
AT32UC3A3256-CTUT 144-ball TFBGA Tray Industrial (-40⋅C to 85⋅C)
AT32UC3A3256-CTUR 144-ball TFBGA Reels Industri al (-40⋅C to 85⋅C)
AT32UC3A3128S AT32UC3A3128S-ALUT 144-lead LQFP Tray Industrial (-40⋅C to 85⋅C)
AT32UC3A3128S-ALUR 144-lead LQFP Reels Indu strial (-40⋅C to 85⋅C)
AT32UC3A3128S-CTUT 144-ball TFBGA Tray Industr ial (-40⋅C to 85⋅C)
AT32UC3A3128S-CTUR 144-ball TFBGA Reels Industrial (-40⋅C to 85⋅C)
AT32UC3A3128 AT32UC3A3128-ALUT 144-lead LQFP Tray Industrial (-40⋅C to 85⋅C)
AT32UC3A3128-ALUR 144-lead LQFP Reels Industrial (-4 0⋅C to 85⋅C)
AT32UC3A3128-CTUT 144-ball TFBGA Tray Industrial (-40⋅C to 85⋅C)
AT32UC3A3128-CTUR 144-ball TFBGA Reels Industri al (-40⋅C to 85⋅C)
AT32UC3A364S AT 32UC3A364S-ALUT 144-lead LQFP Tray Indu strial (-40⋅C to 85⋅C)
AT32UC3A364S-ALUR 144-lead LQFP Reels Industrial (-40⋅C to 85⋅C)
AT32UC3A364S-CTUT 144-ball TFBGA Tray Industrial (-40⋅C to 85⋅C)
AT32UC3A364S-CTUR 144-ball TFBGA Reels Industrial (-4 0⋅C to 85⋅C)
AT32UC3A364 AT32UC3A364-ALUT 144-lead LQFP Tray Industrial (-40⋅C to 85⋅C)
AT32UC3A364-ALUR 144-lead LQFP Reels Industrial (-40⋅C to 85⋅C)
AT32UC3A364-CTUT 144-ball TFBGA Tray Industrial (-40⋅C to 85⋅C)
AT32UC3A364-CTUR 144-ball TFBGA Reels Industrial (-40⋅C to 85⋅C)
AT32UC3A4256S AT32U C3A4256S-C1UT 100-ball VFBGA Tray Industrial (-40⋅C to 85⋅C)
AT32UC3A4256S-C1UR 100-ball VFBGA Reels Industr ial (-40⋅C to 85⋅C)
AT32UC3A4256 AT32UC3A4256-C1UT 100-ball VFBGA Tray Industrial (-40⋅C to 85⋅C)
AT32UC3A4256-C1UR 100-ball VFBGA Reels Industrial (-40⋅C to 85⋅C)
AT32UC3A4128S AT32U C3A4128S-C1UT 100-ball VFBGA Tray Industrial (-40⋅C to 85⋅C)
AT32UC3A4128S-C1UR 100-ball VFBGA Reels Industr ial (-40⋅C to 85⋅C)
AT32UC3A4128 AT32UC3A4128-C1UT 100-ball VFBGA Tray Industrial (-40⋅C to 85⋅C)
AT32UC3A4128-C1UR 100-ball VFBGA Reels Industrial (-40⋅C to 85⋅C)
AT32UC3A464S AT 32UC3A464S-C1UT 100-ball VFBGA Tray Industrial (-40⋅C to 85⋅C)
AT32UC3A464S-C1UR 100-ball VFBGA Reels Industri al (-40⋅C to 85⋅C)
AT32UC3A464 AT32UC3A464-C1UT 100-ball VFBGA Tray Industrial (-40⋅C to 85⋅C)
AT32UC3A464-C1UR 1 00-ball VFBGA Reels Industrial (-40⋅C to 85⋅C)
994
32072H–AVR32–10/2012
AT32UC3A3
39. Errata
39.1 Rev. H
39.1.1 General Devices with Date Code lower than 1233 cannot operate with CPU frequency higher
than 66MHz in 1WS and 36MHz in 0WS in the whole temperature range
Fix/Workaround
None
DMACA data transfer fails when CTLx.SRC_TR_WIDTH is not equal to
CTLx.DST_TR_WIDTH
Fix/Workaround
For any DMACA transfer make sure CTLx.SRC_TR_WIDTH = CTLx.DST_TR_WIDTH.
39.1.2 Processor and Architecture
LDM instruction with PC in the register list and without ++ increments Rp
For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie
the pointer is always updated. This happens even if the ++ field is cleared. Specifically, the
increment of the pointer is done in parallel with the testing of R12.
Fix/Workaround
None.
Hardware breakpoints may corrupt MAC results
Hardware breakpoints on MAC instructions may corrupt the destination register of the MAC
instruction.
Fix/Workaround
Place breakpoints on earlie r or later instructions.
When the main clock is RCSYS, TIMER_CLOCK5 is equal to PBA clock
When the main clock is generated from RCSYS, TIMER_CLOCK5 is equal to PBA Clock
and not PBA Clock / 128.
Fix/Workaround
None.
MPU
Privilege violation when using interrupts in application mode with protected system
stack
If the system stack is protected by the MPU and an interrupt occurs in application mode, an
MPU DTLB exception will occur.
Fix/Workaround
Make a DTLB Protection (Write) exception handler which permits the interrupt request to be
handled in privileged mo de.
39.1.3 USB
UPCFGn.INTFRQ is irrelevant for isochronous pipe
As a consequence, isochronous IN and OUT tokens are sent every 1ms (Full Speed), or
every 125uS (High Speed).
Fix/Workaround
995
32072H–AVR32–10/2012
AT32UC3A3
For higher polling tim e, the software must freeze the pipe for the desired period in order to
prevent any "extra" token.
39.1.4 ADC
Sleep Mode activation needs additional A to D conversion
If the ADC sleep mode is activated when the ADC is idle the AD C will not enter sleep mode
before after the next AD conversion.
Fix/Workaround
Activate the sleep mode in the mode register and then perform an AD conversion.
39.1.5 USART
ISO7816 info register US_NER cannot be read
The NER register always returns zero.
Fix/Workaround
None.
The LIN ID is not transmitted in mode PDCM='0'
Fix/Workaround
Using USART in mode LIN master with the PDCM bit = '0', the LINID written at the first
address of the transmit buffe r is not used. The LINID must b e written in the LINIR register,
after the configurat ion and star t of the PDCA transf er. Wr iting the LINID in th e LINIR register
will start the transfer whenever the PDCA transfer is ready.
The LINID interrupt is only available for the header reception and not available for the
header transmis sion
Fix/Workaround
None.
USART LIN mode is not functional with the PDCA if PDCM bit in LINMR register is set
to 1
If a PDCA transfer is initiated in USART LIN mode with PDCM bit set to 1, the transfer never
starts.
Fix/Workaround
Only use PDCM=0 configuration with the PDCA tran sfe r.
SPI
SPI disable does not work in SLAVE mode
SPI disable does not work in SLAVE mode.
Fix/Workaround
Read the last received data, then perform a software reset by writing a one to the Software
Reset bit in the Control Register (CR.SWRST).
SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and
NCPHA=0
When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one
(CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0,
then an additional pulse will be generated on SCK.
Fix/Workaround
When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1
if CSRn.CPOL=1 and CSRn.NCPHA=0.
996
32072H–AVR32–10/2012
AT32UC3A3
SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0
When CSR0.CSAAT==1 and mode fault de tection is enabled (MR.MODFDIS==0), the SPI
module will not start a data transfer.
Fix/Workaround
Disable mode fault detection by writing a one to MR.MODFDIS.
Disabling SPI has no effect on the SR.TDRE bit
Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered
when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE. If SPI is
disabled during a PDCA transfer, the PDCA will continue to write data to TDR until its buffer
is empty, and this data will be lost.
Fix/Workaround
Disable the PDCA, add two NOPs, and disab le t he SPI . To cont in ue the tr ansf er , ena ble the
SPI and PDCA.
Power Manager
OSC32 not functionnal in Crystal Modes (OSC32CTRL.MODE=1 or
OSC32CTRL.MODE=2)
OSC32 clock output is not active even if the oscillation signal is present on XIN32/XOUT32
pins.
OSC32RDY bit may still set even if the CLK32 is not active.
External clock mode (OSC32CTRL.MODE=0) is not affected.
Fix/Workaround
None.
Clock sources will not be stopped in STATIC sleep mode if the difference between
CPU and PBx division factor is too high
If the division factor between the CPU/HSB and PBx frequencies is more than 4 when going
to a sleep mode where the system RC oscillator is turned off, then high speed clock sources
will not be turned off. This will resu lt in a significantly higher power consumption during the
sleep mode.
Fix/Workaround
Before going to sleep modes where the system RC oscillator is stopped, make sure that the
factor between the CPU/HSB and PBx frequen cies is less than or equal to 4.
PDCA
PCONTROL.CHxRES is non-functional
PCONTROL.CHxRES is non-functional. Counters are reset at power-on, and cannot be
reset by software.
Fix/Workaround
Software needs to keep history of performance counters.
Transfer error will stall a transmit peripheral handshake interface
If a transfer error is encountered on a channel transmitting to a peripheral, the peripheral
handshake of the active channel will stall and the PDCA will not do any more transfers on
the affected peripheral handshake interface.
Fix/Workaround
Disable and then enable the peripheral after the transfer error.
AES
997
32072H–AVR32–10/2012
AT32UC3A3
URAD (Unspecified Register Access Detection Status) does not detect read accesses
to the write-only KEYW[5..8]R registers
Fix/Workaround
None.
39.1.6 HMATRIX
In the PRAS and PRBS registers, the MxPR fields are only two bits
In the PRAS and PRBS reg isters, the MxPR f ields are only t wo bits wide, instea d of four bits.
The unused bits are undefined when reading the registers.
Fix/Workaround
Mask undefined bits when reading PRAS and PRBS.
39.1.7 TWIM
TWIM SR.IDLE goes high immediately when NAK is rece ived
When a NAK is received and there is a non-zero number of bytes to be transmitted,
SR.IDLE goes high immediately and does not wait for the STO P condition to be sent. This
does not cause any problem just by itself, but can cause a problem if software waits for
SR.IDLE to go high and then immediately disables the TWIM by writing a one to CR.MDIS.
Disabling the TWIM causes the TWCK and TWD pins to go high immediately, so the STOP
condition will not be transmitted correctly.
Fix/Workaround
If possible, d o no t dis ab le th e TWIM . If it is absolutely n e ces sa ry to disable th e TWIM, ther e
must be a software delay of at least two TWCK periods between the detection of
SR.IDLE==1 and the disabling of the TWIM.
TWIM TWALM polarity is wrong
The TWALM signal in the TWIM is active high instea d of active low.
Fix/Workaround
Use an external inverter to invert the signal goin g into the TWIM. When using both TWIM
and TWIS on the same pins, the TWALM cannot be used.
SMBALERT bit may be set after res et
The SMBus Alert (SMBALERT) bit in the Stat us Register ( SR) might be er roneously set aft er
system reset.
Fix/Workaround
After system reset, clea r the SR.SMBALERT bit before commencing any TWI transfer.
TWIS
Clearing the NAK bit before the BTF bit is set locks up the TWI bus
When the TWIS is in transmit mode, clearing t he NAK Received (NAK) bit o f the St atus Reg-
ister (SR) before the end of the Acknowledge/Not Acknowledge cycle will cause the TWIS to
attempt to continue transmitting data, thus locking up the bus.
Fix/Workaround
Clear SR.NAK only after the Byte Transfer Finished (BTF) bit of the same register has been
set.
TWIS stretch on Address match error
When the TWIS stretches TWCK due to a slave address match, it also holds TWD low for
the same duration if it is to be receiving data. When TWIS releases TWCK, it releases TWD
at the same time. This can cause a TWI timing violation.
998
32072H–AVR32–10/2012
AT32UC3A3
Fix/Workaround
None.
SSC
Frame Synchro and Frame Synchro Data are delayed by one clock cycle
The frame synchro and the frame synchro data are delayed from 1 SSC_CLOCK when:
- Clock is CKDIV
- The START is selected on either a frame synchro edge or a level
- Frame synchro data is enabled
- Transmit clock is gated on output (through CKO field)
Fix/Workaround
Transmit or receive CL OCK must not be gated (by the mean of CKO field) when START
condition is performed on a generated frame synchro.
39.1.8 FLASHC
Corrupted read in flash may happen after fuses write or erase operations (FLASHC
LP, UP, WGPB, EGPB, SSB, PGPFB, EAGPF commands)
After a flash fuse write or erase operation (FLASHC LP, UP, WGPB, EGPB, SSB, PGPFB,
EAGPF commands), reading (data read or code fetch) in flash may fail. This may lead to an
exception or to other err ors derived from this corrupted read access.
Fix/Workaround
Before the flash fuse write or erase operation, enable the flash high speed mode (FLASHC
HSEN command). The flash fuse write or erase operations (FLASHC LP, UP, WGPB,
EGPB, SSB, PGPFB, EAGPF commands) must be issued from RAM or through the EBI.
After these commands, read 3 times one flash page initialized to 00h. Disable the flash high
speed mode (FLASHC HSDIS command). It is then possible to safely read or code fetch the
flash.
39.2 Rev. E
39.2.1 General Devices cannot operate with CPU frequency higher than 66MHz in 1WS and 36MHz in
0WS
Fix/Workaround
None
Increased Power Consumption in VDDIO in sleep modes
If the OSC0 is enabled in crystal mode when entering a sleep mode where the OSC0 is dis-
abled, this will lead to an increased power consumption in VDDIO.
Fix/Workaround
Disable the OSC0 through the System Control Interface (SCIF) before going to any sleep
mode where the OSC0 is disabled, or pull down or up XIN0 and XOUT0 with 1 Mohm
resistor.
Power consumption in static mode The power consumption in static mode can be up
to 330µA on some part s (t yp ic a l at 25 °C )
Fix/Workaround
Set to 1b bit CORRS4 of the ECCHRS mode register (MD). In C-code: *((volatile int*)
(0xFFFE2404))= 0x400.
999
32072H–AVR32–10/2012
AT32UC3A3
DMACA data transfer fails when CTLx.SRC_TR_WIDTH is not equal to
CTLx.DST_TR_WIDTH
Fix/Workaround
For any DMACA transfer make sure CTLx.SRC_TR_WIDTH = CTLx.DST_TR_WIDTH.
3.3V supply monitor is not available
FGPFRLO[30:2 9] are reserved and should not be used by the application.
Fix/Workaround
None.
Service access bus (SAB) can not access DMACA registers
Fix/Workaround
None.
Processor and Architecture
LDM instruction with PC in the register list and without ++ increments Rp
For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie
the pointer is always updated. This happens even if the ++ field is cleared. Specifically, the
increment of the pointer is done in parallel with the testing of R12.
Fix/Workaround
None.
Hardware breakpoints may corrupt MAC results
Hardware breakpoints on MAC instructions may corrupt the destination register of the MAC
instruction.
Fix/Workaround
Place breakpoints on earlie r or later instructions.
When the main clock is RCSYS, TIMER_CLOCK5 is equal to PBA clock
When the main clock is generated from RCSYS, TIMER_CLOCK5 is equal to PBA Clock
and not PBA Clock / 128.
Fix/Workaround
None.
MPU
Privilege violation when using interrupts in application mode with protected system
stack
If the system stack is protected by the MPU and an interrupt occurs in application mode, an
MPU DTLB exception will occur.
Fix/Workaround
Make a DTLB Protection (Write) exception handler which permits the interrupt request to be
handled in privileged mo de.
39.2.2 USB
UPCFGn.INTFRQ is irrelevant for isochronous pipe
As a consequence, isochronous IN and OUT tokens are sent every 1ms (Full Speed), or
every 125uS (High Speed).
Fix/Workaround
For higher polling tim e, the software must freeze the pipe for the desired period in order to
prevent any "extra" token.
1000
32072H–AVR32–10/2012
AT32UC3A3
39.2.3 ADC
Sleep Mode activation needs additional A to D conversion
If the ADC sleep mode is activated when the ADC is idle the AD C will not enter sleep mode
before after the next AD conversion.
Fix/Workaround
Activate the sleep mode in the mode register and then perform an AD conversion.
39.2.4 USART
ISO7816 info register US_NER cannot be read
The NER register always returns zero.
Fix/Workaround
None.
The LIN ID is not transmitted in mode PDCM='0'
Fix/Workaround
Using USART in mode LIN master with the PDCM bit = '0', the LINID written at the first
address of the transmit buffe r is not used. The LINID must b e written in the LINIR register,
after the configurat ion and star t of the PDCA transf er. Wr iting the LINID in th e LINIR register
will start the transfer whenever the PDCA transfer is ready.
The LINID interrupt is only available for the header reception and not available for the
header transmis sion
Fix/Workaround
None.
USART LIN mode is not functional with the PDCA if PDCM bit in LINMR register is set
to 1
If a PDCA transfer is initiated in USART LIN mode with PDCM bit set to 1, the transfer never
starts.
Fix/Workaround
Only use PDCM=0 configuration with the PDCA tran sfe r.
The RTS output does not function correctly in hardware handshaking mode
The RTS signal is not generated p roperly wh en the USART receives da ta in hard ware hand-
shaking mode. When the Peripheral DMA receive buffer becomes full, the RTS output
should go high, but it will stay low.
Fix/Workaround
Do not use the hardware handshaking mode of the USART. If it is necessary to drive the
RTS output high when the Peripheral DMA receive buffer becomes full, use the normal
mode of the USART. Configure the Peripheral DMA Controller to signal an interrupt when
the receive buffer is full. In the in terrupt handler code, write a one to th e RTSDIS bit in the
USART Control Register (CR). This will drive the RTS output high. After the next DMA trans-
fer is started and a receive buffer is available, write a one to the RTSEN bit in the USART
CR so that RTS will be driven low.
ISO7816 Mode T1: RX impossible after any TX
RX impossible after any TX.
Fix/Workaround
SOFT_RESET on RX+ Config US_MR + Config_US_CR.
SPI
1001
32072H–AVR32–10/2012
AT32UC3A3
SPI disable does not work in SLAVE mode
SPI disable does not work in SLAVE mode.
Fix/Workaround
Read the last received data, then perform a software reset by writing a one to the Software
Reset bit in the Control Register (CR.SWRST).
SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and
NCPHA=0
When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one
(CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0,
then an additional pulse will be generated on SCK.
Fix/Workaround
When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1
if CSRn.CPOL=1 and CSRn.NCPHA=0.
SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0
When CSR0.CSAAT==1 and mode fault de tection is enabled (MR.MODFDIS==0), the SPI
module will not start a data transfer.
Fix/Workaround
Disable mode fault detection by writing a one to MR.MODFDIS.
Disabling SPI has no effect on the SR.TDRE bit
Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered
when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE. If SPI is
disabled during a PDCA transfer, the PDCA will continue to write data to TDR until its buffer
is empty, and this data will be lost.
Fix/Workaround
Disable the PDCA, add two NOPs, and disab le t he SPI . To cont in ue the tr ansf er , ena ble the
SPI and PDCA.
Power Manager
OSC32 not functionnal in Crystal Modes (OSC32CTRL.MODE=1 or
OSC32CTRL.MODE=2)
OSC32 clock output is not active even if the oscillation signal is present on XIN32/XOUT32
pins.
OSC32RDY bit may still set even if the CLK32 is not active.
External clock mode (OSC32CTRL.MODE=0) is not affected.
Fix/Workaround
None.
Clock sources will not be stopped in STATIC sleep mode if the difference between
CPU and PBx division factor is too high
If the division factor between the CPU/HSB and PBx frequencies is more than 4 when going
to a sleep mode where the system RC oscillator is turned off, then high speed clock sources
will not be turned off. This will resu lt in a significantly higher power consumption during the
sleep mode.
Fix/Workaround
Before going to sleep modes where the system RC oscillator is stopped, make sure that the
factor between the CPU/HSB and PBx frequen cies is less than or equal to 4.
PDCA
1002
32072H–AVR32–10/2012
AT32UC3A3
PCONTROL.CHxRES is non-functional
PCONTROL.CHxRES is non-functional. Counters are reset at power-on, and cannot be
reset by software.
Fix/Workaround
Software needs to keep history of performance counters.
Transfer error will stall a transmit peripheral handshake interface
If a transfer error is encountered on a channel transmitting to a peripheral, the peripheral
handshake of the active channel will stall and the PDCA will not do any more transfers on
the affected peripheral handshake interface.
Fix/Workaround
Disable and then enable the peripheral after the transfer error.
AES
URAD (Unspecified Register Access Detection Status) does not detect read accesses
to the write-only KEYW[5..8]R registers
Fix/Workaround
None.
39.2.5 HMATRIX
In the PRAS and PRBS registers, the MxPR fields are only two bits
In the PRAS and PRBS reg isters, the MxPR f ields are only t wo bits wide, instea d of four bits.
The unused bits are undefined when reading the registers.
Fix/Workaround
Mask undefined bits when reading PRAS and PRBS.
39.2.6 TWIM
TWIM SR.IDLE goes high immediately when NAK is rece ived
When a NAK is received and there is a non-zero number of bytes to be transmitted,
SR.IDLE goes high immediately and does not wait for the STO P condition to be sent. This
does not cause any problem just by itself, but can cause a problem if software waits for
SR.IDLE to go high and then immediately disables the TWIM by writing a one to CR.MDIS.
Disabling the TWIM causes the TWCK and TWD pins to go high immediately, so the STOP
condition will not be transmitted correctly.
Fix/Workaround
If possible, d o no t dis ab le th e TWIM . If it is absolutely n e ces sa ry to disable th e TWIM, ther e
must be a software delay of at least two TWCK periods between the detection of
SR.IDLE==1 and the disabling of the TWIM.
TWIM TWALM polarity is wrong
The TWALM signal in the TWIM is active high instea d of active low.
Fix/Workaround
Use an external inverter to invert the signal goin g into the TWIM. When using both TWIM
and TWIS on the same pins, the TWALM cannot be used.
SMBALERT bit may be set after res et
The SMBus Alert (SMBALERT) bit in the Stat us Register ( SR) might be er roneously set aft er
system reset.
Fix/Workaround
After system reset, clea r the SR.SMBALERT bit before commencing any TWI transfer.
1003
32072H–AVR32–10/2012
AT32UC3A3
TWIS
Clearing the NAK bit before the BTF bit is set locks up the TWI bus
When the TWIS is in transmit mode, clearing t he NAK Received (NAK) bit o f the St atus Reg-
ister (SR) before the end of the Acknowledge/Not Acknowledge cycle will cause the TWIS to
attempt to continue transmitting data, thus locking up the bus.
Fix/Workaround
Clear SR.NAK only after the Byte Transfer Finished (BTF) bit of the same register has been
set.
TWIS stretch on Address match error
When the TWIS stretches TWCK due to a slave address match, it also holds TWD low for
the same duration if it is to be receiving data. When TWIS releases TWCK, it releases TWD
at the same time. This can cause a TWI timing violation.
Fix/Workaround
None.
MCI
MCI_CLK features is not available on PX12, PX13 and PX40
Fix/Workaround
MCI_CLK feature is availabl e on PA27 only.
The busy signal of the responses R1b is not taken in account for CMD12
STOP_TRANSFER
It is not possible to know the busy status of the card during the response (R1b) for the com-
mands CMD12.
Fix/Workaround
The card busy line should be polled through the GPIO Input Value register (IVR) for com-
mands CMD12.
SSC
Frame Synchro and Frame Synchro Data are delayed by one clock cycle
The frame synchro and the frame synchro data are delayed from 1 SSC_CLOCK when:
- Clock is CKDIV
- The START is selected on either a frame synchro edge or a level
- Frame synchro data is enabled
- Transmit clock is gated on output (through CKO field)
Fix/Workaround
Transmit or receive CL OCK must not be gated (by the mean of CKO field) when START
condition is performed on a generated frame synchro.
39.2.7 FLASHC
Corrupted read in flash may happen after fuses write or erase operations (FLASHC
LP, UP, WGPB, EGPB, SSB, PGPFB, EAGPF commands)
After a flash fuse write or erase operation (FLASHC LP, UP, WGPB, EGPB, SSB, PGPFB,
EAGPF commands), reading (data read or code fetch) in flash may fail. This may lead to an
exception or to other err ors derived from this corrupted read access.
Fix/Workaround
Before the flash fuse write or erase operation, enable the flash high speed mode (FLASHC
HSEN command). The flash fuse write or erase operations (FLASHC LP, UP, WGPB,
EGPB, SSB, PGPFB, EAGPF commands) must be issued from RAM or through the EBI.
1004
32072H–AVR32–10/2012
AT32UC3A3
After these commands, read 3 times one flash page initialized to 00h. Disable the flash high
speed mode (FLASHC HSDIS command). It is then possible to safely read or code fetch the
flash.
39.3 Rev. D
39.3.1 General Devices cannot operate with CPU frequency higher than 66MHz in 1WS and 36MHz in
0WS
Fix/Workaround
None
DMACA data transfer fails when CTLx.SRC_TR_WIDTH is not equal to
CTLx.DST_TR_WIDTH
Fix/Workaround
For any DMACA transfer make sure CTLx.SRC_TR_WIDTH = CTLx.DST_TR_WIDTH.
3.3V supply monitor is not available
FGPFRLO[30:2 9] are reserved and should not be used by the application.
Fix/Workaround
None.
Service access bus (SAB) can not access DMACA registers
Fix/Workaround
None.
Processor and Architecture
LDM instruction with PC in the register list and without ++ increments Rp
For LDM with PC in the register list: the instruction behaves as if the ++ field is always set, ie
the pointer is always updated. This happens even if the ++ field is cleared. Specifically, the
increment of the pointer is done in parallel with the testing of R12.
Fix/Workaround
None.
Hardware breakpoints may corrupt MAC results
Hardware breakpoints on MAC instructions may corrupt the destination register of the MAC
instruction.
Fix/Workaround
Place breakpoints on earlie r or later instructions.
When the main clock is RCSYS, TIMER_CLOCK5 is equal to PBA clock
When the main clock is generated from RCSYS, TIMER_CLOCK5 is equal to PBA Clock
and not PBA Clock / 128.
Fix/Workaround
None.
RETE instruction does not clear SREG[L] from interrupts
The RETE instruction clears SREG[L] as expected from exceptions.
Fix/Workaround
When using the STCOND instruction, clear SREG[L] in the stacked value of SR before
returning fro m interr up ts with R ETE.
1005
32072H–AVR32–10/2012
AT32UC3A3
RETS behaves incorrectly when MPU is enabled
RETS behaves incorrectly when MPU is enabled and MPU is configured so that system
stack is not reada ble in unprivileged mode.
Fix/Workaround
Make system stack readable in unprivileged mode, or return from supervisor mode using
rete instead of rets. This requires:
1. Changing the mode bits from 001 to 110 before issuing the instruct ion. Updating the
mode bits to the desired value must be done using a single mtsr instruction so it is done
atomically. Even if this step is generally described as not safe in the UC technical reference
manual, it is safe in this very specific case.
2. Execute the RETE instruction.
In the PRAS and PRBS registers, the MxPR fields are only two bits
In the PRAS and PRBS reg isters, the MxPR f ields are only t wo bits wide, instea d of four bits.
The unused bits are undefined when reading the registers.
Fix/Workaround
Mask undefined bits when reading PRAS and PRBS.
Multiply instructions do not work on RevD
All the multiply instructions do not work.
Fix/Workaround
Do not use the multiply instructions.
MPU
Privilege violation when using interrupts in application mode with protected system
stack
If the system stack is protected by the MPU and an interrupt occurs in application mode, an
MPU DTLB exception will occur.
Fix/Workaround
Make a DTLB Protection (Write) exception handler which permits the interrupt request to be
handled in privileged mo de.
39.3.2 USB
UPCFGn.INTFRQ is irrelevant for isochronous pipe
As a consequence, isochronous IN and OUT tokens are sent every 1ms (Full Speed), or
every 125uS (High Speed).
Fix/Workaround
For higher polling tim e, the software must freeze the pipe for the desired period in order to
prevent any "extra" token.
39.3.3 ADC
Sleep Mode activation needs additional A to D conversion
If the ADC sleep mode is activated when the ADC is idle the AD C will not enter sleep mode
before after the next AD conversion.
Fix/Workaround
Activate the sleep mode in the mode register and then perform an AD conversion.
39.3.4 USART
ISO7816 info register US_NER cannot be read
The NER register always returns zero.
1006
32072H–AVR32–10/2012
AT32UC3A3
Fix/Workaround
None.
The LIN ID is not transmitted in mode PDCM='0'
Fix/Workaround
Using USART in mode LIN master with the PDCM bit = '0', the LINID written at the first
address of the transmit buffe r is not used. The LINID must b e written in the LINIR register,
after the configurat ion and star t of the PDCA transf er. Wr iting the LINID in th e LINIR register
will start the transfer whenever the PDCA transfer is ready.
The LINID interrupt is only available for the header reception and not available for the
header transmis sion
Fix/Workaround
None.
USART LIN mode is not functional with the PDCA if PDCM bit in LINMR register is set
to 1
If a PDCA transfer is initiated in USART LIN mode with PDCM bit set to 1, the transfer never
starts.
Fix/Workaround
Only use PDCM=0 configuration with the PDCA tran sfe r.
The RTS output does not function correctly in hardware handshaking mode
The RTS signal is not generated p roperly wh en the USART receives da ta in hard ware hand-
shaking mode. When the Peripheral DMA receive buffer becomes full, the RTS output
should go high, but it will stay low.
Fix/Workaround
Do not use the hardware handshaking mode of the USART. If it is necessary to drive the
RTS output high when the Peripheral DMA receive buffer becomes full, use the normal
mode of the USART. Configure the Peripheral DMA Controller to signal an interrupt when
the receive buffer is full. In the in terrupt handler code, write a one to th e RTSDIS bit in the
USART Control Register (CR). This will drive the RTS output high. After the next DMA trans-
fer is started and a receive buffer is available, write a one to the RTSEN bit in the USART
CR so that RTS will be driven low.
ISO7816 Mode T1: RX impossible after any TX
RX impossible after any TX.
Fix/Workaround
SOFT_RESET on RX+ Config US_MR + Config_US_CR.
SPI
SPI disable does not work in SLAVE mode
SPI disable does not work in SLAVE mode.
Fix/Workaround
Read the last received data, then perform a software reset by writing a one to the Software
Reset bit in the Control Register (CR.SWRST).
SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and
NCPHA=0
When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one
(CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0,
then an additional pulse will be generated on SCK.
1007
32072H–AVR32–10/2012
AT32UC3A3
Fix/Workaround
When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1
if CSRn.CPOL=1 and CSRn.NCPHA=0.
SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0
When CSR0.CSAAT==1 and mode fault de tection is enabled (MR.MODFDIS==0), the SPI
module will not start a data transfer.
Fix/Workaround
Disable mode fault detection by writing a one to MR.MODFDIS.
Disabling SPI has no effect on the SR.TDRE bit
Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered
when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE. If SPI is
disabled during a PDCA transfer, the PDCA will continue to write data to TDR until its buffer
is empty, and this data will be lost.
Fix/Workaround
Disable the PDCA, add two NOPs, and disab le t he SPI . To cont in ue the tr ansf er , ena ble the
SPI and PDCA.
Power Manager
OSC32 not functionnal in Crystal Modes (OSC32CTRL.MODE=1 or
OSC32CTRL.MODE=2)
OSC32 clock output is not active even if the oscillation signal is present on XIN32/XOUT32
pins.
OSC32RDY bit may still set even if the CLK32 is not active.
External clock mode (OSC32CTRL.MODE=0) is not affected.
Fix/Workaround
None.
Clock sources will not be stopped in STATIC sleep mode if the difference between
CPU and PBx division factor is too high
If the division factor between the CPU/HSB and PBx frequencies is more than 4 when going
to a sleep mode where the system RC oscillator is turned off, then high speed clock sources
will not be turned off. This will resu lt in a significantly higher power consumption during the
sleep mode.
Fix/Workaround
Before going to sleep modes where the system RC oscillator is stopped, make sure that the
factor between the CPU/HSB and PBx frequen cies is less than or equal to 4.
PDCA
PCONTROL.CHxRES is non-functional
PCONTROL.CHxRES is non-functional. Counters are reset at power-on, and cannot be
reset by software.
Fix/Workaround
Software needs to keep history of performance counters.
Transfer error will stall a transmit peripheral handshake interface
If a transfer error is encountered on a channel transmitting to a peripheral, the peripheral
handshake of the active channel will stall and the PDCA will not do any more transfers on
the affected peripheral handshake interface.
1008
32072H–AVR32–10/2012
AT32UC3A3
Fix/Workaround
Disable and then enable the peripheral after the transfer error.
AES
URAD (Unspecified Register Access Detection Status) does not detect read accesses
to the write-only KEYW[5..8]R registers
Fix/Workaround
None.
39.3.5 HMATRIX
In the PRAS and PRBS registers, the MxPR fields are only two bits
In the PRAS and PRBS reg isters, the MxPR f ields are only t wo bits wide, instea d of four bits.
The unused bits are undefined when reading the registers.
Fix/Workaround
Mask undefined bits when reading PRAS and PRBS.
39.3.6 TWIM
TWIM SR.IDLE goes high immediately when NAK is rece ived
When a NAK is received and there is a non-zero number of bytes to be transmitted,
SR.IDLE goes high immediately and does not wait for the STO P condition to be sent. This
does not cause any problem just by itself, but can cause a problem if software waits for
SR.IDLE to go high and then immediately disables the TWIM by writing a one to CR.MDIS.
Disabling the TWIM causes the TWCK and TWD pins to go high immediately, so the STOP
condition will not be transmitted correctly.
Fix/Workaround
If possible, d o no t dis ab le th e TWIM . If it is absolutely n e ces sa ry to disable th e TWIM, ther e
must be a software delay of at least two TWCK periods between the detection of
SR.IDLE==1 and the disabling of the TWIM.
TWIM TWALM polarity is wrong
The TWALM signal in the TWIM is active high instea d of active low.
Fix/Workaround
Use an external inverter to invert the signal goin g into the TWIM. When using both TWIM
and TWIS on the same pins, the TWALM cannot be used.
TWIS
TWIS Version Register reads zero
TWIS Version Register (VR) reads zero instead of 0x112.
Fix/Workaround
None.
39.3.7 MCI
The busy signal of the responses R1b is not taken in account for CMD12
STOP_TRANSFER
It is not possible to know the busy status of the card during the response (R1b) for the com-
mands CMD12.
Fix/Workaround
The card busy line should be polled through the GPIO Input Value register (IVR) for com-
mands CMD12.
1009
32072H–AVR32–10/2012
AT32UC3A3
39.3.8 SSC
Frame Synchro and Frame Synchro Data are delayed by one clock cycle
The frame synchro and the frame synchro data are delayed from 1 SSC_CLOCK when:
- Clock is CKDIV
- The START is selected on either a frame synchro edge or a level
- Frame synchro data is enabled
- Transmit clock is gated on output (through CKO field)
Fix/Workaround
Transmit or receive CL OCK must not be gated (by the mean of CKO field) when START
condition is performed on a generated frame synchro.
39.3.9 FLASHC
Corrupted read in flash may happen after fuses write or erase operations (FLASHC
LP, UP, WGPB, EGPB, SSB, PGPFB, EAGPF commands)
After a flash fuse write or erase operation (FLASHC LP, UP, WGPB, EGPB, SSB, PGPFB,
EAGPF commands), reading (data read or code fetch) in flash may fail. This may lead to an
exception or to other err ors derived from this corrupted read access.
Fix/Workaround
Before the flash fuse write or erase operation, enable the flash high speed mode (FLASHC
HSEN command). The flash fuse write or erase operations (FLASHC LP, UP, WGPB,
EGPB, SSB, PGPFB, EAGPF commands) must be issued from RAM or through the EBI.
After these commands, read 3 times one flash page initialized to 00h. Disable the flash high
speed mode (FLASHC HSDIS command). It is then possible to safely read or code fetch the
flash.
1010
32072H–AVR32–10/2012
AT32UC3A3
40. Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The
referring re visio n in th is section are referring to the document revision.
40.1 Rev. H– 10/12
40.2 Rev. G– 11/11
40.3 Rev. F – 08/11
40.4 Rev. E – 06/11
40.5 Rev. D – 04/11
40.6 Rev. C – 03/10
1. Updated max frequency
2. Added Flash Read High Speed Mode description in FLASHC chapter
3. Updated Electrical Characteristics accordingly to new max frequency
4. Fixed wrong description of PLLOPT[0] in PM chapter
5. Updated Errata section according to new maximum frequency
6. Added USB hi-speed PLL electrical characteristics
7 Added OSC32 Errata in Power Management sections for Rev D,E and H
1. Add recommandation for MCI connection with more than 1 slot
1. Final version
1. Updated Errata for E and D
2. Updated FLASHC chapter with HSEN and HSDIS commands
1. Updated Errata for revision H and E
2. Updated Reset Sequence
3. Updated Peripherals’ current consumption and others minor electrical charateristics
4. Updated P eripherals chapters
1. Updated the datasheet with new revision H features.
1011
32072H–AVR32–10/2012
AT32UC3A3
40.7 Rev. B – 08/09
40.8 Rev. A – 03/09
1. Updated the datasheet with new device AT32UC3A4.
1. Initial revision.
1012
32072HAVR3210/2012
AT32UC3A3
Table of Contents
1 Description ............................................................................................... 3
2 Overview ................................................................................................... 4
2.1 Block Dia gr am .................... ... ... ... .... ... ................ ... ... .... ... ... ................ ... .... ... ... ..4
2.2 Configuration Summary .....................................................................................5
3 Package and Pinout ................................................................................. 6
3.1 Packa ge . ...... ...... ....... ...... ....... ...... .... ...... ...... ....... ...... ....... ...... ....... ... ...... ....... .....6
3.2 Peripheral Multiplexing on I/O lines ...................................................................9
3.3 Signal Descriptions ..........................................................................................14
3.4 I/O Line Co nsiderations ...... ... ................ ... ... .... ... ................ ... ... .... ... ................19
3.5 Power Considerations .....................................................................................20
4 Processor and Architecture .................................................................. 21
4.1 Features ..........................................................................................................21
4.2 AVR32 Architecture .........................................................................................21
4.3 The AVR32UC CPU ........................................................................................22
4.4 Programming Model ........................................................................................26
4.5 Exceptions and Interrupts ................................................................................30
4.6 Modu l e Con fig u ra tio n ............................ ... ... .... ... ................ ... ... .... ... ................34
5 Memories ................................................................................................ 35
5.1 Embedded Memories ......................................................................................35
5.2 Physic al Me m or y Ma p . ... .... ... ... ... ................ .... ... ... ... ................ .... ... ... .............35
5.3 Peripheral Address Map ..................................................................................36
5.4 CPU Local Bus Mapping .................................................................................38
6 Boot Sequence ....................................................................................... 40
6.1 Starting of Clocks ............................................................................................40
6.2 Fetching of Initial Instructions ..........................................................................40
7 Power Manager (PM) .............................................................................. 41
7.1 Features ..........................................................................................................41
7.2 Overvie w ...... ...... .... ...... ....... ...... ....... ...... ...... ....... ...... ....... ... ...... ....... ...... ....... ...41
7.3 Block Dia gr am .................... ... ... ... .... ... ................ ... ... .... ... ... ................ ... .... ... ...42
7.4 Product Dependencies ....................................................................................43
7.5 Funct ion al De scr ipt ion .... .... ................ ... ... ... .... ... ................ ... ... .... ... ... .............43
7.6 User Interface ..................................................................................................55
1013
32072HAVR3210/2012
AT32UC3A3
8 Real Time Counter (RTC) ...................................................................... 80
8.1 Features ..........................................................................................................80
8.2 Overvie w ...... ...... .... ...... ....... ...... ....... ...... ...... ....... ...... ....... ... ...... ....... ...... ....... ...80
8.3 Block Dia gr am .................... ... ... ... .... ... ................ ... ... .... ... ... ................ ... .... ... ...80
8.4 Product Dependencies ....................................................................................80
8.5 Funct ion al De scr ipt ion .... .... ................ ... ... ... .... ... ................ ... ... .... ... ... .............81
8.6 User Interface ..................................................................................................83
9 Watchdog Timer (WDT) ......................................................................... 92
9.1 Features ..........................................................................................................92
9.2 Overvie w ...... ...... .... ...... ....... ...... ....... ...... ...... ....... ...... ....... ... ...... ....... ...... ....... ...92
9.3 Block Dia gr am .................... ... ... ... .... ... ................ ... ... .... ... ... ................ ... .... ... ...92
9.4 Product Dependencies ....................................................................................92
9.5 Funct ion al De scr ipt ion .... .... ................ ... ... ... .... ... ................ ... ... .... ... ... .............93
9.6 User Interface ..................................................................................................93
10 Interrupt Controller (INTC) .................................................................... 96
10.1 Features ..........................................................................................................96
10.2 Ove rview ... ... ...... ....... ...... ....... ...... ....... ... ...... ....... ...... ....... ...... ....... ...... ... ....... ...96
10.3 Block Dia gr am ... .... ... ... ... ................. ... ... ... ... .... ................ ... ... ... .... ... ................96
10.4 Product Dependencies ....................................................................................97
10.5 Funct i on al De scr ipt ion .... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... .... ......97
10.6 User Interface ................................................................................................100
10.7 Inte rr up t Re qu est Signal Map .......... ... ... ................ ... .... ... ... ................ ... .... ... .104
11 External Interrupt Controller (EIC) ..................................................... 107
11.1 Features ........................................................................................................107
11.2 Ove rview ... ... ...... ....... ...... ....... ...... ....... ... ...... ....... ...... ....... ...... ....... ...... ... ....... .107
11.3 Block Dia gr am ... .... ... ... ... ................. ... ... ... ... .... ................ ... ... ... .... ... ..............108
11.4 I/O Lin es Descr ip tion ... ... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... .... ....1 0 8
11.5 Product Dependencies ..................................................................................108
11.6 Funct i on al De scr ipt ion .... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... .... ....1 0 9
11.7 User Interface ................................................................................................113
11.8 Mod u le Con fig u ra tio n ............ ... ... ................ .... ... ... ... ................ .... ... ... ... ........129
12 Flash Controller (FLASHC) ................................................................. 130
12.1 Features ........................................................................................................130
12.2 Ove rview ... ... ...... ....... ...... ....... ...... ....... ... ...... ....... ...... ....... ...... ....... ...... ... ....... .130
12.3 Product dependencies ...................................................................................130
1014
32072HAVR3210/2012
AT32UC3A3
12.4 Funct i on al de sc rip tio n .. ... ................. ... ... ... ... .... ................ ... ... ... .... ... ..............131
12.5 Flash commands ...... ... ... .... ................ ... ... ... ................. ... ... ... ... ................. ... .134
12.6 General-purpose fuse bits .............................................................................136
12.7 Security bit .....................................................................................................138
12.8 User interface ................................................................................................139
12.9 Fuses Settings ...............................................................................................147
12.10 Serial number in the factory page ..................................................................148
12.11 Module config u ra tio n ... ... .... ... ... ................ ... .... ... ................ ... ... .... ... ..............148
13 HSB Bus Matrix (HMATRIX) ................................................................ 149
13.1 Features ................ ...... ....... ...... ....... ...... ...... ....... ... ....... ...... ...... ....... ...... ....... .149
13.2 Ove rview ... ... ...... ....... ...... ....... ...... ....... ... ...... ....... ...... ....... ...... ....... ...... ... ....... .149
13.3 Product Dependencies ..................................................................................149
13.4 Funct i on al De scr ipt ion .... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... .... ....1 4 9
13.5 User Interface ................................................................................................153
13.6 Bus Matrix Connections .................................................................................161
14 External Bus Interface (EBI) ................................................................ 163
14.1 Features ........................................................................................................163
14.2 Ove rview ... ... ...... ....... ...... ....... ...... ....... ... ...... ....... ...... ....... ...... ....... ...... ... ....... .163
14.3 Block Dia gr am ... .... ... ... ... ................. ... ... ... ... .... ................ ... ... ... .... ... ..............164
14.4 I/O Lin es Descr ip tion ... ... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... .... ....1 6 5
14.5 Product Dependencies ..................................................................................166
14.6 Funct i on al De scr ipt ion .... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... .... ....1 6 8
14.7 Application Example ......................................................................................175
15 Static Memory Controller (SMC) ......................................................... 178
15.1 Features ................ ...... ....... ...... ....... ...... ...... ....... ... ....... ...... ...... ....... ...... ....... .178
15.2 Ove rview ... ... ...... ....... ...... ....... ...... ....... ... ...... ....... ...... ....... ...... ....... ...... ... ....... .178
15.3 Block Dia gr am ... .... ... ... ... ................. ... ... ... ... .... ................ ... ... ... .... ... ..............179
15.4 I/O Lin es Descr ip tion ... ... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... .... ....1 7 9
15.5 Product Dependencies ..................................................................................179
15.6 Funct i on al De scr ipt ion .... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... .... ....1 8 0
15.7 User Interface ................................................................................................212
16 SDRAM Controller (SDRAMC) ............................................................ 219
16.1 Features ........................................................................................................219
16.2 Ove rview ... ... ...... ....... ...... ....... ...... ....... ... ...... ....... ...... ....... ...... ....... ...... ... ....... .219
16.3 Block Dia gr am ... .... ... ... ... ................. ... ... ... ... .... ................ ... ... ... .... ... ..............220
1015
32072HAVR3210/2012
AT32UC3A3
16.4 I/O Lin es Descr ip tion ... ... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... .... ....2 2 0
16.5 Application Example ......................................................................................221
16.6 Product Dependencies ..................................................................................222
16.7 Funct i on al De scr ipt ion .... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... .... ....2 2 3
16.8 User Interface ................................................................................................232
17 Error Corrected Code Controller (ECCHRS) ...................................... 246
17.1 Features ................ ...... ....... ...... ....... ...... ...... ....... ... ....... ...... ...... ....... ...... ....... .246
17.2 Ove rview ... ... ...... ....... ...... ....... ...... ....... ... ...... ....... ...... ....... ...... ....... ...... ... ....... .246
17.3 Block Dia gr am ... .... ... ... ... ................. ... ... ... ... .... ................ ... ... ... .... ... ..............247
17.4 Product Dependencies ..................................................................................247
17.5 Funct i on al De scr ipt ion .... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... .... ....2 4 8
17.6 User Interface ...............................................................................................254
17.7 Mod u le Con fig u ra tio n ............ ... ... ................ .... ... ... ... ................ .... ... ... ... ........280
18 Peripheral DMA Controller (PDCA) .................................................... 281
18.1 Features ........................................................................................................281
18.2 Ove rview ... ... ...... ....... ...... ....... ...... ....... ... ...... ....... ...... ....... ...... ....... ...... ... ....... .281
18.3 Block Dia gr am ... .... ... ... ... ................. ... ... ... ... .... ................ ... ... ... .... ... ..............282
18.4 Product Dependencies ..................................................................................282
18.5 Funct i on al De scr ipt ion .... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... .... ....2 8 3
18.6 Performance Monitors ...................................................................................285
18.7 User Interface ................................................................................................286
18.8 Mod u le Con fig u ra tio n ............ ... ... ................ .... ... ... ... ................ .... ... ... ... ........314
19 DMA Controller (DMACA) .................................................................... 316
19.1 Features ........................................................................................................316
19.2 Ove rview ... ... ...... ....... ...... ....... ...... ....... ... ...... ....... ...... ....... ...... ....... ...... ... ....... .316
19.3 Block Dia gr am ... .... ... ... ... ................. ... ... ... ... .... ................ ... ... ... .... ... ..............317
19.4 Product Dependencies ..................................................................................317
19.5 Funct i on al De scr ipt ion .... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... .... ....3 1 8
19.6 Arbitration for HSB Master Interface ..............................................................323
19.7 Memory Peripherals ......................................................................................323
19.8 Han dsh a kin g Int er fa ce .............. ... .... ... ... ................ ... .... ... ... ................ ... .... ... .323
19.9 DMACA Transfer Types ................................................................................325
19.10 Programming a Channel ................................................................................329
19.11 Disabling a Channel Prior to Transfer Completion ........................................346
19.12 User Interface ................................................................................................348
1016
32072HAVR3210/2012
AT32UC3A3
19.13 Module Config u ra tio n ............ ... ... .... ................ ... ... ... .... ................ ... ... ... ........380
20 General-Purpose Input/Output Controller (GPIO) ............................. 381
20.1 Features ........................................................................................................381
20.2 Ove rview ... ... ...... ....... ...... ....... ...... ....... ... ...... ....... ...... ....... ...... ....... ...... ... ....... .381
20.3 Block Dia gr am ... .... ... ... ... ................. ... ... ... ... .... ................ ... ... ... .... ... ..............381
20.4 Product Dependencies ..................................................................................381
20.5 Funct i on al De scr ipt ion .... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... .... ....3 8 2
20.6 User Interface ................................................................................................386
20.7 Programming Examples ................................................................................401
20.8 Mod u le con fig u ra tio n ... ... .... ... ................ ... ... .... ... ................ ... ... .... ... ..............403
21 Serial Peripheral Interface (SPI) ......................................................... 404
21.1 Features ........................................................................................................404
21.2 Ove rview ... ... ...... ....... ...... ....... ...... ....... ... ...... ....... ...... ....... ...... ....... ...... ... ....... .404
21.3 Block Dia gr am ... .... ... ... ... ................. ... ... ... ... .... ................ ... ... ... .... ... ..............405
21.4 Application Block Diagram .............................................................................405
21.5 I/O Lin es Descr ip tion ... ... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... .... ....4 0 6
21.6 Product Dependencies ..................................................................................406
21.7 Funct i on al De scr ipt ion .... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... .... ....4 0 6
21.8 User Interface ................................................................................................417
21.9 Mod u le Con fig u ra tio n ............ ... ... ................ .... ... ... ... ................ .... ... ... ... ........443
22 Two-wire Slave Interface (TWIS) ......................................................... 444
22.1 Features ........................................................................................................444
22.2 Ove rview ... ... ...... ....... ...... ....... ...... ....... ... ...... ....... ...... ....... ...... ....... ...... ... ....... .444
22.3 Li st of Ab br ev ia tio n s .... ... .... ................ ... ... ... ................. ... ... ... ................ .... ... .445
22.4 Block Dia gr am ... .... ... ... ... ................. ... ... ... ... .... ................ ... ... ... .... ... ..............445
22.5 Application Block Diagram .............................................................................446
22.6 I/O Lin es Descr ip tion ... ... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... .... ....4 4 6
22.7 Product Dependencies ..................................................................................446
22.8 Funct i on al De scr ipt ion .... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... .... ....4 4 7
22.9 User Interface ................................................................................................457
22.10 Module Config u ra tio n ............ ... ... .... ................ ... ... ... .... ................ ... ... ... ........473
23 Two-wire Master Interface (TWIM) ...................................................... 474
23.1 Features ........................................................................................................474
23.2 Ove rview ... ... ...... ....... ...... ....... ...... ....... ... ...... ....... ...... ....... ...... ....... ...... ... ....... .474
23.3 Li st of Ab br ev ia tio n s .... ... .... ................ ... ... ... ................. ... ... ... ................ .... ... .475
1017
32072HAVR3210/2012
AT32UC3A3
23.4 Block Dia gr am ... .... ... ... ... ................. ... ... ... ... .... ................ ... ... ... .... ... ..............475
23.5 Application Block Diagram .............................................................................476
23.6 I/O Lin es Descr ip tion ... ... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... .... ....4 7 6
23.7 Product Dependencies ..................................................................................476
23.8 Funct i on al De scr ipt ion .... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... .... ....4 7 8
23.9 User Interface ................................................................................................490
23.10 Module Config u ra tio n ............ ... ... .... ................ ... ... ... .... ................ ... ... ... ........507
24 Synchronous Serial Controller (SSC) ................................................ 508
24.1 Features ................ ...... ....... ...... ....... ...... ...... ....... ... ....... ...... ...... ....... ...... ....... .508
24.2 Ove rview ... ... ...... ....... ...... ....... ...... ....... ... ...... ....... ...... ....... ...... ....... ...... ... ....... .508
24.3 Block Dia gr am ... .... ... ... ... ................. ... ... ... ... .... ................ ... ... ... .... ... ..............509
24.4 Application Block Diagram .............................................................................509
24.5 I/O Lin es Descr ip tion ... ... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... .... ....5 1 0
24.6 Product Dependencies ..................................................................................510
24.7 Funct i on al De scr ipt ion .... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... .... ....5 1 0
24.8 SSC Application Examples ............................................................................522
24.9 User Interface ................................................................................................524
25 Universal Synchronous Asynchronous Receiver Transmitter (USART)
546
25.1 Features ........................................................................................................546
25.2 Ove rview ... ... ...... ....... ...... ....... ...... ....... ... ...... ....... ...... ....... ...... ....... ...... ... ....... .546
25.3 Block Dia gr am ... .... ... ... ... ................. ... ... ... ... .... ................ ... ... ... .... ... ..............547
25.4 I/O Lines Description ....................................................................................548
25.5 Product Dependencies ..................................................................................548
25.6 Funct i on al De scr ipt ion .... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... .... ....5 5 0
25.7 User Interface ................................................................................................593
26 ............................................................................................................... 621
26.1 Mod u le Con fig u ra tio n ............ ... ... ................ .... ... ... ... ................ .... ... ... ... ........622
27 Hi-Speed USB Interface (USBB) ......................................................... 624
27.1 Features ........................................................................................................624
27.2 Ove rview ... ... ...... ....... ...... ....... ...... ....... ... ...... ....... ...... ....... ...... ....... ...... ... ....... .624
27.3 Block Dia gr am ... .... ... ... ... ................. ... ... ... ... .... ................ ... ... ... .... ... ..............625
27.4 Application Block Diagram .............................................................................626
27.5 I/O Lin es Descr ip tion ... ... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... .... ....6 2 8
27.6 Product Dependencies ..................................................................................629
1018
32072HAVR3210/2012
AT32UC3A3
27.7 Funct i on al De scr ipt ion .... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... .... ....6 3 0
27.8 User Interface ................................................................................................665
27.9 Mod u le Con fig u ra tio n ............ ... ... ................ .... ... ... ... ................ .... ... ... ... ........748
28 Timer/Counter (TC) .............................................................................. 749
28.1 Features ........................................................................................................749
28.2 Ove rview ... ... ...... ....... ...... ....... ...... ....... ... ...... ....... ...... ....... ...... ....... ...... ... ....... .749
28.3 Block Dia gr am ... .... ... ... ... ................. ... ... ... ... .... ................ ... ... ... .... ... ..............750
28.4 I/O Lin es Descr ip tion ... ... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... .... ....7 5 0
28.5 Product Dependencies ..................................................................................750
28.6 Funct i on al De scr ipt ion .... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... .... ....7 5 1
28.7 User Interface ................................................................................................766
28.8 Mod u le Con fig u ra tio n ............ ... ... ................ .... ... ... ... ................ .... ... ... ... ........789
29 Analog-to-Digital Converter (ADC) ..................................................... 790
29.1 Features ........................................................................................................790
29.2 Ove rview ... ... ...... ....... ...... ....... ...... ....... ... ...... ....... ...... ....... ...... ....... ...... ... ....... .790
29.3 Block Dia gr am ... .... ... ... ... ................. ... ... ... ... .... ................ ... ... ... .... ... ..............791
29.4 I/O Lin es Descr ip tion ... ... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... .... ....7 9 1
29.5 Product Dependencies ..................................................................................791
29.6 Funct i on al De scr ipt ion .... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... .... ....7 9 2
29.7 User Interface ................................................................................................797
29.8 Mod u le Con fig u ra tio n ............ ... ... ................ .... ... ... ... ................ .... ... ... ... ........810
30 HSB Bus Performance Monitor (BUSMON) ....................................... 811
30.1 Features ........................................................................................................811
30.2 Ove rview ... ... ...... ....... ...... ....... ...... ....... ... ...... ....... ...... ....... ...... ....... ...... ... ....... .811
30.3 Block Dia gr am ... .... ... ... ... ................. ... ... ... ... .... ................ ... ... ... .... ... ..............811
30.4 Product Dependencies ..................................................................................812
30.5 Funct i on al De scr ipt ion .... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... .... ....8 1 2
30.6 User interface ................................................................................................813
30.7 Mod u le Con fig u ra tio n ............ ... ... ................ .... ... ... ... ................ .... ... ... ... ........820
31 MultiMedia Card Interface (MCI) ......................................................... 821
31.1 Features ........................................................................................................821
31.2 Ove rview ... ... ...... ....... ...... ....... ...... ....... ... ...... ....... ...... ....... ...... ....... ...... ... ....... .821
31.3 Block Dia gr am ... .... ... ... ... ................. ... ... ... ... .... ................ ... ... ... .... ... ..............822
31.4 I/O Lin es Descr ip tion ... ... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... .... ....8 2 3
31.5 Product Dependencies ..................................................................................823
1019
32072HAVR3210/2012
AT32UC3A3
31.6 Funct i on al De scr ipt ion .... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... .... ....8 2 3
31.7 User Interface ................................................................................................841
31.8 Mod u le Con fig u ra tio n ............ ... ... ................ .... ... ... ... ................ .... ... ... ... ........869
32 Memory Stick Interface (MSI) .............................................................. 870
32.1 Features ........................................................................................................870
32.2 Ove rview ... ... ...... ....... ...... ....... ...... ....... ... ...... ....... ...... ....... ...... ....... ...... ... ....... .870
32.3 Block Dia gr am ... .... ... ... ... ................. ... ... ... ... .... ................ ... ... ... .... ... ..............871
32.4 Product Dependencies ..................................................................................871
32.5 Connection to a Memory Stick .......................................................................872
32.6 Funct i on al De scr ipt ion .... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... .... ....8 7 3
32.7 User Interface ................................................................................................876
33 Advanced Encryption Standard (AES) ............................................... 890
33.1 Features ........................................................................................................890
33.2 Ove rview ... ... ...... ....... ...... ....... ...... ....... ... ...... ....... ...... ....... ...... ....... ...... ... ....... .890
33.3 Product Dependencies ..................................................................................890
33.4 Funct i on al De scr ipt ion .... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... .... ....8 9 1
33.5 User Interface ................................................................................................897
33.6 Mod u le Con fig u ra tio n ............ ... ... ................ .... ... ... ... ................ .... ... ... ... ........912
34 Audio Bitstream DAC (ABDAC) .......................................................... 913
34.1 Features ........................................................................................................913
34.2 Ove rview ... ... ...... ....... ...... ....... ...... ....... ... ...... ....... ...... ....... ...... ....... ...... ... ....... .913
34.3 Block Dia gr am ... .... ... ... ... ................. ... ... ... ... .... ................ ... ... ... .... ... ..............914
34.4 I/O Lin es Descr ip tion ... ... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... .... ....9 1 4
34.5 Product Dependencies ..................................................................................914
34.6 Funct i on al De scr ipt ion .... .... ... ... ................ ... .... ... ... ... ................ .... ... ... ... .... ....9 1 5
34.7 User Interface ................................................................................................918
35 Programming and Debugging ............................................................ 926
35.1 Ove rview ... ... ...... ....... ...... ....... ...... ....... ... ...... ....... ...... ....... ...... ....... ...... ... ....... .926
35.2 Serv ice Acce ss Bus .................. ................ ... .... ... ... ... .... ................ ... ... ... .... ... .926
35.3 On- C h ip Deb u g (O CD) ... .... ... ... ... .... ................ ... ... ... ................ .... ... ... ... ........928
35.4 JTAG and Boundary-scan (JTAG) .................................................................935
35.5 JTAG Instruction Summary ...........................................................................943
36 Electrical Characteristics .................................................................... 960
36.1 Abso lut e Ma xim u m Ra ting s* .............. ................ ... ... .... ... ... ... ................ .... ... .960
1020
32072HAVR3210/2012
AT32UC3A3
36.2 DC Characteristics .........................................................................................961
36.3 I/O pin Cha ra cte ris tics . ... .... ................ ... ... ... .... ... ................ ... ... .... ... ... ...........962
36.4 Regulator characteristics ...............................................................................963
36.5 Analog characteristics ...................................................................................964
36.6 Power Consumption ......................................................................................968
36.7 Syste m Clo ck Cha ra ct er istic s ................ ... ... .... ... ... ... ................ .... ... ... ... .... ... .971
36.8 Oscillator Characteristics ...............................................................................972
36.9 ADC Characteristics ......................................................................................974
36.10 USB Transceiver Characteristics ...................................................................975
36.11 EBI Timings ...................................................................................................977
36.12 JTAG Characteristics .....................................................................................983
36.13 SPI Characteristics ........................................................................................984
36.14 MCI ................................................................................................................ 986
36.15 Flash Memor y Cha ra ct er istic s .. ... ................ .... ... ... ... .... ................ ... ... ... .... ... .987
37 Mechanical Characteristics ................................................................. 988
37.1 Thermal Considerations ................................................................................988
37.2 Packa g e Dra win gs . ... ................ ... .... ... ... ... ................ .... ... ... ... ... ................. ... .989
37.3 Soldering Profile ............................................................................................992
38 Ordering Information ........................................................................... 993
39 Errata ..................................................................................................... 994
39.1 Rev. H ............................................................................................................994
39.2 Rev. E ............................................................................................................998
39.3 Rev. D ..........................................................................................................1004
40 Datasheet Revision History .............................................................. 1010
40.1 Rev. H– 10/12 ..............................................................................................1010
40.2 Rev. G– 11/11 .............................................................................................1010
40.3 Rev. F – 08/11 .............................................................................................1010
40.4 Rev. E – 06/11 .............................................................................................1010
40.5 Rev. D – 04/11 .............................................................................................1010
40.6 Rev. C – 03/10 .............................................................................................1010
40.7 Rev. B – 08/09 .............................................................................................1011
40.8 Rev. A – 03/09 .............................................................................................1011
32072HAVR3210/2012
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131
USA
Tel: (+1)(408) 441-0311
Fax: (+1)(408) 487-2600
www.atmel.com
Atmel Asia Limited
Unit 1-5 & 16, 19/F
BEA Tower, Millennium City 5
418 Kwun Tong Road
Kwun Tong, Kowloon
HONG KONG
Tel: (+852) 2245-6100
Fax: (+852) 2722-1369
Atmel Munich GmbH
Business Campus
Parkring 4
D-85748 Garching b. Munich
GERMANY
Tel: (+49) 89-31970-0
Fax: (+49) 89-3194621
Atmel Japan
16F, Shin Osaki Kangyo Bldg.
1-6-4 Osaka Shinagawa-ku
Tokyo 104-0032
JAPAN
Tel: (+81) 3-6417-0300
Fax: (+81) 3-6417-0370
© 2012 Atmel Corporation. All rights reserved.
Atmel, Atmel logo and combinations thereof AVR, Qtouch, and others ar e registered trademarks or trademark s of Atmel Cor poration
or its subsidiaries. Other ter ms and pr oduct names may be trademarks of others.
Disclaimer: The informati on in this d ocument is provided i n connection w ith Atmel products. No lice nse, express or im plied, by estoppel or otherwise, to
any intellectual proper ty r ight is granted by this document or in connection with the sale o f Atmel products. EXCEPT AS SET FORTH IN THE ATMEL
TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY
EXPRESS, IMPLIED OR STATUT ORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROF-
ITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL
HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or com-
pleteness of the contents of this do cumen t and reserves the right to make changes to specificat ions and pr oduct de scr iption s at any time without no tice.
Atmel does not make any commitment to update the information contained herein. U nless specifically pr ovided otherwise, Atmel products are no t suit-
able for, and shall not be used in, automotive applications. Atmel products are not intended, auth orized, or warranted for use as components in applica-
tions intended to support or sustai n life.