Never stop thinking.
HYS64D64020HBDL–5–C
HYS64D64020GBDL–5–C
HYS64D64020HBDL–6–C
HYS64D64020GBDL–6–C
200-Pin Small Outline Dual-In-Line Memory Modules
SO-DIMM
DDR SDRAM
Data Sheet, Rev. 1.1, May. 2004
Memory Products
Edition 2004-05
Published by Infineon Technologies AG,
St.-Martin-Strasse 53,
81669 München, Germany
© Infineon Technologies AG 2004.
All Rights Reserved.
Attentio n please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
Never stop thinking.
HYS64D64020HBDL–5–C
HYS64D64020GBDL–5–C
HYS64D64020HBDL–6–C
HYS64D64020GBDL–6–C
200-Pin Small Outline Dual-In-Line Memory Modules
SO-DIMM
DDR SDRAM
Data Sheet, Rev. 1.1, May. 2004
Memory Products
Template: mp_a4_v2.0_2003-06-06.fm
HYS64D64020HBDL–5–C, HYS64D64020GBDL–5–C, HYS64D64020HBDL–6–C,HYS64D64020GBDL–6–C
Revision History: Rev. 1.1 2004-05
Previous Version: Rev. 1.0 2004-05
Page Subjects (major changes since last revision)
all
6,7Updated Performance table, Order information
13 Updated Block diagram
19 Update AC Timing table
17,18 Updated Idd currents to final for DDR333 and DDR400
21 Added SPD Codes for DDR400
We Listen to Your Comments
Any information within this document that you feel is wrong, unclear or missing at all?
Your feedback will help us to continuously improve the quality of this document.
Please send your proposal (including a reference to this document) to:
techdoc.mp@infineon.com
Data Sheet 5 Rev. 1.1, 2004-05
HYS64D64020[H/G]BDL–[5/6]–C
Small Outline DDR SDRAM Modules
1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
3 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2 Current Specification and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4 SPD Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table of Contents
Data Sheet 6 Rev. 1.1, 2004-05
200-Pin Small Outline Dual-In-Line Memory Modules
SO-DIMM HYS64D64020HBDL–5–C
HYS64D64020GBDL–5–C
HYS64D64020HBDL–6–C
HYS64D64020GBDL–6–C
1 Overview
1.1 Features
• Non-parity 200-Pin Small Outline Dual-In-Line Memory Modules
•Two ranks 64M×64 organization
• JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM)
•Single +2.5V (±0.2 V) power supply and Single +2.6V (±0.1 V) power supply for DDR400
• Built with 256 Mbit DDR SDRAMs organised as ×8 in P–TFBGA–60 packages
• Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
• Auto Refresh (CBR) and Self Refresh
• All inputs and outputs SSTL_2 compatible
• S eria l Presence Detect with E2PROM
• Jedec standard form factor: 67.60 mm ×31.75 mm ×3.80 mm
• Gold plated contacts
Table 1 Performance
1.2 Description
The HYS64D64020HBDL–5–C and HYS64D64020GBDL–5–C are industry standard 200-Pin Small Outline
Dual-In-Li ne Memory Mod ules (SO-DIMMs ) organized as 64M ×64. The memory array is designed with Doubl e
Data Rate Synchronous DRAMs (DDR SDRAM). A variety of decoupling capacitors are mounted on the PC board.
The DIMMs feature serial presence detect based on a serial E2PROM device using the 2-pin I2C protocol. The first
128 bytes are programmed with configuration data and the second 128 bytes are available to the customer.
Notes
1. All part numbers end with a place code designating the silicon-die revision. Reference information available on
request. Example: HYS64D32020GDL-6-B, indicating rev. B dies are used for SDRAM components.
2. The Comp li anc e Co de i s pri nte d on the m odu le lab els de sc rib ing the s pe ed s ort ( for exam pl e “ PC2 700 ”), th e
latenci es an d S PD code defin iti on (f or ex am pl e “2033–0” means CAS latency of 2.0 clocks, RCD1) latency of
3 clock s, Row Precharge l atency of 3 cloc ks, and JEDEC SPD c ode definiton ver sion 0), and the Ra w Card
used for this module.
Part Number Speed Code –5 –6Unit
Speed Grade Component DDR400B DDR333B —
Module PC3200–3033 PC2700–2533 —
max. Clock Frequ enc y @CL3 fCK3 200 166 MHz
@CL2.5 fCK2.5 166 166 MHz
@CL2 fCK2 133 133 MHz
1) RCD: Row-Column-Delay
Data Sheet 7 Rev. 1.1, 2004-05
HYS64D64020[H/G]BDL–[5/6]–C
Small Outline DDR SDRAM Modules
Overview
Table 2 Ordering Information
Type Compliance Code Description SDRAM
Technology
PC3200 (CL=3.0)
HYS64D64020GBDL–5–C PC3200S–3033–1–Z two ranks 512 MB SO-DIMM 32 MBit (×8)
PC2700 (CL=2.5)
HYS64D64020GBDL–6–C PC2700S–2533–0–Z two ranks 512 MB SO-DIMM 32 MBit (×8)
PC3200 (CL=3.0)
HYS64D64020HBDL–5–C PC3200S–3033–1–Z two ranks 512 MB SO-DIMM 32 MBit (×8)
PC2700 (CL=2.5)
HYS64D64020HBDL–6–C PC2700S–2533–0–Z two ranks 512 MB SO-DIMM 32 MBit (×8)
HYS64D64020[H/G]BDL–[5/6]–C
Small Outline DDR SDRAM Modules
Pin Configuration
Data Sheet 8 Rev. 1.1, 2004-05
08252003-0RWI-CZGZ
2 Pin Configuration
The pin configuration of the Unbuffered Small Outline
DDR SDRAM DIMM is listed by function in Table 3
(184 pins). The abbreviations used in columns Pin and
Buffer Type are explained in Table 4 and Table 5
respectively. The pin numbering is depicted in
Figure 1.
Table 3 Pin Configuration of SO-DIMM
Pin# Name Pin
Type Buffer
Type Function
Clock Signals
35 CK0 I SSTL Clock Signal
160 CK1 I SSTL Clock Signal
89 CK2 I SSTL Clock Signal
Note:ECC type
module
NC NC – Note:non-ECC type
module
37 CK0 ISSTLComplement Clock
158 CK1 ISSTLComplement Clock
91 CK2 ISSTLComplement Clock
Note:ECC type
module
NC NC – Note:non-ECC type
module
96 CKE0 I SSTL Clock Enable Rank 0
95 CKE1 I SSTL Clock Enable Rank 1
Note:2-rank module
NC NC – Note:1-rank module
Control Signals
121 S0 ISSTLChip Select Rank 0
122 S1 ISSTLChip Select Rank 1
Note:2-ranks module
NC NC – Note:1-rank module
118 RAS ISSTLRow Address
Strobe
120 CAS ISSTLColumn Address
Strobe
119 WE ISSTLWrite Enable
Address Signals
117 BA0 I SSTL Bank Addres s Bus
1:0
116 BA1 I SSTL
112 A0 I SSTL Address Bus 11:0
111 A1 I SSTL
110 A2 I SSTL
109 A3 I SSTL
108 A4 I SSTL
107 A5 I SSTL
106 A6 I SSTL
105 A7 I SSTL
102 A8 I SSTL
101 A9 I SSTL
115 A10 I SSTL
AP I SSTL
100 A11 I SSTL
99 A12 I SSTL Address Signal 12
Note:Module based
on 256 Mbit or
larger dies
NC NC – Note:128 Mbit based
module
123 A13 I SSTL Address Signal 13
Note:1 Gbit based
module
NC NC – Note:Module based
on 512 Mbit or
smaller dies
Data Signals
5DQ0I/OSSTLData Bus 63:0
7DQ1I/OSSTL
13 DQ2 I/O SSTL
17 DQ3 I/O SSTL
6DQ4I/OSSTL
8DQ5I/OSSTL
14 DQ6 I/O SSTL
18 DQ7 I/O SSTL
19 DQ8 I/O SSTL
23 DQ9 I/O SSTL
29 DQ10 I/O SSTL
31 DQ11 I/O SSTL
20 DQ12 I/O SSTL
24 DQ13 I/O SSTL
Table 3 Pin Configuration of SO-DIMM (cont’d)
Pin# Name Pin
Type Buffer
Type Function
HYS64D64020[H/G]BDL–[5/6]–C
Small Outline DDR SDRAM Modules
Pin Configuration
Data Sheet 9 Rev. 1.1, 2004-05
08252003-0RWI-CZGZ
30 DQ14 I/O SSTL Data Bus 63:0
32 DQ15 I/O SSTL
41 DQ16 I/O SSTL
43 DQ17 I/O SSTL
49 DQ18 I/O SSTL
53 DQ19 I/O SSTL
42 DQ20 I/O SSTL
44 DQ21 I/O SSTL
50 DQ22 I/O SSTL
54 DQ23 I/O SSTL
55 DQ24 I/O SSTL
59 DQ25 I/O SSTL
65 DQ26 I/O SSTL
67 DQ27 I/O SSTL
56 DQ28 I/O SSTL
60 DQ29 I/O SSTL
66 DQ30 I/O SSTL
68 DQ31 I/O SSTL
127 DQ32 I/O SSTL
129 DQ33 I/O SSTL
135 DQ34 I/O SSTL
139 DQ35 I/O SSTL
128 DQ36 I/O SSTL
130 DQ37 I/O SSTL
136 DQ38 I/O SSTL
140 DQ39 I/O SSTL
141 DQ40 I/O SSTL
145 DQ41 I/O SSTL
151 DQ42 I/O SSTL
153 DQ43 I/O SSTL
142 DQ44 I/O SSTL
146 DQ45 I/O SSTL
152 DQ46 I/O SSTL
154 DQ47 I/O SSTL
163 DQ48 I/O SSTL
165 DQ49 I/O SSTL
171 DQ50 I/O SSTL
175 DQ51 I/O SSTL
164 DQ52 I/O SSTL
166 DQ53 I/O SSTL
Table 3 Pin Configuration of SO-DIMM (cont’d)
Pin# Name Pin
Type Buffer
Type Function
172 DQ54 I/O SSTL Data Bus 63:0
176 DQ55 I/O SSTL
177 DQ56 I/O SSTL
181 DQ57 I/O SSTL
187 DQ58 I/O SSTL
189 DQ59 I/O SSTL
178 DQ60 I/O SSTL
182 DQ61 I/O SSTL
188 DQ62 I/O SSTL
190 DQ63 I/O SSTL
71 CB0 I/O SSTL Check Bit 0
Note:ECC type
module
NC NC – Note:Non-ECC
module
73 CB1 I/O SSTL Check Bit 1
Note:ECC type
module
NC NC – Note:Non-ECC
module
79 CB2 I/O SSTL Check Bit 2
Note:ECC type
module
NC NC – Note:Non-ECC
module
83 CB3 I/O SSTL Check Bit 3
Note:ECC type
module
NC NC – Note:Non-ECC
module
72 CB4 I/O SSTL Check Bit 4
Note:ECC type
module
NC NC – Note:Non-ECC
module
74 CB5 I/O SSTL Check Bit 5
Note:ECC type
module
NC NC – Note:Non-ECC
module
Table 3 Pin Configuration of SO-DIMM (cont’d)
Pin# Name Pin
Type Buffer
Type Function
HYS64D64020[H/G]BDL–[5/6]–C
Small Outline DDR SDRAM Modules
Pin Configuration
Data Sheet 10 Rev. 1.1, 2004-05
08252003-0RWI-CZGZ
80 CB6 I/O SSTL Check Bit 6
Note:ECC type
module
NC NC – Note:Non-ECC
module
84 CB7 I/O SSTL Check Bit 7
Note:ECC type
module
NC NC – Note:Non-ECC
module
11 DQS0 I/O SSTL Data Strobe s 7:0
Note:See block
diagram for
corresponding
DQ signals
25 DQS1 I/O SSTL
47 DQS2 I/O SSTL
61 DQS3 I/O SSTL
133 DQS4 I/O SSTL
147 DQS5 I/O SSTL
169 DQS6 I/O SSTL
183 DQS7 I/O SSTL
77 DQS8 I/O SSTL Data Strobe 8
Note:ECC type
module
NC NC – Note:Non-ECC
module
12 DM0 I SSTL Data Mask 7:0
26 DM1 I SSTL
48 DM2 I SSTL
62 DM3 I SSTL
134 DM4 I SSTL
148 DM5 I SSTL
170 DM6 I SSTL
184 DM7 I SSTL
78 DM8 I SSTL Data Mask 8
Note:ECC type
module
NC NC – Note:Non-ECC
module
EEPROM
195 SCL I CMOS Serial Bus Clock
193 SDA I/O OD Serial Bus Data
194 SA0 I CMOS Slave Add res s
Select Bus 2:0
196 SA1 I CMOS
198 SA2 I CMOS
Table 3 Pin Configuration of SO-DIMM (cont’d)
Pin# Name Pin
Type Buffer
Type Function
Power Supplies
1,2 VREF AI – I/O Reference
Voltage
197 VDDSPD PWR – EEPROM Power
Supply
9,10,
21,
22,
33,
34,
36,
45,
46,
57,
58,
69,
70,
81,
82,
92,
93,
94,
113,
114,
131,
132,
143,
144,
155,
156,
157,
167,
168,
179,
180,
191,
192
VDD PWR – Power Supply
Table 3 Pin Configuration of SO-DIMM (cont’d)
Pin# Name Pin
Type Buffer
Type Function
HYS64D64020[H/G]BDL–[5/6]–C
Small Outline DDR SDRAM Modules
Pin Configuration
Data Sheet 11 Rev. 1.1, 2004-05
08252003-0RWI-CZGZ
3,4,
15,
16,
27,
28,
38,
39,
40,
51,
52,
63,
64,
75,
76,
87,
88,
90,
103,
104,
125,
126,
137,
138,
149,
150,
159,
161,
162,
173,
174,
185,
186
VSS GND – Ground Plane
Other Pins
199 VDDID OODVDD Identification
Note:Pin in tristate,
indicating VDD
and VDDQ nets
connected on
PCB
Table 3 Pin Configuration of SO-DIMM (cont’d)
Pin# Name Pin
Type Buffer
Type Function
85,
86,
97,
98,
124,
200
NC NC – Not connected
Note:Pins not
connected on
Infineon SO
DIMMs
Table 4 Abbreviations for Pin Type
Abbreviation Description
I Standard input-only pin. Digital levels.
O Output. Digital levels.
I/O I/O is a bidirectional input/output signal.
AI Input. Analog level s.
PWR Power
GND Ground
NC Not Connected
Table 5 Abbreviations for Buffer Type
Abbreviation Description
SSTL Serial Stub Termin alt ed Log ic (SSTL2)
LV-CMOS Low Voltage CMOS
CMOS CMOS Levels
OD Open Drain. The corresponding pin has 2
operational states, active low and tristate,
and allows multiple devices to share as a
wire-OR.
Table 3 Pin Configuration of SO-DIMM (cont’d)
Pin# Name Pin
Type Buffer
Type Function
HYS64D64020[H/G]BDL–[5/6]–C
Small Outline DDR SDRAM Modules
Pin Configuration
Data Sheet 12 Rev. 1.1, 2004-05
08252003-0RWI-CZGZ
Figure 1 Pin Configuration Diagram 200-Pin SO-DIMM
Table 6 Address Format
Density Organization Memory
Ranks SDRAMs # of
SDRAMs # of ro w/ba n k /
columns bits Refresh Period Interval
512MB 64M ×64 2 32M ×8 16 13/2/10 8K 64 ms 7.8 µs
MPPD0040
Pin 002
Pin 006
Pin 010
Pin 014
Pin 018
Pin 022
Pin 026
Pin 030
Pin 034
Pin 038
-
-
-
-
-
-
-
-
-
-
Pin 004
Pin 008
Pin 012
Pin 016
Pin 020
Pin 024
Pin 028
Pin 032
Pin 036
Pin 040
-
-
-
-
-
-
-
-
-
-
VREF
DQ4
VDD
DQ6
DQ7
VDD
DM1
DQ14
VDD
DQ6
DM0
DQ12
DQ13
DQ15
Pin 044
Pin 048
Pin 052
Pin 056
Pin 060
Pin 064
Pin 068
Pin 072
Pin 076
Pin 080
Pin 084
Pin 088
Pin 092
Pin 096
Pin 100
Pin 104
Pin 108
Pin 112
Pin 116
Pin 120
Pin 124
Pin 128
Pin 132
Pin 136
Pin 140
Pin 144
Pin 148
Pin 152
Pin 156
Pin 160
Pin 164
Pin 168
Pin 172
Pin 176
Pin 180
Pin 184
Pin 188
Pin 192
Pin 196
Pin 200
DQ21
DM2
DQ28
DQ29
DQ31
CB4/NC
CB6/NC
CB7/NC
CKE0
A11
A4
A0
BA1
CAS
NC
DQ36
DQ38
DQ39
DM5
DQ46
CK1
DQ52
DQ54
DQ55
DM7
DQ62
SA1
NC
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Pin 042
Pin 046
Pin 050
Pin 054
Pin 058
Pin 062
Pin 066
Pin 070
Pin 074
Pin 078
Pin 082
Pin 086
Pin 090
Pin 094
Pin 098
Pin 102
Pin 106
Pin 110
Pin 114
Pin 118
Pin 122
Pin 126
Pin 130
Pin 134
Pin 138
Pin 142
Pin 146
Pin 150
Pin 154
Pin 158
Pin 162
Pin 166
Pin 170
Pin 174
Pin 178
Pin 182
Pin 186
Pin 190
Pin 194
Pin 198
DQ20
DQ22
DQ23
VDD
DM3
DQ30
CB5/NC
DM8/NC
VDD
NC
VSS
VDD
NC
A8
A6
A2
VDD
RAS
S1/NC
DQ37
DM4
DQ44
DQ45
DQ47
CK1
DQ53
DM6
DQ60
DQ61
VSS
DQ63
SA0
SA2
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Pin 001
Pin 005
Pin 009
Pin 013
Pin 017
Pin 021
Pin 025
Pin 029
Pin 033
Pin 037
-
-
-
-
-
-
-
-
-
-
Pin 003
Pin 007
Pin 011
Pin 015
Pin 019
Pin 023
Pin 027
Pin 031
Pin 035
Pin 039
-
-
-
-
-
-
-
-
-
-
VREF
DQ0
VDD
DQ2
DQ3
VDD
DQS1
DQ10
VDD
CK0
DQ1
DQS0
DQ8
DQ09
DQ11
CK0
Pin 043
Pin 047
Pin 051
Pin 055
Pin 059
Pin 063
Pin 067
Pin 071
Pin 075
Pin 079
Pin 083
Pin 087
Pin 091
Pin 095
Pin 099
Pin 103
Pin 107
Pin 111
Pin 115
Pin 119
Pin 123
Pin 127
Pin 131
Pin 135
Pin 139
Pin 143
Pin 147
Pin 151
Pin 155
Pin 159
Pin 163
Pin 167
Pin 171
Pin 175
Pin 179
Pin 183
Pin 187
Pin 191
Pin 195
Pin 199
DQ17
DQS2
DQ33
DQ25
DQ27
CB0/NC
CB2/NC
CB3/NC
CK2/NC
CKE1/NC
A12/NC
A5
A1
A10/AP
WE
A13/NC
DQ32
DQ34
DQ35
DQS5
DQ42
DQ48
DQ50
DQ51
DQS7
DQ58
SCL
VDDID
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Pin 041
Pin 045
Pin 049
Pin 053
Pin 057
Pin 061
Pin 065
Pin 069
Pin 073
Pin 077
Pin 081
Pin 085
Pin 089
Pin 093
Pin 097
Pin 101
Pin 105
Pin 109
Pin 113
Pin 117
Pin 121
Pin 125
Pin 129
Pin 133
Pin 137
Pin 141
Pin 145
Pin 149
Pin 153
Pin 157
Pin 161
Pin 165
Pin 169
Pin 173
Pin 177
Pin 181
Pin 185
Pin 189
Pin 193
Pin 197
DQ16
VDD
DQ18
DQ19
VDD
DQS3
DQ26
VDD
CB1/NC
DQS8/NC
VDD
NC
CK2/NC
VDD
NC
A9
A7
A3
VDD
BA0
S0
DQ33
DQS4
DQ40
DQ41
DQ43
VDD
DQ49
DQS6
DQ56
DQ57
VSS
DQ59
SDA
VDDSPD
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
VDD
VDD
VDD
VSS
VDD
VDD VDD
VDD VDD
VDD VDD
VDD
VDD VDD
VDD VDD
VSS
FRONTSIDE
BACKSIDE
VSS
VSS VSS
VSS VSS
VSS
VSS VSS
VSS VSS
VSS VSS
VSS VSS
VSS VSS
VSS
VSS VSS
VSS VSS
VSS VSS
VSS
VSS VSS
VSS VSS
VDD
HYS64D64020[H/G]BDL–[5/6]–C
Small Outline DDR SDRAM Modules
Pin Configuration
Data Sheet 13 Rev. 1.1, 2004-05
08252003-0RWI-CZGZ
Figure 2 Block Diagram SO-DIMM Raw Card A (×64, 2 Ranks, ×8)
Note:
1. VDD = VDDQ, therefore VDDID strap open
2. DQ, DQS, DM resistors are 22
Ω±
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Table 7 Clock Signal Loads
Clock Input Number of SDRAMs Note
CK0, CK0 8 SDRAMs —
CK1, CK1 8 SDRAMs —
CK2, CK2 0 SDRAMs —
Data Sheet 14 Rev. 1.1, 2004-05
HYS64D64020[H/G]BDL–[5/6]–C
Small Outline DDR SDRAM Modules
Electrical Characteristics
3 Electrical Characteristics
3.1 Operating Conditions
Attention: Permanent damage to the device may occur if “Absolute Maximum Ratings” are exceeded. This
is a stress rating only, and functional operation should be restricted to recommended operation
conditions. Exposure to absolute maximum rating conditions for extended periods of time may
affect device reliability and exceeding only one of the values may cause irreversible damage to
the integrated circuit.
Table 8 Absolute Maximum Ratings
Parameter Symbol Values Unit Note/ Test
Condition
min. typ. max.
Voltage on I/O pin s relat iv e to VSS VIN, VOUT –0.5 – VDDQ +
0.5 V–
Voltage on inputs relative to VSS VIN –1 – +3.6 V –
Voltage on VDD supply relative to VSS VDD –1 – +3.6 V –
Voltage on VDDQ supply relative to VSS VDDQ –1 – +3.6 V –
Operating temperature (ambient) TA0–+70°C–
Storage temperature (plastic) TSTG -55 – +150 °C–
Power dissipation (per SDRAM component) PD–1–W–
Short circuit output current IOUT –50–mA–
Table 9 Electrical Characteristics and DC Operating Conditions
Parameter Symbol Values Unit Note/Test Condition 1)
Min. Typ. Max.
Device Supply Voltage VDD 2.3 2.5 2.7 V fCK ≤166 MHz
Device Supply Voltage VDD 2.5 2.6 2.7 V fCK >166MHz
2)
Output Supply Voltage VDDQ 2.3 2.5 2.7 V fCK ≤166 MHz
Output Supply Voltage VDDQ 2.5 2.6 2.7 V fCK >166MHz
2)
EEPROM supply voltage VDDSPD 2.3 2.5 3.6 V —
Supply Voltage, I/O Supply
Voltage VSS,
VSSQ
00V—
Input Reference Voltage VREF 0.49 ×
VDDQ
0.5 ×
VDDQ
0.51 ×
VDDQ
V3)
I/O Termination Voltage
(System) VTT VREF – 0.04 VREF + 0.04 V 4)
Input High (Logic1) Voltage VIH(DC) VREF + 0.15 VDDQ + 0.3 V 7)
Input Low (Logic0) Voltage VIL(DC) –0.3 VREF – 0.15 V 7)
Input Voltage Level,
CK and CK Inputs VIN(DC) –0.3 VDDQ + 0.3 V 7)
Input Differential Voltage,
CK and CK Inputs VID(DC) 0.36 VDDQ + 0.6 V 7)5)
VI-Matching Pull-up
Current to Pull-down
Current
VIRatio 0.71 1.4 — 6)
Data Sheet 15 Rev. 1.1, 2004-05
HYS64D64020[H/G]BDL–[5/6]–C
Small Outline DDR SDRAM Modules
Electrical Characteristics
Input Leakage Current II–2 2 µA Any input 0 V ≤VIN ≤VDD;
All other pins not under test
=0V
7)8)
Output Leakage Current IOZ –5 5 µA DQs are disabled;
0V ≤ VOUT ≤ VDDQ 7)
Output High Current,
Normal Strength Driver IOH —–16.2mAVOUT = 1.95 V 7)
Output Low
Current, Normal Strength
Driver
IOL 16.2 — mA VOUT = 0.35 V 7)
1) 0 °C ≤ TA ≤ 70 °C
2) DDR400 conditions apply for all clock frequenc ies above 166 MHz
3) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC). VREF is also expected to track noise variations in VDDQ.
4) VTT is not app lied di rectly to the dev ice. VTT is a system suppl y for sig nal termin ation res istors , is ex pected to be set equa l
to VREF, and must track variations in the DC level of VREF.
5) VID is the magnitude of the difference between the input level on CK and the input level on CK.
6) The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire
temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the
maximum difference between pull-up and pull-down drivers due to process variation.
7) Inputs are not recognized as valid until VREF stabilizes.
8) Values are shown per DDR SDRAM component
Table 9 Electrical Characteristics and DC Operating Conditions (cont’d)
Parameter Symbol Values Unit Note/Test Condition 1)
Min. Typ. Max.
Data Sheet 16 Rev. 1.1, 2004-05
HYS64D64020[H/G]BDL–[5/6]–C
Small Outline DDR SDRAM Modules
Electrical Characteristics
3.2 Current Specification and Conditions
Table 10 IDD Conditions
Parameter Symbol
Operating Current 0
one bank; active/ precharge; DQ, DM, and DQS inputs changing once per clock cycle;
address and control inputs changing once every two clock cycles.
IDD0
Operating Current 1
one bank; active/read/precharge; Burst Length = 4; see component data sheet. IDD1
Precharge Power-Down Standby Current
all banks idle; power-down mode; CKE ≤ VIL,MAX
IDD2P
Precharge Floating Standby Current
CS ≥ VIH,,MIN, all banks idle; CKE ≥ VIH,MIN;
address and other control inputs changing once per clock cycle; VIN = VREF for DQ, DQS and DM.
IDD2F
Precharge Quiet Standby Current
CS ≥ VIHMIN, all banks idle; CKE ≥VIH,MIN; VIN = VREF for DQ, DQS and DM;
address and other control inputs stable at ≥ VIH,MIN or ≤ VIL,MAX.
IDD2Q
Active Power-Down Standby Current
one bank active; power-down mode; CKE ≤ VILMAX; VIN = VREF for DQ, DQS and DM. IDD3P
Act ive Standby Current
one bank active; CS ≥ VIH,MIN; CKE ≥ VIH,MIN; tRC =tRAS,MAX;
DQ, DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle.
IDD3N
Operati ng Curre n t Read
one bank active; Burst Length = 2; reads; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B; IOUT =0mA
IDD4R
Operating Current Write
one bank active; Burst Length = 2; writes; continuous burst;
address and control inputs changing once per clock cycle;
50% of data outputs changing on every clock edge;
CL = 2 for DDR266(A), CL = 3 for DDR333 and DDR400B
IDD4W
Auto-Re fres h Curre n t
tRC = tRFCMIN, burst refresh IDD5
Self-Refresh Current
CKE ≤ 0.2 V; external clock on IDD6
Operating Current 7
four bank interleaving with Burst Length = 4; see component data sheet. IDD7
Data Sheet 17 Rev. 1.1, 2004-05
HYS64D64020[H/G]BDL–[5/6]–C
Small Outline DDR SDRAM Modules
Electrical Characteristics
Table 11 IDD Specification for HYS64D64020[G/H]BDL–5–C
Product Type HYS64D64020GBDL–5–C
HYS64D64020HBDL–5–C Unit Note 1)2)
1) Module IDD values are calculated on the basis of component IDD and can be measured differently according to DQ
loading capacity.
2) Test condition for maximum values: VDD =2.7V, TA=10°C
Organization 512MB
×64
2 Ranks
–5
Symbol Typ. Max.
IDD0 940 1150 mA 3)
3) The module IDDx values are calculated from the IDDx values of the component data sheet as follows:
m×IDDx[component] + n×IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank
modules
IDD1 1100 1310 mA 3)4)
4) DQ I/O (IDDQ) currents are not included in the calculations (see note 1)
IDD2P 480 580 mA 5)
5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component]
IDD2F 320 450 mA 5)
IDD2Q 210 290 mA 5)
IDD3P 610 720 mA 5)
IDD3N 690 860 mA 5)
IDD4R 1140 1390 mA 3)4)
IDD4W 1140 1470 mA 3)
IDD5 360 450 mA 3)
IDD6 16 17.6 mA 5)
IDD7 2020 2430 mA 3)4)
Data Sheet 18 Rev. 1.1, 2004-05
HYS64D64020[H/G]BDL–[5/6]–C
Small Outline DDR SDRAM Modules
Electrical Characteristics
Table 12 IDD Specification for HYS64D64020[G/H]BDL–6–C
Product Type HYS64D64020GBDL–6-–C
HYS64D64020HBDL–6–C Unit Note 1)2)
1) Module IDD values are calculated on the basis of component IDD and can be measured differently according to DQ
loading capacity.
2) Test condition for maximum values: VDD =2.7V, TA=10°C
Organization 512MB
×64
2 Ranks
–6
Symbol Typ. Max.
IDD0 810 960 mA 3)
3) The module IDDx values are calculated from the IDDx values of the component data sheet as follows:
m×IDDx[component] + n×IDD3N[component] with m and n number of components of rank 1 and 2; n=0 for 1 rank
modules
IDD1 930 1120 mA 3)4)
4) DQ I/O (IDDQ) currents are not included in the calculations (see note 1)
IDD2P 400 480 mA 5)
5) The module IDDx values are calculated from the corrponent IDDx data sheet values as: (m + n) × IDDx[component]
IDD2F 270 380 mA 5)
IDD2Q 180 240 mA 5)
IDD3P 510 610 mA 5)
IDD3N 580 720 mA 5)
IDD4R 970 1160 mA 3)4)
IDD4W 1010 1240 mA 3)
IDD5 300 380 mA 3)
IDD6 16 17.6 mA 5)
IDD7 1730 2080 mA 3)4)
Data Sheet 19 Rev. 1.1, 2004-05
HYS64D64020[H/G]BDL–[5/6]–C
Small Outline DDR SDRAM Modules
Electrical Characteristics
3.3 AC Chara cteristics
Table 13 AC Timing - Absolute Specifications for PC3200 and PC2700
Parameter Symbol –5 –6 Unit Note/ Test
Condition 1)
DDR400B DDR333
Min. Max. Min. Max.
DQ output access time from CK/CK tAC –0.5 +0.5 –0.7 +0.7 ns 2)3)4)5)
DQS output access time from CK/CK tDQSCK –0.6 +0.6 –0.6 +0.6 ns 2)3)4)5)
CK high-level width tCH 0.45 0.55 0.45 0.55 tCK 2)3)4)5)
CK low-level width tCL 0.45 0.55 0.45 0.55 tCK 2)3)4)5)
Clock Half Period tHP min. (tCL, tCH)min. (tCL, tCH)ns 2)3)4)5)
Clock cycle t ime tCK 5 8 6 12 ns CL = 3.0
2)3)4)5)
6 12 6 12 ns CL = 2.5
2)3)4)5)
7.5 12 7.5 12 ns CL = 2.0
2)3)4)5)
DQ and DM input hold time tDH 0.4 — 0.45 — ns 2)3)4)5)
DQ and DM input setup time tDS 0.4 — 0.45 — ns 2)3)4)5)
Control and Ad dr . input pul se width (ea ch
input) tIPW 2.2 — 2.2 — ns 2)3)4)5)6)
DQ and DM input pulse width (each input) tDIPW 1.75 — 1.75 — ns 2)3)4)5)6)
Data-out high-impedance time from CK/CK tHZ — +0.7 –0.7 +0.7 ns 2)3)4)5)7)
Data-out low-impedance time from CK/CK tLZ –0.7 +0.7 –0.7 +0.7 ns 2)3)4)5)7)
Write command to 1st DQS latching transition tDQSS 0.72 1.25 0.75 1.25 tCK 2)3)4)5)
DQS-DQ skew (DQS and associated DQ
signals) tDQSQ — +0.40 — +0.40 ns TFBGA
2)3)4)5)
Data hold skew factor tQHS — +0.50 — +0.50 ns TFBGA
2)3)4)5)
DQ/DQS output hold time tQH tHP –tQHS ns 2)3)4)5)
DQS input low (high) pulse width (write cycle) tDQSL,H 0.35 — 0.35 — tCK 2)3)4)5)
DQS falling edge to CK setup time (write cycle) tDSS 0.2 — 0.2 — tCK 2)3)4)5)
DQS falling edge hold time from CK (write
cycle) tDSH 0.2 — 0.2 — tCK 2)3)4)5)
Mode register set command cycle time tMRD 2—2—tCK 2)3)4)5)
Write preamble setup time tWPRES 0—0—ns
2)3)4)5)8)
Write postamble tWPST 0.40 0.60 0.40 0.60 tCK 2)3)4)5)9)
Write pr eamble tWPRE 0.25 — 0.25 — tCK 2)3)4)5)
Address and control input setup time tIS 0.6 — 0.75 — ns fast slew rate
3)4)5)6)10)
0.7 — 0.8 — ns slow slew
rate3)4)5)6)10)
Address and control input hold time tIH 0.6 — 0.75 — ns fast slew rate
3)4)5)6)10)
0.7 — 0.8 — ns slow slew
rate3)4)5)6)10)
Data Sheet 20 Rev. 1.1, 2004-05
HYS64D64020[H/G]BDL–[5/6]–C
Small Outline DDR SDRAM Modules
Electrical Characteristics
Read preamble tRPRE 0.9 1.1 0.9 1.1 tCK 2)3)4)5)
Read postamble tRPST 0.40 0.60 0.40 0.60 tCK 2)3)4)5)
Active to Precharge command tRAS 40 70E+3 42 70E+3 ns 2)3)4)5)
Active to Active/Auto-refresh command period tRC 55 — 60 — ns 2)3)4)5)
Auto-refresh to Active/Auto-refresh command
period tRFC 70 — 72 — ns 2)3)4)5)
Active to Read or Write delay tRCD 15 — 18 — ns 2)3)4)5)
Precharge command period tRP 15 — 18 — ns 2)3)4)5)
Active to Autoprecharge delay tRAP tRCD or tRASmin ns 2)3)4)5)
Active bank A to Active bank B command tRRD 10 — 12 — ns 2)3)4)5)
Write recovery time tWR 15 — 15 — ns 2)3)4)5)
Auto precharge write recovery + precharge
time tDAL (tWR/tCK)+(tRP/tCK)tCK 2)3)4)5)11)
Internal write to read command delay tWTR 2—1—tCK 2)3)4)5)
Exit self-refresh to non-read command tXSNR 75 — 75 — ns 2)3)4)5)
Exit self-refresh to read command tXSRD 200 — 200 — tCK 2)3)4)5)
Average Periodic Refresh Interval tREFI — 7.8 — 7.8 µs2)3)4)5)12)
1) 0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5 V ± 0.2 V, VDD = +2. 5 V ± 0.2 V (DDR333); VDDQ = 2.6 V ± 0.1 V, VDD = +2.6 V ±0.1 V
(DDR400)
2) Input slew rate ≥ 1 V/ns for DDR400, DDR333
3) The CK/CK inpu t reference lev el (for timin g reference to C K/CK) i s the point at w hich CK and CK cross: the in put referenc e
level for signals other than CK/CK, is VREF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until VREF stabilizes.
5) The Output timing reference le vel, as measured at the timing reference point indicated in AC Characteri stics (note 3) is VTT.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7) tHZ and tLZ trans itions oc cur in the same acc ess time win dows as valid dat a transit ions. These para meters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific req ui rem ent is th at D Q S b e v al id (HIG H, LOW, or so me po int on a va lid transitio n) on or b efo re this CK edge.
A valid tran sition is defin ed as monoton ic and meeting the input slew rate specifi cations of t he device. Whe n no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
9) The maximu m limi t for this parameter is not a dev ice lim it. The d evice operate s with a greater valu e for th is parame ter, bu t
system performance (bus turnaround) degrades accordingly.
10) F as t sl ew ra te ≥ 1.0 V /ns , sl o w sl ew ra t e ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/
ns, measured between VIH(ac) and VIL(ac).
11) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock
cycle time.
12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Table 13 AC Timing - Absolute Specifications for PC3200 and PC2700
Parameter Symbol –5 –6 Unit Note/ Test
Condition 1)
DDR400B DDR333
Min. Max. Min. Max.
HYS64D64020[H/G]BDL–[5/6]–C
Small Outline DDR SDRAM Modules
SPD Contents
Data Sheet 21 Rev. 1.1, 2004-05
4 SPD Contents
Table 14 SPD Codes for HYS64D64020HBDL–5–C and HYS64D64020GBDL–5–C
Product Type HYS64D64020GBDL–5–C HYS64D64020HBDL–5–C
Organization 512 MB 512 MB
×64 ×64
2 Ranks (×8) 2 Ranks (×8)
Label Code PC3200S–3033–1
JEDEC SPD Revision Rev 1.0 Rev 1.0
Byte# Description HEX HEX
0 Programmed SPD Bytes in E2PROM 80 80
1 Total number of Bytes in E2PROM 08 08
2 Memory Type (DDR = 07h) 07 07
3 Number of Row Addresses 0D 0D
4 Number of Column Addresses 0A 0A
5 Number of DIMM Ranks 02 02
6 Data Width (LSB) 40 40
7 Data Width (MSB) 00 00
8 Interface Voltage Levels 04 04
9 tCK @ CLmax (Byte 18) [ns] 50 50
10 tAC SDRAM @ CLmax (Byte 18) [ns] 50 50
11 Error Correction Support 00 00
12 Refresh Rate 82 82
13 Primary SDRAM Width 08 08
14 Error Checking SDRAM Width 00 00
15 tCCD [cycles] 01 01
16 Burst Length Supported 0E 0E
17 Number of Banks on SDRAM Device 04 04
18 CAS Latency 1C 1C
19 CS Latency 01 01
20 Write Latency 02 02
21 DIMM Attributes 20 20
22 Component Attributes C1 C1
23 tCK @ CLmax -0.5 (Byte 18) [ns] 60 60
24 tAC SDRAM @ CLmax -0.5 [ns] 50 50
25 tCK @ CLmax -1 (Byte 18) [ns] 75 75
26 tAC SDRAM @ CLmax -1 [ns] 50 50
27 tRPmin [ns] 3C 3C
28 tRRDmin [ns] 28 28
29 tRCDmin [ns] 3C 3C
30 tRASmin [ns] 28 28
31 Module Density per Rank 40 40
32 tAS, tCS [ns] 60 60
Data Sheet 22 Rev. 1.1, 2004-05
HYS64D64020[H/G]BDL–[5/6]–C
Small Outline DDR SDRAM Modules
SPD Contents
33 tAH, tCH [ns] 60 60
34 tDS [ns] 40 40
35 tDH [ns] 40 40
36 - 40 not used 00 00
41 tRCmin [ns] 37 37
42 tRFCmin [ns] 41 41
43 tCKmax [ns] 28 28
44 tDQSQmax [ns] 28 28
45 tQHSmax [ns] 50 50
46 not used 00 00
47 DIMM PCB Height 01 01
48 - 61 not used 00 00
62 SPD Revision 10 10
63 Checksum of Byte 0-62 0F 0F
64 JEDEC ID Code of Infineon (1) C1 C1
65 - 71 JEDEC ID Code of Infineon (2 - 8) 00 00
72 Module Manufacturer Location xx xx
73 Part Number, Char 1 36 36
74 Part Number, Char 2 34 34
75 Part Number, Char 3 44 44
76 Part Number, Char 4 36 36
77 Part Number, Char 5 34 34
78 Part Number, Char 6 30 30
79 Part Number, Char 7 32 32
80 Part Number, Char 8 30 30
81 Part Number, Char 9 47 48
82 Part Number, Char 10 42 42
83 Part Number, Char 11 44 44
84 Part Number, Char 12 4C 4C
85 Part Number, Char 13 35 35
86 Part Number, Char 14 43 43
87 Part Number, Char 15 20 20
88 Part Number, Char 16 20 20
89 Part Number, Char 17 20 20
90 Part Number, Char 18 20 20
Table 14 SPD Codes for HYS64D64020HBDL–5–C and HYS64D64020GBDL–5–C (cont’d)
Product Type HYS64D64020GBDL–5–C HYS64D64020HBDL–5–C
Organization 512 MB 512 MB
×64 ×64
2 Ranks (×8) 2 Ranks (×8)
Label Code PC3200S–3033–1
JEDEC SPD Revision Rev 1.0 Rev 1.0
Byte# Description HEX HEX
HYS64D64020[H/G]BDL–[5/6]–C
Small Outline DDR SDRAM Modules
SPD Contents
Data Sheet 23 Rev. 1.1, 2004-05
91 Module Revision Code 0x 0x
92 Test Program Revision Code xx xx
93 Module Manufacturing Date Year xx xx
94 Module Manufacturing Date Week xx xx
95 - 98 Module Serial Number (1 - 4) xx xx
99 - 127 not used 00 00
Table 15 SPD Codes for HYS64D64020HBDL–6–C and HYS64D64020GBDL–6–C
Product Type HYS64D64020GBDL–6–C HYS64D64020HBDL–6–C
Organization 512MB 512MB
×64 ×64
2 Ranks (×8) 2 Ranks (×8)
Label Code PC2700S–2533–0
JEDEC SPD Revision Rev. 0.0 Rev. 0.0
Byte# Description HEX HEX
0 Programmed SPD Bytes in E2PROM 80 80
1 Total number of Bytes in E2PROM 08 08
2 Memory Type DDR = 07h 07 07
3 # of Row Addresses 0D 0D
4 # Number of Column Addresses 0A 0A
5 # of DIMM Ranks 02 02
6 Data Width (LSB) 40 40
7 Data Width (MSB) 00 00
8 Interface Voltage Levels 04 04
9 tCK @ CLmax (Byte 18) [ns] 60 60
10 tAC SDRAM @ CLmax (Byte 18) [ns] 70 70
11 DIMM Configuration Type (non- / ECC) 00 00
12 Refresh Rate 82 82
13 Primary SDRAM width 08 08
14 Error Checking SDRAM width 00 00
15 tCCD [cycles] 01 01
16 Burst Length Supported 0E 0E
17 Number of Banks on SDRAM 04 04
18 CAS Latency 0C 0C
19 CS Latency 01 01
Table 14 SPD Codes for HYS64D64020HBDL–5–C and HYS64D64020GBDL–5–C (cont’d)
Product Type HYS64D64020GBDL–5–C HYS64D64020HBDL–5–C
Organization 512 MB 512 MB
×64 ×64
2 Ranks (×8) 2 Ranks (×8)
Label Code PC3200S–3033–1
JEDEC SPD Revision Rev 1.0 Rev 1.0
Byte# Description HEX HEX
Data Sheet 24 Rev. 1.1, 2004-05
HYS64D64020[H/G]BDL–[5/6]–C
Small Outline DDR SDRAM Modules
SPD Contents
20 WE (Write) Latency 02 02
21 DIMM Attributes 20 20
22 Component Attributes C1 C1
23 tCK @ CLmax -0.5 (Byte 18) [ns] 75 75
24 tAC SDRAM @ CLmax -0.5 [ns] 70 70
25 tCK @ CLmax -1 (Byte 18) [ns] 00 00
26 tAC SDRAM @ CLmax -1 [ns] 00 00
27 tRPmin (ns) 48 48
28 tRRDmin [ns] 30 30
29 tRCDmin [ns] 48 48
30 tRASmin [ns] 2A 2A
31 Module Density per Rank 40 40
32 tAS, tCS [ns] 75 75
33 tAH, tCH [ns] 75 75
34 tDS [ns] 45 45
35 tDH [ns] 45 45
36 - 40 not used 00 00
41 tRCmin [ns] 3C 3C
42 tRFCmin [ns] 48 48
43 tCKmax [ns] 30 30
44 tDQSQmax [ns] 28 28
45 tQHSmax [ns] 50 50
46 - 61 not used 00 00
62 SPD Revision 00 00
63 Checksum of Byte 0-62 (LSB only) F8 F8
64 JEDEC ID Code for Infineon C1 C1
65 JEDEC ID Code for Infineon 00 00
66 JEDEC ID Code for Infineon 00 00
67 JEDEC ID Code for Infineon 00 00
68 JEDEC ID Code for Infineon 00 00
69 JEDEC ID Code for Infineon 00 00
70 JEDEC ID Code for Infineon 00 00
71 JEDEC ID Code for Infineon 00 00
72 Module Manufacturer Location xx xx
73 Part Number, Char 1 36 36
Table 15 SPD Codes for HYS64D64020HBDL–6–C and HYS64D64020GBDL–6–C (cont’d)
Product Type HYS64D64020GBDL–6–C HYS64D64020HBDL–6–C
Organization 512MB 512MB
×64 ×64
2 Ranks (×8) 2 Ranks (×8)
Label Code PC2700S–2533–0
JEDEC SPD Revision Rev. 0.0 Rev. 0.0
Byte# Description HEX HEX
HYS64D64020[H/G]BDL–[5/6]–C
Small Outline DDR SDRAM Modules
SPD Contents
Data Sheet 25 Rev. 1.1, 2004-05
74 Part Number, Char 2 34 34
75 Part Number, Char 3 44 44
76 Part Number, Char 4 36 36
77 Part Number, Char 5 34 34
78 Part Number, Char 6 30 30
79 Part Number, Char 7 32 32
80 Part Number, Char 8 30 30
81 Part Number, Char 9 47 48
82 Part Number, Char 10 42 42
83 Part Number, Char 11 44 44
84 Part Number, Char 12 4C 4C
85 Part Number, Char 13 36 36
86 Part Number, Char 14 43 43
87 Part Number, Char 15 20 20
88 Part Number, Char 16 20 20
89 Part Number, Char 17 20 20
90 Part Number, Char 18 20 20
91 Module Revision Code xx xx
92 Test Program Revision Code xx xx
93 Module Manufacturing Date Year xx xx
94 Module Manufacturing Date Week xx xx
95 - 98 Module Serial Number xx xx
99 - 127 not used 00 00
Table 15 SPD Codes for HYS64D64020HBDL–6–C and HYS64D64020GBDL–6–C (cont’d)
Product Type HYS64D64020GBDL–6–C HYS64D64020HBDL–6–C
Organization 512MB 512MB
×64 ×64
2 Ranks (×8) 2 Ranks (×8)
Label Code PC2700S–2533–0
JEDEC SPD Revision Rev. 0.0 Rev. 0.0
Byte# Description HEX HEX
Data Sheet 26 Rev. 1.1, 2004-05
HYS64D64020[H/G]BDL–[5/6]–C
Small Outline DDR SDRAM Modules
Package Outlines
5 Package Outlines
Figure 3 Package Outline SO-DIMM Raw Card Z (L-DIM-200-9)
±0.1
63.6
67.6
31.75
±0.1
4
1±0.1
18.45
1.8±0.1
11.4
±0.1
(2.4)
47.4±0.1
63±0.1
1
4±0.1
±0.1
±0.1
1.5
(2.7)
2 MIN.
±0.1
20
±0.1
6
3.8 MAX.
1±0.1 0.15
Burnished, no burr allowed
±0.1
0.6 ±0.03
0.45
Detail of contacts
-0.18
0.25
2.55
(2.15) (2.45)
±0.05
1.8
(2.15)
(2.45)
100
200101
Published by Infineon Technologies AG
www.infineon.com