25E D Mm G79045? OO0025. 5 mm ON CHIP SYSTEMS TS0-09 - Sih ME Meade oe . -110 Hightand Ave. ~ : . . : oS . Los Gatos Ca. 95030, USA . . ; : . : Tel, (408) 395-3350 Voltage Controlled Envelope Generator The CEM3310 is a self-contained, precision ADSR type of nvel. ope geriarator Intarded for elec. tronic music and other sound ganration applications. Attack, dacay and seleasa times are - exponentially voltage contral- ~ Sable over.a wide range, and the. sustala level is tinearly voltage Controllable from 0 to. 100% of the peak voltage, A unique de. sign approach allows for a 10,000 times improvement in control voltage rejection over | conventional designs. In addi- tlan, much care has.been given to the accuracy, repeatability and tracking of the parameters fram unit to unit withoutex: ternal telmming. The times are to a first order determined only by the extarnal resistor and capacitor and canstant of phy- sles, KT. Wide tolerance mano- lithi rsistors are not used to sat Up the time constants or the - contral scale, Floally, all four cantrol inputs ara-isolated from the rest of the clrcultry $o that - the. control pins of tracking units may. be simply tled together, Although a low voltage process has been used. to lower the cost. and fawar the leakage currents, aninternal 6.5 volt Zener diode allows the chip tobe. powered by 15 volts supplies, as well as +15,.-5 volt supplies. Zero to-=5V Varies the Times from 2mS to 208 9 Zero to +8V Varies the Sustain Loved from 0 to 100% Featuras BW Low Cost, M1 Third Generation Design @ Large Time Controt Ranga: 50,000 min. . @ Full AOSR Response : @ True AC Envelopes Shape | - @ Exceptionally Law Controi Voltage Feedthrough: 90nV max @ Accurate. Exponential Time Conteol Scales _ @ Isolated Control Inputs W@ Good Repeatability and Tracking Between Units Without External Trim. . ~ M independent Gate and Trigger WM 15-Volt Suppties ee -Circuit Block and Connection Diagram fey ey ae] yemm 4790457 oo00as2 7 mI T-50-CO ON CHIP SYSTEMS eS5E D \ \ . . _, . Absolute Maximum Ratings current), every 100Q will cause " rs 4 1% increase in control scale Voltage Between Vcc and Veg Pins 2av error. Ag the times are increased, Voltage Between Vog and Ground Pins +18V this error will decrease in direc oroportion. . Voltage Between Veg and Ground Pins -6.0V Tha voltage applied to the : sustain level control input will Current Into Veg Pin _ | 50mA directly determine the sustain Voltage Between Control and Ground Pins +6.0V voltage of the output envelope (minus the sustain final voltage Valtage to Gate and Trigger Input Pins Veg to Vcc error), Voltages greater than the threshold voltage will cause the Storage Temperature Range ~85C to +150C envelope to ramp up to this . 9K? higher voltage when the peak Operating Temperature Range 25C to +75C threshold is reached. The rate at which this occurs will be equal Co the fastest attack rate. Since alt taur control inputs are connected only to the bases of NPN transistors, the control input pins of tracking units may be simply tied together. There- fore, m the case of the time control inputs, only one atten: uator ntwork ig required ta control the same parameter in a multiple chip system. Selection of Rx and Cx As 1s shown in the envelope equations, the AC time constant of the attack, decay and release curves is given by AxCx times the exponential multiplier, expl-VG/V7). Practical circuit limitations determine Ry and the moultiplier, from which Cx can then be calculated. The peak capacitor charging and discharg- ing currents is given by (V2/ RxlexalVea/VT), (Ves/Rx} exalVcp/VT), and (Vp/Rxlexp (VoR/VTI for the attack, decay, and release phases respectively. For the best scale accuracy and tacking at the shortest times, these currents should be kept tess than 100 WA, and in all cases they should not be allowed to exceed 300 WA, This sets the minimum valua for Rx at 24K. Larger values of Ry will allow - Hositive time control voltages to be used. However, as can also be sen from the envelope equa- tions, the sustain/final voltage error, the asymptote errar, and the cantrol voltage feedthrough are all affected by Rx. A prac- tical maximum of 240K is recommended for Rx when the internal buffer is used and 1M if an external FET buffer is used, fer with a low output impedance, Ro may be lowered by adding a resistar-from the output pin to VEE. However, every 1mA of current drawn from the output pin may increase the buffer input current as much as 5-6 nA with consequent degradation in performance. Trimming the Envelope Times Envelope Equations The RG time constants of the output envelope will typically track to within + 15% from unit to unit, even at the longest time settings. If better tracking is required, the best methad for trimming the time constants is to simply adjust Rx with a trimming potentiometer, Output Drive Capability The buffer output can sink at least 400 WA and can source up to 10mA, but with considerable degradation in performance. An output load no less than 20K to ground is recommended. The buffer has a somewhat high output impedance. As a result of this, smail-steps (SQmV) appedr in the output waveform at the phase transitions, due to the sudden change in drive the output must provide to Rx, The largast step is at the beginning of the envelope and is given by (RO/RX)Vz. It may be de- creased by increasing Rx, lower- ing Ro, or using an-externatl buf. vr Attack Curve t Voa 2 Vz (1-exnl- RxCx Decay Curve - e VeaNr yy Voo =(Vp-Veslexpl-aray e Release Curve t__ Vor/V. Vor = Ves expl- aro eT) Sustain/Refease Final Voltage Error 1V: F = Vog + lar fx = IggRx/tte VOA/VT Attack/Decay/Release Asymptote Error a = Vos + lat Rx - le2Rx e Vea.o.alVt Vea = Attack Control Voltage. Veo = Decay Contral Voltage Ver = Release Controt Voltage Veg = Sustain Control Voltage Vos = Op Amp Offset tg, = Op Amp Input Current Iga = Buffer Input Current V2 = Attack Asymptote Voltage Ve = Envelope Peak Voltage Vy =kTA t_ Vep/Vr 1+Ves may atPSE D MM 6790457 0000253 9 om T-50-04 ON CHIP SYSTEMS CEM 3310 Electrical Characteristics Application Hints Since the device can withstand no more: than 24 volts between its supply pins, an internal 6.5 voit + 10% zener diode has been Provided to allow the chip torun off virtually any negative supply valtage. If the negative supply is between -4.5 and ~6.0 volts, it Nate 1: Scale factor determined at mid-tange. Spec represents total deviation from tdeal at range extremitie. : Nate 2: Gurput is at either sustain final voltage of celease tinal voltage, Voa.0,p varies 0 to =240mv, Nate 3: Spee represents the difference between the actual final woltages {attack asymptote voltage, sustain final voltage, and releate final voltage in the case of attack, decay, and telease retpectively) and the spparent voltage to which the Gutput seems ta be approaching Hymptotically, Nate 4: Current limiting resistor required when Vee > -6.0 volts, Note Gi Spec alsa represants time constant vatiation between units for Vea,o,A 9. d directly to the negative supply pin (pin 6).. For voltages greater than -7.5 resistor must be added between pin 6 and the supply, Its value is Ree = (VEE - 7.21/.010. The circuit was designed for a The gate input is referenced to ground and therefore will accept any ground referenced TTL or as a high tevel, The trigger input is referenced to the VEE pin (pin 6) and therefore, a grourid refer- Veo = t18.0V Veg * -5.0 ta 15 0V Ay =24K Ta= 26C Supply [Min TYP MAX Units Time Control Range 50,000: 1 266,000-1 - Attack Asymrate Voltage (V2) 6.1 6.5 89 Vv Attack Peak Voltage (V,) 47 5.0 3 v Attack Peak to Asymptate Tracking = 15 4 % Control Scale Sensitivity 58.5 60 tS mV/Decade| Temperature Coetlicient of Control Scale} +3,000 +3,300 +3,600 pam ATK, OCY, RLS Scale Tracking -300 _ a +300 HV/Cecade maybe ec Exponaritial Full Scate Control Accuracy S0nA < 1g <S0uA - 03 \s x ae = Ee = a 30 uv volts, a series current limiting Oecay C.V, Feedthrough? NONE Release C.V, Feedthrough? - NONE foulated as follow: Sustain Final Voltage Ereor (VgQ-Vcgl =a +10 +23 mv calculated as follows: Release Final Voltage Error (Vg) 3 _ +10 +23 mv 3 - ses RG Curve Avymptate Error _ 8 -0 BV positive supply of +16 volts. . A 7 -240mV - -125 1250 mv vonages other than ets vos a will cause the peak thresho ligh Ratio, Voalya eo Current voltage to be either at a min- Charge Current{ATK) 18 1 13 imum of .33Vc or ata max: Discharge Current (OCY, RLS) 83 1 1.2 ; imum of .5 volts, Bulfar Input Current {tg9) - 0s 5 nA j Op Amp Input Current tig) 180 400 800 _na__| Gate and Trigger Inputs Gate Threshoid 2.0 2.3 2.6 v Gate [ngur Current 25 100 uA Trigger Pulse Required to Trigger c Envelope #11 +g +08 Vv CMQS fogic tevel up to +18 Trigger Input Impedance 24 3 4 ; Ka volts. If the gate pin is left Time Controt Input Current os = 2500 nA floating, it will be interpreted Sustain Control Input Current 180 400 a00 nA Attack Output Signal -4 ~8 1.2 v Gutput Currant Sink Capability 420 560 700 uA Gulfee Output tmpedance 100 200 350 2 enced trigger pulse should be Positive Supply Vattage Range 412.5 - a +18 Vv capacitively coupled to the Negative Supply. Voltage Aange4 48 - -18 v trigger input pin (pin S). Supply Currant 56 7.5 9.4 mA - Input Control Voltages As the scale sensitivity on the three time control inputs is 6OmV/decada, attenuation of the incoming control voltages will in most cases be required. Four decades. of control requires only a 240mV voltage excursion. The mora negative the voltages the longer the times. For best scale accuracy at the shortest times, the impedance at the time control pins shauld be kept low. At the shortest times (corres- ponding to 200 WA of peakease Dd ON CHIP SYSTEMS mm 750457 gooo254 o mt T-50-04 Input and Output Waveforms Vpesv Ves a at Onebted the eats Ww oherevee L w sem vee Vv constant of RxCxlexp(Vca/ VT) + 1) (i.e. a rapid attack with only a 2:1 control range}. To Provide the normai full range of attack control under this mode of operation, Q1 should be dis- abled by connecting a resistor from pin 16 to VEE to generate at least -SQOmvV at the base of Q2. This resistance may be culated as follows: = "16 Output 15 Ony 4 loxexzeKeRoke! a nd Dm n Ax Figure t: Connection to External Suffer s COU UDg0O QQAQRBAQRQ e~eannon Vee Figure 2: Genoration af Attach Logic Signal [oxoXkeRekeKexone! Figure 3: Addition of Sustain C.V. Input Limiter Sustain Coanttot Voltage Input Use of External Buffer For various reasons, it may be desirad to use an external buffer, _ One possible benefit might be a lower input bias current (Ig2), with consequent improvement in the associated errors. The exter- nal buffer should be connected as shown in Figure 1. For proper operation, the buffer used should be capable of sourcing at least 700 vA and should have a gosi- tive current flowing into the input pin, such.as that resulting from NPN of P channel JFET inputs, Disabling the Control Voltage Rejection Circuit The purpose of Q1 (see block diagram) is to greatly reduce the cantrol voltage feedthrough. During the attack phase, the base of Q1 is brought negative effectivaly disabling it and allow- ing Q2 to control the charging current. Quring the decay and release phases, however, the base of Q1 is at ground, causing neg- ative voltage excursions on the base of Q2 to vary the charging currnt only a maximum of 2:1 (as opposed to the normal 10,000:1 or greater). Under normal triggering conditions {applying a trigger and a gate), this has no consequence, except to reduce the attack control valtage feedthrough to a negli- gible amount. However, if only a gate is applied with no trigger, the output will ramp up to the sustain level, approaching it asymptotically with a RC time R= 1100(2VeE-1) The result wilt be ,000 times or more sustain and release final voltage shift with the attack control voltage. If external cir- cuitry is added to apply the -500 mV only when the gate is high, then only the sustain final voltage will exhibit significant shift. Use of the Attack and Threshold Voltage Output Pins The attack output pin (pin 16} and the peak threshold voltage pin (pin 3} have been provided to allow additional flexibility. Since pin 16 outputs a ~.4 to =1.2 volts anly during the attack phase, it may. be used to Provide a logic signal which indicates the attack phase (see figure 2). This signal may be ANDed with the gate to provide a lagic signal indicating the decay phase. As was mentioned above, a sustain control voltage greater than the threshold voltage will result ina jump to the sustain level, By using the threshold valtage pin as shown in figure 3, the sustain voltage can be pre- vented from rising above the envelope peak, thus eliminating this undesirable effect. (This effect.can also be eliminated by. disabling the control voltage re- jection circuit as described above). CRS CURTIS ELECTROMUSIC SPECIALTIES 110 Highland Ave. Los Gatos Ca 95030; USA Tel. (408) 395-3350 Covarad by U.S. Patent 24,004,141. Printed in U.S A.D 1979