SMDP-67206HV-15SB - Atmel Corporation

Rev. 4143I–AERO–06/04

Features

•First-in First -out Dual Port Memory

•16384 bits x 9 Organizat ion

•Fast Flag and Access Times: 15, 30 ns

•Wi de Temperat ure Range: - 55°C to + 125°C

•Fully Expandable by Word Width or Depth

•Asynchronous Read/W rite Operat ions

•Empty, Full and Half Fla gs in Sing le Devi ce M ode

•Retransmit Capability

•Bi-directional Applicat ions

•Battery Back-up Operation: 2V Data Retention

•TTL Compatible

•Single 5V ± 10% Power Supply

•No Single Event Latch-up below a LET Threshold of 80 MeV/mg/cm2

•Tested up to a Total Dose of 30 kr ads (Si ) according to MIL STD 883 Method 1019

•QML Q and V with SMD 5962-93177

•ESCC B with specificat ion 9301/048

Description

The M67206H implements a first-in first-out algorithm, featuring asynchronous

read/wri te operations . The FULL and EMPTY flag s prevent dat a overflow and un der-

flow. The Expans ion logic a llows unl imited expansion i n word size an d de pth with no

timing penaltie s. Twin address pointers auto matically generate internal read and write

addresses, and no external address information is required. A ddress pointers are

automatically incremented with the write pin and read pin. The 9 bits wide data are

used in data com m unications applications where a parity b it for error checking is nec -

essary. The R etransmit pin resets the Read pointer to zero without affecting the write

pointer. This is very useful for retransmitting data when an error is detected in the

system.

Using a n array of e ight transistors (8T) memory ce ll, the M6720 6H combines a n

extrem ely l ow standby suppl y curre nt (typ = 0. 1 µA) w ith a fast access time at 15 ns

over the full t emperatu re range. All vers ions offer battery ba ckup data rete ntion capa-

bility with a typical power consump tion at less than 2 µW.

The M6 7206H i s processe d acc ording to the methods of t he la test revision o f the M I L

PRF 38535 (Q and V) or ESA SCC 9000.

Rad. Tolerant

High Speed

16 Kb x 9

Parallel FIFO

M67206H

M67206H 4143I–AERO–06/04

Block Diagram

Pin Configuration

DIL ceramic 28-pin 300 mils

FP 28-pin 400 mils

M67206H

4143I–AERO–06/04

Pin D escription

Data In (I0 - I8)Da ta inputs for 9-bit data

Reset (RS) Reset o ccurs whenev er the Reset (RS) input is taken t o a low s tate. Reset returns both

internal re ad and wri te pointers to the first location. A reset is req uired after powe r-up

before a write operation can be enabled. B oth the Read Enable (R) and Write Enable

(W) inputs must be in the high state during the period shown in Figure 1 (i.e. tRSS before

the rising edge of RS) and should not change until tRSR af ter t he risin g edg e of RS. T he

Half-F ull Flag (HF ) w ill b e reset to h i gh After Re s et (R S)

Fi gure 1. Reset

Notes: 1. EF, FF and HF may cha nge status durin g reset, but flags wil l be val id at tRSC.

2. W and R = VIH around the ri sing edge of RS.

Names Description

I0-8 Inputs

Q0-8 Outputs

W Wr ite Enable

R Read Enable

RS Reset

EF Empty Fla g

FF Full Flag

XO /HF Ex pa nsion Ou t/H a lf-Fu ll Flag

XI Expansion IN

FL/RT First Load/Ret ransmit

VCC Power Supply

GND Ground

M67206H 4143I–AERO–06/04

Wr ite Enable (W)A write cycle is initiated on the falling edge of this input if the Full Flag (FF) is not set.

D ata s et-u p and hold time s mus t be mai ntai ned in the rise time of th e lea ding edge of

the Write Enable (W). Data is stored sequentially in the Ram array, regardless of any

current read operation.

Once half the memory is filled, and during the falling edge of the next write operation,

the Half-Full Flag (HF) w ill be set to low and remain in this s tate until the di fference

between the write and read pointers is les s than or equal to half of the total available

memory in the device. The Half-Full Flag (HF) is then reset by the rising edge of the

read operation.

To prevent data overflow, the Full Flag (FF) will go low, inhibiting further write opera-

tions. On completion of a valid read operation, the Full Flag (FF) will go high af ter TRFF,

allowing a valid write to begin. When the FIFO stack is full, the internal write pointer is

blocked f rom W, so that external changes to W will have no effect on the full FIFO stac k.

Read Enable (R)A read cycle is initiated on the falling edge of the Read Enable (R) provided that the

Empt y Flag (EF) is not set. The da ta is acces sed on a first-in/first-out ba sis , no t includ-

ing any current write operations. After Read Enable (R) goes high, the Data Outputs (Q0

- Q8 ) will r eturn t o a high i mped anc e state until th e nex t Read o per ation. W he n all th e

data in the FIFO stack has been read, the Empty Flag (EF) will go low, allowing the

“final” read cycle, but inhibiting f urth er read operat ions while the data output s remain in

a high impedance state. Once a valid write operation has been completed, the Empty

Flag (EF) will go high after tWEF and a valid read may then be initiated. When the FIFO

stack is empty, the internal read pointer is blocked from R, so that external changes to R

will have no effect on the empty FIFO stack.

First Load/Retransm it

(FL/RT) This pin is a dua l-purpose input. In the Depth Exp ansion Mode, this pin is con nected to

ground t o i ndicat e that it is the first loaded (see O perat ing Mo des ). In the Si ngle Device

Mode , this pin acts as the retransmi t input . Th e Single Device Mod e is initiated by con-

necting the Expansion In (XI) to ground.

The M672 06H c an be s et to retra nsmi t data w hen t he Ret ransm it Ena ble Cont rol (RT)

input is pulsed low. A retransmit operation will set the internal read point to the first loca-

tion and will not affect the write pointer. Read Enable (R) and Write Enable (W) must be

in the high state during retransmit. The retransmit feature is intended for use when a

numbe r of writes are e qual to or l ess than the depth of the F IFO h as occu rred since t he

last RS cycle. The retransmit feature is not compatible with the Depth Expansion Mode

and will affect the Half-Full Flag (HF), in accordance with the relativ e locations of the

read and write pointers.

Expansion In (XI)The XI i nput is a dual-purpose pin. Expansion In (XI) is connected to GND to indicate an

ope rati on in th e si ngle device mod e. E xpans ion In (XI) is connected to Expansion Out

(XO) of the previous device in the Depth Expansion or Dais y Chain modes.

Full Flag (FF)The Full Flag (FF) wi ll go low, inhibiting further write operations when the write pointer is

one location less than the read po inter, indicating that the device is full. If the read

pointer is not moved after Reset (RS), the Full Flag (FF) will go low after 16384 writes.

Emp ty Flag (EF)The Em pty Flag (EF) will go low, inhibiting further read operations when the read pointer

is equal to the write pointer, indicating tha t the device is empty.

M67206H

4143I–AERO–06/04

Expansion Out/Half-Full

Flag (XO/HF) The XO/HF pin is a dua l-purpose output. In the single device m ode, when Expa nsion In

(XI) is c onnected to ground, this output acts as an indication of a half-full memor y.

After half the memory is filled and on the falling edge of the next write operation, the

Half-F ull Flag (HF) will be s et t o low a nd will remain set until the d ifference b etwe en the

write and read pointers is less than or equal to half of the total memory of the device.

The Half-Full Flag (HF) is then reset by the rising edge of the read operation.

In the Depth Expansion Mod e, Expansion In (XI) is connected to Expansion Out (XO) of

the previous device. This output acts as a signal to t he next device in the Daisy Chain by

providing a pulse to the next device when the previo us device reaches the last memory

location.

Data Output (Q0 - Q8)D ATA outp ut fo r 9-bit w ide d ata. This data i s in a high impe danc e con dit ion w henev er

Read (R) is in a high state.

M67206H 4143I–AERO–06/04

Functional Description

Single Device Mode A single M67206H may be used when the application r equirements are for 16384 words

or less. The M67206H is i n a Single Device Configura tion when the Expansion In (XI) control

input is grounded (see Fig ure 2). In this mode the Half-Full Flag (HF), which is an active low

outpu t, is shar ed w ith E xpans io n Out ( XO).

Fi gure 2. Block Diagram of Single 16384 bits × 9

Width Expansion Mode W ord width m ay be increas ed simply by connec ting the c orrespondin g input c ont rol sig-

nals of multiple devices. Status flags (EF, F F and HF) can be det ect ed from any device.

Figu re 3 demonst rat es an 18-bi t word width by using tw o M67 206H. A ny w ord width can be

att ain ed by add ing addi tiona l M6 7206H.

Figu re 3. Block Diagram of 16384 bi t s x 18 FIFO Memory Used in Width Expansion Mode

Note: Flag detection is accomplished by monitoring the FF, EF and the HF signals on ei ther (any) device used in the width expansion

configuration. Do not connect any output cont rol signals together.

(HALF-FULL FLAG)

WRITE (W)(R)READ

DATAIN

(I) DATAOUT

(Q)

FULL FLAG

RESET

(FF)

(RS)

EMPT Y FLAG

RETRANSMIT

(EF)

(RT)

EXPANSION IN (XI)

M67206H

4143I–AERO–06/04

Note: 1. Pointer will increment if flag is high.

Note: 1. XI is connected to XO o f pre vious de v i c e.

See Figur e 4.

Depth Expansion (Daisy

Chain) Mode The M67206H can be easily adapted for applications which require more than 16384

word s. Fig ure 4 d emonstrates Depth Expansi on using three M67 206Hs. Any depth can

be achieved by adding an additional M67206H.

The M 67206H operate s in the Depth Ex pansion c onfiguration if th e following c on ditions

are met:

1. The first device must be desi gnated by connecting the First Load (FL) control

i nput t o gro und.

2. All othe r devices must have FL in the h igh st ate.

3. The Expansion Out (XO) pin of eac h d evice must be con nect ed to the Exp an sio n In

(XI) pi n of t he next devi ce . See Figure 4

4. External logic is needed to generate a composite Full Flag (FF ) and Em pty Flag

(EF). Thi s requires that al l EF’s and al l FFs be ORed (i.e. al l must be set to gener ate th e

correct composite FF or EF). S ee Fi gure 4.

5. The Retransmit (RT) func ti on and H alf -F ull Fla g (HF) are not avai l able in the D epth

Ex pans ion Mode.

Co mp ou nd Expansio n

Module It i s quite simple to apply the two expansion techniques descr ibed above together to cre-

ate large FIFO arrays (see Figure 5).

Tab le 1. Reset and Ret ransmit

Single Device Configuration/ Width Expansion Mode

Mode

Inputs Intern al Status Outputs

RS RT XI Re a d Po in te r Writ e Poin ter EF FF HF

Reset 0X0Locati on Zero Location Zero 011

Retransmit 100

Locati on Zero Unchanged XXX

Read/Write 110

Increment(1) Increment(1) XXX

Tab le 2. Reset and First Load Truth Table

Depth Expan sion/C omp ound Exp ansion Mo de

Mode

Inputs Internal Status Outputs

RS FL XI Read Pointer Write Pointer EF FF

Reset First Devi c e 00(1)

Location Zero Locat ion Zero 01

Reset All Other

Devices 01(1)Location Zero Locat ion Zero 01

Read/Write 1X(1)

XX XX

M67206H 4143I–AERO–06/04

Bi-directional Mode Applications which require data buffering between two systems (each system being

capa ble of Read and Write operations) can be created by couplin g M6720 6H as shown

in Figure 6. Care must be taken to ensure that the appropriate flag is monitored by each

system (i.e. FF i s monit or ed on the d ev ice on wh ich W i s in use; EF is moni to red on t he dev ic e

on whi ch R is i n use ). B oth De pth E xpans ion and Wi dth E xpans ion may be us ed in thi s mode.

Data Flow – Through

Modes Two types of flow-through modes are permitted: a read flow-through and a write flow-

through mode. In the read flow-through mode (Figure 17) the FIFO stack allows a single

word to be read after one word has been written to an empty FIFO stack. The data is

enabl ed on th e bus at (tWE F + tA) ns after t he leading ed ge of W whi ch is known as t he

firs t wr it e edge a nd r emain s on the bu s unt il t he R line is raised from low to hi gh, after which the

bus wi ll go i nto a three-state m ode after tRHZ ns. T he EF line will show a pulse indic ating tem-

porar y res et and t he n will be se t. In t he in t erval in whi ch R is low, more words may be written to

the FIFO stac k (the subsequent writes af ter t he first wri te e dge will reset t he Empty F l ag); how-

ever, the same word (written on the first write edge) presented to the outp ut bus as the read

pointer wi ll not be in crem ent ed if R is lo w. On t og gling R, th e r emaining words w r it te n to th e

FIF O will appe ar o n the o ut put bu s in acco rdanc e wit h th e re ad cy cle ti mi ngs.

In the write flow-through mode (Fi gure 18), the FIFO stac k a llows a single word of data

to be written immediately after a single word of data has been read from a full FIFO

stack. The R lin e caus es t he FF to be reset, but the W li ne, be ing low , cause s i t t o be se t aga in

in anti cipation of a new data word. The new word is lo aded i nt o the FIFO stack on t he l eading

edge of W . The W line m ust be toggled when FF is not set in order to write new data into the

FIF O stack and to i nc remen t th e wri te po int er.

Fi gure 4. Block Diagram of 49152 bits × 9 FIFO Memory (Depth Expansion)

67206H

M67206H

4143I–AERO–06/04

Figu re 5. Comp ound FIFO Expansio n

Notes: 1. For depth expansion block see secti on on De pth Expansion and Figure 4.

2. For Flag det ection see section on Width Expansion and Figur e 3.

Figu re 6. Bi-directional FIFO Mode

I0- I8

I0- I8I9- I17

I917

- I

R W RS

Q - Q

917

Q - Q

917

I(N-8) -I

I(N-8) -

Q(N-8)-Q

M67206H M67206H

67206H

M67206H 4143I–AERO–06/04

Electrical Characteristics

Ab solu te Maximum Rating s

DC Parameters

Su pp l y voltag e (V C C - G N D ):.. .... ... .......... .. ........- 0.5 V to 7.0V

Input or Output voltage applied: (GND - 0.3V) to (Vc c + 0.3V)

Storage temperature:...... .. ........ ..... .. .......... - 65 °C to + 150 °C

*NOTICE: Str esses be yond those listed unde r "Abs olute Maxi-

mum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional oper-

ation of the d evice at these or any other co nditions

beyond th ose indicated in the operational sections of

this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may

affect device reliability.

DC Test Conditions

TA = -5 5°C to + 125°C; Vss = 0V ; Vcc = 4.5V t o 5.5V

Parameter Description M67206H-30 M67206H-15 Unit Value

ICCOP (1) Operating

supply current 110 120 mA Max

ICCSB (2) Standby

supply current 5 5 mA Max

ICCPD (3) Power dow n

current 400 400 µA Max

1. Icc measurements are made wit h outputs open.

2. R = W = RS = FL/RT = VIH.

3. All input = Vcc.

Parameter Description M67206H Unit Value

ILI (1) Input leakage current ± 1 µAMax

ILO (2) Output leakage current ± 1 µAMax

VIL (3) Input low voltage 0.8 V Max

VIH(3) Input hi gh voltage 2.2 V Min

VOL (4) Output low voltage 0.4 V Max

VOH(4) Output high voltage 2.4 V Min

C IN (5 ) Input capacitance 8pFMax

C OUT(5) Output capacitance 8pFMax

1. 0.4 ≤ Vin ≤ Vcc.

2. R = VIH, 0.4 ≤ VOUT ≤ VCC.

3. VIH max = Vcc + 0.3 V. VI L min = -0.3V or -1V pulse width 50 ns. For XI input , VI H = 2.8V

4. Vcc min, IOL = 8 mA, IOH = -2 mA.

5. G uaranteed but not tested.

M67206H

4143I–AERO–06/04

AC Test Conditions

Fi gure 7. Output Load

Input pulse levels: Gnd to 3.0V Output reference levels: 1.5V

Input rise/Fall times: 5 ns Output load: See Figure 7

Input timing reference levels: 1.5V

Tab le 3. AC Test Condit ions

Symbol (1) Symbol (2) Parameter (3) (4)

M67206H- 15 M67206H- 30 Unit

Min Max Min Max

Read Cyc le

TRLRL tRC Read cycle time 25–40–ns

TRLQV tA Access time –15–30ns

TRHRL tRR Read recovery time 10–10–ns

TRLRH tRPW Read pulse width (5) 15–30–ns

TRLQX tRLZ Read low to data low Z (6) 0–0–ns

TWHQX tWLZ Write low to dat a low Z (6) (7) 3–5–ns

TRHQX tDV Data valid from read high 5–5–ns

TRHQZ tRHZ Read high to data high Z(6) –15–20ns

Wr i te C ycle

TWLWL tWC Wri te cycle t ime 25–40–ns

TWLWH tWPW Write pul se width(5) 15–30–ns

TWHWL tWR Write recove ry time 10–10–ns

TDVWH tDS Data set-up time 9–18–ns

TWHDX tDH Data hold time 0–0–ns

Reset Cycle

TRSLWL tRSC Reset cycle time 25–40–ns

TRSLRSH tRS Reset pul se width (5) 15–30–ns

M67206H 4143I–AERO–06/04

TWHRSH tRSS Reset set-up time 20–30–ns

TRSHWL tRSR Reset recovery time 10–10–ns

Ret ransmit Cycle

TRTLWL tRTC Retransmit cycle time 25–40–ns

TRTLRTH tRT Retransmit pulse wid th(5) 15–30–ns

TWHRTH tRTS Retransmit set-up time(6) 15–30–ns

TRTHWL tRTR Retra nsm it reco very time 10–10–ns

Flags

TRSLEFL tEFL Reset to EF low –25–30ns

TRSLFFH tHFH, tFFH Reset to HF/FF hig h –25–30ns

TRLEFL tREF Read low to EF low –25–30ns

TRHFFH tRFF Read high to FF high –25–30ns

TEFHRH tRPE Read width after EF high 15–30–ns

TWHEFH tWEF Write hi gh to EF high –15–30ns

TWLFFL tWFF Write low to FF low –20–30ns

TWLHFL tWHF Write low to HF low –30–30ns

TRHHFH tRHF Read high to HF high –30–30ns

TFFHWH tWPF Wr ite wi dth after FF high 15–30–ns

Expansion

TWLXOL tXOL Rea d/W rite to XO low –15–30ns

TWHXOH tXOH Read/Wri te t o XO high –15–30ns

TXILXIH tXI XI pulse widt h 15–30–ns

TXIHXIL tXIR XI recovery time 10–10–ns

TXILRL tXIS XI set-up time 10–10–ns

1. STD symbol.

2. ALT symbo l.

3. Timings referenced as in AC test conditions.

4. All paramete rs t ested only.

5. Pulse widths less than minimum value ar e not allowed.

6. Values guaranteed by design, not currently tested.

7. Only applies to read data flow- through mo de.

Tab le 3. AC Test Condit ions (Cont i nued)

Symbol (1) Symbol (2) Parameter (3) (4)

M67206H- 15 M67206H- 30 Unit

Min Max Min Max

M67206H

4143I–AERO–06/04

Fi gure 8. Asynchronous Write and Read Operation

Fi gure 9. Full Flag from Last Write to First Read

Fi gure 10 . Em pty Flag from Last Read to First Write

M67206H 4143I–AERO–06/04

Figu re 11. Retransmit

Figu re 12. Empty Flag Timi ng

Figu re 13. Full Flag Timing

M67206H

4143I–AERO–06/04

Figu re 14. Half F u ll Fl a g Timing

Figu re 15. Expans ion Out

Figu re 16. Expans ion In

M67206H 4143I–AERO–06/04

Figu re 17. Read Data Flow – Th rough Mod e

Figu re 18. Write Data Flow – Through Mode

M67206H

4143I–AERO–06/04

Ordering Information

No te : 1. C on ta c t At me l fo r a va il ab i lity.

Part Number Temperature

Range Speed Package Qua li ty Flow

MMCP-67206HV-15-E(1) 25°C 15 ns SB2 8. 3 En gi ne er i ng Sa mp le s

MMCP-67206HV-15 -55 to +125°C 15 ns SB2 8. 3 Standa r d Mi l.

MMCP-67206HV-30 -55 to +125°C 30 ns SB2 8. 3 Standa r d Mi l.

SMCP-67206HV-15SB -55 to +125°C 1 5 ns SB2 8.3 S CC B

SMCP-67206HV-30SB -55 to +125°C 3 0 ns SB2 8.3 S CC B

5962-9317708QTC -55 to +125°C 15 ns SB2 8.3 QM L Q

5962-9317707QTC -55 to +125°C 30 ns SB2 8.3 QM L Q

5962-9317708VTC -55 to +125°C 1 5 ns S B2 8.3 QML V

5962D9317708VTC -55 to +125°C 15 ns SB2 8.3 QML V RH A

5962D9317707VTC -55 to +125°C 30 ns SB2 8.3 QML V RH A

5962-9317707VTC -55 to +125°C 3 0 ns S B2 8.3 QML V

MMDP-67206HV-15-E 25°C 15 ns FP2 8 . 4 En gine eri ng Samp le s

MMDP-67206HV-15 -55 to +125°C 15 ns F P2 8.4 M il.

MMDP-67206HV-30 -55 to +125°C 30 ns F P2 8.4 M il.

SMDP-67206HV-15SB -55 to +125°C 1 5 ns F P2 8.4 SC C B

SMDP-67206HV-30SB -55 to +125°C 3 0 ns F P2 8.4 SC C B

5962-9317708QNC -55 to +125°C 15 ns F P2 8.4 QML Q

5962-9317707QNC -55 to +125°C 30 ns F P2 8.4 QML Q

5962-9317708VNC -55 to +125°C 1 5 ns FP2 8.4 QM L V

5962-9317707VNC -55 to +125°C 3 0 ns FP2 8.4 QM L V

5962D9317708VNC -55 to +125°C 15 ns FP 2 8.4 QM L V RHA

5962D9317707VNC -55 to +125°C 30 ns FP 2 8.4 QM L V RHA

5962-9317708Q9A(1) -55 to +125°C 15 ns Di e QML Q

5962-9317708V9A(1) -55 to +125°C 1 5 ns Die QM L V

MM067206HV-15-E(1) 25°C 1 5 ns Die En gi ne e ri ng Sa mp le s

M67206H 4143I–AERO–06/04

Pac kag e Dra win g s

28-lead Side Braze (300 Mils)

M67206H 4143I–AERO–06/04

28-lead Flat Pack (400 Mils)

Pr inted o n rec ycled paper.

tered trademarks of Atmel Corporation or its subsidiaries. Other terms and product names in this document

may be t he tr a de m ar k s of ot hers.

Dis claim er : A tmel Corporation makes no warranty for the use of its products, other than t hose expressly contained in the Company’s stan dard

warranty which is detailed in A tmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibilit y fo r an y

erro r s whic h m a y ap pe ar in t h is do c um en t , res erve s th e r i gh t t o c h an ge de v ic es o r s pe ci fic a t io ns d eta iled he rein at an y tim e w it hout notic e, and

does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are

gra nted by th e Co mpany in c on nect ion w ith th e sa le of Atme l p roduc ts, ex pre ssl y or by imp lica tio n. A tmel ’s p rod ucts a re n ot au thorized for use

as c rit ic al c om po ne nts i n l ife s up po rt de vi ce s or sys tem s .

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