2009-2014 Microchip Technology Inc. DS20002121C-page 1
MCP23009/MCP23S09
Features:
• 8-Bit Remote Bidirectional I/O Port:
- I/O Pins Default to Input
• Open-Drain Outputs:
-5.5V Tolerant
- 25 mA Sink C apable (per Pin)
-200mA Total
• High-Speed I2C™ Interface (MCP23009):
-100kHz
-400kHz
-3.4MHz
• High-Speed SPI Interface (MCP23S09):
-10MHz
• Single Hardware Address Pin (MCP23009):
- Voltage input to allow up to eight devices on
the bus
• Configurable Interrupt Output Pins:
- Configurable as active-high, active-low or
open-drain
• Configurable Inter rupt Source:
- Interrupt-on-Change from configured defaults
or pin change
• Polari ty inve rsion re gister to config ure the pol arity
of the input port data
• External Reset Input
• Low Standby Current:
- 1 µA (-40°C T
A +85°C)
-6µA (+85°C T
A +125°C)
• Operating Voltage:
- 1.8V to 5.5V
• Available Packages:
- 16-Lead QFN (3x 3x0 .9 mm )
- 18-Lead PDIP (300 mil)
- 18-Lead SOIC (7.50 mm)
- 20-Lead SSOP (5.30 mm)
Block Diagram
GP0
GP1
GP2
GP3
GP4
GP5
GP6
GP7
I2C™
Control
GPIO
SCL
SDA
RESET
INT
8
Configuration/
8
Control
Registers
SPI
SI
SO
SCK
CS MCP23S09
ADDR
Serializer/
Deserializer
Multi-Bit
Decode
MCP23009
8-Bit I/O Expander with Open-Drain Ou tp uts
MCP23009/MCP23S09
DS20002121C-page 2 2009-2014 Microchip Technology Inc.
Package Types
VSS
18 NC
17 NC
16 GP7
15 GP6
14 GP5
13 GP4
12
GP2
10
VDD 1
NC 2
SCL 3
SDA 4
ADDR 5
RESET 6
INT 7
GP0 8GP3
11
GP1 9
VSS
20 NC
19 NC
18 GP7
17 GP6
16 GP5
15 GP4
14 GP3
13 GP2
12 NC
11
VDD 1
NC 2
SCL 3
SDA 4
ADDR 5
RESET 6
INT 7
GP0 8
GP1 9
NC 10
VSS18 NC17 GP716 GP615 GP514 GP413 GP312
GP110
VDD 1
NC 2
CS 3
SCK 4
SI 5
SO 6
RESET 7
INT 8 GP211
GP0 9
* Includes Exposed Thermal Pad (EP); see Tables 1-1 and 1-2.
MCP23009
PDIP, SOIC MCP23009
3x3 QFN* MCP23009
SSOP
MCP23S09
PDIP/SOIC MCP23S09
3x3 QFN*
2
VDD
CS
VSS GP3
GP2
SI
GP1
SO
RESET
INT
GP0
GP7
GP6
GP5
GP4
SCK EP
16
115 14 13
3
4
12
11
10
9
5678
17
2
VDD
SCL
VSS GP3
GP2
SDA
GP1
ADDR
RESET
INT
GP0
GP7
GP6
GP5
GP4
NC EP
16
115 14 13
3
4
12
11
10
9
5678
17
2009-2014 Microchip Technology Inc. DS20002121C-page 3
MCP23009/MCP23S09
1.0 DEVICE OVERVIEW
The MCP23 X09 device pro vides 8-bit, gen eral purpose
parall el I/O e xpansion fo r I2C bus or SPI applications.
The two devices differ only in the serial interface.
• MCP23 009 – I2C interface
• MCP23S09 – SPI interface
The MCP23X09 consists of multiple 8-bit configuration
registers for input, output and polarity selection. The
system master can enable the I/Os as either inputs or
outputs by writing the I/O configuration bits. The data
for each input or output is kept in the corresponding
input or output register. The polarity of the input port
register can be inverted with the polarity inversion
register. All registers can be read by the system master .
The interrupt output can be configured to activate
under two con di tion s (mu tual ly excl us iv e):
1. When any input state differs from its
corresponding input port register state. This is
used to indicate to the system master that an
input state has changed.
2. When an input state differs from a
pre-configured register value (DEFVAL
register).
The Interrupt Capture register captures port values at
the time of the Interrupt, thereby saving the condition
that caused the Interrupt.
The Power-On Reset (POR) sets the registers to their
default values and initializes the device state machine.
The hardware address pin is used to determine the
device address.
MCP23009/MCP23S09
DS20002121C-page 4 2009-2014 Microchip Technology Inc.
1.1 Pin Descriptions
TABLE 1-1: I2C™ PINOUT DESCRIPTION (MCP23009)
Pin
Name
Pin Number Pin
Type St a ndard Func tion
16-lead
QFN 18-lead
PDIP/SOIC 20-lead
SSOP
VDD 31 1PPower
NC 2 2, 16-17 2, 10-11,
18-19 — Not connected
SCL 4 3 3 I Serial clock input
SDA 5 4 4 I/O Serial data I/O
ADDR 6 5 5 I Hardware address pin allows up to eight slave devices on the
bus
RESET 7 6 6 I Hardware reset
INT 8 7 7 O Interrupt output for port. Can be configured as active-high,
active-low or open-drain.
GP0 9 8 8 I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs).
Can be enabled for interrupt on change and/or internal pull-up
resistor.
GP1 10 9 9 I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs).
Can be enabled for interrupt on change and/or internal pull-up
resistor.
GP2 11 10 12 I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs).
Can be enabled for interrupt on change and/or internal pull-up
resistor.
GP3 12 11 13 I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs).
Can be enabled for interrupt on change and/or internal pull-up
resistor.
GP4 13 12 14 I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs).
Can be enabled for interrupt on change and/or internal pull-up
resistor.
GP5 14 13 15 I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs).
Can be enabled for interrupt on change and/or internal pull-up
resistor.
GP6 15 14 16 I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs).
Can be enabled for interrupt on change and/or internal pull-up
resistor.
GP7 16 15 17 I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs).
Can be enabled for interrupt on change and/or internal pull-up
resistor.
VSS 1 18 20 P Ground
EP 17 — — — Exposed Thermal Pad (EP). Can be left floating or connected
to VSS.
2009-2014 Microchip Technology Inc. DS20002121C-page 5
MCP23009/MCP23S09
TABLE 1-2: SPI PINOUT DESCRIPTION (MCP23S09)
Pin
Name
Pin Number Pin
Type St an dard Func tion
16-lead
QFN 18-lead
PDIP/SOIC
VDD 3 1 P Powe r (hi gh-current capabl e)
NC — 2, 17 — Not conne ct ed
CS 4 3 I Chip select
SCK 2 4 I Serial clock input
SI 5 5 I Serial data input
SO 6 6 O Serial data out
RESET 7 7 I Hardware reset (must be ex ternally bias ed)
INT 8 8 O Interrupt output for port. Can be configured as active-high, active-low or
open-drain.
GP0 9 9 I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs). Can be
enabled for Interrupt-on-Change and/or internal pull-up resistor.
GP1 10 10 I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs). Can be
enabled for Interrupt-on-Change and/or internal pull-up resistor.
GP2 11 11 I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs). Can be
enabled for Interrupt-on-Change and/or internal pull-up resistor.
GP3 12 12 I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs). Can be
enabled for Interrupt-on-Change and/or internal pull-up resistor.
GP4 13 13 I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs). Can be
enabled for Interrupt-on-Change and/or internal pull-up resistor.
GP5 14 14 I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs). Can be
enabled for Interrupt-on-Change and/or internal pull-up resistor.
GP6 15 15 I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs). Can be
enabled for Interrupt-on-Change and/or internal pull-up resistor.
GP7 16 16 I/O Bidirectional I/O pin (5.5V tolerant inputs; open-drain outputs). Can be
enabled for Interrupt-on-Change and/or internal pull-up resistor.
VSS 1 18 P Ground (high-curre nt capable)
EP 17 — — Exposed Thermal Pad (EP). Can be left floating or connected to VSS.
MCP23009/MCP23S09
DS20002121C-page 6 2009-2014 Microchip Technology Inc.
1.2 Power-On Reset (POR)
The on -c hip P OR c ircui t ho lds the device in r eset unt il
VDD has reached a high enough voltage to deactivate
the POR circuit (i.e., release the device from reset).
The maximum VDD rise time is specified in the
electrical specification section.
When the device exits the POR condition (releases
reset), the device operating parameters (i.e., voltage,
tempera ture, serial bus frequen cy, etc.) must be met to
ensure proper operation.
1.3 Serial Interface
This block handles the functionality of the I2C
(MCP23009) or SPI (MCP23S09) interface protocol.
The MCP23X09 contains eleven (11) individual
registers which can be addressed through the Serial
Interface block (Table 1-3).
TABLE 1-3: REGISTER ADDRESSES
1.3.1 BYTE MODE AND SE QUENTIA L
MODE
The MCP23 X09 has the ability to operat e in Byte m ode
or Sequential mode (IOCON.SEQOP). Byte mode and
Sequential mode are not to be confused with I2C byte
operations and sequential operations. The modes
explained here relate to the device’s internal address
pointer and whether or not it is incremented after each
byte is clocked on the serial interface.
•Byte mode disables automatic address pointer
incrementing. When operating in Byte mode, the
MCP23X09 does not increment its internal
address counter after each byte during the data
transfer. This gives the ability to continually
access the same address by providing extra
clocks (without additional control bytes). This is
useful for polling the GPIO register for data
changes or for continually writing to the output
latches.
•Sequential mo de enables automatic address
pointer incrementing. When operating in
Sequential mode, the MCP23X09 increments its
address counter after each byte during the data
transfer. The address pointer automatically rolls
over to address 00h after accessing the last
register.
These two modes are not to be confused with single
writes/reads and continuous writes/reads, which are
serial protocol sequences. For example, the device
may be configured for Byte mode and the master may
perform a continuous read. In this case, the
MCP23X09 would not increment the address pointer
and would repeatedly drive data from the same
location.
1.3.2 I2C INTERFACE
1.3.2.1 I2C Write Operation
The I2C write operation includes the control byte and
the r egiste r add ress se quenc e, as shown in the bo ttom
of Figure 1-1. This seq uence is followe d by eigh t bits of
data from the master and an Acknowledge (ACK) from
the MCP 23009. T he opera tion is ended with a S to p (P)
or Restart (SR) condition being generated by the
master.
Data is written to the MCP23009 after every byte
transfer. If a Stop or Restart condition is generated
during a dat a tra nsfer, the dat a w ill no t be writ ten to the
MCP23009.
Both Byte mode and Sequential mode are supported
by the MCP23009. If Sequential mode is enabled
(default), the MCP23009 increments its address
counter after each ACK during the data transfer.
1.3.2.2 I2C Read Operation
I2C read o perations in clu de the control by te se que nc e,
as sho wn in th e b ottom of Figure 1-1. Thi s sequence is
followed by another control byte (including the Start
condition and ACK) with the R/W bit equal to a logic
one (R/W = 1). The MCP230 09 then trans mits th e data
contained in the addressed register. The sequence is
ended with the master generating a Stop or Restart
condition.
1.3.2.3 I2C Sequential Write/Read
For sequential operations (Write or Read), instead of
transmitting a Stop or Restart condition after the data
transfer, the master clocks the next byte pointed to by
the address pointer (see Section 1.3.1 “Byte Mode
and Sequen tial Mode” for detail s regarding sequential
operation control).
The sequence ends with the master sending a Stop or
Restart condition.
The MCP23009 address pointer will roll over to
address zero after reaching the last register address.
Refer to Figure 1-1.
Address Access to
00h IODIR
01h IPOL
02h GPINTEN
03h DEFVAL
04h INTCON
05h IOCON
06h GPPU
07h INTF
08h INTCAP (read-only)
09h GPIO
0Ah OLAT
2009-2014 Microchip Technology Inc. DS20002121C-page 7
MCP23009/MCP23S09
1.3.3 SPI INTERFACE
The MCP23S09 operates in Mode 0,0 and Mode 1,1.
The difference between the two modes is the idle state
of the clo c k.
• Mode 0,0: The idle state of the clock is low. Input
dat a is l atche d on the rising edge o f the cl ock; o ut-
put data is driven on the falling edge of the clock.
• Mode 1,1: The idle state of the clock is high. Input
dat a is l atche d on the rising edge o f the cl ock; o ut-
put data is driven on the falling edge of the clock.
1.3.3.1 SPI Write Operation
The SPI write operation is started by lowering CS. The
write command (slave address with R/W bit cleared) is
then cloc ked into the dev ice. The opcode is follow ed by
an address and at least one data byte.
1.3.3.2 SPI Read Operation
The SPI read operation is started by lowering CS. The
SPI read command (slave address with R/W bit set) is
then cloc ked into the dev ice. The opcode is followed by
an address, with at least one data byte being clocked
out of the device.
1.3.3.3 SPI Sequential Write/Read
For sequential operations, instead of deselecting the
device by raising CS, the master clocks the next byte
pointed to by the address pointer (see Section 1.3.1
“Byte Mode and Sequential Mode” for details
regarding sequential operation control).
The sequence ends by the raising of CS.
The MCP23S09 address pointer will roll over to
address zero after reaching the last register address.
MCP23009/MCP23S09
DS20002121C-page 8 2009-2014 Microchip Technology Inc.
FIGURE 1-1: MCP23009 I2C™ DEVICE PROTOCOL
S P
SR
W
R
OP ADDR DIN DIN
....
S
P
W
R
OP
ADDR
DOUT DOUT
.... P
SR WOP ADDR DIN
.... P
P
SR R
DOUT DOUT
....
P
OP DOUT DOUT
.... P
SR OP DIN
....
P
OP
DIN
S PWOP ADDR DIN DIN
....
Byte and Sequential Write
S
W
OP SR R
OP
DOUT DOUT
.... P
Byte and Sequential Read
S WOP ADDR DIN P
S
WOP SR ROP
DOUT
P
Byte
Sequential
Byte
Sequential
ADDR
ADDR
S
P
SR
W
R
OP
ADDR
DOUT
DIN
- Start
- Restart
- Stop
- Write
- Read
- Device opcode
- Device address
- Data out from MCP23009
- Data in to MCP23009
Legend:
2009-2014 Microchip Technology Inc. DS20002121C-page 9
MCP23009/MCP23S09
1.4 Multi-Bit Address Decoder
The ADDR pin is used to set the slave a ddress of the
MCP23009 (I2C only) to allow up to eight devices on
the bus using only a single pin. Typically, this would
require three pins.
The multi -bit Address Decoder employs a basic FLASH
ADC architecture (Figure 1-4). The seven c omp arato rs
generate eight unique values based on the analog
input. This value is converted to a 3-bit code which
corresponds to the address bits (A2, A1, A0) in the
serial OPCODE.
Sequence of operation (see Figure 1-5 for
timings):
1. Upon power-up (after VDD stabilizes), the
module becomes active after time tADEN. Note
that the analog value on the ADDR pin must be
stable before this point to ensure accurate
address assignment.
2. The 3-bit address is latched after tADDRLAT.
3. The module powers down after the first rising
edge of the serial clock is detected (tADDIS).
Once t he add res s b it s a r e l atc hed , th e d ev ic e wi ll keep
the slave address until a POR or Reset condition
occurs.
1.4.1 CALCULATING VOLTAGE ON ADDR
When calculating the required voltage on the ADDR pin
(V2), the set point shoul d be the mid p oint of the LSb of
the ADC.
The examples in Figures 1-2 and 1-3 show how to
determine the mid-point voltage (V2) and the range of
voltages based on a voltage divider circuit. The
maximum tolerance is 20%, however, it is
recommended to use 5% tolerance worst-case (10%
total tolerance).
FIGURE 1-2: VOLTAGE DIVIDER EXAMPLE
R2
A0
A1
A2
V2
R1
VDD MCP23009 Only
VDD
VSS
VSS
ADDR
MCP23009/MCP23S09
DS20002121C-page 10 2009-2014 Microchip Technology Inc.
FIGURE 1-3: VOLTAGE AND CODE EXAMPLE
Assume:
n = A2, A1, A0 in opcode
ratio = R2/(R1+R2)
V2 = voltage on ADDR pin
V2(min) = V2 – (V
DD
/8) x %tolerance
V2(max) = V2 + (VDD/8) x %tolerance
VDD =1.8
n R2 = 2n + 1 R1 = 16 – R2 R2/(R1 + R2) V2 V2(min) V2(max)
01 15 0.0625 0.113 0.00 0.14
13 13 0.1875 0.338 0.32 0.36
25 11 0.3125 0.563 0.54 0.59
37 9 0.4375 0.788 0.77 0.81
49 7 0.5625 1.013 0.99 1.04
511 5 0.6875 1.238 1.22 1.26
613 3 0.8125 1.463 1.44 1.49
715 1 0.9375 1.688 1.67 1.80
VDD =2.7
n R2 = 2n + 1 R1 = 16 – R2 R2/(R1 + R2) V2 V2(min) V2(max)
0 1 15 0.0625 0.169 0.00 0.19
1 3 13 0.1875 0.506 0.48 0.53
2 5 11 0.3125 0.844 0.82 0.87
3 7 9 0.4375 1.181 1.16 1.20
4 9 7 0.5625 1.519 1.50 1.54
5 11 5 0.6875 1.856 1.83 1.88
6 13 3 0.8125 2.194 2.17 2.22
7 15 1 0.9375 2.531 2.51 2.70
VDD =3.3
n R2 = 2n + 1 R1 = 16 – R2 R2/(R1 + R2) V2 V2(min) V2(max)
0 1 15 0.0625 0.206 0.00 0.23
1 3 13 0.1875 0.619 0.60 0.64
2 5 11 0.3125 1.031 1.01 1.05
3 7 9 0.4375 1.444 1.42 1.47
4 9 7 0.5625 1.856 1.83 1.88
5 11 5 0.6875 2.269 2.25 2.29
6 13 3 0.8125 2.681 2.66 2.70
7 15 1 0.9375 3.094 3.07 3.30
VDD =5.5
n R2 = 2n + 1 R1 = 16 – R2 R2/(R1 + R2) V2 V2(min) V2(max)
0 1 15 0.0625 0.344 0.00 0.37
1 3 13 0.1875 1.031 1.01 1.05
2 5 11 0.3125 1.719 1.70 1.74
3 7 9 0.4375 2.406 2.38 2.43
4 9 7 0.5625 3.094 3.07 3.12
5 11 5 0.6875 3.781 3.76 3.80
6 13 3 0.8125 4.469 4.45 4.49
7 15 1 0.9375 5.156 5.13 5.50
10% Tolerance (total)
10% Tolerance (total)
10% Tolerance (total)
10% Tolerance (total)
2009-2014 Microchip Technology Inc. DS20002121C-page 11
MCP23009/MCP23S09
FIGURE 1-4: FLASH ADC BLOCK DIAGRAM
ADDR
VDD
VSS
adc_en
adc_en
adc_en
adc_en
adc_en
adc_en
adc_en
addr_out 6
addr_out 5
addr_out 4
addr_out 3
addr_out 2
addr_out 1
addr_out 0
en
dqaddr<6:0>
set
dq
'0'
i2c_clk
adc_en
adc_en
adc_en
reset
i2c_addr<2:0>
+
-
+
-
+
-
+
-
+
-
+
-
+
-
MCP23009/MCP23S09
DS20002121C-page 12 2009-2014 Microchip Technology Inc.
FIGURE 1-5: HARDWARE ADDRESS DECODE TIMING
1.4.2 ADDRESSING I2C DEVICES
(MCP23009)
The MCP23009 is a slave I2C device that support s 7-bit
slave addressing, with the read/write bit filling out the
control b yte . The sla ve a ddre ss con t ai ns four fixed bits
and three user-defined hardware address bits
(configured via the ADDR pin). Figure 1-6 shows the
control by te forma t.
1.4.3 ADDRESSING SPI DEVICES
(MCP23S09)
The MCP23S09 is a slave SPI device. The slave
address contains seven fixed bits (no address bits),
with the read/write bit filling out the control byte.
Figure 1-7 shows the control byte format.
FIGURE 1-6: I2C™ CONTROL BYTE
FORMAT
FIGURE 1-7: SPI CONTROL BYTE
FORMAT
VDD
adc_en
i2c_addr[2:0]
i2c_clk
tADEN
tADDRLAT
tADDIS
S 0 1 0 0 A2A1A0R/WACK
Start
bit
Slave Address
R/W bit
ACK bit
Control Byte
R/W = 0 = write
R/W = 1 = read
0100000R/W
Slave Address
R/W bit
Control Byte
R/W = 0 = write
R/W = 1 = read
CS
2009-2014 Microchip Technology Inc. DS20002121C-page 13
MCP23009/MCP23S09
FIGURE 1-8: I2C™ ADDRESSING REGISTERS
FIGURE 1-9: SPI ADDRESSING REGISTERS
S0100A2A1A00ACKA7A6A5A4A3A2A1A0ACK
Device Opcode Register Address
R/W = 0
The ACKs are provided by the MCP23009.
0100000R/WA7A6A5A4A3A2A1A0
Device Opcode Register Address
CS
MCP23009/MCP23S09
DS20002121C-page 14 2009-2014 Microchip Technology Inc.
1.5 GPIO Port
The GPIO module is a general purpose 8-bit wide
bidirectional port.
The outputs are open-drain.
The GPIO module contains the data ports (GPIOn),
internal pull-up resistors and the output latches
(OLATn).
The pull-up resistors are individually configured and
can be enabled when the pin is configured as an input
or output.
Reading the GPIOn register reads the value on the
port. Reading the OLATn register only reads the
latches, not the actual value on the port.
Wr iting to the G PIOn registe r actua lly cau ses a write to
the latches (OLATn). Writing to the OLATn register
forces th e associated output dri vers to drive to the leve l
in OLATn. Pins configured as inputs turn off the
associated output driver and put it in high impedance.
2009-2014 Microchip Technology Inc. DS20002121C-page 15
MCP23009/MCP23S09
1.6 Configuration and Control
Registers
There are eleven (11) registers associated with the
MCP23X09, as shown in Table 1-4.
TABLE 1-4: CONFIGURATION AND CONTROL REGISTERS
Register
Name Address
(hex) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR/RST
Value
IODIR 00 IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0 1111 1111
IPOL 01 IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0 000 0 0000
GPINTEN 02 GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0 0000 0000
DEFVAL 03 DEF7 DEF6 DEF5 DEF4 DEF3 DEF2 DEF1 DEF0 0000 0000
INTCON 04 IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0 0000 0000
IOCON 05 —— SEQOP ——ODRINTPOLINTCC 0000 0000
GPPU 06 PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0 0000 0000
INTF 07 INT7 INT6 INT5 INT4 INT3 INT2 INT1 INTO 0000 0000
INTCAP 08 ICP7 ICP6 ICP5 ICP4 ICP3 ICP2 ICP1 ICP0 0000 0000
GPIO 09 GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0 000 0 0000
OLAT 0A OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0 0000 0000
MCP23009/MCP23S09
DS20002121C-page 16 2009-2014 Microchip Technology Inc.
1.6.1 I/O DIRECTION REGISTER
This register controls the direction of the data I/O.
When a bit is set, the corresponding pin becomes an
input. When a bit is clear, the corresponding pin
beco me s an outp ut.
REGISTER 1-1: IODIR – I/O DIRECTION REGISTER
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
IO7 IO6 IO5 IO4 IO3 IO2 IO1 IO0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 IO<7:0>: Controls the direction of data I/O <7:0>
1 = Pin is configured as an input
0 = Pin is configured as an output
2009-2014 Microchip Technology Inc. DS20002121C-page 17
MCP23009/MCP23S09
1.6.2 INPUT POLARITY REGISTER
This register allows the user to configure the polarity on
the corresponding GPIO port bits.
If a bit is set, the corresponding GPIO register bit will
reflect the inverted va lue on the pin.
REGISTER 1-2: IPOL – INPUT POLARITY PORT REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IP7 IP6 IP5 IP4 IP3 IP2 IP1 IP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 IP<7:0>: Controls the polarity inversion of the input pins <7:0>
1 = GPIO register bit will reflect the opposite logic state of the input pin
0 = GPIO register bit will reflect the same logic state of the input pin
MCP23009/MCP23S09
DS20002121C-page 18 2009-2014 Microchip Technology Inc.
1.6.3 INTERRUPT-ON-CHANGE
CONTROL REGISTER
The GPINTEN register controls the
Interrupt-on-Change feature for each pin.
If a bit is set, the corresponding pin is enabled for
Interrupt-on-Change. The DEFVAL and INTCON
registers must also be configured if any pins are
enabled for Interrupt-on-Change.
REGISTER 1-3: GPINTEN – INTERRUPT-ON-CHANGE PINS
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GPINT7 GPINT6 GPINT5 GPINT4 GPINT3 GPINT2 GPINT1 GPINT0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 GPINT<7:0>: General-purpose I/O interrupt-on-change pins <7:0>
1 = Enable GPIO input pin for Interrupt-on-Change event
0 = Disable GPIO input pin for Interrupt-on-Change event
Refer to the INTCON and DEFVAL registers.
2009-2014 Microchip Technology Inc. DS20002121C-page 19
MCP23009/MCP23S09
1.6.4 DEFAULT COMPARE REGISTER
FOR INTERRUPT-ON-CHANGE
The default comparison value is configured in the
DEFVAL register. If enabled (via GPINTEN and
INTCON) to compare against the DEFVAL register, an
opposite value on the associated pin will cause an
Interrupt to occur.
REGISTER 1-4: DEFVAL – DEFAULT VALUE REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
DEF7 DEF6 DEF5 DEF4 DEF3 DEF2 DEF1 DEF0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 DEF<7:0>: Sets the compare value for pins configured for Interrupt-on-Change from defaults <7:0>.
Refer to the INTCON register.
If the associated pin level is the opposite from the register bit, an Interrupt occurs.
Refer to the INTCON and GPINTEN registers.
MCP23009/MCP23S09
DS20002121C-page 20 2009-2014 Microchip Technology Inc.
1.6.5 INTERRUPT CONTROL REGISTER
The INTCON register controls how the associated pin
value is comp ared for the Inte rrupt-on-C han ge featu re.
If a bit is set, the corresponding I/O pin is compared
against the associated bit in the DEFVAL register. If a
bit value is clea r, the corresponding I/O pin is compared
against the previous value.
REGISTER 1-5: INTCON – INTERRUPT-ON-CHANGE CONTROL REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
IOC7 IOC6 IOC5 IOC4 IOC3 IOC2 IOC1 IOC0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 IOC<7:0>: Controls how the associa ted pin value is compared f or In terrupt- on-Change <7:0>.
1 = Pin value is compared against the associated bit in the DEFVAL register
0 = Pin value is compared against the previous pin value
Refer to the DEFVAL and GPINTEN registers.
2009-2014 Microchip Technology Inc. DS20002121C-page 21
MCP23009/MCP23S09
1.6.6 CONFIGURATION REGISTER
The Sequential Operation (SEQOP) bit controls the
incrementing function of the address pointer. If the
address pointer is disabled, the address pointer does
not automatically increment after each byte is clocked
during a s eria l tra ns fer. This feat ure i s us efu l when it is
desired to continuously poll (read) or modify (write) a
register.
The Ope n-Drain (ODR) co ntrol bit enables /disables the
INT pin for open-drain configuration.
The Interrupt Polarity (INTPOL) bit sets the polarity of
the IN T pin. Thi s bit i s functiona l only wh en the O DR bit
is cl eare d, configuring the I NT pin as active push- pull.
The Interrupt Clearing Control (INTCC) bit configures
how Interru pt s are cl eared. When se t (IN TCC = 1), the
Interrupt is cleared when the INTCAP register is read.
When cleared (INTCC = 0), the Interrupt is cleared
when the GPIO register is read.
The Interrupt can only be cleared when the Interrupt
condition is inactive. Refer to Section 1.7.4 “Clearing
Interrupts” for details.
REGISTER 1-6: IOCON – I/O EXPANDER CONFIGURATION REGISTER
U-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0
— — SEQOP —— ODR INTPOL INTCC
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7 Unimplemented: Read as ‘0’
bit 6 Unimplemented: Read as ‘0’
bit 5 SEQOP: Sequential Operation mode bit.
1 = Sequential operation disabled, address pointer does not increment
0 = Sequential operation enabled, address pointer increments
bit 4 Unimplemented: Read as ‘0’
bit 3 Unimplemented: Read as ‘0’
bit 2 ODR: Configures the INT pin as an open-drain output.
1 = Open-drain output (overrides the INTPOL bit)
0 = Active driver output (INTPOL bit sets the polarity)
bit 1 INTPOL: Sets the polarity of the INT output pin.
1 =Active-High
0 =Active-Low
bit 0 INTCC: Interrupt Clearing Control
1 = Reading INTCAP register clears the Interrupt
0 = Reading GPIO register clears the Interrupt
MCP23009/MCP23S09
DS20002121C-page 22 2009-2014 Microchip Technology Inc.
1.6.7 PULL-UP RESISTOR
CONFIGURATION REGISTER
The GPPU reg ister con trols the pull -up resist ors for the
port pins. If a bit is set, the corresponding port pin is
internally pulled up with an internal resistor.
FIGURE 1-10: TYPICAL PERFORMANCE CURVE FOR THE INTERNAL PULL-UP RESISTORS
REGISTER 1-7: GPPU – GPIO PULL-UP RESISTOR REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
PU7 PU6 PU5 PU4 PU3 PU2 PU1 PU0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 PU<7:0>: Controls the internal pull-up resistors on each pin (when configured as an input or output)
<7:0>.
1 = Pull-Up enabled
0 = Pull-Up disabled
0
50
100
150
200
250
300
350
400
1.5 2 2.5 3 3.5 4 4.5 5 5.5
IPU (µA)
V
DD
(V)
GPIO Pin Internal Pull-Up Current vs. V
DD
T = -40°C
T = +25°C
T = +125°C
T = +85°C
2009-2014 Microchip Technology Inc. DS20002121C-page 23
MCP23009/MCP23S09
1.6.8 INTERRUPT FLAG REGISTER
The INTF register refl ects the Interrupt c ondition on the
port pins of any pin that is enabled for interrupts via the
GPINTEN register. A set bit indicates that the
associated pin caused the Interrupt.
This register is read-only. Writes to this register will be
ignored.
REGISTER 1-8: INTF – INTERRUPT FLAG REGISTER
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
INT7 INT6 INT5 INT4 INT3 INT2 INT1 INT0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 INT<7:0>: Reflects the interrupt condition on the port. Will reflect the change only if interrupts are
enabled (GPINTEN) <7:0>.
1 = Pin caused Interrupt
0 = Interrupt not pending
MCP23009/MCP23S09
DS20002121C-page 24 2009-2014 Microchip Technology Inc.
1.6.9 INTERRUPT CAPTURE REGISTER
The INTCAP register captures the GPIO port value at
the time the Interrupt occurred. The register is
read-only’ and is updated only when an Interrupt
occurs. The register will remain unchanged until the
Interrupt is cleared via a read of INTCAP or GPIO.
REGISTER 1-9: INTCAP – INTERRUPT CAPTURED VALUE FOR PORT REGISTER
R-x R-x R-x R-x R-x R-x R-x R-x
ICP7 ICP6 ICP5 ICP4 ICP3 ICP2 ICP1 ICP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 ICP<7:0>: Reflects the logic level on the port pins at the time of Interrupt due to pin change <7:0>.
1 = Logic-High
0 = Logic-Low
2009-2014 Microchip Technology Inc. DS20002121C-page 25
MCP23009/MCP23S09
1.6.10 PORT REGISTER
The GPIO register reflects the value on the port.
Readi ng from this reg ister reads the por t. Writin g to this
register modifies the Output Latch (OLAT) register.
REGISTER 1-10: GPIO – GENERAL PURPOSE I/O PORT REGISTER
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
GP7 GP6 GP5 GP4 GP3 GP2 GP1 GP0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 GP<7:0>: Reflects the logic level on the pins <7:0>.
1 = Logic-High
0 = Logic-Low
MCP23009/MCP23S09
DS20002121C-page 26 2009-2014 Microchip Technology Inc.
1.6.11 OUTPUT LATCH REGISTER (OLAT)
The OLAT register provides access to the output
latches . A read from this regi ster results in a read of the
OLAT and not the port itself. A write to this register
modifies the output latches that modifies the pins
configured as outputs.
REGISTER 1-11: OLAT – OUTPUT LATCH REGISTER 0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
OL7 OL6 OL5 OL4 OL3 OL2 OL1 OL0
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
bit 7-0 OL<7:0>: Reflects the logic level on the output latch <7:0>.
1 = Logic-High
0 = Logic-Low
2009-2014 Microchip Technology Inc. DS20002121C-page 27
MCP23009/MCP23S09
1.7 Interrupt Logic
If enabled, the MCP23X09 activates the INT interrupt
output when one of the port pin s changes state or when
a pin does not mat ch t he pr e- confi gur ed de fau lt. E ach
pin is individually configurable as follows:
• Enable/disable interrupt via GPINTEN
• Can Inte rrupt on either pin chan ge or change from
default as co nfig ured in DEFVAL
Both condi tio ns are referred to as Inte rrupt-o n-Change
(IOC).
The Interrupt Control Module uses the following
registers/bits:
• GPINTEN – Interrupt enable register
• INTCON – Controls the source for the IOC
• DEFVAL – Contains the register default for IOC
operation
• IOCON (ODR and INTPOL) – Configures the INT
pin as pus h-pull, open -drain and act ive level (high
or low).
1.7.1 IOC FROM PIN CHANGE
If enabled, the MCP23X09 will generate an Interrupt if
a mismatch condition exists between the current port
value and the previous port value. Only IOC-enabled
pins will be compared. See the GPINTEN and INTCON
registers.
1.7.2 IOC FROM REGIST ER DEFAULT
If enabled, the MCP23X09 will generate an Interrupt if
a mismatch occurs between the DEFVAL register and
the port. Only IOC-enab led pins wi ll be co mpared. See
the GPINTEN, INTCON and DEFVAL registers.
1.7.3 INTERRUPT OPERATION
The INT interrupt output can be configured as
active-low, active-high or open-drain via the IOCON
register.
Only tho se pins that are co nfi gured as an inpu t (IODIR
register) with Interrupt-on-Change (IOC) enabled
(GPINTEN register) can cause an Interrupt. Pins
configured as an output have no effect on the interrupt
output pin.
Input ch an ge act iv ity on a port input pin th at is ena ble d
for IOC will generate an internal device Interrupt and
the devic e wi ll captu re the va lue of the port and cop y it
into INTCAP.
The first Interrupt event will cause the port contents to
be copied into the INTCAP register. Subsequent
Interrupt conditions on the port will not cause an
Interrupt t o occu r as lo ng as the Inte rrupt is not cleare d
by a read of INTCAP or GPIO.
1.7.4 CLEARING INTERRUPTS
The Interrupt will remain active until the INTCAP or
GPIO register is read (depending on IOCON.INTCC).
Writing to these registers will not affect the Interrupt.
The Interrupt condition will be cleared after the LSb of
the dat a is c locked o ut during a read operati on of GPIO
or INTCAP (depending on IOCON.INTCC).
Note: Assuming IOCON.INTCC = 0 (INT
cleared on GPIO read), the value in
INTCAP can be lo st if GPIO is read before
INTCAP while another IOC is pending.
After re ading GPIO, the Interru pt will clear
and then set due to the pending IOC,
causing the INTCAP register to update.
MCP23009/MCP23S09
DS20002121C-page 28 2009-2014 Microchip Technology Inc.
1.7.5 INTERRUPT CONDITIONS
There are two possible configurations to cause
Interrupts (configured via INTCON):
1. Pins configured for Interrupt-on-Pin-Change
will cause an Interrupt to occur if a pin changes
to the opposite state. The default state is reset
after an Interrupt occurs. For example, an
Interrupt occurs by an input changing from 1 to
0. The new initial state for the pin is a logic 0.
2. Pins configured for Interrupt-on-Change from
registe r value will c aus e a n Interru pt to oc cu r if
the corresponding input pin differs from the
register bit. The Interrupt condition will remain
as long as the condition exists, regardless of
whether the INTAP or GPIO is read.
See Figures 1-11 and 1-12 for more inform at ion on th e
interrupt operations.
FIGURE 1-11: INTERR UPT-ON-PIN-CHANGE
FIGURE 1-12: INTERRUPT-ON-CHANGE
FROM REGISTER
DEFAULT
GPx
INT ACTIVE ACTIVE
Port value
is captured
into INTCAP
Read GPIO
or INTCAP Port value
is captured
into INTCAP
INT
Port value
is captur ed
into INTCAP Read GPIO
or INTCAP
DEFVAL
X X X X X 1 X X
GP2
76543210GP:
ACTIVE
ACTIVE
(INT clears on ly if Interrupt
condition does not exist.)
2009-2014 Microchip Technology Inc. DS20002121C-page 29
MCP23009/MCP23S09
2.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
Ambient temperature under bias.............................................................................................................-40°C to +125°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.0V
Voltage on RESE T with respect to VSS ..................................................................................................... -0.3V to +14V
Voltage on all other pins with respect to VSS (except VDD and GPIOA/B) .....................................-0.6V to (VDD +0.6V)
Voltage on GPIO Pins..................................................................................................................................-0.6V to 5.5V
Total power dissipation (Note 1)..........................................................................................................................700 mW
Maximum current out of VSS pin ...........................................................................................................................200 mA
Maximum current into VDD pin..............................................................................................................................125 mA
Input clamp current, IIK (VI<0 or VI>VDD) 20 mA
Output clamp cur rent, IOK (VO<0 or VO>VDD) 20 mA
Maximum output current sunk by any output pin....................................................................................................25 mA
Maximum output current sunk by any output pin (VDD = 1.8V)...............................................................................10 mA
ESD protection on all pins (HBM:MM) ..............................................................................................................4 kV:400V
Note 1: Power dissipation is ca lcu la ted as follow s :
PDIS =VDD x{IDD – IOH}+ {(VDD –VOH)xIOH}+(VOL xIOL).
†Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage
to the device. This is a stress rating only and functional operation of the device at those or any other
conditions above those indicated in the operation listings of this specification is not implied. Exposure to
maximum rating conditions for extended periods may affect device reliability.
MCP23009/MCP23S09
DS20002121C-page 30 2009-2014 Microchip Technology Inc.
2.1 DC Characteristics
DC Characteristics Electrical Characteristics: Unless otherwise indicated, all limits are specified
for 1.8V  VDD 5.5V at -40C TA +125C.
Param.
No. Characteristic Sym. Min. Typ.(2)Max. Units Conditions
D001 Supply Voltage VDD 1.8 — 5.5 V
D002 VDD Start Voltage
to Ensure Power-On Reset VPOR —VSS —V
D003 VDD Rise Rate to Ensure
Power-On Reset SVDD 0.05 — — V/ms Design guidance only.
Not tested.
D004 Supply Current IDD — — 1 mA SCL/SCK = 1 MHz
D005 Sta nd by (Idl e) curre nt IDDS ——1µA–40°C TA +85°C
——6µA+85°C TA +125°C
Input Low-Voltage
D031 CS, GPIO, SCL/SCK,
SDA, SI, RESET VIL VSS —0.2VDD V
Input High-Voltage
D041 CS, SCL/SCK, SDA, SI,
RESET VIH 0.8 VDD —VDD V
GPIO VIH 0.8 VDD —5.5 V
Input Leakage Current
D060 I/O port pins IIL ——±1µAVSS  VPIN  VDD
Output Leakage Current
D065 I/O port pins ILO ——±1µAVSS  VPIN  VDD
D070 GPIO internal pull-up
current IPU — 220 — µA VDD =5V, GP Pins=VSS
(Note 1)
Output Low-Voltage
D080 GPIO VOL ——0.6VIOL = 8.5 mA, VDD =4.5V
(open-drain)
INT — — 0.6 IOL = 1.6 mA, VDD =4.5V
SO, SDA — — 0.6 IOL = 3.0 mA, VDD =1.8V
SDA — — 0.8 IOL = 3.0 mA, VDD =4.5V
Output High-Voltage
D090 INT, SO VOH VDD –0.7 — — V IOH =-3.0mA, VDD =4.5V
VDD – 0.7 — — IOH =-400µA, VDD =1.8V
Capacitive Loading Specs on Output Pins
D101 GPIO, SO, INT CIO — — 50 pF These are load conditions for
the timing specifications.
Refer to Figure 2-1.
SDA test condition is 135 pF.
D102 SDA CB——400
(1)
Note 1: This parameter is characterized, not 100% tested.
2: Data in the Typical (“Typ”) column is at 5V, +25C, unless otherwise stated.
2009-2014 Microchip Technology Inc. DS20002121C-page 31
MCP23009/MCP23S09
2.2 AC CHARACTERISTICS
FIGURE 2-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
FIGURE 2-2: RES ET AND DEVICE RESET TIMER TIMING
TABLE 2-1: RESET AND DEVICE RESET TIMER REQUIREMENTS
AC Characteristics Electrical Characteristics: Unless otherwise indicated, all limits are specified for
1.8V  VDD 5.5V at -40C TA +125C.
Param.
No. Sym. Characteristic Min. Typ.(2)Max. Units Conditions
30 TRSTL RESET Pulse Width (low) 1 — — µs VDD =5.0V
32 THLD Device ac tiv e af ter res et high — 0 — µs VDD =5.0V
31 TPOR POR at device power-up — 20 — µs VDD =5.0V
34 TIOZ Output high-impedance from
RESET Low —— 1 µs
Note 1: This parameter is characterized, not 100% tested.
2: Data in the Typical (“Typ”) column is at 5V, +25C, unless otherwise stated.
135 pF
1k
VDD
SCL and
SDA pin
MCP23009
50 pF
Pin
MCP23009/MCP23S09
DS20002121C-page 32 2009-2014 Microchip Technology Inc.
FIGURE 2-3: GPIO AND INT TIMING
TABLE 2-2: GP AND INT PINS
AC Characteristics Electrical Characteristics : Unless otherwise indicated, all limits are specified for
1.8V  VDD 5.5V at -40C TA +125C.
Param.
No. Sym. Characteristic Min. Typ.(2)Max. Units Conditions
50 tGPOV Serial data to output valid — — 500 ns
51 tINTD Interrupt pin disable time — — 600 ns
52 tGPIV GP input change to register valid — 450 — ns Note 1
53 tGPINT IOC event to INT active — — 600 ns
54 tGLITCH Glitch filter on GP pins — — 50 ns Note 1
Note 1: This parameter is characterized, not 100% tested.
2: Data in the Typical (“Typ.”) column is at 5V, +25C, unless otherwise stated.
50
SCL
SDA
In
GPn
Pin
D0
D1
LSb of data byte zero
during a write or read
INT
Pin INT pin active INT pin
51
command, depending
on parameter
Output
GPn
Pin
Input
inactive
53
52
Register
Loaded
2009-2014 Microchip Technology Inc. DS20002121C-page 33
MCP23009/MCP23S09
FIGURE 2-4: HARDWARE ADDRESS LATCH TIMING
TABLE 2-3: HARDWARE ADDRESS LATCH TIMING
AC Characteristics Electrical Characteristics : Unless otherwise indicated, all limits are specified for
1.8V  VDD 5.5V at -40C TA +125C.
Param.
No. Sym. Characteristic Min. Typ.(2)Max. Units Conditions
40 tADEN Time from VDD stable after
POR to ADC enable —0—µsNote 1
41 tADDRLAT Time from ADC enable to
address decode and latch —50—nsNote 1
42 tADDIS Time from raising edge of
serial cloc k to ADC dis able —10—nsNote 1
Note 1: This parameter is characterized, not 100% tested.
2: Data in the Typical (“Typ.”) column is at 5V, +25C, unless otherwise stated.
VDD
adc_en
i2c_addr[2:0]
SCL
40
41
42
MCP23009/MCP23S09
DS20002121C-page 34 2009-2014 Microchip Technology Inc.
FIGURE 2-5: I2C™ BUS START/STOP BITS TIMING
FIGURE 2-6: I2C™ BUS DATA TIMING
Note 1: Refer to Figure 2-1 for load conditions.
91 93
SCL
SDA
Start
Condition Stop
Condition
90 92
Note 1: Refer to Figure 2-1 for load conditions.
90 91 92
100 101
103
106 107
109 109 110
102
SCL
SDA
In
SDA
Out
2009-2014 Microchip Technology Inc. DS20002121C-page 35
MCP23009/MCP23S09
TABLE 2-4: I2C™ BUS DATA REQUIREM ENTS (SLAVE MODE)
I2C™ AC Characteristics Electrical Characterist ics: Unless otherwise indicated, all limits are
specified for 1.8V VDD 5.5V at -40C TA +125C,
RPU (SCL, SDA) = 1 k, CL (SCL, SDA) = 135 pF.
Para m .
No. Characteristic Sym. Min. Typ. Max. Units Conditions
100 Clock High Time: THIGH
100 kHz mode 4.0 — — µs 1.8V – 5.5V
400 kHz mode 0.6 — — µs 1.8V – 5.5V
3.4 MHz mode 0.06 — — µs 2.7V – 5.5V
101 Clock Low Time: TLOW
100 kHz mode 4.7 — — µs 1.8V – 5.5V
400 kHz mode 1.3 — — µs 1.8V – 5.5V
3.4 MHz mode 0.16 — — µs 2.7V – 5.5V
102 SDA and SCL Rise Time: TR
(Note 1)
100 kHz mode — — 1000 ns 1.8V – 5.5V
400 kHz mode 20 + 0.1 CB(2) — 300 ns 1.8V – 5.5V
3.4 MHz mode 10 — 80 ns 2.7V – 5.5V
103 SDA and SCL Fall Time: TF
(Note 1)
100 kHz mode — — 300 ns 1.8V – 5.5V
400 kHz mode 20 + 0.1 CB(2) — 300 ns 1.8V – 5.5V
3.4 MHz mode 10 — 80 ns 2.7V – 5.5V
90 Start Condition Setup Time: TSU:STA
100 kHz mode 4.7 — — µs 1.8V – 5.5V
400 kHz mode 0.6 — — µs 1.8V – 5.5V
3.4 MHz mode 0.16 — — µs 2.7V – 5.5V
91 Start Condition Hold Time: THD:STA
100 kHz mode 4.0 — — µs 1.8V – 5.5V
400 kHz mode 0.6 — — µs 1.8V – 5.5V
3.4 MHz mode 0.16 — — µs 2.7V – 5.5V
106 Data Input Hold Time: THD:DAT
100 kHz mode 0 — 3.45 µs 1.8V – 5.5V
400 kHz mode 0 — 0.9 µs 1.8V – 5.5V
3.4 MHz mode 0 — 0.07 µs 2.7V – 5.5V
107 Data Input Setup Time: TSU:DAT
100 kHz mode 250 — — ns 1.8V – 5.5V
400 kHz mode 100 — — ns 1.8V – 5.5V
3.4 MHz mode 0.01 — — µs 2.7V – 5.5V
92 Stop Condition Setup Time: TSU:STO
100 kHz mode 4.0 — — µs 1.8V – 5.5V
400 kHz mode 0.6 — — µs 1.8V – 5.5V
3.4 MHz mode 0.16 — — µs 2.7V – 5.5V
Note 1: This parameter is characterized, not 100% tested.
2: CB is specified from 10 to 400 (pF).
3: This parameter is not applicable in high-speed mode (3.4 MHz).
MCP23009/MCP23S09
DS20002121C-page 36 2009-2014 Microchip Technology Inc.
FIGURE 2-7: SPI INPUT TIMING
109 Output Valid From Clock: TAA
100 kHz mode — — 3.45 µs 1.8V – 5.5V
400 kHz mode — — 0.9 µs 1.8V – 5.5V
3.4 MHz mode — — 0.18 µs 2.7V – 5.5V
110 Bus Free Time: TBUF
(Note 3)
100 kHz mode 4.7 — — µs 1.8V – 5.5V
400 kHz mode 1.3 — — µs 1.8V – 5.5V
3.4 MHz mode N/A — N/A µs 2.7V – 5.5V
Bus Capacitive Loadi ng: CB
(Note 2)
100 kHz and 400 kHz — — 400 pF Note 1
3.4 MHz — — 100 pF Note 1
Input Filter Spike
Suppression: (SDA and SCL) TSP
100 kHz and 400 kHz — — 50 ns Note 1
3.4 MHz — — 10 ns Note 1
TABLE 2-4: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) (CONTINUED)
I2C™ AC Characteristics Electrical Characterist ics: Unless otherwise indicated, all limits are
specified for 1.8V VDD 5.5V at -40C TA +125C,
RPU (SCL, SDA) = 1 k, CL (SCL, SDA) = 135 pF.
Para m .
No. Characteristic Sym. Min. Typ. Max. Units Conditions
Note 1: This parameter is characterized, not 100% tested.
2: CB is specified from 10 to 400 (pF).
3: This parameter is not applicable in high-speed mode (3.4 MHz).
CS
SCK
SI
SO
1
5
4
7
6
3
10
2
LSB in
MSB in
high impedance
11
Mode 1,1
Mode 0,0
2009-2014 Microchip Technology Inc. DS20002121C-page 37
MCP23009/MCP23S09
FIGURE 2-8: SPI OUTPUT TIMING
CS
SCK
SO
8
13
MSB out LSB out
2
14
don’t care
SI
Mode 1,1
Mode 0,0
9
12
MCP23009/MCP23S09
DS20002121C-page 38 2009-2014 Microchip Technology Inc.
FIGURE 2-9: TYPICAL PERFORMANCE CURVE FOR SPI TV SPECIFICATION (PARAM #12)
TABLE 2-5: SPI INTERFACE AC CHARACTERISTICS
SPI Interface AC Charac ter is tics Electrical Characteristics: Unless otherwise indicated, all limits are specified
for 1.8V V
DD 5. 5V at -40C TA +125C.
Param.
No. Characteristic Sym. Min. Typ. Max. Units Conditions
Clock Freq uen cy FCLK — — 10 MHz 1.8V – 5.5V
1CS
Setup Time TCSS 50 — — ns
2CS
Hold Time TCSH 50 — — ns 1.8V – 5.5V
3CS
Disable Time TCSD 50 — — ns 1.8V – 5.5V
4 Data Setup Time TSU 10 — — ns 1.8V – 5.5V
5Data Hold Time THD 10 — — ns 1.8V – 5.5V
6CLK Rise Time T
R——2µsNote 1
7CLK Fall Time TF——2µsNote 1
8Clock High Time THI 45 — — ns 1.8V – 5.5V
9 Clock Low Time TLO 45 — — ns 1.8V – 5.5V
10 Clock Delay Time TCLD 50 — — ns
11 Clock Enable Time TCLE 50 — — ns
12 Output Valid from Clock
Low TV— — 45 ns 1.8V – 5.5V
13 O utput Hold Time THO 0——ns
14 Output Di sable Time TDIS — — 100 ns
Note 1: This parameter is characterized, not 100% tested.
0
5
10
15
20
25
30
35
40
1.5 2 2.5 3 3.5 4 4.5 5 5.5
T
V
(ns)
V
DD
(V)
T
V
vs. V
DD
T = -40°C
T = +25°C
T = +125°C
T = +85°C
2009-2014 Microchip Technology Inc. DS20002121C-page 39
MCP23009/MCP23S09
3.0 PACKAGING INFORMATION
3.1 Package Marking Information
16-Lead QFN (3x3x0.9 mm) Example
2S9
E432
256
18-Lead PDIP (300 mil) Example
MCP23S09
E/P ^^
1432256
3
e
18-Lead SOIC (7.50 mm) Example
MCP23S09
E/SO ^^
1432
256
3
e
20-Lead SSOP (5.30 mm) Example
MCP23009
E/SS ^^
1432256
3
e
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanu me ric trac ea bil ity code
Pb-free JEDEC® designator for Matte Tin (Sn)
*This package is Pb-fr ee. The Pb- fre e JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the ev ent the fu ll Mic rochip part nu mber ca nnot be m arked o n one lin e, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
EYWW
MCP23009/MCP23S09
DS20002121C-page 40 2009-2014 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2014 Microchip Technology Inc. DS20002121C-page 41
MCP23009/MCP23S09
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP23009/MCP23S09
DS20002121C-page 42 2009-2014 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2014 Microchip Technology Inc. DS20002121C-page 43
MCP23009/MCP23S09
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c
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MCP23009/MCP23S09
DS20002121C-page 44 2009-2014 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2014 Microchip Technology Inc. DS20002121C-page 45
MCP23009/MCP23S09
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP23009/MCP23S09
DS20002121C-page 46 2009-2014 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2014 Microchip Technology Inc. DS20002121C-page 47
MCP23009/MCP23S09
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φ
L
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e
b
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MCP23009/MCP23S09
DS20002121C-page 48 2009-2014 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2009-2014 Microchip Technology Inc. DS20002121C-page 49
MCP23009/MCP23S09
APPENDIX A: REVISION HISTORY
Revision C (August 2014)
The following is the list of modifications:
1. Added ESD data in the Absolute Maximum
Ratings (†) section.
2. Updated Figure 1-1.
3. U pdated t he DC Characteristics table.
4. Updated the Package Marking Information
section.
5. Minor typographical changes.
Revision B (May 2009)
The following is the list of modifications:
1. Added the 3x3 QFN package (MG package
marking).
2. U pdated Revisi on History.
Revision A (December 2008)
• Original Releas e of th is Do cument.
MCP23009/MCP23S09
DS20002121C-page 50 2009-2014 Microchip Technology Inc.
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: MCP23009: 8-Bit I/O Expander w/ I2C™ Interface
MCP23009T: 8-Bit I/O Expander w/ I2C Inter face
(Tape and Reel)
MCP23S09: 8 -Bit I/O Expander w/ SPI Interfa ce
MCP23S09T: 8-Bit I/O Expander w/ SPI Interface
(Tape and Reel)
Tem perature
Range: E= -40C to +125C (Extended)
Package: MG = Plastic Quad Flat, No Lead Package –
3x3x0.9 mm Body, 16-Lead
P = Plastic Dual In-Line – 300 mil Body, 18-Lead
SO = Plastic Small Outline – Wide, 7.50 mm Body,
18-Lead
SS = Lead Plastic Shrink Small Outline –
5.30 mm Body, 20-Lead
PART NO. -X /XX
PackageTemperature
Range
Device
Examples:
a) MCP23009-E/MG: Extended Temperature,
16LD QFN package
b) MCP23009-E/P: Extended Tem perature,
18LD PDIP package
c) MCP23009-E/SO: Extended Temperature,
18LD SOIC package
d) MCP23009T-E/SO: Tape and Reel,
Extended Temperature,
18LD SOIC package
e) MCP23009-E/SS: Extended Temperature,
20LD SSOP package
f) MCP23009T-E/SS: Tape and Reel,
Extended Temperature,
20LD SSOP package
a) MCP23S09-E/MG: Extended Temperature,
16LD QFN package
b) MCP23S09T-E/MG: Tape and Reel,
Extended Temperature,
16LD QFN package
c) MCP23S09-E/P: Extended Temperature,
18LD PDIP package
d) MCP23S09-E/SO: Extended Temperature,
18LD SOIC package
e) MCP23S09T-E/SO: Tape and Reel,
Extended Temperature,
18LD SOIC package
2009-2014 Microchip Technology Inc. DS20002121C-page 51
Information contained in this publication regarding device
applications a nd the lik e is pro vid ed only for your c on ve nience
and may be supers eded by u pdates. It is y our res po ns i bil it y to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer ,
LANCheck, MediaLB, MOST, MOST logo, MPLAB,
OptoL yzer , PIC, PICSTART, PIC32 logo, RightTouch, S pyNIC,
SST, SST Logo, SuperFlash and UNI/O are registered
trademarks of Microchip Technology Inc orporated in the
U.S.A. and other countries.
The Embedded Control Solutions Company and mTouch are
registered trademarks of Microchip Technology Incorporated
in the U.S.A.
Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo,
CodeGuard, dsPICDEM, dsP ICDEM. net, ECA N, In-Circuit
Serial Programming, ICSP, Inter-Chip Connectivity , KleerNet,
KleerNet logo, MiWi, MPAS M, MPF, MPLAB Cert ified logo,
MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail,
RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total
Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporat ed in the U.S.A. and other
countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
Silicon Stor age Te chnology is a registered trademark of
Microchip Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Micro chip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2009-2014, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
ISBN: 978-1-63276-540-6
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that it s f amily of products is one of t he most secure famili es of its kind on the market t oday, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT S
YSTEM
CERTIFIED BY DNV
== ISO/TS 16949 ==
DS20002121C-page 52 2009-2014 Microchip Technology Inc.
AMERICAS
Corporate Office
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Chandler, AZ 85224-6199
Tel: 480-792-7200
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Technical Su pport:
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China - Chengdu
Tel: 86-28-8665-5 511
Fax: 86-28-8665-7889
China - Chongqing
Tel: 86-23-8980-9 588
Fax: 86-23-8980-9500
China - Hangzhou
Tel: 86-571-8792-8115
Fax: 86-571-8792-8116
China - Hong Kong SAR
Tel: 852-2943-5100
Fax: 852-2401-3431
China - Nanjing
Tel: 86-25-8473-2 460
Fax: 86-25-8473-2470
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
China - Shanghai
Tel: 86-21-5407-5 533
Fax: 86-21-5407-5066
China - Shenyang
Tel: 86-24-2334-2 829
Fax: 86-24-2334-2393
China - Shenzhen
Tel: 86-755-8864-2200
Fax: 86-755-8203-1760
China - Wuhan
Tel: 86-27-5980-5 300
Fax: 86-27-5980-5118
China - Xian
Tel: 86-29-8833-7 252
Fax: 86-29-8833-7256
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
ASIA/PACIFIC
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
India - Pune
Tel: 91-20-3019-1500
Japan - Osaka
Tel: 81-6-6152-7160
Fax: 81-6-6152-9310
Japan - Tokyo
Tel: 81-3-6880- 3770
Fax: 81-3-6880-3771
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Taiwan - T aipei
Tel: 886-2-2508-8600
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Cop e nha gen
Tel: 45-4450-2828
Fax: 45-4485-2829
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Dusseldorf
Tel: 49-2129-3766400
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-14 4-44
Germany - Pforzheim
Tel: 49-7231-424750
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Italy - Venice
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Poland - Warsaw
Tel: 48-22-3325737
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08 -91
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921- 5800
Fax: 44-118-921- 5820
Worldwide Sales and Service
03/25/14