Simplifying S ystem Integration
TM
73S8024C
Demo Board User Manual
Nov e mb er 11 , 2009
Rev. 1.3
UM_8024C_061
73S 8024C Demo Board User Manual UM_8024C_061
2 Rev. 1.3
© 20 09 Teridi an Semiconductor C or porati on. All r i ghts r eserve d.
Terid ian Semiconductor Corporation is a registered t r ademar k of Teridian S emico nduct or C or por ation.
S impli fying S ystem Integ r ation i s a trademark of Teridian Semi condu ctor Corpor ation.
A ll other t r ademar ks ar e the property of their r espective own er s.
Terid ian Semiconductor Corporation make s no warran ty for the use of its pr oducts, other t han expressly
contained in the Com pany’s warrant y det ailed in the Terid ian Semiconductor Corporation standard Terms
and Cond ition s. The company assumes no r esponsibili ty for any errors wh i ch may app ear in this
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notice and does not m ake any commi tment t o update th e in format ion cont ai ned herein . Accordingl y, the
reader is ca utioned to verify th at this d ocument is current by comparing i t to the latest version on
http://www.teridi an.co m or by checking with you r sales representative.
Terid ian Semiconductor Corp. , 6440 Oak C anyon, Suite 100, I r vine, CA 92618
TEL (714) 508-8800, FAX (714) 508-8877, http://www.teridian.com
UM_8024C_061 7 3S8024C D emo Board User Manual
Rev. 1.3 3
Table of Contents
1 Introduction ................................................................................................................................... 5
1.1 Package Content s.................................................................................................................... 5
1.2 Safety and ESD Not es ............................................................................................................. 5
2 Basic Connections ........................................................................................................................ 6
3 Hardware Description .................................................................................................................... 7
3.1 Demo B oar d C onnector s, Jum per s and Test Points ................................................................. 7
3.2 Recommended Operating Conditions and Absol ute Maximum R atings ..................................... 9
3.3 73S8024C Pin D escription ....................................................................................................... 9
3.4 73S8024C Pinout .................................................................................................................. 11
4 Design Consi derations ................................................................................................................ 12
4.1 General Layout Ru les ............................................................................................................ 12
4.2 Optimization for Comp liance with EMV and NDS .................................................................... 12
5 73S8024C Demo Board Schematics, PCB Layouts and Bill of M aterials .................................. 13
5.1 Schematic .............................................................................................................................. 13
5.2 Bill of Materials ...................................................................................................................... 14
5.3 PCB Layouts .......................................................................................................................... 15
6 Orde r ing Inform ation ................................................................................................................... 18
7 Related Documentation ............................................................................................................... 18
8 Contact Information ..................................................................................................................... 18
Revisi on History .................................................................................................................................. 19
73S 8024C Demo Board User Manual UM_8024C_061
4 Rev. 1.3
Figures
Figure 1: 73S8024C Demo Board ............................................................................................................ 5
Fi gure 2: 73S802 4C Demo Board Basic C onnection s .............................................................................. 6
Fi gure 3: 73S802 4C Demo Board Connectors, Jumpers and Test Point s ................................................. 8
Figure 4: 73S8024C SO28 Pinout (Top View) ........................................................................................ 11
Fi gure 5: 73S802 4C Demo Board El ectrical Schemat i c .......................................................................... 13
Fi gure 6: 73S802 4C Demo Board Top Vi ew ........................................................................................... 15
Fi gure 7: 73S802 4C Demo Board Bott om View ...................................................................................... 15
Figure 8: 73S802 4C Demo Board Top Signal Layer ............................................................................... 16
Fi gure 9: 73S802 4C Demo Board Mi ddl e Layer 1, Gr ound Plane ........................................................... 16
Figure 10: 73S8024C Middle Layer 2, Supply Plane .............................................................................. 17
Fi gure 11: 73S8024C Dem o Board Bott om Signal Layer ........................................................................ 17
Tables
Tabl e 1: 73S 8024C D emo Board Connector , Jumper and Test Points ...................................................... 7
Tabl e 2: Recommended Operat in g C ondi tions ......................................................................................... 9
Tabl e 3: Ab solute Maximum R atings ........................................................................................................ 9
Tabl e 4: 73S 8024C C ar d Interface Pins ................................................................................................... 9
Tabl e 5: 73S 8024C M i scellaneous P i ns ................................................................................................. 10
Tabl e 6: 73S 8024C Power and Ground Pi ns .......................................................................................... 10
Tabl e 7: 72S 8024C M i crocon trol ler I nterface Pins .................................................................................. 10
Tabl e 8: 73S 8024C D emo Board Bil l of Materials ................................................................................... 14
Tabl e 9: O r der N umbers and Packaging Mar ks ...................................................................................... 18
UM_8024C_061 7 3S8024C D emo Board User Manual
Rev. 1.3 5
1 Introduction
The 73S8024C Demo Board is a platform for evalu ati ng the Teridian 73S8024C Smart Card Interface
device. The board incorporates the 73S8 024C integrated circuit and has been d esigned to operate either
as a standalone platform (to be u sed in con jun ction with an exter nal microcontrol l er) or as a dau ghter
car d to be used in conjunction with the 73S1121F evaluation platform.
The board has been designed to compl y with the EMV 2000 Specification, Version 4.0. 73S8024C Demo
B oar ds can easily be modified to com ply with NDS sp ecifications by replacing a few external components
that are highlighted in this document.
Figure 1: 73S8024C Demo Board
1.1 Package Contents
The 73S8024C Demo Board Kit includes:
• A 73S8024C Demo Board
• The following documents on C D:
• 73S8024C Data Sheet
• 73S8024C Demo Board User Ma nual (this document)
• Application Note
1.2 Saf ety and E S D Not es
Extreme ca uti on should be take n w hen handli ng the 73S8024 C Demo B oard aft er
connecti on to live voltages!
The 73S8024C Demo Boar d i s ESD sensitive ! ESD precautions should be taken when
handl i ng this board!
73S 8024C Demo Board User Manual UM_8024C_061
6 Rev. 1.3
2 Basic Connections
The basic connections to the demo boar d are described below an d shown i n Figure 2.
1. Connect power supply: Apply 3.3 V to pin 10 of J4.
2. Control signals t o the device can b e connected through J 2 and J4 (see Figure 2 and the Electrical
Schematic, Figure 5).
3. To set the clock frequ ency with an external clock sou r ce:
• S et JP 1 to the SCL K set ting.
• A ppl y clock sour ce t o pi n 1 of J2.
• Apply 3. 3V (1 ) or G N D (0) to CLK DIV1 and CLKDIV2 pins to set t he desired clock rate as foll ows:
CLKDIV1 = CL KDIV2 = 0 clock frequency = SCL K/8
CLKDIV1 = 0, CLKDIV2 =1 clock frequency = SCLK /4
CLKDIV1 = 1, CLKDIV2 =0 clock frequency = SCLK
CLKDIV1 = CLKDIV2 = 1 clock frequency = S CLK/2
4. To set t he clock frequency using cryst al Y1 :
• The crystal included on the demo board i s 12 MHz.
• Set JP1 to XTAL position.
• Apply 3.3V (1) or GND (0) to CLKDIV1 and CLKDIV2 pins to se t the desired cl ock r ate as follows:
CLKDIV1 = C LKD IV2 = 0 clock frequency = 1 . 5 MHz
CLKDIV1 = 0, CLKDIV2 =1 clock frequency = 3 MHz
CLKDIV1 = 1, CLKDIV2 =0 clock frequency = 12 MHz
CLKDIV1 = CLKDIV2 = 1 clock frequency = 6 MHz
Figure 2: 73S8024C Demo Board Basic Connections
1
2
CKDIV2
CKDIV1
RSTIN
CMDVCC
GND
VDD
PWRDN
5V/#V
GND
SCLK
OFF
I/OUC
AUX1UC
AUX2UC
External clock source. JP1 must be in
position SCLK when using an
external clock. Otherwise, pin SCLK
can be left open.
V
PC
Power
Supply:
Configure JP2
to 3.3V
V
DD
Power Supply:
+2.7V to +3.6V
(3.3V Typ.) / 50mA
Note: CLKSTOP and CLKLEV
can be left NC if unused.
5V/#V too, for 5V cards only.
UM_8024C_061 7 3S8024C D emo Board User Manual
Rev. 1.3 7
3 Hardware Description
3.1 Demo Boar d C onn e cto r s, Ju mper s an d T est Poi nts
Table 1 describe s the 73S8024C Demo Boar d connectors, jum pers and test points. The Item # in Table 1
refers to Figure 3.
Table 1: 73S8024C Demo Board Connector, Jumper and Te st Points
Item
#
Schematic/
Silkscreen
Reference Name Function
Connectors:
1 J2 5V Board Supply /
Auxiliary Interface 73S8024C au xiliary interface (I/OUC, AUX1UC,
AUX2UC), external clock (SCLK) and interrupt (OFF)
pins. Th e external clock (SC LK) can be left open when
JP 1 is in position XTAL.
The 5V power supply is unused and must be left open
a nd JP2 must be inserte d i n po sition 3.3V.
9 J4 3.3V Board Power /
Digital Con trol
Signals
3.3V board power supply and the 73S8024C host
control signals RSTIN, CMDVCC, 5V/#V, P WRDWN,
CLKDIV2 and CLKDIV1.
16 J5 S mart Card
Connector Smart card connector.
When inse r ting a card (cred it card size format), co ntacts
must face up.
11 J6 S mart Card
Connector SIM/SA M smart ca r d format co nnector .
J6 i s wired in par al lel to t he smart ca r d conn ector J5
( unde r ne a t h the PC B) . No SIM/SAM sh o uld be inse r ted
when using the credit-card size con nector J5.
Jumpers:
3 JP1 Clock S election Ju mper to sel ect between a crystal or an ext er nal clock
as the frequen cy r eference to the d evice. The d efault
setting is for a crystal .
17 JP2 VPC Se l e ct Jumper to se l ect th e value of th e pow er supply for t he
smart car d D C-DC co nverter (73S8024C i np ut VPC) .
To sup por t bot h card voltag es, JP2 must be set to
position 3.3V. The default setting is 3.3V.
2 JP3 VDD Select Jumper t o select the di gi tal voltage whi ch suppl ies the
73S8024C. Must be set for 3.3V.
8 JP4 – Not used.
15
14 JP5
JP6 Car d Polar ity
Detect Select The setting of JP5 and JP6 depends on the type of
smart card connector use d (n ominally open or closed)
and which 73S8024C ca r d pr esence switch input is
used. The switch is nom inally open for the 73S8024C
Demo Board. The j umpers can be se t to:
1. Use of PRE S (default): JP5 set to PRES; JP6 set
to VDD.
2. Use of PRES: JP5 set to P RE B; JP6 set to GND .
73S 8024C Demo Board User Manual UM_8024C_061
8 Rev. 1.3
Item
#
Schematic/
Silkscreen
Reference Name Function
Test Points:
10 TP1 Pin 17 (VDDF_ADJ) V D D voltage fault adjustment. The pin to the left is
connected to the VDDF_ADJ pin of the 73S8024C and
t he pin to the right is G ND. When ei ther a resistor R 3,
or a resistor network R1 and R3 is populated on the
board, i t adjusts the VDD faul t l evel that in ternal l y
t r i ggers a ca r d deacti vation sequence .
B y defau lt, the res i stors R1 and R 3 ar e not co nnected.
This p rovides a VDD fau lt level of 2. 3V typical (int ern ally
set to t he 73S8024C). Refer t o the 73S8024C Data
Sheet for further information about V DD fault level and
deter mination of t he resistor values.
20 TP2 Factory Test F actory test pin. Do not co nnect.
7
12
6
13
5
4
TP3
TP4
TP5
TP6
TP7
TP8
VCC
I/O
RST
C8
CLK
C4
2-pin test poi nts for each respecti ve smart card signal.
The pin l abel name is the respective sign al (i.e. V C C,
CLK) and th e 2nd pin is GND.
Figure 3: 73S8024C Demo Boa r d Connectors, Jumpers and Test Points
UM_8024C_061 7 3S8024C D emo Board User Manual
Rev. 1.3 9
3.2 Recommended Operating Conditions and Absolute Maximum Ratings
Table 2 l ists the reco mmended operating co ndi tions and Table 3 li sts the abso l ute maximum ratings.
O perati on outsi de these r ating limits may cause permanent damage to th e device.
Table 2: Re comm ended Ope r ating Condi tions
Parameter Rating
S uppl y Voltag e VDD 2.7 to 3. 6 VDC
S uppl y Voltag e VPC 2.7 to 3.6 VD C
Ambient Operating Temperature -40 °C to +85 °C
I nput Voltage for Digi tal Input s 0 V to VDD + 0.3 V
Table 3: Absolute Maxim um Rati ngs
Parameter
Rating
S uppl y Voltag e VDD -0 .5 to 4. 0 VD C
S uppl y Voltag e VPC -0.5 t o 4. 0 V DC
I nput Voltage for Digi tal Input s -0.3 to (VDD+0.5) VDC
S torage Temperatu r e -60 °C to 1 50 °C
Pin Voltage -0.3 to (VDD+0.5) VDC
Pin Current ±100 mA
E SD Tolerance – C ar d i nterface pins +/- 6 kV
E SD Tolerance – Other pins +/- 2 kV
E SD testin g on C ar d pi ns is HBM co ndi tion, 3 pulses, each polari ty refe r enced to ground.
3.3 73S8024C Pi n Des cr ipti on
Table 4: 73S8024C C ard Interface P ins
Name
Pi n #
Description
I/O 11 Card I/O : D ata sign al to/from card. Includes a pul l -up resistor to VCC.
AUX1 13 AU X1: Auxiliary dat a signal to/from car d. In cludes a pu ll-u p r esistor to VCC.
AUX2 12 AU X2: Auxiliary dat a signal to/from car d. In cludes a pu ll-u p r esistor to VCC.
RST 14 Card reset: provides r eset (RST) si gnal to ca r d.
CLK 15 Card cl ock: pr ovides clock signal (CL K) to ca r d. Th e r ate of t hi s clock is
deter mined by cr ystal oscillat or frequency or exter nal clock i nput and
CLKDIV selections.
PRES 10 Card P r esence swi tch: active h ig h i ndi cat es card i s pr e sent. Sho uld be tie d
to GND when not used, but it includes a high-impedance pull-down r esistor .
PRES 9 Card Presence switch: active low in di cat es car d i s prese nt. Should be tie d
t o VDD when not used, but it include s a hi gh-impedance pull-up resistor.
VCC 17 Card power supply: logical l y co ntrol l ed by sequence r output of LDO
regulator. Requir es an external fil ter capaci tor to t he card GND.
GND 14 Card g r ound.
73S 8024C Demo Board User Manual UM_8024C_061
10 Rev. 1 .3
Table 5: 73S8024C Miscellaneous Pins
Name Pin # Description
XTALIN 24 C r ystal oscill ator i nput: can either be connected to cryst al or driven as a
source for th e card clock.
XTALOUT 25 C r ystal oscill ator outp ut: connected to crystal. Left open i f XTALIN is being
used as external clock input.
VDDF_ADJ 18 VDD fault thr eshold adj ust ment i nput: this pin can be used t o adj ust the VDDF
val ues (co ntrol s deactivation of the car d) . Must be left open if unused.
NC 5,7 Non-connected pin.
Table 6: 73S8024C Po wer and Ground Pins
Name
Pi n #
Description
VDD 21 System i nterface supply volt age and suppl y voltage for in ternal circuitry.
VPC 6 DC-DC converter power supply source.
GND 4 DC-DC converter ground.
GND 22 Digital g rou nd.
LIN 5 E xternal i nductor. Connect external in duct or from pi n 2 to VPC. Keep the
inductor close to pi n 2.
Table 7: 72S8024C Mi cr ocon tr o ll er In t erfac e P i ns
Name Pin # Description
CMDVCC
19
Command VC C ( negative assertion): Logic l ow on thi s pin ca uses the LDO
regulator to ramp the V CC supply to the ca r d and initiates a car d activat ion
sequence , if a card is pr esent.
5V/#V 3 5 volt / 3 volt card se lection: Log ic one selects 5 volts for V CC and card
interface, logic low selects 3 volt operation.
When the part is to be used with
a si ngl e card volt age, th is pin should be tied to either GND or VDD. However,
it includes a high impedance pull-up resistor to default this pin high
(se l ection of 5V card) wh en not co nnected.
PWRDN 8 Power Down control input. Active high. Wh en the Power Down mode i s set
high, all in ternal anal og functions are disab led to place th e 73S8024C in its
lowest p ower consumption mode. The P ower Down mode i s only allow ed
out of a card session (i.e. when CM D VC C = 1)
CLKDIV1
CLKDIV2
1
2 S ets the di vide ratio from the XTAL oscillator (or external clock input) to the
car d clock. Th ese pins incl ude pull-down resistors.
CLKDIV1
CLKDIV2
CLOCK RATE
0 0 XTALIN/8
0
1
XTALIN/4
1
1
XTALIN/2
1 0 XTALIN
OFF 23 Int er r upt signal to the pr ocessor. A ctive low - multi-function indicatin g fault
conditi ons and /or card presence. Open drain output configuration; includes
an int er nal 22 kΩ pull-up t o VDD.
RSTIN 20 Reset I nput: This sign al is the reset command to th e card.
I/OUC 26 Syste m controller data I/O to /from the card. Include s a pull-up resisto r to V DD.
AUX1UC 27 Syst em cont r oller auxili ary dat a I/O to/from th e card. In cludes a pul l -up
resistor to VDD.
AUX2UC 28 Syst em cont r oller auxili ary dat a I/O to/from th e card. In cludes a pul l -up
resistor to VDD.
UM_8024C_061 7 3S8024C D emo Board User Manual
Rev. 1.3 11
3.4 73S8024C Pinout
CLKDIV1
CLKDIV2
5V/#V
GND
VPC
PRES
PRES
I/O
AUX2
AUX1
GND
AUX2UC
AUX1UC
I/OUC
XTALIN
XTALOUT
OFF
VDD
RSTIN
CMDVCC
VCC
RST
CLK
NC
LIN
PWRDN
VDDF_ADJ
GND
73S8024C
1
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
19
20
28
27
26
25
24
23
22
21
Figure 4: 73S8024C SO28 Pinout (Top Vi ew)
73S 8024C Demo Board User Manual UM_8024C_061
12 Rev. 1 .3
4 Design Considerations
4.1 General Layout Rules
• Route the auxiliary sig nal s away fr om car d i nterface signals.
• Keep the CLK signal as short as possible and with few bends in the trace. Keep the route of the C LK
t r ace t o one l ayer (avo i d vias t o other plane). Keep the CLK trace a way from other trace s, especially
RST and VCC. Fil teri ng of t he CL K trace is allowed for noise pu r pose. U p to 30 pF to ground is
allow ed at the CLK pin of th e smart ca r d connector. In addi tion, th e zero ohm series resistor, R7, can
be replace d for additi onal fil teri ng (no mor e than 100 Ω).
• Keep the VCC trace as short as possible. Make the tr ace a minimum of 0 .5 mm thick. In addi tion,
keep the VCC away from ot her traces, especially RST and CLK.
• K eep the trace from L1 to pin 5 of t he IC as shor t as possible.
• Keep the RST trace away from the VC C and C LK trace s. Up to 30 pF to ground is al l ow ed for
filtering.
• Keep the 0.1 µF capacitor close to the V D D p in of the device and dir ectly t ake the other end to
ground.
• Keep the 0.1 µF capacitor close to the V PC pin of the device and dir ectly t ake the othe r end t o
ground.
• Keep the 3.3 µF (1.0 µF fo r N DS) capacitor close t o the VCC pin of the smar t ca r d connector and
directly take ot her end to ground.
4.2 Optimization for Compliance with EMV and NDS
The default configuration of th e demo board contains a 27 pF capacitor (C12) from the CLK pin of the
smart connector to ground and a 27 pF capaci tor ( C 13) from the RST p in of the smart conn ector to
ground. These capaci tors ser ve as filter s f or the C LK and RST signal s in the ca se of long traces or test
equipment p er turbations. The capacitor on CLK reduce s ringin g on the t r ace, r educes coupling to ot her
t r aces and slows down the edge of the C LK signal. The cap acitor on RST h el ps the p er turbation
specification in a noi sy environment. The filter ca pacitors can be useful in the EMV test environm ent and
have no eff ect on ND S testing.
C12 and C13 are r epresent ed on both the sc hematic and the BOM. Th ese ca pacitors ar e optional fi l ter
capacitors on the sm ar t ca r d l i nes CLK and RST, r especti vely for each ca r d i nterface. These capacitors
may be adj usted (value not to exceed 30 pF) or removed to opt imize per formance i n each specific
app lica tion ( PCB, ca r d clock frequency, compli ance with applicable standards etc).
The default V CC ca pacitor of 3 .3 µF is r equir ed to meet th e dynamic V CC (smart card supply) transien t
curr ent requir ement as specified in the EMV2000 versi on 4.0 specificat i on. For compli ance with N DS, a
smaller capaci tor of 1 µF is requi r ed to meet the activat ion di scharg e ti me specification.
UM_8024C_061 73S8024C Demo Board User Manual
Rev. 1.3 13
5 73S8024C Demo Board Sch ematics, PCB Layouts and Bill of Materials
5.1 Schematic
USR3
CLK
GND
JP6
1
2
3
PGND
5V C4
22pF
J4
TSM_110_01_L_SV
1
2
3
4
5
6
7
8
9
10
SC4
3.3V
R8
Ru
TP6
1
2
VDD
USR5
C4
VPC
R10
Ru
Resistors
not
populated
+
C10 10uF
3.3V
GND
C11
0.1uF
Connectors are positioned to allow
multiple 8024C boards (stacking) to a
73S1121F evaluation board. Also used for
connecting external signals when used as a
stand alone board.
JP4
HEAD ER LOC K 3
1
2
3
CLKDIV1
GND
USR2
+
C1 10uF
JP2 must be
set to 3.3V
Card detection
switches are
normally open
CARD DETECT
POLARITY SELECT
I/O
VDD
R11
Rd
SIO
L1
10uF
R2
0
R5 R7
0
R12
Rd
C8
GND
5.0V
TP7
1
2
JP2
1
2
3
R13
Rd
USR1
3.3V
C2 0.1uF
R6
OFFB
R4 0
C8
0.1uF
C1, C2, C8, C9 and L1 must be
placed within 5mm of the U1 pins
and connected by thick track
(wider than 0.5mm)
5V
S_C8
Resistors not
populated
U1
73S8024C
1
2
3
4
5
6
7
12
8
9
10
11
13
14 15
16
17
18
19
20
21
22
23
28
27
25
24
26
CLKDIV1
CLKDIV2
5V3V
GND_4
LIN
VPC
NC
AUX2
PWRDN
PRES
PRES
I/O
AUX1
GND_14 CLK
RST
VCC
VDDF_ADJ
CMDVCC
RSTIN
VDD
GND
OFF
AUX2UC
AUX1UC
XTALOUT
XTALIN
I/OUC
JP3 must be
set to 3.3V
J5 Smart C ard C onn ec t or
1
2
3
4
5
6
7
8
9
10
VCC
RST
CLK
C4
GND
VPP
I/O
C8
SW-1
SW-2
SIO
TP2
1
2
CLKDIV2
JP3
1
2
3
3.3V
J2
TSM_110_01_L_SV
1
2
3
4
5
6
7
8
9
10
+
C3 10uF
5.0V
TP8
1
2
SC8
5V3VB
3.3V
TP4
1
2
PIN18
Signal names
refer to
73S1121F
Evaluation
board.
GND
NC
USR6
JP5
1
2
3
VDD
C5
22pF
5V
XTALIN
SELECT
GND
PWRDN
USR4
J1
SSM_110_L_SV
1
2
3
4
5
6
7
8
9
10
SCLK
R9
Ru
TP1
1
2
SCLK
VDD
SELECT
Signal names
refer to
73S1121F
Evaluation
board.
VDD
CMDVCCB
TP5
1
2
XTAL
TP3 to TP8 to be placed
very close to the pads
of J5
R3
J6 SIM/SAM Co nnec t or
1
2
3
4
5
6
7
8
C1
C2
C3
C5
C6
C7
SW1
SW2
SCLK
+5V
TP3
1
2
RSTIN
L1 must be
placed close
to pin 5
VPC
SELECT
INT2
PRESB
S_C4
+5V
JP1
1
2
3
GND
PRES
J3
SSM_110_L_SV
1
2
3
4
5
6
7
8
9
10
VCC
C9
0.47uF
+3.3V
VDD
C13
27pF
R1
RST
Y1
12.000MHz
1 4
C12
27pF
5.0V
USR7
USR0
Figure 5: 73S8024C Dem o Board Electrical Schematic
73S 8024C Demo Board User Manual UM_8024C_061
14 Rev. 1 .3
5.2 Bill of Materials
Table 8 provides the bil l of m ateri als for the 7 3S8024C Demo Board schematic provided in Figure 5.
Table 8: 73S8024C Demo Board Bill of Materials
Item Quantity Reference Part PC B Footprint
Digikey Part
Number Part Number Manufacturer
1 3 C1,C3,C10 10 µF 805 PCC2225CT-ND ECJ-2FB0J106M Panasonic
2 2 C2,C8 0.1 µF 603 PCC1762CT-ND ECJ-1VB1C104K Panasonic
3 2 C4,C5 22 pF 603 PCC220ACVCT-ND ECJ-1VC1H220J Panasonic
4
1
C11
3.3 µF
805
PCC1925CT-ND
ECJ-2YB0J335K
Panasonic
5 2 C12, C13 27 pF 402 PCC270CQCT-ND ECJ-0EC1H270J Panasonic
6 1 L1 10 µH X SLF6025 TDK
7 5 JP1,JP2,JP3,JP5,
JP6 HEADER 3 3pin s, 2. 54 mm
pitch S1011-36-ND PZC36SAAN Sullins
8
1
JP4
Header Lock 3
3pins, 2. 54 mm
pitch
WM2701-ND
22-11-2032
Molex
9 2 J1,J3 SSM_110_L_SV SSM_110_L_SV X SSM_110_L_SV Samtec
10 2 J2,J4 TSM_110_01_L_SV TSM_110_01_L_SV X TSM_110_01_L_S
V Samtec
11 1 J5 S mart Card
Connector
ITT_CCM02-2504 ccm02-2504-ND ccm02-2504 ITTCannon
12 1 J6 S IM/SAM Connector ITT_CCM03-3754 CCM03-3754CT-ND
CCM03-3754 ITTCannon
13 3 R2,R4,R7 0 603 P0.0GCT-ND ERJ-3GEY0R00V Panasonic
14 2 R5,R6 X 603 X X
15 4 R1,R8,R9,R10 Ru 603 X X
16 4 R3,R11,R12,R13 Rd 603 X X
17 8 TP1,TP2,TP3,TP4,
TP5,TP6,TP7,TP8 TP2 2X1_Header S1011-36-ND PZC36SAAN Sullins
18 1 U1 73S8024C 28SOP X 73S8024C Teridian
Semiconductor
19
1
Y1
12.000 MHz
HC-49US
X190-ND
ECS-120-20-4DN
ECS
20 2 C4,C5 22 pF 603 PCC220ACVCT-ND ECJ-1VC1H220J Panasonic
1 Ru and Rd are not populated on the board. Th ey can be i mpl em ented to adjust the feat ur es of the smart ca r d reader .
UM_8024C_061 73S8024C Demo Board User Manual
Rev. 1.3 15
5.3 P CB Layouts
Figure 6: 73 S8024C De mo Board Top View
Figure 7: 73S8024C Dem o Board Bottom View
73S 8024C Demo Board User Manual UM_8024C_061
16 Rev. 1 .3
Figure 8: 73S8024C Demo Board Top Signal Lay er
Figure 9: 73S8024C Demo Board Middle Layer 1, Ground Pla ne
UM_8024C_061 73S8024C Demo Board User Manual
Rev. 1.3 17
Figure 10: 73S8024C Mid d l e L ay er 2, Su pp l y P lane
Figure 11: 73S8024C Demo Board Bottom Signal Layer
73S 8024C Demo Board User Manual UM_8024C_061
18 Rev. 1 .3
6 Ordering Information
Table 9 lists t he order number use d to ide nti f y the 73S8024C Demo Board.
Table 9: Order Numbers and Packaging Marks
Part Description Order Number
73 S8 02 4C 28-Pin SO Dem o Board 73S8024C-DB
7 Related Documentation
The following 73S8024C document s are ava ilable from Teridian Semi condu ctor C or poration:
73S8024C Data Sheet
73S8024C Demo Board User Manual (this document)
Teridian 73S8024C versus Philips TDA8024T Application Note
8 Contact Infor mation
For more information about Ter i di an Semi condu ctor products or to check t he avail ability of the
73S8024C, con tact u s at:
644 0 Oak Can yon Road
Suite 100
I r vine, CA 92618-5201
Telephone: (714) 508-8800
FAX : (71 4) 50 8-8878
Email: scr.support@teridian.com
For a complete li st of worldwide sales offices, go to http://www.teridian.com.
UM_8024C_061 73S8024C Demo Board User Manual
Rev. 1.3 19
Rev isi on Histor y
Revision Date Description
1.0 6/8/2004 First publicat ion.
1.1 8/2/2004 M i nor corrections.
1.2
8/23/2005
Added new logo.
1.3 11/11/2009 A dded Secti on 1.1, P ackage C ontents.
A dded Secti on 1.2, S afety and ESD N otes.
A dded Secti on 6, Ordering Information.
A dded Secti on 7, Related D ocumentation.
A dded Secti on 8, Contact Information.
Miscellaneous editori al changes.
